From: Luke Kenneth Casson Leighton Date: Wed, 2 Dec 2020 23:34:30 +0000 (+0000) Subject: add full core back in X-Git-Tag: ls180-24jan2020~14 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8db687c899fba7b607d1dc2a3a77bbd0459caf80;p=soclayout.git add full core back in --- diff --git a/experiments9/non_generated/full_core_ls180.il b/experiments9/non_generated/full_core_ls180.il index ab4601e..dfa10f3 100644 --- a/experiments9/non_generated/full_core_ls180.il +++ b/experiments9/non_generated/full_core_ls180.il @@ -1,1520 +1,89681 @@ # Generated by Yosys 0.9+3578 (git sha1 c6ff947f, clang 9.0.1-12 -fPIC -Os) -autoidx 3702 -attribute \src "libresoc.v:5.1-277.10" +autoidx 14623 +attribute \src "libresoc.v:5.1-330.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.jtag._fsm" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec19" attribute \generator "nMigen" -module \_fsm - attribute \src "libresoc.v:125.3-239.6" - wire width 4 $0\fsm_state$next[3:0]$25 - attribute \src "libresoc.v:91.3-92.35" - wire width 4 $0\fsm_state[3:0] +module \ALU_dec19 + attribute \src "libresoc.v:279.3-288.6" + wire width 3 $0\ALU_dec19_cr_in[2:0] + attribute \src "libresoc.v:289.3-298.6" + wire width 3 $0\ALU_dec19_cr_out[2:0] + attribute \src "libresoc.v:319.3-328.6" + wire width 2 $0\ALU_dec19_cry_in[1:0] + attribute \src "libresoc.v:219.3-228.6" + wire $0\ALU_dec19_cry_out[0:0] + attribute \src "libresoc.v:189.3-198.6" + wire width 12 $0\ALU_dec19_function_unit[11:0] + attribute \src "libresoc.v:259.3-268.6" + wire width 3 $0\ALU_dec19_in1_sel[2:0] + attribute \src "libresoc.v:269.3-278.6" + wire width 4 $0\ALU_dec19_in2_sel[3:0] + attribute \src "libresoc.v:249.3-258.6" + wire width 7 $0\ALU_dec19_internal_op[6:0] + attribute \src "libresoc.v:199.3-208.6" + wire $0\ALU_dec19_inv_a[0:0] + attribute \src "libresoc.v:209.3-218.6" + wire $0\ALU_dec19_inv_out[0:0] + attribute \src "libresoc.v:229.3-238.6" + wire $0\ALU_dec19_is_32b[0:0] + attribute \src "libresoc.v:299.3-308.6" + wire width 4 $0\ALU_dec19_ldst_len[3:0] + attribute \src "libresoc.v:309.3-318.6" + wire width 2 $0\ALU_dec19_rc_sel[1:0] + attribute \src "libresoc.v:239.3-248.6" + wire $0\ALU_dec19_sgn[0:0] attribute \src "libresoc.v:6.7-6.20" wire $0\initial[0:0] - attribute \src "libresoc.v:97.3-124.6" - wire $0\isdr$next[0:0]$21 - attribute \src "libresoc.v:93.3-94.25" - wire $0\isdr[0:0] - attribute \src "libresoc.v:240.3-267.6" - wire $0\isir$next[0:0]$38 - attribute \src "libresoc.v:95.3-96.25" - wire $0\isir[0:0] - attribute \src "libresoc.v:125.3-239.6" - wire width 4 $10\fsm_state$next[3:0]$35 - attribute \src "libresoc.v:125.3-239.6" - wire width 4 $11\fsm_state$next[3:0]$36 - attribute \src "libresoc.v:125.3-239.6" - wire width 4 $1\fsm_state$next[3:0]$26 - attribute \src "libresoc.v:46.13-46.29" - wire width 4 $1\fsm_state[3:0] - attribute \src "libresoc.v:97.3-124.6" - wire $1\isdr$next[0:0]$22 - attribute \src "libresoc.v:51.7-51.18" - wire $1\isdr[0:0] - attribute \src "libresoc.v:240.3-267.6" - wire $1\isir$next[0:0]$39 - attribute \src "libresoc.v:56.7-56.18" - wire $1\isir[0:0] - attribute \src "libresoc.v:125.3-239.6" - wire width 4 $2\fsm_state$next[3:0]$27 - attribute \src "libresoc.v:97.3-124.6" - wire $2\isdr$next[0:0]$23 - attribute \src "libresoc.v:240.3-267.6" - wire $2\isir$next[0:0]$40 - attribute \src "libresoc.v:125.3-239.6" - wire width 4 $3\fsm_state$next[3:0]$28 - attribute \src "libresoc.v:125.3-239.6" - wire width 4 $4\fsm_state$next[3:0]$29 - attribute \src "libresoc.v:125.3-239.6" - wire width 4 $5\fsm_state$next[3:0]$30 - attribute \src "libresoc.v:125.3-239.6" - wire width 4 $6\fsm_state$next[3:0]$31 - attribute \src "libresoc.v:125.3-239.6" - wire width 4 $7\fsm_state$next[3:0]$32 - attribute \src "libresoc.v:125.3-239.6" - wire width 4 $8\fsm_state$next[3:0]$33 - attribute \src "libresoc.v:125.3-239.6" - wire width 4 $9\fsm_state$next[3:0]$34 - attribute \src "libresoc.v:75.17-75.110" - wire $eq$libresoc.v:75$1_Y - attribute \src "libresoc.v:76.18-76.111" - wire $eq$libresoc.v:76$2_Y - attribute \src "libresoc.v:77.18-77.111" - wire $eq$libresoc.v:77$3_Y - attribute \src "libresoc.v:78.18-78.111" - wire $eq$libresoc.v:78$4_Y - attribute \src "libresoc.v:79.18-79.111" - wire $eq$libresoc.v:79$5_Y - attribute \src "libresoc.v:80.17-80.108" - wire $eq$libresoc.v:80$6_Y - attribute \src "libresoc.v:81.18-81.111" - wire $eq$libresoc.v:81$7_Y - attribute \src "libresoc.v:82.18-82.111" - wire $eq$libresoc.v:82$8_Y - attribute \src "libresoc.v:83.18-83.111" - wire $eq$libresoc.v:83$9_Y - attribute \src "libresoc.v:84.18-84.111" - wire $eq$libresoc.v:84$10_Y - attribute \src "libresoc.v:85.18-85.111" - wire $eq$libresoc.v:85$11_Y - attribute \src "libresoc.v:86.18-86.111" - wire $eq$libresoc.v:86$12_Y - attribute \src "libresoc.v:87.18-87.112" - wire $eq$libresoc.v:87$13_Y - attribute \src "libresoc.v:88.17-88.108" - wire $eq$libresoc.v:88$14_Y - attribute \src "libresoc.v:89.17-89.108" - wire $eq$libresoc.v:89$15_Y - attribute \src "libresoc.v:90.17-90.108" - wire $eq$libresoc.v:90$16_Y - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:113" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" - wire \$17 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" - wire \$21 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" - wire \$25 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" - wire \$29 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 9 \TAP_bus__tck - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 10 \TAP_bus__tms - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" - wire output 1 \capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" - wire width 4 \fsm_state - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" - wire width 4 \fsm_state$next + attribute \src "libresoc.v:279.3-288.6" + wire width 3 $1\ALU_dec19_cr_in[2:0] + attribute \src "libresoc.v:289.3-298.6" + wire width 3 $1\ALU_dec19_cr_out[2:0] + attribute \src "libresoc.v:319.3-328.6" + wire width 2 $1\ALU_dec19_cry_in[1:0] + attribute \src "libresoc.v:219.3-228.6" + wire $1\ALU_dec19_cry_out[0:0] + attribute \src "libresoc.v:189.3-198.6" + wire width 12 $1\ALU_dec19_function_unit[11:0] + attribute \src "libresoc.v:259.3-268.6" + wire width 3 $1\ALU_dec19_in1_sel[2:0] + attribute \src "libresoc.v:269.3-278.6" + wire width 4 $1\ALU_dec19_in2_sel[3:0] + attribute \src "libresoc.v:249.3-258.6" + wire width 7 $1\ALU_dec19_internal_op[6:0] + attribute \src "libresoc.v:199.3-208.6" + wire $1\ALU_dec19_inv_a[0:0] + attribute \src "libresoc.v:209.3-218.6" + wire $1\ALU_dec19_inv_out[0:0] + attribute \src "libresoc.v:229.3-238.6" + wire $1\ALU_dec19_is_32b[0:0] + attribute \src "libresoc.v:299.3-308.6" + wire width 4 $1\ALU_dec19_ldst_len[3:0] + attribute \src "libresoc.v:309.3-318.6" + wire width 2 $1\ALU_dec19_rc_sel[1:0] + attribute \src "libresoc.v:239.3-248.6" + wire $1\ALU_dec19_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \ALU_dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 6 \ALU_dec19_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 9 \ALU_dec19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 12 \ALU_dec19_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \ALU_dec19_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 3 \ALU_dec19_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 4 \ALU_dec19_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \ALU_dec19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 10 \ALU_dec19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 11 \ALU_dec19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 13 \ALU_dec19_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 7 \ALU_dec19_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \ALU_dec19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 14 \ALU_dec19_sgn attribute \src "libresoc.v:6.7-6.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" - wire output 11 \isdr - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" - wire \isdr$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" - wire output 4 \isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" - wire \isir$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:49" - wire \local_clk - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" - wire output 8 \negjtag_clk - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" - wire output 6 \negjtag_rst - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" - wire output 7 \posjtag_clk - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" - wire output 5 \posjtag_rst - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:36" - wire \rst - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" - wire output 2 \shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" - wire output 3 \update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" - cell $eq $eq$libresoc.v:75$1 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \TAP_bus__tms - connect \B 1'0 - connect \Y $eq$libresoc.v:75$1_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" - cell $eq $eq$libresoc.v:76$2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \TAP_bus__tms - connect \B 1'0 - connect \Y $eq$libresoc.v:76$2_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" - cell $eq $eq$libresoc.v:77$3 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \TAP_bus__tms - connect \B 1'0 - connect \Y $eq$libresoc.v:77$3_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" - cell $eq $eq$libresoc.v:78$4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \TAP_bus__tms - connect \B 1'1 - connect \Y $eq$libresoc.v:78$4_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" - cell $eq $eq$libresoc.v:79$5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \TAP_bus__tms - connect \B 1'0 - connect \Y $eq$libresoc.v:79$5_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:113" - cell $eq $eq$libresoc.v:80$6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fsm_state - connect \B 1'0 - connect \Y $eq$libresoc.v:80$6_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" - cell $eq $eq$libresoc.v:81$7 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \TAP_bus__tms - connect \B 1'0 - connect \Y $eq$libresoc.v:81$7_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" - cell $eq $eq$libresoc.v:82$8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \TAP_bus__tms - connect \B 1'0 - connect \Y $eq$libresoc.v:82$8_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" - cell $eq $eq$libresoc.v:83$9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \TAP_bus__tms - connect \B 1'1 - connect \Y $eq$libresoc.v:83$9_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" - cell $eq $eq$libresoc.v:84$10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \TAP_bus__tms - connect \B 1'0 - connect \Y $eq$libresoc.v:84$10_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" - cell $eq $eq$libresoc.v:85$11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \TAP_bus__tms - connect \B 1'1 - connect \Y $eq$libresoc.v:85$11_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" - cell $eq $eq$libresoc.v:86$12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \TAP_bus__tms - connect \B 1'0 - connect \Y $eq$libresoc.v:86$12_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" - cell $eq $eq$libresoc.v:87$13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \TAP_bus__tms - connect \B 1'0 - connect \Y $eq$libresoc.v:87$13_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" - cell $eq $eq$libresoc.v:88$14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \fsm_state - connect \B 2'11 - connect \Y $eq$libresoc.v:88$14_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" - cell $eq $eq$libresoc.v:89$15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \fsm_state - connect \B 3'101 - connect \Y $eq$libresoc.v:89$15_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" - cell $eq $eq$libresoc.v:90$16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \fsm_state - connect \B 4'1000 - connect \Y $eq$libresoc.v:90$16_Y - end - attribute \src "libresoc.v:125.3-239.6" - process $proc$libresoc.v:125$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 10 \opcode_switch + attribute \src "libresoc.v:189.3-198.6" + process $proc$libresoc.v:189$1 assign { } { } assign { } { } - assign $0\fsm_state$next[3:0]$25 $1\fsm_state$next[3:0]$26 - attribute \src "libresoc.v:126.5-126.29" + assign $0\ALU_dec19_function_unit[11:0] $1\ALU_dec19_function_unit[11:0] + attribute \src "libresoc.v:190.5-190.29" switch \initial - attribute \src "libresoc.v:126.9-126.17" + attribute \src "libresoc.v:190.9-190.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\fsm_state$next[3:0]$26 $2\fsm_state$next[3:0]$27 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" - switch \$13 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fsm_state$next[3:0]$27 4'0001 - case - assign $2\fsm_state$next[3:0]$27 \fsm_state - end - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\fsm_state$next[3:0]$26 $3\fsm_state$next[3:0]$28 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" - switch \$15 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fsm_state$next[3:0]$28 4'0010 - case - assign $3\fsm_state$next[3:0]$28 \fsm_state - end - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\fsm_state$next[3:0]$26 $4\fsm_state$next[3:0]$29 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" - switch \$17 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\fsm_state$next[3:0]$29 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $4\fsm_state$next[3:0]$29 4'0100 - end - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\fsm_state$next[3:0]$26 $5\fsm_state$next[3:0]$30 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" - switch \$19 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\fsm_state$next[3:0]$30 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $5\fsm_state$next[3:0]$30 4'0000 - end - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\fsm_state$next[3:0]$26 $6\fsm_state$next[3:0]$31 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" - switch \$21 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\fsm_state$next[3:0]$31 4'0101 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $6\fsm_state$next[3:0]$31 4'0110 - end - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\fsm_state$next[3:0]$26 $7\fsm_state$next[3:0]$32 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" - switch \$23 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $7\fsm_state$next[3:0]$32 4'0110 - case - assign $7\fsm_state$next[3:0]$32 \fsm_state - end - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\fsm_state$next[3:0]$26 $8\fsm_state$next[3:0]$33 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" - switch \$25 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $8\fsm_state$next[3:0]$33 4'0111 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $8\fsm_state$next[3:0]$33 4'1000 - end - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\fsm_state$next[3:0]$26 $9\fsm_state$next[3:0]$34 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" - switch \$27 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $9\fsm_state$next[3:0]$34 4'1001 - case - assign $9\fsm_state$next[3:0]$34 \fsm_state - end - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\fsm_state$next[3:0]$26 $10\fsm_state$next[3:0]$35 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" - switch \$29 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $10\fsm_state$next[3:0]$35 4'0101 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $10\fsm_state$next[3:0]$35 4'1000 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'1000 + case 10'0010010110 assign { } { } - assign $1\fsm_state$next[3:0]$26 $11\fsm_state$next[3:0]$36 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" - switch \$31 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $11\fsm_state$next[3:0]$36 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $11\fsm_state$next[3:0]$36 4'0010 - end + assign $1\ALU_dec19_function_unit[11:0] 12'000000000010 case - assign $1\fsm_state$next[3:0]$26 \fsm_state + assign $1\ALU_dec19_function_unit[11:0] 12'000000000000 end sync always - update \fsm_state$next $0\fsm_state$next[3:0]$25 + update \ALU_dec19_function_unit $0\ALU_dec19_function_unit[11:0] end - attribute \src "libresoc.v:240.3-267.6" - process $proc$libresoc.v:240$37 + attribute \src "libresoc.v:199.3-208.6" + process $proc$libresoc.v:199$2 assign { } { } assign { } { } - assign $0\isir$next[0:0]$38 $1\isir$next[0:0]$39 - attribute \src "libresoc.v:241.5-241.29" + assign $0\ALU_dec19_inv_a[0:0] $1\ALU_dec19_inv_a[0:0] + attribute \src "libresoc.v:200.5-200.29" switch \initial - attribute \src "libresoc.v:241.9-241.17" + attribute \src "libresoc.v:200.9-200.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\isir$next[0:0]$39 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\isir$next[0:0]$39 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\isir$next[0:0]$39 $2\isir$next[0:0]$40 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" - switch \$9 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\isir$next[0:0]$40 1'1 - case - assign $2\isir$next[0:0]$40 \isir - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'1000 + case 10'0010010110 assign { } { } - assign $1\isir$next[0:0]$39 1'0 + assign $1\ALU_dec19_inv_a[0:0] 1'0 case - assign $1\isir$next[0:0]$39 \isir + assign $1\ALU_dec19_inv_a[0:0] 1'0 end sync always - update \isir$next $0\isir$next[0:0]$38 + update \ALU_dec19_inv_a $0\ALU_dec19_inv_a[0:0] end - attribute \src "libresoc.v:46.13-46.29" - process $proc$libresoc.v:46$42 + attribute \src "libresoc.v:209.3-218.6" + process $proc$libresoc.v:209$3 assign { } { } - assign $1\fsm_state[3:0] 4'0000 - sync always - sync init - update \fsm_state $1\fsm_state[3:0] - end - attribute \src "libresoc.v:51.7-51.18" - process $proc$libresoc.v:51$43 assign { } { } - assign $1\isdr[0:0] 1'0 + assign $0\ALU_dec19_inv_out[0:0] $1\ALU_dec19_inv_out[0:0] + attribute \src "libresoc.v:210.5-210.29" + switch \initial + attribute \src "libresoc.v:210.9-210.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_inv_out[0:0] 1'0 + case + assign $1\ALU_dec19_inv_out[0:0] 1'0 + end sync always - sync init - update \isdr $1\isdr[0:0] + update \ALU_dec19_inv_out $0\ALU_dec19_inv_out[0:0] end - attribute \src "libresoc.v:56.7-56.18" - process $proc$libresoc.v:56$44 + attribute \src "libresoc.v:219.3-228.6" + process $proc$libresoc.v:219$4 assign { } { } - assign $1\isir[0:0] 1'0 - sync always - sync init - update \isir $1\isir[0:0] - end - attribute \src "libresoc.v:6.7-6.20" - process $proc$libresoc.v:6$41 assign { } { } - assign $0\initial[0:0] 1'0 + assign $0\ALU_dec19_cry_out[0:0] $1\ALU_dec19_cry_out[0:0] + attribute \src "libresoc.v:220.5-220.29" + switch \initial + attribute \src "libresoc.v:220.9-220.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_cry_out[0:0] 1'0 + case + assign $1\ALU_dec19_cry_out[0:0] 1'0 + end sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:91.3-92.35" - process $proc$libresoc.v:91$17 - assign { } { } - assign $0\fsm_state[3:0] \fsm_state$next - sync posedge \local_clk - update \fsm_state $0\fsm_state[3:0] - end - attribute \src "libresoc.v:93.3-94.25" - process $proc$libresoc.v:93$18 - assign { } { } - assign $0\isdr[0:0] \isdr$next - sync posedge \local_clk - update \isdr $0\isdr[0:0] - end - attribute \src "libresoc.v:95.3-96.25" - process $proc$libresoc.v:95$19 - assign { } { } - assign $0\isir[0:0] \isir$next - sync posedge \local_clk - update \isir $0\isir[0:0] + update \ALU_dec19_cry_out $0\ALU_dec19_cry_out[0:0] end - attribute \src "libresoc.v:97.3-124.6" - process $proc$libresoc.v:97$20 + attribute \src "libresoc.v:229.3-238.6" + process $proc$libresoc.v:229$5 assign { } { } assign { } { } - assign $0\isdr$next[0:0]$21 $1\isdr$next[0:0]$22 - attribute \src "libresoc.v:98.5-98.29" + assign $0\ALU_dec19_is_32b[0:0] $1\ALU_dec19_is_32b[0:0] + attribute \src "libresoc.v:230.5-230.29" switch \initial - attribute \src "libresoc.v:98.9-98.17" + attribute \src "libresoc.v:230.9-230.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\isdr$next[0:0]$22 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\isdr$next[0:0]$22 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\isdr$next[0:0]$22 $2\isdr$next[0:0]$23 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" - switch \$11 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\isdr$next[0:0]$23 1'1 - case - assign $2\isdr$next[0:0]$23 \isdr - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'1000 + case 10'0010010110 assign { } { } - assign $1\isdr$next[0:0]$22 1'0 - case - assign $1\isdr$next[0:0]$22 \isdr - end - sync always - update \isdr$next $0\isdr$next[0:0]$21 - end - connect \$9 $eq$libresoc.v:75$1_Y - connect \$11 $eq$libresoc.v:76$2_Y - connect \$13 $eq$libresoc.v:77$3_Y - connect \$15 $eq$libresoc.v:78$4_Y - connect \$17 $eq$libresoc.v:79$5_Y - connect \$1 $eq$libresoc.v:80$6_Y - connect \$19 $eq$libresoc.v:81$7_Y - connect \$21 $eq$libresoc.v:82$8_Y - connect \$23 $eq$libresoc.v:83$9_Y - connect \$25 $eq$libresoc.v:84$10_Y - connect \$27 $eq$libresoc.v:85$11_Y - connect \$29 $eq$libresoc.v:86$12_Y - connect \$31 $eq$libresoc.v:87$13_Y - connect \$3 $eq$libresoc.v:88$14_Y - connect \$5 $eq$libresoc.v:89$15_Y - connect \$7 $eq$libresoc.v:90$16_Y - connect \update \$7 - connect \shift \$5 - connect \capture \$3 - connect \rst \$1 - connect \local_clk \TAP_bus__tck - connect \negjtag_rst \rst - connect \negjtag_clk \TAP_bus__tck - connect \posjtag_rst \rst - connect \posjtag_clk \TAP_bus__tck -end -attribute \src "libresoc.v:281.1-353.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.jtag._idblock" -attribute \generator "nMigen" -module \_idblock - attribute \src "libresoc.v:326.3-346.6" - wire width 32 $0\TAP_id_sr$next[31:0]$50 - attribute \src "libresoc.v:324.3-325.35" - wire width 32 $0\TAP_id_sr[31:0] - attribute \src "libresoc.v:282.7-282.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:326.3-346.6" - wire width 32 $1\TAP_id_sr$next[31:0]$51 - attribute \src "libresoc.v:292.14-292.31" - wire width 32 $1\TAP_id_sr[31:0] - attribute \src "libresoc.v:326.3-346.6" - wire width 32 $2\TAP_id_sr$next[31:0]$52 - attribute \src "libresoc.v:321.17-321.110" - wire $and$libresoc.v:321$45_Y - attribute \src "libresoc.v:322.17-322.108" - wire $and$libresoc.v:322$46_Y - attribute \src "libresoc.v:323.17-323.109" - wire $and$libresoc.v:323$47_Y - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 5 \TAP_bus__tdi - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:236" - wire width 32 \TAP_id_sr - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:236" - wire width 32 \TAP_id_sr$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:225" - wire output 6 \TAP_id_tdo - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:243" - wire \_bypass - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:240" - wire \_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:241" - wire \_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:239" - wire \_tdi - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:242" - wire \_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" - wire input 2 \capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375" - wire input 1 \id_bypass - attribute \src "libresoc.v:282.7-282.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" - wire input 8 \posjtag_clk - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" - wire input 7 \posjtag_rst - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" - wire input 9 \select_id - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" - wire input 3 \shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" - wire input 4 \update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" - cell $and $and$libresoc.v:321$45 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \select_id - connect \B \capture - connect \Y $and$libresoc.v:321$45_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" - cell $and $and$libresoc.v:322$46 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \select_id - connect \B \shift - connect \Y $and$libresoc.v:322$46_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" - cell $and $and$libresoc.v:323$47 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \select_id - connect \B \update - connect \Y $and$libresoc.v:323$47_Y - end - attribute \src "libresoc.v:282.7-282.20" - process $proc$libresoc.v:282$53 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:292.14-292.31" - process $proc$libresoc.v:292$54 - assign { } { } - assign $1\TAP_id_sr[31:0] 0 + assign $1\ALU_dec19_is_32b[0:0] 1'0 + case + assign $1\ALU_dec19_is_32b[0:0] 1'0 + end sync always - sync init - update \TAP_id_sr $1\TAP_id_sr[31:0] - end - attribute \src "libresoc.v:324.3-325.35" - process $proc$libresoc.v:324$48 - assign { } { } - assign $0\TAP_id_sr[31:0] \TAP_id_sr$next - sync posedge \posjtag_clk - update \TAP_id_sr $0\TAP_id_sr[31:0] + update \ALU_dec19_is_32b $0\ALU_dec19_is_32b[0:0] end - attribute \src "libresoc.v:326.3-346.6" - process $proc$libresoc.v:326$49 + attribute \src "libresoc.v:239.3-248.6" + process $proc$libresoc.v:239$6 assign { } { } assign { } { } - assign $0\TAP_id_sr$next[31:0]$50 $1\TAP_id_sr$next[31:0]$51 - attribute \src "libresoc.v:327.5-327.29" + assign $0\ALU_dec19_sgn[0:0] $1\ALU_dec19_sgn[0:0] + attribute \src "libresoc.v:240.5-240.29" switch \initial - attribute \src "libresoc.v:327.9-327.17" + attribute \src "libresoc.v:240.9-240.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:254" - switch { \_shift \_capture } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\TAP_id_sr$next[31:0]$51 6399 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 10'0010010110 assign { } { } - assign $1\TAP_id_sr$next[31:0]$51 $2\TAP_id_sr$next[31:0]$52 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:257" - switch \_bypass - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\TAP_id_sr$next[31:0]$52 [31:1] \TAP_id_sr [31:1] - assign $2\TAP_id_sr$next[31:0]$52 [0] \_tdi - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\TAP_id_sr$next[31:0]$52 { \_tdi \TAP_id_sr [31:1] } - end + assign $1\ALU_dec19_sgn[0:0] 1'0 case - assign $1\TAP_id_sr$next[31:0]$51 \TAP_id_sr + assign $1\ALU_dec19_sgn[0:0] 1'0 end sync always - update \TAP_id_sr$next $0\TAP_id_sr$next[31:0]$50 - end - connect \$1 $and$libresoc.v:321$45_Y - connect \$3 $and$libresoc.v:322$46_Y - connect \$5 $and$libresoc.v:323$47_Y - connect \TAP_id_tdo \TAP_id_sr [0] - connect \_bypass \id_bypass - connect \_update \$5 - connect \_shift \$3 - connect \_capture \$1 - connect \_tdi \TAP_bus__tdi -end -attribute \src "libresoc.v:357.1-441.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.jtag._irblock" -attribute \generator "nMigen" -module \_irblock - attribute \src "libresoc.v:358.7-358.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:419.3-439.6" - wire width 4 $0\ir$next[3:0]$67 - attribute \src "libresoc.v:402.3-403.21" - wire width 4 $0\ir[3:0] - attribute \src "libresoc.v:406.3-418.6" - wire width 4 $0\shift_ir$next[3:0]$64 - attribute \src "libresoc.v:404.3-405.33" - wire width 4 $0\shift_ir[3:0] - attribute \src "libresoc.v:419.3-439.6" - wire width 4 $1\ir$next[3:0]$68 - attribute \src "libresoc.v:377.13-377.22" - wire width 4 $1\ir[3:0] - attribute \src "libresoc.v:406.3-418.6" - wire width 4 $1\shift_ir$next[3:0]$65 - attribute \src "libresoc.v:389.13-389.28" - wire width 4 $1\shift_ir[3:0] - attribute \src "libresoc.v:419.3-439.6" - wire width 4 $2\ir$next[3:0]$69 - attribute \src "libresoc.v:396.17-396.103" - wire $and$libresoc.v:396$55_Y - attribute \src "libresoc.v:397.18-397.105" - wire $and$libresoc.v:397$56_Y - attribute \src "libresoc.v:398.17-398.105" - wire $and$libresoc.v:398$57_Y - attribute \src "libresoc.v:399.17-399.103" - wire $and$libresoc.v:399$58_Y - attribute \src "libresoc.v:400.17-400.104" - wire $and$libresoc.v:400$59_Y - attribute \src "libresoc.v:401.17-401.105" - wire $and$libresoc.v:401$60_Y - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 4 \TAP_bus__tdi - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" - wire input 1 \capture - attribute \src "libresoc.v:358.7-358.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" - wire width 4 output 9 \ir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" - wire width 4 \ir$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" - wire input 5 \isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" - wire input 8 \posjtag_clk - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" - wire input 7 \posjtag_rst - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" - wire input 2 \shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:138" - wire width 4 \shift_ir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:138" - wire width 4 \shift_ir$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" - wire output 6 \tdo - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" - wire input 3 \update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" - cell $and $and$libresoc.v:396$55 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \isir - connect \B \shift - connect \Y $and$libresoc.v:396$55_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" - cell $and $and$libresoc.v:397$56 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \isir - connect \B \update - connect \Y $and$libresoc.v:397$56_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" - cell $and $and$libresoc.v:398$57 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \isir - connect \B \capture - connect \Y $and$libresoc.v:398$57_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" - cell $and $and$libresoc.v:399$58 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \isir - connect \B \shift - connect \Y $and$libresoc.v:399$58_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" - cell $and $and$libresoc.v:400$59 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \isir - connect \B \update - connect \Y $and$libresoc.v:400$59_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" - cell $and $and$libresoc.v:401$60 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \isir - connect \B \capture - connect \Y $and$libresoc.v:401$60_Y + update \ALU_dec19_sgn $0\ALU_dec19_sgn[0:0] end - attribute \src "libresoc.v:358.7-358.20" - process $proc$libresoc.v:358$70 + attribute \src "libresoc.v:249.3-258.6" + process $proc$libresoc.v:249$7 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:377.13-377.22" - process $proc$libresoc.v:377$71 assign { } { } - assign $1\ir[3:0] 4'0001 + assign $0\ALU_dec19_internal_op[6:0] $1\ALU_dec19_internal_op[6:0] + attribute \src "libresoc.v:250.5-250.29" + switch \initial + attribute \src "libresoc.v:250.9-250.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_internal_op[6:0] 7'0100100 + case + assign $1\ALU_dec19_internal_op[6:0] 7'0000000 + end sync always - sync init - update \ir $1\ir[3:0] + update \ALU_dec19_internal_op $0\ALU_dec19_internal_op[6:0] end - attribute \src "libresoc.v:389.13-389.28" - process $proc$libresoc.v:389$72 + attribute \src "libresoc.v:259.3-268.6" + process $proc$libresoc.v:259$8 assign { } { } - assign $1\shift_ir[3:0] 4'0000 + assign { } { } + assign $0\ALU_dec19_in1_sel[2:0] $1\ALU_dec19_in1_sel[2:0] + attribute \src "libresoc.v:260.5-260.29" + switch \initial + attribute \src "libresoc.v:260.9-260.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_in1_sel[2:0] 3'000 + case + assign $1\ALU_dec19_in1_sel[2:0] 3'000 + end sync always - sync init - update \shift_ir $1\shift_ir[3:0] + update \ALU_dec19_in1_sel $0\ALU_dec19_in1_sel[2:0] end - attribute \src "libresoc.v:402.3-403.21" - process $proc$libresoc.v:402$61 + attribute \src "libresoc.v:269.3-278.6" + process $proc$libresoc.v:269$9 assign { } { } - assign $0\ir[3:0] \ir$next - sync posedge \posjtag_clk - update \ir $0\ir[3:0] - end - attribute \src "libresoc.v:404.3-405.33" - process $proc$libresoc.v:404$62 assign { } { } - assign $0\shift_ir[3:0] \shift_ir$next - sync posedge \posjtag_clk - update \shift_ir $0\shift_ir[3:0] + assign $0\ALU_dec19_in2_sel[3:0] $1\ALU_dec19_in2_sel[3:0] + attribute \src "libresoc.v:270.5-270.29" + switch \initial + attribute \src "libresoc.v:270.9-270.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_in2_sel[3:0] 4'0000 + case + assign $1\ALU_dec19_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_dec19_in2_sel $0\ALU_dec19_in2_sel[3:0] end - attribute \src "libresoc.v:406.3-418.6" - process $proc$libresoc.v:406$63 + attribute \src "libresoc.v:279.3-288.6" + process $proc$libresoc.v:279$10 assign { } { } assign { } { } - assign $0\shift_ir$next[3:0]$64 $1\shift_ir$next[3:0]$65 - attribute \src "libresoc.v:407.5-407.29" + assign $0\ALU_dec19_cr_in[2:0] $1\ALU_dec19_cr_in[2:0] + attribute \src "libresoc.v:280.5-280.29" switch \initial - attribute \src "libresoc.v:407.9-407.17" + attribute \src "libresoc.v:280.9-280.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:141" - switch { \$5 \$3 \$1 } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $1\shift_ir$next[3:0]$65 \ir + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 3'-1- + case 10'0010010110 assign { } { } - assign $1\shift_ir$next[3:0]$65 { \TAP_bus__tdi \shift_ir [3:1] } + assign $1\ALU_dec19_cr_in[2:0] 3'000 case - assign $1\shift_ir$next[3:0]$65 \shift_ir + assign $1\ALU_dec19_cr_in[2:0] 3'000 end sync always - update \shift_ir$next $0\shift_ir$next[3:0]$64 + update \ALU_dec19_cr_in $0\ALU_dec19_cr_in[2:0] end - attribute \src "libresoc.v:419.3-439.6" - process $proc$libresoc.v:419$66 + attribute \src "libresoc.v:289.3-298.6" + process $proc$libresoc.v:289$11 assign { } { } assign { } { } - assign { } { } - assign $0\ir$next[3:0]$67 $2\ir$next[3:0]$69 - attribute \src "libresoc.v:420.5-420.29" + assign $0\ALU_dec19_cr_out[2:0] $1\ALU_dec19_cr_out[2:0] + attribute \src "libresoc.v:290.5-290.29" switch \initial - attribute \src "libresoc.v:420.9-420.17" + attribute \src "libresoc.v:290.9-290.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:141" - switch { \$11 \$9 \$7 } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign $1\ir$next[3:0]$68 \ir - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign $1\ir$next[3:0]$68 \ir + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 3'1-- + case 10'0010010110 assign { } { } - assign $1\ir$next[3:0]$68 \shift_ir + assign $1\ALU_dec19_cr_out[2:0] 3'000 case - assign $1\ir$next[3:0]$68 \ir + assign $1\ALU_dec19_cr_out[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \posjtag_rst - attribute \src "libresoc.v:0.0-0.0" + sync always + update \ALU_dec19_cr_out $0\ALU_dec19_cr_out[2:0] + end + attribute \src "libresoc.v:299.3-308.6" + process $proc$libresoc.v:299$12 + assign { } { } + assign { } { } + assign $0\ALU_dec19_ldst_len[3:0] $1\ALU_dec19_ldst_len[3:0] + attribute \src "libresoc.v:300.5-300.29" + switch \initial + attribute \src "libresoc.v:300.9-300.17" case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 assign { } { } - assign $2\ir$next[3:0]$69 4'0001 + assign $1\ALU_dec19_ldst_len[3:0] 4'0000 case - assign $2\ir$next[3:0]$69 $1\ir$next[3:0]$68 + assign $1\ALU_dec19_ldst_len[3:0] 4'0000 end sync always - update \ir$next $0\ir$next[3:0]$67 - end - connect \$9 $and$libresoc.v:396$55_Y - connect \$11 $and$libresoc.v:397$56_Y - connect \$1 $and$libresoc.v:398$57_Y - connect \$3 $and$libresoc.v:399$58_Y - connect \$5 $and$libresoc.v:400$59_Y - connect \$7 $and$libresoc.v:401$60_Y - connect \tdo \ir [0] -end -attribute \src "libresoc.v:445.1-469.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core" -attribute \generator "nMigen" -module \core - attribute \src "libresoc.v:446.7-446.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:460.3-468.6" - wire $0\x$next[0:0]$76 - attribute \src "libresoc.v:458.3-459.19" - wire $0\x[0:0] - attribute \src "libresoc.v:460.3-468.6" - wire $1\x$next[0:0]$77 - attribute \src "libresoc.v:454.7-454.15" - wire $1\x[0:0] - attribute \src "libresoc.v:457.17-457.89" - wire $not$libresoc.v:457$73_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:126" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" - wire input 2 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" - wire input 1 \coresync_rst - attribute \src "libresoc.v:446.7-446.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:125" - wire \x - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:125" - wire \x$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:126" - cell $not $not$libresoc.v:457$73 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x - connect \Y $not$libresoc.v:457$73_Y + update \ALU_dec19_ldst_len $0\ALU_dec19_ldst_len[3:0] end - attribute \src "libresoc.v:446.7-446.20" - process $proc$libresoc.v:446$78 + attribute \src "libresoc.v:309.3-318.6" + process $proc$libresoc.v:309$13 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:454.7-454.15" - process $proc$libresoc.v:454$79 assign { } { } - assign $1\x[0:0] 1'0 + assign $0\ALU_dec19_rc_sel[1:0] $1\ALU_dec19_rc_sel[1:0] + attribute \src "libresoc.v:310.5-310.29" + switch \initial + attribute \src "libresoc.v:310.9-310.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_rc_sel[1:0] 2'00 + case + assign $1\ALU_dec19_rc_sel[1:0] 2'00 + end sync always - sync init - update \x $1\x[0:0] - end - attribute \src "libresoc.v:458.3-459.19" - process $proc$libresoc.v:458$74 - assign { } { } - assign $0\x[0:0] \x$next - sync posedge \coresync_clk - update \x $0\x[0:0] + update \ALU_dec19_rc_sel $0\ALU_dec19_rc_sel[1:0] end - attribute \src "libresoc.v:460.3-468.6" - process $proc$libresoc.v:460$75 + attribute \src "libresoc.v:319.3-328.6" + process $proc$libresoc.v:319$14 assign { } { } assign { } { } - assign $0\x$next[0:0]$76 $1\x$next[0:0]$77 - attribute \src "libresoc.v:461.5-461.29" + assign $0\ALU_dec19_cry_in[1:0] $1\ALU_dec19_cry_in[1:0] + attribute \src "libresoc.v:320.5-320.29" switch \initial - attribute \src "libresoc.v:461.9-461.17" + attribute \src "libresoc.v:320.9-320.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'0010010110 assign { } { } - assign $1\x$next[0:0]$77 1'0 + assign $1\ALU_dec19_cry_in[1:0] 2'00 case - assign $1\x$next[0:0]$77 \$1 + assign $1\ALU_dec19_cry_in[1:0] 2'00 end sync always - update \x$next $0\x$next[0:0]$76 + update \ALU_dec19_cry_in $0\ALU_dec19_cry_in[1:0] + end + attribute \src "libresoc.v:6.7-6.20" + process $proc$libresoc.v:6$15 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - connect \$1 $not$libresoc.v:457$73_Y + connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:473.1-1187.10" +attribute \src "libresoc.v:334.1-1750.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dbg" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31" attribute \generator "nMigen" -module \dbg - attribute \src "libresoc.v:1003.3-1012.6" - wire $0\d_cr_req[0:0] - attribute \src "libresoc.v:810.3-819.6" - wire $0\d_gpr_req[0:0] - attribute \src "libresoc.v:1013.3-1022.6" - wire $0\d_xer_req[0:0] - attribute \src "libresoc.v:792.3-809.6" - wire $0\dmi_ack_o[0:0] - attribute \src "libresoc.v:1023.3-1053.6" - wire width 64 $0\dmi_dout[63:0] - attribute \src "libresoc.v:994.3-1002.6" - wire $0\dmi_read_log_data$next[0:0]$193 - attribute \src "libresoc.v:770.3-771.51" - wire $0\dmi_read_log_data[0:0] - attribute \src "libresoc.v:985.3-993.6" - wire $0\dmi_read_log_data_1$next[0:0]$190 - attribute \src "libresoc.v:772.3-773.55" - wire $0\dmi_read_log_data_1[0:0] - attribute \src "libresoc.v:820.3-828.6" - wire $0\dmi_req_i_1$next[0:0]$156 - attribute \src "libresoc.v:782.3-783.39" - wire $0\dmi_req_i_1[0:0] - attribute \src "libresoc.v:1144.3-1177.6" - wire $0\do_dmi_log_rd$next[0:0]$220 - attribute \src "libresoc.v:784.3-785.43" - wire $0\do_dmi_log_rd[0:0] - attribute \src "libresoc.v:1114.3-1143.6" - wire $0\do_icreset$next[0:0]$213 - attribute \src "libresoc.v:786.3-787.37" - wire $0\do_icreset[0:0] - attribute \src "libresoc.v:1084.3-1113.6" - wire $0\do_reset$next[0:0]$206 - attribute \src "libresoc.v:788.3-789.33" - wire $0\do_reset[0:0] - attribute \src "libresoc.v:1054.3-1083.6" - wire $0\do_step$next[0:0]$199 - attribute \src "libresoc.v:790.3-791.31" - wire $0\do_step[0:0] - attribute \src "libresoc.v:923.3-950.6" - wire width 7 $0\gspr_index$next[6:0]$178 - attribute \src "libresoc.v:776.3-777.37" - wire width 7 $0\gspr_index[6:0] - attribute \src "libresoc.v:474.7-474.20" +module \ALU_dec31 + attribute \src "libresoc.v:1457.3-1478.6" + wire width 3 $0\ALU_dec31_cr_in[2:0] + attribute \src "libresoc.v:1479.3-1500.6" + wire width 3 $0\ALU_dec31_cr_out[2:0] + attribute \src "libresoc.v:1545.3-1566.6" + wire width 2 $0\ALU_dec31_cry_in[1:0] + attribute \src "libresoc.v:1611.3-1632.6" + wire $0\ALU_dec31_cry_out[0:0] + attribute \src "libresoc.v:1677.3-1698.6" + wire width 12 $0\ALU_dec31_function_unit[11:0] + attribute \src "libresoc.v:1721.3-1742.6" + wire width 3 $0\ALU_dec31_in1_sel[2:0] + attribute \src "libresoc.v:1435.3-1456.6" + wire width 4 $0\ALU_dec31_in2_sel[3:0] + attribute \src "libresoc.v:1699.3-1720.6" + wire width 7 $0\ALU_dec31_internal_op[6:0] + attribute \src "libresoc.v:1567.3-1588.6" + wire $0\ALU_dec31_inv_a[0:0] + attribute \src "libresoc.v:1589.3-1610.6" + wire $0\ALU_dec31_inv_out[0:0] + attribute \src "libresoc.v:1633.3-1654.6" + wire $0\ALU_dec31_is_32b[0:0] + attribute \src "libresoc.v:1501.3-1522.6" + wire width 4 $0\ALU_dec31_ldst_len[3:0] + attribute \src "libresoc.v:1523.3-1544.6" + wire width 2 $0\ALU_dec31_rc_sel[1:0] + attribute \src "libresoc.v:1655.3-1676.6" + wire $0\ALU_dec31_sgn[0:0] + attribute \src "libresoc.v:335.7-335.20" wire $0\initial[0:0] - attribute \src "libresoc.v:951.3-984.6" - wire width 32 $0\log_dmi_addr$next[31:0]$184 - attribute \src "libresoc.v:774.3-775.41" - wire width 32 $0\log_dmi_addr[31:0] - attribute \src "libresoc.v:879.3-922.6" - wire $0\stopping$next[0:0]$169 - attribute \src "libresoc.v:778.3-779.33" - wire $0\stopping[0:0] - attribute \src "libresoc.v:829.3-878.6" - wire $0\terminated$next[0:0]$159 - attribute \src "libresoc.v:780.3-781.37" - wire $0\terminated[0:0] - attribute \src "libresoc.v:1003.3-1012.6" - wire $1\d_cr_req[0:0] - attribute \src "libresoc.v:810.3-819.6" - wire $1\d_gpr_req[0:0] - attribute \src "libresoc.v:1013.3-1022.6" - wire $1\d_xer_req[0:0] - attribute \src "libresoc.v:792.3-809.6" - wire $1\dmi_ack_o[0:0] - attribute \src "libresoc.v:1023.3-1053.6" - wire width 64 $1\dmi_dout[63:0] - attribute \src "libresoc.v:994.3-1002.6" - wire $1\dmi_read_log_data$next[0:0]$194 - attribute \src "libresoc.v:647.7-647.31" - wire $1\dmi_read_log_data[0:0] - attribute \src "libresoc.v:985.3-993.6" - wire $1\dmi_read_log_data_1$next[0:0]$191 - attribute \src "libresoc.v:651.7-651.33" - wire $1\dmi_read_log_data_1[0:0] - attribute \src "libresoc.v:820.3-828.6" - wire $1\dmi_req_i_1$next[0:0]$157 - attribute \src "libresoc.v:657.7-657.25" - wire $1\dmi_req_i_1[0:0] - attribute \src "libresoc.v:1144.3-1177.6" - wire $1\do_dmi_log_rd$next[0:0]$221 - attribute \src "libresoc.v:663.7-663.27" - wire $1\do_dmi_log_rd[0:0] - attribute \src "libresoc.v:1114.3-1143.6" - wire $1\do_icreset$next[0:0]$214 - attribute \src "libresoc.v:667.7-667.24" - wire $1\do_icreset[0:0] - attribute \src "libresoc.v:1084.3-1113.6" - wire $1\do_reset$next[0:0]$207 - attribute \src "libresoc.v:671.7-671.22" - wire $1\do_reset[0:0] - attribute \src "libresoc.v:1054.3-1083.6" - wire $1\do_step$next[0:0]$200 - attribute \src "libresoc.v:675.7-675.21" - wire $1\do_step[0:0] - attribute \src "libresoc.v:923.3-950.6" - wire width 7 $1\gspr_index$next[6:0]$179 - attribute \src "libresoc.v:679.13-679.31" - wire width 7 $1\gspr_index[6:0] - attribute \src "libresoc.v:951.3-984.6" - wire width 32 $1\log_dmi_addr$next[31:0]$185 - attribute \src "libresoc.v:685.14-685.34" - wire width 32 $1\log_dmi_addr[31:0] - attribute \src "libresoc.v:879.3-922.6" - wire $1\stopping$next[0:0]$170 - attribute \src "libresoc.v:697.7-697.22" - wire $1\stopping[0:0] - attribute \src "libresoc.v:829.3-878.6" - wire $1\terminated$next[0:0]$160 - attribute \src "libresoc.v:703.7-703.24" - wire $1\terminated[0:0] - attribute \src "libresoc.v:1144.3-1177.6" - wire $2\do_dmi_log_rd$next[0:0]$222 - attribute \src "libresoc.v:1114.3-1143.6" - wire $2\do_icreset$next[0:0]$215 - attribute \src "libresoc.v:1084.3-1113.6" - wire $2\do_reset$next[0:0]$208 - attribute \src "libresoc.v:1054.3-1083.6" - wire $2\do_step$next[0:0]$201 - attribute \src "libresoc.v:923.3-950.6" - wire width 7 $2\gspr_index$next[6:0]$180 - attribute \src "libresoc.v:951.3-984.6" - wire width 32 $2\log_dmi_addr$next[31:0]$186 - attribute \src "libresoc.v:879.3-922.6" - wire $2\stopping$next[0:0]$171 - attribute \src "libresoc.v:829.3-878.6" - wire $2\terminated$next[0:0]$161 - attribute \src "libresoc.v:1144.3-1177.6" - wire $3\do_dmi_log_rd$next[0:0]$223 - attribute \src "libresoc.v:1114.3-1143.6" - wire $3\do_icreset$next[0:0]$216 - attribute \src "libresoc.v:1084.3-1113.6" - wire $3\do_reset$next[0:0]$209 - attribute \src "libresoc.v:1054.3-1083.6" - wire $3\do_step$next[0:0]$202 - attribute \src "libresoc.v:923.3-950.6" - wire width 7 $3\gspr_index$next[6:0]$181 - attribute \src "libresoc.v:951.3-984.6" - wire width 32 $3\log_dmi_addr$next[31:0]$187 - attribute \src "libresoc.v:879.3-922.6" - wire $3\stopping$next[0:0]$172 - attribute \src "libresoc.v:829.3-878.6" - wire $3\terminated$next[0:0]$162 - attribute \src "libresoc.v:1144.3-1177.6" - wire $4\do_dmi_log_rd$next[0:0]$224 - attribute \src "libresoc.v:1114.3-1143.6" - wire $4\do_icreset$next[0:0]$217 - attribute \src "libresoc.v:1084.3-1113.6" - wire $4\do_reset$next[0:0]$210 - attribute \src "libresoc.v:1054.3-1083.6" - wire $4\do_step$next[0:0]$203 - attribute \src "libresoc.v:923.3-950.6" - wire width 7 $4\gspr_index$next[6:0]$182 - attribute \src "libresoc.v:951.3-984.6" - wire width 32 $4\log_dmi_addr$next[31:0]$188 - attribute \src "libresoc.v:879.3-922.6" - wire $4\stopping$next[0:0]$173 - attribute \src "libresoc.v:829.3-878.6" - wire $4\terminated$next[0:0]$163 - attribute \src "libresoc.v:1114.3-1143.6" - wire $5\do_icreset$next[0:0]$218 - attribute \src "libresoc.v:1084.3-1113.6" - wire $5\do_reset$next[0:0]$211 - attribute \src "libresoc.v:1054.3-1083.6" - wire $5\do_step$next[0:0]$204 - attribute \src "libresoc.v:879.3-922.6" - wire $5\stopping$next[0:0]$174 - attribute \src "libresoc.v:829.3-878.6" - wire $5\terminated$next[0:0]$164 - attribute \src "libresoc.v:879.3-922.6" - wire $6\stopping$next[0:0]$175 - attribute \src "libresoc.v:829.3-878.6" - wire $6\terminated$next[0:0]$165 - attribute \src "libresoc.v:879.3-922.6" - wire $7\stopping$next[0:0]$176 - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \ALU_dec31_dec_sub26_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \ALU_dec31_dec_sub8_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \ALU_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 3 \ALU_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 4 \ALU_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \ALU_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 10 \ALU_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 11 \ALU_dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 13 \ALU_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 7 \ALU_dec31_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \ALU_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 14 \ALU_dec31_sgn + attribute \src "libresoc.v:335.7-335.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:1350.22-1366.4" + cell \ALU_dec31_dec_sub0 \ALU_dec31_dec_sub0 + connect \ALU_dec31_dec_sub0_cr_in \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in + connect \ALU_dec31_dec_sub0_cr_out \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out + connect \ALU_dec31_dec_sub0_cry_in \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_in + connect \ALU_dec31_dec_sub0_cry_out \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_out + connect \ALU_dec31_dec_sub0_function_unit \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit + connect \ALU_dec31_dec_sub0_in1_sel \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in1_sel + connect \ALU_dec31_dec_sub0_in2_sel \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in2_sel + connect \ALU_dec31_dec_sub0_internal_op \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_internal_op + connect \ALU_dec31_dec_sub0_inv_a \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_a + connect \ALU_dec31_dec_sub0_inv_out \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_out + connect \ALU_dec31_dec_sub0_is_32b \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_is_32b + connect \ALU_dec31_dec_sub0_ldst_len \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_ldst_len + connect \ALU_dec31_dec_sub0_rc_sel \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_rc_sel + connect \ALU_dec31_dec_sub0_sgn \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_sgn + connect \opcode_in \ALU_dec31_dec_sub0_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:1367.23-1383.4" + cell \ALU_dec31_dec_sub10 \ALU_dec31_dec_sub10 + connect \ALU_dec31_dec_sub10_cr_in \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in + connect \ALU_dec31_dec_sub10_cr_out \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out + connect \ALU_dec31_dec_sub10_cry_in \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_in + connect \ALU_dec31_dec_sub10_cry_out \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_out + connect \ALU_dec31_dec_sub10_function_unit \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit + connect \ALU_dec31_dec_sub10_in1_sel \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in1_sel + connect \ALU_dec31_dec_sub10_in2_sel \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in2_sel + connect \ALU_dec31_dec_sub10_internal_op \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_internal_op + connect \ALU_dec31_dec_sub10_inv_a \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_a + connect \ALU_dec31_dec_sub10_inv_out \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_out + connect \ALU_dec31_dec_sub10_is_32b \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_is_32b + connect \ALU_dec31_dec_sub10_ldst_len \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_ldst_len + connect \ALU_dec31_dec_sub10_rc_sel \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_rc_sel + connect \ALU_dec31_dec_sub10_sgn \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_sgn + connect \opcode_in \ALU_dec31_dec_sub10_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:1384.23-1400.4" + cell \ALU_dec31_dec_sub22 \ALU_dec31_dec_sub22 + connect \ALU_dec31_dec_sub22_cr_in \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_in + connect \ALU_dec31_dec_sub22_cr_out \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_out + connect \ALU_dec31_dec_sub22_cry_in \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_in + connect \ALU_dec31_dec_sub22_cry_out \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_out + connect \ALU_dec31_dec_sub22_function_unit \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit + connect \ALU_dec31_dec_sub22_in1_sel \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in1_sel + connect \ALU_dec31_dec_sub22_in2_sel \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in2_sel + connect \ALU_dec31_dec_sub22_internal_op \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_internal_op + connect \ALU_dec31_dec_sub22_inv_a \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_a + connect \ALU_dec31_dec_sub22_inv_out \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_out + connect \ALU_dec31_dec_sub22_is_32b \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_is_32b + connect \ALU_dec31_dec_sub22_ldst_len \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_ldst_len + connect \ALU_dec31_dec_sub22_rc_sel \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_rc_sel + connect \ALU_dec31_dec_sub22_sgn \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_sgn + connect \opcode_in \ALU_dec31_dec_sub22_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:1401.23-1417.4" + cell \ALU_dec31_dec_sub26 \ALU_dec31_dec_sub26 + connect \ALU_dec31_dec_sub26_cr_in \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_in + connect \ALU_dec31_dec_sub26_cr_out \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_out + connect \ALU_dec31_dec_sub26_cry_in \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_in + connect \ALU_dec31_dec_sub26_cry_out \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_out + connect \ALU_dec31_dec_sub26_function_unit \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit + connect \ALU_dec31_dec_sub26_in1_sel \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in1_sel + connect \ALU_dec31_dec_sub26_in2_sel \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in2_sel + connect \ALU_dec31_dec_sub26_internal_op \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_internal_op + connect \ALU_dec31_dec_sub26_inv_a \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_a + connect \ALU_dec31_dec_sub26_inv_out \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_out + connect \ALU_dec31_dec_sub26_is_32b \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_is_32b + connect \ALU_dec31_dec_sub26_ldst_len \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_ldst_len + connect \ALU_dec31_dec_sub26_rc_sel \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_rc_sel + connect \ALU_dec31_dec_sub26_sgn \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_sgn + connect \opcode_in \ALU_dec31_dec_sub26_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:1418.22-1434.4" + cell \ALU_dec31_dec_sub8 \ALU_dec31_dec_sub8 + connect \ALU_dec31_dec_sub8_cr_in \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_in + connect \ALU_dec31_dec_sub8_cr_out \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out + connect \ALU_dec31_dec_sub8_cry_in \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_in + connect \ALU_dec31_dec_sub8_cry_out \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_out + connect \ALU_dec31_dec_sub8_function_unit \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit + connect \ALU_dec31_dec_sub8_in1_sel \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in1_sel + connect \ALU_dec31_dec_sub8_in2_sel \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in2_sel + connect \ALU_dec31_dec_sub8_internal_op \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_internal_op + connect \ALU_dec31_dec_sub8_inv_a \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_a + connect \ALU_dec31_dec_sub8_inv_out \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_out + connect \ALU_dec31_dec_sub8_is_32b \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_is_32b + connect \ALU_dec31_dec_sub8_ldst_len \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_ldst_len + connect \ALU_dec31_dec_sub8_rc_sel \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_rc_sel + connect \ALU_dec31_dec_sub8_sgn \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn + connect \opcode_in \ALU_dec31_dec_sub8_opcode_in + end + attribute \src "libresoc.v:1435.3-1456.6" + process $proc$libresoc.v:1435$16 + assign { } { } + assign { } { } + assign $0\ALU_dec31_in2_sel[3:0] $1\ALU_dec31_in2_sel[3:0] + attribute \src "libresoc.v:1436.5-1436.29" + switch \initial + attribute \src "libresoc.v:1436.9-1436.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in2_sel + case + assign $1\ALU_dec31_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_dec31_in2_sel $0\ALU_dec31_in2_sel[3:0] + end + attribute \src "libresoc.v:1457.3-1478.6" + process $proc$libresoc.v:1457$17 + assign { } { } + assign { } { } + assign $0\ALU_dec31_cr_in[2:0] $1\ALU_dec31_cr_in[2:0] + attribute \src "libresoc.v:1458.5-1458.29" + switch \initial + attribute \src "libresoc.v:1458.9-1458.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_in + case + assign $1\ALU_dec31_cr_in[2:0] 3'000 + end + sync always + update \ALU_dec31_cr_in $0\ALU_dec31_cr_in[2:0] + end + attribute \src "libresoc.v:1479.3-1500.6" + process $proc$libresoc.v:1479$18 + assign { } { } + assign { } { } + assign $0\ALU_dec31_cr_out[2:0] $1\ALU_dec31_cr_out[2:0] + attribute \src "libresoc.v:1480.5-1480.29" + switch \initial + attribute \src "libresoc.v:1480.9-1480.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out + case + assign $1\ALU_dec31_cr_out[2:0] 3'000 + end + sync always + update \ALU_dec31_cr_out $0\ALU_dec31_cr_out[2:0] + end + attribute \src "libresoc.v:1501.3-1522.6" + process $proc$libresoc.v:1501$19 + assign { } { } + assign { } { } + assign $0\ALU_dec31_ldst_len[3:0] $1\ALU_dec31_ldst_len[3:0] + attribute \src "libresoc.v:1502.5-1502.29" + switch \initial + attribute \src "libresoc.v:1502.9-1502.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_ldst_len + case + assign $1\ALU_dec31_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_dec31_ldst_len $0\ALU_dec31_ldst_len[3:0] + end + attribute \src "libresoc.v:1523.3-1544.6" + process $proc$libresoc.v:1523$20 + assign { } { } + assign { } { } + assign $0\ALU_dec31_rc_sel[1:0] $1\ALU_dec31_rc_sel[1:0] + attribute \src "libresoc.v:1524.5-1524.29" + switch \initial + attribute \src "libresoc.v:1524.9-1524.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_rc_sel + case + assign $1\ALU_dec31_rc_sel[1:0] 2'00 + end + sync always + update \ALU_dec31_rc_sel $0\ALU_dec31_rc_sel[1:0] + end + attribute \src "libresoc.v:1545.3-1566.6" + process $proc$libresoc.v:1545$21 + assign { } { } + assign { } { } + assign $0\ALU_dec31_cry_in[1:0] $1\ALU_dec31_cry_in[1:0] + attribute \src "libresoc.v:1546.5-1546.29" + switch \initial + attribute \src "libresoc.v:1546.9-1546.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_in + case + assign $1\ALU_dec31_cry_in[1:0] 2'00 + end + sync always + update \ALU_dec31_cry_in $0\ALU_dec31_cry_in[1:0] + end + attribute \src "libresoc.v:1567.3-1588.6" + process $proc$libresoc.v:1567$22 + assign { } { } + assign { } { } + assign $0\ALU_dec31_inv_a[0:0] $1\ALU_dec31_inv_a[0:0] + attribute \src "libresoc.v:1568.5-1568.29" + switch \initial + attribute \src "libresoc.v:1568.9-1568.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_a + case + assign $1\ALU_dec31_inv_a[0:0] 1'0 + end + sync always + update \ALU_dec31_inv_a $0\ALU_dec31_inv_a[0:0] + end + attribute \src "libresoc.v:1589.3-1610.6" + process $proc$libresoc.v:1589$23 + assign { } { } + assign { } { } + assign $0\ALU_dec31_inv_out[0:0] $1\ALU_dec31_inv_out[0:0] + attribute \src "libresoc.v:1590.5-1590.29" + switch \initial + attribute \src "libresoc.v:1590.9-1590.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_out + case + assign $1\ALU_dec31_inv_out[0:0] 1'0 + end + sync always + update \ALU_dec31_inv_out $0\ALU_dec31_inv_out[0:0] + end + attribute \src "libresoc.v:1611.3-1632.6" + process $proc$libresoc.v:1611$24 + assign { } { } + assign { } { } + assign $0\ALU_dec31_cry_out[0:0] $1\ALU_dec31_cry_out[0:0] + attribute \src "libresoc.v:1612.5-1612.29" + switch \initial + attribute \src "libresoc.v:1612.9-1612.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_out + case + assign $1\ALU_dec31_cry_out[0:0] 1'0 + end + sync always + update \ALU_dec31_cry_out $0\ALU_dec31_cry_out[0:0] + end + attribute \src "libresoc.v:1633.3-1654.6" + process $proc$libresoc.v:1633$25 + assign { } { } + assign { } { } + assign $0\ALU_dec31_is_32b[0:0] $1\ALU_dec31_is_32b[0:0] + attribute \src "libresoc.v:1634.5-1634.29" + switch \initial + attribute \src "libresoc.v:1634.9-1634.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_is_32b + case + assign $1\ALU_dec31_is_32b[0:0] 1'0 + end + sync always + update \ALU_dec31_is_32b $0\ALU_dec31_is_32b[0:0] + end + attribute \src "libresoc.v:1655.3-1676.6" + process $proc$libresoc.v:1655$26 + assign { } { } + assign { } { } + assign $0\ALU_dec31_sgn[0:0] $1\ALU_dec31_sgn[0:0] + attribute \src "libresoc.v:1656.5-1656.29" + switch \initial + attribute \src "libresoc.v:1656.9-1656.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn + case + assign $1\ALU_dec31_sgn[0:0] 1'0 + end + sync always + update \ALU_dec31_sgn $0\ALU_dec31_sgn[0:0] + end + attribute \src "libresoc.v:1677.3-1698.6" + process $proc$libresoc.v:1677$27 + assign { } { } + assign { } { } + assign $0\ALU_dec31_function_unit[11:0] $1\ALU_dec31_function_unit[11:0] + attribute \src "libresoc.v:1678.5-1678.29" + switch \initial + attribute \src "libresoc.v:1678.9-1678.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_function_unit[11:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_function_unit[11:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_function_unit[11:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_function_unit[11:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_function_unit[11:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit + case + assign $1\ALU_dec31_function_unit[11:0] 12'000000000000 + end + sync always + update \ALU_dec31_function_unit $0\ALU_dec31_function_unit[11:0] + end + attribute \src "libresoc.v:1699.3-1720.6" + process $proc$libresoc.v:1699$28 + assign { } { } + assign { } { } + assign $0\ALU_dec31_internal_op[6:0] $1\ALU_dec31_internal_op[6:0] + attribute \src "libresoc.v:1700.5-1700.29" + switch \initial + attribute \src "libresoc.v:1700.9-1700.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_internal_op + case + assign $1\ALU_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_dec31_internal_op $0\ALU_dec31_internal_op[6:0] + end + attribute \src "libresoc.v:1721.3-1742.6" + process $proc$libresoc.v:1721$29 + assign { } { } + assign { } { } + assign $0\ALU_dec31_in1_sel[2:0] $1\ALU_dec31_in1_sel[2:0] + attribute \src "libresoc.v:1722.5-1722.29" + switch \initial + attribute \src "libresoc.v:1722.9-1722.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in1_sel + case + assign $1\ALU_dec31_in1_sel[2:0] 3'000 + end + sync always + update \ALU_dec31_in1_sel $0\ALU_dec31_in1_sel[2:0] + end + attribute \src "libresoc.v:335.7-335.20" + process $proc$libresoc.v:335$30 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + connect \ALU_dec31_dec_sub8_opcode_in \opcode_in + connect \ALU_dec31_dec_sub22_opcode_in \opcode_in + connect \ALU_dec31_dec_sub26_opcode_in \opcode_in + connect \ALU_dec31_dec_sub0_opcode_in \opcode_in + connect \ALU_dec31_dec_sub10_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:1754.1-2163.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub0" +attribute \generator "nMigen" +module \ALU_dec31_dec_sub0 + attribute \src "libresoc.v:2082.3-2097.6" + wire width 3 $0\ALU_dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:2098.3-2113.6" + wire width 3 $0\ALU_dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:2146.3-2161.6" + wire width 2 $0\ALU_dec31_dec_sub0_cry_in[1:0] + attribute \src "libresoc.v:1986.3-2001.6" + wire $0\ALU_dec31_dec_sub0_cry_out[0:0] + attribute \src "libresoc.v:1938.3-1953.6" + wire width 12 $0\ALU_dec31_dec_sub0_function_unit[11:0] + attribute \src "libresoc.v:2050.3-2065.6" + wire width 3 $0\ALU_dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:2066.3-2081.6" + wire width 4 $0\ALU_dec31_dec_sub0_in2_sel[3:0] + attribute \src "libresoc.v:2034.3-2049.6" + wire width 7 $0\ALU_dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:1954.3-1969.6" + wire $0\ALU_dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:1970.3-1985.6" + wire $0\ALU_dec31_dec_sub0_inv_out[0:0] + attribute \src "libresoc.v:2002.3-2017.6" + wire $0\ALU_dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:2114.3-2129.6" + wire width 4 $0\ALU_dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:2130.3-2145.6" + wire width 2 $0\ALU_dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:2018.3-2033.6" + wire $0\ALU_dec31_dec_sub0_sgn[0:0] + attribute \src "libresoc.v:1755.7-1755.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:2082.3-2097.6" + wire width 3 $1\ALU_dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:2098.3-2113.6" + wire width 3 $1\ALU_dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:2146.3-2161.6" + wire width 2 $1\ALU_dec31_dec_sub0_cry_in[1:0] + attribute \src "libresoc.v:1986.3-2001.6" + wire $1\ALU_dec31_dec_sub0_cry_out[0:0] + attribute \src "libresoc.v:1938.3-1953.6" + wire width 12 $1\ALU_dec31_dec_sub0_function_unit[11:0] + attribute \src "libresoc.v:2050.3-2065.6" + wire width 3 $1\ALU_dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:2066.3-2081.6" + wire width 4 $1\ALU_dec31_dec_sub0_in2_sel[3:0] + attribute \src "libresoc.v:2034.3-2049.6" + wire width 7 $1\ALU_dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:1954.3-1969.6" + wire $1\ALU_dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:1970.3-1985.6" + wire $1\ALU_dec31_dec_sub0_inv_out[0:0] + attribute \src "libresoc.v:2002.3-2017.6" + wire $1\ALU_dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:2114.3-2129.6" + wire width 4 $1\ALU_dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:2130.3-2145.6" + wire width 2 $1\ALU_dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:2018.3-2033.6" + wire $1\ALU_dec31_dec_sub0_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \ALU_dec31_dec_sub0_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 6 \ALU_dec31_dec_sub0_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 9 \ALU_dec31_dec_sub0_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 12 \ALU_dec31_dec_sub0_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \ALU_dec31_dec_sub0_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 3 \ALU_dec31_dec_sub0_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 4 \ALU_dec31_dec_sub0_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \ALU_dec31_dec_sub0_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 10 \ALU_dec31_dec_sub0_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 11 \ALU_dec31_dec_sub0_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 13 \ALU_dec31_dec_sub0_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 7 \ALU_dec31_dec_sub0_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \ALU_dec31_dec_sub0_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 14 \ALU_dec31_dec_sub0_sgn + attribute \src "libresoc.v:1755.7-1755.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:1755.7-1755.20" + process $proc$libresoc.v:1755$45 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:1938.3-1953.6" + process $proc$libresoc.v:1938$31 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_function_unit[11:0] $1\ALU_dec31_dec_sub0_function_unit[11:0] + attribute \src "libresoc.v:1939.5-1939.29" + switch \initial + attribute \src "libresoc.v:1939.9-1939.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_function_unit[11:0] 12'000000000010 + case + assign $1\ALU_dec31_dec_sub0_function_unit[11:0] 12'000000000000 + end + sync always + update \ALU_dec31_dec_sub0_function_unit $0\ALU_dec31_dec_sub0_function_unit[11:0] + end + attribute \src "libresoc.v:1954.3-1969.6" + process $proc$libresoc.v:1954$32 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_inv_a[0:0] $1\ALU_dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:1955.5-1955.29" + switch \initial + attribute \src "libresoc.v:1955.9-1955.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_inv_a[0:0] 1'1 + case + assign $1\ALU_dec31_dec_sub0_inv_a[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub0_inv_a $0\ALU_dec31_dec_sub0_inv_a[0:0] + end + attribute \src "libresoc.v:1970.3-1985.6" + process $proc$libresoc.v:1970$33 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_inv_out[0:0] $1\ALU_dec31_dec_sub0_inv_out[0:0] + attribute \src "libresoc.v:1971.5-1971.29" + switch \initial + attribute \src "libresoc.v:1971.9-1971.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_inv_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub0_inv_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub0_inv_out $0\ALU_dec31_dec_sub0_inv_out[0:0] + end + attribute \src "libresoc.v:1986.3-2001.6" + process $proc$libresoc.v:1986$34 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_cry_out[0:0] $1\ALU_dec31_dec_sub0_cry_out[0:0] + attribute \src "libresoc.v:1987.5-1987.29" + switch \initial + attribute \src "libresoc.v:1987.9-1987.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cry_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub0_cry_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub0_cry_out $0\ALU_dec31_dec_sub0_cry_out[0:0] + end + attribute \src "libresoc.v:2002.3-2017.6" + process $proc$libresoc.v:2002$35 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_is_32b[0:0] $1\ALU_dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:2003.5-2003.29" + switch \initial + attribute \src "libresoc.v:2003.9-2003.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_is_32b[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub0_is_32b[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub0_is_32b $0\ALU_dec31_dec_sub0_is_32b[0:0] + end + attribute \src "libresoc.v:2018.3-2033.6" + process $proc$libresoc.v:2018$36 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_sgn[0:0] $1\ALU_dec31_dec_sub0_sgn[0:0] + attribute \src "libresoc.v:2019.5-2019.29" + switch \initial + attribute \src "libresoc.v:2019.9-2019.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_sgn[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub0_sgn[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub0_sgn $0\ALU_dec31_dec_sub0_sgn[0:0] + end + attribute \src "libresoc.v:2034.3-2049.6" + process $proc$libresoc.v:2034$37 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_internal_op[6:0] $1\ALU_dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:2035.5-2035.29" + switch \initial + attribute \src "libresoc.v:2035.9-2035.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_internal_op[6:0] 7'0001100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_internal_op[6:0] 7'0001010 + case + assign $1\ALU_dec31_dec_sub0_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_dec31_dec_sub0_internal_op $0\ALU_dec31_dec_sub0_internal_op[6:0] + end + attribute \src "libresoc.v:2050.3-2065.6" + process $proc$libresoc.v:2050$38 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_in1_sel[2:0] $1\ALU_dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:2051.5-2051.29" + switch \initial + attribute \src "libresoc.v:2051.9-2051.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_in1_sel[2:0] 3'001 + case + assign $1\ALU_dec31_dec_sub0_in1_sel[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub0_in1_sel $0\ALU_dec31_dec_sub0_in1_sel[2:0] + end + attribute \src "libresoc.v:2066.3-2081.6" + process $proc$libresoc.v:2066$39 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_in2_sel[3:0] $1\ALU_dec31_dec_sub0_in2_sel[3:0] + attribute \src "libresoc.v:2067.5-2067.29" + switch \initial + attribute \src "libresoc.v:2067.9-2067.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_in2_sel[3:0] 4'0001 + case + assign $1\ALU_dec31_dec_sub0_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub0_in2_sel $0\ALU_dec31_dec_sub0_in2_sel[3:0] + end + attribute \src "libresoc.v:2082.3-2097.6" + process $proc$libresoc.v:2082$40 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_cr_in[2:0] $1\ALU_dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:2083.5-2083.29" + switch \initial + attribute \src "libresoc.v:2083.9-2083.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cr_in[2:0] 3'000 + case + assign $1\ALU_dec31_dec_sub0_cr_in[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub0_cr_in $0\ALU_dec31_dec_sub0_cr_in[2:0] + end + attribute \src "libresoc.v:2098.3-2113.6" + process $proc$libresoc.v:2098$41 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_cr_out[2:0] $1\ALU_dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:2099.5-2099.29" + switch \initial + attribute \src "libresoc.v:2099.9-2099.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cr_out[2:0] 3'010 + case + assign $1\ALU_dec31_dec_sub0_cr_out[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub0_cr_out $0\ALU_dec31_dec_sub0_cr_out[2:0] + end + attribute \src "libresoc.v:2114.3-2129.6" + process $proc$libresoc.v:2114$42 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_ldst_len[3:0] $1\ALU_dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:2115.5-2115.29" + switch \initial + attribute \src "libresoc.v:2115.9-2115.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_ldst_len[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub0_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub0_ldst_len $0\ALU_dec31_dec_sub0_ldst_len[3:0] + end + attribute \src "libresoc.v:2130.3-2145.6" + process $proc$libresoc.v:2130$43 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_rc_sel[1:0] $1\ALU_dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:2131.5-2131.29" + switch \initial + attribute \src "libresoc.v:2131.9-2131.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_rc_sel[1:0] 2'00 + case + assign $1\ALU_dec31_dec_sub0_rc_sel[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub0_rc_sel $0\ALU_dec31_dec_sub0_rc_sel[1:0] + end + attribute \src "libresoc.v:2146.3-2161.6" + process $proc$libresoc.v:2146$44 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_cry_in[1:0] $1\ALU_dec31_dec_sub0_cry_in[1:0] + attribute \src "libresoc.v:2147.5-2147.29" + switch \initial + attribute \src "libresoc.v:2147.9-2147.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cry_in[1:0] 2'01 + case + assign $1\ALU_dec31_dec_sub0_cry_in[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub0_cry_in $0\ALU_dec31_dec_sub0_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:2167.1-2870.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub10" +attribute \generator "nMigen" +module \ALU_dec31_dec_sub10 + attribute \src "libresoc.v:2684.3-2720.6" + wire width 3 $0\ALU_dec31_dec_sub10_cr_in[2:0] + attribute \src "libresoc.v:2721.3-2757.6" + wire width 3 $0\ALU_dec31_dec_sub10_cr_out[2:0] + attribute \src "libresoc.v:2832.3-2868.6" + wire width 2 $0\ALU_dec31_dec_sub10_cry_in[1:0] + attribute \src "libresoc.v:2462.3-2498.6" + wire $0\ALU_dec31_dec_sub10_cry_out[0:0] + attribute \src "libresoc.v:2351.3-2387.6" + wire width 12 $0\ALU_dec31_dec_sub10_function_unit[11:0] + attribute \src "libresoc.v:2610.3-2646.6" + wire width 3 $0\ALU_dec31_dec_sub10_in1_sel[2:0] + attribute \src "libresoc.v:2647.3-2683.6" + wire width 4 $0\ALU_dec31_dec_sub10_in2_sel[3:0] + attribute \src "libresoc.v:2573.3-2609.6" + wire width 7 $0\ALU_dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:2388.3-2424.6" + wire $0\ALU_dec31_dec_sub10_inv_a[0:0] + attribute \src "libresoc.v:2425.3-2461.6" + wire $0\ALU_dec31_dec_sub10_inv_out[0:0] + attribute \src "libresoc.v:2499.3-2535.6" + wire $0\ALU_dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:2758.3-2794.6" + wire width 4 $0\ALU_dec31_dec_sub10_ldst_len[3:0] + attribute \src "libresoc.v:2795.3-2831.6" + wire width 2 $0\ALU_dec31_dec_sub10_rc_sel[1:0] + attribute \src "libresoc.v:2536.3-2572.6" + wire $0\ALU_dec31_dec_sub10_sgn[0:0] + attribute \src "libresoc.v:2168.7-2168.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:2684.3-2720.6" + wire width 3 $1\ALU_dec31_dec_sub10_cr_in[2:0] + attribute \src "libresoc.v:2721.3-2757.6" + wire width 3 $1\ALU_dec31_dec_sub10_cr_out[2:0] + attribute \src "libresoc.v:2832.3-2868.6" + wire width 2 $1\ALU_dec31_dec_sub10_cry_in[1:0] + attribute \src "libresoc.v:2462.3-2498.6" + wire $1\ALU_dec31_dec_sub10_cry_out[0:0] + attribute \src "libresoc.v:2351.3-2387.6" + wire width 12 $1\ALU_dec31_dec_sub10_function_unit[11:0] + attribute \src "libresoc.v:2610.3-2646.6" + wire width 3 $1\ALU_dec31_dec_sub10_in1_sel[2:0] + attribute \src "libresoc.v:2647.3-2683.6" + wire width 4 $1\ALU_dec31_dec_sub10_in2_sel[3:0] + attribute \src "libresoc.v:2573.3-2609.6" + wire width 7 $1\ALU_dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:2388.3-2424.6" + wire $1\ALU_dec31_dec_sub10_inv_a[0:0] + attribute \src "libresoc.v:2425.3-2461.6" + wire $1\ALU_dec31_dec_sub10_inv_out[0:0] + attribute \src "libresoc.v:2499.3-2535.6" + wire $1\ALU_dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:2758.3-2794.6" + wire width 4 $1\ALU_dec31_dec_sub10_ldst_len[3:0] + attribute \src "libresoc.v:2795.3-2831.6" + wire width 2 $1\ALU_dec31_dec_sub10_rc_sel[1:0] + attribute \src "libresoc.v:2536.3-2572.6" + wire $1\ALU_dec31_dec_sub10_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \ALU_dec31_dec_sub10_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 6 \ALU_dec31_dec_sub10_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 9 \ALU_dec31_dec_sub10_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 12 \ALU_dec31_dec_sub10_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \ALU_dec31_dec_sub10_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 3 \ALU_dec31_dec_sub10_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 4 \ALU_dec31_dec_sub10_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \ALU_dec31_dec_sub10_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 10 \ALU_dec31_dec_sub10_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 11 \ALU_dec31_dec_sub10_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 13 \ALU_dec31_dec_sub10_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 7 \ALU_dec31_dec_sub10_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \ALU_dec31_dec_sub10_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 14 \ALU_dec31_dec_sub10_sgn + attribute \src "libresoc.v:2168.7-2168.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:2168.7-2168.20" + process $proc$libresoc.v:2168$60 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:2351.3-2387.6" + process $proc$libresoc.v:2351$46 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_function_unit[11:0] $1\ALU_dec31_dec_sub10_function_unit[11:0] + attribute \src "libresoc.v:2352.5-2352.29" + switch \initial + attribute \src "libresoc.v:2352.9-2352.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + case + assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000000 + end + sync always + update \ALU_dec31_dec_sub10_function_unit $0\ALU_dec31_dec_sub10_function_unit[11:0] + end + attribute \src "libresoc.v:2388.3-2424.6" + process $proc$libresoc.v:2388$47 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_inv_a[0:0] $1\ALU_dec31_dec_sub10_inv_a[0:0] + attribute \src "libresoc.v:2389.5-2389.29" + switch \initial + attribute \src "libresoc.v:2389.9-2389.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub10_inv_a $0\ALU_dec31_dec_sub10_inv_a[0:0] + end + attribute \src "libresoc.v:2425.3-2461.6" + process $proc$libresoc.v:2425$48 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_inv_out[0:0] $1\ALU_dec31_dec_sub10_inv_out[0:0] + attribute \src "libresoc.v:2426.5-2426.29" + switch \initial + attribute \src "libresoc.v:2426.9-2426.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub10_inv_out $0\ALU_dec31_dec_sub10_inv_out[0:0] + end + attribute \src "libresoc.v:2462.3-2498.6" + process $proc$libresoc.v:2462$49 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_cry_out[0:0] $1\ALU_dec31_dec_sub10_cry_out[0:0] + attribute \src "libresoc.v:2463.5-2463.29" + switch \initial + attribute \src "libresoc.v:2463.9-2463.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + case + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub10_cry_out $0\ALU_dec31_dec_sub10_cry_out[0:0] + end + attribute \src "libresoc.v:2499.3-2535.6" + process $proc$libresoc.v:2499$50 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_is_32b[0:0] $1\ALU_dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:2500.5-2500.29" + switch \initial + attribute \src "libresoc.v:2500.9-2500.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub10_is_32b $0\ALU_dec31_dec_sub10_is_32b[0:0] + end + attribute \src "libresoc.v:2536.3-2572.6" + process $proc$libresoc.v:2536$51 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_sgn[0:0] $1\ALU_dec31_dec_sub10_sgn[0:0] + attribute \src "libresoc.v:2537.5-2537.29" + switch \initial + attribute \src "libresoc.v:2537.9-2537.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub10_sgn $0\ALU_dec31_dec_sub10_sgn[0:0] + end + attribute \src "libresoc.v:2573.3-2609.6" + process $proc$libresoc.v:2573$52 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_internal_op[6:0] $1\ALU_dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:2574.5-2574.29" + switch \initial + attribute \src "libresoc.v:2574.9-2574.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + case + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_dec31_dec_sub10_internal_op $0\ALU_dec31_dec_sub10_internal_op[6:0] + end + attribute \src "libresoc.v:2610.3-2646.6" + process $proc$libresoc.v:2610$53 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_in1_sel[2:0] $1\ALU_dec31_dec_sub10_in1_sel[2:0] + attribute \src "libresoc.v:2611.5-2611.29" + switch \initial + attribute \src "libresoc.v:2611.9-2611.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + case + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub10_in1_sel $0\ALU_dec31_dec_sub10_in1_sel[2:0] + end + attribute \src "libresoc.v:2647.3-2683.6" + process $proc$libresoc.v:2647$54 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_in2_sel[3:0] $1\ALU_dec31_dec_sub10_in2_sel[3:0] + attribute \src "libresoc.v:2648.5-2648.29" + switch \initial + attribute \src "libresoc.v:2648.9-2648.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub10_in2_sel $0\ALU_dec31_dec_sub10_in2_sel[3:0] + end + attribute \src "libresoc.v:2684.3-2720.6" + process $proc$libresoc.v:2684$55 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_cr_in[2:0] $1\ALU_dec31_dec_sub10_cr_in[2:0] + attribute \src "libresoc.v:2685.5-2685.29" + switch \initial + attribute \src "libresoc.v:2685.9-2685.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + case + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub10_cr_in $0\ALU_dec31_dec_sub10_cr_in[2:0] + end + attribute \src "libresoc.v:2721.3-2757.6" + process $proc$libresoc.v:2721$56 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_cr_out[2:0] $1\ALU_dec31_dec_sub10_cr_out[2:0] + attribute \src "libresoc.v:2722.5-2722.29" + switch \initial + attribute \src "libresoc.v:2722.9-2722.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + case + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub10_cr_out $0\ALU_dec31_dec_sub10_cr_out[2:0] + end + attribute \src "libresoc.v:2758.3-2794.6" + process $proc$libresoc.v:2758$57 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_ldst_len[3:0] $1\ALU_dec31_dec_sub10_ldst_len[3:0] + attribute \src "libresoc.v:2759.5-2759.29" + switch \initial + attribute \src "libresoc.v:2759.9-2759.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub10_ldst_len $0\ALU_dec31_dec_sub10_ldst_len[3:0] + end + attribute \src "libresoc.v:2795.3-2831.6" + process $proc$libresoc.v:2795$58 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_rc_sel[1:0] $1\ALU_dec31_dec_sub10_rc_sel[1:0] + attribute \src "libresoc.v:2796.5-2796.29" + switch \initial + attribute \src "libresoc.v:2796.9-2796.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + case + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub10_rc_sel $0\ALU_dec31_dec_sub10_rc_sel[1:0] + end + attribute \src "libresoc.v:2832.3-2868.6" + process $proc$libresoc.v:2832$59 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_cry_in[1:0] $1\ALU_dec31_dec_sub10_cry_in[1:0] + attribute \src "libresoc.v:2833.5-2833.29" + switch \initial + attribute \src "libresoc.v:2833.9-2833.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 + case + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub10_cry_in $0\ALU_dec31_dec_sub10_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:2874.1-3451.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub22" +attribute \generator "nMigen" +module \ALU_dec31_dec_sub22 + attribute \src "libresoc.v:3310.3-3337.6" + wire width 3 $0\ALU_dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:3338.3-3365.6" + wire width 3 $0\ALU_dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:3422.3-3449.6" + wire width 2 $0\ALU_dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:3142.3-3169.6" + wire $0\ALU_dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:3058.3-3085.6" + wire width 12 $0\ALU_dec31_dec_sub22_function_unit[11:0] + attribute \src "libresoc.v:3254.3-3281.6" + wire width 3 $0\ALU_dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:3282.3-3309.6" + wire width 4 $0\ALU_dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:3226.3-3253.6" + wire width 7 $0\ALU_dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:3086.3-3113.6" + wire $0\ALU_dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:3114.3-3141.6" + wire $0\ALU_dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:3170.3-3197.6" + wire $0\ALU_dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:3366.3-3393.6" + wire width 4 $0\ALU_dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:3394.3-3421.6" + wire width 2 $0\ALU_dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:3198.3-3225.6" + wire $0\ALU_dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:2875.7-2875.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:3310.3-3337.6" + wire width 3 $1\ALU_dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:3338.3-3365.6" + wire width 3 $1\ALU_dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:3422.3-3449.6" + wire width 2 $1\ALU_dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:3142.3-3169.6" + wire $1\ALU_dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:3058.3-3085.6" + wire width 12 $1\ALU_dec31_dec_sub22_function_unit[11:0] + attribute \src "libresoc.v:3254.3-3281.6" + wire width 3 $1\ALU_dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:3282.3-3309.6" + wire width 4 $1\ALU_dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:3226.3-3253.6" + wire width 7 $1\ALU_dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:3086.3-3113.6" + wire $1\ALU_dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:3114.3-3141.6" + wire $1\ALU_dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:3170.3-3197.6" + wire $1\ALU_dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:3366.3-3393.6" + wire width 4 $1\ALU_dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:3394.3-3421.6" + wire width 2 $1\ALU_dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:3198.3-3225.6" + wire $1\ALU_dec31_dec_sub22_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \ALU_dec31_dec_sub22_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 6 \ALU_dec31_dec_sub22_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 9 \ALU_dec31_dec_sub22_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 12 \ALU_dec31_dec_sub22_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \ALU_dec31_dec_sub22_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 3 \ALU_dec31_dec_sub22_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 4 \ALU_dec31_dec_sub22_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \ALU_dec31_dec_sub22_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 10 \ALU_dec31_dec_sub22_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 11 \ALU_dec31_dec_sub22_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 13 \ALU_dec31_dec_sub22_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 7 \ALU_dec31_dec_sub22_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \ALU_dec31_dec_sub22_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 14 \ALU_dec31_dec_sub22_sgn + attribute \src "libresoc.v:2875.7-2875.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:2875.7-2875.20" + process $proc$libresoc.v:2875$75 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:3058.3-3085.6" + process $proc$libresoc.v:3058$61 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_function_unit[11:0] $1\ALU_dec31_dec_sub22_function_unit[11:0] + attribute \src "libresoc.v:3059.5-3059.29" + switch \initial + attribute \src "libresoc.v:3059.9-3059.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 + case + assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000000 + end + sync always + update \ALU_dec31_dec_sub22_function_unit $0\ALU_dec31_dec_sub22_function_unit[11:0] + end + attribute \src "libresoc.v:3086.3-3113.6" + process $proc$libresoc.v:3086$62 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_inv_a[0:0] $1\ALU_dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:3087.5-3087.29" + switch \initial + attribute \src "libresoc.v:3087.9-3087.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub22_inv_a $0\ALU_dec31_dec_sub22_inv_a[0:0] + end + attribute \src "libresoc.v:3114.3-3141.6" + process $proc$libresoc.v:3114$63 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_inv_out[0:0] $1\ALU_dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:3115.5-3115.29" + switch \initial + attribute \src "libresoc.v:3115.9-3115.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub22_inv_out $0\ALU_dec31_dec_sub22_inv_out[0:0] + end + attribute \src "libresoc.v:3142.3-3169.6" + process $proc$libresoc.v:3142$64 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_cry_out[0:0] $1\ALU_dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:3143.5-3143.29" + switch \initial + attribute \src "libresoc.v:3143.9-3143.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub22_cry_out $0\ALU_dec31_dec_sub22_cry_out[0:0] + end + attribute \src "libresoc.v:3170.3-3197.6" + process $proc$libresoc.v:3170$65 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_is_32b[0:0] $1\ALU_dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:3171.5-3171.29" + switch \initial + attribute \src "libresoc.v:3171.9-3171.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub22_is_32b $0\ALU_dec31_dec_sub22_is_32b[0:0] + end + attribute \src "libresoc.v:3198.3-3225.6" + process $proc$libresoc.v:3198$66 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_sgn[0:0] $1\ALU_dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:3199.5-3199.29" + switch \initial + attribute \src "libresoc.v:3199.9-3199.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub22_sgn $0\ALU_dec31_dec_sub22_sgn[0:0] + end + attribute \src "libresoc.v:3226.3-3253.6" + process $proc$libresoc.v:3226$67 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_internal_op[6:0] $1\ALU_dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:3227.5-3227.29" + switch \initial + attribute \src "libresoc.v:3227.9-3227.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0100001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 + case + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_dec31_dec_sub22_internal_op $0\ALU_dec31_dec_sub22_internal_op[6:0] + end + attribute \src "libresoc.v:3254.3-3281.6" + process $proc$libresoc.v:3254$68 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_in1_sel[2:0] $1\ALU_dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:3255.5-3255.29" + switch \initial + attribute \src "libresoc.v:3255.9-3255.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + case + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub22_in1_sel $0\ALU_dec31_dec_sub22_in1_sel[2:0] + end + attribute \src "libresoc.v:3282.3-3309.6" + process $proc$libresoc.v:3282$69 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_in2_sel[3:0] $1\ALU_dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:3283.5-3283.29" + switch \initial + attribute \src "libresoc.v:3283.9-3283.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub22_in2_sel $0\ALU_dec31_dec_sub22_in2_sel[3:0] + end + attribute \src "libresoc.v:3310.3-3337.6" + process $proc$libresoc.v:3310$70 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_cr_in[2:0] $1\ALU_dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:3311.5-3311.29" + switch \initial + attribute \src "libresoc.v:3311.9-3311.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + case + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub22_cr_in $0\ALU_dec31_dec_sub22_cr_in[2:0] + end + attribute \src "libresoc.v:3338.3-3365.6" + process $proc$libresoc.v:3338$71 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_cr_out[2:0] $1\ALU_dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:3339.5-3339.29" + switch \initial + attribute \src "libresoc.v:3339.9-3339.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + case + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub22_cr_out $0\ALU_dec31_dec_sub22_cr_out[2:0] + end + attribute \src "libresoc.v:3366.3-3393.6" + process $proc$libresoc.v:3366$72 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_ldst_len[3:0] $1\ALU_dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:3367.5-3367.29" + switch \initial + attribute \src "libresoc.v:3367.9-3367.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub22_ldst_len $0\ALU_dec31_dec_sub22_ldst_len[3:0] + end + attribute \src "libresoc.v:3394.3-3421.6" + process $proc$libresoc.v:3394$73 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_rc_sel[1:0] $1\ALU_dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:3395.5-3395.29" + switch \initial + attribute \src "libresoc.v:3395.9-3395.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + case + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub22_rc_sel $0\ALU_dec31_dec_sub22_rc_sel[1:0] + end + attribute \src "libresoc.v:3422.3-3449.6" + process $proc$libresoc.v:3422$74 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_cry_in[1:0] $1\ALU_dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:3423.5-3423.29" + switch \initial + attribute \src "libresoc.v:3423.9-3423.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + case + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub22_cry_in $0\ALU_dec31_dec_sub22_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:3455.1-3864.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub26" +attribute \generator "nMigen" +module \ALU_dec31_dec_sub26 + attribute \src "libresoc.v:3783.3-3798.6" + wire width 3 $0\ALU_dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:3799.3-3814.6" + wire width 3 $0\ALU_dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:3847.3-3862.6" + wire width 2 $0\ALU_dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:3687.3-3702.6" + wire $0\ALU_dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:3639.3-3654.6" + wire width 12 $0\ALU_dec31_dec_sub26_function_unit[11:0] + attribute \src "libresoc.v:3751.3-3766.6" + wire width 3 $0\ALU_dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:3767.3-3782.6" + wire width 4 $0\ALU_dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:3735.3-3750.6" + wire width 7 $0\ALU_dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:3655.3-3670.6" + wire $0\ALU_dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:3671.3-3686.6" + wire $0\ALU_dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:3703.3-3718.6" + wire $0\ALU_dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:3815.3-3830.6" + wire width 4 $0\ALU_dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:3831.3-3846.6" + wire width 2 $0\ALU_dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:3719.3-3734.6" + wire $0\ALU_dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:3456.7-3456.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:3783.3-3798.6" + wire width 3 $1\ALU_dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:3799.3-3814.6" + wire width 3 $1\ALU_dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:3847.3-3862.6" + wire width 2 $1\ALU_dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:3687.3-3702.6" + wire $1\ALU_dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:3639.3-3654.6" + wire width 12 $1\ALU_dec31_dec_sub26_function_unit[11:0] + attribute \src "libresoc.v:3751.3-3766.6" + wire width 3 $1\ALU_dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:3767.3-3782.6" + wire width 4 $1\ALU_dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:3735.3-3750.6" + wire width 7 $1\ALU_dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:3655.3-3670.6" + wire $1\ALU_dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:3671.3-3686.6" + wire $1\ALU_dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:3703.3-3718.6" + wire $1\ALU_dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:3815.3-3830.6" + wire width 4 $1\ALU_dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:3831.3-3846.6" + wire width 2 $1\ALU_dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:3719.3-3734.6" + wire $1\ALU_dec31_dec_sub26_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \ALU_dec31_dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 6 \ALU_dec31_dec_sub26_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 9 \ALU_dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 12 \ALU_dec31_dec_sub26_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \ALU_dec31_dec_sub26_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 3 \ALU_dec31_dec_sub26_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 4 \ALU_dec31_dec_sub26_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \ALU_dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 10 \ALU_dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 11 \ALU_dec31_dec_sub26_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 13 \ALU_dec31_dec_sub26_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 7 \ALU_dec31_dec_sub26_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \ALU_dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 14 \ALU_dec31_dec_sub26_sgn + attribute \src "libresoc.v:3456.7-3456.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:3456.7-3456.20" + process $proc$libresoc.v:3456$90 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:3639.3-3654.6" + process $proc$libresoc.v:3639$76 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_function_unit[11:0] $1\ALU_dec31_dec_sub26_function_unit[11:0] + attribute \src "libresoc.v:3640.5-3640.29" + switch \initial + attribute \src "libresoc.v:3640.9-3640.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_function_unit[11:0] 12'000000000010 + case + assign $1\ALU_dec31_dec_sub26_function_unit[11:0] 12'000000000000 + end + sync always + update \ALU_dec31_dec_sub26_function_unit $0\ALU_dec31_dec_sub26_function_unit[11:0] + end + attribute \src "libresoc.v:3655.3-3670.6" + process $proc$libresoc.v:3655$77 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_inv_a[0:0] $1\ALU_dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:3656.5-3656.29" + switch \initial + attribute \src "libresoc.v:3656.9-3656.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_inv_a[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub26_inv_a[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub26_inv_a $0\ALU_dec31_dec_sub26_inv_a[0:0] + end + attribute \src "libresoc.v:3671.3-3686.6" + process $proc$libresoc.v:3671$78 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_inv_out[0:0] $1\ALU_dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:3672.5-3672.29" + switch \initial + attribute \src "libresoc.v:3672.9-3672.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_inv_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub26_inv_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub26_inv_out $0\ALU_dec31_dec_sub26_inv_out[0:0] + end + attribute \src "libresoc.v:3687.3-3702.6" + process $proc$libresoc.v:3687$79 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_cry_out[0:0] $1\ALU_dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:3688.5-3688.29" + switch \initial + attribute \src "libresoc.v:3688.9-3688.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cry_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub26_cry_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub26_cry_out $0\ALU_dec31_dec_sub26_cry_out[0:0] + end + attribute \src "libresoc.v:3703.3-3718.6" + process $proc$libresoc.v:3703$80 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_is_32b[0:0] $1\ALU_dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:3704.5-3704.29" + switch \initial + attribute \src "libresoc.v:3704.9-3704.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_is_32b[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub26_is_32b[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub26_is_32b $0\ALU_dec31_dec_sub26_is_32b[0:0] + end + attribute \src "libresoc.v:3719.3-3734.6" + process $proc$libresoc.v:3719$81 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_sgn[0:0] $1\ALU_dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:3720.5-3720.29" + switch \initial + attribute \src "libresoc.v:3720.9-3720.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_sgn[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub26_sgn[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub26_sgn $0\ALU_dec31_dec_sub26_sgn[0:0] + end + attribute \src "libresoc.v:3735.3-3750.6" + process $proc$libresoc.v:3735$82 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_internal_op[6:0] $1\ALU_dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:3736.5-3736.29" + switch \initial + attribute \src "libresoc.v:3736.9-3736.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_internal_op[6:0] 7'0011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_internal_op[6:0] 7'0011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_internal_op[6:0] 7'0011111 + case + assign $1\ALU_dec31_dec_sub26_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_dec31_dec_sub26_internal_op $0\ALU_dec31_dec_sub26_internal_op[6:0] + end + attribute \src "libresoc.v:3751.3-3766.6" + process $proc$libresoc.v:3751$83 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_in1_sel[2:0] $1\ALU_dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:3752.5-3752.29" + switch \initial + attribute \src "libresoc.v:3752.9-3752.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_in1_sel[2:0] 3'100 + case + assign $1\ALU_dec31_dec_sub26_in1_sel[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub26_in1_sel $0\ALU_dec31_dec_sub26_in1_sel[2:0] + end + attribute \src "libresoc.v:3767.3-3782.6" + process $proc$libresoc.v:3767$84 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_in2_sel[3:0] $1\ALU_dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:3768.5-3768.29" + switch \initial + attribute \src "libresoc.v:3768.9-3768.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_in2_sel[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub26_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub26_in2_sel $0\ALU_dec31_dec_sub26_in2_sel[3:0] + end + attribute \src "libresoc.v:3783.3-3798.6" + process $proc$libresoc.v:3783$85 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_cr_in[2:0] $1\ALU_dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:3784.5-3784.29" + switch \initial + attribute \src "libresoc.v:3784.9-3784.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cr_in[2:0] 3'000 + case + assign $1\ALU_dec31_dec_sub26_cr_in[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub26_cr_in $0\ALU_dec31_dec_sub26_cr_in[2:0] + end + attribute \src "libresoc.v:3799.3-3814.6" + process $proc$libresoc.v:3799$86 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_cr_out[2:0] $1\ALU_dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:3800.5-3800.29" + switch \initial + attribute \src "libresoc.v:3800.9-3800.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cr_out[2:0] 3'001 + case + assign $1\ALU_dec31_dec_sub26_cr_out[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub26_cr_out $0\ALU_dec31_dec_sub26_cr_out[2:0] + end + attribute \src "libresoc.v:3815.3-3830.6" + process $proc$libresoc.v:3815$87 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_ldst_len[3:0] $1\ALU_dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:3816.5-3816.29" + switch \initial + attribute \src "libresoc.v:3816.9-3816.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_ldst_len[3:0] 4'0100 + case + assign $1\ALU_dec31_dec_sub26_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub26_ldst_len $0\ALU_dec31_dec_sub26_ldst_len[3:0] + end + attribute \src "libresoc.v:3831.3-3846.6" + process $proc$libresoc.v:3831$88 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_rc_sel[1:0] $1\ALU_dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:3832.5-3832.29" + switch \initial + attribute \src "libresoc.v:3832.9-3832.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_rc_sel[1:0] 2'10 + case + assign $1\ALU_dec31_dec_sub26_rc_sel[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub26_rc_sel $0\ALU_dec31_dec_sub26_rc_sel[1:0] + end + attribute \src "libresoc.v:3847.3-3862.6" + process $proc$libresoc.v:3847$89 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_cry_in[1:0] $1\ALU_dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:3848.5-3848.29" + switch \initial + attribute \src "libresoc.v:3848.9-3848.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cry_in[1:0] 2'00 + case + assign $1\ALU_dec31_dec_sub26_cry_in[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub26_cry_in $0\ALU_dec31_dec_sub26_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:3868.1-4655.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub8" +attribute \generator "nMigen" +module \ALU_dec31_dec_sub8 + attribute \src "libresoc.v:4439.3-4481.6" + wire width 3 $0\ALU_dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:4482.3-4524.6" + wire width 3 $0\ALU_dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:4611.3-4653.6" + wire width 2 $0\ALU_dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:4181.3-4223.6" + wire $0\ALU_dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:4052.3-4094.6" + wire width 12 $0\ALU_dec31_dec_sub8_function_unit[11:0] + attribute \src "libresoc.v:4353.3-4395.6" + wire width 3 $0\ALU_dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:4396.3-4438.6" + wire width 4 $0\ALU_dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:4310.3-4352.6" + wire width 7 $0\ALU_dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:4095.3-4137.6" + wire $0\ALU_dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:4138.3-4180.6" + wire $0\ALU_dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:4224.3-4266.6" + wire $0\ALU_dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:4525.3-4567.6" + wire width 4 $0\ALU_dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:4568.3-4610.6" + wire width 2 $0\ALU_dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:4267.3-4309.6" + wire $0\ALU_dec31_dec_sub8_sgn[0:0] + attribute \src "libresoc.v:3869.7-3869.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:4439.3-4481.6" + wire width 3 $1\ALU_dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:4482.3-4524.6" + wire width 3 $1\ALU_dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:4611.3-4653.6" + wire width 2 $1\ALU_dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:4181.3-4223.6" + wire $1\ALU_dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:4052.3-4094.6" + wire width 12 $1\ALU_dec31_dec_sub8_function_unit[11:0] + attribute \src "libresoc.v:4353.3-4395.6" + wire width 3 $1\ALU_dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:4396.3-4438.6" + wire width 4 $1\ALU_dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:4310.3-4352.6" + wire width 7 $1\ALU_dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:4095.3-4137.6" + wire $1\ALU_dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:4138.3-4180.6" + wire $1\ALU_dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:4224.3-4266.6" + wire $1\ALU_dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:4525.3-4567.6" + wire width 4 $1\ALU_dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:4568.3-4610.6" + wire width 2 $1\ALU_dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:4267.3-4309.6" + wire $1\ALU_dec31_dec_sub8_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \ALU_dec31_dec_sub8_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 6 \ALU_dec31_dec_sub8_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 9 \ALU_dec31_dec_sub8_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 12 \ALU_dec31_dec_sub8_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \ALU_dec31_dec_sub8_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 3 \ALU_dec31_dec_sub8_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 4 \ALU_dec31_dec_sub8_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \ALU_dec31_dec_sub8_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 10 \ALU_dec31_dec_sub8_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 11 \ALU_dec31_dec_sub8_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 13 \ALU_dec31_dec_sub8_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 7 \ALU_dec31_dec_sub8_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \ALU_dec31_dec_sub8_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 14 \ALU_dec31_dec_sub8_sgn + attribute \src "libresoc.v:3869.7-3869.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:3869.7-3869.20" + process $proc$libresoc.v:3869$105 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:4052.3-4094.6" + process $proc$libresoc.v:4052$91 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_function_unit[11:0] $1\ALU_dec31_dec_sub8_function_unit[11:0] + attribute \src "libresoc.v:4053.5-4053.29" + switch \initial + attribute \src "libresoc.v:4053.9-4053.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + case + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000000 + end + sync always + update \ALU_dec31_dec_sub8_function_unit $0\ALU_dec31_dec_sub8_function_unit[11:0] + end + attribute \src "libresoc.v:4095.3-4137.6" + process $proc$libresoc.v:4095$92 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_inv_a[0:0] $1\ALU_dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:4096.5-4096.29" + switch \initial + attribute \src "libresoc.v:4096.9-4096.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + case + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub8_inv_a $0\ALU_dec31_dec_sub8_inv_a[0:0] + end + attribute \src "libresoc.v:4138.3-4180.6" + process $proc$libresoc.v:4138$93 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_inv_out[0:0] $1\ALU_dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:4139.5-4139.29" + switch \initial + attribute \src "libresoc.v:4139.9-4139.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub8_inv_out $0\ALU_dec31_dec_sub8_inv_out[0:0] + end + attribute \src "libresoc.v:4181.3-4223.6" + process $proc$libresoc.v:4181$94 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_cry_out[0:0] $1\ALU_dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:4182.5-4182.29" + switch \initial + attribute \src "libresoc.v:4182.9-4182.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + case + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub8_cry_out $0\ALU_dec31_dec_sub8_cry_out[0:0] + end + attribute \src "libresoc.v:4224.3-4266.6" + process $proc$libresoc.v:4224$95 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_is_32b[0:0] $1\ALU_dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:4225.5-4225.29" + switch \initial + attribute \src "libresoc.v:4225.9-4225.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub8_is_32b $0\ALU_dec31_dec_sub8_is_32b[0:0] + end + attribute \src "libresoc.v:4267.3-4309.6" + process $proc$libresoc.v:4267$96 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_sgn[0:0] $1\ALU_dec31_dec_sub8_sgn[0:0] + attribute \src "libresoc.v:4268.5-4268.29" + switch \initial + attribute \src "libresoc.v:4268.9-4268.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub8_sgn $0\ALU_dec31_dec_sub8_sgn[0:0] + end + attribute \src "libresoc.v:4310.3-4352.6" + process $proc$libresoc.v:4310$97 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_internal_op[6:0] $1\ALU_dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:4311.5-4311.29" + switch \initial + attribute \src "libresoc.v:4311.9-4311.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + case + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_dec31_dec_sub8_internal_op $0\ALU_dec31_dec_sub8_internal_op[6:0] + end + attribute \src "libresoc.v:4353.3-4395.6" + process $proc$libresoc.v:4353$98 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_in1_sel[2:0] $1\ALU_dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:4354.5-4354.29" + switch \initial + attribute \src "libresoc.v:4354.9-4354.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + case + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub8_in1_sel $0\ALU_dec31_dec_sub8_in1_sel[2:0] + end + attribute \src "libresoc.v:4396.3-4438.6" + process $proc$libresoc.v:4396$99 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_in2_sel[3:0] $1\ALU_dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:4397.5-4397.29" + switch \initial + attribute \src "libresoc.v:4397.9-4397.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub8_in2_sel $0\ALU_dec31_dec_sub8_in2_sel[3:0] + end + attribute \src "libresoc.v:4439.3-4481.6" + process $proc$libresoc.v:4439$100 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_cr_in[2:0] $1\ALU_dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:4440.5-4440.29" + switch \initial + attribute \src "libresoc.v:4440.9-4440.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + case + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub8_cr_in $0\ALU_dec31_dec_sub8_cr_in[2:0] + end + attribute \src "libresoc.v:4482.3-4524.6" + process $proc$libresoc.v:4482$101 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_cr_out[2:0] $1\ALU_dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:4483.5-4483.29" + switch \initial + attribute \src "libresoc.v:4483.9-4483.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + case + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub8_cr_out $0\ALU_dec31_dec_sub8_cr_out[2:0] + end + attribute \src "libresoc.v:4525.3-4567.6" + process $proc$libresoc.v:4525$102 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_ldst_len[3:0] $1\ALU_dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:4526.5-4526.29" + switch \initial + attribute \src "libresoc.v:4526.9-4526.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub8_ldst_len $0\ALU_dec31_dec_sub8_ldst_len[3:0] + end + attribute \src "libresoc.v:4568.3-4610.6" + process $proc$libresoc.v:4568$103 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_rc_sel[1:0] $1\ALU_dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:4569.5-4569.29" + switch \initial + attribute \src "libresoc.v:4569.9-4569.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + case + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub8_rc_sel $0\ALU_dec31_dec_sub8_rc_sel[1:0] + end + attribute \src "libresoc.v:4611.3-4653.6" + process $proc$libresoc.v:4611$104 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_cry_in[1:0] $1\ALU_dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:4612.5-4612.29" + switch \initial + attribute \src "libresoc.v:4612.9-4612.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 + case + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub8_cry_in $0\ALU_dec31_dec_sub8_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:4659.1-4938.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec.BRANCH_dec19" +attribute \generator "nMigen" +module \BRANCH_dec19 + attribute \src "libresoc.v:4857.3-4872.6" + wire width 3 $0\BRANCH_dec19_cr_in[2:0] + attribute \src "libresoc.v:4873.3-4888.6" + wire width 3 $0\BRANCH_dec19_cr_out[2:0] + attribute \src "libresoc.v:4809.3-4824.6" + wire width 12 $0\BRANCH_dec19_function_unit[11:0] + attribute \src "libresoc.v:4841.3-4856.6" + wire width 4 $0\BRANCH_dec19_in2_sel[3:0] + attribute \src "libresoc.v:4825.3-4840.6" + wire width 7 $0\BRANCH_dec19_internal_op[6:0] + attribute \src "libresoc.v:4905.3-4920.6" + wire $0\BRANCH_dec19_is_32b[0:0] + attribute \src "libresoc.v:4921.3-4936.6" + wire $0\BRANCH_dec19_lk[0:0] + attribute \src "libresoc.v:4889.3-4904.6" + wire width 2 $0\BRANCH_dec19_rc_sel[1:0] + attribute \src "libresoc.v:4660.7-4660.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:4857.3-4872.6" + wire width 3 $1\BRANCH_dec19_cr_in[2:0] + attribute \src "libresoc.v:4873.3-4888.6" + wire width 3 $1\BRANCH_dec19_cr_out[2:0] + attribute \src "libresoc.v:4809.3-4824.6" + wire width 12 $1\BRANCH_dec19_function_unit[11:0] + attribute \src "libresoc.v:4841.3-4856.6" + wire width 4 $1\BRANCH_dec19_in2_sel[3:0] + attribute \src "libresoc.v:4825.3-4840.6" + wire width 7 $1\BRANCH_dec19_internal_op[6:0] + attribute \src "libresoc.v:4905.3-4920.6" + wire $1\BRANCH_dec19_is_32b[0:0] + attribute \src "libresoc.v:4921.3-4936.6" + wire $1\BRANCH_dec19_lk[0:0] + attribute \src "libresoc.v:4889.3-4904.6" + wire width 2 $1\BRANCH_dec19_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 4 \BRANCH_dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \BRANCH_dec19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \BRANCH_dec19_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 3 \BRANCH_dec19_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \BRANCH_dec19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 7 \BRANCH_dec19_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 8 \BRANCH_dec19_lk + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 6 \BRANCH_dec19_rc_sel + attribute \src "libresoc.v:4660.7-4660.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 9 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 10 \opcode_switch + attribute \src "libresoc.v:4660.7-4660.20" + process $proc$libresoc.v:4660$114 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:4809.3-4824.6" + process $proc$libresoc.v:4809$106 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_function_unit[11:0] $1\BRANCH_dec19_function_unit[11:0] + attribute \src "libresoc.v:4810.5-4810.29" + switch \initial + attribute \src "libresoc.v:4810.9-4810.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_function_unit[11:0] 12'000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_function_unit[11:0] 12'000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_function_unit[11:0] 12'000000100000 + case + assign $1\BRANCH_dec19_function_unit[11:0] 12'000000000000 + end + sync always + update \BRANCH_dec19_function_unit $0\BRANCH_dec19_function_unit[11:0] + end + attribute \src "libresoc.v:4825.3-4840.6" + process $proc$libresoc.v:4825$107 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_internal_op[6:0] $1\BRANCH_dec19_internal_op[6:0] + attribute \src "libresoc.v:4826.5-4826.29" + switch \initial + attribute \src "libresoc.v:4826.9-4826.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_internal_op[6:0] 7'0001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_internal_op[6:0] 7'0001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_internal_op[6:0] 7'0001000 + case + assign $1\BRANCH_dec19_internal_op[6:0] 7'0000000 + end + sync always + update \BRANCH_dec19_internal_op $0\BRANCH_dec19_internal_op[6:0] + end + attribute \src "libresoc.v:4841.3-4856.6" + process $proc$libresoc.v:4841$108 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_in2_sel[3:0] $1\BRANCH_dec19_in2_sel[3:0] + attribute \src "libresoc.v:4842.5-4842.29" + switch \initial + attribute \src "libresoc.v:4842.9-4842.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_in2_sel[3:0] 4'1100 + case + assign $1\BRANCH_dec19_in2_sel[3:0] 4'0000 + end + sync always + update \BRANCH_dec19_in2_sel $0\BRANCH_dec19_in2_sel[3:0] + end + attribute \src "libresoc.v:4857.3-4872.6" + process $proc$libresoc.v:4857$109 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_cr_in[2:0] $1\BRANCH_dec19_cr_in[2:0] + attribute \src "libresoc.v:4858.5-4858.29" + switch \initial + attribute \src "libresoc.v:4858.9-4858.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_cr_in[2:0] 3'010 + case + assign $1\BRANCH_dec19_cr_in[2:0] 3'000 + end + sync always + update \BRANCH_dec19_cr_in $0\BRANCH_dec19_cr_in[2:0] + end + attribute \src "libresoc.v:4873.3-4888.6" + process $proc$libresoc.v:4873$110 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_cr_out[2:0] $1\BRANCH_dec19_cr_out[2:0] + attribute \src "libresoc.v:4874.5-4874.29" + switch \initial + attribute \src "libresoc.v:4874.9-4874.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_cr_out[2:0] 3'000 + case + assign $1\BRANCH_dec19_cr_out[2:0] 3'000 + end + sync always + update \BRANCH_dec19_cr_out $0\BRANCH_dec19_cr_out[2:0] + end + attribute \src "libresoc.v:4889.3-4904.6" + process $proc$libresoc.v:4889$111 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_rc_sel[1:0] $1\BRANCH_dec19_rc_sel[1:0] + attribute \src "libresoc.v:4890.5-4890.29" + switch \initial + attribute \src "libresoc.v:4890.9-4890.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_rc_sel[1:0] 2'00 + case + assign $1\BRANCH_dec19_rc_sel[1:0] 2'00 + end + sync always + update \BRANCH_dec19_rc_sel $0\BRANCH_dec19_rc_sel[1:0] + end + attribute \src "libresoc.v:4905.3-4920.6" + process $proc$libresoc.v:4905$112 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_is_32b[0:0] $1\BRANCH_dec19_is_32b[0:0] + attribute \src "libresoc.v:4906.5-4906.29" + switch \initial + attribute \src "libresoc.v:4906.9-4906.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_is_32b[0:0] 1'0 + case + assign $1\BRANCH_dec19_is_32b[0:0] 1'0 + end + sync always + update \BRANCH_dec19_is_32b $0\BRANCH_dec19_is_32b[0:0] + end + attribute \src "libresoc.v:4921.3-4936.6" + process $proc$libresoc.v:4921$113 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_lk[0:0] $1\BRANCH_dec19_lk[0:0] + attribute \src "libresoc.v:4922.5-4922.29" + switch \initial + attribute \src "libresoc.v:4922.9-4922.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_lk[0:0] 1'1 + case + assign $1\BRANCH_dec19_lk[0:0] 1'0 + end + sync always + update \BRANCH_dec19_lk $0\BRANCH_dec19_lk[0:0] + end + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:4942.1-5239.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec19" +attribute \generator "nMigen" +module \CR_dec19 + attribute \src "libresoc.v:5136.3-5169.6" + wire width 3 $0\CR_dec19_cr_in[2:0] + attribute \src "libresoc.v:5170.3-5203.6" + wire width 3 $0\CR_dec19_cr_out[2:0] + attribute \src "libresoc.v:5068.3-5101.6" + wire width 12 $0\CR_dec19_function_unit[11:0] + attribute \src "libresoc.v:5102.3-5135.6" + wire width 7 $0\CR_dec19_internal_op[6:0] + attribute \src "libresoc.v:5204.3-5237.6" + wire width 2 $0\CR_dec19_rc_sel[1:0] + attribute \src "libresoc.v:4943.7-4943.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:5136.3-5169.6" + wire width 3 $1\CR_dec19_cr_in[2:0] + attribute \src "libresoc.v:5170.3-5203.6" + wire width 3 $1\CR_dec19_cr_out[2:0] + attribute \src "libresoc.v:5068.3-5101.6" + wire width 12 $1\CR_dec19_function_unit[11:0] + attribute \src "libresoc.v:5102.3-5135.6" + wire width 7 $1\CR_dec19_internal_op[6:0] + attribute \src "libresoc.v:5204.3-5237.6" + wire width 2 $1\CR_dec19_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 3 \CR_dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 4 \CR_dec19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \CR_dec19_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \CR_dec19_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 5 \CR_dec19_rc_sel + attribute \src "libresoc.v:4943.7-4943.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 6 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 10 \opcode_switch + attribute \src "libresoc.v:4943.7-4943.20" + process $proc$libresoc.v:4943$120 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:5068.3-5101.6" + process $proc$libresoc.v:5068$115 + assign { } { } + assign { } { } + assign $0\CR_dec19_function_unit[11:0] $1\CR_dec19_function_unit[11:0] + attribute \src "libresoc.v:5069.5-5069.29" + switch \initial + attribute \src "libresoc.v:5069.9-5069.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\CR_dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\CR_dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\CR_dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\CR_dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\CR_dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\CR_dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\CR_dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\CR_dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\CR_dec19_function_unit[11:0] 12'000001000000 + case + assign $1\CR_dec19_function_unit[11:0] 12'000000000000 + end + sync always + update \CR_dec19_function_unit $0\CR_dec19_function_unit[11:0] + end + attribute \src "libresoc.v:5102.3-5135.6" + process $proc$libresoc.v:5102$116 + assign { } { } + assign { } { } + assign $0\CR_dec19_internal_op[6:0] $1\CR_dec19_internal_op[6:0] + attribute \src "libresoc.v:5103.5-5103.29" + switch \initial + attribute \src "libresoc.v:5103.9-5103.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'0101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + case + assign $1\CR_dec19_internal_op[6:0] 7'0000000 + end + sync always + update \CR_dec19_internal_op $0\CR_dec19_internal_op[6:0] + end + attribute \src "libresoc.v:5136.3-5169.6" + process $proc$libresoc.v:5136$117 + assign { } { } + assign { } { } + assign $0\CR_dec19_cr_in[2:0] $1\CR_dec19_cr_in[2:0] + attribute \src "libresoc.v:5137.5-5137.29" + switch \initial + attribute \src "libresoc.v:5137.9-5137.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + case + assign $1\CR_dec19_cr_in[2:0] 3'000 + end + sync always + update \CR_dec19_cr_in $0\CR_dec19_cr_in[2:0] + end + attribute \src "libresoc.v:5170.3-5203.6" + process $proc$libresoc.v:5170$118 + assign { } { } + assign { } { } + assign $0\CR_dec19_cr_out[2:0] $1\CR_dec19_cr_out[2:0] + attribute \src "libresoc.v:5171.5-5171.29" + switch \initial + attribute \src "libresoc.v:5171.9-5171.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + case + assign $1\CR_dec19_cr_out[2:0] 3'000 + end + sync always + update \CR_dec19_cr_out $0\CR_dec19_cr_out[2:0] + end + attribute \src "libresoc.v:5204.3-5237.6" + process $proc$libresoc.v:5204$119 + assign { } { } + assign { } { } + assign $0\CR_dec19_rc_sel[1:0] $1\CR_dec19_rc_sel[1:0] + attribute \src "libresoc.v:5205.5-5205.29" + switch \initial + attribute \src "libresoc.v:5205.9-5205.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + case + assign $1\CR_dec19_rc_sel[1:0] 2'00 + end + sync always + update \CR_dec19_rc_sel $0\CR_dec19_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:5243.1-5972.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31" +attribute \generator "nMigen" +module \CR_dec31 + attribute \src "libresoc.v:5928.3-5946.6" + wire width 3 $0\CR_dec31_cr_in[2:0] + attribute \src "libresoc.v:5947.3-5965.6" + wire width 3 $0\CR_dec31_cr_out[2:0] + attribute \src "libresoc.v:5890.3-5908.6" + wire width 12 $0\CR_dec31_function_unit[11:0] + attribute \src "libresoc.v:5909.3-5927.6" + wire width 7 $0\CR_dec31_internal_op[6:0] + attribute \src "libresoc.v:5871.3-5889.6" + wire width 2 $0\CR_dec31_rc_sel[1:0] + attribute \src "libresoc.v:5244.7-5244.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:5928.3-5946.6" + wire width 3 $1\CR_dec31_cr_in[2:0] + attribute \src "libresoc.v:5947.3-5965.6" + wire width 3 $1\CR_dec31_cr_out[2:0] + attribute \src "libresoc.v:5890.3-5908.6" + wire width 12 $1\CR_dec31_function_unit[11:0] + attribute \src "libresoc.v:5909.3-5927.6" + wire width 7 $1\CR_dec31_internal_op[6:0] + attribute \src "libresoc.v:5871.3-5889.6" + wire width 2 $1\CR_dec31_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 3 \CR_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 4 \CR_dec31_cr_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \CR_dec31_dec_sub0_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \CR_dec31_dec_sub15_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \CR_dec31_dec_sub16_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \CR_dec31_dec_sub19_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \CR_dec31_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \CR_dec31_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 5 \CR_dec31_rc_sel + attribute \src "libresoc.v:5244.7-5244.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 6 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:5839.21-5846.4" + cell \CR_dec31_dec_sub0 \CR_dec31_dec_sub0 + connect \CR_dec31_dec_sub0_cr_in \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in + connect \CR_dec31_dec_sub0_cr_out \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out + connect \CR_dec31_dec_sub0_function_unit \CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit + connect \CR_dec31_dec_sub0_internal_op \CR_dec31_dec_sub0_CR_dec31_dec_sub0_internal_op + connect \CR_dec31_dec_sub0_rc_sel \CR_dec31_dec_sub0_CR_dec31_dec_sub0_rc_sel + connect \opcode_in \CR_dec31_dec_sub0_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:5847.22-5854.4" + cell \CR_dec31_dec_sub15 \CR_dec31_dec_sub15 + connect \CR_dec31_dec_sub15_cr_in \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in + connect \CR_dec31_dec_sub15_cr_out \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out + connect \CR_dec31_dec_sub15_function_unit \CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit + connect \CR_dec31_dec_sub15_internal_op \CR_dec31_dec_sub15_CR_dec31_dec_sub15_internal_op + connect \CR_dec31_dec_sub15_rc_sel \CR_dec31_dec_sub15_CR_dec31_dec_sub15_rc_sel + connect \opcode_in \CR_dec31_dec_sub15_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:5855.22-5862.4" + cell \CR_dec31_dec_sub16 \CR_dec31_dec_sub16 + connect \CR_dec31_dec_sub16_cr_in \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in + connect \CR_dec31_dec_sub16_cr_out \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out + connect \CR_dec31_dec_sub16_function_unit \CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit + connect \CR_dec31_dec_sub16_internal_op \CR_dec31_dec_sub16_CR_dec31_dec_sub16_internal_op + connect \CR_dec31_dec_sub16_rc_sel \CR_dec31_dec_sub16_CR_dec31_dec_sub16_rc_sel + connect \opcode_in \CR_dec31_dec_sub16_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:5863.22-5870.4" + cell \CR_dec31_dec_sub19 \CR_dec31_dec_sub19 + connect \CR_dec31_dec_sub19_cr_in \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in + connect \CR_dec31_dec_sub19_cr_out \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out + connect \CR_dec31_dec_sub19_function_unit \CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit + connect \CR_dec31_dec_sub19_internal_op \CR_dec31_dec_sub19_CR_dec31_dec_sub19_internal_op + connect \CR_dec31_dec_sub19_rc_sel \CR_dec31_dec_sub19_CR_dec31_dec_sub19_rc_sel + connect \opcode_in \CR_dec31_dec_sub19_opcode_in + end + attribute \src "libresoc.v:5244.7-5244.20" + process $proc$libresoc.v:5244$126 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:5871.3-5889.6" + process $proc$libresoc.v:5871$121 + assign { } { } + assign { } { } + assign $0\CR_dec31_rc_sel[1:0] $1\CR_dec31_rc_sel[1:0] + attribute \src "libresoc.v:5872.5-5872.29" + switch \initial + attribute \src "libresoc.v:5872.9-5872.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_rc_sel[1:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_rc_sel[1:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_rc_sel[1:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_rc_sel[1:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_rc_sel + case + assign $1\CR_dec31_rc_sel[1:0] 2'00 + end + sync always + update \CR_dec31_rc_sel $0\CR_dec31_rc_sel[1:0] + end + attribute \src "libresoc.v:5890.3-5908.6" + process $proc$libresoc.v:5890$122 + assign { } { } + assign { } { } + assign $0\CR_dec31_function_unit[11:0] $1\CR_dec31_function_unit[11:0] + attribute \src "libresoc.v:5891.5-5891.29" + switch \initial + attribute \src "libresoc.v:5891.9-5891.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_function_unit[11:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_function_unit[11:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_function_unit[11:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_function_unit[11:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit + case + assign $1\CR_dec31_function_unit[11:0] 12'000000000000 + end + sync always + update \CR_dec31_function_unit $0\CR_dec31_function_unit[11:0] + end + attribute \src "libresoc.v:5909.3-5927.6" + process $proc$libresoc.v:5909$123 + assign { } { } + assign { } { } + assign $0\CR_dec31_internal_op[6:0] $1\CR_dec31_internal_op[6:0] + attribute \src "libresoc.v:5910.5-5910.29" + switch \initial + attribute \src "libresoc.v:5910.9-5910.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_internal_op[6:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_internal_op[6:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_internal_op[6:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_internal_op[6:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_internal_op + case + assign $1\CR_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \CR_dec31_internal_op $0\CR_dec31_internal_op[6:0] + end + attribute \src "libresoc.v:5928.3-5946.6" + process $proc$libresoc.v:5928$124 + assign { } { } + assign { } { } + assign $0\CR_dec31_cr_in[2:0] $1\CR_dec31_cr_in[2:0] + attribute \src "libresoc.v:5929.5-5929.29" + switch \initial + attribute \src "libresoc.v:5929.9-5929.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_cr_in[2:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_cr_in[2:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_cr_in[2:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_cr_in[2:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in + case + assign $1\CR_dec31_cr_in[2:0] 3'000 + end + sync always + update \CR_dec31_cr_in $0\CR_dec31_cr_in[2:0] + end + attribute \src "libresoc.v:5947.3-5965.6" + process $proc$libresoc.v:5947$125 + assign { } { } + assign { } { } + assign $0\CR_dec31_cr_out[2:0] $1\CR_dec31_cr_out[2:0] + attribute \src "libresoc.v:5948.5-5948.29" + switch \initial + attribute \src "libresoc.v:5948.9-5948.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_cr_out[2:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_cr_out[2:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_cr_out[2:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_cr_out[2:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out + case + assign $1\CR_dec31_cr_out[2:0] 3'000 + end + sync always + update \CR_dec31_cr_out $0\CR_dec31_cr_out[2:0] + end + connect \CR_dec31_dec_sub16_opcode_in \opcode_in + connect \CR_dec31_dec_sub15_opcode_in \opcode_in + connect \CR_dec31_dec_sub19_opcode_in \opcode_in + connect \CR_dec31_dec_sub0_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:5976.1-6153.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub0" +attribute \generator "nMigen" +module \CR_dec31_dec_sub0 + attribute \src "libresoc.v:6122.3-6131.6" + wire width 3 $0\CR_dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:6132.3-6141.6" + wire width 3 $0\CR_dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:6102.3-6111.6" + wire width 12 $0\CR_dec31_dec_sub0_function_unit[11:0] + attribute \src "libresoc.v:6112.3-6121.6" + wire width 7 $0\CR_dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:6142.3-6151.6" + wire width 2 $0\CR_dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:5977.7-5977.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:6122.3-6131.6" + wire width 3 $1\CR_dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:6132.3-6141.6" + wire width 3 $1\CR_dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:6102.3-6111.6" + wire width 12 $1\CR_dec31_dec_sub0_function_unit[11:0] + attribute \src "libresoc.v:6112.3-6121.6" + wire width 7 $1\CR_dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:6142.3-6151.6" + wire width 2 $1\CR_dec31_dec_sub0_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 3 \CR_dec31_dec_sub0_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 4 \CR_dec31_dec_sub0_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \CR_dec31_dec_sub0_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \CR_dec31_dec_sub0_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 5 \CR_dec31_dec_sub0_rc_sel + attribute \src "libresoc.v:5977.7-5977.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 6 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:5977.7-5977.20" + process $proc$libresoc.v:5977$132 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:6102.3-6111.6" + process $proc$libresoc.v:6102$127 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub0_function_unit[11:0] $1\CR_dec31_dec_sub0_function_unit[11:0] + attribute \src "libresoc.v:6103.5-6103.29" + switch \initial + attribute \src "libresoc.v:6103.9-6103.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub0_function_unit[11:0] 12'000001000000 + case + assign $1\CR_dec31_dec_sub0_function_unit[11:0] 12'000000000000 + end + sync always + update \CR_dec31_dec_sub0_function_unit $0\CR_dec31_dec_sub0_function_unit[11:0] + end + attribute \src "libresoc.v:6112.3-6121.6" + process $proc$libresoc.v:6112$128 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub0_internal_op[6:0] $1\CR_dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:6113.5-6113.29" + switch \initial + attribute \src "libresoc.v:6113.9-6113.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub0_internal_op[6:0] 7'0111011 + case + assign $1\CR_dec31_dec_sub0_internal_op[6:0] 7'0000000 + end + sync always + update \CR_dec31_dec_sub0_internal_op $0\CR_dec31_dec_sub0_internal_op[6:0] + end + attribute \src "libresoc.v:6122.3-6131.6" + process $proc$libresoc.v:6122$129 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub0_cr_in[2:0] $1\CR_dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:6123.5-6123.29" + switch \initial + attribute \src "libresoc.v:6123.9-6123.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub0_cr_in[2:0] 3'011 + case + assign $1\CR_dec31_dec_sub0_cr_in[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub0_cr_in $0\CR_dec31_dec_sub0_cr_in[2:0] + end + attribute \src "libresoc.v:6132.3-6141.6" + process $proc$libresoc.v:6132$130 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub0_cr_out[2:0] $1\CR_dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:6133.5-6133.29" + switch \initial + attribute \src "libresoc.v:6133.9-6133.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub0_cr_out[2:0] 3'000 + case + assign $1\CR_dec31_dec_sub0_cr_out[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub0_cr_out $0\CR_dec31_dec_sub0_cr_out[2:0] + end + attribute \src "libresoc.v:6142.3-6151.6" + process $proc$libresoc.v:6142$131 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub0_rc_sel[1:0] $1\CR_dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:6143.5-6143.29" + switch \initial + attribute \src "libresoc.v:6143.9-6143.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub0_rc_sel[1:0] 2'00 + case + assign $1\CR_dec31_dec_sub0_rc_sel[1:0] 2'00 + end + sync always + update \CR_dec31_dec_sub0_rc_sel $0\CR_dec31_dec_sub0_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:6157.1-6799.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub15" +attribute \generator "nMigen" +module \CR_dec31_dec_sub15 + attribute \src "libresoc.v:6489.3-6591.6" + wire width 3 $0\CR_dec31_dec_sub15_cr_in[2:0] + attribute \src "libresoc.v:6592.3-6694.6" + wire width 3 $0\CR_dec31_dec_sub15_cr_out[2:0] + attribute \src "libresoc.v:6283.3-6385.6" + wire width 12 $0\CR_dec31_dec_sub15_function_unit[11:0] + attribute \src "libresoc.v:6386.3-6488.6" + wire width 7 $0\CR_dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:6695.3-6797.6" + wire width 2 $0\CR_dec31_dec_sub15_rc_sel[1:0] + attribute \src "libresoc.v:6158.7-6158.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:6489.3-6591.6" + wire width 3 $1\CR_dec31_dec_sub15_cr_in[2:0] + attribute \src "libresoc.v:6592.3-6694.6" + wire width 3 $1\CR_dec31_dec_sub15_cr_out[2:0] + attribute \src "libresoc.v:6283.3-6385.6" + wire width 12 $1\CR_dec31_dec_sub15_function_unit[11:0] + attribute \src "libresoc.v:6386.3-6488.6" + wire width 7 $1\CR_dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:6695.3-6797.6" + wire width 2 $1\CR_dec31_dec_sub15_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 3 \CR_dec31_dec_sub15_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 4 \CR_dec31_dec_sub15_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \CR_dec31_dec_sub15_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \CR_dec31_dec_sub15_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 5 \CR_dec31_dec_sub15_rc_sel + attribute \src "libresoc.v:6158.7-6158.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 6 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:6158.7-6158.20" + process $proc$libresoc.v:6158$138 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:6283.3-6385.6" + process $proc$libresoc.v:6283$133 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub15_function_unit[11:0] $1\CR_dec31_dec_sub15_function_unit[11:0] + attribute \src "libresoc.v:6284.5-6284.29" + switch \initial + attribute \src "libresoc.v:6284.9-6284.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + case + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000000000000 + end + sync always + update \CR_dec31_dec_sub15_function_unit $0\CR_dec31_dec_sub15_function_unit[11:0] + end + attribute \src "libresoc.v:6386.3-6488.6" + process $proc$libresoc.v:6386$134 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub15_internal_op[6:0] $1\CR_dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:6387.5-6387.29" + switch \initial + attribute \src "libresoc.v:6387.9-6387.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + case + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0000000 + end + sync always + update \CR_dec31_dec_sub15_internal_op $0\CR_dec31_dec_sub15_internal_op[6:0] + end + attribute \src "libresoc.v:6489.3-6591.6" + process $proc$libresoc.v:6489$135 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub15_cr_in[2:0] $1\CR_dec31_dec_sub15_cr_in[2:0] + attribute \src "libresoc.v:6490.5-6490.29" + switch \initial + attribute \src "libresoc.v:6490.9-6490.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + case + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub15_cr_in $0\CR_dec31_dec_sub15_cr_in[2:0] + end + attribute \src "libresoc.v:6592.3-6694.6" + process $proc$libresoc.v:6592$136 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub15_cr_out[2:0] $1\CR_dec31_dec_sub15_cr_out[2:0] + attribute \src "libresoc.v:6593.5-6593.29" + switch \initial + attribute \src "libresoc.v:6593.9-6593.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + case + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub15_cr_out $0\CR_dec31_dec_sub15_cr_out[2:0] + end + attribute \src "libresoc.v:6695.3-6797.6" + process $proc$libresoc.v:6695$137 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub15_rc_sel[1:0] $1\CR_dec31_dec_sub15_rc_sel[1:0] + attribute \src "libresoc.v:6696.5-6696.29" + switch \initial + attribute \src "libresoc.v:6696.9-6696.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + case + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + end + sync always + update \CR_dec31_dec_sub15_rc_sel $0\CR_dec31_dec_sub15_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:6803.1-6980.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub16" +attribute \generator "nMigen" +module \CR_dec31_dec_sub16 + attribute \src "libresoc.v:6949.3-6958.6" + wire width 3 $0\CR_dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:6959.3-6968.6" + wire width 3 $0\CR_dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:6929.3-6938.6" + wire width 12 $0\CR_dec31_dec_sub16_function_unit[11:0] + attribute \src "libresoc.v:6939.3-6948.6" + wire width 7 $0\CR_dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:6969.3-6978.6" + wire width 2 $0\CR_dec31_dec_sub16_rc_sel[1:0] + attribute \src "libresoc.v:6804.7-6804.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:6949.3-6958.6" + wire width 3 $1\CR_dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:6959.3-6968.6" + wire width 3 $1\CR_dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:6929.3-6938.6" + wire width 12 $1\CR_dec31_dec_sub16_function_unit[11:0] + attribute \src "libresoc.v:6939.3-6948.6" + wire width 7 $1\CR_dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:6969.3-6978.6" + wire width 2 $1\CR_dec31_dec_sub16_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 3 \CR_dec31_dec_sub16_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 4 \CR_dec31_dec_sub16_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \CR_dec31_dec_sub16_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \CR_dec31_dec_sub16_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 5 \CR_dec31_dec_sub16_rc_sel + attribute \src "libresoc.v:6804.7-6804.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 6 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:6804.7-6804.20" + process $proc$libresoc.v:6804$144 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:6929.3-6938.6" + process $proc$libresoc.v:6929$139 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub16_function_unit[11:0] $1\CR_dec31_dec_sub16_function_unit[11:0] + attribute \src "libresoc.v:6930.5-6930.29" + switch \initial + attribute \src "libresoc.v:6930.9-6930.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub16_function_unit[11:0] 12'000001000000 + case + assign $1\CR_dec31_dec_sub16_function_unit[11:0] 12'000000000000 + end + sync always + update \CR_dec31_dec_sub16_function_unit $0\CR_dec31_dec_sub16_function_unit[11:0] + end + attribute \src "libresoc.v:6939.3-6948.6" + process $proc$libresoc.v:6939$140 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub16_internal_op[6:0] $1\CR_dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:6940.5-6940.29" + switch \initial + attribute \src "libresoc.v:6940.9-6940.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub16_internal_op[6:0] 7'0110000 + case + assign $1\CR_dec31_dec_sub16_internal_op[6:0] 7'0000000 + end + sync always + update \CR_dec31_dec_sub16_internal_op $0\CR_dec31_dec_sub16_internal_op[6:0] + end + attribute \src "libresoc.v:6949.3-6958.6" + process $proc$libresoc.v:6949$141 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub16_cr_in[2:0] $1\CR_dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:6950.5-6950.29" + switch \initial + attribute \src "libresoc.v:6950.9-6950.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub16_cr_in[2:0] 3'110 + case + assign $1\CR_dec31_dec_sub16_cr_in[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub16_cr_in $0\CR_dec31_dec_sub16_cr_in[2:0] + end + attribute \src "libresoc.v:6959.3-6968.6" + process $proc$libresoc.v:6959$142 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub16_cr_out[2:0] $1\CR_dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:6960.5-6960.29" + switch \initial + attribute \src "libresoc.v:6960.9-6960.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub16_cr_out[2:0] 3'100 + case + assign $1\CR_dec31_dec_sub16_cr_out[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub16_cr_out $0\CR_dec31_dec_sub16_cr_out[2:0] + end + attribute \src "libresoc.v:6969.3-6978.6" + process $proc$libresoc.v:6969$143 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub16_rc_sel[1:0] $1\CR_dec31_dec_sub16_rc_sel[1:0] + attribute \src "libresoc.v:6970.5-6970.29" + switch \initial + attribute \src "libresoc.v:6970.9-6970.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub16_rc_sel[1:0] 2'00 + case + assign $1\CR_dec31_dec_sub16_rc_sel[1:0] 2'00 + end + sync always + update \CR_dec31_dec_sub16_rc_sel $0\CR_dec31_dec_sub16_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:6984.1-7161.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub19" +attribute \generator "nMigen" +module \CR_dec31_dec_sub19 + attribute \src "libresoc.v:7130.3-7139.6" + wire width 3 $0\CR_dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:7140.3-7149.6" + wire width 3 $0\CR_dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:7110.3-7119.6" + wire width 12 $0\CR_dec31_dec_sub19_function_unit[11:0] + attribute \src "libresoc.v:7120.3-7129.6" + wire width 7 $0\CR_dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:7150.3-7159.6" + wire width 2 $0\CR_dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:6985.7-6985.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:7130.3-7139.6" + wire width 3 $1\CR_dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:7140.3-7149.6" + wire width 3 $1\CR_dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:7110.3-7119.6" + wire width 12 $1\CR_dec31_dec_sub19_function_unit[11:0] + attribute \src "libresoc.v:7120.3-7129.6" + wire width 7 $1\CR_dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:7150.3-7159.6" + wire width 2 $1\CR_dec31_dec_sub19_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 3 \CR_dec31_dec_sub19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 4 \CR_dec31_dec_sub19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \CR_dec31_dec_sub19_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \CR_dec31_dec_sub19_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 5 \CR_dec31_dec_sub19_rc_sel + attribute \src "libresoc.v:6985.7-6985.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 6 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:6985.7-6985.20" + process $proc$libresoc.v:6985$150 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:7110.3-7119.6" + process $proc$libresoc.v:7110$145 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub19_function_unit[11:0] $1\CR_dec31_dec_sub19_function_unit[11:0] + attribute \src "libresoc.v:7111.5-7111.29" + switch \initial + attribute \src "libresoc.v:7111.9-7111.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub19_function_unit[11:0] 12'000001000000 + case + assign $1\CR_dec31_dec_sub19_function_unit[11:0] 12'000000000000 + end + sync always + update \CR_dec31_dec_sub19_function_unit $0\CR_dec31_dec_sub19_function_unit[11:0] + end + attribute \src "libresoc.v:7120.3-7129.6" + process $proc$libresoc.v:7120$146 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub19_internal_op[6:0] $1\CR_dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:7121.5-7121.29" + switch \initial + attribute \src "libresoc.v:7121.9-7121.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub19_internal_op[6:0] 7'0101101 + case + assign $1\CR_dec31_dec_sub19_internal_op[6:0] 7'0000000 + end + sync always + update \CR_dec31_dec_sub19_internal_op $0\CR_dec31_dec_sub19_internal_op[6:0] + end + attribute \src "libresoc.v:7130.3-7139.6" + process $proc$libresoc.v:7130$147 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub19_cr_in[2:0] $1\CR_dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:7131.5-7131.29" + switch \initial + attribute \src "libresoc.v:7131.9-7131.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub19_cr_in[2:0] 3'110 + case + assign $1\CR_dec31_dec_sub19_cr_in[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub19_cr_in $0\CR_dec31_dec_sub19_cr_in[2:0] + end + attribute \src "libresoc.v:7140.3-7149.6" + process $proc$libresoc.v:7140$148 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub19_cr_out[2:0] $1\CR_dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:7141.5-7141.29" + switch \initial + attribute \src "libresoc.v:7141.9-7141.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub19_cr_out[2:0] 3'000 + case + assign $1\CR_dec31_dec_sub19_cr_out[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub19_cr_out $0\CR_dec31_dec_sub19_cr_out[2:0] + end + attribute \src "libresoc.v:7150.3-7159.6" + process $proc$libresoc.v:7150$149 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub19_rc_sel[1:0] $1\CR_dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:7151.5-7151.29" + switch \initial + attribute \src "libresoc.v:7151.9-7151.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub19_rc_sel[1:0] 2'00 + case + assign $1\CR_dec31_dec_sub19_rc_sel[1:0] 2'00 + end + sync always + update \CR_dec31_dec_sub19_rc_sel $0\CR_dec31_dec_sub19_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:7165.1-7903.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec.DIV_dec31" +attribute \generator "nMigen" +module \DIV_dec31 + attribute \src "libresoc.v:7873.3-7885.6" + wire width 3 $0\DIV_dec31_cr_in[2:0] + attribute \src "libresoc.v:7886.3-7898.6" + wire width 3 $0\DIV_dec31_cr_out[2:0] + attribute \src "libresoc.v:7743.3-7755.6" + wire width 2 $0\DIV_dec31_cry_in[1:0] + attribute \src "libresoc.v:7782.3-7794.6" + wire $0\DIV_dec31_cry_out[0:0] + attribute \src "libresoc.v:7821.3-7833.6" + wire width 12 $0\DIV_dec31_function_unit[11:0] + attribute \src "libresoc.v:7847.3-7859.6" + wire width 3 $0\DIV_dec31_in1_sel[2:0] + attribute \src "libresoc.v:7860.3-7872.6" + wire width 4 $0\DIV_dec31_in2_sel[3:0] + attribute \src "libresoc.v:7834.3-7846.6" + wire width 7 $0\DIV_dec31_internal_op[6:0] + attribute \src "libresoc.v:7756.3-7768.6" + wire $0\DIV_dec31_inv_a[0:0] + attribute \src "libresoc.v:7769.3-7781.6" + wire $0\DIV_dec31_inv_out[0:0] + attribute \src "libresoc.v:7795.3-7807.6" + wire $0\DIV_dec31_is_32b[0:0] + attribute \src "libresoc.v:7717.3-7729.6" + wire width 4 $0\DIV_dec31_ldst_len[3:0] + attribute \src "libresoc.v:7730.3-7742.6" + wire width 2 $0\DIV_dec31_rc_sel[1:0] + attribute \src "libresoc.v:7808.3-7820.6" + wire $0\DIV_dec31_sgn[0:0] + attribute \src "libresoc.v:7166.7-7166.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:7873.3-7885.6" + wire width 3 $1\DIV_dec31_cr_in[2:0] + attribute \src "libresoc.v:7886.3-7898.6" + wire width 3 $1\DIV_dec31_cr_out[2:0] + attribute \src "libresoc.v:7743.3-7755.6" + wire width 2 $1\DIV_dec31_cry_in[1:0] + attribute \src "libresoc.v:7782.3-7794.6" + wire $1\DIV_dec31_cry_out[0:0] + attribute \src "libresoc.v:7821.3-7833.6" + wire width 12 $1\DIV_dec31_function_unit[11:0] + attribute \src "libresoc.v:7847.3-7859.6" + wire width 3 $1\DIV_dec31_in1_sel[2:0] + attribute \src "libresoc.v:7860.3-7872.6" + wire width 4 $1\DIV_dec31_in2_sel[3:0] + attribute \src "libresoc.v:7834.3-7846.6" + wire width 7 $1\DIV_dec31_internal_op[6:0] + attribute \src "libresoc.v:7756.3-7768.6" + wire $1\DIV_dec31_inv_a[0:0] + attribute \src "libresoc.v:7769.3-7781.6" + wire $1\DIV_dec31_inv_out[0:0] + attribute \src "libresoc.v:7795.3-7807.6" + wire $1\DIV_dec31_is_32b[0:0] + attribute \src "libresoc.v:7717.3-7729.6" + wire width 4 $1\DIV_dec31_ldst_len[3:0] + attribute \src "libresoc.v:7730.3-7742.6" + wire width 2 $1\DIV_dec31_rc_sel[1:0] + attribute \src "libresoc.v:7808.3-7820.6" + wire $1\DIV_dec31_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \DIV_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 6 \DIV_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 9 \DIV_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 12 \DIV_dec31_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \DIV_dec31_dec_sub11_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \DIV_dec31_dec_sub9_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \DIV_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 3 \DIV_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 4 \DIV_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \DIV_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 10 \DIV_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 11 \DIV_dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 13 \DIV_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 7 \DIV_dec31_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \DIV_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 14 \DIV_dec31_sgn + attribute \src "libresoc.v:7166.7-7166.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:7683.23-7699.4" + cell \DIV_dec31_dec_sub11 \DIV_dec31_dec_sub11 + connect \DIV_dec31_dec_sub11_cr_in \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in + connect \DIV_dec31_dec_sub11_cr_out \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out + connect \DIV_dec31_dec_sub11_cry_in \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in + connect \DIV_dec31_dec_sub11_cry_out \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out + connect \DIV_dec31_dec_sub11_function_unit \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit + connect \DIV_dec31_dec_sub11_in1_sel \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in1_sel + connect \DIV_dec31_dec_sub11_in2_sel \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in2_sel + connect \DIV_dec31_dec_sub11_internal_op \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_internal_op + connect \DIV_dec31_dec_sub11_inv_a \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_a + connect \DIV_dec31_dec_sub11_inv_out \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_out + connect \DIV_dec31_dec_sub11_is_32b \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_is_32b + connect \DIV_dec31_dec_sub11_ldst_len \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_ldst_len + connect \DIV_dec31_dec_sub11_rc_sel \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_rc_sel + connect \DIV_dec31_dec_sub11_sgn \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_sgn + connect \opcode_in \DIV_dec31_dec_sub11_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:7700.22-7716.4" + cell \DIV_dec31_dec_sub9 \DIV_dec31_dec_sub9 + connect \DIV_dec31_dec_sub9_cr_in \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in + connect \DIV_dec31_dec_sub9_cr_out \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out + connect \DIV_dec31_dec_sub9_cry_in \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_in + connect \DIV_dec31_dec_sub9_cry_out \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_out + connect \DIV_dec31_dec_sub9_function_unit \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit + connect \DIV_dec31_dec_sub9_in1_sel \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in1_sel + connect \DIV_dec31_dec_sub9_in2_sel \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in2_sel + connect \DIV_dec31_dec_sub9_internal_op \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_internal_op + connect \DIV_dec31_dec_sub9_inv_a \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_a + connect \DIV_dec31_dec_sub9_inv_out \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_out + connect \DIV_dec31_dec_sub9_is_32b \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_is_32b + connect \DIV_dec31_dec_sub9_ldst_len \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_ldst_len + connect \DIV_dec31_dec_sub9_rc_sel \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_rc_sel + connect \DIV_dec31_dec_sub9_sgn \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn + connect \opcode_in \DIV_dec31_dec_sub9_opcode_in + end + attribute \src "libresoc.v:7166.7-7166.20" + process $proc$libresoc.v:7166$165 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:7717.3-7729.6" + process $proc$libresoc.v:7717$151 + assign { } { } + assign { } { } + assign $0\DIV_dec31_ldst_len[3:0] $1\DIV_dec31_ldst_len[3:0] + attribute \src "libresoc.v:7718.5-7718.29" + switch \initial + attribute \src "libresoc.v:7718.9-7718.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_ldst_len[3:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_ldst_len[3:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_ldst_len + case + assign $1\DIV_dec31_ldst_len[3:0] 4'0000 + end + sync always + update \DIV_dec31_ldst_len $0\DIV_dec31_ldst_len[3:0] + end + attribute \src "libresoc.v:7730.3-7742.6" + process $proc$libresoc.v:7730$152 + assign { } { } + assign { } { } + assign $0\DIV_dec31_rc_sel[1:0] $1\DIV_dec31_rc_sel[1:0] + attribute \src "libresoc.v:7731.5-7731.29" + switch \initial + attribute \src "libresoc.v:7731.9-7731.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_rc_sel[1:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_rc_sel[1:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_rc_sel + case + assign $1\DIV_dec31_rc_sel[1:0] 2'00 + end + sync always + update \DIV_dec31_rc_sel $0\DIV_dec31_rc_sel[1:0] + end + attribute \src "libresoc.v:7743.3-7755.6" + process $proc$libresoc.v:7743$153 + assign { } { } + assign { } { } + assign $0\DIV_dec31_cry_in[1:0] $1\DIV_dec31_cry_in[1:0] + attribute \src "libresoc.v:7744.5-7744.29" + switch \initial + attribute \src "libresoc.v:7744.9-7744.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_cry_in[1:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_cry_in[1:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in + case + assign $1\DIV_dec31_cry_in[1:0] 2'00 + end + sync always + update \DIV_dec31_cry_in $0\DIV_dec31_cry_in[1:0] + end + attribute \src "libresoc.v:7756.3-7768.6" + process $proc$libresoc.v:7756$154 + assign { } { } + assign { } { } + assign $0\DIV_dec31_inv_a[0:0] $1\DIV_dec31_inv_a[0:0] + attribute \src "libresoc.v:7757.5-7757.29" + switch \initial + attribute \src "libresoc.v:7757.9-7757.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_inv_a[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_inv_a[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_a + case + assign $1\DIV_dec31_inv_a[0:0] 1'0 + end + sync always + update \DIV_dec31_inv_a $0\DIV_dec31_inv_a[0:0] + end + attribute \src "libresoc.v:7769.3-7781.6" + process $proc$libresoc.v:7769$155 + assign { } { } + assign { } { } + assign $0\DIV_dec31_inv_out[0:0] $1\DIV_dec31_inv_out[0:0] + attribute \src "libresoc.v:7770.5-7770.29" + switch \initial + attribute \src "libresoc.v:7770.9-7770.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_inv_out[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_inv_out[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_out + case + assign $1\DIV_dec31_inv_out[0:0] 1'0 + end + sync always + update \DIV_dec31_inv_out $0\DIV_dec31_inv_out[0:0] + end + attribute \src "libresoc.v:7782.3-7794.6" + process $proc$libresoc.v:7782$156 + assign { } { } + assign { } { } + assign $0\DIV_dec31_cry_out[0:0] $1\DIV_dec31_cry_out[0:0] + attribute \src "libresoc.v:7783.5-7783.29" + switch \initial + attribute \src "libresoc.v:7783.9-7783.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_cry_out[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_cry_out[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out + case + assign $1\DIV_dec31_cry_out[0:0] 1'0 + end + sync always + update \DIV_dec31_cry_out $0\DIV_dec31_cry_out[0:0] + end + attribute \src "libresoc.v:7795.3-7807.6" + process $proc$libresoc.v:7795$157 + assign { } { } + assign { } { } + assign $0\DIV_dec31_is_32b[0:0] $1\DIV_dec31_is_32b[0:0] + attribute \src "libresoc.v:7796.5-7796.29" + switch \initial + attribute \src "libresoc.v:7796.9-7796.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_is_32b[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_is_32b[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_is_32b + case + assign $1\DIV_dec31_is_32b[0:0] 1'0 + end + sync always + update \DIV_dec31_is_32b $0\DIV_dec31_is_32b[0:0] + end + attribute \src "libresoc.v:7808.3-7820.6" + process $proc$libresoc.v:7808$158 + assign { } { } + assign { } { } + assign $0\DIV_dec31_sgn[0:0] $1\DIV_dec31_sgn[0:0] + attribute \src "libresoc.v:7809.5-7809.29" + switch \initial + attribute \src "libresoc.v:7809.9-7809.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_sgn[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_sgn[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_sgn + case + assign $1\DIV_dec31_sgn[0:0] 1'0 + end + sync always + update \DIV_dec31_sgn $0\DIV_dec31_sgn[0:0] + end + attribute \src "libresoc.v:7821.3-7833.6" + process $proc$libresoc.v:7821$159 + assign { } { } + assign { } { } + assign $0\DIV_dec31_function_unit[11:0] $1\DIV_dec31_function_unit[11:0] + attribute \src "libresoc.v:7822.5-7822.29" + switch \initial + attribute \src "libresoc.v:7822.9-7822.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_function_unit[11:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_function_unit[11:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit + case + assign $1\DIV_dec31_function_unit[11:0] 12'000000000000 + end + sync always + update \DIV_dec31_function_unit $0\DIV_dec31_function_unit[11:0] + end + attribute \src "libresoc.v:7834.3-7846.6" + process $proc$libresoc.v:7834$160 + assign { } { } + assign { } { } + assign $0\DIV_dec31_internal_op[6:0] $1\DIV_dec31_internal_op[6:0] + attribute \src "libresoc.v:7835.5-7835.29" + switch \initial + attribute \src "libresoc.v:7835.9-7835.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_internal_op[6:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_internal_op[6:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_internal_op + case + assign $1\DIV_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \DIV_dec31_internal_op $0\DIV_dec31_internal_op[6:0] + end + attribute \src "libresoc.v:7847.3-7859.6" + process $proc$libresoc.v:7847$161 + assign { } { } + assign { } { } + assign $0\DIV_dec31_in1_sel[2:0] $1\DIV_dec31_in1_sel[2:0] + attribute \src "libresoc.v:7848.5-7848.29" + switch \initial + attribute \src "libresoc.v:7848.9-7848.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_in1_sel[2:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_in1_sel[2:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in1_sel + case + assign $1\DIV_dec31_in1_sel[2:0] 3'000 + end + sync always + update \DIV_dec31_in1_sel $0\DIV_dec31_in1_sel[2:0] + end + attribute \src "libresoc.v:7860.3-7872.6" + process $proc$libresoc.v:7860$162 + assign { } { } + assign { } { } + assign $0\DIV_dec31_in2_sel[3:0] $1\DIV_dec31_in2_sel[3:0] + attribute \src "libresoc.v:7861.5-7861.29" + switch \initial + attribute \src "libresoc.v:7861.9-7861.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_in2_sel[3:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_in2_sel[3:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in2_sel + case + assign $1\DIV_dec31_in2_sel[3:0] 4'0000 + end + sync always + update \DIV_dec31_in2_sel $0\DIV_dec31_in2_sel[3:0] + end + attribute \src "libresoc.v:7873.3-7885.6" + process $proc$libresoc.v:7873$163 + assign { } { } + assign { } { } + assign $0\DIV_dec31_cr_in[2:0] $1\DIV_dec31_cr_in[2:0] + attribute \src "libresoc.v:7874.5-7874.29" + switch \initial + attribute \src "libresoc.v:7874.9-7874.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_cr_in[2:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_cr_in[2:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in + case + assign $1\DIV_dec31_cr_in[2:0] 3'000 + end + sync always + update \DIV_dec31_cr_in $0\DIV_dec31_cr_in[2:0] + end + attribute \src "libresoc.v:7886.3-7898.6" + process $proc$libresoc.v:7886$164 + assign { } { } + assign { } { } + assign $0\DIV_dec31_cr_out[2:0] $1\DIV_dec31_cr_out[2:0] + attribute \src "libresoc.v:7887.5-7887.29" + switch \initial + attribute \src "libresoc.v:7887.9-7887.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_cr_out[2:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_cr_out[2:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out + case + assign $1\DIV_dec31_cr_out[2:0] 3'000 + end + sync always + update \DIV_dec31_cr_out $0\DIV_dec31_cr_out[2:0] + end + connect \DIV_dec31_dec_sub11_opcode_in \opcode_in + connect \DIV_dec31_dec_sub9_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:7907.1-8610.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec.DIV_dec31.DIV_dec31_dec_sub11" +attribute \generator "nMigen" +module \DIV_dec31_dec_sub11 + attribute \src "libresoc.v:8424.3-8460.6" + wire width 3 $0\DIV_dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:8461.3-8497.6" + wire width 3 $0\DIV_dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:8572.3-8608.6" + wire width 2 $0\DIV_dec31_dec_sub11_cry_in[1:0] + attribute \src "libresoc.v:8202.3-8238.6" + wire $0\DIV_dec31_dec_sub11_cry_out[0:0] + attribute \src "libresoc.v:8091.3-8127.6" + wire width 12 $0\DIV_dec31_dec_sub11_function_unit[11:0] + attribute \src "libresoc.v:8350.3-8386.6" + wire width 3 $0\DIV_dec31_dec_sub11_in1_sel[2:0] + attribute \src "libresoc.v:8387.3-8423.6" + wire width 4 $0\DIV_dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:8313.3-8349.6" + wire width 7 $0\DIV_dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:8128.3-8164.6" + wire $0\DIV_dec31_dec_sub11_inv_a[0:0] + attribute \src "libresoc.v:8165.3-8201.6" + wire $0\DIV_dec31_dec_sub11_inv_out[0:0] + attribute \src "libresoc.v:8239.3-8275.6" + wire $0\DIV_dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:8498.3-8534.6" + wire width 4 $0\DIV_dec31_dec_sub11_ldst_len[3:0] + attribute \src "libresoc.v:8535.3-8571.6" + wire width 2 $0\DIV_dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:8276.3-8312.6" + wire $0\DIV_dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:7908.7-7908.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:8424.3-8460.6" + wire width 3 $1\DIV_dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:8461.3-8497.6" + wire width 3 $1\DIV_dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:8572.3-8608.6" + wire width 2 $1\DIV_dec31_dec_sub11_cry_in[1:0] + attribute \src "libresoc.v:8202.3-8238.6" + wire $1\DIV_dec31_dec_sub11_cry_out[0:0] + attribute \src "libresoc.v:8091.3-8127.6" + wire width 12 $1\DIV_dec31_dec_sub11_function_unit[11:0] + attribute \src "libresoc.v:8350.3-8386.6" + wire width 3 $1\DIV_dec31_dec_sub11_in1_sel[2:0] + attribute \src "libresoc.v:8387.3-8423.6" + wire width 4 $1\DIV_dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:8313.3-8349.6" + wire width 7 $1\DIV_dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:8128.3-8164.6" + wire $1\DIV_dec31_dec_sub11_inv_a[0:0] + attribute \src "libresoc.v:8165.3-8201.6" + wire $1\DIV_dec31_dec_sub11_inv_out[0:0] + attribute \src "libresoc.v:8239.3-8275.6" + wire $1\DIV_dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:8498.3-8534.6" + wire width 4 $1\DIV_dec31_dec_sub11_ldst_len[3:0] + attribute \src "libresoc.v:8535.3-8571.6" + wire width 2 $1\DIV_dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:8276.3-8312.6" + wire $1\DIV_dec31_dec_sub11_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \DIV_dec31_dec_sub11_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 6 \DIV_dec31_dec_sub11_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 9 \DIV_dec31_dec_sub11_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 12 \DIV_dec31_dec_sub11_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \DIV_dec31_dec_sub11_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 3 \DIV_dec31_dec_sub11_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 4 \DIV_dec31_dec_sub11_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \DIV_dec31_dec_sub11_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 10 \DIV_dec31_dec_sub11_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 11 \DIV_dec31_dec_sub11_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 13 \DIV_dec31_dec_sub11_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 7 \DIV_dec31_dec_sub11_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \DIV_dec31_dec_sub11_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 14 \DIV_dec31_dec_sub11_sgn + attribute \src "libresoc.v:7908.7-7908.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:7908.7-7908.20" + process $proc$libresoc.v:7908$180 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:8091.3-8127.6" + process $proc$libresoc.v:8091$166 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_function_unit[11:0] $1\DIV_dec31_dec_sub11_function_unit[11:0] + attribute \src "libresoc.v:8092.5-8092.29" + switch \initial + attribute \src "libresoc.v:8092.9-8092.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + case + assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'000000000000 + end + sync always + update \DIV_dec31_dec_sub11_function_unit $0\DIV_dec31_dec_sub11_function_unit[11:0] + end + attribute \src "libresoc.v:8128.3-8164.6" + process $proc$libresoc.v:8128$167 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_inv_a[0:0] $1\DIV_dec31_dec_sub11_inv_a[0:0] + attribute \src "libresoc.v:8129.5-8129.29" + switch \initial + attribute \src "libresoc.v:8129.9-8129.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + case + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub11_inv_a $0\DIV_dec31_dec_sub11_inv_a[0:0] + end + attribute \src "libresoc.v:8165.3-8201.6" + process $proc$libresoc.v:8165$168 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_inv_out[0:0] $1\DIV_dec31_dec_sub11_inv_out[0:0] + attribute \src "libresoc.v:8166.5-8166.29" + switch \initial + attribute \src "libresoc.v:8166.9-8166.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + case + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub11_inv_out $0\DIV_dec31_dec_sub11_inv_out[0:0] + end + attribute \src "libresoc.v:8202.3-8238.6" + process $proc$libresoc.v:8202$169 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_cry_out[0:0] $1\DIV_dec31_dec_sub11_cry_out[0:0] + attribute \src "libresoc.v:8203.5-8203.29" + switch \initial + attribute \src "libresoc.v:8203.9-8203.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + case + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub11_cry_out $0\DIV_dec31_dec_sub11_cry_out[0:0] + end + attribute \src "libresoc.v:8239.3-8275.6" + process $proc$libresoc.v:8239$170 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_is_32b[0:0] $1\DIV_dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:8240.5-8240.29" + switch \initial + attribute \src "libresoc.v:8240.9-8240.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + case + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub11_is_32b $0\DIV_dec31_dec_sub11_is_32b[0:0] + end + attribute \src "libresoc.v:8276.3-8312.6" + process $proc$libresoc.v:8276$171 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_sgn[0:0] $1\DIV_dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:8277.5-8277.29" + switch \initial + attribute \src "libresoc.v:8277.9-8277.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 + case + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub11_sgn $0\DIV_dec31_dec_sub11_sgn[0:0] + end + attribute \src "libresoc.v:8313.3-8349.6" + process $proc$libresoc.v:8313$172 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_internal_op[6:0] $1\DIV_dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:8314.5-8314.29" + switch \initial + attribute \src "libresoc.v:8314.9-8314.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0101111 + case + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0000000 + end + sync always + update \DIV_dec31_dec_sub11_internal_op $0\DIV_dec31_dec_sub11_internal_op[6:0] + end + attribute \src "libresoc.v:8350.3-8386.6" + process $proc$libresoc.v:8350$173 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_in1_sel[2:0] $1\DIV_dec31_dec_sub11_in1_sel[2:0] + attribute \src "libresoc.v:8351.5-8351.29" + switch \initial + attribute \src "libresoc.v:8351.9-8351.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + case + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'000 + end + sync always + update \DIV_dec31_dec_sub11_in1_sel $0\DIV_dec31_dec_sub11_in1_sel[2:0] + end + attribute \src "libresoc.v:8387.3-8423.6" + process $proc$libresoc.v:8387$174 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_in2_sel[3:0] $1\DIV_dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:8388.5-8388.29" + switch \initial + attribute \src "libresoc.v:8388.9-8388.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + case + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0000 + end + sync always + update \DIV_dec31_dec_sub11_in2_sel $0\DIV_dec31_dec_sub11_in2_sel[3:0] + end + attribute \src "libresoc.v:8424.3-8460.6" + process $proc$libresoc.v:8424$175 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_cr_in[2:0] $1\DIV_dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:8425.5-8425.29" + switch \initial + attribute \src "libresoc.v:8425.9-8425.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + case + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + end + sync always + update \DIV_dec31_dec_sub11_cr_in $0\DIV_dec31_dec_sub11_cr_in[2:0] + end + attribute \src "libresoc.v:8461.3-8497.6" + process $proc$libresoc.v:8461$176 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_cr_out[2:0] $1\DIV_dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:8462.5-8462.29" + switch \initial + attribute \src "libresoc.v:8462.9-8462.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'000 + case + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'000 + end + sync always + update \DIV_dec31_dec_sub11_cr_out $0\DIV_dec31_dec_sub11_cr_out[2:0] + end + attribute \src "libresoc.v:8498.3-8534.6" + process $proc$libresoc.v:8498$177 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_ldst_len[3:0] $1\DIV_dec31_dec_sub11_ldst_len[3:0] + attribute \src "libresoc.v:8499.5-8499.29" + switch \initial + attribute \src "libresoc.v:8499.9-8499.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + case + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + end + sync always + update \DIV_dec31_dec_sub11_ldst_len $0\DIV_dec31_dec_sub11_ldst_len[3:0] + end + attribute \src "libresoc.v:8535.3-8571.6" + process $proc$libresoc.v:8535$178 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_rc_sel[1:0] $1\DIV_dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:8536.5-8536.29" + switch \initial + attribute \src "libresoc.v:8536.9-8536.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'00 + case + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'00 + end + sync always + update \DIV_dec31_dec_sub11_rc_sel $0\DIV_dec31_dec_sub11_rc_sel[1:0] + end + attribute \src "libresoc.v:8572.3-8608.6" + process $proc$libresoc.v:8572$179 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_cry_in[1:0] $1\DIV_dec31_dec_sub11_cry_in[1:0] + attribute \src "libresoc.v:8573.5-8573.29" + switch \initial + attribute \src "libresoc.v:8573.9-8573.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + case + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + end + sync always + update \DIV_dec31_dec_sub11_cry_in $0\DIV_dec31_dec_sub11_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:8614.1-9317.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec.DIV_dec31.DIV_dec31_dec_sub9" +attribute \generator "nMigen" +module \DIV_dec31_dec_sub9 + attribute \src "libresoc.v:9131.3-9167.6" + wire width 3 $0\DIV_dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:9168.3-9204.6" + wire width 3 $0\DIV_dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:9279.3-9315.6" + wire width 2 $0\DIV_dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:8909.3-8945.6" + wire $0\DIV_dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:8798.3-8834.6" + wire width 12 $0\DIV_dec31_dec_sub9_function_unit[11:0] + attribute \src "libresoc.v:9057.3-9093.6" + wire width 3 $0\DIV_dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:9094.3-9130.6" + wire width 4 $0\DIV_dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:9020.3-9056.6" + wire width 7 $0\DIV_dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:8835.3-8871.6" + wire $0\DIV_dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:8872.3-8908.6" + wire $0\DIV_dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:8946.3-8982.6" + wire $0\DIV_dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:9205.3-9241.6" + wire width 4 $0\DIV_dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:9242.3-9278.6" + wire width 2 $0\DIV_dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:8983.3-9019.6" + wire $0\DIV_dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:8615.7-8615.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:9131.3-9167.6" + wire width 3 $1\DIV_dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:9168.3-9204.6" + wire width 3 $1\DIV_dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:9279.3-9315.6" + wire width 2 $1\DIV_dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:8909.3-8945.6" + wire $1\DIV_dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:8798.3-8834.6" + wire width 12 $1\DIV_dec31_dec_sub9_function_unit[11:0] + attribute \src "libresoc.v:9057.3-9093.6" + wire width 3 $1\DIV_dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:9094.3-9130.6" + wire width 4 $1\DIV_dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:9020.3-9056.6" + wire width 7 $1\DIV_dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:8835.3-8871.6" + wire $1\DIV_dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:8872.3-8908.6" + wire $1\DIV_dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:8946.3-8982.6" + wire $1\DIV_dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:9205.3-9241.6" + wire width 4 $1\DIV_dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:9242.3-9278.6" + wire width 2 $1\DIV_dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:8983.3-9019.6" + wire $1\DIV_dec31_dec_sub9_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \DIV_dec31_dec_sub9_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 6 \DIV_dec31_dec_sub9_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 9 \DIV_dec31_dec_sub9_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 12 \DIV_dec31_dec_sub9_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \DIV_dec31_dec_sub9_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 3 \DIV_dec31_dec_sub9_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 4 \DIV_dec31_dec_sub9_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \DIV_dec31_dec_sub9_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 10 \DIV_dec31_dec_sub9_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 11 \DIV_dec31_dec_sub9_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 13 \DIV_dec31_dec_sub9_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 7 \DIV_dec31_dec_sub9_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \DIV_dec31_dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 14 \DIV_dec31_dec_sub9_sgn + attribute \src "libresoc.v:8615.7-8615.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:8615.7-8615.20" + process $proc$libresoc.v:8615$195 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:8798.3-8834.6" + process $proc$libresoc.v:8798$181 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_function_unit[11:0] $1\DIV_dec31_dec_sub9_function_unit[11:0] + attribute \src "libresoc.v:8799.5-8799.29" + switch \initial + attribute \src "libresoc.v:8799.9-8799.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + case + assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'000000000000 + end + sync always + update \DIV_dec31_dec_sub9_function_unit $0\DIV_dec31_dec_sub9_function_unit[11:0] + end + attribute \src "libresoc.v:8835.3-8871.6" + process $proc$libresoc.v:8835$182 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_inv_a[0:0] $1\DIV_dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:8836.5-8836.29" + switch \initial + attribute \src "libresoc.v:8836.9-8836.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + case + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub9_inv_a $0\DIV_dec31_dec_sub9_inv_a[0:0] + end + attribute \src "libresoc.v:8872.3-8908.6" + process $proc$libresoc.v:8872$183 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_inv_out[0:0] $1\DIV_dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:8873.5-8873.29" + switch \initial + attribute \src "libresoc.v:8873.9-8873.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + case + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub9_inv_out $0\DIV_dec31_dec_sub9_inv_out[0:0] + end + attribute \src "libresoc.v:8909.3-8945.6" + process $proc$libresoc.v:8909$184 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_cry_out[0:0] $1\DIV_dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:8910.5-8910.29" + switch \initial + attribute \src "libresoc.v:8910.9-8910.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + case + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub9_cry_out $0\DIV_dec31_dec_sub9_cry_out[0:0] + end + attribute \src "libresoc.v:8946.3-8982.6" + process $proc$libresoc.v:8946$185 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_is_32b[0:0] $1\DIV_dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:8947.5-8947.29" + switch \initial + attribute \src "libresoc.v:8947.9-8947.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + case + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub9_is_32b $0\DIV_dec31_dec_sub9_is_32b[0:0] + end + attribute \src "libresoc.v:8983.3-9019.6" + process $proc$libresoc.v:8983$186 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_sgn[0:0] $1\DIV_dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:8984.5-8984.29" + switch \initial + attribute \src "libresoc.v:8984.9-8984.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 + case + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub9_sgn $0\DIV_dec31_dec_sub9_sgn[0:0] + end + attribute \src "libresoc.v:9020.3-9056.6" + process $proc$libresoc.v:9020$187 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_internal_op[6:0] $1\DIV_dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:9021.5-9021.29" + switch \initial + attribute \src "libresoc.v:9021.9-9021.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0101111 + case + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0000000 + end + sync always + update \DIV_dec31_dec_sub9_internal_op $0\DIV_dec31_dec_sub9_internal_op[6:0] + end + attribute \src "libresoc.v:9057.3-9093.6" + process $proc$libresoc.v:9057$188 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_in1_sel[2:0] $1\DIV_dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:9058.5-9058.29" + switch \initial + attribute \src "libresoc.v:9058.9-9058.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + case + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'000 + end + sync always + update \DIV_dec31_dec_sub9_in1_sel $0\DIV_dec31_dec_sub9_in1_sel[2:0] + end + attribute \src "libresoc.v:9094.3-9130.6" + process $proc$libresoc.v:9094$189 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_in2_sel[3:0] $1\DIV_dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:9095.5-9095.29" + switch \initial + attribute \src "libresoc.v:9095.9-9095.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + case + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0000 + end + sync always + update \DIV_dec31_dec_sub9_in2_sel $0\DIV_dec31_dec_sub9_in2_sel[3:0] + end + attribute \src "libresoc.v:9131.3-9167.6" + process $proc$libresoc.v:9131$190 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_cr_in[2:0] $1\DIV_dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:9132.5-9132.29" + switch \initial + attribute \src "libresoc.v:9132.9-9132.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + case + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + end + sync always + update \DIV_dec31_dec_sub9_cr_in $0\DIV_dec31_dec_sub9_cr_in[2:0] + end + attribute \src "libresoc.v:9168.3-9204.6" + process $proc$libresoc.v:9168$191 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_cr_out[2:0] $1\DIV_dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:9169.5-9169.29" + switch \initial + attribute \src "libresoc.v:9169.9-9169.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'000 + case + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'000 + end + sync always + update \DIV_dec31_dec_sub9_cr_out $0\DIV_dec31_dec_sub9_cr_out[2:0] + end + attribute \src "libresoc.v:9205.3-9241.6" + process $proc$libresoc.v:9205$192 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_ldst_len[3:0] $1\DIV_dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:9206.5-9206.29" + switch \initial + attribute \src "libresoc.v:9206.9-9206.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + case + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + end + sync always + update \DIV_dec31_dec_sub9_ldst_len $0\DIV_dec31_dec_sub9_ldst_len[3:0] + end + attribute \src "libresoc.v:9242.3-9278.6" + process $proc$libresoc.v:9242$193 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_rc_sel[1:0] $1\DIV_dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:9243.5-9243.29" + switch \initial + attribute \src "libresoc.v:9243.9-9243.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'00 + case + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'00 + end + sync always + update \DIV_dec31_dec_sub9_rc_sel $0\DIV_dec31_dec_sub9_rc_sel[1:0] + end + attribute \src "libresoc.v:9279.3-9315.6" + process $proc$libresoc.v:9279$194 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_cry_in[1:0] $1\DIV_dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:9280.5-9280.29" + switch \initial + attribute \src "libresoc.v:9280.9-9280.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + case + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + end + sync always + update \DIV_dec31_dec_sub9_cry_in $0\DIV_dec31_dec_sub9_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:9321.1-10482.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31" +attribute \generator "nMigen" +module \LDST_dec31 + attribute \src "libresoc.v:10324.3-10342.6" + wire $0\LDST_dec31_br[0:0] + attribute \src "libresoc.v:10229.3-10247.6" + wire width 3 $0\LDST_dec31_cr_in[2:0] + attribute \src "libresoc.v:10248.3-10266.6" + wire width 3 $0\LDST_dec31_cr_out[2:0] + attribute \src "libresoc.v:10400.3-10418.6" + wire width 12 $0\LDST_dec31_function_unit[11:0] + attribute \src "libresoc.v:10438.3-10456.6" + wire width 3 $0\LDST_dec31_in1_sel[2:0] + attribute \src "libresoc.v:10457.3-10475.6" + wire width 4 $0\LDST_dec31_in2_sel[3:0] + attribute \src "libresoc.v:10419.3-10437.6" + wire width 7 $0\LDST_dec31_internal_op[6:0] + attribute \src "libresoc.v:10362.3-10380.6" + wire $0\LDST_dec31_is_32b[0:0] + attribute \src "libresoc.v:10267.3-10285.6" + wire width 4 $0\LDST_dec31_ldst_len[3:0] + attribute \src "libresoc.v:10305.3-10323.6" + wire width 2 $0\LDST_dec31_rc_sel[1:0] + attribute \src "libresoc.v:10381.3-10399.6" + wire $0\LDST_dec31_sgn[0:0] + attribute \src "libresoc.v:10343.3-10361.6" + wire $0\LDST_dec31_sgn_ext[0:0] + attribute \src "libresoc.v:10286.3-10304.6" + wire width 2 $0\LDST_dec31_upd[1:0] + attribute \src "libresoc.v:9322.7-9322.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:10324.3-10342.6" + wire $1\LDST_dec31_br[0:0] + attribute \src "libresoc.v:10229.3-10247.6" + wire width 3 $1\LDST_dec31_cr_in[2:0] + attribute \src "libresoc.v:10248.3-10266.6" + wire width 3 $1\LDST_dec31_cr_out[2:0] + attribute \src "libresoc.v:10400.3-10418.6" + wire width 12 $1\LDST_dec31_function_unit[11:0] + attribute \src "libresoc.v:10438.3-10456.6" + wire width 3 $1\LDST_dec31_in1_sel[2:0] + attribute \src "libresoc.v:10457.3-10475.6" + wire width 4 $1\LDST_dec31_in2_sel[3:0] + attribute \src "libresoc.v:10419.3-10437.6" + wire width 7 $1\LDST_dec31_internal_op[6:0] + attribute \src "libresoc.v:10362.3-10380.6" + wire $1\LDST_dec31_is_32b[0:0] + attribute \src "libresoc.v:10267.3-10285.6" + wire width 4 $1\LDST_dec31_ldst_len[3:0] + attribute \src "libresoc.v:10305.3-10323.6" + wire width 2 $1\LDST_dec31_rc_sel[1:0] + attribute \src "libresoc.v:10381.3-10399.6" + wire $1\LDST_dec31_sgn[0:0] + attribute \src "libresoc.v:10343.3-10361.6" + wire $1\LDST_dec31_sgn_ext[0:0] + attribute \src "libresoc.v:10286.3-10304.6" + wire width 2 $1\LDST_dec31_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 10 \LDST_dec31_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \LDST_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 6 \LDST_dec31_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src 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\enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \LDST_dec31_dec_sub23_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \LDST_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 3 \LDST_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 4 \LDST_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \LDST_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 12 \LDST_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 7 \LDST_dec31_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 9 \LDST_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 13 \LDST_dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 11 \LDST_dec31_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \LDST_dec31_upd + attribute \src "libresoc.v:9322.7-9322.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 14 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:10165.24-10180.4" + cell \LDST_dec31_dec_sub20 \LDST_dec31_dec_sub20 + connect \LDST_dec31_dec_sub20_br \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br + connect \LDST_dec31_dec_sub20_cr_in \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in + connect \LDST_dec31_dec_sub20_cr_out \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_out + connect \LDST_dec31_dec_sub20_function_unit \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit + connect \LDST_dec31_dec_sub20_in1_sel \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in1_sel + connect \LDST_dec31_dec_sub20_in2_sel \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in2_sel + connect \LDST_dec31_dec_sub20_internal_op \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_internal_op + connect \LDST_dec31_dec_sub20_is_32b \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_is_32b + connect \LDST_dec31_dec_sub20_ldst_len \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_ldst_len + connect \LDST_dec31_dec_sub20_rc_sel \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_rc_sel + connect \LDST_dec31_dec_sub20_sgn \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn + connect \LDST_dec31_dec_sub20_sgn_ext \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn_ext + connect \LDST_dec31_dec_sub20_upd \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_upd + connect \opcode_in \LDST_dec31_dec_sub20_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10181.24-10196.4" + cell \LDST_dec31_dec_sub21 \LDST_dec31_dec_sub21 + connect \LDST_dec31_dec_sub21_br \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_br + connect \LDST_dec31_dec_sub21_cr_in \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_in + connect \LDST_dec31_dec_sub21_cr_out \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_out + connect \LDST_dec31_dec_sub21_function_unit \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit + connect \LDST_dec31_dec_sub21_in1_sel \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in1_sel + connect \LDST_dec31_dec_sub21_in2_sel \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in2_sel + connect \LDST_dec31_dec_sub21_internal_op \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_internal_op + connect \LDST_dec31_dec_sub21_is_32b \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_is_32b + connect \LDST_dec31_dec_sub21_ldst_len \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_ldst_len + connect \LDST_dec31_dec_sub21_rc_sel \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_rc_sel + connect \LDST_dec31_dec_sub21_sgn \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn + connect \LDST_dec31_dec_sub21_sgn_ext \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn_ext + connect \LDST_dec31_dec_sub21_upd \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_upd + connect \opcode_in \LDST_dec31_dec_sub21_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10197.24-10212.4" + cell \LDST_dec31_dec_sub22 \LDST_dec31_dec_sub22 + connect \LDST_dec31_dec_sub22_br \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_br + connect \LDST_dec31_dec_sub22_cr_in \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_in + connect \LDST_dec31_dec_sub22_cr_out \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_out + connect \LDST_dec31_dec_sub22_function_unit \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit + connect \LDST_dec31_dec_sub22_in1_sel \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in1_sel + connect \LDST_dec31_dec_sub22_in2_sel \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in2_sel + connect \LDST_dec31_dec_sub22_internal_op \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_internal_op + connect \LDST_dec31_dec_sub22_is_32b \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_is_32b + connect \LDST_dec31_dec_sub22_ldst_len \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_ldst_len + connect \LDST_dec31_dec_sub22_rc_sel \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_rc_sel + connect \LDST_dec31_dec_sub22_sgn \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn + connect \LDST_dec31_dec_sub22_sgn_ext \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn_ext + connect \LDST_dec31_dec_sub22_upd \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_upd + connect \opcode_in \LDST_dec31_dec_sub22_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10213.24-10228.4" + cell \LDST_dec31_dec_sub23 \LDST_dec31_dec_sub23 + connect \LDST_dec31_dec_sub23_br \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_br + connect \LDST_dec31_dec_sub23_cr_in \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_in + connect \LDST_dec31_dec_sub23_cr_out \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_out + connect \LDST_dec31_dec_sub23_function_unit \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit + connect \LDST_dec31_dec_sub23_in1_sel \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in1_sel + connect \LDST_dec31_dec_sub23_in2_sel \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in2_sel + connect \LDST_dec31_dec_sub23_internal_op \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_internal_op + connect \LDST_dec31_dec_sub23_is_32b \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_is_32b + connect \LDST_dec31_dec_sub23_ldst_len \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_ldst_len + connect \LDST_dec31_dec_sub23_rc_sel \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_rc_sel + connect \LDST_dec31_dec_sub23_sgn \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn + connect \LDST_dec31_dec_sub23_sgn_ext \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn_ext + connect \LDST_dec31_dec_sub23_upd \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd + connect \opcode_in \LDST_dec31_dec_sub23_opcode_in + end + attribute \src "libresoc.v:10229.3-10247.6" + process $proc$libresoc.v:10229$196 + assign { } { } + assign { } { } + assign $0\LDST_dec31_cr_in[2:0] $1\LDST_dec31_cr_in[2:0] + attribute \src "libresoc.v:10230.5-10230.29" + switch \initial + attribute \src "libresoc.v:10230.9-10230.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_cr_in[2:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_cr_in[2:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_cr_in[2:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_cr_in[2:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_in + case + assign $1\LDST_dec31_cr_in[2:0] 3'000 + end + sync always + update \LDST_dec31_cr_in $0\LDST_dec31_cr_in[2:0] + end + attribute \src "libresoc.v:10248.3-10266.6" + process $proc$libresoc.v:10248$197 + assign { } { } + assign { } { } + assign $0\LDST_dec31_cr_out[2:0] $1\LDST_dec31_cr_out[2:0] + attribute \src "libresoc.v:10249.5-10249.29" + switch \initial + attribute \src "libresoc.v:10249.9-10249.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_cr_out[2:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_cr_out[2:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_cr_out[2:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_cr_out[2:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_out + case + assign $1\LDST_dec31_cr_out[2:0] 3'000 + end + sync always + update \LDST_dec31_cr_out $0\LDST_dec31_cr_out[2:0] + end + attribute \src "libresoc.v:10267.3-10285.6" + process $proc$libresoc.v:10267$198 + assign { } { } + assign { } { } + assign $0\LDST_dec31_ldst_len[3:0] $1\LDST_dec31_ldst_len[3:0] + attribute \src "libresoc.v:10268.5-10268.29" + switch \initial + attribute \src "libresoc.v:10268.9-10268.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_ldst_len[3:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_ldst_len[3:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_ldst_len[3:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_ldst_len[3:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_ldst_len + case + assign $1\LDST_dec31_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_dec31_ldst_len $0\LDST_dec31_ldst_len[3:0] + end + attribute \src "libresoc.v:10286.3-10304.6" + process $proc$libresoc.v:10286$199 + assign { } { } + assign { } { } + assign $0\LDST_dec31_upd[1:0] $1\LDST_dec31_upd[1:0] + attribute \src "libresoc.v:10287.5-10287.29" + switch \initial + attribute \src "libresoc.v:10287.9-10287.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_upd[1:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_upd[1:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_upd[1:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_upd[1:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd + case + assign $1\LDST_dec31_upd[1:0] 2'00 + end + sync always + update \LDST_dec31_upd $0\LDST_dec31_upd[1:0] + end + attribute \src "libresoc.v:10305.3-10323.6" + process $proc$libresoc.v:10305$200 + assign { } { } + assign { } { } + assign $0\LDST_dec31_rc_sel[1:0] $1\LDST_dec31_rc_sel[1:0] + attribute \src "libresoc.v:10306.5-10306.29" + switch \initial + attribute \src "libresoc.v:10306.9-10306.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_rc_sel[1:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_rc_sel[1:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_rc_sel[1:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_rc_sel[1:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_rc_sel + case + assign $1\LDST_dec31_rc_sel[1:0] 2'00 + end + sync always + update \LDST_dec31_rc_sel $0\LDST_dec31_rc_sel[1:0] + end + attribute \src "libresoc.v:10324.3-10342.6" + process $proc$libresoc.v:10324$201 + assign { } { } + assign { } { } + assign $0\LDST_dec31_br[0:0] $1\LDST_dec31_br[0:0] + attribute \src "libresoc.v:10325.5-10325.29" + switch \initial + attribute \src "libresoc.v:10325.9-10325.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_br[0:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_br[0:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_br[0:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_br[0:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_br + case + assign $1\LDST_dec31_br[0:0] 1'0 + end + sync always + update \LDST_dec31_br $0\LDST_dec31_br[0:0] + end + attribute \src "libresoc.v:10343.3-10361.6" + process $proc$libresoc.v:10343$202 + assign { } { } + assign { } { } + assign $0\LDST_dec31_sgn_ext[0:0] $1\LDST_dec31_sgn_ext[0:0] + attribute \src "libresoc.v:10344.5-10344.29" + switch \initial + attribute \src "libresoc.v:10344.9-10344.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_sgn_ext[0:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_sgn_ext[0:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_sgn_ext[0:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_sgn_ext[0:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn_ext + case + assign $1\LDST_dec31_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_dec31_sgn_ext $0\LDST_dec31_sgn_ext[0:0] + end + attribute \src "libresoc.v:10362.3-10380.6" + process $proc$libresoc.v:10362$203 + assign { } { } + assign { } { } + assign $0\LDST_dec31_is_32b[0:0] $1\LDST_dec31_is_32b[0:0] + attribute \src "libresoc.v:10363.5-10363.29" + switch \initial + attribute \src "libresoc.v:10363.9-10363.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_is_32b[0:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_is_32b[0:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_is_32b[0:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_is_32b[0:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_is_32b + case + assign $1\LDST_dec31_is_32b[0:0] 1'0 + end + sync always + update \LDST_dec31_is_32b $0\LDST_dec31_is_32b[0:0] + end + attribute \src "libresoc.v:10381.3-10399.6" + process $proc$libresoc.v:10381$204 + assign { } { } + assign { } { } + assign $0\LDST_dec31_sgn[0:0] $1\LDST_dec31_sgn[0:0] + attribute \src "libresoc.v:10382.5-10382.29" + switch \initial + attribute \src "libresoc.v:10382.9-10382.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_sgn[0:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_sgn[0:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_sgn[0:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_sgn[0:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn + case + assign $1\LDST_dec31_sgn[0:0] 1'0 + end + sync always + update \LDST_dec31_sgn $0\LDST_dec31_sgn[0:0] + end + attribute \src "libresoc.v:10400.3-10418.6" + process $proc$libresoc.v:10400$205 + assign { } { } + assign { } { } + assign $0\LDST_dec31_function_unit[11:0] $1\LDST_dec31_function_unit[11:0] + attribute \src "libresoc.v:10401.5-10401.29" + switch \initial + attribute \src "libresoc.v:10401.9-10401.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_function_unit[11:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_function_unit[11:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_function_unit[11:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_function_unit[11:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit + case + assign $1\LDST_dec31_function_unit[11:0] 12'000000000000 + end + sync always + update \LDST_dec31_function_unit $0\LDST_dec31_function_unit[11:0] + end + attribute \src "libresoc.v:10419.3-10437.6" + process $proc$libresoc.v:10419$206 + assign { } { } + assign { } { } + assign $0\LDST_dec31_internal_op[6:0] $1\LDST_dec31_internal_op[6:0] + attribute \src "libresoc.v:10420.5-10420.29" + switch \initial + attribute \src "libresoc.v:10420.9-10420.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_internal_op[6:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_internal_op[6:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_internal_op[6:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_internal_op[6:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_internal_op + case + assign $1\LDST_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_dec31_internal_op $0\LDST_dec31_internal_op[6:0] + end + attribute \src "libresoc.v:10438.3-10456.6" + process $proc$libresoc.v:10438$207 + assign { } { } + assign { } { } + assign $0\LDST_dec31_in1_sel[2:0] $1\LDST_dec31_in1_sel[2:0] + attribute \src "libresoc.v:10439.5-10439.29" + switch \initial + attribute \src "libresoc.v:10439.9-10439.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_in1_sel[2:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_in1_sel[2:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_in1_sel[2:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_in1_sel[2:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in1_sel + case + assign $1\LDST_dec31_in1_sel[2:0] 3'000 + end + sync always + update \LDST_dec31_in1_sel $0\LDST_dec31_in1_sel[2:0] + end + attribute \src "libresoc.v:10457.3-10475.6" + process $proc$libresoc.v:10457$208 + assign { } { } + assign { } { } + assign $0\LDST_dec31_in2_sel[3:0] $1\LDST_dec31_in2_sel[3:0] + attribute \src "libresoc.v:10458.5-10458.29" + switch \initial + attribute \src "libresoc.v:10458.9-10458.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_in2_sel[3:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_in2_sel[3:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_in2_sel[3:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_in2_sel[3:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in2_sel + case + assign $1\LDST_dec31_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_dec31_in2_sel $0\LDST_dec31_in2_sel[3:0] + end + attribute \src "libresoc.v:9322.7-9322.20" + process $proc$libresoc.v:9322$209 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + connect \LDST_dec31_dec_sub23_opcode_in \opcode_in + connect \LDST_dec31_dec_sub21_opcode_in \opcode_in + connect \LDST_dec31_dec_sub20_opcode_in \opcode_in + connect \LDST_dec31_dec_sub22_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:10486.1-10994.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub20" +attribute \generator "nMigen" +module \LDST_dec31_dec_sub20 + attribute \src "libresoc.v:10693.3-10717.6" + wire $0\LDST_dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:10868.3-10892.6" + wire width 3 $0\LDST_dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:10893.3-10917.6" + wire width 3 $0\LDST_dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:10668.3-10692.6" + wire width 12 $0\LDST_dec31_dec_sub20_function_unit[11:0] + attribute \src "libresoc.v:10818.3-10842.6" + wire width 3 $0\LDST_dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:10843.3-10867.6" + wire width 4 $0\LDST_dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:10793.3-10817.6" + wire width 7 $0\LDST_dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:10743.3-10767.6" + wire $0\LDST_dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:10918.3-10942.6" + wire width 4 $0\LDST_dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:10968.3-10992.6" + wire width 2 $0\LDST_dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:10768.3-10792.6" + wire $0\LDST_dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:10718.3-10742.6" + wire $0\LDST_dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:10943.3-10967.6" + wire width 2 $0\LDST_dec31_dec_sub20_upd[1:0] + attribute \src "libresoc.v:10487.7-10487.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:10693.3-10717.6" + wire $1\LDST_dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:10868.3-10892.6" + wire width 3 $1\LDST_dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:10893.3-10917.6" + wire width 3 $1\LDST_dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:10668.3-10692.6" + wire width 12 $1\LDST_dec31_dec_sub20_function_unit[11:0] + attribute \src "libresoc.v:10818.3-10842.6" + wire width 3 $1\LDST_dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:10843.3-10867.6" + wire width 4 $1\LDST_dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:10793.3-10817.6" + wire width 7 $1\LDST_dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:10743.3-10767.6" + wire $1\LDST_dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:10918.3-10942.6" + wire width 4 $1\LDST_dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:10968.3-10992.6" + wire width 2 $1\LDST_dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:10768.3-10792.6" + wire $1\LDST_dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:10718.3-10742.6" + wire $1\LDST_dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:10943.3-10967.6" + wire width 2 $1\LDST_dec31_dec_sub20_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 10 \LDST_dec31_dec_sub20_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \LDST_dec31_dec_sub20_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 6 \LDST_dec31_dec_sub20_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \LDST_dec31_dec_sub20_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 3 \LDST_dec31_dec_sub20_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 4 \LDST_dec31_dec_sub20_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \LDST_dec31_dec_sub20_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 12 \LDST_dec31_dec_sub20_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 7 \LDST_dec31_dec_sub20_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 9 \LDST_dec31_dec_sub20_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 13 \LDST_dec31_dec_sub20_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 11 \LDST_dec31_dec_sub20_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \LDST_dec31_dec_sub20_upd + attribute \src "libresoc.v:10487.7-10487.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 14 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:10487.7-10487.20" + process $proc$libresoc.v:10487$223 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:10668.3-10692.6" + process $proc$libresoc.v:10668$210 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_function_unit[11:0] $1\LDST_dec31_dec_sub20_function_unit[11:0] + attribute \src "libresoc.v:10669.5-10669.29" + switch \initial + attribute \src "libresoc.v:10669.9-10669.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000100 + case + assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000000 + end + sync always + update \LDST_dec31_dec_sub20_function_unit $0\LDST_dec31_dec_sub20_function_unit[11:0] + end + attribute \src "libresoc.v:10693.3-10717.6" + process $proc$libresoc.v:10693$211 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_br[0:0] $1\LDST_dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:10694.5-10694.29" + switch \initial + attribute \src "libresoc.v:10694.9-10694.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_br[0:0] 1'1 + case + assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub20_br $0\LDST_dec31_dec_sub20_br[0:0] + end + attribute \src "libresoc.v:10718.3-10742.6" + process $proc$libresoc.v:10718$212 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_sgn_ext[0:0] $1\LDST_dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:10719.5-10719.29" + switch \initial + attribute \src "libresoc.v:10719.9-10719.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub20_sgn_ext $0\LDST_dec31_dec_sub20_sgn_ext[0:0] + end + attribute \src "libresoc.v:10743.3-10767.6" + process $proc$libresoc.v:10743$213 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_is_32b[0:0] $1\LDST_dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:10744.5-10744.29" + switch \initial + attribute \src "libresoc.v:10744.9-10744.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub20_is_32b $0\LDST_dec31_dec_sub20_is_32b[0:0] + end + attribute \src "libresoc.v:10768.3-10792.6" + process $proc$libresoc.v:10768$214 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_sgn[0:0] $1\LDST_dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:10769.5-10769.29" + switch \initial + attribute \src "libresoc.v:10769.9-10769.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub20_sgn $0\LDST_dec31_dec_sub20_sgn[0:0] + end + attribute \src "libresoc.v:10793.3-10817.6" + process $proc$libresoc.v:10793$215 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_internal_op[6:0] $1\LDST_dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:10794.5-10794.29" + switch \initial + attribute \src "libresoc.v:10794.9-10794.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100110 + case + assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_dec31_dec_sub20_internal_op $0\LDST_dec31_dec_sub20_internal_op[6:0] + end + attribute \src "libresoc.v:10818.3-10842.6" + process $proc$libresoc.v:10818$216 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_in1_sel[2:0] $1\LDST_dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:10819.5-10819.29" + switch \initial + attribute \src "libresoc.v:10819.9-10819.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 + case + assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub20_in1_sel $0\LDST_dec31_dec_sub20_in1_sel[2:0] + end + attribute \src "libresoc.v:10843.3-10867.6" + process $proc$libresoc.v:10843$217 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_in2_sel[3:0] $1\LDST_dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:10844.5-10844.29" + switch \initial + attribute \src "libresoc.v:10844.9-10844.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 + case + assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub20_in2_sel $0\LDST_dec31_dec_sub20_in2_sel[3:0] + end + attribute \src "libresoc.v:10868.3-10892.6" + process $proc$libresoc.v:10868$218 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_cr_in[2:0] $1\LDST_dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:10869.5-10869.29" + switch \initial + attribute \src "libresoc.v:10869.9-10869.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub20_cr_in $0\LDST_dec31_dec_sub20_cr_in[2:0] + end + attribute \src "libresoc.v:10893.3-10917.6" + process $proc$libresoc.v:10893$219 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_cr_out[2:0] $1\LDST_dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:10894.5-10894.29" + switch \initial + attribute \src "libresoc.v:10894.9-10894.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub20_cr_out $0\LDST_dec31_dec_sub20_cr_out[2:0] + end + attribute \src "libresoc.v:10918.3-10942.6" + process $proc$libresoc.v:10918$220 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_ldst_len[3:0] $1\LDST_dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:10919.5-10919.29" + switch \initial + attribute \src "libresoc.v:10919.9-10919.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'1000 + case + assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub20_ldst_len $0\LDST_dec31_dec_sub20_ldst_len[3:0] + end + attribute \src "libresoc.v:10943.3-10967.6" + process $proc$libresoc.v:10943$221 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_upd[1:0] $1\LDST_dec31_dec_sub20_upd[1:0] + attribute \src "libresoc.v:10944.5-10944.29" + switch \initial + attribute \src "libresoc.v:10944.9-10944.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 + case + assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub20_upd $0\LDST_dec31_dec_sub20_upd[1:0] + end + attribute \src "libresoc.v:10968.3-10992.6" + process $proc$libresoc.v:10968$222 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_rc_sel[1:0] $1\LDST_dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:10969.5-10969.29" + switch \initial + attribute \src "libresoc.v:10969.9-10969.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 + case + assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub20_rc_sel $0\LDST_dec31_dec_sub20_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:10998.1-11818.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub21" +attribute \generator "nMigen" +module \LDST_dec31_dec_sub21 + attribute \src "libresoc.v:11229.3-11277.6" + wire $0\LDST_dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:11572.3-11620.6" + wire width 3 $0\LDST_dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:11621.3-11669.6" + wire width 3 $0\LDST_dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:11180.3-11228.6" + wire width 12 $0\LDST_dec31_dec_sub21_function_unit[11:0] + attribute \src "libresoc.v:11474.3-11522.6" + wire width 3 $0\LDST_dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:11523.3-11571.6" + wire width 4 $0\LDST_dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:11425.3-11473.6" + wire width 7 $0\LDST_dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:11327.3-11375.6" + wire $0\LDST_dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:11670.3-11718.6" + wire width 4 $0\LDST_dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:11768.3-11816.6" + wire width 2 $0\LDST_dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:11376.3-11424.6" + wire $0\LDST_dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:11278.3-11326.6" + wire $0\LDST_dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:11719.3-11767.6" + wire width 2 $0\LDST_dec31_dec_sub21_upd[1:0] + attribute \src "libresoc.v:10999.7-10999.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:11229.3-11277.6" + wire $1\LDST_dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:11572.3-11620.6" + wire width 3 $1\LDST_dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:11621.3-11669.6" + wire width 3 $1\LDST_dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:11180.3-11228.6" + wire width 12 $1\LDST_dec31_dec_sub21_function_unit[11:0] + attribute \src "libresoc.v:11474.3-11522.6" + wire width 3 $1\LDST_dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:11523.3-11571.6" + wire width 4 $1\LDST_dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:11425.3-11473.6" + wire width 7 $1\LDST_dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:11327.3-11375.6" + wire $1\LDST_dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:11670.3-11718.6" + wire width 4 $1\LDST_dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:11768.3-11816.6" + wire width 2 $1\LDST_dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:11376.3-11424.6" + wire $1\LDST_dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:11278.3-11326.6" + wire $1\LDST_dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:11719.3-11767.6" + wire width 2 $1\LDST_dec31_dec_sub21_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 10 \LDST_dec31_dec_sub21_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \LDST_dec31_dec_sub21_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 6 \LDST_dec31_dec_sub21_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \LDST_dec31_dec_sub21_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 3 \LDST_dec31_dec_sub21_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 4 \LDST_dec31_dec_sub21_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \LDST_dec31_dec_sub21_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 12 \LDST_dec31_dec_sub21_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 7 \LDST_dec31_dec_sub21_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 9 \LDST_dec31_dec_sub21_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 13 \LDST_dec31_dec_sub21_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 11 \LDST_dec31_dec_sub21_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \LDST_dec31_dec_sub21_upd + attribute \src "libresoc.v:10999.7-10999.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 14 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:10999.7-10999.20" + process $proc$libresoc.v:10999$237 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:11180.3-11228.6" + process $proc$libresoc.v:11180$224 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_function_unit[11:0] $1\LDST_dec31_dec_sub21_function_unit[11:0] + attribute \src "libresoc.v:11181.5-11181.29" + switch \initial + attribute \src "libresoc.v:11181.9-11181.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + case + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000000 + end + sync always + update \LDST_dec31_dec_sub21_function_unit $0\LDST_dec31_dec_sub21_function_unit[11:0] + end + attribute \src "libresoc.v:11229.3-11277.6" + process $proc$libresoc.v:11229$225 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_br[0:0] $1\LDST_dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:11230.5-11230.29" + switch \initial + attribute \src "libresoc.v:11230.9-11230.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub21_br $0\LDST_dec31_dec_sub21_br[0:0] + end + attribute \src "libresoc.v:11278.3-11326.6" + process $proc$libresoc.v:11278$226 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_sgn_ext[0:0] $1\LDST_dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:11279.5-11279.29" + switch \initial + attribute \src "libresoc.v:11279.9-11279.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub21_sgn_ext $0\LDST_dec31_dec_sub21_sgn_ext[0:0] + end + attribute \src "libresoc.v:11327.3-11375.6" + process $proc$libresoc.v:11327$227 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_is_32b[0:0] $1\LDST_dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:11328.5-11328.29" + switch \initial + attribute \src "libresoc.v:11328.9-11328.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub21_is_32b $0\LDST_dec31_dec_sub21_is_32b[0:0] + end + attribute \src "libresoc.v:11376.3-11424.6" + process $proc$libresoc.v:11376$228 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_sgn[0:0] $1\LDST_dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:11377.5-11377.29" + switch \initial + attribute \src "libresoc.v:11377.9-11377.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub21_sgn $0\LDST_dec31_dec_sub21_sgn[0:0] + end + attribute \src "libresoc.v:11425.3-11473.6" + process $proc$libresoc.v:11425$229 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_internal_op[6:0] $1\LDST_dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:11426.5-11426.29" + switch \initial + attribute \src "libresoc.v:11426.9-11426.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 + case + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_dec31_dec_sub21_internal_op $0\LDST_dec31_dec_sub21_internal_op[6:0] + end + attribute \src "libresoc.v:11474.3-11522.6" + process $proc$libresoc.v:11474$230 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_in1_sel[2:0] $1\LDST_dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:11475.5-11475.29" + switch \initial + attribute \src "libresoc.v:11475.9-11475.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + case + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub21_in1_sel $0\LDST_dec31_dec_sub21_in1_sel[2:0] + end + attribute \src "libresoc.v:11523.3-11571.6" + process $proc$libresoc.v:11523$231 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_in2_sel[3:0] $1\LDST_dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:11524.5-11524.29" + switch \initial + attribute \src "libresoc.v:11524.9-11524.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + case + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub21_in2_sel $0\LDST_dec31_dec_sub21_in2_sel[3:0] + end + attribute \src "libresoc.v:11572.3-11620.6" + process $proc$libresoc.v:11572$232 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_cr_in[2:0] $1\LDST_dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:11573.5-11573.29" + switch \initial + attribute \src "libresoc.v:11573.9-11573.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub21_cr_in $0\LDST_dec31_dec_sub21_cr_in[2:0] + end + attribute \src "libresoc.v:11621.3-11669.6" + process $proc$libresoc.v:11621$233 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_cr_out[2:0] $1\LDST_dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:11622.5-11622.29" + switch \initial + attribute \src "libresoc.v:11622.9-11622.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub21_cr_out $0\LDST_dec31_dec_sub21_cr_out[2:0] + end + attribute \src "libresoc.v:11670.3-11718.6" + process $proc$libresoc.v:11670$234 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_ldst_len[3:0] $1\LDST_dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:11671.5-11671.29" + switch \initial + attribute \src "libresoc.v:11671.9-11671.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0100 + case + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub21_ldst_len $0\LDST_dec31_dec_sub21_ldst_len[3:0] + end + attribute \src "libresoc.v:11719.3-11767.6" + process $proc$libresoc.v:11719$235 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_upd[1:0] $1\LDST_dec31_dec_sub21_upd[1:0] + attribute \src "libresoc.v:11720.5-11720.29" + switch \initial + attribute \src "libresoc.v:11720.9-11720.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + case + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub21_upd $0\LDST_dec31_dec_sub21_upd[1:0] + end + attribute \src "libresoc.v:11768.3-11816.6" + process $proc$libresoc.v:11768$236 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_rc_sel[1:0] $1\LDST_dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:11769.5-11769.29" + switch \initial + attribute \src "libresoc.v:11769.9-11769.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + case + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub21_rc_sel $0\LDST_dec31_dec_sub21_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:11822.1-12408.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub22" +attribute \generator "nMigen" +module \LDST_dec31_dec_sub22 + attribute \src "libresoc.v:12035.3-12065.6" + wire $0\LDST_dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:12252.3-12282.6" + wire width 3 $0\LDST_dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:12283.3-12313.6" + wire width 3 $0\LDST_dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:12004.3-12034.6" + wire width 12 $0\LDST_dec31_dec_sub22_function_unit[11:0] + attribute \src "libresoc.v:12190.3-12220.6" + wire width 3 $0\LDST_dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:12221.3-12251.6" + wire width 4 $0\LDST_dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:12159.3-12189.6" + wire width 7 $0\LDST_dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:12097.3-12127.6" + wire $0\LDST_dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:12314.3-12344.6" + wire width 4 $0\LDST_dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:12376.3-12406.6" + wire width 2 $0\LDST_dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:12128.3-12158.6" + wire $0\LDST_dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:12066.3-12096.6" + wire $0\LDST_dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:12345.3-12375.6" + wire width 2 $0\LDST_dec31_dec_sub22_upd[1:0] + attribute \src "libresoc.v:11823.7-11823.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:12035.3-12065.6" + wire $1\LDST_dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:12252.3-12282.6" + wire width 3 $1\LDST_dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:12283.3-12313.6" + wire width 3 $1\LDST_dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:12004.3-12034.6" + wire width 12 $1\LDST_dec31_dec_sub22_function_unit[11:0] + attribute \src "libresoc.v:12190.3-12220.6" + wire width 3 $1\LDST_dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:12221.3-12251.6" + wire width 4 $1\LDST_dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:12159.3-12189.6" + wire width 7 $1\LDST_dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:12097.3-12127.6" + wire $1\LDST_dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:12314.3-12344.6" + wire width 4 $1\LDST_dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:12376.3-12406.6" + wire width 2 $1\LDST_dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:12128.3-12158.6" + wire $1\LDST_dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:12066.3-12096.6" + wire $1\LDST_dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:12345.3-12375.6" + wire width 2 $1\LDST_dec31_dec_sub22_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 10 \LDST_dec31_dec_sub22_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \LDST_dec31_dec_sub22_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 6 \LDST_dec31_dec_sub22_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \LDST_dec31_dec_sub22_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 3 \LDST_dec31_dec_sub22_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 4 \LDST_dec31_dec_sub22_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \LDST_dec31_dec_sub22_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 12 \LDST_dec31_dec_sub22_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 7 \LDST_dec31_dec_sub22_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 9 \LDST_dec31_dec_sub22_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 13 \LDST_dec31_dec_sub22_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 11 \LDST_dec31_dec_sub22_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \LDST_dec31_dec_sub22_upd + attribute \src "libresoc.v:11823.7-11823.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 14 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:11823.7-11823.20" + process $proc$libresoc.v:11823$251 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:12004.3-12034.6" + process $proc$libresoc.v:12004$238 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_function_unit[11:0] $1\LDST_dec31_dec_sub22_function_unit[11:0] + attribute \src "libresoc.v:12005.5-12005.29" + switch \initial + attribute \src "libresoc.v:12005.9-12005.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 + case + assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000000 + end + sync always + update \LDST_dec31_dec_sub22_function_unit $0\LDST_dec31_dec_sub22_function_unit[11:0] + end + attribute \src "libresoc.v:12035.3-12065.6" + process $proc$libresoc.v:12035$239 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_br[0:0] $1\LDST_dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:12036.5-12036.29" + switch \initial + attribute \src "libresoc.v:12036.9-12036.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub22_br $0\LDST_dec31_dec_sub22_br[0:0] + end + attribute \src "libresoc.v:12066.3-12096.6" + process $proc$libresoc.v:12066$240 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_sgn_ext[0:0] $1\LDST_dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:12067.5-12067.29" + switch \initial + attribute \src "libresoc.v:12067.9-12067.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub22_sgn_ext $0\LDST_dec31_dec_sub22_sgn_ext[0:0] + end + attribute \src "libresoc.v:12097.3-12127.6" + process $proc$libresoc.v:12097$241 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_is_32b[0:0] $1\LDST_dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:12098.5-12098.29" + switch \initial + attribute \src "libresoc.v:12098.9-12098.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub22_is_32b $0\LDST_dec31_dec_sub22_is_32b[0:0] + end + attribute \src "libresoc.v:12128.3-12158.6" + process $proc$libresoc.v:12128$242 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_sgn[0:0] $1\LDST_dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:12129.5-12129.29" + switch \initial + attribute \src "libresoc.v:12129.9-12129.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub22_sgn $0\LDST_dec31_dec_sub22_sgn[0:0] + end + attribute \src "libresoc.v:12159.3-12189.6" + process $proc$libresoc.v:12159$243 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_internal_op[6:0] $1\LDST_dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:12160.5-12160.29" + switch \initial + attribute \src "libresoc.v:12160.9-12160.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 + case + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_dec31_dec_sub22_internal_op $0\LDST_dec31_dec_sub22_internal_op[6:0] + end + attribute \src "libresoc.v:12190.3-12220.6" + process $proc$libresoc.v:12190$244 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_in1_sel[2:0] $1\LDST_dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:12191.5-12191.29" + switch \initial + attribute \src "libresoc.v:12191.9-12191.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + case + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub22_in1_sel $0\LDST_dec31_dec_sub22_in1_sel[2:0] + end + attribute \src "libresoc.v:12221.3-12251.6" + process $proc$libresoc.v:12221$245 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_in2_sel[3:0] $1\LDST_dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:12222.5-12222.29" + switch \initial + attribute \src "libresoc.v:12222.9-12222.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + case + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub22_in2_sel $0\LDST_dec31_dec_sub22_in2_sel[3:0] + end + attribute \src "libresoc.v:12252.3-12282.6" + process $proc$libresoc.v:12252$246 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_cr_in[2:0] $1\LDST_dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:12253.5-12253.29" + switch \initial + attribute \src "libresoc.v:12253.9-12253.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub22_cr_in $0\LDST_dec31_dec_sub22_cr_in[2:0] + end + attribute \src "libresoc.v:12283.3-12313.6" + process $proc$libresoc.v:12283$247 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_cr_out[2:0] $1\LDST_dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:12284.5-12284.29" + switch \initial + attribute \src "libresoc.v:12284.9-12284.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub22_cr_out $0\LDST_dec31_dec_sub22_cr_out[2:0] + end + attribute \src "libresoc.v:12314.3-12344.6" + process $proc$libresoc.v:12314$248 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_ldst_len[3:0] $1\LDST_dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:12315.5-12315.29" + switch \initial + attribute \src "libresoc.v:12315.9-12315.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0100 + case + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub22_ldst_len $0\LDST_dec31_dec_sub22_ldst_len[3:0] + end + attribute \src "libresoc.v:12345.3-12375.6" + process $proc$libresoc.v:12345$249 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_upd[1:0] $1\LDST_dec31_dec_sub22_upd[1:0] + attribute \src "libresoc.v:12346.5-12346.29" + switch \initial + attribute \src "libresoc.v:12346.9-12346.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + case + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub22_upd $0\LDST_dec31_dec_sub22_upd[1:0] + end + attribute \src "libresoc.v:12376.3-12406.6" + process $proc$libresoc.v:12376$250 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_rc_sel[1:0] $1\LDST_dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:12377.5-12377.29" + switch \initial + attribute \src "libresoc.v:12377.9-12377.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + case + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub22_rc_sel $0\LDST_dec31_dec_sub22_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:12412.1-13232.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub23" +attribute \generator "nMigen" +module \LDST_dec31_dec_sub23 + attribute \src "libresoc.v:12643.3-12691.6" + wire $0\LDST_dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:12986.3-13034.6" + wire width 3 $0\LDST_dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:13035.3-13083.6" + wire width 3 $0\LDST_dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:12594.3-12642.6" + wire width 12 $0\LDST_dec31_dec_sub23_function_unit[11:0] + attribute \src "libresoc.v:12888.3-12936.6" + wire width 3 $0\LDST_dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:12937.3-12985.6" + wire width 4 $0\LDST_dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:12839.3-12887.6" + wire width 7 $0\LDST_dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:12741.3-12789.6" + wire $0\LDST_dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:13084.3-13132.6" + wire width 4 $0\LDST_dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:13182.3-13230.6" + wire width 2 $0\LDST_dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:12790.3-12838.6" + wire $0\LDST_dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:12692.3-12740.6" + wire $0\LDST_dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:13133.3-13181.6" + wire width 2 $0\LDST_dec31_dec_sub23_upd[1:0] + attribute \src "libresoc.v:12413.7-12413.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:12643.3-12691.6" + wire $1\LDST_dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:12986.3-13034.6" + wire width 3 $1\LDST_dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:13035.3-13083.6" + wire width 3 $1\LDST_dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:12594.3-12642.6" + wire width 12 $1\LDST_dec31_dec_sub23_function_unit[11:0] + attribute \src "libresoc.v:12888.3-12936.6" + wire width 3 $1\LDST_dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:12937.3-12985.6" + wire width 4 $1\LDST_dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:12839.3-12887.6" + wire width 7 $1\LDST_dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:12741.3-12789.6" + wire $1\LDST_dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:13084.3-13132.6" + wire width 4 $1\LDST_dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:13182.3-13230.6" + wire width 2 $1\LDST_dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:12790.3-12838.6" + wire $1\LDST_dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:12692.3-12740.6" + wire $1\LDST_dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:13133.3-13181.6" + wire width 2 $1\LDST_dec31_dec_sub23_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 10 \LDST_dec31_dec_sub23_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \LDST_dec31_dec_sub23_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 6 \LDST_dec31_dec_sub23_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \LDST_dec31_dec_sub23_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 3 \LDST_dec31_dec_sub23_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 4 \LDST_dec31_dec_sub23_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \LDST_dec31_dec_sub23_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 12 \LDST_dec31_dec_sub23_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 7 \LDST_dec31_dec_sub23_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 9 \LDST_dec31_dec_sub23_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 13 \LDST_dec31_dec_sub23_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 11 \LDST_dec31_dec_sub23_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \LDST_dec31_dec_sub23_upd + attribute \src "libresoc.v:12413.7-12413.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 14 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:12413.7-12413.20" + process $proc$libresoc.v:12413$265 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:12594.3-12642.6" + process $proc$libresoc.v:12594$252 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_function_unit[11:0] $1\LDST_dec31_dec_sub23_function_unit[11:0] + attribute \src "libresoc.v:12595.5-12595.29" + switch \initial + attribute \src "libresoc.v:12595.9-12595.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + case + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000000 + end + sync always + update \LDST_dec31_dec_sub23_function_unit $0\LDST_dec31_dec_sub23_function_unit[11:0] + end + attribute \src "libresoc.v:12643.3-12691.6" + process $proc$libresoc.v:12643$253 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_br[0:0] $1\LDST_dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:12644.5-12644.29" + switch \initial + attribute \src "libresoc.v:12644.9-12644.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub23_br $0\LDST_dec31_dec_sub23_br[0:0] + end + attribute \src "libresoc.v:12692.3-12740.6" + process $proc$libresoc.v:12692$254 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_sgn_ext[0:0] $1\LDST_dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:12693.5-12693.29" + switch \initial + attribute \src "libresoc.v:12693.9-12693.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub23_sgn_ext $0\LDST_dec31_dec_sub23_sgn_ext[0:0] + end + attribute \src "libresoc.v:12741.3-12789.6" + process $proc$libresoc.v:12741$255 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_is_32b[0:0] $1\LDST_dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:12742.5-12742.29" + switch \initial + attribute \src "libresoc.v:12742.9-12742.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub23_is_32b $0\LDST_dec31_dec_sub23_is_32b[0:0] + end + attribute \src "libresoc.v:12790.3-12838.6" + process $proc$libresoc.v:12790$256 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_sgn[0:0] $1\LDST_dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:12791.5-12791.29" + switch \initial + attribute \src "libresoc.v:12791.9-12791.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub23_sgn $0\LDST_dec31_dec_sub23_sgn[0:0] + end + attribute \src "libresoc.v:12839.3-12887.6" + process $proc$libresoc.v:12839$257 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_internal_op[6:0] $1\LDST_dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:12840.5-12840.29" + switch \initial + attribute \src "libresoc.v:12840.9-12840.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 + case + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_dec31_dec_sub23_internal_op $0\LDST_dec31_dec_sub23_internal_op[6:0] + end + attribute \src "libresoc.v:12888.3-12936.6" + process $proc$libresoc.v:12888$258 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_in1_sel[2:0] $1\LDST_dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:12889.5-12889.29" + switch \initial + attribute \src "libresoc.v:12889.9-12889.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + case + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub23_in1_sel $0\LDST_dec31_dec_sub23_in1_sel[2:0] + end + attribute \src "libresoc.v:12937.3-12985.6" + process $proc$libresoc.v:12937$259 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_in2_sel[3:0] $1\LDST_dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:12938.5-12938.29" + switch \initial + attribute \src "libresoc.v:12938.9-12938.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + case + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub23_in2_sel $0\LDST_dec31_dec_sub23_in2_sel[3:0] + end + attribute \src "libresoc.v:12986.3-13034.6" + process $proc$libresoc.v:12986$260 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_cr_in[2:0] $1\LDST_dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:12987.5-12987.29" + switch \initial + attribute \src "libresoc.v:12987.9-12987.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub23_cr_in $0\LDST_dec31_dec_sub23_cr_in[2:0] + end + attribute \src "libresoc.v:13035.3-13083.6" + process $proc$libresoc.v:13035$261 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_cr_out[2:0] $1\LDST_dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:13036.5-13036.29" + switch \initial + attribute \src "libresoc.v:13036.9-13036.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub23_cr_out $0\LDST_dec31_dec_sub23_cr_out[2:0] + end + attribute \src "libresoc.v:13084.3-13132.6" + process $proc$libresoc.v:13084$262 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_ldst_len[3:0] $1\LDST_dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:13085.5-13085.29" + switch \initial + attribute \src "libresoc.v:13085.9-13085.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0100 + case + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub23_ldst_len $0\LDST_dec31_dec_sub23_ldst_len[3:0] + end + attribute \src "libresoc.v:13133.3-13181.6" + process $proc$libresoc.v:13133$263 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_upd[1:0] $1\LDST_dec31_dec_sub23_upd[1:0] + attribute \src "libresoc.v:13134.5-13134.29" + switch \initial + attribute \src "libresoc.v:13134.9-13134.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + case + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub23_upd $0\LDST_dec31_dec_sub23_upd[1:0] + end + attribute \src "libresoc.v:13182.3-13230.6" + process $proc$libresoc.v:13182$264 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_rc_sel[1:0] $1\LDST_dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:13183.5-13183.29" + switch \initial + attribute \src "libresoc.v:13183.9-13183.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + case + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub23_rc_sel $0\LDST_dec31_dec_sub23_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:13236.1-13627.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec58" +attribute \generator "nMigen" +module \LDST_dec58 + attribute \src "libresoc.v:13434.3-13449.6" + wire $0\LDST_dec58_br[0:0] + attribute \src "libresoc.v:13546.3-13561.6" + wire width 3 $0\LDST_dec58_cr_in[2:0] + attribute \src "libresoc.v:13562.3-13577.6" + wire width 3 $0\LDST_dec58_cr_out[2:0] + attribute \src "libresoc.v:13418.3-13433.6" + wire width 12 $0\LDST_dec58_function_unit[11:0] + attribute \src "libresoc.v:13514.3-13529.6" + wire width 3 $0\LDST_dec58_in1_sel[2:0] + attribute \src "libresoc.v:13530.3-13545.6" + wire width 4 $0\LDST_dec58_in2_sel[3:0] + attribute \src "libresoc.v:13498.3-13513.6" + wire width 7 $0\LDST_dec58_internal_op[6:0] + attribute \src "libresoc.v:13466.3-13481.6" + wire $0\LDST_dec58_is_32b[0:0] + attribute \src "libresoc.v:13578.3-13593.6" + wire width 4 $0\LDST_dec58_ldst_len[3:0] + attribute \src "libresoc.v:13610.3-13625.6" + wire width 2 $0\LDST_dec58_rc_sel[1:0] + attribute \src "libresoc.v:13482.3-13497.6" + wire $0\LDST_dec58_sgn[0:0] + attribute \src "libresoc.v:13450.3-13465.6" + wire $0\LDST_dec58_sgn_ext[0:0] + attribute \src "libresoc.v:13594.3-13609.6" + wire width 2 $0\LDST_dec58_upd[1:0] + attribute \src "libresoc.v:13237.7-13237.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:13434.3-13449.6" + wire $1\LDST_dec58_br[0:0] + attribute \src "libresoc.v:13546.3-13561.6" + wire width 3 $1\LDST_dec58_cr_in[2:0] + attribute \src "libresoc.v:13562.3-13577.6" + wire width 3 $1\LDST_dec58_cr_out[2:0] + attribute \src "libresoc.v:13418.3-13433.6" + wire width 12 $1\LDST_dec58_function_unit[11:0] + attribute \src "libresoc.v:13514.3-13529.6" + wire width 3 $1\LDST_dec58_in1_sel[2:0] + attribute \src "libresoc.v:13530.3-13545.6" + wire width 4 $1\LDST_dec58_in2_sel[3:0] + attribute \src "libresoc.v:13498.3-13513.6" + wire width 7 $1\LDST_dec58_internal_op[6:0] + attribute \src "libresoc.v:13466.3-13481.6" + wire $1\LDST_dec58_is_32b[0:0] + attribute \src "libresoc.v:13578.3-13593.6" + wire width 4 $1\LDST_dec58_ldst_len[3:0] + attribute \src "libresoc.v:13610.3-13625.6" + wire width 2 $1\LDST_dec58_rc_sel[1:0] + attribute \src "libresoc.v:13482.3-13497.6" + wire $1\LDST_dec58_sgn[0:0] + attribute \src "libresoc.v:13450.3-13465.6" + wire $1\LDST_dec58_sgn_ext[0:0] + attribute \src "libresoc.v:13594.3-13609.6" + wire width 2 $1\LDST_dec58_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 10 \LDST_dec58_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \LDST_dec58_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 6 \LDST_dec58_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \LDST_dec58_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 3 \LDST_dec58_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 4 \LDST_dec58_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \LDST_dec58_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 12 \LDST_dec58_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 7 \LDST_dec58_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 9 \LDST_dec58_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 13 \LDST_dec58_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 11 \LDST_dec58_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \LDST_dec58_upd + attribute \src "libresoc.v:13237.7-13237.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 14 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 2 \opcode_switch + attribute \src "libresoc.v:13237.7-13237.20" + process $proc$libresoc.v:13237$279 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:13418.3-13433.6" + process $proc$libresoc.v:13418$266 + assign { } { } + assign { } { } + assign $0\LDST_dec58_function_unit[11:0] $1\LDST_dec58_function_unit[11:0] + attribute \src "libresoc.v:13419.5-13419.29" + switch \initial + attribute \src "libresoc.v:13419.9-13419.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_function_unit[11:0] 12'000000000100 + case + assign $1\LDST_dec58_function_unit[11:0] 12'000000000000 + end + sync always + update \LDST_dec58_function_unit $0\LDST_dec58_function_unit[11:0] + end + attribute \src "libresoc.v:13434.3-13449.6" + process $proc$libresoc.v:13434$267 + assign { } { } + assign { } { } + assign $0\LDST_dec58_br[0:0] $1\LDST_dec58_br[0:0] + attribute \src "libresoc.v:13435.5-13435.29" + switch \initial + attribute \src "libresoc.v:13435.9-13435.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_br[0:0] 1'0 + case + assign $1\LDST_dec58_br[0:0] 1'0 + end + sync always + update \LDST_dec58_br $0\LDST_dec58_br[0:0] + end + attribute \src "libresoc.v:13450.3-13465.6" + process $proc$libresoc.v:13450$268 + assign { } { } + assign { } { } + assign $0\LDST_dec58_sgn_ext[0:0] $1\LDST_dec58_sgn_ext[0:0] + attribute \src "libresoc.v:13451.5-13451.29" + switch \initial + attribute \src "libresoc.v:13451.9-13451.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_sgn_ext[0:0] 1'1 + case + assign $1\LDST_dec58_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_dec58_sgn_ext $0\LDST_dec58_sgn_ext[0:0] + end + attribute \src "libresoc.v:13466.3-13481.6" + process $proc$libresoc.v:13466$269 + assign { } { } + assign { } { } + assign $0\LDST_dec58_is_32b[0:0] $1\LDST_dec58_is_32b[0:0] + attribute \src "libresoc.v:13467.5-13467.29" + switch \initial + attribute \src "libresoc.v:13467.9-13467.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_is_32b[0:0] 1'0 + case + assign $1\LDST_dec58_is_32b[0:0] 1'0 + end + sync always + update \LDST_dec58_is_32b $0\LDST_dec58_is_32b[0:0] + end + attribute \src "libresoc.v:13482.3-13497.6" + process $proc$libresoc.v:13482$270 + assign { } { } + assign { } { } + assign $0\LDST_dec58_sgn[0:0] $1\LDST_dec58_sgn[0:0] + attribute \src "libresoc.v:13483.5-13483.29" + switch \initial + attribute \src "libresoc.v:13483.9-13483.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_sgn[0:0] 1'0 + case + assign $1\LDST_dec58_sgn[0:0] 1'0 + end + sync always + update \LDST_dec58_sgn $0\LDST_dec58_sgn[0:0] + end + attribute \src "libresoc.v:13498.3-13513.6" + process $proc$libresoc.v:13498$271 + assign { } { } + assign { } { } + assign $0\LDST_dec58_internal_op[6:0] $1\LDST_dec58_internal_op[6:0] + attribute \src "libresoc.v:13499.5-13499.29" + switch \initial + attribute \src "libresoc.v:13499.9-13499.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_internal_op[6:0] 7'0100101 + case + assign $1\LDST_dec58_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_dec58_internal_op $0\LDST_dec58_internal_op[6:0] + end + attribute \src "libresoc.v:13514.3-13529.6" + process $proc$libresoc.v:13514$272 + assign { } { } + assign { } { } + assign $0\LDST_dec58_in1_sel[2:0] $1\LDST_dec58_in1_sel[2:0] + attribute \src "libresoc.v:13515.5-13515.29" + switch \initial + attribute \src "libresoc.v:13515.9-13515.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_in1_sel[2:0] 3'010 + case + assign $1\LDST_dec58_in1_sel[2:0] 3'000 + end + sync always + update \LDST_dec58_in1_sel $0\LDST_dec58_in1_sel[2:0] + end + attribute \src "libresoc.v:13530.3-13545.6" + process $proc$libresoc.v:13530$273 + assign { } { } + assign { } { } + assign $0\LDST_dec58_in2_sel[3:0] $1\LDST_dec58_in2_sel[3:0] + attribute \src "libresoc.v:13531.5-13531.29" + switch \initial + attribute \src "libresoc.v:13531.9-13531.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_in2_sel[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_in2_sel[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_in2_sel[3:0] 4'1000 + case + assign $1\LDST_dec58_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_dec58_in2_sel $0\LDST_dec58_in2_sel[3:0] + end + attribute \src "libresoc.v:13546.3-13561.6" + process $proc$libresoc.v:13546$274 + assign { } { } + assign { } { } + assign $0\LDST_dec58_cr_in[2:0] $1\LDST_dec58_cr_in[2:0] + attribute \src "libresoc.v:13547.5-13547.29" + switch \initial + attribute \src "libresoc.v:13547.9-13547.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_cr_in[2:0] 3'000 + case + assign $1\LDST_dec58_cr_in[2:0] 3'000 + end + sync always + update \LDST_dec58_cr_in $0\LDST_dec58_cr_in[2:0] + end + attribute \src "libresoc.v:13562.3-13577.6" + process $proc$libresoc.v:13562$275 + assign { } { } + assign { } { } + assign $0\LDST_dec58_cr_out[2:0] $1\LDST_dec58_cr_out[2:0] + attribute \src "libresoc.v:13563.5-13563.29" + switch \initial + attribute \src "libresoc.v:13563.9-13563.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_cr_out[2:0] 3'000 + case + assign $1\LDST_dec58_cr_out[2:0] 3'000 + end + sync always + update \LDST_dec58_cr_out $0\LDST_dec58_cr_out[2:0] + end + attribute \src "libresoc.v:13578.3-13593.6" + process $proc$libresoc.v:13578$276 + assign { } { } + assign { } { } + assign $0\LDST_dec58_ldst_len[3:0] $1\LDST_dec58_ldst_len[3:0] + attribute \src "libresoc.v:13579.5-13579.29" + switch \initial + attribute \src "libresoc.v:13579.9-13579.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_ldst_len[3:0] 4'0100 + case + assign $1\LDST_dec58_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_dec58_ldst_len $0\LDST_dec58_ldst_len[3:0] + end + attribute \src "libresoc.v:13594.3-13609.6" + process $proc$libresoc.v:13594$277 + assign { } { } + assign { } { } + assign $0\LDST_dec58_upd[1:0] $1\LDST_dec58_upd[1:0] + attribute \src "libresoc.v:13595.5-13595.29" + switch \initial + attribute \src "libresoc.v:13595.9-13595.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_upd[1:0] 2'00 + case + assign $1\LDST_dec58_upd[1:0] 2'00 + end + sync always + update \LDST_dec58_upd $0\LDST_dec58_upd[1:0] + end + attribute \src "libresoc.v:13610.3-13625.6" + process $proc$libresoc.v:13610$278 + assign { } { } + assign { } { } + assign $0\LDST_dec58_rc_sel[1:0] $1\LDST_dec58_rc_sel[1:0] + attribute \src "libresoc.v:13611.5-13611.29" + switch \initial + attribute \src "libresoc.v:13611.9-13611.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_rc_sel[1:0] 2'00 + case + assign $1\LDST_dec58_rc_sel[1:0] 2'00 + end + sync always + update \LDST_dec58_rc_sel $0\LDST_dec58_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [1:0] +end +attribute \src "libresoc.v:13631.1-13983.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec62" +attribute \generator "nMigen" +module \LDST_dec62 + attribute \src "libresoc.v:13826.3-13838.6" + wire $0\LDST_dec62_br[0:0] + attribute \src "libresoc.v:13917.3-13929.6" + wire width 3 $0\LDST_dec62_cr_in[2:0] + attribute \src "libresoc.v:13930.3-13942.6" + wire width 3 $0\LDST_dec62_cr_out[2:0] + attribute \src "libresoc.v:13813.3-13825.6" + wire width 12 $0\LDST_dec62_function_unit[11:0] + attribute \src "libresoc.v:13891.3-13903.6" + wire width 3 $0\LDST_dec62_in1_sel[2:0] + attribute \src "libresoc.v:13904.3-13916.6" + wire width 4 $0\LDST_dec62_in2_sel[3:0] + attribute \src "libresoc.v:13878.3-13890.6" + wire width 7 $0\LDST_dec62_internal_op[6:0] + attribute \src "libresoc.v:13852.3-13864.6" + wire $0\LDST_dec62_is_32b[0:0] + attribute \src "libresoc.v:13943.3-13955.6" + wire width 4 $0\LDST_dec62_ldst_len[3:0] + attribute \src "libresoc.v:13969.3-13981.6" + wire width 2 $0\LDST_dec62_rc_sel[1:0] + attribute \src "libresoc.v:13865.3-13877.6" + wire $0\LDST_dec62_sgn[0:0] + attribute \src "libresoc.v:13839.3-13851.6" + wire $0\LDST_dec62_sgn_ext[0:0] + attribute \src "libresoc.v:13956.3-13968.6" + wire width 2 $0\LDST_dec62_upd[1:0] + attribute \src "libresoc.v:13632.7-13632.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:13826.3-13838.6" + wire $1\LDST_dec62_br[0:0] + attribute \src "libresoc.v:13917.3-13929.6" + wire width 3 $1\LDST_dec62_cr_in[2:0] + attribute \src "libresoc.v:13930.3-13942.6" + wire width 3 $1\LDST_dec62_cr_out[2:0] + attribute \src "libresoc.v:13813.3-13825.6" + wire width 12 $1\LDST_dec62_function_unit[11:0] + attribute \src "libresoc.v:13891.3-13903.6" + wire width 3 $1\LDST_dec62_in1_sel[2:0] + attribute \src "libresoc.v:13904.3-13916.6" + wire width 4 $1\LDST_dec62_in2_sel[3:0] + attribute \src "libresoc.v:13878.3-13890.6" + wire width 7 $1\LDST_dec62_internal_op[6:0] + attribute \src "libresoc.v:13852.3-13864.6" + wire $1\LDST_dec62_is_32b[0:0] + attribute \src "libresoc.v:13943.3-13955.6" + wire width 4 $1\LDST_dec62_ldst_len[3:0] + attribute \src "libresoc.v:13969.3-13981.6" + wire width 2 $1\LDST_dec62_rc_sel[1:0] + attribute \src "libresoc.v:13865.3-13877.6" + wire $1\LDST_dec62_sgn[0:0] + attribute \src "libresoc.v:13839.3-13851.6" + wire $1\LDST_dec62_sgn_ext[0:0] + attribute \src "libresoc.v:13956.3-13968.6" + wire width 2 $1\LDST_dec62_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 10 \LDST_dec62_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \LDST_dec62_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 6 \LDST_dec62_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \LDST_dec62_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 3 \LDST_dec62_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 4 \LDST_dec62_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \LDST_dec62_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 12 \LDST_dec62_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 7 \LDST_dec62_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 9 \LDST_dec62_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 13 \LDST_dec62_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 11 \LDST_dec62_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \LDST_dec62_upd + attribute \src "libresoc.v:13632.7-13632.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 14 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 2 \opcode_switch + attribute \src "libresoc.v:13632.7-13632.20" + process $proc$libresoc.v:13632$293 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:13813.3-13825.6" + process $proc$libresoc.v:13813$280 + assign { } { } + assign { } { } + assign $0\LDST_dec62_function_unit[11:0] $1\LDST_dec62_function_unit[11:0] + attribute \src "libresoc.v:13814.5-13814.29" + switch \initial + attribute \src "libresoc.v:13814.9-13814.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_function_unit[11:0] 12'000000000100 + case + assign $1\LDST_dec62_function_unit[11:0] 12'000000000000 + end + sync always + update \LDST_dec62_function_unit $0\LDST_dec62_function_unit[11:0] + end + attribute \src "libresoc.v:13826.3-13838.6" + process $proc$libresoc.v:13826$281 + assign { } { } + assign { } { } + assign $0\LDST_dec62_br[0:0] $1\LDST_dec62_br[0:0] + attribute \src "libresoc.v:13827.5-13827.29" + switch \initial + attribute \src "libresoc.v:13827.9-13827.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_br[0:0] 1'0 + case + assign $1\LDST_dec62_br[0:0] 1'0 + end + sync always + update \LDST_dec62_br $0\LDST_dec62_br[0:0] + end + attribute \src "libresoc.v:13839.3-13851.6" + process $proc$libresoc.v:13839$282 + assign { } { } + assign { } { } + assign $0\LDST_dec62_sgn_ext[0:0] $1\LDST_dec62_sgn_ext[0:0] + attribute \src "libresoc.v:13840.5-13840.29" + switch \initial + attribute \src "libresoc.v:13840.9-13840.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_sgn_ext[0:0] 1'0 + case + assign $1\LDST_dec62_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_dec62_sgn_ext $0\LDST_dec62_sgn_ext[0:0] + end + attribute \src "libresoc.v:13852.3-13864.6" + process $proc$libresoc.v:13852$283 + assign { } { } + assign { } { } + assign $0\LDST_dec62_is_32b[0:0] $1\LDST_dec62_is_32b[0:0] + attribute \src "libresoc.v:13853.5-13853.29" + switch \initial + attribute \src "libresoc.v:13853.9-13853.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_is_32b[0:0] 1'0 + case + assign $1\LDST_dec62_is_32b[0:0] 1'0 + end + sync always + update \LDST_dec62_is_32b $0\LDST_dec62_is_32b[0:0] + end + attribute \src "libresoc.v:13865.3-13877.6" + process $proc$libresoc.v:13865$284 + assign { } { } + assign { } { } + assign $0\LDST_dec62_sgn[0:0] $1\LDST_dec62_sgn[0:0] + attribute \src "libresoc.v:13866.5-13866.29" + switch \initial + attribute \src "libresoc.v:13866.9-13866.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_sgn[0:0] 1'0 + case + assign $1\LDST_dec62_sgn[0:0] 1'0 + end + sync always + update \LDST_dec62_sgn $0\LDST_dec62_sgn[0:0] + end + attribute \src "libresoc.v:13878.3-13890.6" + process $proc$libresoc.v:13878$285 + assign { } { } + assign { } { } + assign $0\LDST_dec62_internal_op[6:0] $1\LDST_dec62_internal_op[6:0] + attribute \src "libresoc.v:13879.5-13879.29" + switch \initial + attribute \src "libresoc.v:13879.9-13879.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_internal_op[6:0] 7'0100110 + case + assign $1\LDST_dec62_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_dec62_internal_op $0\LDST_dec62_internal_op[6:0] + end + attribute \src "libresoc.v:13891.3-13903.6" + process $proc$libresoc.v:13891$286 + assign { } { } + assign { } { } + assign $0\LDST_dec62_in1_sel[2:0] $1\LDST_dec62_in1_sel[2:0] + attribute \src "libresoc.v:13892.5-13892.29" + switch \initial + attribute \src "libresoc.v:13892.9-13892.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_in1_sel[2:0] 3'010 + case + assign $1\LDST_dec62_in1_sel[2:0] 3'000 + end + sync always + update \LDST_dec62_in1_sel $0\LDST_dec62_in1_sel[2:0] + end + attribute \src "libresoc.v:13904.3-13916.6" + process $proc$libresoc.v:13904$287 + assign { } { } + assign { } { } + assign $0\LDST_dec62_in2_sel[3:0] $1\LDST_dec62_in2_sel[3:0] + attribute \src "libresoc.v:13905.5-13905.29" + switch \initial + attribute \src "libresoc.v:13905.9-13905.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_in2_sel[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_in2_sel[3:0] 4'1000 + case + assign $1\LDST_dec62_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_dec62_in2_sel $0\LDST_dec62_in2_sel[3:0] + end + attribute \src "libresoc.v:13917.3-13929.6" + process $proc$libresoc.v:13917$288 + assign { } { } + assign { } { } + assign $0\LDST_dec62_cr_in[2:0] $1\LDST_dec62_cr_in[2:0] + attribute \src "libresoc.v:13918.5-13918.29" + switch \initial + attribute \src "libresoc.v:13918.9-13918.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_cr_in[2:0] 3'000 + case + assign $1\LDST_dec62_cr_in[2:0] 3'000 + end + sync always + update \LDST_dec62_cr_in $0\LDST_dec62_cr_in[2:0] + end + attribute \src "libresoc.v:13930.3-13942.6" + process $proc$libresoc.v:13930$289 + assign { } { } + assign { } { } + assign $0\LDST_dec62_cr_out[2:0] $1\LDST_dec62_cr_out[2:0] + attribute \src "libresoc.v:13931.5-13931.29" + switch \initial + attribute \src "libresoc.v:13931.9-13931.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_cr_out[2:0] 3'000 + case + assign $1\LDST_dec62_cr_out[2:0] 3'000 + end + sync always + update \LDST_dec62_cr_out $0\LDST_dec62_cr_out[2:0] + end + attribute \src "libresoc.v:13943.3-13955.6" + process $proc$libresoc.v:13943$290 + assign { } { } + assign { } { } + assign $0\LDST_dec62_ldst_len[3:0] $1\LDST_dec62_ldst_len[3:0] + attribute \src "libresoc.v:13944.5-13944.29" + switch \initial + attribute \src "libresoc.v:13944.9-13944.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_ldst_len[3:0] 4'1000 + case + assign $1\LDST_dec62_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_dec62_ldst_len $0\LDST_dec62_ldst_len[3:0] + end + attribute \src "libresoc.v:13956.3-13968.6" + process $proc$libresoc.v:13956$291 + assign { } { } + assign { } { } + assign $0\LDST_dec62_upd[1:0] $1\LDST_dec62_upd[1:0] + attribute \src "libresoc.v:13957.5-13957.29" + switch \initial + attribute \src "libresoc.v:13957.9-13957.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_upd[1:0] 2'01 + case + assign $1\LDST_dec62_upd[1:0] 2'00 + end + sync always + update \LDST_dec62_upd $0\LDST_dec62_upd[1:0] + end + attribute \src "libresoc.v:13969.3-13981.6" + process $proc$libresoc.v:13969$292 + assign { } { } + assign { } { } + assign $0\LDST_dec62_rc_sel[1:0] $1\LDST_dec62_rc_sel[1:0] + attribute \src "libresoc.v:13970.5-13970.29" + switch \initial + attribute \src "libresoc.v:13970.9-13970.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_rc_sel[1:0] 2'00 + case + assign $1\LDST_dec62_rc_sel[1:0] 2'00 + end + sync always + update \LDST_dec62_rc_sel $0\LDST_dec62_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [1:0] +end +attribute \src "libresoc.v:13987.1-14725.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec.LOGICAL_dec31" +attribute \generator "nMigen" +module \LOGICAL_dec31 + attribute \src "libresoc.v:14695.3-14707.6" + wire width 3 $0\LOGICAL_dec31_cr_in[2:0] + attribute \src "libresoc.v:14708.3-14720.6" + wire width 3 $0\LOGICAL_dec31_cr_out[2:0] + attribute \src "libresoc.v:14565.3-14577.6" + wire width 2 $0\LOGICAL_dec31_cry_in[1:0] + attribute \src "libresoc.v:14604.3-14616.6" + wire $0\LOGICAL_dec31_cry_out[0:0] + attribute \src "libresoc.v:14643.3-14655.6" + wire width 12 $0\LOGICAL_dec31_function_unit[11:0] + attribute \src "libresoc.v:14669.3-14681.6" + wire width 3 $0\LOGICAL_dec31_in1_sel[2:0] + attribute \src "libresoc.v:14682.3-14694.6" + wire width 4 $0\LOGICAL_dec31_in2_sel[3:0] + attribute \src "libresoc.v:14656.3-14668.6" + wire width 7 $0\LOGICAL_dec31_internal_op[6:0] + attribute \src "libresoc.v:14578.3-14590.6" + wire $0\LOGICAL_dec31_inv_a[0:0] + attribute \src "libresoc.v:14591.3-14603.6" + wire $0\LOGICAL_dec31_inv_out[0:0] + attribute \src "libresoc.v:14617.3-14629.6" + wire $0\LOGICAL_dec31_is_32b[0:0] + attribute \src "libresoc.v:14539.3-14551.6" + wire width 4 $0\LOGICAL_dec31_ldst_len[3:0] + attribute \src "libresoc.v:14552.3-14564.6" + wire width 2 $0\LOGICAL_dec31_rc_sel[1:0] + attribute \src "libresoc.v:14630.3-14642.6" + wire $0\LOGICAL_dec31_sgn[0:0] + attribute \src "libresoc.v:13988.7-13988.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:14695.3-14707.6" + wire width 3 $1\LOGICAL_dec31_cr_in[2:0] + attribute \src "libresoc.v:14708.3-14720.6" + wire width 3 $1\LOGICAL_dec31_cr_out[2:0] + attribute \src "libresoc.v:14565.3-14577.6" + wire width 2 $1\LOGICAL_dec31_cry_in[1:0] + attribute \src "libresoc.v:14604.3-14616.6" + wire $1\LOGICAL_dec31_cry_out[0:0] + attribute \src "libresoc.v:14643.3-14655.6" + wire width 12 $1\LOGICAL_dec31_function_unit[11:0] + attribute \src "libresoc.v:14669.3-14681.6" + wire width 3 $1\LOGICAL_dec31_in1_sel[2:0] + attribute \src "libresoc.v:14682.3-14694.6" + wire width 4 $1\LOGICAL_dec31_in2_sel[3:0] + attribute \src "libresoc.v:14656.3-14668.6" + wire width 7 $1\LOGICAL_dec31_internal_op[6:0] + attribute \src "libresoc.v:14578.3-14590.6" + wire $1\LOGICAL_dec31_inv_a[0:0] + attribute \src "libresoc.v:14591.3-14603.6" + wire $1\LOGICAL_dec31_inv_out[0:0] + attribute \src "libresoc.v:14617.3-14629.6" + wire $1\LOGICAL_dec31_is_32b[0:0] + attribute \src "libresoc.v:14539.3-14551.6" + wire width 4 $1\LOGICAL_dec31_ldst_len[3:0] + attribute \src "libresoc.v:14552.3-14564.6" + wire width 2 $1\LOGICAL_dec31_rc_sel[1:0] + attribute \src "libresoc.v:14630.3-14642.6" + wire $1\LOGICAL_dec31_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \LOGICAL_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 6 \LOGICAL_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 9 \LOGICAL_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 12 \LOGICAL_dec31_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \LOGICAL_dec31_dec_sub26_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \LOGICAL_dec31_dec_sub28_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \LOGICAL_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 3 \LOGICAL_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 4 \LOGICAL_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \LOGICAL_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 10 \LOGICAL_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 11 \LOGICAL_dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 13 \LOGICAL_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 7 \LOGICAL_dec31_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \LOGICAL_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 14 \LOGICAL_dec31_sgn + attribute \src "libresoc.v:13988.7-13988.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:14505.27-14521.4" + cell \LOGICAL_dec31_dec_sub26 \LOGICAL_dec31_dec_sub26 + connect \LOGICAL_dec31_dec_sub26_cr_in \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in + connect \LOGICAL_dec31_dec_sub26_cr_out \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out + connect \LOGICAL_dec31_dec_sub26_cry_in \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in + connect \LOGICAL_dec31_dec_sub26_cry_out \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out + connect \LOGICAL_dec31_dec_sub26_function_unit \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit + connect \LOGICAL_dec31_dec_sub26_in1_sel \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in1_sel + connect \LOGICAL_dec31_dec_sub26_in2_sel \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in2_sel + connect \LOGICAL_dec31_dec_sub26_internal_op \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_internal_op + connect \LOGICAL_dec31_dec_sub26_inv_a \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_a + connect \LOGICAL_dec31_dec_sub26_inv_out \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_out + connect \LOGICAL_dec31_dec_sub26_is_32b \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_is_32b + connect \LOGICAL_dec31_dec_sub26_ldst_len \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_ldst_len + connect \LOGICAL_dec31_dec_sub26_rc_sel \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_rc_sel + connect \LOGICAL_dec31_dec_sub26_sgn \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_sgn + connect \opcode_in \LOGICAL_dec31_dec_sub26_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:14522.27-14538.4" + cell \LOGICAL_dec31_dec_sub28 \LOGICAL_dec31_dec_sub28 + connect \LOGICAL_dec31_dec_sub28_cr_in \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in + connect \LOGICAL_dec31_dec_sub28_cr_out \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out + connect \LOGICAL_dec31_dec_sub28_cry_in \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in + connect \LOGICAL_dec31_dec_sub28_cry_out \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out + connect \LOGICAL_dec31_dec_sub28_function_unit \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit + connect \LOGICAL_dec31_dec_sub28_in1_sel \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in1_sel + connect \LOGICAL_dec31_dec_sub28_in2_sel \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in2_sel + connect \LOGICAL_dec31_dec_sub28_internal_op \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op + connect \LOGICAL_dec31_dec_sub28_inv_a \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_a + connect \LOGICAL_dec31_dec_sub28_inv_out \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_out + connect \LOGICAL_dec31_dec_sub28_is_32b \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_is_32b + connect \LOGICAL_dec31_dec_sub28_ldst_len \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_ldst_len + connect \LOGICAL_dec31_dec_sub28_rc_sel \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_rc_sel + connect \LOGICAL_dec31_dec_sub28_sgn \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn + connect \opcode_in \LOGICAL_dec31_dec_sub28_opcode_in + end + attribute \src "libresoc.v:13988.7-13988.20" + process $proc$libresoc.v:13988$308 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:14539.3-14551.6" + process $proc$libresoc.v:14539$294 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_ldst_len[3:0] $1\LOGICAL_dec31_ldst_len[3:0] + attribute \src "libresoc.v:14540.5-14540.29" + switch \initial + attribute \src "libresoc.v:14540.9-14540.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_ldst_len[3:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_ldst_len[3:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_ldst_len + case + assign $1\LOGICAL_dec31_ldst_len[3:0] 4'0000 + end + sync always + update \LOGICAL_dec31_ldst_len $0\LOGICAL_dec31_ldst_len[3:0] + end + attribute \src "libresoc.v:14552.3-14564.6" + process $proc$libresoc.v:14552$295 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_rc_sel[1:0] $1\LOGICAL_dec31_rc_sel[1:0] + attribute \src "libresoc.v:14553.5-14553.29" + switch \initial + attribute \src "libresoc.v:14553.9-14553.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_rc_sel[1:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_rc_sel[1:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_rc_sel + case + assign $1\LOGICAL_dec31_rc_sel[1:0] 2'00 + end + sync always + update \LOGICAL_dec31_rc_sel $0\LOGICAL_dec31_rc_sel[1:0] + end + attribute \src "libresoc.v:14565.3-14577.6" + process $proc$libresoc.v:14565$296 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_cry_in[1:0] $1\LOGICAL_dec31_cry_in[1:0] + attribute \src "libresoc.v:14566.5-14566.29" + switch \initial + attribute \src "libresoc.v:14566.9-14566.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_cry_in[1:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_cry_in[1:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in + case + assign $1\LOGICAL_dec31_cry_in[1:0] 2'00 + end + sync always + update \LOGICAL_dec31_cry_in $0\LOGICAL_dec31_cry_in[1:0] + end + attribute \src "libresoc.v:14578.3-14590.6" + process $proc$libresoc.v:14578$297 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_inv_a[0:0] $1\LOGICAL_dec31_inv_a[0:0] + attribute \src "libresoc.v:14579.5-14579.29" + switch \initial + attribute \src "libresoc.v:14579.9-14579.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_inv_a[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_inv_a[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_a + case + assign $1\LOGICAL_dec31_inv_a[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_inv_a $0\LOGICAL_dec31_inv_a[0:0] + end + attribute \src "libresoc.v:14591.3-14603.6" + process $proc$libresoc.v:14591$298 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_inv_out[0:0] $1\LOGICAL_dec31_inv_out[0:0] + attribute \src "libresoc.v:14592.5-14592.29" + switch \initial + attribute \src "libresoc.v:14592.9-14592.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_inv_out[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_inv_out[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_out + case + assign $1\LOGICAL_dec31_inv_out[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_inv_out $0\LOGICAL_dec31_inv_out[0:0] + end + attribute \src "libresoc.v:14604.3-14616.6" + process $proc$libresoc.v:14604$299 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_cry_out[0:0] $1\LOGICAL_dec31_cry_out[0:0] + attribute \src "libresoc.v:14605.5-14605.29" + switch \initial + attribute \src "libresoc.v:14605.9-14605.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_cry_out[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_cry_out[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out + case + assign $1\LOGICAL_dec31_cry_out[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_cry_out $0\LOGICAL_dec31_cry_out[0:0] + end + attribute \src "libresoc.v:14617.3-14629.6" + process $proc$libresoc.v:14617$300 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_is_32b[0:0] $1\LOGICAL_dec31_is_32b[0:0] + attribute \src "libresoc.v:14618.5-14618.29" + switch \initial + attribute \src "libresoc.v:14618.9-14618.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_is_32b[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_is_32b[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_is_32b + case + assign $1\LOGICAL_dec31_is_32b[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_is_32b $0\LOGICAL_dec31_is_32b[0:0] + end + attribute \src "libresoc.v:14630.3-14642.6" + process $proc$libresoc.v:14630$301 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_sgn[0:0] $1\LOGICAL_dec31_sgn[0:0] + attribute \src "libresoc.v:14631.5-14631.29" + switch \initial + attribute \src "libresoc.v:14631.9-14631.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_sgn[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_sgn[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_sgn + case + assign $1\LOGICAL_dec31_sgn[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_sgn $0\LOGICAL_dec31_sgn[0:0] + end + attribute \src "libresoc.v:14643.3-14655.6" + process $proc$libresoc.v:14643$302 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_function_unit[11:0] $1\LOGICAL_dec31_function_unit[11:0] + attribute \src "libresoc.v:14644.5-14644.29" + switch \initial + attribute \src "libresoc.v:14644.9-14644.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_function_unit[11:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_function_unit[11:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit + case + assign $1\LOGICAL_dec31_function_unit[11:0] 12'000000000000 + end + sync always + update \LOGICAL_dec31_function_unit $0\LOGICAL_dec31_function_unit[11:0] + end + attribute \src "libresoc.v:14656.3-14668.6" + process $proc$libresoc.v:14656$303 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_internal_op[6:0] $1\LOGICAL_dec31_internal_op[6:0] + attribute \src "libresoc.v:14657.5-14657.29" + switch \initial + attribute \src "libresoc.v:14657.9-14657.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_internal_op[6:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_internal_op[6:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_internal_op + case + assign $1\LOGICAL_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \LOGICAL_dec31_internal_op $0\LOGICAL_dec31_internal_op[6:0] + end + attribute \src "libresoc.v:14669.3-14681.6" + process $proc$libresoc.v:14669$304 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_in1_sel[2:0] $1\LOGICAL_dec31_in1_sel[2:0] + attribute \src "libresoc.v:14670.5-14670.29" + switch \initial + attribute \src "libresoc.v:14670.9-14670.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_in1_sel[2:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_in1_sel[2:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in1_sel + case + assign $1\LOGICAL_dec31_in1_sel[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_in1_sel $0\LOGICAL_dec31_in1_sel[2:0] + end + attribute \src "libresoc.v:14682.3-14694.6" + process $proc$libresoc.v:14682$305 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_in2_sel[3:0] $1\LOGICAL_dec31_in2_sel[3:0] + attribute \src "libresoc.v:14683.5-14683.29" + switch \initial + attribute \src "libresoc.v:14683.9-14683.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_in2_sel[3:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_in2_sel[3:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in2_sel + case + assign $1\LOGICAL_dec31_in2_sel[3:0] 4'0000 + end + sync always + update \LOGICAL_dec31_in2_sel $0\LOGICAL_dec31_in2_sel[3:0] + end + attribute \src "libresoc.v:14695.3-14707.6" + process $proc$libresoc.v:14695$306 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_cr_in[2:0] $1\LOGICAL_dec31_cr_in[2:0] + attribute \src "libresoc.v:14696.5-14696.29" + switch \initial + attribute \src "libresoc.v:14696.9-14696.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_cr_in[2:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_cr_in[2:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in + case + assign $1\LOGICAL_dec31_cr_in[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_cr_in $0\LOGICAL_dec31_cr_in[2:0] + end + attribute \src "libresoc.v:14708.3-14720.6" + process $proc$libresoc.v:14708$307 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_cr_out[2:0] $1\LOGICAL_dec31_cr_out[2:0] + attribute \src "libresoc.v:14709.5-14709.29" + switch \initial + attribute \src "libresoc.v:14709.9-14709.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_cr_out[2:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_cr_out[2:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out + case + assign $1\LOGICAL_dec31_cr_out[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_cr_out $0\LOGICAL_dec31_cr_out[2:0] + end + connect \LOGICAL_dec31_dec_sub26_opcode_in \opcode_in + connect \LOGICAL_dec31_dec_sub28_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:14729.1-15390.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec31_dec_sub26" +attribute \generator "nMigen" +module \LOGICAL_dec31_dec_sub26 + attribute \src "libresoc.v:15219.3-15252.6" + wire width 3 $0\LOGICAL_dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:15253.3-15286.6" + wire width 3 $0\LOGICAL_dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:15355.3-15388.6" + wire width 2 $0\LOGICAL_dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:15015.3-15048.6" + wire $0\LOGICAL_dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:14913.3-14946.6" + wire width 12 $0\LOGICAL_dec31_dec_sub26_function_unit[11:0] + attribute \src "libresoc.v:15151.3-15184.6" + wire width 3 $0\LOGICAL_dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:15185.3-15218.6" + wire width 4 $0\LOGICAL_dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:15117.3-15150.6" + wire width 7 $0\LOGICAL_dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:14947.3-14980.6" + wire $0\LOGICAL_dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:14981.3-15014.6" + wire $0\LOGICAL_dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:15049.3-15082.6" + wire $0\LOGICAL_dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:15287.3-15320.6" + wire width 4 $0\LOGICAL_dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:15321.3-15354.6" + wire width 2 $0\LOGICAL_dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:15083.3-15116.6" + wire $0\LOGICAL_dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:14730.7-14730.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:15219.3-15252.6" + wire width 3 $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:15253.3-15286.6" + wire width 3 $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:15355.3-15388.6" + wire width 2 $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:15015.3-15048.6" + wire $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:14913.3-14946.6" + wire width 12 $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] + attribute \src "libresoc.v:15151.3-15184.6" + wire width 3 $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:15185.3-15218.6" + wire width 4 $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:15117.3-15150.6" + wire width 7 $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:14947.3-14980.6" + wire $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:14981.3-15014.6" + wire $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:15049.3-15082.6" + wire $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:15287.3-15320.6" + wire width 4 $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:15321.3-15354.6" + wire width 2 $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:15083.3-15116.6" + wire $1\LOGICAL_dec31_dec_sub26_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \LOGICAL_dec31_dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 6 \LOGICAL_dec31_dec_sub26_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 9 \LOGICAL_dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 12 \LOGICAL_dec31_dec_sub26_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \LOGICAL_dec31_dec_sub26_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 3 \LOGICAL_dec31_dec_sub26_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 4 \LOGICAL_dec31_dec_sub26_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \LOGICAL_dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 10 \LOGICAL_dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 11 \LOGICAL_dec31_dec_sub26_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 13 \LOGICAL_dec31_dec_sub26_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 7 \LOGICAL_dec31_dec_sub26_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \LOGICAL_dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 14 \LOGICAL_dec31_dec_sub26_sgn + attribute \src "libresoc.v:14730.7-14730.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:14730.7-14730.20" + process $proc$libresoc.v:14730$323 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:14913.3-14946.6" + process $proc$libresoc.v:14913$309 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_function_unit[11:0] $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] + attribute \src "libresoc.v:14914.5-14914.29" + switch \initial + attribute \src "libresoc.v:14914.9-14914.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 + case + assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000000000 + end + sync always + update \LOGICAL_dec31_dec_sub26_function_unit $0\LOGICAL_dec31_dec_sub26_function_unit[11:0] + end + attribute \src "libresoc.v:14947.3-14980.6" + process $proc$libresoc.v:14947$310 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_inv_a[0:0] $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:14948.5-14948.29" + switch \initial + attribute \src "libresoc.v:14948.9-14948.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub26_inv_a $0\LOGICAL_dec31_dec_sub26_inv_a[0:0] + end + attribute \src "libresoc.v:14981.3-15014.6" + process $proc$libresoc.v:14981$311 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_inv_out[0:0] $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:14982.5-14982.29" + switch \initial + attribute \src "libresoc.v:14982.9-14982.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub26_inv_out $0\LOGICAL_dec31_dec_sub26_inv_out[0:0] + end + attribute \src "libresoc.v:15015.3-15048.6" + process $proc$libresoc.v:15015$312 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_cry_out[0:0] $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:15016.5-15016.29" + switch \initial + attribute \src "libresoc.v:15016.9-15016.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub26_cry_out $0\LOGICAL_dec31_dec_sub26_cry_out[0:0] + end + attribute \src "libresoc.v:15049.3-15082.6" + process $proc$libresoc.v:15049$313 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_is_32b[0:0] $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:15050.5-15050.29" + switch \initial + attribute \src "libresoc.v:15050.9-15050.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub26_is_32b $0\LOGICAL_dec31_dec_sub26_is_32b[0:0] + end + attribute \src "libresoc.v:15083.3-15116.6" + process $proc$libresoc.v:15083$314 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_sgn[0:0] $1\LOGICAL_dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:15084.5-15084.29" + switch \initial + attribute \src "libresoc.v:15084.9-15084.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub26_sgn $0\LOGICAL_dec31_dec_sub26_sgn[0:0] + end + attribute \src "libresoc.v:15117.3-15150.6" + process $proc$libresoc.v:15117$315 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_internal_op[6:0] $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:15118.5-15118.29" + switch \initial + attribute \src "libresoc.v:15118.9-15118.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110111 + case + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0000000 + end + sync always + update \LOGICAL_dec31_dec_sub26_internal_op $0\LOGICAL_dec31_dec_sub26_internal_op[6:0] + end + attribute \src "libresoc.v:15151.3-15184.6" + process $proc$libresoc.v:15151$316 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_in1_sel[2:0] $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:15152.5-15152.29" + switch \initial + attribute \src "libresoc.v:15152.9-15152.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + case + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_dec_sub26_in1_sel $0\LOGICAL_dec31_dec_sub26_in1_sel[2:0] + end + attribute \src "libresoc.v:15185.3-15218.6" + process $proc$libresoc.v:15185$317 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_in2_sel[3:0] $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:15186.5-15186.29" + switch \initial + attribute \src "libresoc.v:15186.9-15186.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + case + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + end + sync always + update \LOGICAL_dec31_dec_sub26_in2_sel $0\LOGICAL_dec31_dec_sub26_in2_sel[3:0] + end + attribute \src "libresoc.v:15219.3-15252.6" + process $proc$libresoc.v:15219$318 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_cr_in[2:0] $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:15220.5-15220.29" + switch \initial + attribute \src "libresoc.v:15220.9-15220.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + case + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_dec_sub26_cr_in $0\LOGICAL_dec31_dec_sub26_cr_in[2:0] + end + attribute \src "libresoc.v:15253.3-15286.6" + process $proc$libresoc.v:15253$319 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_cr_out[2:0] $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:15254.5-15254.29" + switch \initial + attribute \src "libresoc.v:15254.9-15254.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 + case + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_dec_sub26_cr_out $0\LOGICAL_dec31_dec_sub26_cr_out[2:0] + end + attribute \src "libresoc.v:15287.3-15320.6" + process $proc$libresoc.v:15287$320 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_ldst_len[3:0] $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:15288.5-15288.29" + switch \initial + attribute \src "libresoc.v:15288.9-15288.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0100 + case + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 + end + sync always + update \LOGICAL_dec31_dec_sub26_ldst_len $0\LOGICAL_dec31_dec_sub26_ldst_len[3:0] + end + attribute \src "libresoc.v:15321.3-15354.6" + process $proc$libresoc.v:15321$321 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_rc_sel[1:0] $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:15322.5-15322.29" + switch \initial + attribute \src "libresoc.v:15322.9-15322.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 + case + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 + end + sync always + update \LOGICAL_dec31_dec_sub26_rc_sel $0\LOGICAL_dec31_dec_sub26_rc_sel[1:0] + end + attribute \src "libresoc.v:15355.3-15388.6" + process $proc$libresoc.v:15355$322 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_cry_in[1:0] $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:15356.5-15356.29" + switch \initial + attribute \src "libresoc.v:15356.9-15356.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + case + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + end + sync always + update \LOGICAL_dec31_dec_sub26_cry_in $0\LOGICAL_dec31_dec_sub26_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:15394.1-16097.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec31_dec_sub28" +attribute \generator "nMigen" +module \LOGICAL_dec31_dec_sub28 + attribute \src "libresoc.v:15911.3-15947.6" + wire width 3 $0\LOGICAL_dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:15948.3-15984.6" + wire width 3 $0\LOGICAL_dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:16059.3-16095.6" + wire width 2 $0\LOGICAL_dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:15689.3-15725.6" + wire $0\LOGICAL_dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:15578.3-15614.6" + wire width 12 $0\LOGICAL_dec31_dec_sub28_function_unit[11:0] + attribute \src "libresoc.v:15837.3-15873.6" + wire width 3 $0\LOGICAL_dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:15874.3-15910.6" + wire width 4 $0\LOGICAL_dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:15800.3-15836.6" + wire width 7 $0\LOGICAL_dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:15615.3-15651.6" + wire $0\LOGICAL_dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:15652.3-15688.6" + wire $0\LOGICAL_dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:15726.3-15762.6" + wire $0\LOGICAL_dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:15985.3-16021.6" + wire width 4 $0\LOGICAL_dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:16022.3-16058.6" + wire width 2 $0\LOGICAL_dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:15763.3-15799.6" + wire $0\LOGICAL_dec31_dec_sub28_sgn[0:0] + attribute \src "libresoc.v:15395.7-15395.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:15911.3-15947.6" + wire width 3 $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:15948.3-15984.6" + wire width 3 $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:16059.3-16095.6" + wire width 2 $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:15689.3-15725.6" + wire $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:15578.3-15614.6" + wire width 12 $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] + attribute \src "libresoc.v:15837.3-15873.6" + wire width 3 $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:15874.3-15910.6" + wire width 4 $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:15800.3-15836.6" + wire width 7 $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:15615.3-15651.6" + wire $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:15652.3-15688.6" + wire $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:15726.3-15762.6" + wire $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:15985.3-16021.6" + wire width 4 $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:16022.3-16058.6" + wire width 2 $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:15763.3-15799.6" + wire $1\LOGICAL_dec31_dec_sub28_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \LOGICAL_dec31_dec_sub28_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 6 \LOGICAL_dec31_dec_sub28_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 9 \LOGICAL_dec31_dec_sub28_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 12 \LOGICAL_dec31_dec_sub28_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \LOGICAL_dec31_dec_sub28_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 3 \LOGICAL_dec31_dec_sub28_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 4 \LOGICAL_dec31_dec_sub28_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \LOGICAL_dec31_dec_sub28_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 10 \LOGICAL_dec31_dec_sub28_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 11 \LOGICAL_dec31_dec_sub28_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 13 \LOGICAL_dec31_dec_sub28_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 7 \LOGICAL_dec31_dec_sub28_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \LOGICAL_dec31_dec_sub28_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 14 \LOGICAL_dec31_dec_sub28_sgn + attribute \src "libresoc.v:15395.7-15395.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:15395.7-15395.20" + process $proc$libresoc.v:15395$338 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:15578.3-15614.6" + process $proc$libresoc.v:15578$324 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_function_unit[11:0] $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] + attribute \src "libresoc.v:15579.5-15579.29" + switch \initial + attribute \src "libresoc.v:15579.9-15579.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + case + assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000000000 + end + sync always + update \LOGICAL_dec31_dec_sub28_function_unit $0\LOGICAL_dec31_dec_sub28_function_unit[11:0] + end + attribute \src "libresoc.v:15615.3-15651.6" + process $proc$libresoc.v:15615$325 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_inv_a[0:0] $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:15616.5-15616.29" + switch \initial + attribute \src "libresoc.v:15616.9-15616.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub28_inv_a $0\LOGICAL_dec31_dec_sub28_inv_a[0:0] + end + attribute \src "libresoc.v:15652.3-15688.6" + process $proc$libresoc.v:15652$326 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_inv_out[0:0] $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:15653.5-15653.29" + switch \initial + attribute \src "libresoc.v:15653.9-15653.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub28_inv_out $0\LOGICAL_dec31_dec_sub28_inv_out[0:0] + end + attribute \src "libresoc.v:15689.3-15725.6" + process $proc$libresoc.v:15689$327 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_cry_out[0:0] $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:15690.5-15690.29" + switch \initial + attribute \src "libresoc.v:15690.9-15690.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub28_cry_out $0\LOGICAL_dec31_dec_sub28_cry_out[0:0] + end + attribute \src "libresoc.v:15726.3-15762.6" + process $proc$libresoc.v:15726$328 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_is_32b[0:0] $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:15727.5-15727.29" + switch \initial + attribute \src "libresoc.v:15727.9-15727.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub28_is_32b $0\LOGICAL_dec31_dec_sub28_is_32b[0:0] + end + attribute \src "libresoc.v:15763.3-15799.6" + process $proc$libresoc.v:15763$329 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_sgn[0:0] $1\LOGICAL_dec31_dec_sub28_sgn[0:0] + attribute \src "libresoc.v:15764.5-15764.29" + switch \initial + attribute \src "libresoc.v:15764.9-15764.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub28_sgn $0\LOGICAL_dec31_dec_sub28_sgn[0:0] + end + attribute \src "libresoc.v:15800.3-15836.6" + process $proc$libresoc.v:15800$330 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_internal_op[6:0] $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:15801.5-15801.29" + switch \initial + attribute \src "libresoc.v:15801.9-15801.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0001001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'1000011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'1000011 + case + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0000000 + end + sync always + update \LOGICAL_dec31_dec_sub28_internal_op $0\LOGICAL_dec31_dec_sub28_internal_op[6:0] + end + attribute \src "libresoc.v:15837.3-15873.6" + process $proc$libresoc.v:15837$331 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_in1_sel[2:0] $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:15838.5-15838.29" + switch \initial + attribute \src "libresoc.v:15838.9-15838.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + case + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_dec_sub28_in1_sel $0\LOGICAL_dec31_dec_sub28_in1_sel[2:0] + end + attribute \src "libresoc.v:15874.3-15910.6" + process $proc$libresoc.v:15874$332 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_in2_sel[3:0] $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:15875.5-15875.29" + switch \initial + attribute \src "libresoc.v:15875.9-15875.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + case + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0000 + end + sync always + update \LOGICAL_dec31_dec_sub28_in2_sel $0\LOGICAL_dec31_dec_sub28_in2_sel[3:0] + end + attribute \src "libresoc.v:15911.3-15947.6" + process $proc$libresoc.v:15911$333 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_cr_in[2:0] $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:15912.5-15912.29" + switch \initial + attribute \src "libresoc.v:15912.9-15912.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + case + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_dec_sub28_cr_in $0\LOGICAL_dec31_dec_sub28_cr_in[2:0] + end + attribute \src "libresoc.v:15948.3-15984.6" + process $proc$libresoc.v:15948$334 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_cr_out[2:0] $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:15949.5-15949.29" + switch \initial + attribute \src "libresoc.v:15949.9-15949.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + case + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_dec_sub28_cr_out $0\LOGICAL_dec31_dec_sub28_cr_out[2:0] + end + attribute \src "libresoc.v:15985.3-16021.6" + process $proc$libresoc.v:15985$335 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_ldst_len[3:0] $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:15986.5-15986.29" + switch \initial + attribute \src "libresoc.v:15986.9-15986.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + case + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + end + sync always + update \LOGICAL_dec31_dec_sub28_ldst_len $0\LOGICAL_dec31_dec_sub28_ldst_len[3:0] + end + attribute \src "libresoc.v:16022.3-16058.6" + process $proc$libresoc.v:16022$336 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_rc_sel[1:0] $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:16023.5-16023.29" + switch \initial + attribute \src "libresoc.v:16023.9-16023.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + case + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'00 + end + sync always + update \LOGICAL_dec31_dec_sub28_rc_sel $0\LOGICAL_dec31_dec_sub28_rc_sel[1:0] + end + attribute \src "libresoc.v:16059.3-16095.6" + process $proc$libresoc.v:16059$337 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_cry_in[1:0] $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:16060.5-16060.29" + switch \initial + attribute \src "libresoc.v:16060.9-16060.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + case + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + end + sync always + update \LOGICAL_dec31_dec_sub28_cry_in $0\LOGICAL_dec31_dec_sub28_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:16101.1-16659.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec.MUL_dec31" +attribute \generator "nMigen" +module \MUL_dec31 + attribute \src "libresoc.v:16616.3-16628.6" + wire width 3 $0\MUL_dec31_cr_in[2:0] + attribute \src "libresoc.v:16629.3-16641.6" + wire width 3 $0\MUL_dec31_cr_out[2:0] + attribute \src "libresoc.v:16577.3-16589.6" + wire width 12 $0\MUL_dec31_function_unit[11:0] + attribute \src "libresoc.v:16603.3-16615.6" + wire width 4 $0\MUL_dec31_in2_sel[3:0] + attribute \src "libresoc.v:16590.3-16602.6" + wire width 7 $0\MUL_dec31_internal_op[6:0] + attribute \src "libresoc.v:16551.3-16563.6" + wire $0\MUL_dec31_is_32b[0:0] + attribute \src "libresoc.v:16642.3-16654.6" + wire width 2 $0\MUL_dec31_rc_sel[1:0] + attribute \src "libresoc.v:16564.3-16576.6" + wire $0\MUL_dec31_sgn[0:0] + attribute \src "libresoc.v:16102.7-16102.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:16616.3-16628.6" + wire width 3 $1\MUL_dec31_cr_in[2:0] + attribute \src "libresoc.v:16629.3-16641.6" + wire width 3 $1\MUL_dec31_cr_out[2:0] + attribute \src "libresoc.v:16577.3-16589.6" + wire width 12 $1\MUL_dec31_function_unit[11:0] + attribute \src "libresoc.v:16603.3-16615.6" + wire width 4 $1\MUL_dec31_in2_sel[3:0] + attribute \src "libresoc.v:16590.3-16602.6" + wire width 7 $1\MUL_dec31_internal_op[6:0] + attribute \src "libresoc.v:16551.3-16563.6" + wire $1\MUL_dec31_is_32b[0:0] + attribute \src "libresoc.v:16642.3-16654.6" + wire width 2 $1\MUL_dec31_rc_sel[1:0] + attribute \src "libresoc.v:16564.3-16576.6" + wire $1\MUL_dec31_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 4 \MUL_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \MUL_dec31_cr_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \MUL_dec31_dec_sub11_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \MUL_dec31_dec_sub9_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \MUL_dec31_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 3 \MUL_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \MUL_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 7 \MUL_dec31_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 6 \MUL_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 8 \MUL_dec31_sgn + attribute \src "libresoc.v:16102.7-16102.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 9 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:16529.23-16539.4" + cell \MUL_dec31_dec_sub11 \MUL_dec31_dec_sub11 + connect \MUL_dec31_dec_sub11_cr_in \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in + connect \MUL_dec31_dec_sub11_cr_out \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out + connect \MUL_dec31_dec_sub11_function_unit \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit + connect \MUL_dec31_dec_sub11_in2_sel \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel + connect \MUL_dec31_dec_sub11_internal_op \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op + connect \MUL_dec31_dec_sub11_is_32b \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b + connect \MUL_dec31_dec_sub11_rc_sel \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel + connect \MUL_dec31_dec_sub11_sgn \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn + connect \opcode_in \MUL_dec31_dec_sub11_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16540.22-16550.4" + cell \MUL_dec31_dec_sub9 \MUL_dec31_dec_sub9 + connect \MUL_dec31_dec_sub9_cr_in \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in + connect \MUL_dec31_dec_sub9_cr_out \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out + connect \MUL_dec31_dec_sub9_function_unit \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit + connect \MUL_dec31_dec_sub9_in2_sel \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_in2_sel + connect \MUL_dec31_dec_sub9_internal_op \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op + connect \MUL_dec31_dec_sub9_is_32b \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_is_32b + connect \MUL_dec31_dec_sub9_rc_sel \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel + connect \MUL_dec31_dec_sub9_sgn \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn + connect \opcode_in \MUL_dec31_dec_sub9_opcode_in + end + attribute \src "libresoc.v:16102.7-16102.20" + process $proc$libresoc.v:16102$347 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:16551.3-16563.6" + process $proc$libresoc.v:16551$339 + assign { } { } + assign { } { } + assign $0\MUL_dec31_is_32b[0:0] $1\MUL_dec31_is_32b[0:0] + attribute \src "libresoc.v:16552.5-16552.29" + switch \initial + attribute \src "libresoc.v:16552.9-16552.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_is_32b[0:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_is_32b[0:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b + case + assign $1\MUL_dec31_is_32b[0:0] 1'0 + end + sync always + update \MUL_dec31_is_32b $0\MUL_dec31_is_32b[0:0] + end + attribute \src "libresoc.v:16564.3-16576.6" + process $proc$libresoc.v:16564$340 + assign { } { } + assign { } { } + assign $0\MUL_dec31_sgn[0:0] $1\MUL_dec31_sgn[0:0] + attribute \src "libresoc.v:16565.5-16565.29" + switch \initial + attribute \src "libresoc.v:16565.9-16565.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_sgn[0:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_sgn[0:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn + case + assign $1\MUL_dec31_sgn[0:0] 1'0 + end + sync always + update \MUL_dec31_sgn $0\MUL_dec31_sgn[0:0] + end + attribute \src "libresoc.v:16577.3-16589.6" + process $proc$libresoc.v:16577$341 + assign { } { } + assign { } { } + assign $0\MUL_dec31_function_unit[11:0] $1\MUL_dec31_function_unit[11:0] + attribute \src "libresoc.v:16578.5-16578.29" + switch \initial + attribute \src "libresoc.v:16578.9-16578.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_function_unit[11:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_function_unit[11:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit + case + assign $1\MUL_dec31_function_unit[11:0] 12'000000000000 + end + sync always + update \MUL_dec31_function_unit $0\MUL_dec31_function_unit[11:0] + end + attribute \src "libresoc.v:16590.3-16602.6" + process $proc$libresoc.v:16590$342 + assign { } { } + assign { } { } + assign $0\MUL_dec31_internal_op[6:0] $1\MUL_dec31_internal_op[6:0] + attribute \src "libresoc.v:16591.5-16591.29" + switch \initial + attribute \src "libresoc.v:16591.9-16591.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_internal_op[6:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_internal_op[6:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op + case + assign $1\MUL_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \MUL_dec31_internal_op $0\MUL_dec31_internal_op[6:0] + end + attribute \src "libresoc.v:16603.3-16615.6" + process $proc$libresoc.v:16603$343 + assign { } { } + assign { } { } + assign $0\MUL_dec31_in2_sel[3:0] $1\MUL_dec31_in2_sel[3:0] + attribute \src "libresoc.v:16604.5-16604.29" + switch \initial + attribute \src "libresoc.v:16604.9-16604.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_in2_sel[3:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_in2_sel[3:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel + case + assign $1\MUL_dec31_in2_sel[3:0] 4'0000 + end + sync always + update \MUL_dec31_in2_sel $0\MUL_dec31_in2_sel[3:0] + end + attribute \src "libresoc.v:16616.3-16628.6" + process $proc$libresoc.v:16616$344 + assign { } { } + assign { } { } + assign $0\MUL_dec31_cr_in[2:0] $1\MUL_dec31_cr_in[2:0] + attribute \src "libresoc.v:16617.5-16617.29" + switch \initial + attribute \src "libresoc.v:16617.9-16617.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_cr_in[2:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_cr_in[2:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in + case + assign $1\MUL_dec31_cr_in[2:0] 3'000 + end + sync always + update \MUL_dec31_cr_in $0\MUL_dec31_cr_in[2:0] + end + attribute \src "libresoc.v:16629.3-16641.6" + process $proc$libresoc.v:16629$345 + assign { } { } + assign { } { } + assign $0\MUL_dec31_cr_out[2:0] $1\MUL_dec31_cr_out[2:0] + attribute \src "libresoc.v:16630.5-16630.29" + switch \initial + attribute \src "libresoc.v:16630.9-16630.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_cr_out[2:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_cr_out[2:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out + case + assign $1\MUL_dec31_cr_out[2:0] 3'000 + end + sync always + update \MUL_dec31_cr_out $0\MUL_dec31_cr_out[2:0] + end + attribute \src "libresoc.v:16642.3-16654.6" + process $proc$libresoc.v:16642$346 + assign { } { } + assign { } { } + assign $0\MUL_dec31_rc_sel[1:0] $1\MUL_dec31_rc_sel[1:0] + attribute \src "libresoc.v:16643.5-16643.29" + switch \initial + attribute \src "libresoc.v:16643.9-16643.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_rc_sel[1:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_rc_sel[1:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel + case + assign $1\MUL_dec31_rc_sel[1:0] 2'00 + end + sync always + update \MUL_dec31_rc_sel $0\MUL_dec31_rc_sel[1:0] + end + connect \MUL_dec31_dec_sub11_opcode_in \opcode_in + connect \MUL_dec31_dec_sub9_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:16663.1-17014.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec.MUL_dec31.MUL_dec31_dec_sub11" +attribute \generator "nMigen" +module \MUL_dec31_dec_sub11 + attribute \src "libresoc.v:16888.3-16912.6" + wire width 3 $0\MUL_dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:16913.3-16937.6" + wire width 3 $0\MUL_dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:16813.3-16837.6" + wire width 12 $0\MUL_dec31_dec_sub11_function_unit[11:0] + attribute \src "libresoc.v:16863.3-16887.6" + wire width 4 $0\MUL_dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:16838.3-16862.6" + wire width 7 $0\MUL_dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:16963.3-16987.6" + wire $0\MUL_dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:16938.3-16962.6" + wire width 2 $0\MUL_dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:16988.3-17012.6" + wire $0\MUL_dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:16664.7-16664.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:16888.3-16912.6" + wire width 3 $1\MUL_dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:16913.3-16937.6" + wire width 3 $1\MUL_dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:16813.3-16837.6" + wire width 12 $1\MUL_dec31_dec_sub11_function_unit[11:0] + attribute \src "libresoc.v:16863.3-16887.6" + wire width 4 $1\MUL_dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:16838.3-16862.6" + wire width 7 $1\MUL_dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:16963.3-16987.6" + wire $1\MUL_dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:16938.3-16962.6" + wire width 2 $1\MUL_dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:16988.3-17012.6" + wire $1\MUL_dec31_dec_sub11_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 4 \MUL_dec31_dec_sub11_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \MUL_dec31_dec_sub11_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \MUL_dec31_dec_sub11_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 3 \MUL_dec31_dec_sub11_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \MUL_dec31_dec_sub11_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 7 \MUL_dec31_dec_sub11_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 6 \MUL_dec31_dec_sub11_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 8 \MUL_dec31_dec_sub11_sgn + attribute \src "libresoc.v:16664.7-16664.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 9 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:16664.7-16664.20" + process $proc$libresoc.v:16664$356 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:16813.3-16837.6" + process $proc$libresoc.v:16813$348 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_function_unit[11:0] $1\MUL_dec31_dec_sub11_function_unit[11:0] + attribute \src "libresoc.v:16814.5-16814.29" + switch \initial + attribute \src "libresoc.v:16814.9-16814.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000100000000 + case + assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000000000000 + end + sync always + update \MUL_dec31_dec_sub11_function_unit $0\MUL_dec31_dec_sub11_function_unit[11:0] + end + attribute \src "libresoc.v:16838.3-16862.6" + process $proc$libresoc.v:16838$349 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_internal_op[6:0] $1\MUL_dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:16839.5-16839.29" + switch \initial + attribute \src "libresoc.v:16839.9-16839.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110010 + case + assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0000000 + end + sync always + update \MUL_dec31_dec_sub11_internal_op $0\MUL_dec31_dec_sub11_internal_op[6:0] + end + attribute \src "libresoc.v:16863.3-16887.6" + process $proc$libresoc.v:16863$350 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_in2_sel[3:0] $1\MUL_dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:16864.5-16864.29" + switch \initial + attribute \src "libresoc.v:16864.9-16864.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 + case + assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0000 + end + sync always + update \MUL_dec31_dec_sub11_in2_sel $0\MUL_dec31_dec_sub11_in2_sel[3:0] + end + attribute \src "libresoc.v:16888.3-16912.6" + process $proc$libresoc.v:16888$351 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_cr_in[2:0] $1\MUL_dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:16889.5-16889.29" + switch \initial + attribute \src "libresoc.v:16889.9-16889.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 + case + assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 + end + sync always + update \MUL_dec31_dec_sub11_cr_in $0\MUL_dec31_dec_sub11_cr_in[2:0] + end + attribute \src "libresoc.v:16913.3-16937.6" + process $proc$libresoc.v:16913$352 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_cr_out[2:0] $1\MUL_dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:16914.5-16914.29" + switch \initial + attribute \src "libresoc.v:16914.9-16914.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 + case + assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'000 + end + sync always + update \MUL_dec31_dec_sub11_cr_out $0\MUL_dec31_dec_sub11_cr_out[2:0] + end + attribute \src "libresoc.v:16938.3-16962.6" + process $proc$libresoc.v:16938$353 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_rc_sel[1:0] $1\MUL_dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:16939.5-16939.29" + switch \initial + attribute \src "libresoc.v:16939.9-16939.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 + case + assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'00 + end + sync always + update \MUL_dec31_dec_sub11_rc_sel $0\MUL_dec31_dec_sub11_rc_sel[1:0] + end + attribute \src "libresoc.v:16963.3-16987.6" + process $proc$libresoc.v:16963$354 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_is_32b[0:0] $1\MUL_dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:16964.5-16964.29" + switch \initial + attribute \src "libresoc.v:16964.9-16964.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 + case + assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'0 + end + sync always + update \MUL_dec31_dec_sub11_is_32b $0\MUL_dec31_dec_sub11_is_32b[0:0] + end + attribute \src "libresoc.v:16988.3-17012.6" + process $proc$libresoc.v:16988$355 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_sgn[0:0] $1\MUL_dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:16989.5-16989.29" + switch \initial + attribute \src "libresoc.v:16989.9-16989.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'1 + case + assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'0 + end + sync always + update \MUL_dec31_dec_sub11_sgn $0\MUL_dec31_dec_sub11_sgn[0:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:17018.1-17369.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec.MUL_dec31.MUL_dec31_dec_sub9" +attribute \generator "nMigen" +module \MUL_dec31_dec_sub9 + attribute \src "libresoc.v:17243.3-17267.6" + wire width 3 $0\MUL_dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:17268.3-17292.6" + wire width 3 $0\MUL_dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:17168.3-17192.6" + wire width 12 $0\MUL_dec31_dec_sub9_function_unit[11:0] + attribute \src "libresoc.v:17218.3-17242.6" + wire width 4 $0\MUL_dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:17193.3-17217.6" + wire width 7 $0\MUL_dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:17318.3-17342.6" + wire $0\MUL_dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:17293.3-17317.6" + wire width 2 $0\MUL_dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:17343.3-17367.6" + wire $0\MUL_dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:17019.7-17019.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:17243.3-17267.6" + wire width 3 $1\MUL_dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:17268.3-17292.6" + wire width 3 $1\MUL_dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:17168.3-17192.6" + wire width 12 $1\MUL_dec31_dec_sub9_function_unit[11:0] + attribute \src "libresoc.v:17218.3-17242.6" + wire width 4 $1\MUL_dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:17193.3-17217.6" + wire width 7 $1\MUL_dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:17318.3-17342.6" + wire $1\MUL_dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:17293.3-17317.6" + wire width 2 $1\MUL_dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:17343.3-17367.6" + wire $1\MUL_dec31_dec_sub9_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 4 \MUL_dec31_dec_sub9_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \MUL_dec31_dec_sub9_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \MUL_dec31_dec_sub9_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 3 \MUL_dec31_dec_sub9_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \MUL_dec31_dec_sub9_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 7 \MUL_dec31_dec_sub9_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 6 \MUL_dec31_dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 8 \MUL_dec31_dec_sub9_sgn + attribute \src "libresoc.v:17019.7-17019.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 9 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:17019.7-17019.20" + process $proc$libresoc.v:17019$365 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:17168.3-17192.6" + process $proc$libresoc.v:17168$357 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_function_unit[11:0] $1\MUL_dec31_dec_sub9_function_unit[11:0] + attribute \src "libresoc.v:17169.5-17169.29" + switch \initial + attribute \src "libresoc.v:17169.9-17169.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000100000000 + case + assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000000000000 + end + sync always + update \MUL_dec31_dec_sub9_function_unit $0\MUL_dec31_dec_sub9_function_unit[11:0] + end + attribute \src "libresoc.v:17193.3-17217.6" + process $proc$libresoc.v:17193$358 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_internal_op[6:0] $1\MUL_dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:17194.5-17194.29" + switch \initial + attribute \src "libresoc.v:17194.9-17194.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110010 + case + assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0000000 + end + sync always + update \MUL_dec31_dec_sub9_internal_op $0\MUL_dec31_dec_sub9_internal_op[6:0] + end + attribute \src "libresoc.v:17218.3-17242.6" + process $proc$libresoc.v:17218$359 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_in2_sel[3:0] $1\MUL_dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:17219.5-17219.29" + switch \initial + attribute \src "libresoc.v:17219.9-17219.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 + case + assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0000 + end + sync always + update \MUL_dec31_dec_sub9_in2_sel $0\MUL_dec31_dec_sub9_in2_sel[3:0] + end + attribute \src "libresoc.v:17243.3-17267.6" + process $proc$libresoc.v:17243$360 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_cr_in[2:0] $1\MUL_dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:17244.5-17244.29" + switch \initial + attribute \src "libresoc.v:17244.9-17244.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 + case + assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 + end + sync always + update \MUL_dec31_dec_sub9_cr_in $0\MUL_dec31_dec_sub9_cr_in[2:0] + end + attribute \src "libresoc.v:17268.3-17292.6" + process $proc$libresoc.v:17268$361 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_cr_out[2:0] $1\MUL_dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:17269.5-17269.29" + switch \initial + attribute \src "libresoc.v:17269.9-17269.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 + case + assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'000 + end + sync always + update \MUL_dec31_dec_sub9_cr_out $0\MUL_dec31_dec_sub9_cr_out[2:0] + end + attribute \src "libresoc.v:17293.3-17317.6" + process $proc$libresoc.v:17293$362 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_rc_sel[1:0] $1\MUL_dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:17294.5-17294.29" + switch \initial + attribute \src "libresoc.v:17294.9-17294.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 + case + assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'00 + end + sync always + update \MUL_dec31_dec_sub9_rc_sel $0\MUL_dec31_dec_sub9_rc_sel[1:0] + end + attribute \src "libresoc.v:17318.3-17342.6" + process $proc$libresoc.v:17318$363 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_is_32b[0:0] $1\MUL_dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:17319.5-17319.29" + switch \initial + attribute \src "libresoc.v:17319.9-17319.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 + case + assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 + end + sync always + update \MUL_dec31_dec_sub9_is_32b $0\MUL_dec31_dec_sub9_is_32b[0:0] + end + attribute \src "libresoc.v:17343.3-17367.6" + process $proc$libresoc.v:17343$364 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_sgn[0:0] $1\MUL_dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:17344.5-17344.29" + switch \initial + attribute \src "libresoc.v:17344.9-17344.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'1 + case + assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'0 + end + sync always + update \MUL_dec31_dec_sub9_sgn $0\MUL_dec31_dec_sub9_sgn[0:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:17373.1-17944.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec30" +attribute \generator "nMigen" +module \SHIFT_ROT_dec30 + attribute \src "libresoc.v:17721.3-17757.6" + wire width 3 $0\SHIFT_ROT_dec30_cr_in[2:0] + attribute \src "libresoc.v:17758.3-17794.6" + wire width 3 $0\SHIFT_ROT_dec30_cr_out[2:0] + attribute \src "libresoc.v:17832.3-17868.6" + wire width 2 $0\SHIFT_ROT_dec30_cry_in[1:0] + attribute \src "libresoc.v:17906.3-17942.6" + wire $0\SHIFT_ROT_dec30_cry_out[0:0] + attribute \src "libresoc.v:17536.3-17572.6" + wire width 12 $0\SHIFT_ROT_dec30_function_unit[11:0] + attribute \src "libresoc.v:17684.3-17720.6" + wire width 4 $0\SHIFT_ROT_dec30_in2_sel[3:0] + attribute \src "libresoc.v:17647.3-17683.6" + wire width 7 $0\SHIFT_ROT_dec30_internal_op[6:0] + attribute \src "libresoc.v:17869.3-17905.6" + wire $0\SHIFT_ROT_dec30_inv_a[0:0] + attribute \src "libresoc.v:17573.3-17609.6" + wire $0\SHIFT_ROT_dec30_is_32b[0:0] + attribute \src "libresoc.v:17795.3-17831.6" + wire width 2 $0\SHIFT_ROT_dec30_rc_sel[1:0] + attribute \src "libresoc.v:17610.3-17646.6" + wire $0\SHIFT_ROT_dec30_sgn[0:0] + attribute \src "libresoc.v:17374.7-17374.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:17721.3-17757.6" + wire width 3 $1\SHIFT_ROT_dec30_cr_in[2:0] + attribute \src "libresoc.v:17758.3-17794.6" + wire width 3 $1\SHIFT_ROT_dec30_cr_out[2:0] + attribute \src "libresoc.v:17832.3-17868.6" + wire width 2 $1\SHIFT_ROT_dec30_cry_in[1:0] + attribute \src "libresoc.v:17906.3-17942.6" + wire $1\SHIFT_ROT_dec30_cry_out[0:0] + attribute \src "libresoc.v:17536.3-17572.6" + wire width 12 $1\SHIFT_ROT_dec30_function_unit[11:0] + attribute \src "libresoc.v:17684.3-17720.6" + wire width 4 $1\SHIFT_ROT_dec30_in2_sel[3:0] + attribute \src "libresoc.v:17647.3-17683.6" + wire width 7 $1\SHIFT_ROT_dec30_internal_op[6:0] + attribute \src "libresoc.v:17869.3-17905.6" + wire $1\SHIFT_ROT_dec30_inv_a[0:0] + attribute \src "libresoc.v:17573.3-17609.6" + wire $1\SHIFT_ROT_dec30_is_32b[0:0] + attribute \src "libresoc.v:17795.3-17831.6" + wire width 2 $1\SHIFT_ROT_dec30_rc_sel[1:0] + attribute \src "libresoc.v:17610.3-17646.6" + wire $1\SHIFT_ROT_dec30_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 4 \SHIFT_ROT_dec30_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \SHIFT_ROT_dec30_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \SHIFT_ROT_dec30_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 9 \SHIFT_ROT_dec30_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \SHIFT_ROT_dec30_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 3 \SHIFT_ROT_dec30_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \SHIFT_ROT_dec30_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 8 \SHIFT_ROT_dec30_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 10 \SHIFT_ROT_dec30_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 6 \SHIFT_ROT_dec30_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 11 \SHIFT_ROT_dec30_sgn + attribute \src "libresoc.v:17374.7-17374.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 12 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 4 \opcode_switch + attribute \src "libresoc.v:17374.7-17374.20" + process $proc$libresoc.v:17374$377 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:17536.3-17572.6" + process $proc$libresoc.v:17536$366 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_function_unit[11:0] $1\SHIFT_ROT_dec30_function_unit[11:0] + attribute \src "libresoc.v:17537.5-17537.29" + switch \initial + attribute \src "libresoc.v:17537.9-17537.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + case + assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000000000 + end + sync always + update \SHIFT_ROT_dec30_function_unit $0\SHIFT_ROT_dec30_function_unit[11:0] + end + attribute \src "libresoc.v:17573.3-17609.6" + process $proc$libresoc.v:17573$367 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_is_32b[0:0] $1\SHIFT_ROT_dec30_is_32b[0:0] + attribute \src "libresoc.v:17574.5-17574.29" + switch \initial + attribute \src "libresoc.v:17574.9-17574.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec30_is_32b $0\SHIFT_ROT_dec30_is_32b[0:0] + end + attribute \src "libresoc.v:17610.3-17646.6" + process $proc$libresoc.v:17610$368 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_sgn[0:0] $1\SHIFT_ROT_dec30_sgn[0:0] + attribute \src "libresoc.v:17611.5-17611.29" + switch \initial + attribute \src "libresoc.v:17611.9-17611.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec30_sgn $0\SHIFT_ROT_dec30_sgn[0:0] + end + attribute \src "libresoc.v:17647.3-17683.6" + process $proc$libresoc.v:17647$369 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_internal_op[6:0] $1\SHIFT_ROT_dec30_internal_op[6:0] + attribute \src "libresoc.v:17648.5-17648.29" + switch \initial + attribute \src "libresoc.v:17648.9-17648.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111010 + case + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0000000 + end + sync always + update \SHIFT_ROT_dec30_internal_op $0\SHIFT_ROT_dec30_internal_op[6:0] + end + attribute \src "libresoc.v:17684.3-17720.6" + process $proc$libresoc.v:17684$370 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_in2_sel[3:0] $1\SHIFT_ROT_dec30_in2_sel[3:0] + attribute \src "libresoc.v:17685.5-17685.29" + switch \initial + attribute \src "libresoc.v:17685.9-17685.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'0001 + case + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'0000 + end + sync always + update \SHIFT_ROT_dec30_in2_sel $0\SHIFT_ROT_dec30_in2_sel[3:0] + end + attribute \src "libresoc.v:17721.3-17757.6" + process $proc$libresoc.v:17721$371 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_cr_in[2:0] $1\SHIFT_ROT_dec30_cr_in[2:0] + attribute \src "libresoc.v:17722.5-17722.29" + switch \initial + attribute \src "libresoc.v:17722.9-17722.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + case + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec30_cr_in $0\SHIFT_ROT_dec30_cr_in[2:0] + end + attribute \src "libresoc.v:17758.3-17794.6" + process $proc$libresoc.v:17758$372 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_cr_out[2:0] $1\SHIFT_ROT_dec30_cr_out[2:0] + attribute \src "libresoc.v:17759.5-17759.29" + switch \initial + attribute \src "libresoc.v:17759.9-17759.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + case + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec30_cr_out $0\SHIFT_ROT_dec30_cr_out[2:0] + end + attribute \src "libresoc.v:17795.3-17831.6" + process $proc$libresoc.v:17795$373 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_rc_sel[1:0] $1\SHIFT_ROT_dec30_rc_sel[1:0] + attribute \src "libresoc.v:17796.5-17796.29" + switch \initial + attribute \src "libresoc.v:17796.9-17796.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + case + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec30_rc_sel $0\SHIFT_ROT_dec30_rc_sel[1:0] + end + attribute \src "libresoc.v:17832.3-17868.6" + process $proc$libresoc.v:17832$374 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_cry_in[1:0] $1\SHIFT_ROT_dec30_cry_in[1:0] + attribute \src "libresoc.v:17833.5-17833.29" + switch \initial + attribute \src "libresoc.v:17833.9-17833.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + case + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec30_cry_in $0\SHIFT_ROT_dec30_cry_in[1:0] + end + attribute \src "libresoc.v:17869.3-17905.6" + process $proc$libresoc.v:17869$375 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_inv_a[0:0] $1\SHIFT_ROT_dec30_inv_a[0:0] + attribute \src "libresoc.v:17870.5-17870.29" + switch \initial + attribute \src "libresoc.v:17870.9-17870.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec30_inv_a $0\SHIFT_ROT_dec30_inv_a[0:0] + end + attribute \src "libresoc.v:17906.3-17942.6" + process $proc$libresoc.v:17906$376 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_cry_out[0:0] $1\SHIFT_ROT_dec30_cry_out[0:0] + attribute \src "libresoc.v:17907.5-17907.29" + switch \initial + attribute \src "libresoc.v:17907.9-17907.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec30_cry_out $0\SHIFT_ROT_dec30_cry_out[0:0] + end + connect \opcode_switch \opcode_in [4:1] +end +attribute \src "libresoc.v:17948.1-18780.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31" +attribute \generator "nMigen" +module \SHIFT_ROT_dec31 + attribute \src "libresoc.v:18743.3-18758.6" + wire width 3 $0\SHIFT_ROT_dec31_cr_in[2:0] + attribute \src "libresoc.v:18759.3-18774.6" + wire width 3 $0\SHIFT_ROT_dec31_cr_out[2:0] + attribute \src "libresoc.v:18615.3-18630.6" + wire width 2 $0\SHIFT_ROT_dec31_cry_in[1:0] + attribute \src "libresoc.v:18647.3-18662.6" + wire $0\SHIFT_ROT_dec31_cry_out[0:0] + attribute \src "libresoc.v:18695.3-18710.6" + wire width 12 $0\SHIFT_ROT_dec31_function_unit[11:0] + attribute \src "libresoc.v:18727.3-18742.6" + wire width 4 $0\SHIFT_ROT_dec31_in2_sel[3:0] + attribute \src "libresoc.v:18711.3-18726.6" + wire width 7 $0\SHIFT_ROT_dec31_internal_op[6:0] + attribute \src "libresoc.v:18631.3-18646.6" + wire $0\SHIFT_ROT_dec31_inv_a[0:0] + attribute \src "libresoc.v:18663.3-18678.6" + wire $0\SHIFT_ROT_dec31_is_32b[0:0] + attribute \src "libresoc.v:18599.3-18614.6" + wire width 2 $0\SHIFT_ROT_dec31_rc_sel[1:0] + attribute \src "libresoc.v:18679.3-18694.6" + wire $0\SHIFT_ROT_dec31_sgn[0:0] + attribute \src "libresoc.v:17949.7-17949.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:18743.3-18758.6" + wire width 3 $1\SHIFT_ROT_dec31_cr_in[2:0] + attribute \src "libresoc.v:18759.3-18774.6" + wire width 3 $1\SHIFT_ROT_dec31_cr_out[2:0] + attribute \src "libresoc.v:18615.3-18630.6" + wire width 2 $1\SHIFT_ROT_dec31_cry_in[1:0] + attribute \src "libresoc.v:18647.3-18662.6" + wire $1\SHIFT_ROT_dec31_cry_out[0:0] + attribute \src "libresoc.v:18695.3-18710.6" + wire width 12 $1\SHIFT_ROT_dec31_function_unit[11:0] + attribute \src "libresoc.v:18727.3-18742.6" + wire width 4 $1\SHIFT_ROT_dec31_in2_sel[3:0] + attribute \src "libresoc.v:18711.3-18726.6" + wire width 7 $1\SHIFT_ROT_dec31_internal_op[6:0] + attribute \src "libresoc.v:18631.3-18646.6" + wire $1\SHIFT_ROT_dec31_inv_a[0:0] + attribute \src "libresoc.v:18663.3-18678.6" + wire $1\SHIFT_ROT_dec31_is_32b[0:0] + attribute \src "libresoc.v:18599.3-18614.6" + wire width 2 $1\SHIFT_ROT_dec31_rc_sel[1:0] + attribute \src "libresoc.v:18679.3-18694.6" + wire $1\SHIFT_ROT_dec31_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 4 \SHIFT_ROT_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \SHIFT_ROT_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \SHIFT_ROT_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 9 \SHIFT_ROT_dec31_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \SHIFT_ROT_dec31_dec_sub24_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \SHIFT_ROT_dec31_dec_sub26_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \SHIFT_ROT_dec31_dec_sub27_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \SHIFT_ROT_dec31_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 3 \SHIFT_ROT_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \SHIFT_ROT_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 8 \SHIFT_ROT_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 10 \SHIFT_ROT_dec31_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 6 \SHIFT_ROT_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 11 \SHIFT_ROT_dec31_sgn + attribute \src "libresoc.v:17949.7-17949.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 12 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:18557.29-18570.4" + cell \SHIFT_ROT_dec31_dec_sub24 \SHIFT_ROT_dec31_dec_sub24 + connect \SHIFT_ROT_dec31_dec_sub24_cr_in \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in + connect \SHIFT_ROT_dec31_dec_sub24_cr_out \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out + connect \SHIFT_ROT_dec31_dec_sub24_cry_in \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in + connect \SHIFT_ROT_dec31_dec_sub24_cry_out \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out + connect \SHIFT_ROT_dec31_dec_sub24_function_unit \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit + connect \SHIFT_ROT_dec31_dec_sub24_in2_sel \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel + connect \SHIFT_ROT_dec31_dec_sub24_internal_op \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op + connect \SHIFT_ROT_dec31_dec_sub24_inv_a \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_inv_a + connect \SHIFT_ROT_dec31_dec_sub24_is_32b \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b + connect \SHIFT_ROT_dec31_dec_sub24_rc_sel \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel + connect \SHIFT_ROT_dec31_dec_sub24_sgn \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn + connect \opcode_in \SHIFT_ROT_dec31_dec_sub24_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:18571.29-18584.4" + cell \SHIFT_ROT_dec31_dec_sub26 \SHIFT_ROT_dec31_dec_sub26 + connect \SHIFT_ROT_dec31_dec_sub26_cr_in \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in + connect \SHIFT_ROT_dec31_dec_sub26_cr_out \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out + connect \SHIFT_ROT_dec31_dec_sub26_cry_in \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in + connect \SHIFT_ROT_dec31_dec_sub26_cry_out \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out + connect \SHIFT_ROT_dec31_dec_sub26_function_unit \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit + connect \SHIFT_ROT_dec31_dec_sub26_in2_sel \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel + connect \SHIFT_ROT_dec31_dec_sub26_internal_op \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op + connect \SHIFT_ROT_dec31_dec_sub26_inv_a \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_inv_a + connect \SHIFT_ROT_dec31_dec_sub26_is_32b \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b + connect \SHIFT_ROT_dec31_dec_sub26_rc_sel \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel + connect \SHIFT_ROT_dec31_dec_sub26_sgn \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn + connect \opcode_in \SHIFT_ROT_dec31_dec_sub26_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:18585.29-18598.4" + cell \SHIFT_ROT_dec31_dec_sub27 \SHIFT_ROT_dec31_dec_sub27 + connect \SHIFT_ROT_dec31_dec_sub27_cr_in \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in + connect \SHIFT_ROT_dec31_dec_sub27_cr_out \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out + connect \SHIFT_ROT_dec31_dec_sub27_cry_in \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in + connect \SHIFT_ROT_dec31_dec_sub27_cry_out \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out + connect \SHIFT_ROT_dec31_dec_sub27_function_unit \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit + connect \SHIFT_ROT_dec31_dec_sub27_in2_sel \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel + connect \SHIFT_ROT_dec31_dec_sub27_internal_op \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op + connect \SHIFT_ROT_dec31_dec_sub27_inv_a \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_inv_a + connect \SHIFT_ROT_dec31_dec_sub27_is_32b \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b + connect \SHIFT_ROT_dec31_dec_sub27_rc_sel \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel + connect \SHIFT_ROT_dec31_dec_sub27_sgn \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn + connect \opcode_in \SHIFT_ROT_dec31_dec_sub27_opcode_in + end + attribute \src "libresoc.v:17949.7-17949.20" + process $proc$libresoc.v:17949$389 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:18599.3-18614.6" + process $proc$libresoc.v:18599$378 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_rc_sel[1:0] $1\SHIFT_ROT_dec31_rc_sel[1:0] + attribute \src "libresoc.v:18600.5-18600.29" + switch \initial + attribute \src "libresoc.v:18600.9-18600.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_rc_sel[1:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_rc_sel[1:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_rc_sel[1:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel + case + assign $1\SHIFT_ROT_dec31_rc_sel[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_rc_sel $0\SHIFT_ROT_dec31_rc_sel[1:0] + end + attribute \src "libresoc.v:18615.3-18630.6" + process $proc$libresoc.v:18615$379 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_cry_in[1:0] $1\SHIFT_ROT_dec31_cry_in[1:0] + attribute \src "libresoc.v:18616.5-18616.29" + switch \initial + attribute \src "libresoc.v:18616.9-18616.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_cry_in[1:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_cry_in[1:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_cry_in[1:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in + case + assign $1\SHIFT_ROT_dec31_cry_in[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_cry_in $0\SHIFT_ROT_dec31_cry_in[1:0] + end + attribute \src "libresoc.v:18631.3-18646.6" + process $proc$libresoc.v:18631$380 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_inv_a[0:0] $1\SHIFT_ROT_dec31_inv_a[0:0] + attribute \src "libresoc.v:18632.5-18632.29" + switch \initial + attribute \src "libresoc.v:18632.9-18632.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_inv_a[0:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_inv_a[0:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_inv_a[0:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_inv_a + case + assign $1\SHIFT_ROT_dec31_inv_a[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_inv_a $0\SHIFT_ROT_dec31_inv_a[0:0] + end + attribute \src "libresoc.v:18647.3-18662.6" + process $proc$libresoc.v:18647$381 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_cry_out[0:0] $1\SHIFT_ROT_dec31_cry_out[0:0] + attribute \src "libresoc.v:18648.5-18648.29" + switch \initial + attribute \src "libresoc.v:18648.9-18648.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_cry_out[0:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_cry_out[0:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_cry_out[0:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out + case + assign $1\SHIFT_ROT_dec31_cry_out[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_cry_out $0\SHIFT_ROT_dec31_cry_out[0:0] + end + attribute \src "libresoc.v:18663.3-18678.6" + process $proc$libresoc.v:18663$382 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_is_32b[0:0] $1\SHIFT_ROT_dec31_is_32b[0:0] + attribute \src "libresoc.v:18664.5-18664.29" + switch \initial + attribute \src "libresoc.v:18664.9-18664.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_is_32b[0:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_is_32b[0:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_is_32b[0:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b + case + assign $1\SHIFT_ROT_dec31_is_32b[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_is_32b $0\SHIFT_ROT_dec31_is_32b[0:0] + end + attribute \src "libresoc.v:18679.3-18694.6" + process $proc$libresoc.v:18679$383 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_sgn[0:0] $1\SHIFT_ROT_dec31_sgn[0:0] + attribute \src "libresoc.v:18680.5-18680.29" + switch \initial + attribute \src "libresoc.v:18680.9-18680.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_sgn[0:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_sgn[0:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_sgn[0:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn + case + assign $1\SHIFT_ROT_dec31_sgn[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_sgn $0\SHIFT_ROT_dec31_sgn[0:0] + end + attribute \src "libresoc.v:18695.3-18710.6" + process $proc$libresoc.v:18695$384 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_function_unit[11:0] $1\SHIFT_ROT_dec31_function_unit[11:0] + attribute \src "libresoc.v:18696.5-18696.29" + switch \initial + attribute \src "libresoc.v:18696.9-18696.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_function_unit[11:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_function_unit[11:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_function_unit[11:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit + case + assign $1\SHIFT_ROT_dec31_function_unit[11:0] 12'000000000000 + end + sync always + update \SHIFT_ROT_dec31_function_unit $0\SHIFT_ROT_dec31_function_unit[11:0] + end + attribute \src "libresoc.v:18711.3-18726.6" + process $proc$libresoc.v:18711$385 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_internal_op[6:0] $1\SHIFT_ROT_dec31_internal_op[6:0] + attribute \src "libresoc.v:18712.5-18712.29" + switch \initial + attribute \src "libresoc.v:18712.9-18712.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_internal_op[6:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_internal_op[6:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_internal_op[6:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op + case + assign $1\SHIFT_ROT_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \SHIFT_ROT_dec31_internal_op $0\SHIFT_ROT_dec31_internal_op[6:0] + end + attribute \src "libresoc.v:18727.3-18742.6" + process $proc$libresoc.v:18727$386 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_in2_sel[3:0] $1\SHIFT_ROT_dec31_in2_sel[3:0] + attribute \src "libresoc.v:18728.5-18728.29" + switch \initial + attribute \src "libresoc.v:18728.9-18728.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_in2_sel[3:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_in2_sel[3:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_in2_sel[3:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel + case + assign $1\SHIFT_ROT_dec31_in2_sel[3:0] 4'0000 + end + sync always + update \SHIFT_ROT_dec31_in2_sel $0\SHIFT_ROT_dec31_in2_sel[3:0] + end + attribute \src "libresoc.v:18743.3-18758.6" + process $proc$libresoc.v:18743$387 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_cr_in[2:0] $1\SHIFT_ROT_dec31_cr_in[2:0] + attribute \src "libresoc.v:18744.5-18744.29" + switch \initial + attribute \src "libresoc.v:18744.9-18744.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_cr_in[2:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_cr_in[2:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_cr_in[2:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in + case + assign $1\SHIFT_ROT_dec31_cr_in[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_cr_in $0\SHIFT_ROT_dec31_cr_in[2:0] + end + attribute \src "libresoc.v:18759.3-18774.6" + process $proc$libresoc.v:18759$388 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_cr_out[2:0] $1\SHIFT_ROT_dec31_cr_out[2:0] + attribute \src "libresoc.v:18760.5-18760.29" + switch \initial + attribute \src "libresoc.v:18760.9-18760.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_cr_out[2:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_cr_out[2:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_cr_out[2:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out + case + assign $1\SHIFT_ROT_dec31_cr_out[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_cr_out $0\SHIFT_ROT_dec31_cr_out[2:0] + end + connect \SHIFT_ROT_dec31_dec_sub24_opcode_in \opcode_in + connect \SHIFT_ROT_dec31_dec_sub27_opcode_in \opcode_in + connect \SHIFT_ROT_dec31_dec_sub26_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:18784.1-19157.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub24" +attribute \generator "nMigen" +module \SHIFT_ROT_dec31_dec_sub24 + attribute \src "libresoc.v:19042.3-19060.6" + wire width 3 $0\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:19061.3-19079.6" + wire width 3 $0\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:19099.3-19117.6" + wire width 2 $0\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:19137.3-19155.6" + wire $0\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:18947.3-18965.6" + wire width 12 $0\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] + attribute \src "libresoc.v:19023.3-19041.6" + wire width 4 $0\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:19004.3-19022.6" + wire width 7 $0\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:19118.3-19136.6" + wire $0\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:18966.3-18984.6" + wire $0\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:19080.3-19098.6" + wire width 2 $0\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:18985.3-19003.6" + wire $0\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] + attribute \src "libresoc.v:18785.7-18785.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:19042.3-19060.6" + wire width 3 $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:19061.3-19079.6" + wire width 3 $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:19099.3-19117.6" + wire width 2 $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:19137.3-19155.6" + wire $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:18947.3-18965.6" + wire width 12 $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] + attribute \src "libresoc.v:19023.3-19041.6" + wire width 4 $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:19004.3-19022.6" + wire width 7 $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:19118.3-19136.6" + wire $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:18966.3-18984.6" + wire $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:19080.3-19098.6" + wire width 2 $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:18985.3-19003.6" + wire $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 4 \SHIFT_ROT_dec31_dec_sub24_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \SHIFT_ROT_dec31_dec_sub24_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \SHIFT_ROT_dec31_dec_sub24_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 9 \SHIFT_ROT_dec31_dec_sub24_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \SHIFT_ROT_dec31_dec_sub24_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 3 \SHIFT_ROT_dec31_dec_sub24_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub24_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 8 \SHIFT_ROT_dec31_dec_sub24_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 10 \SHIFT_ROT_dec31_dec_sub24_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub24_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 11 \SHIFT_ROT_dec31_dec_sub24_sgn + attribute \src "libresoc.v:18785.7-18785.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 12 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:18785.7-18785.20" + process $proc$libresoc.v:18785$401 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:18947.3-18965.6" + process $proc$libresoc.v:18947$390 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] + attribute \src "libresoc.v:18948.5-18948.29" + switch \initial + attribute \src "libresoc.v:18948.9-18948.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] 12'000000001000 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] 12'000000000000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_function_unit $0\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] + end + attribute \src "libresoc.v:18966.3-18984.6" + process $proc$libresoc.v:18966$391 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:18967.5-18967.29" + switch \initial + attribute \src "libresoc.v:18967.9-18967.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_is_32b $0\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] + end + attribute \src "libresoc.v:18985.3-19003.6" + process $proc$libresoc.v:18985$392 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] + attribute \src "libresoc.v:18986.5-18986.29" + switch \initial + attribute \src "libresoc.v:18986.9-18986.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_sgn $0\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] + end + attribute \src "libresoc.v:19004.3-19022.6" + process $proc$libresoc.v:19004$393 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:19005.5-19005.29" + switch \initial + attribute \src "libresoc.v:19005.9-19005.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0111101 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0000000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_internal_op $0\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] + end + attribute \src "libresoc.v:19023.3-19041.6" + process $proc$libresoc.v:19023$394 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:19024.5-19024.29" + switch \initial + attribute \src "libresoc.v:19024.9-19024.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'1011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'0001 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'0000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_in2_sel $0\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] + end + attribute \src "libresoc.v:19042.3-19060.6" + process $proc$libresoc.v:19042$395 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:19043.5-19043.29" + switch \initial + attribute \src "libresoc.v:19043.9-19043.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_cr_in $0\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] + end + attribute \src "libresoc.v:19061.3-19079.6" + process $proc$libresoc.v:19061$396 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:19062.5-19062.29" + switch \initial + attribute \src "libresoc.v:19062.9-19062.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'001 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_cr_out $0\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] + end + attribute \src "libresoc.v:19080.3-19098.6" + process $proc$libresoc.v:19080$397 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:19081.5-19081.29" + switch \initial + attribute \src "libresoc.v:19081.9-19081.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'10 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_rc_sel $0\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] + end + attribute \src "libresoc.v:19099.3-19117.6" + process $proc$libresoc.v:19099$398 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:19100.5-19100.29" + switch \initial + attribute \src "libresoc.v:19100.9-19100.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_cry_in $0\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] + end + attribute \src "libresoc.v:19118.3-19136.6" + process $proc$libresoc.v:19118$399 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:19119.5-19119.29" + switch \initial + attribute \src "libresoc.v:19119.9-19119.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_inv_a $0\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] + end + attribute \src "libresoc.v:19137.3-19155.6" + process $proc$libresoc.v:19137$400 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:19138.5-19138.29" + switch \initial + attribute \src "libresoc.v:19138.9-19138.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_cry_out $0\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:19161.1-19501.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub26" +attribute \generator "nMigen" +module \SHIFT_ROT_dec31_dec_sub26 + attribute \src "libresoc.v:19404.3-19419.6" + wire width 3 $0\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:19420.3-19435.6" + wire width 3 $0\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:19452.3-19467.6" + wire width 2 $0\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:19484.3-19499.6" + wire $0\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:19324.3-19339.6" + wire width 12 $0\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] + attribute \src "libresoc.v:19388.3-19403.6" + wire width 4 $0\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:19372.3-19387.6" + wire width 7 $0\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:19468.3-19483.6" + wire $0\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:19340.3-19355.6" + wire $0\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:19436.3-19451.6" + wire width 2 $0\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:19356.3-19371.6" + wire $0\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:19162.7-19162.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:19404.3-19419.6" + wire width 3 $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:19420.3-19435.6" + wire width 3 $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:19452.3-19467.6" + wire width 2 $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:19484.3-19499.6" + wire $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:19324.3-19339.6" + wire width 12 $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] + attribute \src "libresoc.v:19388.3-19403.6" + wire width 4 $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:19372.3-19387.6" + wire width 7 $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:19468.3-19483.6" + wire $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:19340.3-19355.6" + wire $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:19436.3-19451.6" + wire width 2 $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:19356.3-19371.6" + wire $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 4 \SHIFT_ROT_dec31_dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \SHIFT_ROT_dec31_dec_sub26_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \SHIFT_ROT_dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 9 \SHIFT_ROT_dec31_dec_sub26_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \SHIFT_ROT_dec31_dec_sub26_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 3 \SHIFT_ROT_dec31_dec_sub26_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 8 \SHIFT_ROT_dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 10 \SHIFT_ROT_dec31_dec_sub26_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 11 \SHIFT_ROT_dec31_dec_sub26_sgn + attribute \src "libresoc.v:19162.7-19162.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 12 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:19162.7-19162.20" + process $proc$libresoc.v:19162$413 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:19324.3-19339.6" + process $proc$libresoc.v:19324$402 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] + attribute \src "libresoc.v:19325.5-19325.29" + switch \initial + attribute \src "libresoc.v:19325.9-19325.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] 12'000000001000 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] 12'000000000000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_function_unit $0\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] + end + attribute \src "libresoc.v:19340.3-19355.6" + process $proc$libresoc.v:19340$403 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:19341.5-19341.29" + switch \initial + attribute \src "libresoc.v:19341.9-19341.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_is_32b $0\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] + end + attribute \src "libresoc.v:19356.3-19371.6" + process $proc$libresoc.v:19356$404 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:19357.5-19357.29" + switch \initial + attribute \src "libresoc.v:19357.9-19357.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] 1'1 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_sgn $0\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] + end + attribute \src "libresoc.v:19372.3-19387.6" + process $proc$libresoc.v:19372$405 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:19373.5-19373.29" + switch \initial + attribute \src "libresoc.v:19373.9-19373.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] 7'0100000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] 7'0111101 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] 7'0000000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_internal_op $0\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] + end + attribute \src "libresoc.v:19388.3-19403.6" + process $proc$libresoc.v:19388$406 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:19389.5-19389.29" + switch \initial + attribute \src "libresoc.v:19389.9-19389.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] 4'1010 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] 4'0000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_in2_sel $0\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] + end + attribute \src "libresoc.v:19404.3-19419.6" + process $proc$libresoc.v:19404$407 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:19405.5-19405.29" + switch \initial + attribute \src "libresoc.v:19405.9-19405.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] 3'000 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_cr_in $0\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] + end + attribute \src "libresoc.v:19420.3-19435.6" + process $proc$libresoc.v:19420$408 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:19421.5-19421.29" + switch \initial + attribute \src "libresoc.v:19421.9-19421.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] 3'001 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_cr_out $0\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] + end + attribute \src "libresoc.v:19436.3-19451.6" + process $proc$libresoc.v:19436$409 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:19437.5-19437.29" + switch \initial + attribute \src "libresoc.v:19437.9-19437.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] 2'10 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_rc_sel $0\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] + end + attribute \src "libresoc.v:19452.3-19467.6" + process $proc$libresoc.v:19452$410 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:19453.5-19453.29" + switch \initial + attribute \src "libresoc.v:19453.9-19453.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] 2'00 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_cry_in $0\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] + end + attribute \src "libresoc.v:19468.3-19483.6" + process $proc$libresoc.v:19468$411 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:19469.5-19469.29" + switch \initial + attribute \src "libresoc.v:19469.9-19469.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_inv_a $0\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] + end + attribute \src "libresoc.v:19484.3-19499.6" + process $proc$libresoc.v:19484$412 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:19485.5-19485.29" + switch \initial + attribute \src "libresoc.v:19485.9-19485.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'1 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_cry_out $0\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:19505.1-19878.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub27" +attribute \generator "nMigen" +module \SHIFT_ROT_dec31_dec_sub27 + attribute \src "libresoc.v:19763.3-19781.6" + wire width 3 $0\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:19782.3-19800.6" + wire width 3 $0\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:19820.3-19838.6" + wire width 2 $0\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:19858.3-19876.6" + wire $0\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:19668.3-19686.6" + wire width 12 $0\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] + attribute \src "libresoc.v:19744.3-19762.6" + wire width 4 $0\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:19725.3-19743.6" + wire width 7 $0\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:19839.3-19857.6" + wire $0\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:19687.3-19705.6" + wire $0\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:19801.3-19819.6" + wire width 2 $0\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:19706.3-19724.6" + wire $0\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] + attribute \src "libresoc.v:19506.7-19506.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:19763.3-19781.6" + wire width 3 $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:19782.3-19800.6" + wire width 3 $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:19820.3-19838.6" + wire width 2 $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:19858.3-19876.6" + wire $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:19668.3-19686.6" + wire width 12 $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] + attribute \src "libresoc.v:19744.3-19762.6" + wire width 4 $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:19725.3-19743.6" + wire width 7 $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:19839.3-19857.6" + wire $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:19687.3-19705.6" + wire $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:19801.3-19819.6" + wire width 2 $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:19706.3-19724.6" + wire $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 4 \SHIFT_ROT_dec31_dec_sub27_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \SHIFT_ROT_dec31_dec_sub27_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \SHIFT_ROT_dec31_dec_sub27_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 9 \SHIFT_ROT_dec31_dec_sub27_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \SHIFT_ROT_dec31_dec_sub27_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 3 \SHIFT_ROT_dec31_dec_sub27_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub27_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 8 \SHIFT_ROT_dec31_dec_sub27_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 10 \SHIFT_ROT_dec31_dec_sub27_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub27_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 11 \SHIFT_ROT_dec31_dec_sub27_sgn + attribute \src "libresoc.v:19506.7-19506.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 12 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:19506.7-19506.20" + process $proc$libresoc.v:19506$425 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:19668.3-19686.6" + process $proc$libresoc.v:19668$414 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] + attribute \src "libresoc.v:19669.5-19669.29" + switch \initial + attribute \src "libresoc.v:19669.9-19669.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] 12'000000001000 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] 12'000000000000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_function_unit $0\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] + end + attribute \src "libresoc.v:19687.3-19705.6" + process $proc$libresoc.v:19687$415 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:19688.5-19688.29" + switch \initial + attribute \src "libresoc.v:19688.9-19688.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_is_32b $0\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] + end + attribute \src "libresoc.v:19706.3-19724.6" + process $proc$libresoc.v:19706$416 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] + attribute \src "libresoc.v:19707.5-19707.29" + switch \initial + attribute \src "libresoc.v:19707.9-19707.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_sgn $0\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] + end + attribute \src "libresoc.v:19725.3-19743.6" + process $proc$libresoc.v:19725$417 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:19726.5-19726.29" + switch \initial + attribute \src "libresoc.v:19726.9-19726.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0100000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0111101 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0000000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_internal_op $0\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] + end + attribute \src "libresoc.v:19744.3-19762.6" + process $proc$libresoc.v:19744$418 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:19745.5-19745.29" + switch \initial + attribute \src "libresoc.v:19745.9-19745.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'0001 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'0000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_in2_sel $0\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] + end + attribute \src "libresoc.v:19763.3-19781.6" + process $proc$libresoc.v:19763$419 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:19764.5-19764.29" + switch \initial + attribute \src "libresoc.v:19764.9-19764.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_cr_in $0\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] + end + attribute \src "libresoc.v:19782.3-19800.6" + process $proc$libresoc.v:19782$420 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:19783.5-19783.29" + switch \initial + attribute \src "libresoc.v:19783.9-19783.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'001 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_cr_out $0\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] + end + attribute \src "libresoc.v:19801.3-19819.6" + process $proc$libresoc.v:19801$421 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:19802.5-19802.29" + switch \initial + attribute \src "libresoc.v:19802.9-19802.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'10 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_rc_sel $0\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] + end + attribute \src "libresoc.v:19820.3-19838.6" + process $proc$libresoc.v:19820$422 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:19821.5-19821.29" + switch \initial + attribute \src "libresoc.v:19821.9-19821.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_cry_in $0\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] + end + attribute \src "libresoc.v:19839.3-19857.6" + process $proc$libresoc.v:19839$423 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:19840.5-19840.29" + switch \initial + attribute \src "libresoc.v:19840.9-19840.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_inv_a $0\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] + end + attribute \src "libresoc.v:19858.3-19876.6" + process $proc$libresoc.v:19858$424 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:19859.5-19859.29" + switch \initial + attribute \src "libresoc.v:19859.9-19859.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_cry_out $0\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:19882.1-20204.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec.SPR_dec31" +attribute \generator "nMigen" +module \SPR_dec31 + attribute \src "libresoc.v:20161.3-20170.6" + wire width 3 $0\SPR_dec31_cr_in[2:0] + attribute \src "libresoc.v:20171.3-20180.6" + wire width 3 $0\SPR_dec31_cr_out[2:0] + attribute \src "libresoc.v:20141.3-20150.6" + wire width 12 $0\SPR_dec31_function_unit[11:0] + attribute \src "libresoc.v:20151.3-20160.6" + wire width 7 $0\SPR_dec31_internal_op[6:0] + attribute \src "libresoc.v:20191.3-20200.6" + wire $0\SPR_dec31_is_32b[0:0] + attribute \src "libresoc.v:20181.3-20190.6" + wire width 2 $0\SPR_dec31_rc_sel[1:0] + attribute \src "libresoc.v:19883.7-19883.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:20161.3-20170.6" + wire width 3 $1\SPR_dec31_cr_in[2:0] + attribute \src "libresoc.v:20171.3-20180.6" + wire width 3 $1\SPR_dec31_cr_out[2:0] + attribute \src "libresoc.v:20141.3-20150.6" + wire width 12 $1\SPR_dec31_function_unit[11:0] + attribute \src "libresoc.v:20151.3-20160.6" + wire width 7 $1\SPR_dec31_internal_op[6:0] + attribute \src "libresoc.v:20191.3-20200.6" + wire $1\SPR_dec31_is_32b[0:0] + attribute \src "libresoc.v:20181.3-20190.6" + wire width 2 $1\SPR_dec31_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 3 \SPR_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 4 \SPR_dec31_cr_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \SPR_dec31_dec_sub19_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \SPR_dec31_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \SPR_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 6 \SPR_dec31_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 5 \SPR_dec31_rc_sel + attribute \src "libresoc.v:19883.7-19883.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 7 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:20132.23-20140.4" + cell \SPR_dec31_dec_sub19 \SPR_dec31_dec_sub19 + connect \SPR_dec31_dec_sub19_cr_in \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in + connect \SPR_dec31_dec_sub19_cr_out \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out + connect \SPR_dec31_dec_sub19_function_unit \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit + connect \SPR_dec31_dec_sub19_internal_op \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op + connect \SPR_dec31_dec_sub19_is_32b \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b + connect \SPR_dec31_dec_sub19_rc_sel \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel + connect \opcode_in \SPR_dec31_dec_sub19_opcode_in + end + attribute \src "libresoc.v:19883.7-19883.20" + process $proc$libresoc.v:19883$432 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:20141.3-20150.6" + process $proc$libresoc.v:20141$426 + assign { } { } + assign { } { } + assign $0\SPR_dec31_function_unit[11:0] $1\SPR_dec31_function_unit[11:0] + attribute \src "libresoc.v:20142.5-20142.29" + switch \initial + attribute \src "libresoc.v:20142.9-20142.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\SPR_dec31_function_unit[11:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit + case + assign $1\SPR_dec31_function_unit[11:0] 12'000000000000 + end + sync always + update \SPR_dec31_function_unit $0\SPR_dec31_function_unit[11:0] + end + attribute \src "libresoc.v:20151.3-20160.6" + process $proc$libresoc.v:20151$427 + assign { } { } + assign { } { } + assign $0\SPR_dec31_internal_op[6:0] $1\SPR_dec31_internal_op[6:0] + attribute \src "libresoc.v:20152.5-20152.29" + switch \initial + attribute \src "libresoc.v:20152.9-20152.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\SPR_dec31_internal_op[6:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op + case + assign $1\SPR_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \SPR_dec31_internal_op $0\SPR_dec31_internal_op[6:0] + end + attribute \src "libresoc.v:20161.3-20170.6" + process $proc$libresoc.v:20161$428 + assign { } { } + assign { } { } + assign $0\SPR_dec31_cr_in[2:0] $1\SPR_dec31_cr_in[2:0] + attribute \src "libresoc.v:20162.5-20162.29" + switch \initial + attribute \src "libresoc.v:20162.9-20162.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\SPR_dec31_cr_in[2:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in + case + assign $1\SPR_dec31_cr_in[2:0] 3'000 + end + sync always + update \SPR_dec31_cr_in $0\SPR_dec31_cr_in[2:0] + end + attribute \src "libresoc.v:20171.3-20180.6" + process $proc$libresoc.v:20171$429 + assign { } { } + assign { } { } + assign $0\SPR_dec31_cr_out[2:0] $1\SPR_dec31_cr_out[2:0] + attribute \src "libresoc.v:20172.5-20172.29" + switch \initial + attribute \src "libresoc.v:20172.9-20172.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\SPR_dec31_cr_out[2:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out + case + assign $1\SPR_dec31_cr_out[2:0] 3'000 + end + sync always + update \SPR_dec31_cr_out $0\SPR_dec31_cr_out[2:0] + end + attribute \src "libresoc.v:20181.3-20190.6" + process $proc$libresoc.v:20181$430 + assign { } { } + assign { } { } + assign $0\SPR_dec31_rc_sel[1:0] $1\SPR_dec31_rc_sel[1:0] + attribute \src "libresoc.v:20182.5-20182.29" + switch \initial + attribute \src "libresoc.v:20182.9-20182.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\SPR_dec31_rc_sel[1:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel + case + assign $1\SPR_dec31_rc_sel[1:0] 2'00 + end + sync always + update \SPR_dec31_rc_sel $0\SPR_dec31_rc_sel[1:0] + end + attribute \src "libresoc.v:20191.3-20200.6" + process $proc$libresoc.v:20191$431 + assign { } { } + assign { } { } + assign $0\SPR_dec31_is_32b[0:0] $1\SPR_dec31_is_32b[0:0] + attribute \src "libresoc.v:20192.5-20192.29" + switch \initial + attribute \src "libresoc.v:20192.9-20192.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\SPR_dec31_is_32b[0:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b + case + assign $1\SPR_dec31_is_32b[0:0] 1'0 + end + sync always + update \SPR_dec31_is_32b $0\SPR_dec31_is_32b[0:0] + end + connect \SPR_dec31_dec_sub19_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:20208.1-20416.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec.SPR_dec31.SPR_dec31_dec_sub19" +attribute \generator "nMigen" +module \SPR_dec31_dec_sub19 + attribute \src "libresoc.v:20363.3-20375.6" + wire width 3 $0\SPR_dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:20376.3-20388.6" + wire width 3 $0\SPR_dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:20337.3-20349.6" + wire width 12 $0\SPR_dec31_dec_sub19_function_unit[11:0] + attribute \src "libresoc.v:20350.3-20362.6" + wire width 7 $0\SPR_dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:20402.3-20414.6" + wire $0\SPR_dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:20389.3-20401.6" + wire width 2 $0\SPR_dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:20209.7-20209.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:20363.3-20375.6" + wire width 3 $1\SPR_dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:20376.3-20388.6" + wire width 3 $1\SPR_dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:20337.3-20349.6" + wire width 12 $1\SPR_dec31_dec_sub19_function_unit[11:0] + attribute \src "libresoc.v:20350.3-20362.6" + wire width 7 $1\SPR_dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:20402.3-20414.6" + wire $1\SPR_dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:20389.3-20401.6" + wire width 2 $1\SPR_dec31_dec_sub19_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 3 \SPR_dec31_dec_sub19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 4 \SPR_dec31_dec_sub19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \SPR_dec31_dec_sub19_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \SPR_dec31_dec_sub19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 6 \SPR_dec31_dec_sub19_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 5 \SPR_dec31_dec_sub19_rc_sel + attribute \src "libresoc.v:20209.7-20209.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 7 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:20209.7-20209.20" + process $proc$libresoc.v:20209$439 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:20337.3-20349.6" + process $proc$libresoc.v:20337$433 + assign { } { } + assign { } { } + assign $0\SPR_dec31_dec_sub19_function_unit[11:0] $1\SPR_dec31_dec_sub19_function_unit[11:0] + attribute \src "libresoc.v:20338.5-20338.29" + switch \initial + attribute \src "libresoc.v:20338.9-20338.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\SPR_dec31_dec_sub19_function_unit[11:0] 12'010000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\SPR_dec31_dec_sub19_function_unit[11:0] 12'010000000000 + case + assign $1\SPR_dec31_dec_sub19_function_unit[11:0] 12'000000000000 + end + sync always + update \SPR_dec31_dec_sub19_function_unit $0\SPR_dec31_dec_sub19_function_unit[11:0] + end + attribute \src "libresoc.v:20350.3-20362.6" + process $proc$libresoc.v:20350$434 + assign { } { } + assign { } { } + assign $0\SPR_dec31_dec_sub19_internal_op[6:0] $1\SPR_dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:20351.5-20351.29" + switch \initial + attribute \src "libresoc.v:20351.9-20351.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\SPR_dec31_dec_sub19_internal_op[6:0] 7'0101110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\SPR_dec31_dec_sub19_internal_op[6:0] 7'0110001 + case + assign $1\SPR_dec31_dec_sub19_internal_op[6:0] 7'0000000 + end + sync always + update \SPR_dec31_dec_sub19_internal_op $0\SPR_dec31_dec_sub19_internal_op[6:0] + end + attribute \src "libresoc.v:20363.3-20375.6" + process $proc$libresoc.v:20363$435 + assign { } { } + assign { } { } + assign $0\SPR_dec31_dec_sub19_cr_in[2:0] $1\SPR_dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:20364.5-20364.29" + switch \initial + attribute \src "libresoc.v:20364.9-20364.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\SPR_dec31_dec_sub19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\SPR_dec31_dec_sub19_cr_in[2:0] 3'000 + case + assign $1\SPR_dec31_dec_sub19_cr_in[2:0] 3'000 + end + sync always + update \SPR_dec31_dec_sub19_cr_in $0\SPR_dec31_dec_sub19_cr_in[2:0] + end + attribute \src "libresoc.v:20376.3-20388.6" + process $proc$libresoc.v:20376$436 + assign { } { } + assign { } { } + assign $0\SPR_dec31_dec_sub19_cr_out[2:0] $1\SPR_dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:20377.5-20377.29" + switch \initial + attribute \src "libresoc.v:20377.9-20377.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\SPR_dec31_dec_sub19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\SPR_dec31_dec_sub19_cr_out[2:0] 3'000 + case + assign $1\SPR_dec31_dec_sub19_cr_out[2:0] 3'000 + end + sync always + update \SPR_dec31_dec_sub19_cr_out $0\SPR_dec31_dec_sub19_cr_out[2:0] + end + attribute \src "libresoc.v:20389.3-20401.6" + process $proc$libresoc.v:20389$437 + assign { } { } + assign { } { } + assign $0\SPR_dec31_dec_sub19_rc_sel[1:0] $1\SPR_dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:20390.5-20390.29" + switch \initial + attribute \src "libresoc.v:20390.9-20390.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\SPR_dec31_dec_sub19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\SPR_dec31_dec_sub19_rc_sel[1:0] 2'00 + case + assign $1\SPR_dec31_dec_sub19_rc_sel[1:0] 2'00 + end + sync always + update \SPR_dec31_dec_sub19_rc_sel $0\SPR_dec31_dec_sub19_rc_sel[1:0] + end + attribute \src "libresoc.v:20402.3-20414.6" + process $proc$libresoc.v:20402$438 + assign { } { } + assign { } { } + assign $0\SPR_dec31_dec_sub19_is_32b[0:0] $1\SPR_dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:20403.5-20403.29" + switch \initial + attribute \src "libresoc.v:20403.9-20403.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\SPR_dec31_dec_sub19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\SPR_dec31_dec_sub19_is_32b[0:0] 1'0 + case + assign $1\SPR_dec31_dec_sub19_is_32b[0:0] 1'0 + end + sync always + update \SPR_dec31_dec_sub19_is_32b $0\SPR_dec31_dec_sub19_is_32b[0:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:20420.1-20692.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.jtag._fsm" +attribute \generator "nMigen" +module \_fsm + attribute \src "libresoc.v:20540.3-20654.6" + wire width 4 $0\fsm_state$next[3:0]$464 + attribute \src "libresoc.v:20506.3-20507.35" + wire width 4 $0\fsm_state[3:0] + attribute \src "libresoc.v:20421.7-20421.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:20512.3-20539.6" + wire $0\isdr$next[0:0]$460 + attribute \src "libresoc.v:20508.3-20509.25" + wire $0\isdr[0:0] + attribute \src "libresoc.v:20655.3-20682.6" + wire $0\isir$next[0:0]$477 + attribute \src "libresoc.v:20510.3-20511.25" + wire $0\isir[0:0] + attribute \src "libresoc.v:20540.3-20654.6" + wire width 4 $10\fsm_state$next[3:0]$474 + attribute \src "libresoc.v:20540.3-20654.6" + wire width 4 $11\fsm_state$next[3:0]$475 + attribute \src "libresoc.v:20540.3-20654.6" + wire width 4 $1\fsm_state$next[3:0]$465 + attribute \src "libresoc.v:20461.13-20461.29" + wire width 4 $1\fsm_state[3:0] + attribute \src "libresoc.v:20512.3-20539.6" + wire $1\isdr$next[0:0]$461 + attribute \src "libresoc.v:20466.7-20466.18" + wire $1\isdr[0:0] + attribute \src "libresoc.v:20655.3-20682.6" + wire $1\isir$next[0:0]$478 + attribute \src "libresoc.v:20471.7-20471.18" + wire $1\isir[0:0] + attribute \src "libresoc.v:20540.3-20654.6" + wire width 4 $2\fsm_state$next[3:0]$466 + attribute \src "libresoc.v:20512.3-20539.6" + wire $2\isdr$next[0:0]$462 + attribute \src "libresoc.v:20655.3-20682.6" + wire $2\isir$next[0:0]$479 + attribute \src "libresoc.v:20540.3-20654.6" + wire width 4 $3\fsm_state$next[3:0]$467 + attribute \src "libresoc.v:20540.3-20654.6" + wire width 4 $4\fsm_state$next[3:0]$468 + attribute \src "libresoc.v:20540.3-20654.6" + wire width 4 $5\fsm_state$next[3:0]$469 + attribute \src "libresoc.v:20540.3-20654.6" + wire width 4 $6\fsm_state$next[3:0]$470 + attribute \src "libresoc.v:20540.3-20654.6" + wire width 4 $7\fsm_state$next[3:0]$471 + attribute \src "libresoc.v:20540.3-20654.6" + wire width 4 $8\fsm_state$next[3:0]$472 + attribute \src "libresoc.v:20540.3-20654.6" + wire width 4 $9\fsm_state$next[3:0]$473 + attribute \src "libresoc.v:20490.17-20490.110" + wire $eq$libresoc.v:20490$440_Y + attribute \src "libresoc.v:20491.18-20491.111" + wire $eq$libresoc.v:20491$441_Y + attribute \src "libresoc.v:20492.18-20492.111" + wire $eq$libresoc.v:20492$442_Y + attribute \src "libresoc.v:20493.18-20493.111" + wire $eq$libresoc.v:20493$443_Y + attribute \src "libresoc.v:20494.18-20494.111" + wire $eq$libresoc.v:20494$444_Y + attribute \src "libresoc.v:20495.17-20495.108" + wire $eq$libresoc.v:20495$445_Y + attribute \src "libresoc.v:20496.18-20496.111" + wire $eq$libresoc.v:20496$446_Y + attribute \src "libresoc.v:20497.18-20497.111" + wire $eq$libresoc.v:20497$447_Y + attribute \src "libresoc.v:20498.18-20498.111" + wire $eq$libresoc.v:20498$448_Y + attribute \src "libresoc.v:20499.18-20499.111" + wire $eq$libresoc.v:20499$449_Y + attribute \src "libresoc.v:20500.18-20500.111" + wire $eq$libresoc.v:20500$450_Y + attribute \src "libresoc.v:20501.18-20501.111" + wire $eq$libresoc.v:20501$451_Y + attribute \src "libresoc.v:20502.18-20502.112" + wire $eq$libresoc.v:20502$452_Y + attribute \src "libresoc.v:20503.17-20503.108" + wire $eq$libresoc.v:20503$453_Y + attribute \src "libresoc.v:20504.17-20504.108" + wire $eq$libresoc.v:20504$454_Y + attribute \src "libresoc.v:20505.17-20505.108" + wire $eq$libresoc.v:20505$455_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:113" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 9 \TAP_bus__tck + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 10 \TAP_bus__tms + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" + wire output 1 \capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" + wire width 4 \fsm_state + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" + wire width 4 \fsm_state$next + attribute \src "libresoc.v:20421.7-20421.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" + wire output 11 \isdr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" + wire \isdr$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" + wire output 4 \isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" + wire \isir$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:49" + wire \local_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire output 8 \negjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire output 6 \negjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire output 7 \posjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire output 5 \posjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:36" + wire \rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" + wire output 2 \shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" + wire output 3 \update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" + cell $eq $eq$libresoc.v:20490$440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:20490$440_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" + cell $eq $eq$libresoc.v:20491$441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:20491$441_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" + cell $eq $eq$libresoc.v:20492$442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:20492$442_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" + cell $eq $eq$libresoc.v:20493$443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'1 + connect \Y $eq$libresoc.v:20493$443_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" + cell $eq $eq$libresoc.v:20494$444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:20494$444_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:113" + cell $eq $eq$libresoc.v:20495$445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 1'0 + connect \Y $eq$libresoc.v:20495$445_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" + cell $eq $eq$libresoc.v:20496$446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:20496$446_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" + cell $eq $eq$libresoc.v:20497$447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:20497$447_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" + cell $eq $eq$libresoc.v:20498$448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'1 + connect \Y $eq$libresoc.v:20498$448_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" + cell $eq $eq$libresoc.v:20499$449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:20499$449_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" + cell $eq $eq$libresoc.v:20500$450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'1 + connect \Y $eq$libresoc.v:20500$450_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" + cell $eq $eq$libresoc.v:20501$451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:20501$451_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" + cell $eq $eq$libresoc.v:20502$452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:20502$452_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" + cell $eq $eq$libresoc.v:20503$453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 2'11 + connect \Y $eq$libresoc.v:20503$453_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" + cell $eq $eq$libresoc.v:20504$454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 3'101 + connect \Y $eq$libresoc.v:20504$454_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" + cell $eq $eq$libresoc.v:20505$455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 4'1000 + connect \Y $eq$libresoc.v:20505$455_Y + end + attribute \src "libresoc.v:20421.7-20421.20" + process $proc$libresoc.v:20421$480 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:20461.13-20461.29" + process $proc$libresoc.v:20461$481 + assign { } { } + assign $1\fsm_state[3:0] 4'0000 + sync always + sync init + update \fsm_state $1\fsm_state[3:0] + end + attribute \src "libresoc.v:20466.7-20466.18" + process $proc$libresoc.v:20466$482 + assign { } { } + assign $1\isdr[0:0] 1'0 + sync always + sync init + update \isdr $1\isdr[0:0] + end + attribute \src "libresoc.v:20471.7-20471.18" + process $proc$libresoc.v:20471$483 + assign { } { } + assign $1\isir[0:0] 1'0 + sync always + sync init + update \isir $1\isir[0:0] + end + attribute \src "libresoc.v:20506.3-20507.35" + process $proc$libresoc.v:20506$456 + assign { } { } + assign $0\fsm_state[3:0] \fsm_state$next + sync posedge \local_clk + update \fsm_state $0\fsm_state[3:0] + end + attribute \src "libresoc.v:20508.3-20509.25" + process $proc$libresoc.v:20508$457 + assign { } { } + assign $0\isdr[0:0] \isdr$next + sync posedge \local_clk + update \isdr $0\isdr[0:0] + end + attribute \src "libresoc.v:20510.3-20511.25" + process $proc$libresoc.v:20510$458 + assign { } { } + assign $0\isir[0:0] \isir$next + sync posedge \local_clk + update \isir $0\isir[0:0] + end + attribute \src "libresoc.v:20512.3-20539.6" + process $proc$libresoc.v:20512$459 + assign { } { } + assign { } { } + assign $0\isdr$next[0:0]$460 $1\isdr$next[0:0]$461 + attribute \src "libresoc.v:20513.5-20513.29" + switch \initial + attribute \src "libresoc.v:20513.9-20513.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\isdr$next[0:0]$461 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\isdr$next[0:0]$461 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\isdr$next[0:0]$461 $2\isdr$next[0:0]$462 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" + switch \$11 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\isdr$next[0:0]$462 1'1 + case + assign $2\isdr$next[0:0]$462 \isdr + end + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\isdr$next[0:0]$461 1'0 + case + assign $1\isdr$next[0:0]$461 \isdr + end + sync always + update \isdr$next $0\isdr$next[0:0]$460 + end + attribute \src "libresoc.v:20540.3-20654.6" + process $proc$libresoc.v:20540$463 + assign { } { } + assign { } { } + assign $0\fsm_state$next[3:0]$464 $1\fsm_state$next[3:0]$465 + attribute \src "libresoc.v:20541.5-20541.29" + switch \initial + attribute \src "libresoc.v:20541.9-20541.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\fsm_state$next[3:0]$465 $2\fsm_state$next[3:0]$466 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fsm_state$next[3:0]$466 4'0001 + case + assign $2\fsm_state$next[3:0]$466 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\fsm_state$next[3:0]$465 $3\fsm_state$next[3:0]$467 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fsm_state$next[3:0]$467 4'0010 + case + assign $3\fsm_state$next[3:0]$467 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\fsm_state$next[3:0]$465 $4\fsm_state$next[3:0]$468 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" + switch \$17 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$next[3:0]$468 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\fsm_state$next[3:0]$468 4'0100 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\fsm_state$next[3:0]$465 $5\fsm_state$next[3:0]$469 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fsm_state$next[3:0]$469 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $5\fsm_state$next[3:0]$469 4'0000 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\fsm_state$next[3:0]$465 $6\fsm_state$next[3:0]$470 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" + switch \$21 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\fsm_state$next[3:0]$470 4'0101 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $6\fsm_state$next[3:0]$470 4'0110 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\fsm_state$next[3:0]$465 $7\fsm_state$next[3:0]$471 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" + switch \$23 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\fsm_state$next[3:0]$471 4'0110 + case + assign $7\fsm_state$next[3:0]$471 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\fsm_state$next[3:0]$465 $8\fsm_state$next[3:0]$472 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\fsm_state$next[3:0]$472 4'0111 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $8\fsm_state$next[3:0]$472 4'1000 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\fsm_state$next[3:0]$465 $9\fsm_state$next[3:0]$473 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\fsm_state$next[3:0]$473 4'1001 + case + assign $9\fsm_state$next[3:0]$473 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\fsm_state$next[3:0]$465 $10\fsm_state$next[3:0]$474 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $10\fsm_state$next[3:0]$474 4'0101 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $10\fsm_state$next[3:0]$474 4'1000 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\fsm_state$next[3:0]$465 $11\fsm_state$next[3:0]$475 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" + switch \$31 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $11\fsm_state$next[3:0]$475 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $11\fsm_state$next[3:0]$475 4'0010 + end + case + assign $1\fsm_state$next[3:0]$465 \fsm_state + end + sync always + update \fsm_state$next $0\fsm_state$next[3:0]$464 + end + attribute \src "libresoc.v:20655.3-20682.6" + process $proc$libresoc.v:20655$476 + assign { } { } + assign { } { } + assign $0\isir$next[0:0]$477 $1\isir$next[0:0]$478 + attribute \src "libresoc.v:20656.5-20656.29" + switch \initial + attribute \src "libresoc.v:20656.9-20656.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\isir$next[0:0]$478 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\isir$next[0:0]$478 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\isir$next[0:0]$478 $2\isir$next[0:0]$479 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\isir$next[0:0]$479 1'1 + case + assign $2\isir$next[0:0]$479 \isir + end + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\isir$next[0:0]$478 1'0 + case + assign $1\isir$next[0:0]$478 \isir + end + sync always + update \isir$next $0\isir$next[0:0]$477 + end + connect \$9 $eq$libresoc.v:20490$440_Y + connect \$11 $eq$libresoc.v:20491$441_Y + connect \$13 $eq$libresoc.v:20492$442_Y + connect \$15 $eq$libresoc.v:20493$443_Y + connect \$17 $eq$libresoc.v:20494$444_Y + connect \$1 $eq$libresoc.v:20495$445_Y + connect \$19 $eq$libresoc.v:20496$446_Y + connect \$21 $eq$libresoc.v:20497$447_Y + connect \$23 $eq$libresoc.v:20498$448_Y + connect \$25 $eq$libresoc.v:20499$449_Y + connect \$27 $eq$libresoc.v:20500$450_Y + connect \$29 $eq$libresoc.v:20501$451_Y + connect \$31 $eq$libresoc.v:20502$452_Y + connect \$3 $eq$libresoc.v:20503$453_Y + connect \$5 $eq$libresoc.v:20504$454_Y + connect \$7 $eq$libresoc.v:20505$455_Y + connect \update \$7 + connect \shift \$5 + connect \capture \$3 + connect \rst \$1 + connect \local_clk \TAP_bus__tck + connect \negjtag_rst \rst + connect \negjtag_clk \TAP_bus__tck + connect \posjtag_rst \rst + connect \posjtag_clk \TAP_bus__tck +end +attribute \src "libresoc.v:20696.1-20768.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.jtag._idblock" +attribute \generator "nMigen" +module \_idblock + attribute \src "libresoc.v:20741.3-20761.6" + wire width 32 $0\TAP_id_sr$next[31:0]$489 + attribute \src "libresoc.v:20739.3-20740.35" + wire width 32 $0\TAP_id_sr[31:0] + attribute \src "libresoc.v:20697.7-20697.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:20741.3-20761.6" + wire width 32 $1\TAP_id_sr$next[31:0]$490 + attribute \src "libresoc.v:20707.14-20707.31" + wire width 32 $1\TAP_id_sr[31:0] + attribute \src "libresoc.v:20741.3-20761.6" + wire width 32 $2\TAP_id_sr$next[31:0]$491 + attribute \src "libresoc.v:20736.17-20736.110" + wire $and$libresoc.v:20736$484_Y + attribute \src "libresoc.v:20737.17-20737.108" + wire $and$libresoc.v:20737$485_Y + attribute \src "libresoc.v:20738.17-20738.109" + wire $and$libresoc.v:20738$486_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 5 \TAP_bus__tdi + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:236" + wire width 32 \TAP_id_sr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:236" + wire width 32 \TAP_id_sr$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:225" + wire output 6 \TAP_id_tdo + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:243" + wire \_bypass + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:240" + wire \_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:241" + wire \_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:239" + wire \_tdi + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:242" + wire \_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" + wire input 2 \capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375" + wire input 1 \id_bypass + attribute \src "libresoc.v:20697.7-20697.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire input 8 \posjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire input 7 \posjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" + wire input 9 \select_id + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" + wire input 3 \shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" + wire input 4 \update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" + cell $and $and$libresoc.v:20736$484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \select_id + connect \B \capture + connect \Y $and$libresoc.v:20736$484_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" + cell $and $and$libresoc.v:20737$485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \select_id + connect \B \shift + connect \Y $and$libresoc.v:20737$485_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" + cell $and $and$libresoc.v:20738$486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \select_id + connect \B \update + connect \Y $and$libresoc.v:20738$486_Y + end + attribute \src "libresoc.v:20697.7-20697.20" + process $proc$libresoc.v:20697$492 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:20707.14-20707.31" + process $proc$libresoc.v:20707$493 + assign { } { } + assign $1\TAP_id_sr[31:0] 0 + sync always + sync init + update \TAP_id_sr $1\TAP_id_sr[31:0] + end + attribute \src "libresoc.v:20739.3-20740.35" + process $proc$libresoc.v:20739$487 + assign { } { } + assign $0\TAP_id_sr[31:0] \TAP_id_sr$next + sync posedge \posjtag_clk + update \TAP_id_sr $0\TAP_id_sr[31:0] + end + attribute \src "libresoc.v:20741.3-20761.6" + process $proc$libresoc.v:20741$488 + assign { } { } + assign { } { } + assign $0\TAP_id_sr$next[31:0]$489 $1\TAP_id_sr$next[31:0]$490 + attribute \src "libresoc.v:20742.5-20742.29" + switch \initial + attribute \src "libresoc.v:20742.9-20742.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:254" + switch { \_shift \_capture } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\TAP_id_sr$next[31:0]$490 6399 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\TAP_id_sr$next[31:0]$490 $2\TAP_id_sr$next[31:0]$491 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:257" + switch \_bypass + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\TAP_id_sr$next[31:0]$491 [31:1] \TAP_id_sr [31:1] + assign $2\TAP_id_sr$next[31:0]$491 [0] \_tdi + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\TAP_id_sr$next[31:0]$491 { \_tdi \TAP_id_sr [31:1] } + end + case + assign $1\TAP_id_sr$next[31:0]$490 \TAP_id_sr + end + sync always + update \TAP_id_sr$next $0\TAP_id_sr$next[31:0]$489 + end + connect \$1 $and$libresoc.v:20736$484_Y + connect \$3 $and$libresoc.v:20737$485_Y + connect \$5 $and$libresoc.v:20738$486_Y + connect \TAP_id_tdo \TAP_id_sr [0] + connect \_bypass \id_bypass + connect \_update \$5 + connect \_shift \$3 + connect \_capture \$1 + connect \_tdi \TAP_bus__tdi +end +attribute \src "libresoc.v:20772.1-20856.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.jtag._irblock" +attribute \generator "nMigen" +module \_irblock + attribute \src "libresoc.v:20773.7-20773.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:20834.3-20854.6" + wire width 4 $0\ir$next[3:0]$506 + attribute \src "libresoc.v:20817.3-20818.21" + wire width 4 $0\ir[3:0] + attribute \src "libresoc.v:20821.3-20833.6" + wire width 4 $0\shift_ir$next[3:0]$503 + attribute \src "libresoc.v:20819.3-20820.33" + wire width 4 $0\shift_ir[3:0] + attribute \src "libresoc.v:20834.3-20854.6" + wire width 4 $1\ir$next[3:0]$507 + attribute \src "libresoc.v:20792.13-20792.22" + wire width 4 $1\ir[3:0] + attribute \src "libresoc.v:20821.3-20833.6" + wire width 4 $1\shift_ir$next[3:0]$504 + attribute \src "libresoc.v:20804.13-20804.28" + wire width 4 $1\shift_ir[3:0] + attribute \src "libresoc.v:20834.3-20854.6" + wire width 4 $2\ir$next[3:0]$508 + attribute \src "libresoc.v:20811.17-20811.103" + wire $and$libresoc.v:20811$494_Y + attribute \src "libresoc.v:20812.18-20812.105" + wire $and$libresoc.v:20812$495_Y + attribute \src "libresoc.v:20813.17-20813.105" + wire $and$libresoc.v:20813$496_Y + attribute \src "libresoc.v:20814.17-20814.103" + wire $and$libresoc.v:20814$497_Y + attribute \src "libresoc.v:20815.17-20815.104" + wire $and$libresoc.v:20815$498_Y + attribute \src "libresoc.v:20816.17-20816.105" + wire $and$libresoc.v:20816$499_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 4 \TAP_bus__tdi + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" + wire input 1 \capture + attribute \src "libresoc.v:20773.7-20773.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" + wire width 4 output 9 \ir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" + wire width 4 \ir$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" + wire input 5 \isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire input 8 \posjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire input 7 \posjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" + wire input 2 \shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:138" + wire width 4 \shift_ir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:138" + wire width 4 \shift_ir$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" + wire output 6 \tdo + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" + wire input 3 \update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" + cell $and $and$libresoc.v:20811$494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \shift + connect \Y $and$libresoc.v:20811$494_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" + cell $and $and$libresoc.v:20812$495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \update + connect \Y $and$libresoc.v:20812$495_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" + cell $and $and$libresoc.v:20813$496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \capture + connect \Y $and$libresoc.v:20813$496_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" + cell $and $and$libresoc.v:20814$497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \shift + connect \Y $and$libresoc.v:20814$497_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" + cell $and $and$libresoc.v:20815$498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \update + connect \Y $and$libresoc.v:20815$498_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" + cell $and $and$libresoc.v:20816$499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \capture + connect \Y $and$libresoc.v:20816$499_Y + end + attribute \src "libresoc.v:20773.7-20773.20" + process $proc$libresoc.v:20773$509 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:20792.13-20792.22" + process $proc$libresoc.v:20792$510 + assign { } { } + assign $1\ir[3:0] 4'0001 + sync always + sync init + update \ir $1\ir[3:0] + end + attribute \src "libresoc.v:20804.13-20804.28" + process $proc$libresoc.v:20804$511 + assign { } { } + assign $1\shift_ir[3:0] 4'0000 + sync always + sync init + update \shift_ir $1\shift_ir[3:0] + end + attribute \src "libresoc.v:20817.3-20818.21" + process $proc$libresoc.v:20817$500 + assign { } { } + assign $0\ir[3:0] \ir$next + sync posedge \posjtag_clk + update \ir $0\ir[3:0] + end + attribute \src "libresoc.v:20819.3-20820.33" + process $proc$libresoc.v:20819$501 + assign { } { } + assign $0\shift_ir[3:0] \shift_ir$next + sync posedge \posjtag_clk + update \shift_ir $0\shift_ir[3:0] + end + attribute \src "libresoc.v:20821.3-20833.6" + process $proc$libresoc.v:20821$502 + assign { } { } + assign { } { } + assign $0\shift_ir$next[3:0]$503 $1\shift_ir$next[3:0]$504 + attribute \src "libresoc.v:20822.5-20822.29" + switch \initial + attribute \src "libresoc.v:20822.9-20822.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:141" + switch { \$5 \$3 \$1 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\shift_ir$next[3:0]$504 \ir + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $1\shift_ir$next[3:0]$504 { \TAP_bus__tdi \shift_ir [3:1] } + case + assign $1\shift_ir$next[3:0]$504 \shift_ir + end + sync always + update \shift_ir$next $0\shift_ir$next[3:0]$503 + end + attribute \src "libresoc.v:20834.3-20854.6" + process $proc$libresoc.v:20834$505 + assign { } { } + assign { } { } + assign { } { } + assign $0\ir$next[3:0]$506 $2\ir$next[3:0]$508 + attribute \src "libresoc.v:20835.5-20835.29" + switch \initial + attribute \src "libresoc.v:20835.9-20835.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:141" + switch { \$11 \$9 \$7 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $1\ir$next[3:0]$507 \ir + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $1\ir$next[3:0]$507 \ir + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $1\ir$next[3:0]$507 \shift_ir + case + assign $1\ir$next[3:0]$507 \ir + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ir$next[3:0]$508 4'0001 + case + assign $2\ir$next[3:0]$508 $1\ir$next[3:0]$507 + end + sync always + update \ir$next $0\ir$next[3:0]$506 + end + connect \$9 $and$libresoc.v:20811$494_Y + connect \$11 $and$libresoc.v:20812$495_Y + connect \$1 $and$libresoc.v:20813$496_Y + connect \$3 $and$libresoc.v:20814$497_Y + connect \$5 $and$libresoc.v:20815$498_Y + connect \$7 $and$libresoc.v:20816$499_Y + connect \tdo \ir [0] +end +attribute \src "libresoc.v:20860.1-20918.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.adr_l" +attribute \generator "nMigen" +module \adr_l + attribute \src "libresoc.v:20861.7-20861.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:20906.3-20914.6" + wire $0\q_int$next[0:0]$522 + attribute \src "libresoc.v:20904.3-20905.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:20906.3-20914.6" + wire $1\q_int$next[0:0]$523 + attribute \src "libresoc.v:20885.7-20885.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:20896.17-20896.96" + wire $and$libresoc.v:20896$512_Y + attribute \src "libresoc.v:20901.17-20901.96" + wire $and$libresoc.v:20901$517_Y + attribute \src "libresoc.v:20898.18-20898.93" + wire $not$libresoc.v:20898$514_Y + attribute \src "libresoc.v:20900.17-20900.92" + wire $not$libresoc.v:20900$516_Y + attribute \src "libresoc.v:20903.17-20903.92" + wire $not$libresoc.v:20903$519_Y + attribute \src "libresoc.v:20897.18-20897.98" + wire $or$libresoc.v:20897$513_Y + attribute \src "libresoc.v:20899.18-20899.99" + wire $or$libresoc.v:20899$515_Y + attribute \src "libresoc.v:20902.17-20902.97" + wire $or$libresoc.v:20902$518_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:20861.7-20861.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:20896$512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:20896$512_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:20901$517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:20901$517_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:20898$514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_adr + connect \Y $not$libresoc.v:20898$514_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:20900$516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_adr + connect \Y $not$libresoc.v:20900$516_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:20903$519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_adr + connect \Y $not$libresoc.v:20903$519_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:20897$513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_adr + connect \Y $or$libresoc.v:20897$513_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:20899$515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_adr + connect \B \q_int + connect \Y $or$libresoc.v:20899$515_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:20902$518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_adr + connect \Y $or$libresoc.v:20902$518_Y + end + attribute \src "libresoc.v:20861.7-20861.20" + process $proc$libresoc.v:20861$524 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:20885.7-20885.19" + process $proc$libresoc.v:20885$525 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:20904.3-20905.27" + process $proc$libresoc.v:20904$520 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:20906.3-20914.6" + process $proc$libresoc.v:20906$521 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$522 $1\q_int$next[0:0]$523 + attribute \src "libresoc.v:20907.5-20907.29" + switch \initial + attribute \src "libresoc.v:20907.9-20907.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$523 1'0 + case + assign $1\q_int$next[0:0]$523 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$522 + end + connect \$9 $and$libresoc.v:20896$512_Y + connect \$11 $or$libresoc.v:20897$513_Y + connect \$13 $not$libresoc.v:20898$514_Y + connect \$15 $or$libresoc.v:20899$515_Y + connect \$1 $not$libresoc.v:20900$516_Y + connect \$3 $and$libresoc.v:20901$517_Y + connect \$5 $or$libresoc.v:20902$518_Y + connect \$7 $not$libresoc.v:20903$519_Y + connect \qlq_adr \$15 + connect \qn_adr \$13 + connect \q_adr \$11 +end +attribute \src "libresoc.v:20922.1-20980.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.adrok_l" +attribute \generator "nMigen" +module \adrok_l + attribute \src "libresoc.v:20923.7-20923.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:20968.3-20976.6" + wire $0\q_int$next[0:0]$536 + attribute \src "libresoc.v:20966.3-20967.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:20968.3-20976.6" + wire $1\q_int$next[0:0]$537 + attribute \src "libresoc.v:20947.7-20947.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:20958.17-20958.96" + wire $and$libresoc.v:20958$526_Y + attribute \src "libresoc.v:20963.17-20963.96" + wire $and$libresoc.v:20963$531_Y + attribute \src "libresoc.v:20960.18-20960.100" + wire $not$libresoc.v:20960$528_Y + attribute \src "libresoc.v:20962.17-20962.99" + wire $not$libresoc.v:20962$530_Y + attribute \src "libresoc.v:20965.17-20965.99" + wire $not$libresoc.v:20965$533_Y + attribute \src "libresoc.v:20959.18-20959.105" + wire $or$libresoc.v:20959$527_Y + attribute \src "libresoc.v:20961.18-20961.106" + wire $or$libresoc.v:20961$529_Y + attribute \src "libresoc.v:20964.17-20964.104" + wire $or$libresoc.v:20964$532_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 6 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:20923.7-20923.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 5 \q_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire output 4 \qn_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:20958$526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:20958$526_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:20963$531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:20963$531_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:20960$528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_addr_acked + connect \Y $not$libresoc.v:20960$528_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:20962$530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_addr_acked + connect \Y $not$libresoc.v:20962$530_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:20965$533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_addr_acked + connect \Y $not$libresoc.v:20965$533_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:20959$527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_addr_acked + connect \Y $or$libresoc.v:20959$527_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:20961$529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_addr_acked + connect \B \q_int + connect \Y $or$libresoc.v:20961$529_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:20964$532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_addr_acked + connect \Y $or$libresoc.v:20964$532_Y + end + attribute \src "libresoc.v:20923.7-20923.20" + process $proc$libresoc.v:20923$538 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:20947.7-20947.19" + process $proc$libresoc.v:20947$539 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:20966.3-20967.27" + process $proc$libresoc.v:20966$534 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:20968.3-20976.6" + process $proc$libresoc.v:20968$535 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$536 $1\q_int$next[0:0]$537 + attribute \src "libresoc.v:20969.5-20969.29" + switch \initial + attribute \src "libresoc.v:20969.9-20969.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$537 1'0 + case + assign $1\q_int$next[0:0]$537 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$536 + end + connect \$9 $and$libresoc.v:20958$526_Y + connect \$11 $or$libresoc.v:20959$527_Y + connect \$13 $not$libresoc.v:20960$528_Y + connect \$15 $or$libresoc.v:20961$529_Y + connect \$1 $not$libresoc.v:20962$530_Y + connect \$3 $and$libresoc.v:20963$531_Y + connect \$5 $or$libresoc.v:20964$532_Y + connect \$7 $not$libresoc.v:20965$533_Y + connect \qlq_addr_acked \$15 + connect \qn_addr_acked \$13 + connect \q_addr_acked \$11 +end +attribute \src "libresoc.v:20984.1-22309.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0" +attribute \generator "nMigen" +module \alu0 + attribute \src "libresoc.v:21820.3-21821.25" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:22010.3-22048.6" + wire width 4 $0\alu_alu0_alu_op__data_len$next[3:0]$686 + attribute \src "libresoc.v:21792.3-21793.67" + wire width 4 $0\alu_alu0_alu_op__data_len[3:0] + attribute \src "libresoc.v:22010.3-22048.6" + wire width 12 $0\alu_alu0_alu_op__fn_unit$next[11:0]$687 + attribute \src "libresoc.v:21762.3-21763.65" + wire width 12 $0\alu_alu0_alu_op__fn_unit[11:0] + attribute \src "libresoc.v:22010.3-22048.6" + wire width 64 $0\alu_alu0_alu_op__imm_data__data$next[63:0]$688 + attribute \src "libresoc.v:21764.3-21765.79" + wire width 64 $0\alu_alu0_alu_op__imm_data__data[63:0] + attribute \src "libresoc.v:22010.3-22048.6" + wire $0\alu_alu0_alu_op__imm_data__ok$next[0:0]$689 + attribute \src "libresoc.v:21766.3-21767.75" + wire $0\alu_alu0_alu_op__imm_data__ok[0:0] + attribute \src "libresoc.v:22010.3-22048.6" + wire width 2 $0\alu_alu0_alu_op__input_carry$next[1:0]$690 + attribute \src "libresoc.v:21784.3-21785.73" + wire width 2 $0\alu_alu0_alu_op__input_carry[1:0] + attribute \src "libresoc.v:22010.3-22048.6" + wire width 32 $0\alu_alu0_alu_op__insn$next[31:0]$691 + attribute \src "libresoc.v:21794.3-21795.59" + wire width 32 $0\alu_alu0_alu_op__insn[31:0] + attribute \src "libresoc.v:22010.3-22048.6" + wire width 7 $0\alu_alu0_alu_op__insn_type$next[6:0]$692 + attribute \src "libresoc.v:21760.3-21761.69" + wire width 7 $0\alu_alu0_alu_op__insn_type[6:0] + attribute \src "libresoc.v:22010.3-22048.6" + wire $0\alu_alu0_alu_op__invert_in$next[0:0]$693 + attribute \src "libresoc.v:21776.3-21777.69" + wire $0\alu_alu0_alu_op__invert_in[0:0] + attribute \src "libresoc.v:22010.3-22048.6" + wire $0\alu_alu0_alu_op__invert_out$next[0:0]$694 + attribute \src "libresoc.v:21780.3-21781.71" + wire $0\alu_alu0_alu_op__invert_out[0:0] + attribute \src "libresoc.v:22010.3-22048.6" + wire $0\alu_alu0_alu_op__is_32bit$next[0:0]$695 + attribute \src "libresoc.v:21788.3-21789.67" + wire $0\alu_alu0_alu_op__is_32bit[0:0] + attribute \src "libresoc.v:22010.3-22048.6" + wire $0\alu_alu0_alu_op__is_signed$next[0:0]$696 + attribute \src "libresoc.v:21790.3-21791.69" + wire $0\alu_alu0_alu_op__is_signed[0:0] + attribute \src "libresoc.v:22010.3-22048.6" + wire $0\alu_alu0_alu_op__oe__oe$next[0:0]$697 + attribute \src "libresoc.v:21772.3-21773.63" + wire $0\alu_alu0_alu_op__oe__oe[0:0] + attribute \src "libresoc.v:22010.3-22048.6" + wire $0\alu_alu0_alu_op__oe__ok$next[0:0]$698 + attribute \src "libresoc.v:21774.3-21775.63" + wire $0\alu_alu0_alu_op__oe__ok[0:0] + attribute \src "libresoc.v:22010.3-22048.6" + wire $0\alu_alu0_alu_op__output_carry$next[0:0]$699 + attribute \src "libresoc.v:21786.3-21787.75" + wire $0\alu_alu0_alu_op__output_carry[0:0] + attribute \src "libresoc.v:22010.3-22048.6" + wire $0\alu_alu0_alu_op__rc__ok$next[0:0]$700 + attribute \src "libresoc.v:21770.3-21771.63" + wire $0\alu_alu0_alu_op__rc__ok[0:0] + attribute \src "libresoc.v:22010.3-22048.6" + wire $0\alu_alu0_alu_op__rc__rc$next[0:0]$701 + attribute \src "libresoc.v:21768.3-21769.63" + wire $0\alu_alu0_alu_op__rc__rc[0:0] + attribute \src "libresoc.v:22010.3-22048.6" + wire $0\alu_alu0_alu_op__write_cr0$next[0:0]$702 + attribute \src "libresoc.v:21782.3-21783.69" + wire $0\alu_alu0_alu_op__write_cr0[0:0] + attribute \src "libresoc.v:22010.3-22048.6" + wire $0\alu_alu0_alu_op__zero_a$next[0:0]$703 + attribute \src "libresoc.v:21778.3-21779.63" + wire $0\alu_alu0_alu_op__zero_a[0:0] + attribute \src "libresoc.v:21818.3-21819.40" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:22208.3-22216.6" + wire $0\alu_l_r_alu$next[0:0]$784 + attribute \src "libresoc.v:21728.3-21729.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:22199.3-22207.6" + wire $0\alui_l_r_alui$next[0:0]$781 + attribute \src "libresoc.v:21730.3-21731.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:22049.3-22070.6" + wire width 64 $0\data_r0__o$next[63:0]$729 + attribute \src "libresoc.v:21756.3-21757.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "libresoc.v:22049.3-22070.6" + wire $0\data_r0__o_ok$next[0:0]$730 + attribute \src "libresoc.v:21758.3-21759.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "libresoc.v:22071.3-22092.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$737 + attribute \src "libresoc.v:21752.3-21753.43" + wire width 4 $0\data_r1__cr_a[3:0] + attribute \src "libresoc.v:22071.3-22092.6" + wire $0\data_r1__cr_a_ok$next[0:0]$738 + attribute \src "libresoc.v:21754.3-21755.49" + wire $0\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:22093.3-22114.6" + wire width 2 $0\data_r2__xer_ca$next[1:0]$745 + attribute \src "libresoc.v:21748.3-21749.47" + wire width 2 $0\data_r2__xer_ca[1:0] + attribute \src "libresoc.v:22093.3-22114.6" + wire $0\data_r2__xer_ca_ok$next[0:0]$746 + attribute \src "libresoc.v:21750.3-21751.53" + wire $0\data_r2__xer_ca_ok[0:0] + attribute \src "libresoc.v:22115.3-22136.6" + wire width 2 $0\data_r3__xer_ov$next[1:0]$753 + attribute \src "libresoc.v:21744.3-21745.47" + wire width 2 $0\data_r3__xer_ov[1:0] + attribute \src "libresoc.v:22115.3-22136.6" + wire $0\data_r3__xer_ov_ok$next[0:0]$754 + attribute \src "libresoc.v:21746.3-21747.53" + wire $0\data_r3__xer_ov_ok[0:0] + attribute \src "libresoc.v:22137.3-22158.6" + wire $0\data_r4__xer_so$next[0:0]$761 + attribute \src "libresoc.v:21740.3-21741.47" + wire $0\data_r4__xer_so[0:0] + attribute \src "libresoc.v:22137.3-22158.6" + wire $0\data_r4__xer_so_ok$next[0:0]$762 + attribute \src "libresoc.v:21742.3-21743.53" + wire $0\data_r4__xer_so_ok[0:0] + attribute \src "libresoc.v:22217.3-22226.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:22227.3-22236.6" + wire width 4 $0\dest2_o[3:0] + attribute \src "libresoc.v:22237.3-22246.6" + wire width 2 $0\dest3_o[1:0] + attribute \src "libresoc.v:22247.3-22256.6" + wire width 2 $0\dest4_o[1:0] + attribute \src "libresoc.v:22257.3-22266.6" + wire $0\dest5_o[0:0] + attribute \src "libresoc.v:20985.7-20985.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:21965.3-21973.6" + wire $0\opc_l_r_opc$next[0:0]$671 + attribute \src "libresoc.v:21804.3-21805.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:21956.3-21964.6" + wire $0\opc_l_s_opc$next[0:0]$668 + attribute \src "libresoc.v:21806.3-21807.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:22267.3-22275.6" + wire width 5 $0\prev_wr_go$next[4:0]$792 + attribute \src "libresoc.v:21816.3-21817.37" + wire width 5 $0\prev_wr_go[4:0] + attribute \src "libresoc.v:21910.3-21919.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:22001.3-22009.6" + wire width 5 $0\req_l_r_req$next[4:0]$683 + attribute \src "libresoc.v:21796.3-21797.39" + wire width 5 $0\req_l_r_req[4:0] + attribute \src "libresoc.v:21992.3-22000.6" + wire width 5 $0\req_l_s_req$next[4:0]$680 + attribute \src "libresoc.v:21798.3-21799.39" + wire width 5 $0\req_l_s_req[4:0] + attribute \src "libresoc.v:21929.3-21937.6" + wire $0\rok_l_r_rdok$next[0:0]$659 + attribute \src "libresoc.v:21812.3-21813.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:21920.3-21928.6" + wire $0\rok_l_s_rdok$next[0:0]$656 + attribute \src "libresoc.v:21814.3-21815.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:21947.3-21955.6" + wire $0\rst_l_r_rst$next[0:0]$665 + attribute \src "libresoc.v:21808.3-21809.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:21938.3-21946.6" + wire $0\rst_l_s_rst$next[0:0]$662 + attribute \src "libresoc.v:21810.3-21811.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:21983.3-21991.6" + wire width 4 $0\src_l_r_src$next[3:0]$677 + attribute \src "libresoc.v:21800.3-21801.39" + wire width 4 $0\src_l_r_src[3:0] + attribute \src "libresoc.v:21974.3-21982.6" + wire width 4 $0\src_l_s_src$next[3:0]$674 + attribute \src "libresoc.v:21802.3-21803.39" + wire width 4 $0\src_l_s_src[3:0] + attribute \src "libresoc.v:22159.3-22168.6" + wire width 64 $0\src_r0$next[63:0]$769 + attribute \src "libresoc.v:21738.3-21739.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:22169.3-22178.6" + wire width 64 $0\src_r1$next[63:0]$772 + attribute \src "libresoc.v:21736.3-21737.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:22179.3-22188.6" + wire $0\src_r2$next[0:0]$775 + attribute \src "libresoc.v:21734.3-21735.29" + wire $0\src_r2[0:0] + attribute \src "libresoc.v:22189.3-22198.6" + wire width 2 $0\src_r3$next[1:0]$778 + attribute \src "libresoc.v:21732.3-21733.29" + wire width 2 $0\src_r3[1:0] + attribute \src "libresoc.v:21123.7-21123.24" + wire $1\all_rd_dly[0:0] + attribute \src "libresoc.v:22010.3-22048.6" + wire width 4 $1\alu_alu0_alu_op__data_len$next[3:0]$704 + attribute \src "libresoc.v:21131.13-21131.45" + wire width 4 $1\alu_alu0_alu_op__data_len[3:0] + attribute \src "libresoc.v:22010.3-22048.6" + wire width 12 $1\alu_alu0_alu_op__fn_unit$next[11:0]$705 + attribute \src "libresoc.v:21148.14-21148.48" + wire width 12 $1\alu_alu0_alu_op__fn_unit[11:0] + attribute \src "libresoc.v:22010.3-22048.6" + wire width 64 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$706 + attribute \src "libresoc.v:21152.14-21152.68" + wire width 64 $1\alu_alu0_alu_op__imm_data__data[63:0] + attribute \src "libresoc.v:22010.3-22048.6" + wire $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$707 + attribute \src "libresoc.v:21156.7-21156.43" + wire $1\alu_alu0_alu_op__imm_data__ok[0:0] + attribute \src "libresoc.v:22010.3-22048.6" + wire width 2 $1\alu_alu0_alu_op__input_carry$next[1:0]$708 + attribute \src "libresoc.v:21164.13-21164.48" + wire width 2 $1\alu_alu0_alu_op__input_carry[1:0] + attribute \src "libresoc.v:22010.3-22048.6" + wire width 32 $1\alu_alu0_alu_op__insn$next[31:0]$709 + attribute \src "libresoc.v:21168.14-21168.43" + wire width 32 $1\alu_alu0_alu_op__insn[31:0] + attribute \src "libresoc.v:22010.3-22048.6" + wire width 7 $1\alu_alu0_alu_op__insn_type$next[6:0]$710 + attribute \src "libresoc.v:21246.13-21246.47" + wire width 7 $1\alu_alu0_alu_op__insn_type[6:0] + attribute \src "libresoc.v:22010.3-22048.6" + wire $1\alu_alu0_alu_op__invert_in$next[0:0]$711 + attribute \src "libresoc.v:21250.7-21250.40" + wire $1\alu_alu0_alu_op__invert_in[0:0] + attribute \src "libresoc.v:22010.3-22048.6" + wire $1\alu_alu0_alu_op__invert_out$next[0:0]$712 + attribute \src "libresoc.v:21254.7-21254.41" + wire $1\alu_alu0_alu_op__invert_out[0:0] + attribute \src "libresoc.v:22010.3-22048.6" + wire $1\alu_alu0_alu_op__is_32bit$next[0:0]$713 + attribute \src "libresoc.v:21258.7-21258.39" + wire $1\alu_alu0_alu_op__is_32bit[0:0] + attribute \src "libresoc.v:22010.3-22048.6" + wire $1\alu_alu0_alu_op__is_signed$next[0:0]$714 + attribute \src "libresoc.v:21262.7-21262.40" + wire $1\alu_alu0_alu_op__is_signed[0:0] + attribute \src "libresoc.v:22010.3-22048.6" + wire $1\alu_alu0_alu_op__oe__oe$next[0:0]$715 + attribute \src "libresoc.v:21266.7-21266.37" + wire $1\alu_alu0_alu_op__oe__oe[0:0] + attribute \src "libresoc.v:22010.3-22048.6" + wire $1\alu_alu0_alu_op__oe__ok$next[0:0]$716 + attribute \src "libresoc.v:21270.7-21270.37" + wire $1\alu_alu0_alu_op__oe__ok[0:0] + attribute \src "libresoc.v:22010.3-22048.6" + wire $1\alu_alu0_alu_op__output_carry$next[0:0]$717 + attribute \src "libresoc.v:21274.7-21274.43" + wire $1\alu_alu0_alu_op__output_carry[0:0] + attribute \src "libresoc.v:22010.3-22048.6" + wire $1\alu_alu0_alu_op__rc__ok$next[0:0]$718 + attribute \src "libresoc.v:21278.7-21278.37" + wire $1\alu_alu0_alu_op__rc__ok[0:0] + attribute \src "libresoc.v:22010.3-22048.6" + wire $1\alu_alu0_alu_op__rc__rc$next[0:0]$719 + attribute \src "libresoc.v:21282.7-21282.37" + wire $1\alu_alu0_alu_op__rc__rc[0:0] + attribute \src "libresoc.v:22010.3-22048.6" + wire $1\alu_alu0_alu_op__write_cr0$next[0:0]$720 + attribute \src "libresoc.v:21286.7-21286.40" + wire $1\alu_alu0_alu_op__write_cr0[0:0] + attribute \src "libresoc.v:22010.3-22048.6" + wire $1\alu_alu0_alu_op__zero_a$next[0:0]$721 + attribute \src "libresoc.v:21290.7-21290.37" + wire $1\alu_alu0_alu_op__zero_a[0:0] + attribute \src "libresoc.v:21322.7-21322.26" + wire $1\alu_done_dly[0:0] + attribute \src "libresoc.v:22208.3-22216.6" + wire $1\alu_l_r_alu$next[0:0]$785 + attribute \src "libresoc.v:21330.7-21330.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "libresoc.v:22199.3-22207.6" + wire $1\alui_l_r_alui$next[0:0]$782 + attribute \src "libresoc.v:21342.7-21342.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "libresoc.v:22049.3-22070.6" + wire width 64 $1\data_r0__o$next[63:0]$731 + attribute \src "libresoc.v:21376.14-21376.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "libresoc.v:22049.3-22070.6" + wire $1\data_r0__o_ok$next[0:0]$732 + attribute \src "libresoc.v:21380.7-21380.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "libresoc.v:22071.3-22092.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$739 + attribute \src "libresoc.v:21384.13-21384.33" + wire width 4 $1\data_r1__cr_a[3:0] + attribute \src "libresoc.v:22071.3-22092.6" + wire $1\data_r1__cr_a_ok$next[0:0]$740 + attribute \src "libresoc.v:21388.7-21388.30" + wire $1\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:22093.3-22114.6" + wire width 2 $1\data_r2__xer_ca$next[1:0]$747 + attribute \src "libresoc.v:21392.13-21392.35" + wire width 2 $1\data_r2__xer_ca[1:0] + attribute \src "libresoc.v:22093.3-22114.6" + wire $1\data_r2__xer_ca_ok$next[0:0]$748 + attribute \src "libresoc.v:21396.7-21396.32" + wire $1\data_r2__xer_ca_ok[0:0] + attribute \src "libresoc.v:22115.3-22136.6" + wire width 2 $1\data_r3__xer_ov$next[1:0]$755 + attribute \src "libresoc.v:21400.13-21400.35" + wire width 2 $1\data_r3__xer_ov[1:0] + attribute \src "libresoc.v:22115.3-22136.6" + wire $1\data_r3__xer_ov_ok$next[0:0]$756 + attribute \src "libresoc.v:21404.7-21404.32" + wire $1\data_r3__xer_ov_ok[0:0] + attribute \src "libresoc.v:22137.3-22158.6" + wire $1\data_r4__xer_so$next[0:0]$763 + attribute \src "libresoc.v:21408.7-21408.29" + wire $1\data_r4__xer_so[0:0] + attribute \src "libresoc.v:22137.3-22158.6" + wire $1\data_r4__xer_so_ok$next[0:0]$764 + attribute \src "libresoc.v:21412.7-21412.32" + wire $1\data_r4__xer_so_ok[0:0] + attribute \src "libresoc.v:22217.3-22226.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "libresoc.v:22227.3-22236.6" + wire width 4 $1\dest2_o[3:0] + attribute \src "libresoc.v:22237.3-22246.6" + wire width 2 $1\dest3_o[1:0] + attribute \src "libresoc.v:22247.3-22256.6" + wire width 2 $1\dest4_o[1:0] + attribute \src "libresoc.v:22257.3-22266.6" + wire $1\dest5_o[0:0] + attribute \src "libresoc.v:21965.3-21973.6" + wire $1\opc_l_r_opc$next[0:0]$672 + attribute \src "libresoc.v:21435.7-21435.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "libresoc.v:21956.3-21964.6" + wire $1\opc_l_s_opc$next[0:0]$669 + attribute \src "libresoc.v:21439.7-21439.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "libresoc.v:22267.3-22275.6" + wire width 5 $1\prev_wr_go$next[4:0]$793 + attribute \src "libresoc.v:21570.13-21570.31" + wire width 5 $1\prev_wr_go[4:0] + attribute \src "libresoc.v:21910.3-21919.6" + wire $1\req_done[0:0] + attribute \src "libresoc.v:22001.3-22009.6" + wire width 5 $1\req_l_r_req$next[4:0]$684 + attribute \src "libresoc.v:21578.13-21578.32" + wire width 5 $1\req_l_r_req[4:0] + attribute \src "libresoc.v:21992.3-22000.6" + wire width 5 $1\req_l_s_req$next[4:0]$681 + attribute \src "libresoc.v:21582.13-21582.32" + wire width 5 $1\req_l_s_req[4:0] + attribute \src "libresoc.v:21929.3-21937.6" + wire $1\rok_l_r_rdok$next[0:0]$660 + attribute \src "libresoc.v:21594.7-21594.26" + wire $1\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:21920.3-21928.6" + wire $1\rok_l_s_rdok$next[0:0]$657 + attribute \src "libresoc.v:21598.7-21598.26" + wire $1\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:21947.3-21955.6" + wire $1\rst_l_r_rst$next[0:0]$666 + attribute \src "libresoc.v:21602.7-21602.25" + wire $1\rst_l_r_rst[0:0] + attribute \src "libresoc.v:21938.3-21946.6" + wire $1\rst_l_s_rst$next[0:0]$663 + attribute \src "libresoc.v:21606.7-21606.25" + wire $1\rst_l_s_rst[0:0] + attribute \src "libresoc.v:21983.3-21991.6" + wire width 4 $1\src_l_r_src$next[3:0]$678 + attribute \src "libresoc.v:21622.13-21622.31" + wire width 4 $1\src_l_r_src[3:0] + attribute \src "libresoc.v:21974.3-21982.6" + wire width 4 $1\src_l_s_src$next[3:0]$675 + attribute \src "libresoc.v:21626.13-21626.31" + wire width 4 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connect \Y $and$libresoc.v:21703$582_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:21704$583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$51 + connect \B \alu_alu0_n_valid_o + connect \Y $and$libresoc.v:21704$583_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:21705$584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$53 + connect \B \cu_busy_o + connect \Y $and$libresoc.v:21705$584_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + cell $and $and$libresoc.v:21710$589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_alu0_n_valid_o + connect \B \cu_busy_o + connect \Y $and$libresoc.v:21710$589_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + cell $and $and$libresoc.v:21711$590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \alu_pulsem + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:21711$590_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:21714$593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:21714$593_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:21715$594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cr_a_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:21715$594_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:21716$595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_ca_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:21716$595_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:21717$596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_ov_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:21717$596_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:21718$597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_so_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:21718$597_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $eq$libresoc.v:21700$579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$43 + connect \B 1'0 + connect \Y $eq$libresoc.v:21700$579_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $eq$libresoc.v:21702$581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $eq$libresoc.v:21702$581_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$libresoc.v:21665$544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_alu0_alu_op__zero_a + connect \Y $not$libresoc.v:21665$544_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$libresoc.v:21666$545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_alu0_alu_op__imm_data__ok + connect \Y $not$libresoc.v:21666$545_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$libresoc.v:21668$547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_rdmaskn_i + connect \Y $not$libresoc.v:21668$547_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:21683$562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $not$libresoc.v:21683$562_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:21685$564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $not$libresoc.v:21685$564_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:21688$567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_wrmask_o + connect \Y $not$libresoc.v:21688$567_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:21691$570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:21691$570_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$libresoc.v:21697$576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_alu0_n_ready_i + connect \Y $not$libresoc.v:21697$576_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$libresoc.v:21712$591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_rd__rel_o + connect \Y $not$libresoc.v:21712$591_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$libresoc.v:21695$574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$33 + connect \B \$35 + connect \Y $or$libresoc.v:21695$574_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$libresoc.v:21706$585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:21706$585_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$libresoc.v:21707$586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:21707$586_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$libresoc.v:21708$587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:21708$587_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$libresoc.v:21709$588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:21709$588_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:21713$592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$libresoc.v:21713$592_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:21722$601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$6 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:21722$601_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:21661$540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $reduce_and$libresoc.v:21661$540_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:21690$569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \$27 + connect \Y $reduce_or$libresoc.v:21690$569_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:21693$572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:21693$572_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:21694$573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:21694$573_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:21719$598 + parameter \WIDTH 1 + connect \A \src_l_q_src [0] + connect \B \opc_l_q_opc + connect \S \alu_alu0_alu_op__zero_a + connect \Y $ternary$libresoc.v:21719$598_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:21720$599 + parameter \WIDTH 64 + connect \A \src1_i + connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \S \alu_alu0_alu_op__zero_a + connect \Y $ternary$libresoc.v:21720$599_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:21721$600 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_alu0_alu_op__imm_data__ok + connect \Y $ternary$libresoc.v:21721$600_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:21723$602 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_alu0_alu_op__imm_data__data + connect \S \alu_alu0_alu_op__imm_data__ok + connect \Y $ternary$libresoc.v:21723$602_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:21724$603 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $ternary$libresoc.v:21724$603_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:21725$604 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm$88 + connect \S \src_sel$85 + connect \Y $ternary$libresoc.v:21725$604_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:21726$605 + parameter \WIDTH 1 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:21726$605_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:21727$606 + parameter \WIDTH 2 + connect \A \src_r3 + connect \B \src4_i + connect \S \src_l_q_src [3] + connect \Y $ternary$libresoc.v:21727$606_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:21822.12-21861.4" + cell \alu_alu0 \alu_alu0 + connect \alu_op__data_len \alu_alu0_alu_op__data_len + connect \alu_op__fn_unit \alu_alu0_alu_op__fn_unit + connect \alu_op__imm_data__data \alu_alu0_alu_op__imm_data__data + connect \alu_op__imm_data__ok \alu_alu0_alu_op__imm_data__ok + connect \alu_op__input_carry \alu_alu0_alu_op__input_carry + connect \alu_op__insn \alu_alu0_alu_op__insn + connect \alu_op__insn_type \alu_alu0_alu_op__insn_type + connect \alu_op__invert_in \alu_alu0_alu_op__invert_in + connect \alu_op__invert_out \alu_alu0_alu_op__invert_out + connect \alu_op__is_32bit \alu_alu0_alu_op__is_32bit + connect \alu_op__is_signed \alu_alu0_alu_op__is_signed + connect \alu_op__oe__oe \alu_alu0_alu_op__oe__oe + connect \alu_op__oe__ok \alu_alu0_alu_op__oe__ok + connect \alu_op__output_carry \alu_alu0_alu_op__output_carry + connect \alu_op__rc__ok \alu_alu0_alu_op__rc__ok + connect \alu_op__rc__rc \alu_alu0_alu_op__rc__rc + connect \alu_op__write_cr0 \alu_alu0_alu_op__write_cr0 + connect \alu_op__zero_a \alu_alu0_alu_op__zero_a + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \alu_alu0_cr_a + connect \cr_a_ok \cr_a_ok + connect \n_ready_i \alu_alu0_n_ready_i + connect \n_valid_o \alu_alu0_n_valid_o + connect \o \alu_alu0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_alu0_p_ready_o + connect \p_valid_i \alu_alu0_p_valid_i + connect \ra \alu_alu0_ra + connect \rb \alu_alu0_rb + connect \xer_ca \alu_alu0_xer_ca + connect \xer_ca$2 \alu_alu0_xer_ca$2 + connect \xer_ca_ok \xer_ca_ok + connect \xer_ov \alu_alu0_xer_ov + connect \xer_ov_ok \xer_ov_ok + connect \xer_so \alu_alu0_xer_so + connect \xer_so$1 \alu_alu0_xer_so$1 + connect \xer_so_ok \xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:21862.9-21868.4" + cell \alu_l \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:21869.10-21875.4" + cell \alui_l \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:21876.9-21882.4" + cell \opc_l \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:21883.9-21889.4" + cell \req_l \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:21890.9-21896.4" + cell \rok_l \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:21897.9-21902.4" + cell \rst_l \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:21903.9-21909.4" + cell \src_l \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "libresoc.v:20985.7-20985.20" + process $proc$libresoc.v:20985$794 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:21123.7-21123.24" + process $proc$libresoc.v:21123$795 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "libresoc.v:21131.13-21131.45" + process $proc$libresoc.v:21131$796 + assign { } { } + assign $1\alu_alu0_alu_op__data_len[3:0] 4'0000 + sync always + sync init + update \alu_alu0_alu_op__data_len $1\alu_alu0_alu_op__data_len[3:0] + end + attribute \src "libresoc.v:21148.14-21148.48" + process $proc$libresoc.v:21148$797 + assign { } { } + assign $1\alu_alu0_alu_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \alu_alu0_alu_op__fn_unit $1\alu_alu0_alu_op__fn_unit[11:0] + end + attribute \src "libresoc.v:21152.14-21152.68" + process $proc$libresoc.v:21152$798 + assign { } { } + assign $1\alu_alu0_alu_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_alu0_alu_op__imm_data__data $1\alu_alu0_alu_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:21156.7-21156.43" + process $proc$libresoc.v:21156$799 + assign { } { } + assign $1\alu_alu0_alu_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__imm_data__ok $1\alu_alu0_alu_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:21164.13-21164.48" + process $proc$libresoc.v:21164$800 + assign { } { } + assign $1\alu_alu0_alu_op__input_carry[1:0] 2'00 + sync always + sync init + update \alu_alu0_alu_op__input_carry $1\alu_alu0_alu_op__input_carry[1:0] + end + attribute \src "libresoc.v:21168.14-21168.43" + process $proc$libresoc.v:21168$801 + assign { } { } + assign $1\alu_alu0_alu_op__insn[31:0] 0 + sync always + sync init + update \alu_alu0_alu_op__insn $1\alu_alu0_alu_op__insn[31:0] + end + attribute \src "libresoc.v:21246.13-21246.47" + process $proc$libresoc.v:21246$802 + assign { } { } + assign $1\alu_alu0_alu_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_alu0_alu_op__insn_type $1\alu_alu0_alu_op__insn_type[6:0] + end + attribute \src "libresoc.v:21250.7-21250.40" + process $proc$libresoc.v:21250$803 + assign { } { } + assign $1\alu_alu0_alu_op__invert_in[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__invert_in $1\alu_alu0_alu_op__invert_in[0:0] + end + attribute \src "libresoc.v:21254.7-21254.41" + process $proc$libresoc.v:21254$804 + assign { } { } + assign $1\alu_alu0_alu_op__invert_out[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__invert_out $1\alu_alu0_alu_op__invert_out[0:0] + end + attribute \src "libresoc.v:21258.7-21258.39" + process $proc$libresoc.v:21258$805 + assign { } { } + assign $1\alu_alu0_alu_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__is_32bit $1\alu_alu0_alu_op__is_32bit[0:0] + end + attribute \src "libresoc.v:21262.7-21262.40" + process $proc$libresoc.v:21262$806 + assign { } { } + assign $1\alu_alu0_alu_op__is_signed[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__is_signed $1\alu_alu0_alu_op__is_signed[0:0] + end + attribute \src "libresoc.v:21266.7-21266.37" + process $proc$libresoc.v:21266$807 + assign { } { } + assign $1\alu_alu0_alu_op__oe__oe[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__oe__oe $1\alu_alu0_alu_op__oe__oe[0:0] + end + attribute \src "libresoc.v:21270.7-21270.37" + process $proc$libresoc.v:21270$808 + assign { } { } + assign $1\alu_alu0_alu_op__oe__ok[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__oe__ok $1\alu_alu0_alu_op__oe__ok[0:0] + end + attribute \src "libresoc.v:21274.7-21274.43" + process $proc$libresoc.v:21274$809 + assign { } { } + assign $1\alu_alu0_alu_op__output_carry[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__output_carry $1\alu_alu0_alu_op__output_carry[0:0] + end + attribute \src "libresoc.v:21278.7-21278.37" + process $proc$libresoc.v:21278$810 + assign { } { } + assign $1\alu_alu0_alu_op__rc__ok[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__rc__ok $1\alu_alu0_alu_op__rc__ok[0:0] + end + attribute \src "libresoc.v:21282.7-21282.37" + process $proc$libresoc.v:21282$811 + assign { } { } + assign $1\alu_alu0_alu_op__rc__rc[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__rc__rc $1\alu_alu0_alu_op__rc__rc[0:0] + end + attribute \src "libresoc.v:21286.7-21286.40" + process $proc$libresoc.v:21286$812 + assign { } { } + assign $1\alu_alu0_alu_op__write_cr0[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__write_cr0 $1\alu_alu0_alu_op__write_cr0[0:0] + end + attribute \src "libresoc.v:21290.7-21290.37" + process $proc$libresoc.v:21290$813 + assign { } { } + assign $1\alu_alu0_alu_op__zero_a[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__zero_a $1\alu_alu0_alu_op__zero_a[0:0] + end + attribute \src "libresoc.v:21322.7-21322.26" + process $proc$libresoc.v:21322$814 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "libresoc.v:21330.7-21330.25" + process $proc$libresoc.v:21330$815 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:21342.7-21342.27" + process $proc$libresoc.v:21342$816 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:21376.14-21376.47" + process $proc$libresoc.v:21376$817 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "libresoc.v:21380.7-21380.27" + process $proc$libresoc.v:21380$818 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:21384.13-21384.33" + process $proc$libresoc.v:21384$819 + assign { } { } + assign $1\data_r1__cr_a[3:0] 4'0000 + sync always + sync init + update \data_r1__cr_a $1\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:21388.7-21388.30" + process $proc$libresoc.v:21388$820 + assign { } { } + assign $1\data_r1__cr_a_ok[0:0] 1'0 + sync always + sync init + update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:21392.13-21392.35" + process $proc$libresoc.v:21392$821 + assign { } { } + assign $1\data_r2__xer_ca[1:0] 2'00 + sync always + sync init + update \data_r2__xer_ca $1\data_r2__xer_ca[1:0] + end + attribute \src "libresoc.v:21396.7-21396.32" + process $proc$libresoc.v:21396$822 + assign { } { } + assign $1\data_r2__xer_ca_ok[0:0] 1'0 + sync always + sync init + update \data_r2__xer_ca_ok $1\data_r2__xer_ca_ok[0:0] + end + attribute \src "libresoc.v:21400.13-21400.35" + process $proc$libresoc.v:21400$823 + assign { } { } + assign $1\data_r3__xer_ov[1:0] 2'00 + sync always + sync init + update \data_r3__xer_ov $1\data_r3__xer_ov[1:0] + end + attribute \src "libresoc.v:21404.7-21404.32" + process $proc$libresoc.v:21404$824 + assign { } { } + assign $1\data_r3__xer_ov_ok[0:0] 1'0 + sync always + sync init + update \data_r3__xer_ov_ok $1\data_r3__xer_ov_ok[0:0] + end + attribute \src "libresoc.v:21408.7-21408.29" + process $proc$libresoc.v:21408$825 + assign { } { } + assign $1\data_r4__xer_so[0:0] 1'0 + sync always + sync init + update \data_r4__xer_so $1\data_r4__xer_so[0:0] + end + attribute \src "libresoc.v:21412.7-21412.32" + process $proc$libresoc.v:21412$826 + assign { } { } + assign $1\data_r4__xer_so_ok[0:0] 1'0 + sync always + sync init + update \data_r4__xer_so_ok $1\data_r4__xer_so_ok[0:0] + end + attribute \src "libresoc.v:21435.7-21435.25" + process $proc$libresoc.v:21435$827 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:21439.7-21439.25" + process $proc$libresoc.v:21439$828 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:21570.13-21570.31" + process $proc$libresoc.v:21570$829 + assign { } { } + assign $1\prev_wr_go[4:0] 5'00000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[4:0] + end + attribute \src "libresoc.v:21578.13-21578.32" + process $proc$libresoc.v:21578$830 + assign { } { } + assign $1\req_l_r_req[4:0] 5'11111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[4:0] + end + attribute \src "libresoc.v:21582.13-21582.32" + process $proc$libresoc.v:21582$831 + assign { } { } + assign $1\req_l_s_req[4:0] 5'00000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[4:0] + end + attribute \src "libresoc.v:21594.7-21594.26" + process $proc$libresoc.v:21594$832 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:21598.7-21598.26" + process $proc$libresoc.v:21598$833 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:21602.7-21602.25" + process $proc$libresoc.v:21602$834 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:21606.7-21606.25" + process $proc$libresoc.v:21606$835 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:21622.13-21622.31" + process $proc$libresoc.v:21622$836 + assign { } { } + assign $1\src_l_r_src[3:0] 4'1111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[3:0] + end + attribute \src "libresoc.v:21626.13-21626.31" + process $proc$libresoc.v:21626$837 + assign { } { } + assign $1\src_l_s_src[3:0] 4'0000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[3:0] + end + attribute \src "libresoc.v:21634.14-21634.43" + process $proc$libresoc.v:21634$838 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:21638.14-21638.43" + process $proc$libresoc.v:21638$839 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:21642.7-21642.20" + process $proc$libresoc.v:21642$840 + assign { } { } + assign $1\src_r2[0:0] 1'0 + sync always + sync init + update \src_r2 $1\src_r2[0:0] + end + attribute \src "libresoc.v:21646.13-21646.26" + process $proc$libresoc.v:21646$841 + assign { } { } + assign $1\src_r3[1:0] 2'00 + sync always + sync init + update \src_r3 $1\src_r3[1:0] + end + attribute \src "libresoc.v:21728.3-21729.39" + process $proc$libresoc.v:21728$607 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:21730.3-21731.43" + process $proc$libresoc.v:21730$608 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:21732.3-21733.29" + process $proc$libresoc.v:21732$609 + assign { } { } + assign $0\src_r3[1:0] \src_r3$next + sync posedge \coresync_clk + update \src_r3 $0\src_r3[1:0] + end + attribute \src "libresoc.v:21734.3-21735.29" + process $proc$libresoc.v:21734$610 + assign { } { } + assign $0\src_r2[0:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[0:0] + end + attribute \src "libresoc.v:21736.3-21737.29" + process $proc$libresoc.v:21736$611 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:21738.3-21739.29" + process $proc$libresoc.v:21738$612 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:21740.3-21741.47" + process $proc$libresoc.v:21740$613 + assign { } { } + assign $0\data_r4__xer_so[0:0] \data_r4__xer_so$next + sync posedge \coresync_clk + update \data_r4__xer_so $0\data_r4__xer_so[0:0] + end + attribute \src "libresoc.v:21742.3-21743.53" + process $proc$libresoc.v:21742$614 + assign { } { } + assign $0\data_r4__xer_so_ok[0:0] \data_r4__xer_so_ok$next + sync posedge \coresync_clk + update \data_r4__xer_so_ok $0\data_r4__xer_so_ok[0:0] + end + attribute \src "libresoc.v:21744.3-21745.47" + process $proc$libresoc.v:21744$615 + assign { } { } + assign $0\data_r3__xer_ov[1:0] \data_r3__xer_ov$next + sync posedge \coresync_clk + update \data_r3__xer_ov $0\data_r3__xer_ov[1:0] + end + attribute \src "libresoc.v:21746.3-21747.53" + process $proc$libresoc.v:21746$616 + assign { } { } + assign $0\data_r3__xer_ov_ok[0:0] \data_r3__xer_ov_ok$next + sync posedge \coresync_clk + update \data_r3__xer_ov_ok $0\data_r3__xer_ov_ok[0:0] + end + attribute \src "libresoc.v:21748.3-21749.47" + process $proc$libresoc.v:21748$617 + assign { } { } + assign $0\data_r2__xer_ca[1:0] \data_r2__xer_ca$next + sync posedge \coresync_clk + update \data_r2__xer_ca $0\data_r2__xer_ca[1:0] + end + attribute \src "libresoc.v:21750.3-21751.53" + process $proc$libresoc.v:21750$618 + assign { } { } + assign $0\data_r2__xer_ca_ok[0:0] \data_r2__xer_ca_ok$next + sync posedge \coresync_clk + update \data_r2__xer_ca_ok $0\data_r2__xer_ca_ok[0:0] + end + attribute \src "libresoc.v:21752.3-21753.43" + process $proc$libresoc.v:21752$619 + assign { } { } + assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next + sync posedge \coresync_clk + update \data_r1__cr_a $0\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:21754.3-21755.49" + process $proc$libresoc.v:21754$620 + assign { } { } + assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next + sync posedge \coresync_clk + update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:21756.3-21757.37" + process $proc$libresoc.v:21756$621 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "libresoc.v:21758.3-21759.43" + process $proc$libresoc.v:21758$622 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:21760.3-21761.69" + process $proc$libresoc.v:21760$623 + assign { } { } + assign $0\alu_alu0_alu_op__insn_type[6:0] \alu_alu0_alu_op__insn_type$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__insn_type $0\alu_alu0_alu_op__insn_type[6:0] + end + attribute \src "libresoc.v:21762.3-21763.65" + process $proc$libresoc.v:21762$624 + assign { } { } + assign $0\alu_alu0_alu_op__fn_unit[11:0] \alu_alu0_alu_op__fn_unit$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__fn_unit $0\alu_alu0_alu_op__fn_unit[11:0] + end + attribute \src "libresoc.v:21764.3-21765.79" + process $proc$libresoc.v:21764$625 + assign { } { } + assign $0\alu_alu0_alu_op__imm_data__data[63:0] \alu_alu0_alu_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__imm_data__data $0\alu_alu0_alu_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:21766.3-21767.75" + process $proc$libresoc.v:21766$626 + assign { } { } + assign $0\alu_alu0_alu_op__imm_data__ok[0:0] \alu_alu0_alu_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__imm_data__ok $0\alu_alu0_alu_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:21768.3-21769.63" + process $proc$libresoc.v:21768$627 + assign { } { } + assign $0\alu_alu0_alu_op__rc__rc[0:0] \alu_alu0_alu_op__rc__rc$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__rc__rc $0\alu_alu0_alu_op__rc__rc[0:0] + end + attribute \src "libresoc.v:21770.3-21771.63" + process $proc$libresoc.v:21770$628 + assign { } { } + assign $0\alu_alu0_alu_op__rc__ok[0:0] \alu_alu0_alu_op__rc__ok$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__rc__ok $0\alu_alu0_alu_op__rc__ok[0:0] + end + attribute \src "libresoc.v:21772.3-21773.63" + process $proc$libresoc.v:21772$629 + assign { } { } + assign $0\alu_alu0_alu_op__oe__oe[0:0] \alu_alu0_alu_op__oe__oe$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__oe__oe $0\alu_alu0_alu_op__oe__oe[0:0] + end + attribute \src "libresoc.v:21774.3-21775.63" + process $proc$libresoc.v:21774$630 + assign { } { } + assign $0\alu_alu0_alu_op__oe__ok[0:0] \alu_alu0_alu_op__oe__ok$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__oe__ok $0\alu_alu0_alu_op__oe__ok[0:0] + end + attribute \src "libresoc.v:21776.3-21777.69" + process $proc$libresoc.v:21776$631 + assign { } { } + assign $0\alu_alu0_alu_op__invert_in[0:0] \alu_alu0_alu_op__invert_in$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__invert_in $0\alu_alu0_alu_op__invert_in[0:0] + end + attribute \src "libresoc.v:21778.3-21779.63" + process $proc$libresoc.v:21778$632 + assign { } { } + assign $0\alu_alu0_alu_op__zero_a[0:0] \alu_alu0_alu_op__zero_a$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__zero_a $0\alu_alu0_alu_op__zero_a[0:0] + end + attribute \src "libresoc.v:21780.3-21781.71" + process $proc$libresoc.v:21780$633 + assign { } { } + assign $0\alu_alu0_alu_op__invert_out[0:0] \alu_alu0_alu_op__invert_out$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__invert_out $0\alu_alu0_alu_op__invert_out[0:0] + end + attribute \src "libresoc.v:21782.3-21783.69" + process $proc$libresoc.v:21782$634 + assign { } { } + assign $0\alu_alu0_alu_op__write_cr0[0:0] \alu_alu0_alu_op__write_cr0$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__write_cr0 $0\alu_alu0_alu_op__write_cr0[0:0] + end + attribute \src "libresoc.v:21784.3-21785.73" + process $proc$libresoc.v:21784$635 + assign { } { } + assign $0\alu_alu0_alu_op__input_carry[1:0] \alu_alu0_alu_op__input_carry$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__input_carry $0\alu_alu0_alu_op__input_carry[1:0] + end + attribute \src "libresoc.v:21786.3-21787.75" + process $proc$libresoc.v:21786$636 + assign { } { } + assign $0\alu_alu0_alu_op__output_carry[0:0] \alu_alu0_alu_op__output_carry$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__output_carry $0\alu_alu0_alu_op__output_carry[0:0] + end + attribute \src "libresoc.v:21788.3-21789.67" + process $proc$libresoc.v:21788$637 + assign { } { } + assign $0\alu_alu0_alu_op__is_32bit[0:0] \alu_alu0_alu_op__is_32bit$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__is_32bit $0\alu_alu0_alu_op__is_32bit[0:0] + end + attribute \src "libresoc.v:21790.3-21791.69" + process $proc$libresoc.v:21790$638 + assign { } { } + assign $0\alu_alu0_alu_op__is_signed[0:0] \alu_alu0_alu_op__is_signed$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__is_signed $0\alu_alu0_alu_op__is_signed[0:0] + end + attribute \src "libresoc.v:21792.3-21793.67" + process $proc$libresoc.v:21792$639 + assign { } { } + assign $0\alu_alu0_alu_op__data_len[3:0] \alu_alu0_alu_op__data_len$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__data_len $0\alu_alu0_alu_op__data_len[3:0] + end + attribute \src "libresoc.v:21794.3-21795.59" + process $proc$libresoc.v:21794$640 + assign { } { } + assign $0\alu_alu0_alu_op__insn[31:0] \alu_alu0_alu_op__insn$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__insn $0\alu_alu0_alu_op__insn[31:0] + end + attribute \src "libresoc.v:21796.3-21797.39" + process $proc$libresoc.v:21796$641 + assign { } { } + assign $0\req_l_r_req[4:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[4:0] + end + attribute \src "libresoc.v:21798.3-21799.39" + process $proc$libresoc.v:21798$642 + assign { } { } + assign $0\req_l_s_req[4:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[4:0] + end + attribute \src "libresoc.v:21800.3-21801.39" + process $proc$libresoc.v:21800$643 + assign { } { } + assign $0\src_l_r_src[3:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[3:0] + end + attribute \src "libresoc.v:21802.3-21803.39" + process $proc$libresoc.v:21802$644 + assign { } { } + assign $0\src_l_s_src[3:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[3:0] + end + attribute \src "libresoc.v:21804.3-21805.39" + process $proc$libresoc.v:21804$645 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:21806.3-21807.39" + process $proc$libresoc.v:21806$646 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:21808.3-21809.39" + process $proc$libresoc.v:21808$647 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:21810.3-21811.39" + process $proc$libresoc.v:21810$648 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:21812.3-21813.41" + process $proc$libresoc.v:21812$649 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:21814.3-21815.41" + process $proc$libresoc.v:21814$650 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:21816.3-21817.37" + process $proc$libresoc.v:21816$651 + assign { } { } + assign $0\prev_wr_go[4:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[4:0] + end + attribute \src "libresoc.v:21818.3-21819.40" + process $proc$libresoc.v:21818$652 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_alu0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "libresoc.v:21820.3-21821.25" + process $proc$libresoc.v:21820$653 + assign { } { } + assign $0\all_rd_dly[0:0] \$11 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "libresoc.v:21910.3-21919.6" + process $proc$libresoc.v:21910$654 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:21911.5-21911.29" + switch \initial + attribute \src "libresoc.v:21911.9-21911.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$55 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$47 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "libresoc.v:21920.3-21928.6" + process $proc$libresoc.v:21920$655 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$656 $1\rok_l_s_rdok$next[0:0]$657 + attribute \src "libresoc.v:21921.5-21921.29" + switch \initial + attribute \src "libresoc.v:21921.9-21921.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$657 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$657 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$656 + end + attribute \src "libresoc.v:21929.3-21937.6" + process $proc$libresoc.v:21929$658 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$659 $1\rok_l_r_rdok$next[0:0]$660 + attribute \src "libresoc.v:21930.5-21930.29" + switch \initial + attribute \src "libresoc.v:21930.9-21930.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$660 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$660 \$65 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$659 + end + attribute \src "libresoc.v:21938.3-21946.6" + process $proc$libresoc.v:21938$661 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$662 $1\rst_l_s_rst$next[0:0]$663 + attribute \src "libresoc.v:21939.5-21939.29" + switch \initial + attribute \src "libresoc.v:21939.9-21939.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$663 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$663 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$662 + end + attribute \src "libresoc.v:21947.3-21955.6" + process $proc$libresoc.v:21947$664 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$665 $1\rst_l_r_rst$next[0:0]$666 + attribute \src "libresoc.v:21948.5-21948.29" + switch \initial + attribute \src "libresoc.v:21948.9-21948.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$666 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$666 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$665 + end + attribute \src "libresoc.v:21956.3-21964.6" + process $proc$libresoc.v:21956$667 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$668 $1\opc_l_s_opc$next[0:0]$669 + attribute \src "libresoc.v:21957.5-21957.29" + switch \initial + attribute \src "libresoc.v:21957.9-21957.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$669 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$669 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$668 + end + attribute \src "libresoc.v:21965.3-21973.6" + process $proc$libresoc.v:21965$670 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$671 $1\opc_l_r_opc$next[0:0]$672 + attribute \src "libresoc.v:21966.5-21966.29" + switch \initial + attribute \src "libresoc.v:21966.9-21966.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$672 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$672 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$671 + end + attribute \src "libresoc.v:21974.3-21982.6" + process $proc$libresoc.v:21974$673 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[3:0]$674 $1\src_l_s_src$next[3:0]$675 + attribute \src "libresoc.v:21975.5-21975.29" + switch \initial + attribute \src "libresoc.v:21975.9-21975.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[3:0]$675 4'0000 + case + assign $1\src_l_s_src$next[3:0]$675 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[3:0]$674 + end + attribute \src "libresoc.v:21983.3-21991.6" + process $proc$libresoc.v:21983$676 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[3:0]$677 $1\src_l_r_src$next[3:0]$678 + attribute \src "libresoc.v:21984.5-21984.29" + switch \initial + attribute \src "libresoc.v:21984.9-21984.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[3:0]$678 4'1111 + case + assign $1\src_l_r_src$next[3:0]$678 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[3:0]$677 + end + attribute \src "libresoc.v:21992.3-22000.6" + process $proc$libresoc.v:21992$679 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[4:0]$680 $1\req_l_s_req$next[4:0]$681 + attribute \src "libresoc.v:21993.5-21993.29" + switch \initial + attribute \src "libresoc.v:21993.9-21993.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[4:0]$681 5'00000 + case + assign $1\req_l_s_req$next[4:0]$681 \$67 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[4:0]$680 + end + attribute \src "libresoc.v:22001.3-22009.6" + process $proc$libresoc.v:22001$682 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[4:0]$683 $1\req_l_r_req$next[4:0]$684 + attribute \src "libresoc.v:22002.5-22002.29" + switch \initial + attribute \src "libresoc.v:22002.9-22002.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[4:0]$684 5'11111 + case + assign $1\req_l_r_req$next[4:0]$684 \$69 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[4:0]$683 + end + attribute \src "libresoc.v:22010.3-22048.6" + process $proc$libresoc.v:22010$685 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_alu0_alu_op__data_len$next[3:0]$686 $1\alu_alu0_alu_op__data_len$next[3:0]$704 + assign $0\alu_alu0_alu_op__fn_unit$next[11:0]$687 $1\alu_alu0_alu_op__fn_unit$next[11:0]$705 + assign { } { } + assign { } { } + assign $0\alu_alu0_alu_op__input_carry$next[1:0]$690 $1\alu_alu0_alu_op__input_carry$next[1:0]$708 + assign $0\alu_alu0_alu_op__insn$next[31:0]$691 $1\alu_alu0_alu_op__insn$next[31:0]$709 + assign $0\alu_alu0_alu_op__insn_type$next[6:0]$692 $1\alu_alu0_alu_op__insn_type$next[6:0]$710 + assign $0\alu_alu0_alu_op__invert_in$next[0:0]$693 $1\alu_alu0_alu_op__invert_in$next[0:0]$711 + assign $0\alu_alu0_alu_op__invert_out$next[0:0]$694 $1\alu_alu0_alu_op__invert_out$next[0:0]$712 + assign $0\alu_alu0_alu_op__is_32bit$next[0:0]$695 $1\alu_alu0_alu_op__is_32bit$next[0:0]$713 + assign $0\alu_alu0_alu_op__is_signed$next[0:0]$696 $1\alu_alu0_alu_op__is_signed$next[0:0]$714 + assign { } { } + assign { } { } + assign $0\alu_alu0_alu_op__output_carry$next[0:0]$699 $1\alu_alu0_alu_op__output_carry$next[0:0]$717 + assign { } { } + assign { } { } + assign $0\alu_alu0_alu_op__write_cr0$next[0:0]$702 $1\alu_alu0_alu_op__write_cr0$next[0:0]$720 + assign $0\alu_alu0_alu_op__zero_a$next[0:0]$703 $1\alu_alu0_alu_op__zero_a$next[0:0]$721 + assign $0\alu_alu0_alu_op__imm_data__data$next[63:0]$688 $2\alu_alu0_alu_op__imm_data__data$next[63:0]$722 + assign $0\alu_alu0_alu_op__imm_data__ok$next[0:0]$689 $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$723 + assign $0\alu_alu0_alu_op__oe__oe$next[0:0]$697 $2\alu_alu0_alu_op__oe__oe$next[0:0]$724 + assign $0\alu_alu0_alu_op__oe__ok$next[0:0]$698 $2\alu_alu0_alu_op__oe__ok$next[0:0]$725 + assign $0\alu_alu0_alu_op__rc__ok$next[0:0]$700 $2\alu_alu0_alu_op__rc__ok$next[0:0]$726 + assign $0\alu_alu0_alu_op__rc__rc$next[0:0]$701 $2\alu_alu0_alu_op__rc__rc$next[0:0]$727 + attribute \src "libresoc.v:22011.5-22011.29" + switch \initial + attribute \src "libresoc.v:22011.9-22011.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_alu0_alu_op__insn$next[31:0]$709 $1\alu_alu0_alu_op__data_len$next[3:0]$704 $1\alu_alu0_alu_op__is_signed$next[0:0]$714 $1\alu_alu0_alu_op__is_32bit$next[0:0]$713 $1\alu_alu0_alu_op__output_carry$next[0:0]$717 $1\alu_alu0_alu_op__input_carry$next[1:0]$708 $1\alu_alu0_alu_op__write_cr0$next[0:0]$720 $1\alu_alu0_alu_op__invert_out$next[0:0]$712 $1\alu_alu0_alu_op__zero_a$next[0:0]$721 $1\alu_alu0_alu_op__invert_in$next[0:0]$711 $1\alu_alu0_alu_op__oe__ok$next[0:0]$716 $1\alu_alu0_alu_op__oe__oe$next[0:0]$715 $1\alu_alu0_alu_op__rc__ok$next[0:0]$718 $1\alu_alu0_alu_op__rc__rc$next[0:0]$719 $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$707 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$706 $1\alu_alu0_alu_op__fn_unit$next[11:0]$705 $1\alu_alu0_alu_op__insn_type$next[6:0]$710 } { \oper_i_alu_alu0__insn \oper_i_alu_alu0__data_len \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__invert_in \oper_i_alu_alu0__oe__ok \oper_i_alu_alu0__oe__oe \oper_i_alu_alu0__rc__ok \oper_i_alu_alu0__rc__rc \oper_i_alu_alu0__imm_data__ok \oper_i_alu_alu0__imm_data__data \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__insn_type } + case + assign $1\alu_alu0_alu_op__data_len$next[3:0]$704 \alu_alu0_alu_op__data_len + assign $1\alu_alu0_alu_op__fn_unit$next[11:0]$705 \alu_alu0_alu_op__fn_unit + assign $1\alu_alu0_alu_op__imm_data__data$next[63:0]$706 \alu_alu0_alu_op__imm_data__data + assign $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$707 \alu_alu0_alu_op__imm_data__ok + assign $1\alu_alu0_alu_op__input_carry$next[1:0]$708 \alu_alu0_alu_op__input_carry + assign $1\alu_alu0_alu_op__insn$next[31:0]$709 \alu_alu0_alu_op__insn + assign $1\alu_alu0_alu_op__insn_type$next[6:0]$710 \alu_alu0_alu_op__insn_type + assign $1\alu_alu0_alu_op__invert_in$next[0:0]$711 \alu_alu0_alu_op__invert_in + assign $1\alu_alu0_alu_op__invert_out$next[0:0]$712 \alu_alu0_alu_op__invert_out + assign $1\alu_alu0_alu_op__is_32bit$next[0:0]$713 \alu_alu0_alu_op__is_32bit + assign $1\alu_alu0_alu_op__is_signed$next[0:0]$714 \alu_alu0_alu_op__is_signed + assign $1\alu_alu0_alu_op__oe__oe$next[0:0]$715 \alu_alu0_alu_op__oe__oe + assign $1\alu_alu0_alu_op__oe__ok$next[0:0]$716 \alu_alu0_alu_op__oe__ok + assign $1\alu_alu0_alu_op__output_carry$next[0:0]$717 \alu_alu0_alu_op__output_carry + assign $1\alu_alu0_alu_op__rc__ok$next[0:0]$718 \alu_alu0_alu_op__rc__ok + assign $1\alu_alu0_alu_op__rc__rc$next[0:0]$719 \alu_alu0_alu_op__rc__rc + assign $1\alu_alu0_alu_op__write_cr0$next[0:0]$720 \alu_alu0_alu_op__write_cr0 + assign $1\alu_alu0_alu_op__zero_a$next[0:0]$721 \alu_alu0_alu_op__zero_a + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_alu0_alu_op__imm_data__data$next[63:0]$722 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$723 1'0 + assign $2\alu_alu0_alu_op__rc__rc$next[0:0]$727 1'0 + assign $2\alu_alu0_alu_op__rc__ok$next[0:0]$726 1'0 + assign $2\alu_alu0_alu_op__oe__oe$next[0:0]$724 1'0 + assign $2\alu_alu0_alu_op__oe__ok$next[0:0]$725 1'0 + case + assign $2\alu_alu0_alu_op__imm_data__data$next[63:0]$722 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$706 + assign $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$723 $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$707 + assign $2\alu_alu0_alu_op__oe__oe$next[0:0]$724 $1\alu_alu0_alu_op__oe__oe$next[0:0]$715 + assign $2\alu_alu0_alu_op__oe__ok$next[0:0]$725 $1\alu_alu0_alu_op__oe__ok$next[0:0]$716 + assign $2\alu_alu0_alu_op__rc__ok$next[0:0]$726 $1\alu_alu0_alu_op__rc__ok$next[0:0]$718 + assign $2\alu_alu0_alu_op__rc__rc$next[0:0]$727 $1\alu_alu0_alu_op__rc__rc$next[0:0]$719 + end + sync always + update \alu_alu0_alu_op__data_len$next $0\alu_alu0_alu_op__data_len$next[3:0]$686 + update \alu_alu0_alu_op__fn_unit$next $0\alu_alu0_alu_op__fn_unit$next[11:0]$687 + update \alu_alu0_alu_op__imm_data__data$next $0\alu_alu0_alu_op__imm_data__data$next[63:0]$688 + update \alu_alu0_alu_op__imm_data__ok$next $0\alu_alu0_alu_op__imm_data__ok$next[0:0]$689 + update \alu_alu0_alu_op__input_carry$next $0\alu_alu0_alu_op__input_carry$next[1:0]$690 + update \alu_alu0_alu_op__insn$next $0\alu_alu0_alu_op__insn$next[31:0]$691 + update \alu_alu0_alu_op__insn_type$next $0\alu_alu0_alu_op__insn_type$next[6:0]$692 + update \alu_alu0_alu_op__invert_in$next $0\alu_alu0_alu_op__invert_in$next[0:0]$693 + update \alu_alu0_alu_op__invert_out$next $0\alu_alu0_alu_op__invert_out$next[0:0]$694 + update \alu_alu0_alu_op__is_32bit$next $0\alu_alu0_alu_op__is_32bit$next[0:0]$695 + update \alu_alu0_alu_op__is_signed$next $0\alu_alu0_alu_op__is_signed$next[0:0]$696 + update \alu_alu0_alu_op__oe__oe$next $0\alu_alu0_alu_op__oe__oe$next[0:0]$697 + update \alu_alu0_alu_op__oe__ok$next $0\alu_alu0_alu_op__oe__ok$next[0:0]$698 + update \alu_alu0_alu_op__output_carry$next $0\alu_alu0_alu_op__output_carry$next[0:0]$699 + update \alu_alu0_alu_op__rc__ok$next $0\alu_alu0_alu_op__rc__ok$next[0:0]$700 + update \alu_alu0_alu_op__rc__rc$next $0\alu_alu0_alu_op__rc__rc$next[0:0]$701 + update \alu_alu0_alu_op__write_cr0$next $0\alu_alu0_alu_op__write_cr0$next[0:0]$702 + update \alu_alu0_alu_op__zero_a$next $0\alu_alu0_alu_op__zero_a$next[0:0]$703 + end + attribute \src "libresoc.v:22049.3-22070.6" + process $proc$libresoc.v:22049$728 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$729 $2\data_r0__o$next[63:0]$733 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$730 $3\data_r0__o_ok$next[0:0]$735 + attribute \src "libresoc.v:22050.5-22050.29" + switch \initial + attribute \src "libresoc.v:22050.9-22050.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$732 $1\data_r0__o$next[63:0]$731 } { \o_ok \alu_alu0_o } + case + assign $1\data_r0__o$next[63:0]$731 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$732 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$734 $2\data_r0__o$next[63:0]$733 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$733 $1\data_r0__o$next[63:0]$731 + assign $2\data_r0__o_ok$next[0:0]$734 $1\data_r0__o_ok$next[0:0]$732 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$735 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$735 $2\data_r0__o_ok$next[0:0]$734 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$729 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$730 + end + attribute \src "libresoc.v:22071.3-22092.6" + process $proc$libresoc.v:22071$736 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__cr_a$next[3:0]$737 $2\data_r1__cr_a$next[3:0]$741 + assign { } { } + assign $0\data_r1__cr_a_ok$next[0:0]$738 $3\data_r1__cr_a_ok$next[0:0]$743 + attribute \src "libresoc.v:22072.5-22072.29" + switch \initial + attribute \src "libresoc.v:22072.9-22072.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__cr_a_ok$next[0:0]$740 $1\data_r1__cr_a$next[3:0]$739 } { \cr_a_ok \alu_alu0_cr_a } + case + assign $1\data_r1__cr_a$next[3:0]$739 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$740 \data_r1__cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__cr_a_ok$next[0:0]$742 $2\data_r1__cr_a$next[3:0]$741 } 5'00000 + case + assign $2\data_r1__cr_a$next[3:0]$741 $1\data_r1__cr_a$next[3:0]$739 + assign $2\data_r1__cr_a_ok$next[0:0]$742 $1\data_r1__cr_a_ok$next[0:0]$740 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__cr_a_ok$next[0:0]$743 1'0 + case + assign $3\data_r1__cr_a_ok$next[0:0]$743 $2\data_r1__cr_a_ok$next[0:0]$742 + end + sync always + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$737 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$738 + end + attribute \src "libresoc.v:22093.3-22114.6" + process $proc$libresoc.v:22093$744 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__xer_ca$next[1:0]$745 $2\data_r2__xer_ca$next[1:0]$749 + assign { } { } + assign $0\data_r2__xer_ca_ok$next[0:0]$746 $3\data_r2__xer_ca_ok$next[0:0]$751 + attribute \src "libresoc.v:22094.5-22094.29" + switch \initial + attribute \src "libresoc.v:22094.9-22094.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__xer_ca_ok$next[0:0]$748 $1\data_r2__xer_ca$next[1:0]$747 } { \xer_ca_ok \alu_alu0_xer_ca } + case + assign $1\data_r2__xer_ca$next[1:0]$747 \data_r2__xer_ca + assign $1\data_r2__xer_ca_ok$next[0:0]$748 \data_r2__xer_ca_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__xer_ca_ok$next[0:0]$750 $2\data_r2__xer_ca$next[1:0]$749 } 3'000 + case + assign $2\data_r2__xer_ca$next[1:0]$749 $1\data_r2__xer_ca$next[1:0]$747 + assign $2\data_r2__xer_ca_ok$next[0:0]$750 $1\data_r2__xer_ca_ok$next[0:0]$748 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__xer_ca_ok$next[0:0]$751 1'0 + case + assign $3\data_r2__xer_ca_ok$next[0:0]$751 $2\data_r2__xer_ca_ok$next[0:0]$750 + end + sync always + update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$745 + update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$746 + end + attribute \src "libresoc.v:22115.3-22136.6" + process $proc$libresoc.v:22115$752 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r3__xer_ov$next[1:0]$753 $2\data_r3__xer_ov$next[1:0]$757 + assign { } { } + assign $0\data_r3__xer_ov_ok$next[0:0]$754 $3\data_r3__xer_ov_ok$next[0:0]$759 + attribute \src "libresoc.v:22116.5-22116.29" + switch \initial + attribute \src "libresoc.v:22116.9-22116.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r3__xer_ov_ok$next[0:0]$756 $1\data_r3__xer_ov$next[1:0]$755 } { \xer_ov_ok \alu_alu0_xer_ov } + case + assign $1\data_r3__xer_ov$next[1:0]$755 \data_r3__xer_ov + assign $1\data_r3__xer_ov_ok$next[0:0]$756 \data_r3__xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r3__xer_ov_ok$next[0:0]$758 $2\data_r3__xer_ov$next[1:0]$757 } 3'000 + case + assign $2\data_r3__xer_ov$next[1:0]$757 $1\data_r3__xer_ov$next[1:0]$755 + assign $2\data_r3__xer_ov_ok$next[0:0]$758 $1\data_r3__xer_ov_ok$next[0:0]$756 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r3__xer_ov_ok$next[0:0]$759 1'0 + case + assign $3\data_r3__xer_ov_ok$next[0:0]$759 $2\data_r3__xer_ov_ok$next[0:0]$758 + end + sync always + update \data_r3__xer_ov$next $0\data_r3__xer_ov$next[1:0]$753 + update \data_r3__xer_ov_ok$next $0\data_r3__xer_ov_ok$next[0:0]$754 + end + attribute \src "libresoc.v:22137.3-22158.6" + process $proc$libresoc.v:22137$760 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r4__xer_so$next[0:0]$761 $2\data_r4__xer_so$next[0:0]$765 + assign { } { } + assign $0\data_r4__xer_so_ok$next[0:0]$762 $3\data_r4__xer_so_ok$next[0:0]$767 + attribute \src "libresoc.v:22138.5-22138.29" + switch \initial + attribute \src "libresoc.v:22138.9-22138.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r4__xer_so_ok$next[0:0]$764 $1\data_r4__xer_so$next[0:0]$763 } { \xer_so_ok \alu_alu0_xer_so } + case + assign $1\data_r4__xer_so$next[0:0]$763 \data_r4__xer_so + assign $1\data_r4__xer_so_ok$next[0:0]$764 \data_r4__xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r4__xer_so_ok$next[0:0]$766 $2\data_r4__xer_so$next[0:0]$765 } 2'00 + case + assign $2\data_r4__xer_so$next[0:0]$765 $1\data_r4__xer_so$next[0:0]$763 + assign $2\data_r4__xer_so_ok$next[0:0]$766 $1\data_r4__xer_so_ok$next[0:0]$764 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r4__xer_so_ok$next[0:0]$767 1'0 + case + assign $3\data_r4__xer_so_ok$next[0:0]$767 $2\data_r4__xer_so_ok$next[0:0]$766 + end + sync always + update \data_r4__xer_so$next $0\data_r4__xer_so$next[0:0]$761 + update \data_r4__xer_so_ok$next $0\data_r4__xer_so_ok$next[0:0]$762 + end + attribute \src "libresoc.v:22159.3-22168.6" + process $proc$libresoc.v:22159$768 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$769 $1\src_r0$next[63:0]$770 + attribute \src "libresoc.v:22160.5-22160.29" + switch \initial + attribute \src "libresoc.v:22160.9-22160.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_sel + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$770 \src_or_imm + case + assign $1\src_r0$next[63:0]$770 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$769 + end + attribute \src "libresoc.v:22169.3-22178.6" + process $proc$libresoc.v:22169$771 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$772 $1\src_r1$next[63:0]$773 + attribute \src "libresoc.v:22170.5-22170.29" + switch \initial + attribute \src "libresoc.v:22170.9-22170.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_sel$85 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$773 \src_or_imm$88 + case + assign $1\src_r1$next[63:0]$773 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$772 + end + attribute \src "libresoc.v:22179.3-22188.6" + process $proc$libresoc.v:22179$774 + assign { } { } + assign { } { } + assign $0\src_r2$next[0:0]$775 $1\src_r2$next[0:0]$776 + attribute \src "libresoc.v:22180.5-22180.29" + switch \initial + attribute \src "libresoc.v:22180.9-22180.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[0:0]$776 \src3_i + case + assign $1\src_r2$next[0:0]$776 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[0:0]$775 + end + attribute \src "libresoc.v:22189.3-22198.6" + process $proc$libresoc.v:22189$777 + assign { } { } + assign { } { } + assign $0\src_r3$next[1:0]$778 $1\src_r3$next[1:0]$779 + attribute \src "libresoc.v:22190.5-22190.29" + switch \initial + attribute \src "libresoc.v:22190.9-22190.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r3$next[1:0]$779 \src4_i + case + assign $1\src_r3$next[1:0]$779 \src_r3 + end + sync always + update \src_r3$next $0\src_r3$next[1:0]$778 + end + attribute \src "libresoc.v:22199.3-22207.6" + process $proc$libresoc.v:22199$780 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$781 $1\alui_l_r_alui$next[0:0]$782 + attribute \src "libresoc.v:22200.5-22200.29" + switch \initial + attribute \src "libresoc.v:22200.9-22200.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$782 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$782 \$99 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$781 + end + attribute \src "libresoc.v:22208.3-22216.6" + process $proc$libresoc.v:22208$783 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$784 $1\alu_l_r_alu$next[0:0]$785 + attribute \src "libresoc.v:22209.5-22209.29" + switch \initial + attribute \src "libresoc.v:22209.9-22209.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$785 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$785 \$101 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$784 + end + attribute \src "libresoc.v:22217.3-22226.6" + process $proc$libresoc.v:22217$786 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:22218.5-22218.29" + switch \initial + attribute \src "libresoc.v:22218.9-22218.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$129 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__o + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "libresoc.v:22227.3-22236.6" + process $proc$libresoc.v:22227$787 + assign { } { } + assign { } { } + assign $0\dest2_o[3:0] $1\dest2_o[3:0] + attribute \src "libresoc.v:22228.5-22228.29" + switch \initial + attribute \src "libresoc.v:22228.9-22228.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$131 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[3:0] \data_r1__cr_a + case + assign $1\dest2_o[3:0] 4'0000 + end + sync always + update \dest2_o $0\dest2_o[3:0] + end + attribute \src "libresoc.v:22237.3-22246.6" + process $proc$libresoc.v:22237$788 + assign { } { } + assign { } { } + assign $0\dest3_o[1:0] $1\dest3_o[1:0] + attribute \src "libresoc.v:22238.5-22238.29" + switch \initial + attribute \src "libresoc.v:22238.9-22238.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$133 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest3_o[1:0] \data_r2__xer_ca + case + assign $1\dest3_o[1:0] 2'00 + end + sync always + update \dest3_o $0\dest3_o[1:0] + end + attribute \src "libresoc.v:22247.3-22256.6" + process $proc$libresoc.v:22247$789 + assign { } { } + assign { } { } + assign $0\dest4_o[1:0] $1\dest4_o[1:0] + attribute \src "libresoc.v:22248.5-22248.29" + switch \initial + attribute \src "libresoc.v:22248.9-22248.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$135 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest4_o[1:0] \data_r3__xer_ov + case + assign $1\dest4_o[1:0] 2'00 + end + sync always + update \dest4_o $0\dest4_o[1:0] + end + attribute \src "libresoc.v:22257.3-22266.6" + process $proc$libresoc.v:22257$790 + assign { } { } + assign { } { } + assign $0\dest5_o[0:0] $1\dest5_o[0:0] + attribute \src "libresoc.v:22258.5-22258.29" + switch \initial + attribute \src "libresoc.v:22258.9-22258.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$137 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest5_o[0:0] \data_r4__xer_so + case + assign $1\dest5_o[0:0] 1'0 + end + sync always + update \dest5_o $0\dest5_o[0:0] + end + attribute \src "libresoc.v:22267.3-22275.6" + process $proc$libresoc.v:22267$791 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[4:0]$792 $1\prev_wr_go$next[4:0]$793 + attribute \src "libresoc.v:22268.5-22268.29" + switch \initial + attribute \src "libresoc.v:22268.9-22268.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[4:0]$793 5'00000 + case + assign $1\prev_wr_go$next[4:0]$793 \$21 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[4:0]$792 + end + connect \$5 $reduce_and$libresoc.v:21661$540_Y + connect \$99 $and$libresoc.v:21662$541_Y + connect \$101 $and$libresoc.v:21663$542_Y + connect \$103 $and$libresoc.v:21664$543_Y + connect \$105 $not$libresoc.v:21665$544_Y + connect \$107 $not$libresoc.v:21666$545_Y + connect \$109 $and$libresoc.v:21667$546_Y + connect \$111 $not$libresoc.v:21668$547_Y + connect \$113 $and$libresoc.v:21669$548_Y + connect \$115 $and$libresoc.v:21670$549_Y + connect \$117 $and$libresoc.v:21671$550_Y + connect \$11 $and$libresoc.v:21672$551_Y + connect \$119 $and$libresoc.v:21673$552_Y + connect \$121 $and$libresoc.v:21674$553_Y + connect \$123 $and$libresoc.v:21675$554_Y + connect \$125 $and$libresoc.v:21676$555_Y + connect \$127 $and$libresoc.v:21677$556_Y + connect \$129 $and$libresoc.v:21678$557_Y + connect \$131 $and$libresoc.v:21679$558_Y + connect \$133 $and$libresoc.v:21680$559_Y + connect \$135 $and$libresoc.v:21681$560_Y + connect \$137 $and$libresoc.v:21682$561_Y + connect \$13 $not$libresoc.v:21683$562_Y + connect \$15 $and$libresoc.v:21684$563_Y + connect \$17 $not$libresoc.v:21685$564_Y + connect \$19 $and$libresoc.v:21686$565_Y + connect \$21 $and$libresoc.v:21687$566_Y + connect \$25 $not$libresoc.v:21688$567_Y + connect \$27 $and$libresoc.v:21689$568_Y + connect \$24 $reduce_or$libresoc.v:21690$569_Y + connect \$23 $not$libresoc.v:21691$570_Y + connect \$31 $and$libresoc.v:21692$571_Y + connect \$33 $reduce_or$libresoc.v:21693$572_Y + connect \$35 $reduce_or$libresoc.v:21694$573_Y + connect \$37 $or$libresoc.v:21695$574_Y + connect \$3 $and$libresoc.v:21696$575_Y + connect \$39 $not$libresoc.v:21697$576_Y + connect \$41 $and$libresoc.v:21698$577_Y + connect \$43 $and$libresoc.v:21699$578_Y + connect \$45 $eq$libresoc.v:21700$579_Y + connect \$47 $and$libresoc.v:21701$580_Y + connect \$49 $eq$libresoc.v:21702$581_Y + connect \$51 $and$libresoc.v:21703$582_Y + connect \$53 $and$libresoc.v:21704$583_Y + connect \$55 $and$libresoc.v:21705$584_Y + connect \$57 $or$libresoc.v:21706$585_Y + connect \$59 $or$libresoc.v:21707$586_Y + connect \$61 $or$libresoc.v:21708$587_Y + connect \$63 $or$libresoc.v:21709$588_Y + connect \$65 $and$libresoc.v:21710$589_Y + connect \$67 $and$libresoc.v:21711$590_Y + connect \$6 $not$libresoc.v:21712$591_Y + connect \$69 $or$libresoc.v:21713$592_Y + connect \$71 $and$libresoc.v:21714$593_Y + connect \$73 $and$libresoc.v:21715$594_Y + connect \$75 $and$libresoc.v:21716$595_Y + connect \$77 $and$libresoc.v:21717$596_Y + connect \$79 $and$libresoc.v:21718$597_Y + connect \$81 $ternary$libresoc.v:21719$598_Y + connect \$83 $ternary$libresoc.v:21720$599_Y + connect \$86 $ternary$libresoc.v:21721$600_Y + connect \$8 $or$libresoc.v:21722$601_Y + connect \$89 $ternary$libresoc.v:21723$602_Y + connect \$91 $ternary$libresoc.v:21724$603_Y + connect \$93 $ternary$libresoc.v:21725$604_Y + connect \$95 $ternary$libresoc.v:21726$605_Y + connect \$97 $ternary$libresoc.v:21727$606_Y + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \cu_wr__rel_o \$127 + connect \cu_rd__rel_o \$113 + connect \cu_busy_o \opc_l_q_opc + connect \alu_l_s_alu \all_rd_pulse + connect \alu_alu0_n_ready_i \alu_l_q_alu + connect \alui_l_s_alui \all_rd_pulse + connect \alu_alu0_p_valid_i \alui_l_q_alui + connect \alu_alu0_xer_ca$2 \$97 + connect \alu_alu0_xer_so$1 \$95 + connect \alu_alu0_rb \$93 + connect \alu_alu0_ra \$91 + connect \src_or_imm$88 \$89 + connect \src_sel$85 \$86 + connect \src_or_imm \$83 + connect \src_sel \$81 + connect \cu_wrmask_o { \$79 \$77 \$75 \$73 \$71 } + connect \reset_r \$63 + connect \reset_w \$61 + connect \rst_r \$59 + connect \reset \$57 + connect \wr_any \$37 + connect \cu_done_o \$31 + connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse } + connect \alu_pulse \alu_done_rise + connect \alu_done_rise \$19 + connect \alu_done_dly$next \alu_done + connect \alu_done \alu_alu0_n_valid_o + connect \all_rd_pulse \all_rd_rise + connect \all_rd_rise \$15 + connect \all_rd_dly$next \all_rd + connect \all_rd \$11 +end +attribute \src "libresoc.v:22313.1-23373.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0" +attribute \generator "nMigen" +module \alu_alu0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 25 \alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$70 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 10 \alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_op__fn_unit$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 11 \alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__data$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__imm_data__ok$57 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 21 \alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 26 \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$71 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 9 \alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_op__insn_type$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_in$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_out$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 23 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_32bit$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 24 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_signed$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__oe$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__ok$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 22 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__output_carry$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__ok$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__rc$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__write_cr0$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__zero_a$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 38 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 28 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$53 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 8 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 7 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 27 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 37 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 36 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe1_alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe1_alu_op__data_len$20 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe1_alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe1_alu_op__fn_unit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe1_alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe1_alu_op__imm_data__data$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__imm_data__ok$7 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe1_alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe1_alu_op__input_carry$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe1_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe1_alu_op__insn$21 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe1_alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe1_alu_op__insn_type$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__invert_in$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__oe__oe$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__oe__ok$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__rc__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__rc__rc$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__write_cr0$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__zero_a$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \pipe1_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe1_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe1_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe1_muxid$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \pipe1_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \pipe1_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe1_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \pipe1_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \pipe1_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \pipe1_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \pipe1_xer_ca$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe1_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \pipe1_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe1_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe1_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe1_xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe1_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe2_alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe2_alu_op__data_len$41 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe2_alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe2_alu_op__fn_unit$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_alu_op__imm_data__data$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__imm_data__ok$28 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe2_alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe2_alu_op__input_carry$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe2_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe2_alu_op__insn$42 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe2_alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe2_alu_op__insn_type$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__invert_in$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__invert_out$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__is_32bit$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__is_signed$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__oe__oe$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__oe__ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__output_carry$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__rc__ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__rc__rc$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__write_cr0$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__zero_a$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \pipe2_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \pipe2_cr_a$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_cr_a_ok$46 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe2_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe2_muxid$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \pipe2_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \pipe2_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe2_o$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_o_ok$44 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \pipe2_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \pipe2_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \pipe2_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \pipe2_xer_ca$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_xer_ca_ok$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \pipe2_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \pipe2_xer_ov$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_xer_ov_ok$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_xer_so$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_xer_so_ok$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 32 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 33 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 29 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 35 \xer_ca$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 30 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 5 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 31 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 34 \xer_so$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 6 \xer_so_ok + attribute \module_not_derived 1 + attribute \src "libresoc.v:23212.5-23215.4" + cell \n \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:23216.5-23219.4" + cell \p \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:23220.9-23279.4" + cell \pipe1 \pipe1 + connect \alu_op__data_len \pipe1_alu_op__data_len + connect \alu_op__data_len$18 \pipe1_alu_op__data_len$20 + connect \alu_op__fn_unit \pipe1_alu_op__fn_unit + connect \alu_op__fn_unit$3 \pipe1_alu_op__fn_unit$5 + connect \alu_op__imm_data__data \pipe1_alu_op__imm_data__data + connect \alu_op__imm_data__data$4 \pipe1_alu_op__imm_data__data$6 + connect \alu_op__imm_data__ok \pipe1_alu_op__imm_data__ok + connect \alu_op__imm_data__ok$5 \pipe1_alu_op__imm_data__ok$7 + connect \alu_op__input_carry \pipe1_alu_op__input_carry + connect \alu_op__input_carry$14 \pipe1_alu_op__input_carry$16 + connect \alu_op__insn \pipe1_alu_op__insn + connect \alu_op__insn$19 \pipe1_alu_op__insn$21 + connect \alu_op__insn_type \pipe1_alu_op__insn_type + connect \alu_op__insn_type$2 \pipe1_alu_op__insn_type$4 + connect \alu_op__invert_in \pipe1_alu_op__invert_in + connect \alu_op__invert_in$10 \pipe1_alu_op__invert_in$12 + connect \alu_op__invert_out \pipe1_alu_op__invert_out + connect \alu_op__invert_out$12 \pipe1_alu_op__invert_out$14 + connect \alu_op__is_32bit \pipe1_alu_op__is_32bit + connect \alu_op__is_32bit$16 \pipe1_alu_op__is_32bit$18 + connect \alu_op__is_signed \pipe1_alu_op__is_signed + connect \alu_op__is_signed$17 \pipe1_alu_op__is_signed$19 + connect \alu_op__oe__oe \pipe1_alu_op__oe__oe + connect \alu_op__oe__oe$8 \pipe1_alu_op__oe__oe$10 + connect \alu_op__oe__ok \pipe1_alu_op__oe__ok + connect \alu_op__oe__ok$9 \pipe1_alu_op__oe__ok$11 + connect \alu_op__output_carry \pipe1_alu_op__output_carry + connect \alu_op__output_carry$15 \pipe1_alu_op__output_carry$17 + connect \alu_op__rc__ok \pipe1_alu_op__rc__ok + connect \alu_op__rc__ok$7 \pipe1_alu_op__rc__ok$9 + connect \alu_op__rc__rc \pipe1_alu_op__rc__rc + connect \alu_op__rc__rc$6 \pipe1_alu_op__rc__rc$8 + connect \alu_op__write_cr0 \pipe1_alu_op__write_cr0 + connect \alu_op__write_cr0$13 \pipe1_alu_op__write_cr0$15 + connect \alu_op__zero_a \pipe1_alu_op__zero_a + connect \alu_op__zero_a$11 \pipe1_alu_op__zero_a$13 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \pipe1_cr_a + connect \cr_a_ok \pipe1_cr_a_ok + connect \muxid \pipe1_muxid + connect \muxid$1 \pipe1_muxid$3 + connect \n_ready_i \pipe1_n_ready_i + connect \n_valid_o \pipe1_n_valid_o + connect \o \pipe1_o + connect \o_ok \pipe1_o_ok + connect \p_ready_o \pipe1_p_ready_o + connect \p_valid_i \pipe1_p_valid_i + connect \ra \pipe1_ra + connect \rb \pipe1_rb + connect \xer_ca \pipe1_xer_ca + connect \xer_ca$21 \pipe1_xer_ca$23 + connect \xer_ca_ok \pipe1_xer_ca_ok + connect \xer_ov \pipe1_xer_ov + connect \xer_ov_ok \pipe1_xer_ov_ok + connect \xer_so \pipe1_xer_so + connect \xer_so$20 \pipe1_xer_so$22 + connect \xer_so_ok \pipe1_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:23280.9-23345.4" + cell \pipe2 \pipe2 + connect \alu_op__data_len \pipe2_alu_op__data_len + connect \alu_op__data_len$18 \pipe2_alu_op__data_len$41 + connect \alu_op__fn_unit \pipe2_alu_op__fn_unit + connect \alu_op__fn_unit$3 \pipe2_alu_op__fn_unit$26 + connect \alu_op__imm_data__data \pipe2_alu_op__imm_data__data + connect \alu_op__imm_data__data$4 \pipe2_alu_op__imm_data__data$27 + connect \alu_op__imm_data__ok \pipe2_alu_op__imm_data__ok + connect \alu_op__imm_data__ok$5 \pipe2_alu_op__imm_data__ok$28 + connect \alu_op__input_carry \pipe2_alu_op__input_carry + connect \alu_op__input_carry$14 \pipe2_alu_op__input_carry$37 + connect \alu_op__insn \pipe2_alu_op__insn + connect \alu_op__insn$19 \pipe2_alu_op__insn$42 + connect \alu_op__insn_type \pipe2_alu_op__insn_type + connect \alu_op__insn_type$2 \pipe2_alu_op__insn_type$25 + connect \alu_op__invert_in \pipe2_alu_op__invert_in + connect \alu_op__invert_in$10 \pipe2_alu_op__invert_in$33 + connect \alu_op__invert_out \pipe2_alu_op__invert_out + connect \alu_op__invert_out$12 \pipe2_alu_op__invert_out$35 + connect \alu_op__is_32bit \pipe2_alu_op__is_32bit + connect \alu_op__is_32bit$16 \pipe2_alu_op__is_32bit$39 + connect \alu_op__is_signed \pipe2_alu_op__is_signed + connect \alu_op__is_signed$17 \pipe2_alu_op__is_signed$40 + connect \alu_op__oe__oe \pipe2_alu_op__oe__oe + connect \alu_op__oe__oe$8 \pipe2_alu_op__oe__oe$31 + connect \alu_op__oe__ok \pipe2_alu_op__oe__ok + connect \alu_op__oe__ok$9 \pipe2_alu_op__oe__ok$32 + connect \alu_op__output_carry \pipe2_alu_op__output_carry + connect \alu_op__output_carry$15 \pipe2_alu_op__output_carry$38 + connect \alu_op__rc__ok \pipe2_alu_op__rc__ok + connect \alu_op__rc__ok$7 \pipe2_alu_op__rc__ok$30 + connect \alu_op__rc__rc \pipe2_alu_op__rc__rc + connect \alu_op__rc__rc$6 \pipe2_alu_op__rc__rc$29 + connect \alu_op__write_cr0 \pipe2_alu_op__write_cr0 + connect \alu_op__write_cr0$13 \pipe2_alu_op__write_cr0$36 + connect \alu_op__zero_a \pipe2_alu_op__zero_a + connect \alu_op__zero_a$11 \pipe2_alu_op__zero_a$34 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \pipe2_cr_a + connect \cr_a$22 \pipe2_cr_a$45 + connect \cr_a_ok \pipe2_cr_a_ok + connect \cr_a_ok$23 \pipe2_cr_a_ok$46 + connect \muxid \pipe2_muxid + connect \muxid$1 \pipe2_muxid$24 + connect \n_ready_i \pipe2_n_ready_i + connect \n_valid_o \pipe2_n_valid_o + connect \o \pipe2_o + connect \o$20 \pipe2_o$43 + connect \o_ok \pipe2_o_ok + connect \o_ok$21 \pipe2_o_ok$44 + connect \p_ready_o \pipe2_p_ready_o + connect \p_valid_i \pipe2_p_valid_i + connect \xer_ca \pipe2_xer_ca + connect \xer_ca$24 \pipe2_xer_ca$47 + connect \xer_ca_ok \pipe2_xer_ca_ok + connect \xer_ca_ok$25 \pipe2_xer_ca_ok$48 + connect \xer_ov \pipe2_xer_ov + connect \xer_ov$26 \pipe2_xer_ov$49 + connect \xer_ov_ok \pipe2_xer_ov_ok + connect \xer_ov_ok$27 \pipe2_xer_ov_ok$50 + connect \xer_so \pipe2_xer_so + connect \xer_so$28 \pipe2_xer_so$51 + connect \xer_so_ok \pipe2_xer_so_ok + connect \xer_so_ok$29 \pipe2_xer_so_ok$52 + end + connect \muxid 2'00 + connect { \xer_so_ok \xer_so } { \pipe2_xer_so_ok$52 \pipe2_xer_so$51 } + connect { \xer_ov_ok \xer_ov } { \pipe2_xer_ov_ok$50 \pipe2_xer_ov$49 } + connect { \xer_ca_ok \xer_ca } { \pipe2_xer_ca_ok$48 \pipe2_xer_ca$47 } + connect { \cr_a_ok \cr_a } { \pipe2_cr_a_ok$46 \pipe2_cr_a$45 } + connect { \o_ok \o } { \pipe2_o_ok$44 \pipe2_o$43 } + connect { \alu_op__insn$71 \alu_op__data_len$70 \alu_op__is_signed$69 \alu_op__is_32bit$68 \alu_op__output_carry$67 \alu_op__input_carry$66 \alu_op__write_cr0$65 \alu_op__invert_out$64 \alu_op__zero_a$63 \alu_op__invert_in$62 \alu_op__oe__ok$61 \alu_op__oe__oe$60 \alu_op__rc__ok$59 \alu_op__rc__rc$58 \alu_op__imm_data__ok$57 \alu_op__imm_data__data$56 \alu_op__fn_unit$55 \alu_op__insn_type$54 } { \pipe2_alu_op__insn$42 \pipe2_alu_op__data_len$41 \pipe2_alu_op__is_signed$40 \pipe2_alu_op__is_32bit$39 \pipe2_alu_op__output_carry$38 \pipe2_alu_op__input_carry$37 \pipe2_alu_op__write_cr0$36 \pipe2_alu_op__invert_out$35 \pipe2_alu_op__zero_a$34 \pipe2_alu_op__invert_in$33 \pipe2_alu_op__oe__ok$32 \pipe2_alu_op__oe__oe$31 \pipe2_alu_op__rc__ok$30 \pipe2_alu_op__rc__rc$29 \pipe2_alu_op__imm_data__ok$28 \pipe2_alu_op__imm_data__data$27 \pipe2_alu_op__fn_unit$26 \pipe2_alu_op__insn_type$25 } + connect \muxid$53 \pipe2_muxid$24 + connect \pipe2_n_ready_i \n_ready_i + connect \n_valid_o \pipe2_n_valid_o + connect \pipe1_xer_ca$23 \xer_ca$2 + connect \pipe1_xer_so$22 \xer_so$1 + connect \pipe1_rb \rb + connect \pipe1_ra \ra + connect { \pipe1_alu_op__insn$21 \pipe1_alu_op__data_len$20 \pipe1_alu_op__is_signed$19 \pipe1_alu_op__is_32bit$18 \pipe1_alu_op__output_carry$17 \pipe1_alu_op__input_carry$16 \pipe1_alu_op__write_cr0$15 \pipe1_alu_op__invert_out$14 \pipe1_alu_op__zero_a$13 \pipe1_alu_op__invert_in$12 \pipe1_alu_op__oe__ok$11 \pipe1_alu_op__oe__oe$10 \pipe1_alu_op__rc__ok$9 \pipe1_alu_op__rc__rc$8 \pipe1_alu_op__imm_data__ok$7 \pipe1_alu_op__imm_data__data$6 \pipe1_alu_op__fn_unit$5 \pipe1_alu_op__insn_type$4 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } + connect \pipe1_muxid$3 2'00 + connect \p_ready_o \pipe1_p_ready_o + connect \pipe1_p_valid_i \p_valid_i + connect { \pipe2_xer_so_ok \pipe2_xer_so } { \pipe1_xer_so_ok \pipe1_xer_so } + connect { \pipe2_xer_ov_ok \pipe2_xer_ov } { \pipe1_xer_ov_ok \pipe1_xer_ov } + connect { \pipe2_xer_ca_ok \pipe2_xer_ca } { \pipe1_xer_ca_ok \pipe1_xer_ca } + connect { \pipe2_cr_a_ok \pipe2_cr_a } { \pipe1_cr_a_ok \pipe1_cr_a } + connect { \pipe2_o_ok \pipe2_o } { \pipe1_o_ok \pipe1_o } + connect { \pipe2_alu_op__insn \pipe2_alu_op__data_len \pipe2_alu_op__is_signed \pipe2_alu_op__is_32bit \pipe2_alu_op__output_carry \pipe2_alu_op__input_carry \pipe2_alu_op__write_cr0 \pipe2_alu_op__invert_out \pipe2_alu_op__zero_a \pipe2_alu_op__invert_in \pipe2_alu_op__oe__ok \pipe2_alu_op__oe__oe \pipe2_alu_op__rc__ok \pipe2_alu_op__rc__rc \pipe2_alu_op__imm_data__ok \pipe2_alu_op__imm_data__data \pipe2_alu_op__fn_unit \pipe2_alu_op__insn_type } { \pipe1_alu_op__insn \pipe1_alu_op__data_len \pipe1_alu_op__is_signed \pipe1_alu_op__is_32bit \pipe1_alu_op__output_carry \pipe1_alu_op__input_carry \pipe1_alu_op__write_cr0 \pipe1_alu_op__invert_out \pipe1_alu_op__zero_a \pipe1_alu_op__invert_in \pipe1_alu_op__oe__ok \pipe1_alu_op__oe__oe \pipe1_alu_op__rc__ok \pipe1_alu_op__rc__rc \pipe1_alu_op__imm_data__ok \pipe1_alu_op__imm_data__data \pipe1_alu_op__fn_unit \pipe1_alu_op__insn_type } + connect \pipe2_muxid \pipe1_muxid + connect \pipe1_n_ready_i \pipe2_p_ready_o + connect \pipe2_p_valid_i \pipe1_n_valid_o +end +attribute \src "libresoc.v:23377.1-23912.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0" +attribute \generator "nMigen" +module \alu_branch0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \br_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \br_op__cia$15 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 9 \br_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \br_op__fn_unit$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 11 \br_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \br_op__imm_data__data$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \br_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__imm_data__ok$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 10 \br_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \br_op__insn$18 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 8 \br_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \br_op__insn_type$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \br_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__is_32bit$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \br_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__lk$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 23 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 20 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 15 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 18 \fast1$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 16 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \fast2$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 6 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 5 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 17 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \nia_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 22 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 21 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_br_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_br_op__cia$4 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_br_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_br_op__fn_unit$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_br_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_br_op__imm_data__data$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_br_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_br_op__imm_data__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_br_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_br_op__insn$7 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_br_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_br_op__insn_type$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_br_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_br_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_br_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_br_op__lk$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \pipe_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe_fast1$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe_fast2$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_fast2_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_muxid$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \pipe_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \pipe_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe_nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_nia_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \pipe_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \pipe_p_valid_i + attribute \module_not_derived 1 + attribute \src "libresoc.v:23854.10-23857.4" + cell \n$18 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:23858.10-23861.4" + cell \p$17 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:23862.13-23896.4" + cell \pipe$19 \pipe + connect \br_op__cia \pipe_br_op__cia + connect \br_op__cia$2 \pipe_br_op__cia$4 + connect \br_op__fn_unit \pipe_br_op__fn_unit + connect \br_op__fn_unit$4 \pipe_br_op__fn_unit$6 + connect \br_op__imm_data__data \pipe_br_op__imm_data__data + connect \br_op__imm_data__data$6 \pipe_br_op__imm_data__data$8 + connect \br_op__imm_data__ok \pipe_br_op__imm_data__ok + connect \br_op__imm_data__ok$7 \pipe_br_op__imm_data__ok$9 + connect \br_op__insn \pipe_br_op__insn + connect \br_op__insn$5 \pipe_br_op__insn$7 + connect \br_op__insn_type \pipe_br_op__insn_type + connect \br_op__insn_type$3 \pipe_br_op__insn_type$5 + connect \br_op__is_32bit \pipe_br_op__is_32bit + connect \br_op__is_32bit$9 \pipe_br_op__is_32bit$11 + connect \br_op__lk \pipe_br_op__lk + connect \br_op__lk$8 \pipe_br_op__lk$10 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \pipe_cr_a + connect \fast1 \pipe_fast1 + connect \fast1$10 \pipe_fast1$12 + connect \fast1_ok \pipe_fast1_ok + connect \fast2 \pipe_fast2 + connect \fast2$11 \pipe_fast2$13 + connect \fast2_ok \pipe_fast2_ok + connect \muxid \pipe_muxid + connect \muxid$1 \pipe_muxid$3 + connect \n_ready_i \pipe_n_ready_i + connect \n_valid_o \pipe_n_valid_o + connect \nia \pipe_nia + connect \nia_ok \pipe_nia_ok + connect \p_ready_o \pipe_p_ready_o + connect \p_valid_i \pipe_p_valid_i + end + connect \muxid 2'00 + connect { \nia_ok \nia } { \pipe_nia_ok \pipe_nia } + connect { \fast2_ok \fast2 } { \pipe_fast2_ok \pipe_fast2$13 } + connect { \fast1_ok \fast1 } { \pipe_fast1_ok \pipe_fast1$12 } + connect { \br_op__is_32bit$22 \br_op__lk$21 \br_op__imm_data__ok$20 \br_op__imm_data__data$19 \br_op__insn$18 \br_op__fn_unit$17 \br_op__insn_type$16 \br_op__cia$15 } { \pipe_br_op__is_32bit$11 \pipe_br_op__lk$10 \pipe_br_op__imm_data__ok$9 \pipe_br_op__imm_data__data$8 \pipe_br_op__insn$7 \pipe_br_op__fn_unit$6 \pipe_br_op__insn_type$5 \pipe_br_op__cia$4 } + connect \muxid$14 \pipe_muxid$3 + connect \pipe_n_ready_i \n_ready_i + connect \n_valid_o \pipe_n_valid_o + connect \pipe_cr_a \cr_a + connect \pipe_fast2 \fast2$2 + connect \pipe_fast1 \fast1$1 + connect { \pipe_br_op__is_32bit \pipe_br_op__lk \pipe_br_op__imm_data__ok \pipe_br_op__imm_data__data \pipe_br_op__insn \pipe_br_op__fn_unit \pipe_br_op__insn_type \pipe_br_op__cia } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } + connect \pipe_muxid 2'00 + connect \p_ready_o \pipe_p_ready_o + connect \pipe_p_valid_i \p_valid_i +end +attribute \src "libresoc.v:23916.1-24419.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0" +attribute \generator "nMigen" +module \alu_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 21 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 12 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 16 \cr_a$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 17 \cr_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 18 \cr_c + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 8 \cr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \cr_op__fn_unit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 9 \cr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \cr_op__insn$12 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 7 \cr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \cr_op__insn_type$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 32 output 11 \full_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 32 input 15 \full_cr$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \full_cr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 6 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 5 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 10 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 20 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 19 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \pipe_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \pipe_cr_a$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \pipe_cr_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \pipe_cr_c + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_cr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_cr_op__fn_unit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_cr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_cr_op__insn$6 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_cr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_cr_op__insn_type$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 32 \pipe_full_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 32 \pipe_full_cr$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_full_cr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_muxid$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \pipe_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \pipe_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \pipe_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \pipe_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 13 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \rb + attribute \module_not_derived 1 + attribute \src "libresoc.v:24365.9-24368.4" + cell \n$6 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:24369.9-24372.4" + cell \p$5 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:24373.8-24400.4" + cell \pipe \pipe + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \pipe_cr_a + connect \cr_a$6 \pipe_cr_a$8 + connect \cr_a_ok \pipe_cr_a_ok + connect \cr_b \pipe_cr_b + connect \cr_c \pipe_cr_c + connect \cr_op__fn_unit \pipe_cr_op__fn_unit + connect \cr_op__fn_unit$3 \pipe_cr_op__fn_unit$5 + connect \cr_op__insn \pipe_cr_op__insn + connect \cr_op__insn$4 \pipe_cr_op__insn$6 + connect \cr_op__insn_type \pipe_cr_op__insn_type + connect \cr_op__insn_type$2 \pipe_cr_op__insn_type$4 + connect \full_cr \pipe_full_cr + connect \full_cr$5 \pipe_full_cr$7 + connect \full_cr_ok \pipe_full_cr_ok + connect \muxid \pipe_muxid + connect \muxid$1 \pipe_muxid$3 + connect \n_ready_i \pipe_n_ready_i + connect \n_valid_o \pipe_n_valid_o + connect \o \pipe_o + connect \o_ok \pipe_o_ok + connect \p_ready_o \pipe_p_ready_o + connect \p_valid_i \pipe_p_valid_i + connect \ra \pipe_ra + connect \rb \pipe_rb + end + connect \muxid 2'00 + connect { \cr_a_ok \cr_a } { \pipe_cr_a_ok \pipe_cr_a$8 } + connect { \full_cr_ok \full_cr } { \pipe_full_cr_ok \pipe_full_cr$7 } + connect { \o_ok \o } { \pipe_o_ok \pipe_o } + connect { \cr_op__insn$12 \cr_op__fn_unit$11 \cr_op__insn_type$10 } { \pipe_cr_op__insn$6 \pipe_cr_op__fn_unit$5 \pipe_cr_op__insn_type$4 } + connect \muxid$9 \pipe_muxid$3 + connect \pipe_n_ready_i \n_ready_i + connect \n_valid_o \pipe_n_valid_o + connect \pipe_cr_c \cr_c + connect \pipe_cr_b \cr_b + connect \pipe_cr_a \cr_a$2 + connect \pipe_full_cr \full_cr$1 + connect \pipe_rb \rb + connect \pipe_ra \ra + connect { \pipe_cr_op__insn \pipe_cr_op__fn_unit \pipe_cr_op__insn_type } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } + connect \pipe_muxid 2'00 + connect \p_ready_o \pipe_p_ready_o + connect \pipe_p_valid_i \p_valid_i +end +attribute \src "libresoc.v:24423.1-25864.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0" +attribute \generator "nMigen" +module \alu_div0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 35 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 27 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 24 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$88 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 9 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_op__fn_unit$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 10 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$75 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 18 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 25 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$89 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 8 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 22 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 23 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 21 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$81 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$71 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 7 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 6 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 26 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 34 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 33 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \pipe_end_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_end_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \pipe_end_div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \pipe_end_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \pipe_end_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \pipe_end_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \pipe_end_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_end_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_end_logical_op__data_len$68 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_end_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_end_logical_op__fn_unit$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_end_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_end_logical_op__imm_data__data$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__imm_data__ok$55 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_end_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_end_logical_op__input_carry$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_end_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_end_logical_op__insn$69 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_end_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_end_logical_op__insn_type$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__invert_in$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__invert_out$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__is_32bit$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__is_signed$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__oe__oe$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__oe__ok$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__output_carry$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__rc__ok$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__rc__rc$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__write_cr0$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__zero_a$61 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_end_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_end_muxid$51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \pipe_end_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \pipe_end_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe_end_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_end_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \pipe_end_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \pipe_end_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 64 \pipe_end_quotient_root + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_end_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_end_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" + wire width 192 \pipe_end_remainder + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \pipe_end_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_end_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe_end_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_end_xer_so$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_end_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \pipe_middle_0_div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \pipe_middle_0_div_by_zero$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \pipe_middle_0_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \pipe_middle_0_dive_abs_ov32$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \pipe_middle_0_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \pipe_middle_0_dive_abs_ov64$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \pipe_middle_0_dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \pipe_middle_0_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \pipe_middle_0_dividend_neg$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \pipe_middle_0_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \pipe_middle_0_divisor_neg$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \pipe_middle_0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_0_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_0_logical_op__data_len$41 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_middle_0_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_middle_0_logical_op__fn_unit$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_0_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_0_logical_op__imm_data__data$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__imm_data__ok$28 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_0_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_0_logical_op__input_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_0_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_0_logical_op__insn$42 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_0_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_0_logical_op__insn_type$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__invert_in$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__invert_out$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__is_32bit$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__is_signed$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__oe__oe$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__oe__ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__output_carry$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__rc__ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__rc__rc$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__write_cr0$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__zero_a$34 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_0_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_0_muxid$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \pipe_middle_0_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \pipe_middle_0_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \pipe_middle_0_operation + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \pipe_middle_0_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \pipe_middle_0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 64 \pipe_middle_0_quotient_root + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_0_ra$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_0_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_0_rb$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" + wire width 192 \pipe_middle_0_remainder + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe_middle_0_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe_middle_0_xer_so$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \pipe_start_div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \pipe_start_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \pipe_start_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \pipe_start_dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \pipe_start_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \pipe_start_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \pipe_start_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_start_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_start_logical_op__data_len$19 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_start_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_start_logical_op__fn_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_start_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_start_logical_op__imm_data__data$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__imm_data__ok$6 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_start_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_start_logical_op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_start_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_start_logical_op__insn$20 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_start_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_start_logical_op__insn_type$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__invert_in$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__is_32bit$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__is_signed$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__oe__ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__output_carry$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__rc__ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__write_cr0$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__zero_a$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_start_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_start_muxid$2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \pipe_start_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \pipe_start_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \pipe_start_operation + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \pipe_start_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \pipe_start_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_start_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_start_ra$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_start_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_start_rb$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe_start_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe_start_xer_so$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 30 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 31 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 28 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 29 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 32 \xer_so$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 5 \xer_so_ok + attribute \module_not_derived 1 + attribute \src "libresoc.v:25620.10-25623.4" + cell \n$75 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:25624.10-25627.4" + cell \p$74 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:25628.12-25691.4" + cell \pipe_end \pipe_end + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \pipe_end_cr_a + connect \cr_a_ok \pipe_end_cr_a_ok + connect \div_by_zero \pipe_end_div_by_zero + connect \dive_abs_ov32 \pipe_end_dive_abs_ov32 + connect \dive_abs_ov64 \pipe_end_dive_abs_ov64 + connect \dividend_neg \pipe_end_dividend_neg + connect \divisor_neg \pipe_end_divisor_neg + connect \logical_op__data_len \pipe_end_logical_op__data_len + connect \logical_op__data_len$18 \pipe_end_logical_op__data_len$68 + connect \logical_op__fn_unit \pipe_end_logical_op__fn_unit + connect \logical_op__fn_unit$3 \pipe_end_logical_op__fn_unit$53 + connect \logical_op__imm_data__data \pipe_end_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \pipe_end_logical_op__imm_data__data$54 + connect \logical_op__imm_data__ok \pipe_end_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \pipe_end_logical_op__imm_data__ok$55 + connect \logical_op__input_carry \pipe_end_logical_op__input_carry + connect \logical_op__input_carry$12 \pipe_end_logical_op__input_carry$62 + connect \logical_op__insn \pipe_end_logical_op__insn + connect \logical_op__insn$19 \pipe_end_logical_op__insn$69 + connect \logical_op__insn_type \pipe_end_logical_op__insn_type + connect \logical_op__insn_type$2 \pipe_end_logical_op__insn_type$52 + connect \logical_op__invert_in \pipe_end_logical_op__invert_in + connect \logical_op__invert_in$10 \pipe_end_logical_op__invert_in$60 + connect \logical_op__invert_out \pipe_end_logical_op__invert_out + connect \logical_op__invert_out$13 \pipe_end_logical_op__invert_out$63 + connect \logical_op__is_32bit \pipe_end_logical_op__is_32bit + connect \logical_op__is_32bit$16 \pipe_end_logical_op__is_32bit$66 + connect \logical_op__is_signed \pipe_end_logical_op__is_signed + connect \logical_op__is_signed$17 \pipe_end_logical_op__is_signed$67 + connect \logical_op__oe__oe \pipe_end_logical_op__oe__oe + connect \logical_op__oe__oe$8 \pipe_end_logical_op__oe__oe$58 + connect \logical_op__oe__ok \pipe_end_logical_op__oe__ok + connect \logical_op__oe__ok$9 \pipe_end_logical_op__oe__ok$59 + connect \logical_op__output_carry \pipe_end_logical_op__output_carry + connect \logical_op__output_carry$15 \pipe_end_logical_op__output_carry$65 + connect \logical_op__rc__ok \pipe_end_logical_op__rc__ok + connect \logical_op__rc__ok$7 \pipe_end_logical_op__rc__ok$57 + connect \logical_op__rc__rc \pipe_end_logical_op__rc__rc + connect \logical_op__rc__rc$6 \pipe_end_logical_op__rc__rc$56 + connect \logical_op__write_cr0 \pipe_end_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \pipe_end_logical_op__write_cr0$64 + connect \logical_op__zero_a \pipe_end_logical_op__zero_a + connect \logical_op__zero_a$11 \pipe_end_logical_op__zero_a$61 + connect \muxid \pipe_end_muxid + connect \muxid$1 \pipe_end_muxid$51 + connect \n_ready_i \pipe_end_n_ready_i + connect \n_valid_o \pipe_end_n_valid_o + connect \o \pipe_end_o + connect \o_ok \pipe_end_o_ok + connect \p_ready_o \pipe_end_p_ready_o + connect \p_valid_i \pipe_end_p_valid_i + connect \quotient_root \pipe_end_quotient_root + connect \ra \pipe_end_ra + connect \rb \pipe_end_rb + connect \remainder \pipe_end_remainder + connect \xer_ov \pipe_end_xer_ov + connect \xer_ov_ok \pipe_end_xer_ov_ok + connect \xer_so \pipe_end_xer_so + connect \xer_so$20 \pipe_end_xer_so$70 + connect \xer_so_ok \pipe_end_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:25692.17-25758.4" + cell \pipe_middle_0 \pipe_middle_0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \div_by_zero \pipe_middle_0_div_by_zero + connect \div_by_zero$27 \pipe_middle_0_div_by_zero$50 + connect \dive_abs_ov32 \pipe_middle_0_dive_abs_ov32 + connect \dive_abs_ov32$25 \pipe_middle_0_dive_abs_ov32$48 + connect \dive_abs_ov64 \pipe_middle_0_dive_abs_ov64 + connect \dive_abs_ov64$26 \pipe_middle_0_dive_abs_ov64$49 + connect \dividend \pipe_middle_0_dividend + connect \dividend_neg \pipe_middle_0_dividend_neg + connect \dividend_neg$24 \pipe_middle_0_dividend_neg$47 + connect \divisor_neg \pipe_middle_0_divisor_neg + connect \divisor_neg$23 \pipe_middle_0_divisor_neg$46 + connect \divisor_radicand \pipe_middle_0_divisor_radicand + connect \logical_op__data_len \pipe_middle_0_logical_op__data_len + connect \logical_op__data_len$18 \pipe_middle_0_logical_op__data_len$41 + connect \logical_op__fn_unit \pipe_middle_0_logical_op__fn_unit + connect \logical_op__fn_unit$3 \pipe_middle_0_logical_op__fn_unit$26 + connect \logical_op__imm_data__data \pipe_middle_0_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \pipe_middle_0_logical_op__imm_data__data$27 + connect \logical_op__imm_data__ok \pipe_middle_0_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \pipe_middle_0_logical_op__imm_data__ok$28 + connect \logical_op__input_carry \pipe_middle_0_logical_op__input_carry + connect \logical_op__input_carry$12 \pipe_middle_0_logical_op__input_carry$35 + connect \logical_op__insn \pipe_middle_0_logical_op__insn + connect \logical_op__insn$19 \pipe_middle_0_logical_op__insn$42 + connect \logical_op__insn_type \pipe_middle_0_logical_op__insn_type + connect \logical_op__insn_type$2 \pipe_middle_0_logical_op__insn_type$25 + connect \logical_op__invert_in \pipe_middle_0_logical_op__invert_in + connect \logical_op__invert_in$10 \pipe_middle_0_logical_op__invert_in$33 + connect \logical_op__invert_out \pipe_middle_0_logical_op__invert_out + connect \logical_op__invert_out$13 \pipe_middle_0_logical_op__invert_out$36 + connect \logical_op__is_32bit \pipe_middle_0_logical_op__is_32bit + connect \logical_op__is_32bit$16 \pipe_middle_0_logical_op__is_32bit$39 + connect \logical_op__is_signed \pipe_middle_0_logical_op__is_signed + connect \logical_op__is_signed$17 \pipe_middle_0_logical_op__is_signed$40 + connect \logical_op__oe__oe \pipe_middle_0_logical_op__oe__oe + connect \logical_op__oe__oe$8 \pipe_middle_0_logical_op__oe__oe$31 + connect \logical_op__oe__ok \pipe_middle_0_logical_op__oe__ok + connect \logical_op__oe__ok$9 \pipe_middle_0_logical_op__oe__ok$32 + connect \logical_op__output_carry \pipe_middle_0_logical_op__output_carry + connect \logical_op__output_carry$15 \pipe_middle_0_logical_op__output_carry$38 + connect \logical_op__rc__ok \pipe_middle_0_logical_op__rc__ok + connect \logical_op__rc__ok$7 \pipe_middle_0_logical_op__rc__ok$30 + connect \logical_op__rc__rc \pipe_middle_0_logical_op__rc__rc + connect \logical_op__rc__rc$6 \pipe_middle_0_logical_op__rc__rc$29 + connect \logical_op__write_cr0 \pipe_middle_0_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \pipe_middle_0_logical_op__write_cr0$37 + connect \logical_op__zero_a \pipe_middle_0_logical_op__zero_a + connect \logical_op__zero_a$11 \pipe_middle_0_logical_op__zero_a$34 + connect \muxid \pipe_middle_0_muxid + connect \muxid$1 \pipe_middle_0_muxid$24 + connect \n_ready_i \pipe_middle_0_n_ready_i + connect \n_valid_o \pipe_middle_0_n_valid_o + connect \operation \pipe_middle_0_operation + connect \p_ready_o \pipe_middle_0_p_ready_o + connect \p_valid_i \pipe_middle_0_p_valid_i + connect \quotient_root \pipe_middle_0_quotient_root + connect \ra \pipe_middle_0_ra + connect \ra$20 \pipe_middle_0_ra$43 + connect \rb \pipe_middle_0_rb + connect \rb$21 \pipe_middle_0_rb$44 + connect \remainder \pipe_middle_0_remainder + connect \xer_so \pipe_middle_0_xer_so + connect \xer_so$22 \pipe_middle_0_xer_so$45 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:25759.14-25818.4" + cell \pipe_start \pipe_start + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \div_by_zero \pipe_start_div_by_zero + connect \dive_abs_ov32 \pipe_start_dive_abs_ov32 + connect \dive_abs_ov64 \pipe_start_dive_abs_ov64 + connect \dividend \pipe_start_dividend + connect \dividend_neg \pipe_start_dividend_neg + connect \divisor_neg \pipe_start_divisor_neg + connect \divisor_radicand \pipe_start_divisor_radicand + connect \logical_op__data_len \pipe_start_logical_op__data_len + connect \logical_op__data_len$18 \pipe_start_logical_op__data_len$19 + connect \logical_op__fn_unit \pipe_start_logical_op__fn_unit + connect \logical_op__fn_unit$3 \pipe_start_logical_op__fn_unit$4 + connect \logical_op__imm_data__data \pipe_start_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \pipe_start_logical_op__imm_data__data$5 + connect \logical_op__imm_data__ok \pipe_start_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \pipe_start_logical_op__imm_data__ok$6 + connect \logical_op__input_carry \pipe_start_logical_op__input_carry + connect \logical_op__input_carry$12 \pipe_start_logical_op__input_carry$13 + connect \logical_op__insn \pipe_start_logical_op__insn + connect \logical_op__insn$19 \pipe_start_logical_op__insn$20 + connect \logical_op__insn_type \pipe_start_logical_op__insn_type + connect \logical_op__insn_type$2 \pipe_start_logical_op__insn_type$3 + connect \logical_op__invert_in \pipe_start_logical_op__invert_in + connect \logical_op__invert_in$10 \pipe_start_logical_op__invert_in$11 + connect \logical_op__invert_out \pipe_start_logical_op__invert_out + connect \logical_op__invert_out$13 \pipe_start_logical_op__invert_out$14 + connect \logical_op__is_32bit \pipe_start_logical_op__is_32bit + connect \logical_op__is_32bit$16 \pipe_start_logical_op__is_32bit$17 + connect \logical_op__is_signed \pipe_start_logical_op__is_signed + connect \logical_op__is_signed$17 \pipe_start_logical_op__is_signed$18 + connect \logical_op__oe__oe \pipe_start_logical_op__oe__oe + connect \logical_op__oe__oe$8 \pipe_start_logical_op__oe__oe$9 + connect \logical_op__oe__ok \pipe_start_logical_op__oe__ok + connect \logical_op__oe__ok$9 \pipe_start_logical_op__oe__ok$10 + connect \logical_op__output_carry \pipe_start_logical_op__output_carry + connect \logical_op__output_carry$15 \pipe_start_logical_op__output_carry$16 + connect \logical_op__rc__ok \pipe_start_logical_op__rc__ok + connect \logical_op__rc__ok$7 \pipe_start_logical_op__rc__ok$8 + connect \logical_op__rc__rc \pipe_start_logical_op__rc__rc + connect \logical_op__rc__rc$6 \pipe_start_logical_op__rc__rc$7 + connect \logical_op__write_cr0 \pipe_start_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \pipe_start_logical_op__write_cr0$15 + connect \logical_op__zero_a \pipe_start_logical_op__zero_a + connect \logical_op__zero_a$11 \pipe_start_logical_op__zero_a$12 + connect \muxid \pipe_start_muxid + connect \muxid$1 \pipe_start_muxid$2 + connect \n_ready_i \pipe_start_n_ready_i + connect \n_valid_o \pipe_start_n_valid_o + connect \operation \pipe_start_operation + connect \p_ready_o \pipe_start_p_ready_o + connect \p_valid_i \pipe_start_p_valid_i + connect \ra \pipe_start_ra + connect \ra$20 \pipe_start_ra$21 + connect \rb \pipe_start_rb + connect \rb$21 \pipe_start_rb$22 + connect \xer_so \pipe_start_xer_so + connect \xer_so$22 \pipe_start_xer_so$23 + end + connect \muxid 2'00 + connect { \xer_so_ok \xer_so } { \pipe_end_xer_so_ok \pipe_end_xer_so$70 } + connect { \xer_ov_ok \xer_ov } { \pipe_end_xer_ov_ok \pipe_end_xer_ov } + connect { \cr_a_ok \cr_a } { \pipe_end_cr_a_ok \pipe_end_cr_a } + connect { \o_ok \o } { \pipe_end_o_ok \pipe_end_o } + connect { \logical_op__insn$89 \logical_op__data_len$88 \logical_op__is_signed$87 \logical_op__is_32bit$86 \logical_op__output_carry$85 \logical_op__write_cr0$84 \logical_op__invert_out$83 \logical_op__input_carry$82 \logical_op__zero_a$81 \logical_op__invert_in$80 \logical_op__oe__ok$79 \logical_op__oe__oe$78 \logical_op__rc__ok$77 \logical_op__rc__rc$76 \logical_op__imm_data__ok$75 \logical_op__imm_data__data$74 \logical_op__fn_unit$73 \logical_op__insn_type$72 } { \pipe_end_logical_op__insn$69 \pipe_end_logical_op__data_len$68 \pipe_end_logical_op__is_signed$67 \pipe_end_logical_op__is_32bit$66 \pipe_end_logical_op__output_carry$65 \pipe_end_logical_op__write_cr0$64 \pipe_end_logical_op__invert_out$63 \pipe_end_logical_op__input_carry$62 \pipe_end_logical_op__zero_a$61 \pipe_end_logical_op__invert_in$60 \pipe_end_logical_op__oe__ok$59 \pipe_end_logical_op__oe__oe$58 \pipe_end_logical_op__rc__ok$57 \pipe_end_logical_op__rc__rc$56 \pipe_end_logical_op__imm_data__ok$55 \pipe_end_logical_op__imm_data__data$54 \pipe_end_logical_op__fn_unit$53 \pipe_end_logical_op__insn_type$52 } + connect \muxid$71 \pipe_end_muxid$51 + connect \pipe_end_n_ready_i \n_ready_i + connect \n_valid_o \pipe_end_n_valid_o + connect \pipe_start_xer_so$23 \xer_so$1 + connect \pipe_start_rb$22 \rb + connect \pipe_start_ra$21 \ra + connect { \pipe_start_logical_op__insn$20 \pipe_start_logical_op__data_len$19 \pipe_start_logical_op__is_signed$18 \pipe_start_logical_op__is_32bit$17 \pipe_start_logical_op__output_carry$16 \pipe_start_logical_op__write_cr0$15 \pipe_start_logical_op__invert_out$14 \pipe_start_logical_op__input_carry$13 \pipe_start_logical_op__zero_a$12 \pipe_start_logical_op__invert_in$11 \pipe_start_logical_op__oe__ok$10 \pipe_start_logical_op__oe__oe$9 \pipe_start_logical_op__rc__ok$8 \pipe_start_logical_op__rc__rc$7 \pipe_start_logical_op__imm_data__ok$6 \pipe_start_logical_op__imm_data__data$5 \pipe_start_logical_op__fn_unit$4 \pipe_start_logical_op__insn_type$3 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \pipe_start_muxid$2 2'00 + connect \p_ready_o \pipe_start_p_ready_o + connect \pipe_start_p_valid_i \p_valid_i + connect \pipe_end_remainder \pipe_middle_0_remainder + connect \pipe_end_quotient_root \pipe_middle_0_quotient_root + connect \pipe_end_div_by_zero \pipe_middle_0_div_by_zero$50 + connect \pipe_end_dive_abs_ov64 \pipe_middle_0_dive_abs_ov64$49 + connect \pipe_end_dive_abs_ov32 \pipe_middle_0_dive_abs_ov32$48 + connect \pipe_end_dividend_neg \pipe_middle_0_dividend_neg$47 + connect \pipe_end_divisor_neg \pipe_middle_0_divisor_neg$46 + connect \pipe_end_xer_so \pipe_middle_0_xer_so$45 + connect \pipe_end_rb \pipe_middle_0_rb$44 + connect \pipe_end_ra \pipe_middle_0_ra$43 + connect { \pipe_end_logical_op__insn \pipe_end_logical_op__data_len \pipe_end_logical_op__is_signed \pipe_end_logical_op__is_32bit \pipe_end_logical_op__output_carry \pipe_end_logical_op__write_cr0 \pipe_end_logical_op__invert_out \pipe_end_logical_op__input_carry \pipe_end_logical_op__zero_a \pipe_end_logical_op__invert_in \pipe_end_logical_op__oe__ok \pipe_end_logical_op__oe__oe \pipe_end_logical_op__rc__ok \pipe_end_logical_op__rc__rc \pipe_end_logical_op__imm_data__ok \pipe_end_logical_op__imm_data__data \pipe_end_logical_op__fn_unit \pipe_end_logical_op__insn_type } { \pipe_middle_0_logical_op__insn$42 \pipe_middle_0_logical_op__data_len$41 \pipe_middle_0_logical_op__is_signed$40 \pipe_middle_0_logical_op__is_32bit$39 \pipe_middle_0_logical_op__output_carry$38 \pipe_middle_0_logical_op__write_cr0$37 \pipe_middle_0_logical_op__invert_out$36 \pipe_middle_0_logical_op__input_carry$35 \pipe_middle_0_logical_op__zero_a$34 \pipe_middle_0_logical_op__invert_in$33 \pipe_middle_0_logical_op__oe__ok$32 \pipe_middle_0_logical_op__oe__oe$31 \pipe_middle_0_logical_op__rc__ok$30 \pipe_middle_0_logical_op__rc__rc$29 \pipe_middle_0_logical_op__imm_data__ok$28 \pipe_middle_0_logical_op__imm_data__data$27 \pipe_middle_0_logical_op__fn_unit$26 \pipe_middle_0_logical_op__insn_type$25 } + connect \pipe_end_muxid \pipe_middle_0_muxid$24 + connect \pipe_middle_0_n_ready_i \pipe_end_p_ready_o + connect \pipe_end_p_valid_i \pipe_middle_0_n_valid_o + connect \pipe_middle_0_operation \pipe_start_operation + connect \pipe_middle_0_divisor_radicand \pipe_start_divisor_radicand + connect \pipe_middle_0_dividend \pipe_start_dividend + connect \pipe_middle_0_div_by_zero \pipe_start_div_by_zero + connect \pipe_middle_0_dive_abs_ov64 \pipe_start_dive_abs_ov64 + connect \pipe_middle_0_dive_abs_ov32 \pipe_start_dive_abs_ov32 + connect \pipe_middle_0_dividend_neg \pipe_start_dividend_neg + connect \pipe_middle_0_divisor_neg \pipe_start_divisor_neg + connect \pipe_middle_0_xer_so \pipe_start_xer_so + connect \pipe_middle_0_rb \pipe_start_rb + connect \pipe_middle_0_ra \pipe_start_ra + connect { \pipe_middle_0_logical_op__insn \pipe_middle_0_logical_op__data_len \pipe_middle_0_logical_op__is_signed \pipe_middle_0_logical_op__is_32bit \pipe_middle_0_logical_op__output_carry \pipe_middle_0_logical_op__write_cr0 \pipe_middle_0_logical_op__invert_out \pipe_middle_0_logical_op__input_carry \pipe_middle_0_logical_op__zero_a \pipe_middle_0_logical_op__invert_in \pipe_middle_0_logical_op__oe__ok \pipe_middle_0_logical_op__oe__oe \pipe_middle_0_logical_op__rc__ok \pipe_middle_0_logical_op__rc__rc \pipe_middle_0_logical_op__imm_data__ok \pipe_middle_0_logical_op__imm_data__data \pipe_middle_0_logical_op__fn_unit \pipe_middle_0_logical_op__insn_type } { \pipe_start_logical_op__insn \pipe_start_logical_op__data_len \pipe_start_logical_op__is_signed \pipe_start_logical_op__is_32bit \pipe_start_logical_op__output_carry \pipe_start_logical_op__write_cr0 \pipe_start_logical_op__invert_out \pipe_start_logical_op__input_carry \pipe_start_logical_op__zero_a \pipe_start_logical_op__invert_in \pipe_start_logical_op__oe__ok \pipe_start_logical_op__oe__oe \pipe_start_logical_op__rc__ok \pipe_start_logical_op__rc__rc \pipe_start_logical_op__imm_data__ok \pipe_start_logical_op__imm_data__data \pipe_start_logical_op__fn_unit \pipe_start_logical_op__insn_type } + connect \pipe_middle_0_muxid \pipe_start_muxid + connect \pipe_start_n_ready_i \pipe_middle_0_p_ready_o + connect \pipe_middle_0_p_valid_i \pipe_start_n_valid_o +end +attribute \src "libresoc.v:25868.1-25926.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_l" +attribute \generator "nMigen" +module \alu_l + attribute \src "libresoc.v:25869.7-25869.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:25914.3-25922.6" + wire $0\q_int$next[0:0]$852 + attribute \src "libresoc.v:25912.3-25913.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:25914.3-25922.6" + wire $1\q_int$next[0:0]$853 + attribute \src "libresoc.v:25893.7-25893.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:25904.17-25904.96" + wire $and$libresoc.v:25904$842_Y + attribute \src "libresoc.v:25909.17-25909.96" + wire $and$libresoc.v:25909$847_Y + attribute \src "libresoc.v:25906.18-25906.93" + wire $not$libresoc.v:25906$844_Y + attribute \src "libresoc.v:25908.17-25908.92" + wire $not$libresoc.v:25908$846_Y + attribute \src "libresoc.v:25911.17-25911.92" + wire $not$libresoc.v:25911$849_Y + attribute \src "libresoc.v:25905.18-25905.98" + wire $or$libresoc.v:25905$843_Y + attribute \src "libresoc.v:25907.18-25907.99" + wire $or$libresoc.v:25907$845_Y + attribute \src "libresoc.v:25910.17-25910.97" + wire $or$libresoc.v:25910$848_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:25869.7-25869.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:25904$842 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:25904$842_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:25909$847 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:25909$847_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:25906$844 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$libresoc.v:25906$844_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:25908$846 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:25908$846_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:25911$849 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:25911$849_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:25905$843 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$libresoc.v:25905$843_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:25907$845 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$libresoc.v:25907$845_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:25910$848 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$libresoc.v:25910$848_Y + end + attribute \src "libresoc.v:25869.7-25869.20" + process $proc$libresoc.v:25869$854 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:25893.7-25893.19" + process $proc$libresoc.v:25893$855 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:25912.3-25913.27" + process $proc$libresoc.v:25912$850 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:25914.3-25922.6" + process $proc$libresoc.v:25914$851 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$852 $1\q_int$next[0:0]$853 + attribute \src "libresoc.v:25915.5-25915.29" + switch \initial + attribute \src "libresoc.v:25915.9-25915.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$853 1'0 + case + assign $1\q_int$next[0:0]$853 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$852 + end + connect \$9 $and$libresoc.v:25904$842_Y + connect \$11 $or$libresoc.v:25905$843_Y + connect \$13 $not$libresoc.v:25906$844_Y + connect \$15 $or$libresoc.v:25907$845_Y + connect \$1 $not$libresoc.v:25908$846_Y + connect \$3 $and$libresoc.v:25909$847_Y + connect \$5 $or$libresoc.v:25910$848_Y + connect \$7 $not$libresoc.v:25911$849_Y + connect \qlq_alu \$15 + connect \qn_alu \$13 + connect \q_alu \$11 +end +attribute \src "libresoc.v:25930.1-25988.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_l" +attribute \generator "nMigen" +module \alu_l$107 + attribute \src "libresoc.v:25931.7-25931.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:25976.3-25984.6" + wire $0\q_int$next[0:0]$866 + attribute \src "libresoc.v:25974.3-25975.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:25976.3-25984.6" + wire $1\q_int$next[0:0]$867 + attribute \src "libresoc.v:25955.7-25955.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:25966.17-25966.96" + wire $and$libresoc.v:25966$856_Y + attribute \src "libresoc.v:25971.17-25971.96" + wire $and$libresoc.v:25971$861_Y + attribute \src "libresoc.v:25968.18-25968.93" + wire $not$libresoc.v:25968$858_Y + attribute \src "libresoc.v:25970.17-25970.92" + wire $not$libresoc.v:25970$860_Y + attribute \src "libresoc.v:25973.17-25973.92" + wire $not$libresoc.v:25973$863_Y + attribute \src "libresoc.v:25967.18-25967.98" + wire $or$libresoc.v:25967$857_Y + attribute \src "libresoc.v:25969.18-25969.99" + wire $or$libresoc.v:25969$859_Y + attribute \src "libresoc.v:25972.17-25972.97" + wire $or$libresoc.v:25972$862_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:25931.7-25931.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:25966$856 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:25966$856_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:25971$861 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:25971$861_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:25968$858 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$libresoc.v:25968$858_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:25970$860 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:25970$860_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:25973$863 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:25973$863_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:25967$857 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$libresoc.v:25967$857_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:25969$859 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$libresoc.v:25969$859_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:25972$862 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$libresoc.v:25972$862_Y + end + attribute \src "libresoc.v:25931.7-25931.20" + process $proc$libresoc.v:25931$868 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:25955.7-25955.19" + process $proc$libresoc.v:25955$869 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:25974.3-25975.27" + process $proc$libresoc.v:25974$864 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:25976.3-25984.6" + process $proc$libresoc.v:25976$865 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$866 $1\q_int$next[0:0]$867 + attribute \src "libresoc.v:25977.5-25977.29" + switch \initial + attribute \src "libresoc.v:25977.9-25977.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$867 1'0 + case + assign $1\q_int$next[0:0]$867 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$866 + end + connect \$9 $and$libresoc.v:25966$856_Y + connect \$11 $or$libresoc.v:25967$857_Y + connect \$13 $not$libresoc.v:25968$858_Y + connect \$15 $or$libresoc.v:25969$859_Y + connect \$1 $not$libresoc.v:25970$860_Y + connect \$3 $and$libresoc.v:25971$861_Y + connect \$5 $or$libresoc.v:25972$862_Y + connect \$7 $not$libresoc.v:25973$863_Y + connect \qlq_alu \$15 + connect \qn_alu \$13 + connect \q_alu \$11 +end +attribute \src "libresoc.v:25992.1-26050.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_l" +attribute \generator "nMigen" +module \alu_l$125 + attribute \src "libresoc.v:25993.7-25993.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:26038.3-26046.6" + wire $0\q_int$next[0:0]$880 + attribute \src "libresoc.v:26036.3-26037.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:26038.3-26046.6" + wire $1\q_int$next[0:0]$881 + attribute \src "libresoc.v:26017.7-26017.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:26028.17-26028.96" + wire $and$libresoc.v:26028$870_Y + attribute \src "libresoc.v:26033.17-26033.96" + wire $and$libresoc.v:26033$875_Y + attribute \src "libresoc.v:26030.18-26030.93" + wire $not$libresoc.v:26030$872_Y + attribute \src "libresoc.v:26032.17-26032.92" + wire $not$libresoc.v:26032$874_Y + attribute \src "libresoc.v:26035.17-26035.92" + wire $not$libresoc.v:26035$877_Y + attribute \src "libresoc.v:26029.18-26029.98" + wire $or$libresoc.v:26029$871_Y + attribute \src "libresoc.v:26031.18-26031.99" + wire $or$libresoc.v:26031$873_Y + attribute \src "libresoc.v:26034.17-26034.97" + wire $or$libresoc.v:26034$876_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:25993.7-25993.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:26028$870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:26028$870_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:26033$875 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:26033$875_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:26030$872 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$libresoc.v:26030$872_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:26032$874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26032$874_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:26035$877 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26035$877_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:26029$871 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$libresoc.v:26029$871_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:26031$873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$libresoc.v:26031$873_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:26034$876 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$libresoc.v:26034$876_Y + end + attribute \src "libresoc.v:25993.7-25993.20" + process $proc$libresoc.v:25993$882 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:26017.7-26017.19" + process $proc$libresoc.v:26017$883 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:26036.3-26037.27" + process $proc$libresoc.v:26036$878 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:26038.3-26046.6" + process $proc$libresoc.v:26038$879 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$880 $1\q_int$next[0:0]$881 + attribute \src "libresoc.v:26039.5-26039.29" + switch \initial + attribute \src "libresoc.v:26039.9-26039.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$881 1'0 + case + assign $1\q_int$next[0:0]$881 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$880 + end + connect \$9 $and$libresoc.v:26028$870_Y + connect \$11 $or$libresoc.v:26029$871_Y + connect \$13 $not$libresoc.v:26030$872_Y + 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$and$libresoc.v:26095$889_Y + attribute \src "libresoc.v:26092.18-26092.93" + wire $not$libresoc.v:26092$886_Y + attribute \src "libresoc.v:26094.17-26094.92" + wire $not$libresoc.v:26094$888_Y + attribute \src "libresoc.v:26097.17-26097.92" + wire $not$libresoc.v:26097$891_Y + attribute \src "libresoc.v:26091.18-26091.98" + wire $or$libresoc.v:26091$885_Y + attribute \src "libresoc.v:26093.18-26093.99" + wire $or$libresoc.v:26093$887_Y + attribute \src "libresoc.v:26096.17-26096.97" + wire $or$libresoc.v:26096$890_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src 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\A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$libresoc.v:26093$887_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:26096$890 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$libresoc.v:26096$890_Y + end + attribute \src "libresoc.v:26055.7-26055.20" + process $proc$libresoc.v:26055$896 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:26079.7-26079.19" + process $proc$libresoc.v:26079$897 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:26098.3-26099.27" + process $proc$libresoc.v:26098$892 + assign { } { } + assign $0\q_int[0:0] \q_int$next + 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$and$libresoc.v:26152$898 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:26152$898_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:26157$903 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:26157$903_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:26154$900 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$libresoc.v:26154$900_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:26156$902 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y 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"libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$923 1'0 + case + assign $1\q_int$next[0:0]$923 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$922 + end + connect \$9 $and$libresoc.v:26214$912_Y + connect \$11 $or$libresoc.v:26215$913_Y + connect \$13 $not$libresoc.v:26216$914_Y + connect \$15 $or$libresoc.v:26217$915_Y + connect \$1 $not$libresoc.v:26218$916_Y + connect \$3 $and$libresoc.v:26219$917_Y + connect \$5 $or$libresoc.v:26220$918_Y + connect \$7 $not$libresoc.v:26221$919_Y + connect \qlq_alu \$15 + connect \qn_alu \$13 + connect \q_alu \$11 +end +attribute \src "libresoc.v:26240.1-26298.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_l" +attribute \generator "nMigen" +module \alu_l$45 + attribute \src "libresoc.v:26241.7-26241.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:26286.3-26294.6" + wire $0\q_int$next[0:0]$936 + attribute \src "libresoc.v:26284.3-26285.27" + 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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:26241.7-26241.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:26276$926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:26276$926_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:26281$931 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:26281$931_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:26278$928 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$libresoc.v:26278$928_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:26280$930 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26280$930_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:26283$933 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26283$933_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:26277$927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$libresoc.v:26277$927_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:26279$929 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$libresoc.v:26279$929_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:26282$932 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$libresoc.v:26282$932_Y + end + attribute \src "libresoc.v:26241.7-26241.20" + process $proc$libresoc.v:26241$938 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:26265.7-26265.19" + process $proc$libresoc.v:26265$939 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:26284.3-26285.27" + process $proc$libresoc.v:26284$934 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:26286.3-26294.6" + process $proc$libresoc.v:26286$935 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$936 $1\q_int$next[0:0]$937 + attribute \src "libresoc.v:26287.5-26287.29" + switch \initial + attribute \src "libresoc.v:26287.9-26287.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$937 1'0 + case + assign $1\q_int$next[0:0]$937 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$936 + end + connect \$9 $and$libresoc.v:26276$926_Y + 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$and$libresoc.v:26338$940_Y + attribute \src "libresoc.v:26343.17-26343.96" + wire $and$libresoc.v:26343$945_Y + attribute \src "libresoc.v:26340.18-26340.93" + wire $not$libresoc.v:26340$942_Y + attribute \src "libresoc.v:26342.17-26342.92" + wire $not$libresoc.v:26342$944_Y + attribute \src "libresoc.v:26345.17-26345.92" + wire $not$libresoc.v:26345$947_Y + attribute \src "libresoc.v:26339.18-26339.98" + wire $or$libresoc.v:26339$941_Y + attribute \src "libresoc.v:26341.18-26341.99" + wire $or$libresoc.v:26341$943_Y + attribute \src "libresoc.v:26344.17-26344.97" + wire $or$libresoc.v:26344$946_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:26338$940 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:26338$940_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:26343$945 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:26343$945_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:26340$942 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$libresoc.v:26340$942_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:26342$944 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26342$944_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:26345$947 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26345$947_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:26339$941 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$libresoc.v:26339$941_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:26341$943 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$libresoc.v:26341$943_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:26344$946 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$libresoc.v:26344$946_Y + end + attribute \src "libresoc.v:26303.7-26303.20" + process $proc$libresoc.v:26303$952 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:26327.7-26327.19" + process $proc$libresoc.v:26327$953 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:26346.3-26347.27" + process $proc$libresoc.v:26346$948 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:26348.3-26356.6" + process $proc$libresoc.v:26348$949 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$950 $1\q_int$next[0:0]$951 + attribute \src "libresoc.v:26349.5-26349.29" + switch \initial + attribute \src "libresoc.v:26349.9-26349.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$951 1'0 + case + assign $1\q_int$next[0:0]$951 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$950 + end + connect \$9 $and$libresoc.v:26338$940_Y + connect \$11 $or$libresoc.v:26339$941_Y + connect \$13 $not$libresoc.v:26340$942_Y + connect \$15 $or$libresoc.v:26341$943_Y + connect \$1 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\enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute 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\enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 6 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 21 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \logical_pipe1_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \logical_pipe1_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_pipe1_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_pipe1_logical_op__data_len$18 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_pipe1_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_pipe1_logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_pipe1_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_pipe1_logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_pipe1_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_pipe1_logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_pipe1_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_pipe1_logical_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_pipe1_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_pipe1_logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire 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attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_pipe2_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_pipe2_logical_op__fn_unit$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_pipe2_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_pipe2_logical_op__imm_data__data$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__imm_data__ok$25 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_pipe2_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_pipe2_logical_op__input_carry$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_pipe2_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_pipe2_logical_op__insn$39 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_pipe2_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_pipe2_logical_op__insn_type$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__invert_in$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__invert_out$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__is_32bit$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__is_signed$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__oe__oe$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__oe__ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__output_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__rc__ok$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__rc__rc$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__write_cr0$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__zero_a$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \logical_pipe2_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \logical_pipe2_muxid$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \logical_pipe2_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \logical_pipe2_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \logical_pipe2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \logical_pipe2_o$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \logical_pipe2_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \logical_pipe2_o_ok$41 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \logical_pipe2_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \logical_pipe2_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \logical_pipe2_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \logical_pipe2_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$44 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 5 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 4 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 24 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 30 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 29 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 26 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 27 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 28 \xer_so + attribute \module_not_derived 1 + attribute \src "libresoc.v:27343.17-27397.4" + cell \logical_pipe1 \logical_pipe1 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \logical_pipe1_cr_a + connect \cr_a_ok \logical_pipe1_cr_a_ok + connect \logical_op__data_len \logical_pipe1_logical_op__data_len + connect \logical_op__data_len$18 \logical_pipe1_logical_op__data_len$18 + connect \logical_op__fn_unit \logical_pipe1_logical_op__fn_unit + connect \logical_op__fn_unit$3 \logical_pipe1_logical_op__fn_unit$3 + connect \logical_op__imm_data__data \logical_pipe1_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \logical_pipe1_logical_op__imm_data__data$4 + connect \logical_op__imm_data__ok \logical_pipe1_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \logical_pipe1_logical_op__imm_data__ok$5 + connect \logical_op__input_carry \logical_pipe1_logical_op__input_carry + connect \logical_op__input_carry$12 \logical_pipe1_logical_op__input_carry$12 + connect \logical_op__insn \logical_pipe1_logical_op__insn + connect \logical_op__insn$19 \logical_pipe1_logical_op__insn$19 + connect \logical_op__insn_type \logical_pipe1_logical_op__insn_type + connect \logical_op__insn_type$2 \logical_pipe1_logical_op__insn_type$2 + connect \logical_op__invert_in \logical_pipe1_logical_op__invert_in + connect \logical_op__invert_in$10 \logical_pipe1_logical_op__invert_in$10 + connect \logical_op__invert_out \logical_pipe1_logical_op__invert_out + connect \logical_op__invert_out$13 \logical_pipe1_logical_op__invert_out$13 + connect \logical_op__is_32bit \logical_pipe1_logical_op__is_32bit + connect \logical_op__is_32bit$16 \logical_pipe1_logical_op__is_32bit$16 + connect \logical_op__is_signed \logical_pipe1_logical_op__is_signed + connect \logical_op__is_signed$17 \logical_pipe1_logical_op__is_signed$17 + connect \logical_op__oe__oe \logical_pipe1_logical_op__oe__oe + connect \logical_op__oe__oe$8 \logical_pipe1_logical_op__oe__oe$8 + connect \logical_op__oe__ok \logical_pipe1_logical_op__oe__ok + connect \logical_op__oe__ok$9 \logical_pipe1_logical_op__oe__ok$9 + connect \logical_op__output_carry \logical_pipe1_logical_op__output_carry + connect \logical_op__output_carry$15 \logical_pipe1_logical_op__output_carry$15 + connect \logical_op__rc__ok \logical_pipe1_logical_op__rc__ok + connect \logical_op__rc__ok$7 \logical_pipe1_logical_op__rc__ok$7 + connect \logical_op__rc__rc \logical_pipe1_logical_op__rc__rc + connect \logical_op__rc__rc$6 \logical_pipe1_logical_op__rc__rc$6 + connect \logical_op__write_cr0 \logical_pipe1_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \logical_pipe1_logical_op__write_cr0$14 + connect \logical_op__zero_a \logical_pipe1_logical_op__zero_a + connect \logical_op__zero_a$11 \logical_pipe1_logical_op__zero_a$11 + connect \muxid \logical_pipe1_muxid + connect \muxid$1 \logical_pipe1_muxid$1 + connect \n_ready_i \logical_pipe1_n_ready_i + connect \n_valid_o \logical_pipe1_n_valid_o + connect \o \logical_pipe1_o + connect \o_ok \logical_pipe1_o_ok + connect \p_ready_o \logical_pipe1_p_ready_o + connect \p_valid_i \logical_pipe1_p_valid_i + connect \ra \logical_pipe1_ra + connect \rb \logical_pipe1_rb + connect \xer_so \logical_pipe1_xer_so + connect \xer_so$20 \logical_pipe1_xer_so$20 + connect \xer_so_ok \logical_pipe1_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:27398.17-27453.4" + cell \logical_pipe2 \logical_pipe2 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \logical_pipe2_cr_a + connect \cr_a$22 \logical_pipe2_cr_a$42 + connect \cr_a_ok \logical_pipe2_cr_a_ok + connect \cr_a_ok$23 \logical_pipe2_cr_a_ok$43 + connect \logical_op__data_len \logical_pipe2_logical_op__data_len + connect \logical_op__data_len$18 \logical_pipe2_logical_op__data_len$38 + connect \logical_op__fn_unit \logical_pipe2_logical_op__fn_unit + connect \logical_op__fn_unit$3 \logical_pipe2_logical_op__fn_unit$23 + connect \logical_op__imm_data__data \logical_pipe2_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \logical_pipe2_logical_op__imm_data__data$24 + connect \logical_op__imm_data__ok \logical_pipe2_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \logical_pipe2_logical_op__imm_data__ok$25 + connect \logical_op__input_carry \logical_pipe2_logical_op__input_carry + connect \logical_op__input_carry$12 \logical_pipe2_logical_op__input_carry$32 + connect \logical_op__insn \logical_pipe2_logical_op__insn + connect \logical_op__insn$19 \logical_pipe2_logical_op__insn$39 + connect \logical_op__insn_type \logical_pipe2_logical_op__insn_type + connect \logical_op__insn_type$2 \logical_pipe2_logical_op__insn_type$22 + connect \logical_op__invert_in \logical_pipe2_logical_op__invert_in + connect \logical_op__invert_in$10 \logical_pipe2_logical_op__invert_in$30 + connect \logical_op__invert_out \logical_pipe2_logical_op__invert_out + connect \logical_op__invert_out$13 \logical_pipe2_logical_op__invert_out$33 + connect \logical_op__is_32bit \logical_pipe2_logical_op__is_32bit + connect \logical_op__is_32bit$16 \logical_pipe2_logical_op__is_32bit$36 + connect \logical_op__is_signed \logical_pipe2_logical_op__is_signed + connect \logical_op__is_signed$17 \logical_pipe2_logical_op__is_signed$37 + connect \logical_op__oe__oe \logical_pipe2_logical_op__oe__oe + connect \logical_op__oe__oe$8 \logical_pipe2_logical_op__oe__oe$28 + connect \logical_op__oe__ok \logical_pipe2_logical_op__oe__ok + connect \logical_op__oe__ok$9 \logical_pipe2_logical_op__oe__ok$29 + connect \logical_op__output_carry \logical_pipe2_logical_op__output_carry + connect \logical_op__output_carry$15 \logical_pipe2_logical_op__output_carry$35 + connect \logical_op__rc__ok \logical_pipe2_logical_op__rc__ok + connect \logical_op__rc__ok$7 \logical_pipe2_logical_op__rc__ok$27 + connect \logical_op__rc__rc \logical_pipe2_logical_op__rc__rc + connect \logical_op__rc__rc$6 \logical_pipe2_logical_op__rc__rc$26 + connect \logical_op__write_cr0 \logical_pipe2_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \logical_pipe2_logical_op__write_cr0$34 + connect \logical_op__zero_a \logical_pipe2_logical_op__zero_a + connect \logical_op__zero_a$11 \logical_pipe2_logical_op__zero_a$31 + connect \muxid \logical_pipe2_muxid + connect \muxid$1 \logical_pipe2_muxid$21 + connect \n_ready_i \logical_pipe2_n_ready_i + connect \n_valid_o \logical_pipe2_n_valid_o + connect \o \logical_pipe2_o + connect \o$20 \logical_pipe2_o$40 + connect \o_ok \logical_pipe2_o_ok + connect \o_ok$21 \logical_pipe2_o_ok$41 + connect \p_ready_o \logical_pipe2_p_ready_o + connect \p_valid_i \logical_pipe2_p_valid_i + connect \xer_so \logical_pipe2_xer_so + connect \xer_so_ok \logical_pipe2_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:27454.10-27457.4" + cell \n$47 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:27458.10-27461.4" + cell \p$46 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + connect \muxid 2'00 + connect { \cr_a_ok \cr_a } { \logical_pipe2_cr_a_ok$43 \logical_pipe2_cr_a$42 } + connect { \o_ok \o } { \logical_pipe2_o_ok$41 \logical_pipe2_o$40 } + connect { \logical_op__insn$62 \logical_op__data_len$61 \logical_op__is_signed$60 \logical_op__is_32bit$59 \logical_op__output_carry$58 \logical_op__write_cr0$57 \logical_op__invert_out$56 \logical_op__input_carry$55 \logical_op__zero_a$54 \logical_op__invert_in$53 \logical_op__oe__ok$52 \logical_op__oe__oe$51 \logical_op__rc__ok$50 \logical_op__rc__rc$49 \logical_op__imm_data__ok$48 \logical_op__imm_data__data$47 \logical_op__fn_unit$46 \logical_op__insn_type$45 } { \logical_pipe2_logical_op__insn$39 \logical_pipe2_logical_op__data_len$38 \logical_pipe2_logical_op__is_signed$37 \logical_pipe2_logical_op__is_32bit$36 \logical_pipe2_logical_op__output_carry$35 \logical_pipe2_logical_op__write_cr0$34 \logical_pipe2_logical_op__invert_out$33 \logical_pipe2_logical_op__input_carry$32 \logical_pipe2_logical_op__zero_a$31 \logical_pipe2_logical_op__invert_in$30 \logical_pipe2_logical_op__oe__ok$29 \logical_pipe2_logical_op__oe__oe$28 \logical_pipe2_logical_op__rc__ok$27 \logical_pipe2_logical_op__rc__rc$26 \logical_pipe2_logical_op__imm_data__ok$25 \logical_pipe2_logical_op__imm_data__data$24 \logical_pipe2_logical_op__fn_unit$23 \logical_pipe2_logical_op__insn_type$22 } + connect \muxid$44 \logical_pipe2_muxid$21 + connect \logical_pipe2_n_ready_i \n_ready_i + connect \n_valid_o \logical_pipe2_n_valid_o + connect \logical_pipe1_xer_so$20 \xer_so + connect \logical_pipe1_rb \rb + connect \logical_pipe1_ra \ra + connect { \logical_pipe1_logical_op__insn$19 \logical_pipe1_logical_op__data_len$18 \logical_pipe1_logical_op__is_signed$17 \logical_pipe1_logical_op__is_32bit$16 \logical_pipe1_logical_op__output_carry$15 \logical_pipe1_logical_op__write_cr0$14 \logical_pipe1_logical_op__invert_out$13 \logical_pipe1_logical_op__input_carry$12 \logical_pipe1_logical_op__zero_a$11 \logical_pipe1_logical_op__invert_in$10 \logical_pipe1_logical_op__oe__ok$9 \logical_pipe1_logical_op__oe__oe$8 \logical_pipe1_logical_op__rc__ok$7 \logical_pipe1_logical_op__rc__rc$6 \logical_pipe1_logical_op__imm_data__ok$5 \logical_pipe1_logical_op__imm_data__data$4 \logical_pipe1_logical_op__fn_unit$3 \logical_pipe1_logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \logical_pipe1_muxid$1 2'00 + connect \p_ready_o \logical_pipe1_p_ready_o + connect \logical_pipe1_p_valid_i \p_valid_i + connect { \logical_pipe2_xer_so_ok \logical_pipe2_xer_so } { \logical_pipe1_xer_so_ok \logical_pipe1_xer_so } + connect { \logical_pipe2_cr_a_ok \logical_pipe2_cr_a } { \logical_pipe1_cr_a_ok \logical_pipe1_cr_a } + connect { \logical_pipe2_o_ok \logical_pipe2_o } { \logical_pipe1_o_ok \logical_pipe1_o } + connect { \logical_pipe2_logical_op__insn \logical_pipe2_logical_op__data_len \logical_pipe2_logical_op__is_signed \logical_pipe2_logical_op__is_32bit \logical_pipe2_logical_op__output_carry \logical_pipe2_logical_op__write_cr0 \logical_pipe2_logical_op__invert_out \logical_pipe2_logical_op__input_carry \logical_pipe2_logical_op__zero_a \logical_pipe2_logical_op__invert_in \logical_pipe2_logical_op__oe__ok \logical_pipe2_logical_op__oe__oe \logical_pipe2_logical_op__rc__ok \logical_pipe2_logical_op__rc__rc \logical_pipe2_logical_op__imm_data__ok \logical_pipe2_logical_op__imm_data__data \logical_pipe2_logical_op__fn_unit \logical_pipe2_logical_op__insn_type } { \logical_pipe1_logical_op__insn \logical_pipe1_logical_op__data_len \logical_pipe1_logical_op__is_signed \logical_pipe1_logical_op__is_32bit \logical_pipe1_logical_op__output_carry \logical_pipe1_logical_op__write_cr0 \logical_pipe1_logical_op__invert_out \logical_pipe1_logical_op__input_carry \logical_pipe1_logical_op__zero_a \logical_pipe1_logical_op__invert_in \logical_pipe1_logical_op__oe__ok \logical_pipe1_logical_op__oe__oe \logical_pipe1_logical_op__rc__ok \logical_pipe1_logical_op__rc__rc \logical_pipe1_logical_op__imm_data__ok \logical_pipe1_logical_op__imm_data__data \logical_pipe1_logical_op__fn_unit \logical_pipe1_logical_op__insn_type } + connect \logical_pipe2_muxid \logical_pipe1_muxid + connect \logical_pipe1_n_ready_i \logical_pipe2_p_ready_o + connect \logical_pipe2_p_valid_i \logical_pipe1_n_valid_o +end +attribute \src "libresoc.v:27487.1-28680.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0" +attribute \generator "nMigen" +module \alu_mul0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 29 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 21 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \cr_a_ok + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 9 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_op__fn_unit$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 10 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__data$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 19 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$61 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 8 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_32bit$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_signed$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__oe$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__ok$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$58 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_pipe1_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_pipe1_mul_op__fn_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_pipe1_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_pipe1_mul_op__imm_data__data$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__imm_data__ok$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_pipe1_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_pipe1_mul_op__insn$14 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_pipe1_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_pipe1_mul_op__insn_type$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__is_32bit$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__is_signed$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__oe__ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__rc__ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__write_cr0$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul_pipe1_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul_pipe1_muxid$2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \mul_pipe1_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \mul_pipe1_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire \mul_pipe1_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire \mul_pipe1_neg_res32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \mul_pipe1_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \mul_pipe1_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul_pipe1_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul_pipe1_ra$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul_pipe1_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul_pipe1_rb$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul_pipe1_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul_pipe1_xer_so$17 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_pipe2_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_pipe2_mul_op__fn_unit$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_pipe2_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_pipe2_mul_op__imm_data__data$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__imm_data__ok$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_pipe2_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_pipe2_mul_op__insn$30 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_pipe2_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_pipe2_mul_op__insn_type$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__is_32bit$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__is_signed$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__oe__oe$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__oe__ok$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__rc__ok$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__rc__rc$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__write_cr0$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul_pipe2_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul_pipe2_muxid$18 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \mul_pipe2_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \mul_pipe2_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire \mul_pipe2_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire \mul_pipe2_neg_res$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire \mul_pipe2_neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire \mul_pipe2_neg_res32$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \mul_pipe2_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \mul_pipe2_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \mul_pipe2_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul_pipe2_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul_pipe2_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul_pipe2_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul_pipe2_xer_so$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \mul_pipe3_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \mul_pipe3_cr_a_ok + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_pipe3_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_pipe3_mul_op__fn_unit$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_pipe3_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_pipe3_mul_op__imm_data__data$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__imm_data__ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_pipe3_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_pipe3_mul_op__insn$46 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_pipe3_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_pipe3_mul_op__insn_type$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__is_32bit$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__is_signed$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__oe__oe$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__oe__ok$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__rc__ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__rc__rc$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__write_cr0$43 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul_pipe3_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul_pipe3_muxid$34 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \mul_pipe3_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \mul_pipe3_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire \mul_pipe3_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire \mul_pipe3_neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \mul_pipe3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \mul_pipe3_o$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \mul_pipe3_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \mul_pipe3_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \mul_pipe3_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \mul_pipe3_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \mul_pipe3_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul_pipe3_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \mul_pipe3_xer_so$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \mul_pipe3_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$49 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 7 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 6 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 20 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 28 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 27 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 25 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 22 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 26 \xer_so$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 5 \xer_so_ok + attribute \module_not_derived 1 + attribute \src "libresoc.v:28508.13-28549.4" + cell \mul_pipe1 \mul_pipe1 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \mul_op__fn_unit \mul_pipe1_mul_op__fn_unit + connect \mul_op__fn_unit$3 \mul_pipe1_mul_op__fn_unit$4 + connect \mul_op__imm_data__data \mul_pipe1_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \mul_pipe1_mul_op__imm_data__data$5 + connect \mul_op__imm_data__ok \mul_pipe1_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \mul_pipe1_mul_op__imm_data__ok$6 + connect \mul_op__insn \mul_pipe1_mul_op__insn + connect \mul_op__insn$13 \mul_pipe1_mul_op__insn$14 + connect \mul_op__insn_type \mul_pipe1_mul_op__insn_type + connect \mul_op__insn_type$2 \mul_pipe1_mul_op__insn_type$3 + connect \mul_op__is_32bit \mul_pipe1_mul_op__is_32bit + connect \mul_op__is_32bit$11 \mul_pipe1_mul_op__is_32bit$12 + connect \mul_op__is_signed \mul_pipe1_mul_op__is_signed + connect \mul_op__is_signed$12 \mul_pipe1_mul_op__is_signed$13 + connect \mul_op__oe__oe \mul_pipe1_mul_op__oe__oe + connect \mul_op__oe__oe$8 \mul_pipe1_mul_op__oe__oe$9 + connect \mul_op__oe__ok \mul_pipe1_mul_op__oe__ok + connect \mul_op__oe__ok$9 \mul_pipe1_mul_op__oe__ok$10 + connect \mul_op__rc__ok \mul_pipe1_mul_op__rc__ok + connect \mul_op__rc__ok$7 \mul_pipe1_mul_op__rc__ok$8 + connect \mul_op__rc__rc \mul_pipe1_mul_op__rc__rc + connect \mul_op__rc__rc$6 \mul_pipe1_mul_op__rc__rc$7 + connect \mul_op__write_cr0 \mul_pipe1_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \mul_pipe1_mul_op__write_cr0$11 + connect \muxid \mul_pipe1_muxid + connect \muxid$1 \mul_pipe1_muxid$2 + connect \n_ready_i \mul_pipe1_n_ready_i + connect \n_valid_o \mul_pipe1_n_valid_o + connect \neg_res \mul_pipe1_neg_res + connect \neg_res32 \mul_pipe1_neg_res32 + connect \p_ready_o \mul_pipe1_p_ready_o + connect \p_valid_i \mul_pipe1_p_valid_i + connect \ra \mul_pipe1_ra + connect \ra$14 \mul_pipe1_ra$15 + connect \rb \mul_pipe1_rb + connect \rb$15 \mul_pipe1_rb$16 + connect \xer_so \mul_pipe1_xer_so + connect \xer_so$16 \mul_pipe1_xer_so$17 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:28550.13-28592.4" + cell \mul_pipe2 \mul_pipe2 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \mul_op__fn_unit \mul_pipe2_mul_op__fn_unit + connect \mul_op__fn_unit$3 \mul_pipe2_mul_op__fn_unit$20 + connect \mul_op__imm_data__data \mul_pipe2_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \mul_pipe2_mul_op__imm_data__data$21 + connect \mul_op__imm_data__ok \mul_pipe2_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \mul_pipe2_mul_op__imm_data__ok$22 + connect \mul_op__insn \mul_pipe2_mul_op__insn + connect \mul_op__insn$13 \mul_pipe2_mul_op__insn$30 + connect \mul_op__insn_type \mul_pipe2_mul_op__insn_type + connect \mul_op__insn_type$2 \mul_pipe2_mul_op__insn_type$19 + connect \mul_op__is_32bit \mul_pipe2_mul_op__is_32bit + connect \mul_op__is_32bit$11 \mul_pipe2_mul_op__is_32bit$28 + connect \mul_op__is_signed \mul_pipe2_mul_op__is_signed + connect \mul_op__is_signed$12 \mul_pipe2_mul_op__is_signed$29 + connect \mul_op__oe__oe \mul_pipe2_mul_op__oe__oe + connect \mul_op__oe__oe$8 \mul_pipe2_mul_op__oe__oe$25 + connect \mul_op__oe__ok \mul_pipe2_mul_op__oe__ok + connect \mul_op__oe__ok$9 \mul_pipe2_mul_op__oe__ok$26 + connect \mul_op__rc__ok \mul_pipe2_mul_op__rc__ok + connect \mul_op__rc__ok$7 \mul_pipe2_mul_op__rc__ok$24 + connect \mul_op__rc__rc \mul_pipe2_mul_op__rc__rc + connect \mul_op__rc__rc$6 \mul_pipe2_mul_op__rc__rc$23 + connect \mul_op__write_cr0 \mul_pipe2_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \mul_pipe2_mul_op__write_cr0$27 + connect \muxid \mul_pipe2_muxid + connect \muxid$1 \mul_pipe2_muxid$18 + connect \n_ready_i \mul_pipe2_n_ready_i + connect \n_valid_o \mul_pipe2_n_valid_o + connect \neg_res \mul_pipe2_neg_res + connect \neg_res$15 \mul_pipe2_neg_res$32 + connect \neg_res32 \mul_pipe2_neg_res32 + connect \neg_res32$16 \mul_pipe2_neg_res32$33 + connect \o \mul_pipe2_o + connect \p_ready_o \mul_pipe2_p_ready_o + connect \p_valid_i \mul_pipe2_p_valid_i + connect \ra \mul_pipe2_ra + connect \rb \mul_pipe2_rb + connect \xer_so \mul_pipe2_xer_so + connect \xer_so$14 \mul_pipe2_xer_so$31 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:28593.13-28638.4" + cell \mul_pipe3 \mul_pipe3 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \mul_pipe3_cr_a + connect \cr_a_ok \mul_pipe3_cr_a_ok + connect \mul_op__fn_unit \mul_pipe3_mul_op__fn_unit + connect \mul_op__fn_unit$3 \mul_pipe3_mul_op__fn_unit$36 + connect \mul_op__imm_data__data \mul_pipe3_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \mul_pipe3_mul_op__imm_data__data$37 + connect \mul_op__imm_data__ok \mul_pipe3_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \mul_pipe3_mul_op__imm_data__ok$38 + connect \mul_op__insn \mul_pipe3_mul_op__insn + connect \mul_op__insn$13 \mul_pipe3_mul_op__insn$46 + connect \mul_op__insn_type \mul_pipe3_mul_op__insn_type + connect \mul_op__insn_type$2 \mul_pipe3_mul_op__insn_type$35 + connect \mul_op__is_32bit \mul_pipe3_mul_op__is_32bit + connect \mul_op__is_32bit$11 \mul_pipe3_mul_op__is_32bit$44 + connect \mul_op__is_signed \mul_pipe3_mul_op__is_signed + connect \mul_op__is_signed$12 \mul_pipe3_mul_op__is_signed$45 + connect \mul_op__oe__oe \mul_pipe3_mul_op__oe__oe + connect \mul_op__oe__oe$8 \mul_pipe3_mul_op__oe__oe$41 + connect \mul_op__oe__ok \mul_pipe3_mul_op__oe__ok + connect \mul_op__oe__ok$9 \mul_pipe3_mul_op__oe__ok$42 + connect \mul_op__rc__ok \mul_pipe3_mul_op__rc__ok + connect \mul_op__rc__ok$7 \mul_pipe3_mul_op__rc__ok$40 + connect \mul_op__rc__rc \mul_pipe3_mul_op__rc__rc + connect \mul_op__rc__rc$6 \mul_pipe3_mul_op__rc__rc$39 + connect \mul_op__write_cr0 \mul_pipe3_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \mul_pipe3_mul_op__write_cr0$43 + connect \muxid \mul_pipe3_muxid + connect \muxid$1 \mul_pipe3_muxid$34 + connect \n_ready_i \mul_pipe3_n_ready_i + connect \n_valid_o \mul_pipe3_n_valid_o + connect \neg_res \mul_pipe3_neg_res + connect \neg_res32 \mul_pipe3_neg_res32 + connect \o \mul_pipe3_o + connect \o$14 \mul_pipe3_o$47 + connect \o_ok \mul_pipe3_o_ok + connect \p_ready_o \mul_pipe3_p_ready_o + connect \p_valid_i \mul_pipe3_p_valid_i + connect \xer_ov \mul_pipe3_xer_ov + connect \xer_ov_ok \mul_pipe3_xer_ov_ok + connect \xer_so \mul_pipe3_xer_so + connect \xer_so$15 \mul_pipe3_xer_so$48 + connect \xer_so_ok \mul_pipe3_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:28639.10-28642.4" + cell \n$92 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:28643.10-28646.4" + cell \p$91 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + connect \muxid 2'00 + connect { \xer_so_ok \xer_so } { \mul_pipe3_xer_so_ok \mul_pipe3_xer_so$48 } + connect { \xer_ov_ok \xer_ov } { \mul_pipe3_xer_ov_ok \mul_pipe3_xer_ov } + connect { \cr_a_ok \cr_a } { \mul_pipe3_cr_a_ok \mul_pipe3_cr_a } + connect { \o_ok \o } { \mul_pipe3_o_ok \mul_pipe3_o$47 } + connect { \mul_op__insn$61 \mul_op__is_signed$60 \mul_op__is_32bit$59 \mul_op__write_cr0$58 \mul_op__oe__ok$57 \mul_op__oe__oe$56 \mul_op__rc__ok$55 \mul_op__rc__rc$54 \mul_op__imm_data__ok$53 \mul_op__imm_data__data$52 \mul_op__fn_unit$51 \mul_op__insn_type$50 } { \mul_pipe3_mul_op__insn$46 \mul_pipe3_mul_op__is_signed$45 \mul_pipe3_mul_op__is_32bit$44 \mul_pipe3_mul_op__write_cr0$43 \mul_pipe3_mul_op__oe__ok$42 \mul_pipe3_mul_op__oe__oe$41 \mul_pipe3_mul_op__rc__ok$40 \mul_pipe3_mul_op__rc__rc$39 \mul_pipe3_mul_op__imm_data__ok$38 \mul_pipe3_mul_op__imm_data__data$37 \mul_pipe3_mul_op__fn_unit$36 \mul_pipe3_mul_op__insn_type$35 } + connect \muxid$49 \mul_pipe3_muxid$34 + connect \mul_pipe3_n_ready_i \n_ready_i + connect \n_valid_o \mul_pipe3_n_valid_o + connect \mul_pipe1_xer_so$17 \xer_so$1 + connect \mul_pipe1_rb$16 \rb + connect \mul_pipe1_ra$15 \ra + connect { \mul_pipe1_mul_op__insn$14 \mul_pipe1_mul_op__is_signed$13 \mul_pipe1_mul_op__is_32bit$12 \mul_pipe1_mul_op__write_cr0$11 \mul_pipe1_mul_op__oe__ok$10 \mul_pipe1_mul_op__oe__oe$9 \mul_pipe1_mul_op__rc__ok$8 \mul_pipe1_mul_op__rc__rc$7 \mul_pipe1_mul_op__imm_data__ok$6 \mul_pipe1_mul_op__imm_data__data$5 \mul_pipe1_mul_op__fn_unit$4 \mul_pipe1_mul_op__insn_type$3 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \mul_pipe1_muxid$2 2'00 + connect \p_ready_o \mul_pipe1_p_ready_o + connect \mul_pipe1_p_valid_i \p_valid_i + connect \mul_pipe3_neg_res32 \mul_pipe2_neg_res32$33 + connect \mul_pipe3_neg_res \mul_pipe2_neg_res$32 + connect \mul_pipe3_xer_so \mul_pipe2_xer_so$31 + connect \mul_pipe3_o \mul_pipe2_o + connect { \mul_pipe3_mul_op__insn \mul_pipe3_mul_op__is_signed \mul_pipe3_mul_op__is_32bit \mul_pipe3_mul_op__write_cr0 \mul_pipe3_mul_op__oe__ok \mul_pipe3_mul_op__oe__oe \mul_pipe3_mul_op__rc__ok \mul_pipe3_mul_op__rc__rc \mul_pipe3_mul_op__imm_data__ok \mul_pipe3_mul_op__imm_data__data \mul_pipe3_mul_op__fn_unit \mul_pipe3_mul_op__insn_type } { \mul_pipe2_mul_op__insn$30 \mul_pipe2_mul_op__is_signed$29 \mul_pipe2_mul_op__is_32bit$28 \mul_pipe2_mul_op__write_cr0$27 \mul_pipe2_mul_op__oe__ok$26 \mul_pipe2_mul_op__oe__oe$25 \mul_pipe2_mul_op__rc__ok$24 \mul_pipe2_mul_op__rc__rc$23 \mul_pipe2_mul_op__imm_data__ok$22 \mul_pipe2_mul_op__imm_data__data$21 \mul_pipe2_mul_op__fn_unit$20 \mul_pipe2_mul_op__insn_type$19 } + connect \mul_pipe3_muxid \mul_pipe2_muxid$18 + connect \mul_pipe2_n_ready_i \mul_pipe3_p_ready_o + connect \mul_pipe3_p_valid_i \mul_pipe2_n_valid_o + connect \mul_pipe2_neg_res32 \mul_pipe1_neg_res32 + connect \mul_pipe2_neg_res \mul_pipe1_neg_res + connect \mul_pipe2_xer_so \mul_pipe1_xer_so + connect \mul_pipe2_rb \mul_pipe1_rb + connect \mul_pipe2_ra \mul_pipe1_ra + connect { \mul_pipe2_mul_op__insn \mul_pipe2_mul_op__is_signed \mul_pipe2_mul_op__is_32bit \mul_pipe2_mul_op__write_cr0 \mul_pipe2_mul_op__oe__ok \mul_pipe2_mul_op__oe__oe \mul_pipe2_mul_op__rc__ok \mul_pipe2_mul_op__rc__rc \mul_pipe2_mul_op__imm_data__ok \mul_pipe2_mul_op__imm_data__data \mul_pipe2_mul_op__fn_unit \mul_pipe2_mul_op__insn_type } { \mul_pipe1_mul_op__insn \mul_pipe1_mul_op__is_signed \mul_pipe1_mul_op__is_32bit \mul_pipe1_mul_op__write_cr0 \mul_pipe1_mul_op__oe__ok \mul_pipe1_mul_op__oe__oe \mul_pipe1_mul_op__rc__ok \mul_pipe1_mul_op__rc__rc \mul_pipe1_mul_op__imm_data__ok \mul_pipe1_mul_op__imm_data__data \mul_pipe1_mul_op__fn_unit \mul_pipe1_mul_op__insn_type } + connect \mul_pipe2_muxid \mul_pipe1_muxid + connect \mul_pipe1_n_ready_i \mul_pipe2_p_ready_o + connect \mul_pipe2_p_valid_i \mul_pipe1_n_valid_o +end +attribute \src "libresoc.v:28684.1-29699.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0" +attribute \generator "nMigen" +module \alu_shift_rot0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 34 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 25 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$46 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 6 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 5 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 24 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 33 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 32 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \pipe1_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe1_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe1_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe1_muxid$2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \pipe1_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \pipe1_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe1_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \pipe1_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \pipe1_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_rc + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe1_sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe1_sr_op__fn_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe1_sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe1_sr_op__imm_data__data$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__imm_data__ok$6 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe1_sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe1_sr_op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__input_cr$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe1_sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe1_sr_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute 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attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__invert_in$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__is_32bit$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__is_signed$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__oe__ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__output_carry$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__output_cr$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__rc__ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__write_cr0$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \pipe1_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \pipe1_xer_ca$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe1_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe1_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe1_xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe1_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \pipe2_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \pipe2_cr_a$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_cr_a_ok$43 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe2_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe2_muxid$22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \pipe2_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \pipe2_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe2_o$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_o_ok$41 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \pipe2_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \pipe2_p_valid_i + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe2_sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe2_sr_op__fn_unit$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_sr_op__imm_data__data + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__input_cr$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe2_sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe2_sr_op__insn$39 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe2_sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe2_sr_op__insn_type$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__invert_in$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__is_32bit$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__is_signed$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__oe__oe$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__oe__ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__output_carry$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__output_cr$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__rc__ok$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__rc__rc$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__write_cr0$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \pipe2_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \pipe2_xer_ca$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_xer_ca_ok$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 27 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 28 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 29 \rc + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 8 \sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \sr_op__fn_unit$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 9 \sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__data$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__imm_data__ok$50 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 17 \sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \sr_op__input_carry$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__input_cr$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 23 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$63 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 7 \sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \sr_op__insn_type$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \sr_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__invert_in$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 21 \sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_32bit$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 22 \sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_signed$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__oe$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__ok$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_carry$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_cr$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__ok$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__rc$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__write_cr0$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 26 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 31 \xer_ca$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 30 \xer_so + attribute \module_not_derived 1 + attribute \src "libresoc.v:29551.11-29554.4" + cell \n$109 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:29555.11-29558.4" + cell \p$108 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:29559.15-29615.4" + cell \pipe1$110 \pipe1 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \pipe1_cr_a + connect \cr_a_ok \pipe1_cr_a_ok + connect \muxid \pipe1_muxid + connect \muxid$1 \pipe1_muxid$2 + connect \n_ready_i \pipe1_n_ready_i + connect \n_valid_o \pipe1_n_valid_o + connect \o \pipe1_o + connect \o_ok \pipe1_o_ok + connect \p_ready_o \pipe1_p_ready_o + connect \p_valid_i \pipe1_p_valid_i + connect \ra \pipe1_ra + connect \rb \pipe1_rb + connect \rc \pipe1_rc + connect \sr_op__fn_unit \pipe1_sr_op__fn_unit + connect \sr_op__fn_unit$3 \pipe1_sr_op__fn_unit$4 + connect \sr_op__imm_data__data \pipe1_sr_op__imm_data__data + connect \sr_op__imm_data__data$4 \pipe1_sr_op__imm_data__data$5 + connect \sr_op__imm_data__ok \pipe1_sr_op__imm_data__ok + connect \sr_op__imm_data__ok$5 \pipe1_sr_op__imm_data__ok$6 + connect \sr_op__input_carry \pipe1_sr_op__input_carry + connect \sr_op__input_carry$12 \pipe1_sr_op__input_carry$13 + connect \sr_op__input_cr \pipe1_sr_op__input_cr + connect \sr_op__input_cr$14 \pipe1_sr_op__input_cr$15 + connect \sr_op__insn \pipe1_sr_op__insn + connect \sr_op__insn$18 \pipe1_sr_op__insn$19 + connect \sr_op__insn_type \pipe1_sr_op__insn_type + connect \sr_op__insn_type$2 \pipe1_sr_op__insn_type$3 + connect \sr_op__invert_in \pipe1_sr_op__invert_in + connect \sr_op__invert_in$11 \pipe1_sr_op__invert_in$12 + connect \sr_op__is_32bit \pipe1_sr_op__is_32bit + connect \sr_op__is_32bit$16 \pipe1_sr_op__is_32bit$17 + connect \sr_op__is_signed \pipe1_sr_op__is_signed + connect \sr_op__is_signed$17 \pipe1_sr_op__is_signed$18 + connect \sr_op__oe__oe \pipe1_sr_op__oe__oe + connect \sr_op__oe__oe$8 \pipe1_sr_op__oe__oe$9 + connect \sr_op__oe__ok \pipe1_sr_op__oe__ok + connect \sr_op__oe__ok$9 \pipe1_sr_op__oe__ok$10 + connect \sr_op__output_carry \pipe1_sr_op__output_carry + connect \sr_op__output_carry$13 \pipe1_sr_op__output_carry$14 + connect \sr_op__output_cr \pipe1_sr_op__output_cr + connect \sr_op__output_cr$15 \pipe1_sr_op__output_cr$16 + connect \sr_op__rc__ok \pipe1_sr_op__rc__ok + connect \sr_op__rc__ok$7 \pipe1_sr_op__rc__ok$8 + connect \sr_op__rc__rc \pipe1_sr_op__rc__rc + connect \sr_op__rc__rc$6 \pipe1_sr_op__rc__rc$7 + connect \sr_op__write_cr0 \pipe1_sr_op__write_cr0 + connect \sr_op__write_cr0$10 \pipe1_sr_op__write_cr0$11 + connect \xer_ca \pipe1_xer_ca + connect \xer_ca$20 \pipe1_xer_ca$21 + connect \xer_ca_ok \pipe1_xer_ca_ok + connect \xer_so \pipe1_xer_so + connect \xer_so$19 \pipe1_xer_so$20 + connect \xer_so_ok \pipe1_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:29616.15-29673.4" + cell \pipe2$115 \pipe2 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \pipe2_cr_a + connect \cr_a$21 \pipe2_cr_a$42 + connect \cr_a_ok \pipe2_cr_a_ok + connect \cr_a_ok$22 \pipe2_cr_a_ok$43 + connect \muxid \pipe2_muxid + connect \muxid$1 \pipe2_muxid$22 + connect \n_ready_i \pipe2_n_ready_i + connect \n_valid_o \pipe2_n_valid_o + connect \o \pipe2_o + connect \o$19 \pipe2_o$40 + connect \o_ok \pipe2_o_ok + connect \o_ok$20 \pipe2_o_ok$41 + connect \p_ready_o \pipe2_p_ready_o + connect \p_valid_i \pipe2_p_valid_i + connect \sr_op__fn_unit \pipe2_sr_op__fn_unit + connect \sr_op__fn_unit$3 \pipe2_sr_op__fn_unit$24 + connect \sr_op__imm_data__data \pipe2_sr_op__imm_data__data + connect \sr_op__imm_data__data$4 \pipe2_sr_op__imm_data__data$25 + connect \sr_op__imm_data__ok \pipe2_sr_op__imm_data__ok + connect \sr_op__imm_data__ok$5 \pipe2_sr_op__imm_data__ok$26 + connect \sr_op__input_carry \pipe2_sr_op__input_carry + connect \sr_op__input_carry$12 \pipe2_sr_op__input_carry$33 + connect \sr_op__input_cr \pipe2_sr_op__input_cr + connect \sr_op__input_cr$14 \pipe2_sr_op__input_cr$35 + connect \sr_op__insn \pipe2_sr_op__insn + connect \sr_op__insn$18 \pipe2_sr_op__insn$39 + connect \sr_op__insn_type \pipe2_sr_op__insn_type + connect \sr_op__insn_type$2 \pipe2_sr_op__insn_type$23 + connect \sr_op__invert_in \pipe2_sr_op__invert_in + connect \sr_op__invert_in$11 \pipe2_sr_op__invert_in$32 + connect \sr_op__is_32bit \pipe2_sr_op__is_32bit + connect \sr_op__is_32bit$16 \pipe2_sr_op__is_32bit$37 + connect \sr_op__is_signed \pipe2_sr_op__is_signed + connect \sr_op__is_signed$17 \pipe2_sr_op__is_signed$38 + connect \sr_op__oe__oe \pipe2_sr_op__oe__oe + connect \sr_op__oe__oe$8 \pipe2_sr_op__oe__oe$29 + connect \sr_op__oe__ok \pipe2_sr_op__oe__ok + connect \sr_op__oe__ok$9 \pipe2_sr_op__oe__ok$30 + connect \sr_op__output_carry \pipe2_sr_op__output_carry + connect \sr_op__output_carry$13 \pipe2_sr_op__output_carry$34 + connect \sr_op__output_cr \pipe2_sr_op__output_cr + connect \sr_op__output_cr$15 \pipe2_sr_op__output_cr$36 + connect \sr_op__rc__ok \pipe2_sr_op__rc__ok + connect \sr_op__rc__ok$7 \pipe2_sr_op__rc__ok$28 + connect \sr_op__rc__rc \pipe2_sr_op__rc__rc + connect \sr_op__rc__rc$6 \pipe2_sr_op__rc__rc$27 + connect \sr_op__write_cr0 \pipe2_sr_op__write_cr0 + connect \sr_op__write_cr0$10 \pipe2_sr_op__write_cr0$31 + connect \xer_ca \pipe2_xer_ca + connect \xer_ca$23 \pipe2_xer_ca$44 + connect \xer_ca_ok \pipe2_xer_ca_ok + connect \xer_ca_ok$24 \pipe2_xer_ca_ok$45 + connect \xer_so \pipe2_xer_so + connect \xer_so_ok \pipe2_xer_so_ok + end + connect \muxid 2'00 + connect { \xer_ca_ok \xer_ca } { \pipe2_xer_ca_ok$45 \pipe2_xer_ca$44 } + connect { \cr_a_ok \cr_a } { \pipe2_cr_a_ok$43 \pipe2_cr_a$42 } + connect { \o_ok \o } { \pipe2_o_ok$41 \pipe2_o$40 } + connect { \sr_op__insn$63 \sr_op__is_signed$62 \sr_op__is_32bit$61 \sr_op__output_cr$60 \sr_op__input_cr$59 \sr_op__output_carry$58 \sr_op__input_carry$57 \sr_op__invert_in$56 \sr_op__write_cr0$55 \sr_op__oe__ok$54 \sr_op__oe__oe$53 \sr_op__rc__ok$52 \sr_op__rc__rc$51 \sr_op__imm_data__ok$50 \sr_op__imm_data__data$49 \sr_op__fn_unit$48 \sr_op__insn_type$47 } { \pipe2_sr_op__insn$39 \pipe2_sr_op__is_signed$38 \pipe2_sr_op__is_32bit$37 \pipe2_sr_op__output_cr$36 \pipe2_sr_op__input_cr$35 \pipe2_sr_op__output_carry$34 \pipe2_sr_op__input_carry$33 \pipe2_sr_op__invert_in$32 \pipe2_sr_op__write_cr0$31 \pipe2_sr_op__oe__ok$30 \pipe2_sr_op__oe__oe$29 \pipe2_sr_op__rc__ok$28 \pipe2_sr_op__rc__rc$27 \pipe2_sr_op__imm_data__ok$26 \pipe2_sr_op__imm_data__data$25 \pipe2_sr_op__fn_unit$24 \pipe2_sr_op__insn_type$23 } + connect \muxid$46 \pipe2_muxid$22 + connect \pipe2_n_ready_i \n_ready_i + connect \n_valid_o \pipe2_n_valid_o + connect \pipe1_xer_ca$21 \xer_ca$1 + connect \pipe1_xer_so$20 \xer_so + connect \pipe1_rc \rc + connect \pipe1_rb \rb + connect \pipe1_ra \ra + connect { \pipe1_sr_op__insn$19 \pipe1_sr_op__is_signed$18 \pipe1_sr_op__is_32bit$17 \pipe1_sr_op__output_cr$16 \pipe1_sr_op__input_cr$15 \pipe1_sr_op__output_carry$14 \pipe1_sr_op__input_carry$13 \pipe1_sr_op__invert_in$12 \pipe1_sr_op__write_cr0$11 \pipe1_sr_op__oe__ok$10 \pipe1_sr_op__oe__oe$9 \pipe1_sr_op__rc__ok$8 \pipe1_sr_op__rc__rc$7 \pipe1_sr_op__imm_data__ok$6 \pipe1_sr_op__imm_data__data$5 \pipe1_sr_op__fn_unit$4 \pipe1_sr_op__insn_type$3 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } + connect \pipe1_muxid$2 2'00 + connect \p_ready_o \pipe1_p_ready_o + connect \pipe1_p_valid_i \p_valid_i + connect { \pipe2_xer_ca_ok \pipe2_xer_ca } { \pipe1_xer_ca_ok \pipe1_xer_ca } + connect { \pipe2_xer_so_ok \pipe2_xer_so } { \pipe1_xer_so_ok \pipe1_xer_so } + connect { \pipe2_cr_a_ok \pipe2_cr_a } { \pipe1_cr_a_ok \pipe1_cr_a } + connect { \pipe2_o_ok \pipe2_o } { \pipe1_o_ok \pipe1_o } + connect { \pipe2_sr_op__insn \pipe2_sr_op__is_signed \pipe2_sr_op__is_32bit \pipe2_sr_op__output_cr \pipe2_sr_op__input_cr \pipe2_sr_op__output_carry \pipe2_sr_op__input_carry \pipe2_sr_op__invert_in \pipe2_sr_op__write_cr0 \pipe2_sr_op__oe__ok \pipe2_sr_op__oe__oe \pipe2_sr_op__rc__ok \pipe2_sr_op__rc__rc \pipe2_sr_op__imm_data__ok \pipe2_sr_op__imm_data__data \pipe2_sr_op__fn_unit \pipe2_sr_op__insn_type } { \pipe1_sr_op__insn \pipe1_sr_op__is_signed \pipe1_sr_op__is_32bit \pipe1_sr_op__output_cr \pipe1_sr_op__input_cr \pipe1_sr_op__output_carry \pipe1_sr_op__input_carry \pipe1_sr_op__invert_in \pipe1_sr_op__write_cr0 \pipe1_sr_op__oe__ok \pipe1_sr_op__oe__oe \pipe1_sr_op__rc__ok \pipe1_sr_op__rc__rc \pipe1_sr_op__imm_data__ok \pipe1_sr_op__imm_data__data \pipe1_sr_op__fn_unit \pipe1_sr_op__insn_type } + connect \pipe2_muxid \pipe1_muxid + connect \pipe1_n_ready_i \pipe2_p_ready_o + connect \pipe2_p_valid_i \pipe1_n_valid_o +end +attribute \src "libresoc.v:29703.1-30249.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0" +attribute \generator "nMigen" +module \alu_spr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 28 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 16 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 22 \fast1$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 6 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 9 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 8 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 14 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 27 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 26 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe_fast1$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_fast1_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_muxid$6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \pipe_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \pipe_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \pipe_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \pipe_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe_spr1$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_spr1_ok + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_spr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_spr_op__fn_unit$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_spr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_spr_op__insn$9 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_spr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_spr_op__insn_type$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_spr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_spr_op__is_32bit$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \pipe_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \pipe_xer_ca$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \pipe_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \pipe_xer_ov$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_xer_so$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 15 \spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 21 \spr1$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 7 \spr1_ok + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 11 \spr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \spr_op__fn_unit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 12 \spr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \spr_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 10 \spr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \spr_op__insn_type$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \spr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \spr_op__is_32bit$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 19 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 25 \xer_ca$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 18 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 24 \xer_ov$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 17 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 23 \xer_so$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 5 \xer_so_ok + attribute \module_not_derived 1 + attribute \src "libresoc.v:30184.10-30187.4" + cell \n$63 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:30188.10-30191.4" + cell \p$62 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:30192.13-30227.4" + cell \pipe$64 \pipe + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \fast1 \pipe_fast1 + connect \fast1$7 \pipe_fast1$12 + connect \fast1_ok \pipe_fast1_ok + connect \muxid \pipe_muxid + connect \muxid$1 \pipe_muxid$6 + connect \n_ready_i \pipe_n_ready_i + connect \n_valid_o \pipe_n_valid_o + connect \o \pipe_o + connect \o_ok \pipe_o_ok + connect \p_ready_o \pipe_p_ready_o + connect \p_valid_i \pipe_p_valid_i + connect \ra \pipe_ra + connect \spr1 \pipe_spr1 + connect \spr1$6 \pipe_spr1$11 + connect \spr1_ok \pipe_spr1_ok + connect \spr_op__fn_unit \pipe_spr_op__fn_unit + connect \spr_op__fn_unit$3 \pipe_spr_op__fn_unit$8 + connect \spr_op__insn \pipe_spr_op__insn + connect \spr_op__insn$4 \pipe_spr_op__insn$9 + connect \spr_op__insn_type \pipe_spr_op__insn_type + connect \spr_op__insn_type$2 \pipe_spr_op__insn_type$7 + connect \spr_op__is_32bit \pipe_spr_op__is_32bit + connect \spr_op__is_32bit$5 \pipe_spr_op__is_32bit$10 + connect \xer_ca \pipe_xer_ca + connect \xer_ca$10 \pipe_xer_ca$15 + connect \xer_ca_ok \pipe_xer_ca_ok + connect \xer_ov \pipe_xer_ov + connect \xer_ov$9 \pipe_xer_ov$14 + connect \xer_ov_ok \pipe_xer_ov_ok + connect \xer_so \pipe_xer_so + connect \xer_so$8 \pipe_xer_so$13 + connect \xer_so_ok \pipe_xer_so_ok + end + connect \muxid 2'00 + connect { \xer_ca_ok \xer_ca } { \pipe_xer_ca_ok \pipe_xer_ca$15 } + connect { \xer_ov_ok \xer_ov } { \pipe_xer_ov_ok \pipe_xer_ov$14 } + connect { \xer_so_ok \xer_so } { \pipe_xer_so_ok \pipe_xer_so$13 } + connect { \fast1_ok \fast1 } { \pipe_fast1_ok \pipe_fast1$12 } + connect { \spr1_ok \spr1 } { \pipe_spr1_ok \pipe_spr1$11 } + connect { \o_ok \o } { \pipe_o_ok \pipe_o } + connect { \spr_op__is_32bit$20 \spr_op__insn$19 \spr_op__fn_unit$18 \spr_op__insn_type$17 } { \pipe_spr_op__is_32bit$10 \pipe_spr_op__insn$9 \pipe_spr_op__fn_unit$8 \pipe_spr_op__insn_type$7 } + connect \muxid$16 \pipe_muxid$6 + connect \pipe_n_ready_i \n_ready_i + connect \n_valid_o \pipe_n_valid_o + connect \pipe_xer_ca \xer_ca$5 + connect \pipe_xer_ov \xer_ov$4 + connect \pipe_xer_so \xer_so$3 + connect \pipe_fast1 \fast1$2 + connect \pipe_spr1 \spr1$1 + connect \pipe_ra \ra + connect { \pipe_spr_op__is_32bit \pipe_spr_op__insn \pipe_spr_op__fn_unit \pipe_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } + connect \pipe_muxid 2'00 + connect \p_ready_o \pipe_p_ready_o + connect \pipe_p_valid_i \p_valid_i +end +attribute \src "libresoc.v:30253.1-31108.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0" +attribute \generator "nMigen" +module \alu_trap0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 29 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 19 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 25 \fast1$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 20 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 26 \fast2$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 22 \msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 6 \msr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 8 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 7 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 21 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 5 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 18 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 28 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 27 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_fast1$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_fast2$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe1_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe1_muxid$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \pipe1_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \pipe1_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \pipe1_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \pipe1_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_ra$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_rb$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe1_trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe1_trap_op__cia$8 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe1_trap_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe1_trap_op__fn_unit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe1_trap_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe1_trap_op__insn$6 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe1_trap_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe1_trap_op__insn_type$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_trap_op__is_32bit$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \pipe1_trap_op__ldst_exc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \pipe1_trap_op__ldst_exc$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe1_trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe1_trap_op__msr$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe1_trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe1_trap_op__trapaddr$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \pipe1_trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \pipe1_trap_op__traptype$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe2_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe2_fast1$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe2_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe2_fast2$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe2_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_msr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe2_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe2_muxid$17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \pipe2_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \pipe2_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe2_nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \pipe2_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \pipe2_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe2_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe2_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_trap_op__cia$22 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe2_trap_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe2_trap_op__fn_unit$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe2_trap_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe2_trap_op__insn$20 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe2_trap_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe2_trap_op__insn_type$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_trap_op__is_32bit$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \pipe2_trap_op__ldst_exc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \pipe2_trap_op__ldst_exc$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_trap_op__msr$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe2_trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe2_trap_op__trapaddr$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \pipe2_trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \pipe2_trap_op__traptype$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 23 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 13 \trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__cia$34 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 10 \trap_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \trap_op__fn_unit$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 11 \trap_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \trap_op__insn$32 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 9 \trap_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \trap_op__insn_type$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \trap_op__is_32bit$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 17 \trap_op__ldst_exc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \trap_op__ldst_exc$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 12 \trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__msr$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 16 \trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \trap_op__trapaddr$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 15 \trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \trap_op__traptype$36 + attribute \module_not_derived 1 + attribute \src "libresoc.v:30996.10-30999.4" + cell \n$31 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:31000.10-31003.4" + cell \p$30 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:31004.14-31039.4" + cell \pipe1$32 \pipe1 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \fast1 \pipe1_fast1 + connect \fast1$13 \pipe1_fast1$15 + connect \fast2 \pipe1_fast2 + connect \fast2$14 \pipe1_fast2$16 + connect \muxid \pipe1_muxid + connect \muxid$1 \pipe1_muxid$3 + connect \n_ready_i \pipe1_n_ready_i + connect \n_valid_o \pipe1_n_valid_o + connect \p_ready_o \pipe1_p_ready_o + connect \p_valid_i \pipe1_p_valid_i + connect \ra \pipe1_ra + connect \ra$11 \pipe1_ra$13 + connect \rb \pipe1_rb + connect \rb$12 \pipe1_rb$14 + connect \trap_op__cia \pipe1_trap_op__cia + connect \trap_op__cia$6 \pipe1_trap_op__cia$8 + connect \trap_op__fn_unit \pipe1_trap_op__fn_unit + connect \trap_op__fn_unit$3 \pipe1_trap_op__fn_unit$5 + connect \trap_op__insn \pipe1_trap_op__insn + connect \trap_op__insn$4 \pipe1_trap_op__insn$6 + connect \trap_op__insn_type \pipe1_trap_op__insn_type + connect \trap_op__insn_type$2 \pipe1_trap_op__insn_type$4 + connect \trap_op__is_32bit \pipe1_trap_op__is_32bit + connect \trap_op__is_32bit$7 \pipe1_trap_op__is_32bit$9 + connect \trap_op__ldst_exc \pipe1_trap_op__ldst_exc + connect \trap_op__ldst_exc$10 \pipe1_trap_op__ldst_exc$12 + connect \trap_op__msr \pipe1_trap_op__msr + connect \trap_op__msr$5 \pipe1_trap_op__msr$7 + connect \trap_op__trapaddr \pipe1_trap_op__trapaddr + connect \trap_op__trapaddr$9 \pipe1_trap_op__trapaddr$11 + connect \trap_op__traptype \pipe1_trap_op__traptype + connect \trap_op__traptype$8 \pipe1_trap_op__traptype$10 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:31040.14-31081.4" + cell \pipe2$35 \pipe2 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \fast1 \pipe2_fast1 + connect \fast1$11 \pipe2_fast1$27 + connect \fast1_ok \pipe2_fast1_ok + connect \fast2 \pipe2_fast2 + connect \fast2$12 \pipe2_fast2$28 + connect \fast2_ok \pipe2_fast2_ok + connect \msr \pipe2_msr + connect \msr_ok \pipe2_msr_ok + connect \muxid \pipe2_muxid + connect \muxid$1 \pipe2_muxid$17 + connect \n_ready_i \pipe2_n_ready_i + connect \n_valid_o \pipe2_n_valid_o + connect \nia \pipe2_nia + connect \nia_ok \pipe2_nia_ok + connect \o \pipe2_o + connect \o_ok \pipe2_o_ok + connect \p_ready_o \pipe2_p_ready_o + connect \p_valid_i \pipe2_p_valid_i + connect \ra \pipe2_ra + connect \rb \pipe2_rb + connect \trap_op__cia \pipe2_trap_op__cia + connect \trap_op__cia$6 \pipe2_trap_op__cia$22 + connect \trap_op__fn_unit \pipe2_trap_op__fn_unit + connect \trap_op__fn_unit$3 \pipe2_trap_op__fn_unit$19 + connect \trap_op__insn \pipe2_trap_op__insn + connect \trap_op__insn$4 \pipe2_trap_op__insn$20 + connect \trap_op__insn_type \pipe2_trap_op__insn_type + connect \trap_op__insn_type$2 \pipe2_trap_op__insn_type$18 + connect \trap_op__is_32bit \pipe2_trap_op__is_32bit + connect \trap_op__is_32bit$7 \pipe2_trap_op__is_32bit$23 + connect \trap_op__ldst_exc \pipe2_trap_op__ldst_exc + connect \trap_op__ldst_exc$10 \pipe2_trap_op__ldst_exc$26 + connect \trap_op__msr \pipe2_trap_op__msr + connect \trap_op__msr$5 \pipe2_trap_op__msr$21 + connect \trap_op__trapaddr \pipe2_trap_op__trapaddr + connect \trap_op__trapaddr$9 \pipe2_trap_op__trapaddr$25 + connect \trap_op__traptype \pipe2_trap_op__traptype + connect \trap_op__traptype$8 \pipe2_trap_op__traptype$24 + end + connect \muxid 2'00 + connect { \msr_ok \msr } { \pipe2_msr_ok \pipe2_msr } + connect { \nia_ok \nia } { \pipe2_nia_ok \pipe2_nia } + connect { \fast2_ok \fast2 } { \pipe2_fast2_ok \pipe2_fast2$28 } + connect { \fast1_ok \fast1 } { \pipe2_fast1_ok \pipe2_fast1$27 } + connect { \o_ok \o } { \pipe2_o_ok \pipe2_o } + connect { \trap_op__ldst_exc$38 \trap_op__trapaddr$37 \trap_op__traptype$36 \trap_op__is_32bit$35 \trap_op__cia$34 \trap_op__msr$33 \trap_op__insn$32 \trap_op__fn_unit$31 \trap_op__insn_type$30 } { \pipe2_trap_op__ldst_exc$26 \pipe2_trap_op__trapaddr$25 \pipe2_trap_op__traptype$24 \pipe2_trap_op__is_32bit$23 \pipe2_trap_op__cia$22 \pipe2_trap_op__msr$21 \pipe2_trap_op__insn$20 \pipe2_trap_op__fn_unit$19 \pipe2_trap_op__insn_type$18 } + connect \muxid$29 \pipe2_muxid$17 + connect \pipe2_n_ready_i \n_ready_i + connect \n_valid_o \pipe2_n_valid_o + connect \pipe1_fast2$16 \fast2$2 + connect \pipe1_fast1$15 \fast1$1 + connect \pipe1_rb$14 \rb + connect \pipe1_ra$13 \ra + connect { \pipe1_trap_op__ldst_exc$12 \pipe1_trap_op__trapaddr$11 \pipe1_trap_op__traptype$10 \pipe1_trap_op__is_32bit$9 \pipe1_trap_op__cia$8 \pipe1_trap_op__msr$7 \pipe1_trap_op__insn$6 \pipe1_trap_op__fn_unit$5 \pipe1_trap_op__insn_type$4 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } + connect \pipe1_muxid$3 2'00 + connect \p_ready_o \pipe1_p_ready_o + connect \pipe1_p_valid_i \p_valid_i + connect \pipe2_fast2 \pipe1_fast2 + connect \pipe2_fast1 \pipe1_fast1 + connect \pipe2_rb \pipe1_rb + connect \pipe2_ra \pipe1_ra + connect { \pipe2_trap_op__ldst_exc \pipe2_trap_op__trapaddr \pipe2_trap_op__traptype \pipe2_trap_op__is_32bit \pipe2_trap_op__cia \pipe2_trap_op__msr \pipe2_trap_op__insn \pipe2_trap_op__fn_unit \pipe2_trap_op__insn_type } { \pipe1_trap_op__ldst_exc \pipe1_trap_op__trapaddr \pipe1_trap_op__traptype \pipe1_trap_op__is_32bit \pipe1_trap_op__cia \pipe1_trap_op__msr \pipe1_trap_op__insn \pipe1_trap_op__fn_unit \pipe1_trap_op__insn_type } + connect \pipe2_muxid \pipe1_muxid + connect \pipe1_n_ready_i \pipe2_p_ready_o + connect \pipe2_p_valid_i \pipe1_n_valid_o +end +attribute \src "libresoc.v:31112.1-31170.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alui_l" +attribute \generator "nMigen" +module \alui_l + attribute \src "libresoc.v:31113.7-31113.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:31158.3-31166.6" + wire $0\q_int$next[0:0]$992 + attribute \src "libresoc.v:31156.3-31157.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:31158.3-31166.6" + wire $1\q_int$next[0:0]$993 + attribute \src "libresoc.v:31137.7-31137.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:31148.17-31148.96" + wire $and$libresoc.v:31148$982_Y + attribute \src "libresoc.v:31153.17-31153.96" + wire $and$libresoc.v:31153$987_Y + attribute \src "libresoc.v:31150.18-31150.94" + wire $not$libresoc.v:31150$984_Y + attribute \src "libresoc.v:31152.17-31152.93" + wire $not$libresoc.v:31152$986_Y + attribute \src "libresoc.v:31155.17-31155.93" + wire $not$libresoc.v:31155$989_Y + attribute \src "libresoc.v:31149.18-31149.99" + wire $or$libresoc.v:31149$983_Y + attribute \src "libresoc.v:31151.18-31151.100" + wire $or$libresoc.v:31151$985_Y + attribute \src "libresoc.v:31154.17-31154.98" + wire $or$libresoc.v:31154$988_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:31113.7-31113.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:31148$982 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:31148$982_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:31153$987 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:31153$987_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:31150$984 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$libresoc.v:31150$984_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:31152$986 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31152$986_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:31155$989 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31155$989_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:31149$983 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$libresoc.v:31149$983_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:31151$985 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$libresoc.v:31151$985_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:31154$988 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$libresoc.v:31154$988_Y + end + attribute \src "libresoc.v:31113.7-31113.20" + process $proc$libresoc.v:31113$994 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:31137.7-31137.19" + process $proc$libresoc.v:31137$995 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:31156.3-31157.27" + process $proc$libresoc.v:31156$990 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:31158.3-31166.6" + process $proc$libresoc.v:31158$991 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$992 $1\q_int$next[0:0]$993 + attribute \src "libresoc.v:31159.5-31159.29" + switch \initial + attribute \src "libresoc.v:31159.9-31159.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$993 1'0 + case + assign $1\q_int$next[0:0]$993 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$992 + end + connect \$9 $and$libresoc.v:31148$982_Y + connect \$11 $or$libresoc.v:31149$983_Y + connect \$13 $not$libresoc.v:31150$984_Y + connect \$15 $or$libresoc.v:31151$985_Y + connect \$1 $not$libresoc.v:31152$986_Y + connect \$3 $and$libresoc.v:31153$987_Y + connect \$5 $or$libresoc.v:31154$988_Y + connect \$7 $not$libresoc.v:31155$989_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "libresoc.v:31174.1-31232.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alui_l" +attribute \generator "nMigen" +module \alui_l$106 + attribute \src "libresoc.v:31175.7-31175.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:31220.3-31228.6" + wire $0\q_int$next[0:0]$1006 + attribute \src "libresoc.v:31218.3-31219.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:31220.3-31228.6" + wire $1\q_int$next[0:0]$1007 + attribute \src "libresoc.v:31199.7-31199.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:31210.17-31210.96" + wire $and$libresoc.v:31210$996_Y + attribute \src "libresoc.v:31215.17-31215.96" + wire $and$libresoc.v:31215$1001_Y + attribute \src "libresoc.v:31212.18-31212.94" + wire $not$libresoc.v:31212$998_Y + attribute \src "libresoc.v:31214.17-31214.93" + wire $not$libresoc.v:31214$1000_Y + attribute \src "libresoc.v:31217.17-31217.93" + wire $not$libresoc.v:31217$1003_Y + attribute \src "libresoc.v:31211.18-31211.99" + wire $or$libresoc.v:31211$997_Y + attribute \src "libresoc.v:31213.18-31213.100" + wire $or$libresoc.v:31213$999_Y + attribute \src "libresoc.v:31216.17-31216.98" + wire $or$libresoc.v:31216$1002_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:31175.7-31175.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:31210$996 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:31210$996_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:31215$1001 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:31215$1001_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:31212$998 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$libresoc.v:31212$998_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:31214$1000 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31214$1000_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:31217$1003 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31217$1003_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:31211$997 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$libresoc.v:31211$997_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:31213$999 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$libresoc.v:31213$999_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:31216$1002 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$libresoc.v:31216$1002_Y + end + attribute \src "libresoc.v:31175.7-31175.20" + process $proc$libresoc.v:31175$1008 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:31199.7-31199.19" + process $proc$libresoc.v:31199$1009 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:31218.3-31219.27" + process $proc$libresoc.v:31218$1004 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:31220.3-31228.6" + process $proc$libresoc.v:31220$1005 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1006 $1\q_int$next[0:0]$1007 + attribute \src "libresoc.v:31221.5-31221.29" + switch \initial + attribute \src "libresoc.v:31221.9-31221.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1007 1'0 + case + assign $1\q_int$next[0:0]$1007 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1006 + end + connect \$9 $and$libresoc.v:31210$996_Y + connect \$11 $or$libresoc.v:31211$997_Y + connect \$13 $not$libresoc.v:31212$998_Y + connect \$15 $or$libresoc.v:31213$999_Y + connect \$1 $not$libresoc.v:31214$1000_Y + connect \$3 $and$libresoc.v:31215$1001_Y + connect \$5 $or$libresoc.v:31216$1002_Y + connect \$7 $not$libresoc.v:31217$1003_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "libresoc.v:31236.1-31294.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alui_l" +attribute \generator "nMigen" +module \alui_l$124 + attribute \src "libresoc.v:31237.7-31237.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:31282.3-31290.6" + wire $0\q_int$next[0:0]$1020 + attribute \src "libresoc.v:31280.3-31281.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:31282.3-31290.6" + wire $1\q_int$next[0:0]$1021 + attribute \src "libresoc.v:31261.7-31261.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:31272.17-31272.96" + wire $and$libresoc.v:31272$1010_Y + attribute \src "libresoc.v:31277.17-31277.96" + wire $and$libresoc.v:31277$1015_Y + attribute \src "libresoc.v:31274.18-31274.94" + wire $not$libresoc.v:31274$1012_Y + attribute \src "libresoc.v:31276.17-31276.93" + wire $not$libresoc.v:31276$1014_Y + attribute \src "libresoc.v:31279.17-31279.93" + wire $not$libresoc.v:31279$1017_Y + attribute \src "libresoc.v:31273.18-31273.99" + wire $or$libresoc.v:31273$1011_Y + attribute \src "libresoc.v:31275.18-31275.100" + wire $or$libresoc.v:31275$1013_Y + attribute \src "libresoc.v:31278.17-31278.98" + wire $or$libresoc.v:31278$1016_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:31237.7-31237.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:31272$1010 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:31272$1010_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:31277$1015 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:31277$1015_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:31274$1012 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$libresoc.v:31274$1012_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:31276$1014 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31276$1014_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:31279$1017 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31279$1017_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:31273$1011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$libresoc.v:31273$1011_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:31275$1013 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$libresoc.v:31275$1013_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:31278$1016 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$libresoc.v:31278$1016_Y + end + attribute \src "libresoc.v:31237.7-31237.20" + process $proc$libresoc.v:31237$1022 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:31261.7-31261.19" + process $proc$libresoc.v:31261$1023 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:31280.3-31281.27" + process $proc$libresoc.v:31280$1018 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:31282.3-31290.6" + process $proc$libresoc.v:31282$1019 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1020 $1\q_int$next[0:0]$1021 + attribute \src "libresoc.v:31283.5-31283.29" + switch \initial + attribute \src "libresoc.v:31283.9-31283.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1021 1'0 + case + assign $1\q_int$next[0:0]$1021 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1020 + end + connect \$9 $and$libresoc.v:31272$1010_Y + connect \$11 $or$libresoc.v:31273$1011_Y + connect \$13 $not$libresoc.v:31274$1012_Y + connect \$15 $or$libresoc.v:31275$1013_Y + connect \$1 $not$libresoc.v:31276$1014_Y + connect \$3 $and$libresoc.v:31277$1015_Y + connect \$5 $or$libresoc.v:31278$1016_Y + connect \$7 $not$libresoc.v:31279$1017_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "libresoc.v:31298.1-31356.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alui_l" +attribute \generator "nMigen" +module \alui_l$15 + attribute \src "libresoc.v:31299.7-31299.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:31344.3-31352.6" + wire $0\q_int$next[0:0]$1034 + attribute \src "libresoc.v:31342.3-31343.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:31344.3-31352.6" + wire $1\q_int$next[0:0]$1035 + attribute \src "libresoc.v:31323.7-31323.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:31334.17-31334.96" + wire $and$libresoc.v:31334$1024_Y + attribute \src "libresoc.v:31339.17-31339.96" + wire $and$libresoc.v:31339$1029_Y + attribute \src "libresoc.v:31336.18-31336.94" + wire $not$libresoc.v:31336$1026_Y + attribute \src "libresoc.v:31338.17-31338.93" + wire $not$libresoc.v:31338$1028_Y + attribute \src "libresoc.v:31341.17-31341.93" + wire $not$libresoc.v:31341$1031_Y + attribute \src "libresoc.v:31335.18-31335.99" + wire $or$libresoc.v:31335$1025_Y + attribute \src "libresoc.v:31337.18-31337.100" + wire $or$libresoc.v:31337$1027_Y + attribute \src "libresoc.v:31340.17-31340.98" + wire $or$libresoc.v:31340$1030_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:31299.7-31299.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:31334$1024 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:31334$1024_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:31339$1029 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:31339$1029_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:31336$1026 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$libresoc.v:31336$1026_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:31338$1028 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31338$1028_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:31341$1031 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31341$1031_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:31335$1025 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$libresoc.v:31335$1025_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:31337$1027 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$libresoc.v:31337$1027_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:31340$1030 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$libresoc.v:31340$1030_Y + end + attribute \src "libresoc.v:31299.7-31299.20" + process $proc$libresoc.v:31299$1036 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:31323.7-31323.19" + process $proc$libresoc.v:31323$1037 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:31342.3-31343.27" + process $proc$libresoc.v:31342$1032 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:31344.3-31352.6" + process $proc$libresoc.v:31344$1033 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1034 $1\q_int$next[0:0]$1035 + attribute \src "libresoc.v:31345.5-31345.29" + switch \initial + attribute \src "libresoc.v:31345.9-31345.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1035 1'0 + case + assign $1\q_int$next[0:0]$1035 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1034 + end + connect \$9 $and$libresoc.v:31334$1024_Y + connect \$11 $or$libresoc.v:31335$1025_Y + connect \$13 $not$libresoc.v:31336$1026_Y + connect \$15 $or$libresoc.v:31337$1027_Y + connect \$1 $not$libresoc.v:31338$1028_Y + connect \$3 $and$libresoc.v:31339$1029_Y + connect \$5 $or$libresoc.v:31340$1030_Y + connect \$7 $not$libresoc.v:31341$1031_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "libresoc.v:31360.1-31418.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alui_l" +attribute \generator "nMigen" +module \alui_l$28 + attribute \src "libresoc.v:31361.7-31361.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:31406.3-31414.6" + wire $0\q_int$next[0:0]$1048 + attribute \src "libresoc.v:31404.3-31405.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:31406.3-31414.6" + wire $1\q_int$next[0:0]$1049 + attribute \src "libresoc.v:31385.7-31385.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:31396.17-31396.96" + wire $and$libresoc.v:31396$1038_Y + attribute \src "libresoc.v:31401.17-31401.96" + wire $and$libresoc.v:31401$1043_Y + attribute \src "libresoc.v:31398.18-31398.94" + wire $not$libresoc.v:31398$1040_Y + attribute \src "libresoc.v:31400.17-31400.93" + wire $not$libresoc.v:31400$1042_Y + attribute \src "libresoc.v:31403.17-31403.93" + wire $not$libresoc.v:31403$1045_Y + attribute \src "libresoc.v:31397.18-31397.99" + wire $or$libresoc.v:31397$1039_Y + attribute \src "libresoc.v:31399.18-31399.100" + wire $or$libresoc.v:31399$1041_Y + attribute \src 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wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:31396$1038 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:31396$1038_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:31401$1043 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:31401$1043_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:31398$1040 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$libresoc.v:31398$1040_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:31400$1042 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31400$1042_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:31403$1045 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31403$1045_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:31397$1039 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$libresoc.v:31397$1039_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:31399$1041 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$libresoc.v:31399$1041_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:31402$1044 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$libresoc.v:31402$1044_Y + end + attribute \src "libresoc.v:31361.7-31361.20" + process $proc$libresoc.v:31361$1050 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:31385.7-31385.19" + process $proc$libresoc.v:31385$1051 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:31404.3-31405.27" + process $proc$libresoc.v:31404$1046 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:31406.3-31414.6" + process $proc$libresoc.v:31406$1047 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1048 $1\q_int$next[0:0]$1049 + attribute \src "libresoc.v:31407.5-31407.29" + switch \initial + attribute \src "libresoc.v:31407.9-31407.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1049 1'0 + case + assign $1\q_int$next[0:0]$1049 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1048 + end + connect \$9 $and$libresoc.v:31396$1038_Y + connect \$11 $or$libresoc.v:31397$1039_Y + connect \$13 $not$libresoc.v:31398$1040_Y + connect \$15 $or$libresoc.v:31399$1041_Y + connect \$1 $not$libresoc.v:31400$1042_Y + connect \$3 $and$libresoc.v:31401$1043_Y + connect \$5 $or$libresoc.v:31402$1044_Y + connect \$7 $not$libresoc.v:31403$1045_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "libresoc.v:31422.1-31480.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alui_l" +attribute \generator "nMigen" +module \alui_l$44 + attribute \src "libresoc.v:31423.7-31423.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:31468.3-31476.6" + wire $0\q_int$next[0:0]$1062 + attribute \src "libresoc.v:31466.3-31467.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:31468.3-31476.6" + wire $1\q_int$next[0:0]$1063 + attribute \src "libresoc.v:31447.7-31447.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:31458.17-31458.96" + wire $and$libresoc.v:31458$1052_Y + attribute \src "libresoc.v:31463.17-31463.96" + wire $and$libresoc.v:31463$1057_Y + attribute \src "libresoc.v:31460.18-31460.94" + wire $not$libresoc.v:31460$1054_Y + attribute \src "libresoc.v:31462.17-31462.93" + wire $not$libresoc.v:31462$1056_Y + attribute \src "libresoc.v:31465.17-31465.93" + wire $not$libresoc.v:31465$1059_Y + attribute \src "libresoc.v:31459.18-31459.99" + wire $or$libresoc.v:31459$1053_Y + attribute \src "libresoc.v:31461.18-31461.100" + wire $or$libresoc.v:31461$1055_Y + attribute \src "libresoc.v:31464.17-31464.98" + wire $or$libresoc.v:31464$1058_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:31423.7-31423.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:31458$1052 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:31458$1052_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:31463$1057 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:31463$1057_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:31460$1054 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$libresoc.v:31460$1054_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:31462$1056 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31462$1056_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:31465$1059 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31465$1059_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:31459$1053 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$libresoc.v:31459$1053_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:31461$1055 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$libresoc.v:31461$1055_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:31464$1058 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$libresoc.v:31464$1058_Y + end + attribute \src "libresoc.v:31423.7-31423.20" + process $proc$libresoc.v:31423$1064 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:31447.7-31447.19" + process $proc$libresoc.v:31447$1065 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:31466.3-31467.27" + process $proc$libresoc.v:31466$1060 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:31468.3-31476.6" + process $proc$libresoc.v:31468$1061 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1062 $1\q_int$next[0:0]$1063 + attribute \src "libresoc.v:31469.5-31469.29" + switch \initial + attribute \src "libresoc.v:31469.9-31469.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1063 1'0 + case + assign $1\q_int$next[0:0]$1063 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1062 + end + connect \$9 $and$libresoc.v:31458$1052_Y + connect \$11 $or$libresoc.v:31459$1053_Y + connect \$13 $not$libresoc.v:31460$1054_Y + connect \$15 $or$libresoc.v:31461$1055_Y + connect \$1 $not$libresoc.v:31462$1056_Y + connect \$3 $and$libresoc.v:31463$1057_Y + connect \$5 $or$libresoc.v:31464$1058_Y + connect \$7 $not$libresoc.v:31465$1059_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "libresoc.v:31484.1-31542.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alui_l" +attribute \generator "nMigen" +module \alui_l$60 + attribute \src "libresoc.v:31485.7-31485.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:31530.3-31538.6" + wire $0\q_int$next[0:0]$1076 + attribute \src "libresoc.v:31528.3-31529.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:31530.3-31538.6" + wire $1\q_int$next[0:0]$1077 + attribute \src "libresoc.v:31509.7-31509.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:31520.17-31520.96" + wire $and$libresoc.v:31520$1066_Y + attribute \src "libresoc.v:31525.17-31525.96" + wire $and$libresoc.v:31525$1071_Y + attribute \src "libresoc.v:31522.18-31522.94" + wire $not$libresoc.v:31522$1068_Y + attribute \src "libresoc.v:31524.17-31524.93" + wire $not$libresoc.v:31524$1070_Y + attribute \src "libresoc.v:31527.17-31527.93" + wire $not$libresoc.v:31527$1073_Y + attribute \src "libresoc.v:31521.18-31521.99" + wire $or$libresoc.v:31521$1067_Y + attribute \src "libresoc.v:31523.18-31523.100" + wire $or$libresoc.v:31523$1069_Y + attribute \src "libresoc.v:31526.17-31526.98" + wire $or$libresoc.v:31526$1072_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:31485.7-31485.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:31520$1066 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:31520$1066_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:31525$1071 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:31525$1071_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:31522$1068 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$libresoc.v:31522$1068_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:31524$1070 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31524$1070_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:31527$1073 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31527$1073_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:31521$1067 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$libresoc.v:31521$1067_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:31523$1069 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$libresoc.v:31523$1069_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:31526$1072 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$libresoc.v:31526$1072_Y + end + attribute \src "libresoc.v:31485.7-31485.20" + process $proc$libresoc.v:31485$1078 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:31509.7-31509.19" + process $proc$libresoc.v:31509$1079 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:31528.3-31529.27" + process $proc$libresoc.v:31528$1074 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:31530.3-31538.6" + process $proc$libresoc.v:31530$1075 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1076 $1\q_int$next[0:0]$1077 + attribute \src "libresoc.v:31531.5-31531.29" + switch \initial + attribute \src "libresoc.v:31531.9-31531.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1077 1'0 + case + assign $1\q_int$next[0:0]$1077 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1076 + end + connect \$9 $and$libresoc.v:31520$1066_Y + connect \$11 $or$libresoc.v:31521$1067_Y + connect \$13 $not$libresoc.v:31522$1068_Y + connect \$15 $or$libresoc.v:31523$1069_Y + connect \$1 $not$libresoc.v:31524$1070_Y + connect \$3 $and$libresoc.v:31525$1071_Y + connect \$5 $or$libresoc.v:31526$1072_Y + connect \$7 $not$libresoc.v:31527$1073_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "libresoc.v:31546.1-31604.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alui_l" +attribute \generator "nMigen" +module \alui_l$72 + attribute \src "libresoc.v:31547.7-31547.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:31592.3-31600.6" + wire $0\q_int$next[0:0]$1090 + attribute \src "libresoc.v:31590.3-31591.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:31592.3-31600.6" + wire $1\q_int$next[0:0]$1091 + attribute \src "libresoc.v:31571.7-31571.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:31582.17-31582.96" + wire $and$libresoc.v:31582$1080_Y + attribute \src "libresoc.v:31587.17-31587.96" + wire $and$libresoc.v:31587$1085_Y + attribute \src "libresoc.v:31584.18-31584.94" + wire $not$libresoc.v:31584$1082_Y + attribute \src "libresoc.v:31586.17-31586.93" + wire $not$libresoc.v:31586$1084_Y + attribute \src "libresoc.v:31589.17-31589.93" + wire $not$libresoc.v:31589$1087_Y + attribute \src "libresoc.v:31583.18-31583.99" + wire $or$libresoc.v:31583$1081_Y + attribute \src "libresoc.v:31585.18-31585.100" + wire $or$libresoc.v:31585$1083_Y + attribute \src "libresoc.v:31588.17-31588.98" + wire $or$libresoc.v:31588$1086_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:31547.7-31547.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:31582$1080 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:31582$1080_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:31587$1085 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:31587$1085_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:31584$1082 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$libresoc.v:31584$1082_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:31586$1084 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31586$1084_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:31589$1087 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31589$1087_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:31583$1081 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$libresoc.v:31583$1081_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:31585$1083 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$libresoc.v:31585$1083_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:31588$1086 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$libresoc.v:31588$1086_Y + end + attribute \src "libresoc.v:31547.7-31547.20" + process $proc$libresoc.v:31547$1092 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:31571.7-31571.19" + process $proc$libresoc.v:31571$1093 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:31590.3-31591.27" + process $proc$libresoc.v:31590$1088 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:31592.3-31600.6" + process $proc$libresoc.v:31592$1089 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1090 $1\q_int$next[0:0]$1091 + attribute \src "libresoc.v:31593.5-31593.29" + switch \initial + attribute \src "libresoc.v:31593.9-31593.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1091 1'0 + case + assign $1\q_int$next[0:0]$1091 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1090 + end + connect \$9 $and$libresoc.v:31582$1080_Y + connect \$11 $or$libresoc.v:31583$1081_Y + connect \$13 $not$libresoc.v:31584$1082_Y + connect \$15 $or$libresoc.v:31585$1083_Y + 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"libresoc.v:31646.18-31646.94" + wire $not$libresoc.v:31646$1096_Y + attribute \src "libresoc.v:31648.17-31648.93" + wire $not$libresoc.v:31648$1098_Y + attribute \src "libresoc.v:31651.17-31651.93" + wire $not$libresoc.v:31651$1101_Y + attribute \src "libresoc.v:31645.18-31645.99" + wire $or$libresoc.v:31645$1095_Y + attribute \src "libresoc.v:31647.18-31647.100" + wire $or$libresoc.v:31647$1097_Y + attribute \src "libresoc.v:31650.17-31650.98" + wire $or$libresoc.v:31650$1100_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:31609.7-31609.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:31644$1094 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:31644$1094_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:31649$1099 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:31649$1099_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:31646$1096 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$libresoc.v:31646$1096_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:31648$1098 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31648$1098_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:31651$1101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31651$1101_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:31645$1095 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$libresoc.v:31645$1095_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:31647$1097 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$libresoc.v:31647$1097_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:31650$1100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$libresoc.v:31650$1100_Y + end + attribute \src "libresoc.v:31609.7-31609.20" + process $proc$libresoc.v:31609$1106 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:31633.7-31633.19" + process $proc$libresoc.v:31633$1107 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:31652.3-31653.27" + process $proc$libresoc.v:31652$1102 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:31654.3-31662.6" + process $proc$libresoc.v:31654$1103 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1104 $1\q_int$next[0:0]$1105 + attribute \src "libresoc.v:31655.5-31655.29" + switch \initial + attribute \src "libresoc.v:31655.9-31655.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1105 1'0 + case + assign $1\q_int$next[0:0]$1105 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1104 + end + connect \$9 $and$libresoc.v:31644$1094_Y + connect \$11 $or$libresoc.v:31645$1095_Y + connect \$13 $not$libresoc.v:31646$1096_Y + connect \$15 $or$libresoc.v:31647$1097_Y + connect \$1 $not$libresoc.v:31648$1098_Y + connect \$3 $and$libresoc.v:31649$1099_Y + connect \$5 $or$libresoc.v:31650$1100_Y + connect \$7 $not$libresoc.v:31651$1101_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "libresoc.v:31670.1-33014.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.bpermd" +attribute \generator "nMigen" +module \bpermd + attribute \src "libresoc.v:31671.7-31671.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:31848.3-32939.6" + wire width 64 $0\perm[63:0] + attribute \src "libresoc.v:31848.3-32939.6" + wire $10\perm[4:4] + attribute \src "libresoc.v:31848.3-32939.6" + wire $11\perm[5:5] + attribute \src "libresoc.v:31848.3-32939.6" + wire $12\perm[5:5] + attribute \src "libresoc.v:31848.3-32939.6" + wire $13\perm[6:6] + attribute \src "libresoc.v:31848.3-32939.6" + wire $14\perm[6:6] + attribute \src "libresoc.v:31848.3-32939.6" + wire $15\perm[7:7] + attribute \src "libresoc.v:31848.3-32939.6" + wire $16\perm[7:7] + attribute \src "libresoc.v:31848.3-32939.6" + wire $1\perm[0:0] + attribute \src "libresoc.v:31848.3-32939.6" + wire $2\perm[0:0] + attribute \src "libresoc.v:31848.3-32939.6" + wire $3\perm[1:1] + attribute \src "libresoc.v:31848.3-32939.6" + wire $4\perm[1:1] + attribute \src "libresoc.v:31848.3-32939.6" + wire $5\perm[2:2] + attribute \src "libresoc.v:31848.3-32939.6" + wire $6\perm[2:2] + attribute \src "libresoc.v:31848.3-32939.6" + wire $7\perm[3:3] + attribute \src "libresoc.v:31848.3-32939.6" + wire $8\perm[3:3] + attribute \src "libresoc.v:31848.3-32939.6" + wire $9\perm[4:4] + attribute \src "libresoc.v:31840.17-31840.104" + wire $lt$libresoc.v:31840$1108_Y + attribute \src "libresoc.v:31841.18-31841.105" + wire $lt$libresoc.v:31841$1109_Y + attribute \src "libresoc.v:31842.18-31842.105" + wire $lt$libresoc.v:31842$1110_Y + attribute \src "libresoc.v:31843.18-31843.105" + wire $lt$libresoc.v:31843$1111_Y + attribute \src "libresoc.v:31844.17-31844.104" + wire $lt$libresoc.v:31844$1112_Y + attribute \src "libresoc.v:31845.17-31845.104" + wire $lt$libresoc.v:31845$1113_Y + attribute \src "libresoc.v:31846.17-31846.104" + wire $lt$libresoc.v:31846$1114_Y + attribute \src "libresoc.v:31847.17-31847.104" + wire $lt$libresoc.v:31847$1115_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_7 + attribute \src "libresoc.v:31671.7-31671.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:60" + wire width 64 \perm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:55" + wire width 64 output 2 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:56" + wire width 64 input 1 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:54" + wire width 64 input 3 \rs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$libresoc.v:31840$1108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_4 + connect \B 7'1000000 + connect \Y $lt$libresoc.v:31840$1108_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$libresoc.v:31841$1109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_5 + connect \B 7'1000000 + connect \Y $lt$libresoc.v:31841$1109_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$libresoc.v:31842$1110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_6 + connect \B 7'1000000 + connect \Y $lt$libresoc.v:31842$1110_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$libresoc.v:31843$1111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_7 + connect \B 7'1000000 + connect \Y $lt$libresoc.v:31843$1111_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$libresoc.v:31844$1112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_0 + connect \B 7'1000000 + connect \Y $lt$libresoc.v:31844$1112_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$libresoc.v:31845$1113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_1 + connect \B 7'1000000 + connect \Y $lt$libresoc.v:31845$1113_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$libresoc.v:31846$1114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_2 + connect \B 7'1000000 + connect \Y $lt$libresoc.v:31846$1114_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$libresoc.v:31847$1115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_3 + connect \B 7'1000000 + connect \Y $lt$libresoc.v:31847$1115_Y + end + attribute \src "libresoc.v:31671.7-31671.20" + process $proc$libresoc.v:31671$1117 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:31848.3-32939.6" + process $proc$libresoc.v:31848$1116 + assign { } { } + assign $0\perm[63:0] [63:8] 56'00000000000000000000000000000000000000000000000000000000 + assign $0\perm[63:0] [0] $1\perm[0:0] + assign $0\perm[63:0] [1] $3\perm[1:1] + assign $0\perm[63:0] [2] $5\perm[2:2] + assign $0\perm[63:0] [3] $7\perm[3:3] + assign $0\perm[63:0] [4] $9\perm[4:4] + assign $0\perm[63:0] [5] $11\perm[5:5] + assign $0\perm[63:0] [6] $13\perm[6:6] + assign $0\perm[63:0] [7] $15\perm[7:7] + attribute \src "libresoc.v:31849.5-31849.29" + switch \initial + attribute \src "libresoc.v:31849.9-31849.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\perm[0:0] $2\perm[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_0 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $2\perm[0:0] \rb64_0 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $2\perm[0:0] \rb64_1 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $2\perm[0:0] \rb64_2 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $2\perm[0:0] \rb64_3 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $2\perm[0:0] \rb64_4 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $2\perm[0:0] \rb64_5 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $2\perm[0:0] \rb64_6 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $2\perm[0:0] \rb64_7 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $2\perm[0:0] \rb64_8 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $2\perm[0:0] \rb64_9 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $2\perm[0:0] \rb64_10 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $2\perm[0:0] \rb64_11 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $2\perm[0:0] \rb64_12 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $2\perm[0:0] \rb64_13 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $2\perm[0:0] \rb64_14 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $2\perm[0:0] \rb64_15 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $2\perm[0:0] \rb64_16 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $2\perm[0:0] \rb64_17 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $2\perm[0:0] \rb64_18 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $2\perm[0:0] \rb64_19 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $2\perm[0:0] \rb64_20 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $2\perm[0:0] \rb64_21 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $2\perm[0:0] \rb64_22 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $2\perm[0:0] \rb64_23 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $2\perm[0:0] \rb64_24 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $2\perm[0:0] \rb64_25 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $2\perm[0:0] \rb64_26 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $2\perm[0:0] \rb64_27 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $2\perm[0:0] \rb64_28 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $2\perm[0:0] \rb64_29 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $2\perm[0:0] \rb64_30 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $2\perm[0:0] \rb64_31 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $2\perm[0:0] \rb64_32 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $2\perm[0:0] \rb64_33 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $2\perm[0:0] \rb64_34 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $2\perm[0:0] \rb64_35 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $2\perm[0:0] \rb64_36 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $2\perm[0:0] \rb64_37 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $2\perm[0:0] \rb64_38 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $2\perm[0:0] \rb64_39 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $2\perm[0:0] \rb64_40 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $2\perm[0:0] \rb64_41 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $2\perm[0:0] \rb64_42 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $2\perm[0:0] \rb64_43 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $2\perm[0:0] \rb64_44 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $2\perm[0:0] \rb64_45 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $2\perm[0:0] \rb64_46 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $2\perm[0:0] \rb64_47 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $2\perm[0:0] \rb64_48 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $2\perm[0:0] \rb64_49 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $2\perm[0:0] \rb64_50 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $2\perm[0:0] \rb64_51 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $2\perm[0:0] \rb64_52 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $2\perm[0:0] \rb64_53 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $2\perm[0:0] \rb64_54 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $2\perm[0:0] \rb64_55 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $2\perm[0:0] \rb64_56 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $2\perm[0:0] \rb64_57 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $2\perm[0:0] \rb64_58 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $2\perm[0:0] \rb64_59 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $2\perm[0:0] \rb64_60 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $2\perm[0:0] \rb64_61 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $2\perm[0:0] \rb64_62 + attribute \src "libresoc.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $2\perm[0:0] \rb64_63 + case + assign $2\perm[0:0] 1'0 + end + case + assign $1\perm[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\perm[1:1] $4\perm[1:1] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_1 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $4\perm[1:1] \rb64_0 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $4\perm[1:1] \rb64_1 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $4\perm[1:1] \rb64_2 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $4\perm[1:1] \rb64_3 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $4\perm[1:1] \rb64_4 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $4\perm[1:1] \rb64_5 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $4\perm[1:1] \rb64_6 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $4\perm[1:1] \rb64_7 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $4\perm[1:1] \rb64_8 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $4\perm[1:1] \rb64_9 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $4\perm[1:1] \rb64_10 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $4\perm[1:1] \rb64_11 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $4\perm[1:1] \rb64_12 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $4\perm[1:1] \rb64_13 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $4\perm[1:1] \rb64_14 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $4\perm[1:1] \rb64_15 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $4\perm[1:1] \rb64_16 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $4\perm[1:1] \rb64_17 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $4\perm[1:1] \rb64_18 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $4\perm[1:1] \rb64_19 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $4\perm[1:1] \rb64_20 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $4\perm[1:1] \rb64_21 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $4\perm[1:1] \rb64_22 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $4\perm[1:1] \rb64_23 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $4\perm[1:1] \rb64_24 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $4\perm[1:1] \rb64_25 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $4\perm[1:1] \rb64_26 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $4\perm[1:1] \rb64_27 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $4\perm[1:1] \rb64_28 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $4\perm[1:1] \rb64_29 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $4\perm[1:1] \rb64_30 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $4\perm[1:1] \rb64_31 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $4\perm[1:1] \rb64_32 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $4\perm[1:1] \rb64_33 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $4\perm[1:1] \rb64_34 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $4\perm[1:1] \rb64_35 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $4\perm[1:1] \rb64_36 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $4\perm[1:1] \rb64_37 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $4\perm[1:1] \rb64_38 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $4\perm[1:1] \rb64_39 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $4\perm[1:1] \rb64_40 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $4\perm[1:1] \rb64_41 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $4\perm[1:1] \rb64_42 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $4\perm[1:1] \rb64_43 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $4\perm[1:1] \rb64_44 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $4\perm[1:1] \rb64_45 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $4\perm[1:1] \rb64_46 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $4\perm[1:1] \rb64_47 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $4\perm[1:1] \rb64_48 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $4\perm[1:1] \rb64_49 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $4\perm[1:1] \rb64_50 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $4\perm[1:1] \rb64_51 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $4\perm[1:1] \rb64_52 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $4\perm[1:1] \rb64_53 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $4\perm[1:1] \rb64_54 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $4\perm[1:1] \rb64_55 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $4\perm[1:1] \rb64_56 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $4\perm[1:1] \rb64_57 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $4\perm[1:1] \rb64_58 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $4\perm[1:1] \rb64_59 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $4\perm[1:1] \rb64_60 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $4\perm[1:1] \rb64_61 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $4\perm[1:1] \rb64_62 + attribute \src "libresoc.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $4\perm[1:1] \rb64_63 + case + assign $4\perm[1:1] 1'0 + end + case + assign $3\perm[1:1] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\perm[2:2] $6\perm[2:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_2 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $6\perm[2:2] \rb64_0 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $6\perm[2:2] \rb64_1 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $6\perm[2:2] \rb64_2 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $6\perm[2:2] \rb64_3 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $6\perm[2:2] \rb64_4 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $6\perm[2:2] \rb64_5 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $6\perm[2:2] \rb64_6 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $6\perm[2:2] \rb64_7 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $6\perm[2:2] \rb64_8 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $6\perm[2:2] \rb64_9 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $6\perm[2:2] \rb64_10 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $6\perm[2:2] \rb64_11 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $6\perm[2:2] \rb64_12 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $6\perm[2:2] \rb64_13 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $6\perm[2:2] \rb64_14 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $6\perm[2:2] \rb64_15 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $6\perm[2:2] \rb64_16 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $6\perm[2:2] \rb64_17 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $6\perm[2:2] \rb64_18 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $6\perm[2:2] \rb64_19 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $6\perm[2:2] \rb64_20 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $6\perm[2:2] \rb64_21 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $6\perm[2:2] \rb64_22 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $6\perm[2:2] \rb64_23 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $6\perm[2:2] \rb64_24 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $6\perm[2:2] \rb64_25 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $6\perm[2:2] \rb64_26 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $6\perm[2:2] \rb64_27 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $6\perm[2:2] \rb64_28 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $6\perm[2:2] \rb64_29 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $6\perm[2:2] \rb64_30 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $6\perm[2:2] \rb64_31 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $6\perm[2:2] \rb64_32 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $6\perm[2:2] \rb64_33 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $6\perm[2:2] \rb64_34 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $6\perm[2:2] \rb64_35 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $6\perm[2:2] \rb64_36 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $6\perm[2:2] \rb64_37 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $6\perm[2:2] \rb64_38 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $6\perm[2:2] \rb64_39 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $6\perm[2:2] \rb64_40 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $6\perm[2:2] \rb64_41 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $6\perm[2:2] \rb64_42 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $6\perm[2:2] \rb64_43 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $6\perm[2:2] \rb64_44 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $6\perm[2:2] \rb64_45 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $6\perm[2:2] \rb64_46 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $6\perm[2:2] \rb64_47 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $6\perm[2:2] \rb64_48 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $6\perm[2:2] \rb64_49 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $6\perm[2:2] \rb64_50 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $6\perm[2:2] \rb64_51 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $6\perm[2:2] \rb64_52 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $6\perm[2:2] \rb64_53 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $6\perm[2:2] \rb64_54 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $6\perm[2:2] \rb64_55 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $6\perm[2:2] \rb64_56 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $6\perm[2:2] \rb64_57 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $6\perm[2:2] \rb64_58 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $6\perm[2:2] \rb64_59 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $6\perm[2:2] \rb64_60 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $6\perm[2:2] \rb64_61 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $6\perm[2:2] \rb64_62 + attribute \src "libresoc.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $6\perm[2:2] \rb64_63 + case + assign $6\perm[2:2] 1'0 + end + case + assign $5\perm[2:2] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\perm[3:3] $8\perm[3:3] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_3 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $8\perm[3:3] \rb64_0 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $8\perm[3:3] \rb64_1 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $8\perm[3:3] \rb64_2 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $8\perm[3:3] \rb64_3 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $8\perm[3:3] \rb64_4 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $8\perm[3:3] \rb64_5 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $8\perm[3:3] \rb64_6 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $8\perm[3:3] \rb64_7 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $8\perm[3:3] \rb64_8 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $8\perm[3:3] \rb64_9 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $8\perm[3:3] \rb64_10 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $8\perm[3:3] \rb64_11 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $8\perm[3:3] \rb64_12 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $8\perm[3:3] \rb64_13 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $8\perm[3:3] \rb64_14 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $8\perm[3:3] \rb64_15 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $8\perm[3:3] \rb64_16 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $8\perm[3:3] \rb64_17 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $8\perm[3:3] \rb64_18 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $8\perm[3:3] \rb64_19 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $8\perm[3:3] \rb64_20 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $8\perm[3:3] \rb64_21 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $8\perm[3:3] \rb64_22 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $8\perm[3:3] \rb64_23 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $8\perm[3:3] \rb64_24 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $8\perm[3:3] \rb64_25 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $8\perm[3:3] \rb64_26 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $8\perm[3:3] \rb64_27 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $8\perm[3:3] \rb64_28 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $8\perm[3:3] \rb64_29 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $8\perm[3:3] \rb64_30 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $8\perm[3:3] \rb64_31 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $8\perm[3:3] \rb64_32 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $8\perm[3:3] \rb64_33 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $8\perm[3:3] \rb64_34 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $8\perm[3:3] \rb64_35 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $8\perm[3:3] \rb64_36 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $8\perm[3:3] \rb64_37 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $8\perm[3:3] \rb64_38 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $8\perm[3:3] \rb64_39 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $8\perm[3:3] \rb64_40 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $8\perm[3:3] \rb64_41 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $8\perm[3:3] \rb64_42 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $8\perm[3:3] \rb64_43 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $8\perm[3:3] \rb64_44 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $8\perm[3:3] \rb64_45 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $8\perm[3:3] \rb64_46 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $8\perm[3:3] \rb64_47 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $8\perm[3:3] \rb64_48 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $8\perm[3:3] \rb64_49 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $8\perm[3:3] \rb64_50 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $8\perm[3:3] \rb64_51 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $8\perm[3:3] \rb64_52 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $8\perm[3:3] \rb64_53 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $8\perm[3:3] \rb64_54 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $8\perm[3:3] \rb64_55 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $8\perm[3:3] \rb64_56 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $8\perm[3:3] \rb64_57 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $8\perm[3:3] \rb64_58 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $8\perm[3:3] \rb64_59 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $8\perm[3:3] \rb64_60 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $8\perm[3:3] \rb64_61 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $8\perm[3:3] \rb64_62 + attribute \src "libresoc.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $8\perm[3:3] \rb64_63 + case + assign $8\perm[3:3] 1'0 + end + case + assign $7\perm[3:3] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\perm[4:4] $10\perm[4:4] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_4 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $10\perm[4:4] \rb64_0 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $10\perm[4:4] \rb64_1 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $10\perm[4:4] \rb64_2 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $10\perm[4:4] \rb64_3 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $10\perm[4:4] \rb64_4 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $10\perm[4:4] \rb64_5 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $10\perm[4:4] \rb64_6 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $10\perm[4:4] \rb64_7 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $10\perm[4:4] \rb64_8 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $10\perm[4:4] \rb64_9 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $10\perm[4:4] \rb64_10 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $10\perm[4:4] \rb64_11 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $10\perm[4:4] \rb64_12 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $10\perm[4:4] \rb64_13 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $10\perm[4:4] \rb64_14 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $10\perm[4:4] \rb64_15 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $10\perm[4:4] \rb64_16 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $10\perm[4:4] \rb64_17 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $10\perm[4:4] \rb64_18 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $10\perm[4:4] \rb64_19 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $10\perm[4:4] \rb64_20 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $10\perm[4:4] \rb64_21 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $10\perm[4:4] \rb64_22 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $10\perm[4:4] \rb64_23 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $10\perm[4:4] \rb64_24 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $10\perm[4:4] \rb64_25 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $10\perm[4:4] \rb64_26 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $10\perm[4:4] \rb64_27 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $10\perm[4:4] \rb64_28 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $10\perm[4:4] \rb64_29 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $10\perm[4:4] \rb64_30 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $10\perm[4:4] \rb64_31 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $10\perm[4:4] \rb64_32 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $10\perm[4:4] \rb64_33 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $10\perm[4:4] \rb64_34 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $10\perm[4:4] \rb64_35 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $10\perm[4:4] \rb64_36 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $10\perm[4:4] \rb64_37 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $10\perm[4:4] \rb64_38 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $10\perm[4:4] \rb64_39 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $10\perm[4:4] \rb64_40 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $10\perm[4:4] \rb64_41 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $10\perm[4:4] \rb64_42 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $10\perm[4:4] \rb64_43 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $10\perm[4:4] \rb64_44 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $10\perm[4:4] \rb64_45 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $10\perm[4:4] \rb64_46 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $10\perm[4:4] \rb64_47 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $10\perm[4:4] \rb64_48 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $10\perm[4:4] \rb64_49 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $10\perm[4:4] \rb64_50 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $10\perm[4:4] \rb64_51 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $10\perm[4:4] \rb64_52 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $10\perm[4:4] \rb64_53 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $10\perm[4:4] \rb64_54 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $10\perm[4:4] \rb64_55 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $10\perm[4:4] \rb64_56 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $10\perm[4:4] \rb64_57 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $10\perm[4:4] \rb64_58 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $10\perm[4:4] \rb64_59 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $10\perm[4:4] \rb64_60 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $10\perm[4:4] \rb64_61 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $10\perm[4:4] \rb64_62 + attribute \src "libresoc.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $10\perm[4:4] \rb64_63 + case + assign $10\perm[4:4] 1'0 + end + case + assign $9\perm[4:4] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$11 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $11\perm[5:5] $12\perm[5:5] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_5 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $12\perm[5:5] \rb64_0 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $12\perm[5:5] \rb64_1 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $12\perm[5:5] \rb64_2 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $12\perm[5:5] \rb64_3 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $12\perm[5:5] \rb64_4 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $12\perm[5:5] \rb64_5 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $12\perm[5:5] \rb64_6 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $12\perm[5:5] \rb64_7 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $12\perm[5:5] \rb64_8 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $12\perm[5:5] \rb64_9 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $12\perm[5:5] \rb64_10 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $12\perm[5:5] \rb64_11 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $12\perm[5:5] \rb64_12 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $12\perm[5:5] \rb64_13 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $12\perm[5:5] \rb64_14 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $12\perm[5:5] \rb64_15 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $12\perm[5:5] \rb64_16 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $12\perm[5:5] \rb64_17 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $12\perm[5:5] \rb64_18 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $12\perm[5:5] \rb64_19 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $12\perm[5:5] \rb64_20 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $12\perm[5:5] \rb64_21 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $12\perm[5:5] \rb64_22 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $12\perm[5:5] \rb64_23 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $12\perm[5:5] \rb64_24 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $12\perm[5:5] \rb64_25 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $12\perm[5:5] \rb64_26 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $12\perm[5:5] \rb64_27 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $12\perm[5:5] \rb64_28 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $12\perm[5:5] \rb64_29 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $12\perm[5:5] \rb64_30 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $12\perm[5:5] \rb64_31 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $12\perm[5:5] \rb64_32 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $12\perm[5:5] \rb64_33 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $12\perm[5:5] \rb64_34 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $12\perm[5:5] \rb64_35 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $12\perm[5:5] \rb64_36 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $12\perm[5:5] \rb64_37 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $12\perm[5:5] \rb64_38 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $12\perm[5:5] \rb64_39 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $12\perm[5:5] \rb64_40 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $12\perm[5:5] \rb64_41 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $12\perm[5:5] \rb64_42 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $12\perm[5:5] \rb64_43 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $12\perm[5:5] \rb64_44 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $12\perm[5:5] \rb64_45 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $12\perm[5:5] \rb64_46 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $12\perm[5:5] \rb64_47 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $12\perm[5:5] \rb64_48 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $12\perm[5:5] \rb64_49 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $12\perm[5:5] \rb64_50 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $12\perm[5:5] \rb64_51 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $12\perm[5:5] \rb64_52 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $12\perm[5:5] \rb64_53 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $12\perm[5:5] \rb64_54 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $12\perm[5:5] \rb64_55 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $12\perm[5:5] \rb64_56 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $12\perm[5:5] \rb64_57 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $12\perm[5:5] \rb64_58 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $12\perm[5:5] \rb64_59 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $12\perm[5:5] \rb64_60 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $12\perm[5:5] \rb64_61 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $12\perm[5:5] \rb64_62 + attribute \src "libresoc.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $12\perm[5:5] \rb64_63 + case + assign $12\perm[5:5] 1'0 + end + case + assign $11\perm[5:5] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $13\perm[6:6] $14\perm[6:6] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_6 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $14\perm[6:6] \rb64_0 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $14\perm[6:6] \rb64_1 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $14\perm[6:6] \rb64_2 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $14\perm[6:6] \rb64_3 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $14\perm[6:6] \rb64_4 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $14\perm[6:6] \rb64_5 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $14\perm[6:6] \rb64_6 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $14\perm[6:6] \rb64_7 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $14\perm[6:6] \rb64_8 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $14\perm[6:6] \rb64_9 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $14\perm[6:6] \rb64_10 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $14\perm[6:6] \rb64_11 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $14\perm[6:6] \rb64_12 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $14\perm[6:6] \rb64_13 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $14\perm[6:6] \rb64_14 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $14\perm[6:6] \rb64_15 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $14\perm[6:6] \rb64_16 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $14\perm[6:6] \rb64_17 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $14\perm[6:6] \rb64_18 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $14\perm[6:6] \rb64_19 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $14\perm[6:6] \rb64_20 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $14\perm[6:6] \rb64_21 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $14\perm[6:6] \rb64_22 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $14\perm[6:6] \rb64_23 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $14\perm[6:6] \rb64_24 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $14\perm[6:6] \rb64_25 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $14\perm[6:6] \rb64_26 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $14\perm[6:6] \rb64_27 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $14\perm[6:6] \rb64_28 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $14\perm[6:6] \rb64_29 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $14\perm[6:6] \rb64_30 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $14\perm[6:6] \rb64_31 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $14\perm[6:6] \rb64_32 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $14\perm[6:6] \rb64_33 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $14\perm[6:6] \rb64_34 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $14\perm[6:6] \rb64_35 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $14\perm[6:6] \rb64_36 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $14\perm[6:6] \rb64_37 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $14\perm[6:6] \rb64_38 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $14\perm[6:6] \rb64_39 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $14\perm[6:6] \rb64_40 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $14\perm[6:6] \rb64_41 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $14\perm[6:6] \rb64_42 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $14\perm[6:6] \rb64_43 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $14\perm[6:6] \rb64_44 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $14\perm[6:6] \rb64_45 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $14\perm[6:6] \rb64_46 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $14\perm[6:6] \rb64_47 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $14\perm[6:6] \rb64_48 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $14\perm[6:6] \rb64_49 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $14\perm[6:6] \rb64_50 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $14\perm[6:6] \rb64_51 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $14\perm[6:6] \rb64_52 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $14\perm[6:6] \rb64_53 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $14\perm[6:6] \rb64_54 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $14\perm[6:6] \rb64_55 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $14\perm[6:6] \rb64_56 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $14\perm[6:6] \rb64_57 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $14\perm[6:6] \rb64_58 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $14\perm[6:6] \rb64_59 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $14\perm[6:6] \rb64_60 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $14\perm[6:6] \rb64_61 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $14\perm[6:6] \rb64_62 + attribute \src "libresoc.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $14\perm[6:6] \rb64_63 + case + assign $14\perm[6:6] 1'0 + end + case + assign $13\perm[6:6] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $15\perm[7:7] $16\perm[7:7] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_7 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $16\perm[7:7] \rb64_0 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $16\perm[7:7] \rb64_1 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $16\perm[7:7] \rb64_2 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $16\perm[7:7] \rb64_3 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $16\perm[7:7] \rb64_4 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $16\perm[7:7] \rb64_5 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $16\perm[7:7] \rb64_6 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $16\perm[7:7] \rb64_7 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $16\perm[7:7] \rb64_8 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $16\perm[7:7] \rb64_9 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $16\perm[7:7] \rb64_10 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $16\perm[7:7] \rb64_11 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $16\perm[7:7] \rb64_12 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $16\perm[7:7] \rb64_13 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $16\perm[7:7] \rb64_14 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $16\perm[7:7] \rb64_15 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $16\perm[7:7] \rb64_16 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $16\perm[7:7] \rb64_17 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $16\perm[7:7] \rb64_18 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $16\perm[7:7] \rb64_19 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $16\perm[7:7] \rb64_20 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $16\perm[7:7] \rb64_21 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $16\perm[7:7] \rb64_22 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $16\perm[7:7] \rb64_23 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $16\perm[7:7] \rb64_24 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $16\perm[7:7] \rb64_25 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $16\perm[7:7] \rb64_26 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $16\perm[7:7] \rb64_27 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $16\perm[7:7] \rb64_28 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $16\perm[7:7] \rb64_29 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $16\perm[7:7] \rb64_30 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $16\perm[7:7] \rb64_31 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $16\perm[7:7] \rb64_32 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $16\perm[7:7] \rb64_33 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $16\perm[7:7] \rb64_34 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $16\perm[7:7] \rb64_35 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $16\perm[7:7] \rb64_36 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $16\perm[7:7] \rb64_37 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $16\perm[7:7] \rb64_38 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $16\perm[7:7] \rb64_39 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $16\perm[7:7] \rb64_40 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $16\perm[7:7] \rb64_41 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $16\perm[7:7] \rb64_42 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $16\perm[7:7] \rb64_43 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $16\perm[7:7] \rb64_44 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $16\perm[7:7] \rb64_45 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $16\perm[7:7] \rb64_46 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $16\perm[7:7] \rb64_47 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $16\perm[7:7] \rb64_48 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $16\perm[7:7] \rb64_49 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $16\perm[7:7] \rb64_50 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $16\perm[7:7] \rb64_51 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $16\perm[7:7] \rb64_52 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $16\perm[7:7] \rb64_53 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $16\perm[7:7] \rb64_54 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $16\perm[7:7] \rb64_55 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $16\perm[7:7] \rb64_56 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $16\perm[7:7] \rb64_57 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $16\perm[7:7] \rb64_58 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $16\perm[7:7] \rb64_59 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $16\perm[7:7] \rb64_60 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $16\perm[7:7] \rb64_61 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $16\perm[7:7] \rb64_62 + attribute \src "libresoc.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $16\perm[7:7] \rb64_63 + case + assign $16\perm[7:7] 1'0 + end + case + assign $15\perm[7:7] 1'0 + end + sync always + update \perm $0\perm[63:0] + end + connect \$9 $lt$libresoc.v:31840$1108_Y + connect \$11 $lt$libresoc.v:31841$1109_Y + connect \$13 $lt$libresoc.v:31842$1110_Y + connect \$15 $lt$libresoc.v:31843$1111_Y + connect \$1 $lt$libresoc.v:31844$1112_Y + connect \$3 $lt$libresoc.v:31845$1113_Y + connect \$5 $lt$libresoc.v:31846$1114_Y + connect \$7 $lt$libresoc.v:31847$1115_Y + connect \ra [7:0] \perm [7:0] + connect \ra [63:8] 56'00000000000000000000000000000000000000000000000000000000 + connect \idx_7 \rs [63:56] + connect \idx_6 \rs [55:48] + connect \idx_5 \rs [47:40] + connect \idx_4 \rs [39:32] + connect \idx_3 \rs [31:24] + connect \idx_2 \rs [23:16] + connect \idx_1 \rs [15:8] + connect \idx_0 \rs [7:0] + connect \rb64_63 \rb [0] + connect \rb64_62 \rb [1] + connect \rb64_61 \rb [2] + connect \rb64_60 \rb [3] + connect \rb64_59 \rb [4] + connect \rb64_58 \rb [5] + connect \rb64_57 \rb [6] + connect \rb64_56 \rb [7] + connect \rb64_55 \rb [8] + connect \rb64_54 \rb [9] + connect \rb64_53 \rb [10] + connect \rb64_52 \rb [11] + connect \rb64_51 \rb [12] + connect \rb64_50 \rb [13] + connect \rb64_49 \rb [14] + connect \rb64_48 \rb [15] + connect \rb64_47 \rb [16] + connect \rb64_46 \rb [17] + connect \rb64_45 \rb [18] + connect \rb64_44 \rb [19] + connect \rb64_43 \rb [20] + connect \rb64_42 \rb [21] + connect \rb64_41 \rb [22] + connect \rb64_40 \rb [23] + connect \rb64_39 \rb [24] + connect \rb64_38 \rb [25] + connect \rb64_37 \rb [26] + connect \rb64_36 \rb [27] + connect \rb64_35 \rb [28] + connect \rb64_34 \rb [29] + connect \rb64_33 \rb [30] + connect \rb64_32 \rb [31] + connect \rb64_31 \rb [32] + connect \rb64_30 \rb [33] + connect \rb64_29 \rb [34] + connect \rb64_28 \rb [35] + connect \rb64_27 \rb [36] + connect \rb64_26 \rb [37] + connect \rb64_25 \rb [38] + connect \rb64_24 \rb [39] + connect \rb64_23 \rb [40] + connect \rb64_22 \rb [41] + connect \rb64_21 \rb [42] + connect \rb64_20 \rb [43] + connect \rb64_19 \rb [44] + connect \rb64_18 \rb [45] + connect \rb64_17 \rb [46] + connect \rb64_16 \rb [47] + connect \rb64_15 \rb [48] + connect \rb64_14 \rb [49] + connect \rb64_13 \rb [50] + connect \rb64_12 \rb [51] + connect \rb64_11 \rb [52] + connect \rb64_10 \rb [53] + connect \rb64_9 \rb [54] + connect \rb64_8 \rb [55] + connect \rb64_7 \rb [56] + connect \rb64_6 \rb [57] + connect \rb64_5 \rb [58] + connect \rb64_4 \rb [59] + connect \rb64_3 \rb [60] + connect \rb64_2 \rb [61] + connect \rb64_1 \rb [62] + connect \rb64_0 \rb [63] +end +attribute \src "libresoc.v:33018.1-34067.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0" +attribute \generator "nMigen" +module \branch0 + attribute \src "libresoc.v:33684.3-33685.25" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:33859.3-33883.6" + wire width 64 $0\alu_branch0_br_op__cia$next[63:0]$1239 + attribute \src "libresoc.v:33644.3-33645.61" + wire width 64 $0\alu_branch0_br_op__cia[63:0] + attribute \src "libresoc.v:33859.3-33883.6" + wire width 12 $0\alu_branch0_br_op__fn_unit$next[11:0]$1240 + attribute \src "libresoc.v:33648.3-33649.69" + wire width 12 $0\alu_branch0_br_op__fn_unit[11:0] + attribute \src "libresoc.v:33859.3-33883.6" + wire width 64 $0\alu_branch0_br_op__imm_data__data$next[63:0]$1241 + attribute \src "libresoc.v:33652.3-33653.83" + wire width 64 $0\alu_branch0_br_op__imm_data__data[63:0] + attribute \src "libresoc.v:33859.3-33883.6" + wire $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1242 + attribute \src "libresoc.v:33654.3-33655.79" + wire $0\alu_branch0_br_op__imm_data__ok[0:0] + attribute \src "libresoc.v:33859.3-33883.6" + wire width 32 $0\alu_branch0_br_op__insn$next[31:0]$1243 + attribute \src "libresoc.v:33650.3-33651.63" + wire width 32 $0\alu_branch0_br_op__insn[31:0] + attribute \src "libresoc.v:33859.3-33883.6" + wire width 7 $0\alu_branch0_br_op__insn_type$next[6:0]$1244 + attribute \src "libresoc.v:33646.3-33647.73" + wire width 7 $0\alu_branch0_br_op__insn_type[6:0] + attribute \src "libresoc.v:33859.3-33883.6" + wire $0\alu_branch0_br_op__is_32bit$next[0:0]$1245 + attribute \src "libresoc.v:33658.3-33659.71" + wire $0\alu_branch0_br_op__is_32bit[0:0] + attribute \src "libresoc.v:33859.3-33883.6" + wire $0\alu_branch0_br_op__lk$next[0:0]$1246 + attribute \src "libresoc.v:33656.3-33657.59" + wire $0\alu_branch0_br_op__lk[0:0] + attribute \src "libresoc.v:33682.3-33683.43" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:33989.3-33997.6" + wire $0\alu_l_r_alu$next[0:0]$1294 + attribute \src "libresoc.v:33622.3-33623.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:33980.3-33988.6" + wire $0\alui_l_r_alui$next[0:0]$1291 + attribute \src "libresoc.v:33624.3-33625.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:33884.3-33905.6" + wire width 64 $0\data_r0__fast1$next[63:0]$1258 + attribute \src "libresoc.v:33640.3-33641.45" + wire width 64 $0\data_r0__fast1[63:0] + attribute \src "libresoc.v:33884.3-33905.6" + wire $0\data_r0__fast1_ok$next[0:0]$1259 + attribute \src "libresoc.v:33642.3-33643.51" + wire $0\data_r0__fast1_ok[0:0] + attribute \src "libresoc.v:33906.3-33927.6" + wire width 64 $0\data_r1__fast2$next[63:0]$1266 + attribute \src "libresoc.v:33636.3-33637.45" + wire width 64 $0\data_r1__fast2[63:0] + attribute \src "libresoc.v:33906.3-33927.6" + wire $0\data_r1__fast2_ok$next[0:0]$1267 + attribute \src "libresoc.v:33638.3-33639.51" + wire $0\data_r1__fast2_ok[0:0] + attribute \src "libresoc.v:33928.3-33949.6" + wire width 64 $0\data_r2__nia$next[63:0]$1274 + attribute \src "libresoc.v:33632.3-33633.41" + wire width 64 $0\data_r2__nia[63:0] + attribute \src "libresoc.v:33928.3-33949.6" + wire $0\data_r2__nia_ok$next[0:0]$1275 + attribute \src "libresoc.v:33634.3-33635.47" + wire $0\data_r2__nia_ok[0:0] + attribute \src "libresoc.v:33998.3-34007.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:34008.3-34017.6" + wire width 64 $0\dest2_o[63:0] + attribute \src "libresoc.v:34018.3-34027.6" + wire width 64 $0\dest3_o[63:0] + attribute \src "libresoc.v:33019.7-33019.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:33814.3-33822.6" + wire $0\opc_l_r_opc$next[0:0]$1224 + attribute \src "libresoc.v:33668.3-33669.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:33805.3-33813.6" + wire $0\opc_l_s_opc$next[0:0]$1221 + attribute \src "libresoc.v:33670.3-33671.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:34028.3-34036.6" + wire width 3 $0\prev_wr_go$next[2:0]$1300 + attribute \src "libresoc.v:33680.3-33681.37" + wire width 3 $0\prev_wr_go[2:0] + attribute \src "libresoc.v:33759.3-33768.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:33850.3-33858.6" + wire width 3 $0\req_l_r_req$next[2:0]$1236 + attribute \src "libresoc.v:33660.3-33661.39" + wire width 3 $0\req_l_r_req[2:0] + attribute \src "libresoc.v:33841.3-33849.6" + wire width 3 $0\req_l_s_req$next[2:0]$1233 + attribute \src "libresoc.v:33662.3-33663.39" + wire width 3 $0\req_l_s_req[2:0] + attribute \src "libresoc.v:33778.3-33786.6" + wire $0\rok_l_r_rdok$next[0:0]$1212 + attribute \src "libresoc.v:33676.3-33677.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:33769.3-33777.6" + wire $0\rok_l_s_rdok$next[0:0]$1209 + attribute \src "libresoc.v:33678.3-33679.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:33796.3-33804.6" + wire $0\rst_l_r_rst$next[0:0]$1218 + attribute \src "libresoc.v:33672.3-33673.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:33787.3-33795.6" + wire $0\rst_l_s_rst$next[0:0]$1215 + attribute \src "libresoc.v:33674.3-33675.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:33832.3-33840.6" + wire width 3 $0\src_l_r_src$next[2:0]$1230 + attribute \src "libresoc.v:33664.3-33665.39" + wire width 3 $0\src_l_r_src[2:0] + attribute \src "libresoc.v:33823.3-33831.6" + wire width 3 $0\src_l_s_src$next[2:0]$1227 + attribute \src "libresoc.v:33666.3-33667.39" + wire width 3 $0\src_l_s_src[2:0] + attribute \src "libresoc.v:33950.3-33959.6" + wire width 64 $0\src_r0$next[63:0]$1282 + attribute \src "libresoc.v:33630.3-33631.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:33960.3-33969.6" + wire width 64 $0\src_r1$next[63:0]$1285 + attribute \src "libresoc.v:33628.3-33629.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:33970.3-33979.6" + wire width 4 $0\src_r2$next[3:0]$1288 + attribute \src "libresoc.v:33626.3-33627.29" + wire width 4 $0\src_r2[3:0] + attribute \src "libresoc.v:33137.7-33137.24" + wire $1\all_rd_dly[0:0] + attribute \src "libresoc.v:33859.3-33883.6" + wire width 64 $1\alu_branch0_br_op__cia$next[63:0]$1247 + attribute \src "libresoc.v:33145.14-33145.59" + wire width 64 $1\alu_branch0_br_op__cia[63:0] + attribute \src "libresoc.v:33859.3-33883.6" + wire width 12 $1\alu_branch0_br_op__fn_unit$next[11:0]$1248 + attribute \src "libresoc.v:33162.14-33162.50" + wire width 12 $1\alu_branch0_br_op__fn_unit[11:0] + attribute \src "libresoc.v:33859.3-33883.6" + wire width 64 $1\alu_branch0_br_op__imm_data__data$next[63:0]$1249 + attribute \src "libresoc.v:33166.14-33166.70" + wire width 64 $1\alu_branch0_br_op__imm_data__data[63:0] + attribute \src "libresoc.v:33859.3-33883.6" + wire $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 + attribute \src "libresoc.v:33170.7-33170.45" + wire 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$not$libresoc.v:33584$1137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:33584$1137_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$libresoc.v:33590$1143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_branch0_n_ready_i + connect \Y $not$libresoc.v:33590$1143_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$libresoc.v:33605$1158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__rel_o + connect \Y $not$libresoc.v:33605$1158_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$libresoc.v:33619$1172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_branch0_br_op__imm_data__ok + connect \Y $not$libresoc.v:33619$1172_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$libresoc.v:33621$1174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rdmaskn_i + connect \Y $not$libresoc.v:33621$1174_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$libresoc.v:33588$1141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$33 + connect \B \$35 + connect \Y $or$libresoc.v:33588$1141_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$libresoc.v:33599$1152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:33599$1152_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$libresoc.v:33600$1153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:33600$1153_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$libresoc.v:33601$1154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:33601$1154_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$libresoc.v:33602$1155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:33602$1155_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:33606$1159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$libresoc.v:33606$1159_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:33616$1169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$6 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:33616$1169_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:33565$1118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $reduce_and$libresoc.v:33565$1118_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:33583$1136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$27 + connect \Y $reduce_or$libresoc.v:33583$1136_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:33586$1139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:33586$1139_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:33587$1140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:33587$1140_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:33610$1163 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_branch0_br_op__imm_data__ok + connect \Y $ternary$libresoc.v:33610$1163_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:33611$1164 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_branch0_br_op__imm_data__data + connect \S \alu_branch0_br_op__imm_data__ok + connect \Y $ternary$libresoc.v:33611$1164_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:33612$1165 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $ternary$libresoc.v:33612$1165_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:33613$1166 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $ternary$libresoc.v:33613$1166_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:33614$1167 + parameter \WIDTH 4 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:33614$1167_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:33686.15-33710.4" + cell \alu_branch0 \alu_branch0 + connect \br_op__cia \alu_branch0_br_op__cia + connect \br_op__fn_unit \alu_branch0_br_op__fn_unit + connect \br_op__imm_data__data \alu_branch0_br_op__imm_data__data + connect \br_op__imm_data__ok \alu_branch0_br_op__imm_data__ok + connect \br_op__insn \alu_branch0_br_op__insn + connect \br_op__insn_type \alu_branch0_br_op__insn_type + connect \br_op__is_32bit \alu_branch0_br_op__is_32bit + connect \br_op__lk \alu_branch0_br_op__lk + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \alu_branch0_cr_a + connect \fast1 \alu_branch0_fast1 + connect \fast1$1 \alu_branch0_fast1$1 + connect \fast1_ok \fast1_ok + connect \fast2 \alu_branch0_fast2 + connect \fast2$2 \alu_branch0_fast2$2 + connect \fast2_ok \fast2_ok + connect \n_ready_i \alu_branch0_n_ready_i + connect \n_valid_o \alu_branch0_n_valid_o + connect \nia \alu_branch0_nia + connect \nia_ok \nia_ok + connect \p_ready_o \alu_branch0_p_ready_o + connect \p_valid_i \alu_branch0_p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:33711.14-33717.4" + cell \alu_l$29 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:33718.15-33724.4" + cell \alui_l$28 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:33725.14-33731.4" + cell \opc_l$24 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:33732.14-33738.4" + cell \req_l$25 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:33739.14-33745.4" + cell \rok_l$27 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:33746.14-33751.4" + cell \rst_l$26 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:33752.14-33758.4" + cell \src_l$23 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "libresoc.v:33019.7-33019.20" + process $proc$libresoc.v:33019$1302 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:33137.7-33137.24" + process $proc$libresoc.v:33137$1303 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "libresoc.v:33145.14-33145.59" + process $proc$libresoc.v:33145$1304 + assign { } { } + assign $1\alu_branch0_br_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_branch0_br_op__cia $1\alu_branch0_br_op__cia[63:0] + end + attribute \src "libresoc.v:33162.14-33162.50" + process $proc$libresoc.v:33162$1305 + assign { } { } + assign $1\alu_branch0_br_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \alu_branch0_br_op__fn_unit $1\alu_branch0_br_op__fn_unit[11:0] + end + attribute \src "libresoc.v:33166.14-33166.70" + process $proc$libresoc.v:33166$1306 + assign { } { } + assign $1\alu_branch0_br_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_branch0_br_op__imm_data__data $1\alu_branch0_br_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:33170.7-33170.45" + process $proc$libresoc.v:33170$1307 + assign { } { } + assign $1\alu_branch0_br_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \alu_branch0_br_op__imm_data__ok $1\alu_branch0_br_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:33174.14-33174.45" + process $proc$libresoc.v:33174$1308 + assign { } { } + assign $1\alu_branch0_br_op__insn[31:0] 0 + sync always + sync init + update \alu_branch0_br_op__insn $1\alu_branch0_br_op__insn[31:0] + end + attribute \src "libresoc.v:33252.13-33252.49" + process $proc$libresoc.v:33252$1309 + assign { } { } + assign $1\alu_branch0_br_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_branch0_br_op__insn_type $1\alu_branch0_br_op__insn_type[6:0] + end + attribute \src "libresoc.v:33256.7-33256.41" + process $proc$libresoc.v:33256$1310 + assign { } { } + assign $1\alu_branch0_br_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_branch0_br_op__is_32bit $1\alu_branch0_br_op__is_32bit[0:0] + end + attribute \src "libresoc.v:33260.7-33260.35" + process $proc$libresoc.v:33260$1311 + assign { } { } + assign $1\alu_branch0_br_op__lk[0:0] 1'0 + sync always + sync init + update \alu_branch0_br_op__lk $1\alu_branch0_br_op__lk[0:0] + end + attribute \src "libresoc.v:33286.7-33286.26" + process $proc$libresoc.v:33286$1312 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "libresoc.v:33294.7-33294.25" + process $proc$libresoc.v:33294$1313 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:33306.7-33306.27" + process $proc$libresoc.v:33306$1314 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:33338.14-33338.51" + process $proc$libresoc.v:33338$1315 + assign { } { } + assign $1\data_r0__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__fast1 $1\data_r0__fast1[63:0] + end + attribute \src "libresoc.v:33342.7-33342.31" + process $proc$libresoc.v:33342$1316 + assign { } { } + assign $1\data_r0__fast1_ok[0:0] 1'0 + sync always + sync init + update \data_r0__fast1_ok $1\data_r0__fast1_ok[0:0] + end + attribute \src "libresoc.v:33346.14-33346.51" + process $proc$libresoc.v:33346$1317 + assign { } { } + assign $1\data_r1__fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r1__fast2 $1\data_r1__fast2[63:0] + end + attribute \src "libresoc.v:33350.7-33350.31" + process $proc$libresoc.v:33350$1318 + assign { } { } + assign $1\data_r1__fast2_ok[0:0] 1'0 + sync always + sync init + update \data_r1__fast2_ok $1\data_r1__fast2_ok[0:0] + end + attribute \src "libresoc.v:33354.14-33354.49" + process $proc$libresoc.v:33354$1319 + assign { } { } + assign $1\data_r2__nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r2__nia $1\data_r2__nia[63:0] + end + attribute \src "libresoc.v:33358.7-33358.29" + process $proc$libresoc.v:33358$1320 + assign { } { } + assign $1\data_r2__nia_ok[0:0] 1'0 + sync always + sync init + update \data_r2__nia_ok $1\data_r2__nia_ok[0:0] + end + attribute \src "libresoc.v:33379.7-33379.25" + process $proc$libresoc.v:33379$1321 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:33383.7-33383.25" + process $proc$libresoc.v:33383$1322 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:33490.13-33490.30" + process $proc$libresoc.v:33490$1323 + assign { } { } + assign $1\prev_wr_go[2:0] 3'000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[2:0] + end + attribute \src "libresoc.v:33498.13-33498.31" + process $proc$libresoc.v:33498$1324 + assign { } { } + assign $1\req_l_r_req[2:0] 3'111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[2:0] + end + attribute \src "libresoc.v:33502.13-33502.31" + process $proc$libresoc.v:33502$1325 + assign { } { } + assign $1\req_l_s_req[2:0] 3'000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[2:0] + end + attribute \src "libresoc.v:33514.7-33514.26" + process $proc$libresoc.v:33514$1326 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:33518.7-33518.26" + process $proc$libresoc.v:33518$1327 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:33522.7-33522.25" + process $proc$libresoc.v:33522$1328 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:33526.7-33526.25" + process $proc$libresoc.v:33526$1329 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:33540.13-33540.31" + process $proc$libresoc.v:33540$1330 + assign { } { } + assign $1\src_l_r_src[2:0] 3'111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[2:0] + end + attribute \src "libresoc.v:33544.13-33544.31" + process $proc$libresoc.v:33544$1331 + assign { } { } + assign $1\src_l_s_src[2:0] 3'000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[2:0] + end + attribute \src "libresoc.v:33550.14-33550.43" + process $proc$libresoc.v:33550$1332 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:33554.14-33554.43" + process $proc$libresoc.v:33554$1333 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:33558.13-33558.26" + process $proc$libresoc.v:33558$1334 + assign { } { } + assign $1\src_r2[3:0] 4'0000 + sync always + sync init + update \src_r2 $1\src_r2[3:0] + end + attribute \src "libresoc.v:33622.3-33623.39" + process $proc$libresoc.v:33622$1175 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:33624.3-33625.43" + process $proc$libresoc.v:33624$1176 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:33626.3-33627.29" + process $proc$libresoc.v:33626$1177 + assign { } { } + assign $0\src_r2[3:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[3:0] + end + attribute \src "libresoc.v:33628.3-33629.29" + process $proc$libresoc.v:33628$1178 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:33630.3-33631.29" + process $proc$libresoc.v:33630$1179 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:33632.3-33633.41" + process $proc$libresoc.v:33632$1180 + assign { } { } + assign $0\data_r2__nia[63:0] \data_r2__nia$next + sync posedge \coresync_clk + update \data_r2__nia $0\data_r2__nia[63:0] + end + attribute \src "libresoc.v:33634.3-33635.47" + process $proc$libresoc.v:33634$1181 + assign { } { } + assign $0\data_r2__nia_ok[0:0] \data_r2__nia_ok$next + sync posedge \coresync_clk + update \data_r2__nia_ok $0\data_r2__nia_ok[0:0] + end + attribute \src "libresoc.v:33636.3-33637.45" + process $proc$libresoc.v:33636$1182 + assign { } { } + assign $0\data_r1__fast2[63:0] \data_r1__fast2$next + sync posedge \coresync_clk + update \data_r1__fast2 $0\data_r1__fast2[63:0] + end + attribute \src "libresoc.v:33638.3-33639.51" + process $proc$libresoc.v:33638$1183 + assign { } { } + assign $0\data_r1__fast2_ok[0:0] \data_r1__fast2_ok$next + sync posedge \coresync_clk + update \data_r1__fast2_ok $0\data_r1__fast2_ok[0:0] + end + attribute \src "libresoc.v:33640.3-33641.45" + process $proc$libresoc.v:33640$1184 + assign { } { } + assign $0\data_r0__fast1[63:0] \data_r0__fast1$next + sync posedge \coresync_clk + update \data_r0__fast1 $0\data_r0__fast1[63:0] + end + attribute \src "libresoc.v:33642.3-33643.51" + process $proc$libresoc.v:33642$1185 + assign { } { } + assign $0\data_r0__fast1_ok[0:0] \data_r0__fast1_ok$next + sync posedge \coresync_clk + update \data_r0__fast1_ok $0\data_r0__fast1_ok[0:0] + end + attribute \src "libresoc.v:33644.3-33645.61" + process $proc$libresoc.v:33644$1186 + assign { } { } + assign $0\alu_branch0_br_op__cia[63:0] \alu_branch0_br_op__cia$next + sync posedge \coresync_clk + update \alu_branch0_br_op__cia $0\alu_branch0_br_op__cia[63:0] + end + attribute \src "libresoc.v:33646.3-33647.73" + process $proc$libresoc.v:33646$1187 + assign { } { } + assign $0\alu_branch0_br_op__insn_type[6:0] \alu_branch0_br_op__insn_type$next + sync posedge \coresync_clk + update \alu_branch0_br_op__insn_type $0\alu_branch0_br_op__insn_type[6:0] + end + attribute \src "libresoc.v:33648.3-33649.69" + process $proc$libresoc.v:33648$1188 + assign { } { } + assign $0\alu_branch0_br_op__fn_unit[11:0] \alu_branch0_br_op__fn_unit$next + sync posedge \coresync_clk + update \alu_branch0_br_op__fn_unit $0\alu_branch0_br_op__fn_unit[11:0] + end + attribute \src "libresoc.v:33650.3-33651.63" + process $proc$libresoc.v:33650$1189 + assign { } { } + assign $0\alu_branch0_br_op__insn[31:0] \alu_branch0_br_op__insn$next + sync posedge \coresync_clk + update \alu_branch0_br_op__insn $0\alu_branch0_br_op__insn[31:0] + end + attribute \src "libresoc.v:33652.3-33653.83" + process $proc$libresoc.v:33652$1190 + assign { } { } + assign $0\alu_branch0_br_op__imm_data__data[63:0] \alu_branch0_br_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_branch0_br_op__imm_data__data $0\alu_branch0_br_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:33654.3-33655.79" + process $proc$libresoc.v:33654$1191 + assign { } { } + assign $0\alu_branch0_br_op__imm_data__ok[0:0] \alu_branch0_br_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_branch0_br_op__imm_data__ok $0\alu_branch0_br_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:33656.3-33657.59" + process $proc$libresoc.v:33656$1192 + assign { } { } + assign $0\alu_branch0_br_op__lk[0:0] \alu_branch0_br_op__lk$next + sync posedge \coresync_clk + update \alu_branch0_br_op__lk $0\alu_branch0_br_op__lk[0:0] + end + attribute \src "libresoc.v:33658.3-33659.71" + process $proc$libresoc.v:33658$1193 + assign { } { } + assign $0\alu_branch0_br_op__is_32bit[0:0] \alu_branch0_br_op__is_32bit$next + sync posedge \coresync_clk + update \alu_branch0_br_op__is_32bit $0\alu_branch0_br_op__is_32bit[0:0] + end + attribute \src "libresoc.v:33660.3-33661.39" + process $proc$libresoc.v:33660$1194 + assign { } { } + assign $0\req_l_r_req[2:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[2:0] + end + attribute \src "libresoc.v:33662.3-33663.39" + process $proc$libresoc.v:33662$1195 + assign { } { } + assign $0\req_l_s_req[2:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[2:0] + end + attribute \src "libresoc.v:33664.3-33665.39" + process $proc$libresoc.v:33664$1196 + assign { } { } + assign $0\src_l_r_src[2:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[2:0] + end + attribute \src "libresoc.v:33666.3-33667.39" + process $proc$libresoc.v:33666$1197 + assign { } { } + assign $0\src_l_s_src[2:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[2:0] + end + attribute \src "libresoc.v:33668.3-33669.39" + process $proc$libresoc.v:33668$1198 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:33670.3-33671.39" + process $proc$libresoc.v:33670$1199 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:33672.3-33673.39" + process $proc$libresoc.v:33672$1200 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:33674.3-33675.39" + process $proc$libresoc.v:33674$1201 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:33676.3-33677.41" + process $proc$libresoc.v:33676$1202 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:33678.3-33679.41" + process $proc$libresoc.v:33678$1203 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:33680.3-33681.37" + process $proc$libresoc.v:33680$1204 + assign { } { } + assign $0\prev_wr_go[2:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[2:0] + end + attribute \src "libresoc.v:33682.3-33683.43" + process $proc$libresoc.v:33682$1205 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_branch0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "libresoc.v:33684.3-33685.25" + process $proc$libresoc.v:33684$1206 + assign { } { } + assign $0\all_rd_dly[0:0] \$11 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "libresoc.v:33759.3-33768.6" + process $proc$libresoc.v:33759$1207 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:33760.5-33760.29" + switch \initial + attribute \src "libresoc.v:33760.9-33760.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$55 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$47 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "libresoc.v:33769.3-33777.6" + process $proc$libresoc.v:33769$1208 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$1209 $1\rok_l_s_rdok$next[0:0]$1210 + attribute \src "libresoc.v:33770.5-33770.29" + switch \initial + attribute \src "libresoc.v:33770.9-33770.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$1210 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$1210 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$1209 + end + attribute \src "libresoc.v:33778.3-33786.6" + process $proc$libresoc.v:33778$1211 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$1212 $1\rok_l_r_rdok$next[0:0]$1213 + attribute \src "libresoc.v:33779.5-33779.29" + switch \initial + attribute \src "libresoc.v:33779.9-33779.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$1213 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$1213 \$65 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$1212 + end + attribute \src "libresoc.v:33787.3-33795.6" + process $proc$libresoc.v:33787$1214 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$1215 $1\rst_l_s_rst$next[0:0]$1216 + attribute \src "libresoc.v:33788.5-33788.29" + switch \initial + attribute \src "libresoc.v:33788.9-33788.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$1216 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$1216 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$1215 + end + attribute \src "libresoc.v:33796.3-33804.6" + process $proc$libresoc.v:33796$1217 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$1218 $1\rst_l_r_rst$next[0:0]$1219 + attribute \src "libresoc.v:33797.5-33797.29" + switch \initial + attribute \src "libresoc.v:33797.9-33797.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$1219 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$1219 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$1218 + end + attribute \src "libresoc.v:33805.3-33813.6" + process $proc$libresoc.v:33805$1220 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$1221 $1\opc_l_s_opc$next[0:0]$1222 + attribute \src "libresoc.v:33806.5-33806.29" + switch \initial + attribute \src "libresoc.v:33806.9-33806.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$1222 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$1222 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$1221 + end + attribute \src "libresoc.v:33814.3-33822.6" + process $proc$libresoc.v:33814$1223 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$1224 $1\opc_l_r_opc$next[0:0]$1225 + attribute \src "libresoc.v:33815.5-33815.29" + switch \initial + attribute \src "libresoc.v:33815.9-33815.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$1225 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$1225 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$1224 + end + attribute \src "libresoc.v:33823.3-33831.6" + process $proc$libresoc.v:33823$1226 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[2:0]$1227 $1\src_l_s_src$next[2:0]$1228 + attribute \src "libresoc.v:33824.5-33824.29" + switch \initial + attribute \src "libresoc.v:33824.9-33824.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[2:0]$1228 3'000 + case + assign $1\src_l_s_src$next[2:0]$1228 { \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$1227 + end + attribute \src "libresoc.v:33832.3-33840.6" + process $proc$libresoc.v:33832$1229 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[2:0]$1230 $1\src_l_r_src$next[2:0]$1231 + attribute \src "libresoc.v:33833.5-33833.29" + switch \initial + attribute \src "libresoc.v:33833.9-33833.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[2:0]$1231 3'111 + case + assign $1\src_l_r_src$next[2:0]$1231 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$1230 + end + attribute \src "libresoc.v:33841.3-33849.6" + process $proc$libresoc.v:33841$1232 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[2:0]$1233 $1\req_l_s_req$next[2:0]$1234 + attribute \src "libresoc.v:33842.5-33842.29" + switch \initial + attribute \src "libresoc.v:33842.9-33842.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[2:0]$1234 3'000 + case + assign $1\req_l_s_req$next[2:0]$1234 \$67 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[2:0]$1233 + end + attribute \src "libresoc.v:33850.3-33858.6" + process $proc$libresoc.v:33850$1235 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[2:0]$1236 $1\req_l_r_req$next[2:0]$1237 + attribute \src "libresoc.v:33851.5-33851.29" + switch \initial + attribute \src "libresoc.v:33851.9-33851.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[2:0]$1237 3'111 + case + assign $1\req_l_r_req$next[2:0]$1237 \$69 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[2:0]$1236 + end + attribute \src "libresoc.v:33859.3-33883.6" + process $proc$libresoc.v:33859$1238 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_branch0_br_op__cia$next[63:0]$1239 $1\alu_branch0_br_op__cia$next[63:0]$1247 + assign $0\alu_branch0_br_op__fn_unit$next[11:0]$1240 $1\alu_branch0_br_op__fn_unit$next[11:0]$1248 + assign { } { } + assign { } { } + assign $0\alu_branch0_br_op__insn$next[31:0]$1243 $1\alu_branch0_br_op__insn$next[31:0]$1251 + assign $0\alu_branch0_br_op__insn_type$next[6:0]$1244 $1\alu_branch0_br_op__insn_type$next[6:0]$1252 + assign $0\alu_branch0_br_op__is_32bit$next[0:0]$1245 $1\alu_branch0_br_op__is_32bit$next[0:0]$1253 + assign $0\alu_branch0_br_op__lk$next[0:0]$1246 $1\alu_branch0_br_op__lk$next[0:0]$1254 + assign $0\alu_branch0_br_op__imm_data__data$next[63:0]$1241 $2\alu_branch0_br_op__imm_data__data$next[63:0]$1255 + assign $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1242 $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1256 + attribute \src "libresoc.v:33860.5-33860.29" + switch \initial + attribute \src "libresoc.v:33860.9-33860.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_branch0_br_op__is_32bit$next[0:0]$1253 $1\alu_branch0_br_op__lk$next[0:0]$1254 $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 $1\alu_branch0_br_op__imm_data__data$next[63:0]$1249 $1\alu_branch0_br_op__insn$next[31:0]$1251 $1\alu_branch0_br_op__fn_unit$next[11:0]$1248 $1\alu_branch0_br_op__insn_type$next[6:0]$1252 $1\alu_branch0_br_op__cia$next[63:0]$1247 } { \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__lk \oper_i_alu_branch0__imm_data__ok \oper_i_alu_branch0__imm_data__data \oper_i_alu_branch0__insn \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__cia } + case + assign $1\alu_branch0_br_op__cia$next[63:0]$1247 \alu_branch0_br_op__cia + assign $1\alu_branch0_br_op__fn_unit$next[11:0]$1248 \alu_branch0_br_op__fn_unit + assign $1\alu_branch0_br_op__imm_data__data$next[63:0]$1249 \alu_branch0_br_op__imm_data__data + assign $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 \alu_branch0_br_op__imm_data__ok + assign $1\alu_branch0_br_op__insn$next[31:0]$1251 \alu_branch0_br_op__insn + assign $1\alu_branch0_br_op__insn_type$next[6:0]$1252 \alu_branch0_br_op__insn_type + assign $1\alu_branch0_br_op__is_32bit$next[0:0]$1253 \alu_branch0_br_op__is_32bit + assign $1\alu_branch0_br_op__lk$next[0:0]$1254 \alu_branch0_br_op__lk + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $2\alu_branch0_br_op__imm_data__data$next[63:0]$1255 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1256 1'0 + case + assign $2\alu_branch0_br_op__imm_data__data$next[63:0]$1255 $1\alu_branch0_br_op__imm_data__data$next[63:0]$1249 + assign $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1256 $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 + end + sync always + update \alu_branch0_br_op__cia$next $0\alu_branch0_br_op__cia$next[63:0]$1239 + update \alu_branch0_br_op__fn_unit$next $0\alu_branch0_br_op__fn_unit$next[11:0]$1240 + update \alu_branch0_br_op__imm_data__data$next $0\alu_branch0_br_op__imm_data__data$next[63:0]$1241 + update \alu_branch0_br_op__imm_data__ok$next $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1242 + update \alu_branch0_br_op__insn$next $0\alu_branch0_br_op__insn$next[31:0]$1243 + update \alu_branch0_br_op__insn_type$next $0\alu_branch0_br_op__insn_type$next[6:0]$1244 + update \alu_branch0_br_op__is_32bit$next $0\alu_branch0_br_op__is_32bit$next[0:0]$1245 + update \alu_branch0_br_op__lk$next $0\alu_branch0_br_op__lk$next[0:0]$1246 + end + attribute \src "libresoc.v:33884.3-33905.6" + process $proc$libresoc.v:33884$1257 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__fast1$next[63:0]$1258 $2\data_r0__fast1$next[63:0]$1262 + assign { } { } + assign $0\data_r0__fast1_ok$next[0:0]$1259 $3\data_r0__fast1_ok$next[0:0]$1264 + attribute \src "libresoc.v:33885.5-33885.29" + switch \initial + attribute \src "libresoc.v:33885.9-33885.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__fast1_ok$next[0:0]$1261 $1\data_r0__fast1$next[63:0]$1260 } { \fast1_ok \alu_branch0_fast1 } + case + assign $1\data_r0__fast1$next[63:0]$1260 \data_r0__fast1 + assign $1\data_r0__fast1_ok$next[0:0]$1261 \data_r0__fast1_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__fast1_ok$next[0:0]$1263 $2\data_r0__fast1$next[63:0]$1262 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__fast1$next[63:0]$1262 $1\data_r0__fast1$next[63:0]$1260 + assign $2\data_r0__fast1_ok$next[0:0]$1263 $1\data_r0__fast1_ok$next[0:0]$1261 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__fast1_ok$next[0:0]$1264 1'0 + case + assign $3\data_r0__fast1_ok$next[0:0]$1264 $2\data_r0__fast1_ok$next[0:0]$1263 + end + sync always + update \data_r0__fast1$next $0\data_r0__fast1$next[63:0]$1258 + update \data_r0__fast1_ok$next $0\data_r0__fast1_ok$next[0:0]$1259 + end + attribute \src "libresoc.v:33906.3-33927.6" + process $proc$libresoc.v:33906$1265 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__fast2$next[63:0]$1266 $2\data_r1__fast2$next[63:0]$1270 + assign { } { } + assign $0\data_r1__fast2_ok$next[0:0]$1267 $3\data_r1__fast2_ok$next[0:0]$1272 + attribute \src "libresoc.v:33907.5-33907.29" + switch \initial + attribute \src "libresoc.v:33907.9-33907.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__fast2_ok$next[0:0]$1269 $1\data_r1__fast2$next[63:0]$1268 } { \fast2_ok \alu_branch0_fast2 } + case + assign $1\data_r1__fast2$next[63:0]$1268 \data_r1__fast2 + assign $1\data_r1__fast2_ok$next[0:0]$1269 \data_r1__fast2_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__fast2_ok$next[0:0]$1271 $2\data_r1__fast2$next[63:0]$1270 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r1__fast2$next[63:0]$1270 $1\data_r1__fast2$next[63:0]$1268 + assign $2\data_r1__fast2_ok$next[0:0]$1271 $1\data_r1__fast2_ok$next[0:0]$1269 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__fast2_ok$next[0:0]$1272 1'0 + case + assign $3\data_r1__fast2_ok$next[0:0]$1272 $2\data_r1__fast2_ok$next[0:0]$1271 + end + sync always + update \data_r1__fast2$next $0\data_r1__fast2$next[63:0]$1266 + update \data_r1__fast2_ok$next $0\data_r1__fast2_ok$next[0:0]$1267 + end + attribute \src "libresoc.v:33928.3-33949.6" + process $proc$libresoc.v:33928$1273 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__nia$next[63:0]$1274 $2\data_r2__nia$next[63:0]$1278 + assign { } { } + assign $0\data_r2__nia_ok$next[0:0]$1275 $3\data_r2__nia_ok$next[0:0]$1280 + attribute \src "libresoc.v:33929.5-33929.29" + switch \initial + attribute \src "libresoc.v:33929.9-33929.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__nia_ok$next[0:0]$1277 $1\data_r2__nia$next[63:0]$1276 } { \nia_ok \alu_branch0_nia } + case + assign $1\data_r2__nia$next[63:0]$1276 \data_r2__nia + assign $1\data_r2__nia_ok$next[0:0]$1277 \data_r2__nia_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__nia_ok$next[0:0]$1279 $2\data_r2__nia$next[63:0]$1278 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r2__nia$next[63:0]$1278 $1\data_r2__nia$next[63:0]$1276 + assign $2\data_r2__nia_ok$next[0:0]$1279 $1\data_r2__nia_ok$next[0:0]$1277 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__nia_ok$next[0:0]$1280 1'0 + case + assign $3\data_r2__nia_ok$next[0:0]$1280 $2\data_r2__nia_ok$next[0:0]$1279 + end + sync always + update \data_r2__nia$next $0\data_r2__nia$next[63:0]$1274 + update \data_r2__nia_ok$next $0\data_r2__nia_ok$next[0:0]$1275 + end + attribute \src "libresoc.v:33950.3-33959.6" + process $proc$libresoc.v:33950$1281 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$1282 $1\src_r0$next[63:0]$1283 + attribute \src "libresoc.v:33951.5-33951.29" + switch \initial + attribute \src "libresoc.v:33951.9-33951.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$1283 \src1_i + case + assign $1\src_r0$next[63:0]$1283 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$1282 + end + attribute \src "libresoc.v:33960.3-33969.6" + process $proc$libresoc.v:33960$1284 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$1285 $1\src_r1$next[63:0]$1286 + attribute \src "libresoc.v:33961.5-33961.29" + switch \initial + attribute \src "libresoc.v:33961.9-33961.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_sel + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$1286 \src_or_imm + case + assign $1\src_r1$next[63:0]$1286 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$1285 + end + attribute \src "libresoc.v:33970.3-33979.6" + process $proc$libresoc.v:33970$1287 + assign { } { } + assign { } { } + assign $0\src_r2$next[3:0]$1288 $1\src_r2$next[3:0]$1289 + attribute \src "libresoc.v:33971.5-33971.29" + switch \initial + attribute \src "libresoc.v:33971.9-33971.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[3:0]$1289 \src3_i + case + assign $1\src_r2$next[3:0]$1289 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[3:0]$1288 + end + attribute \src "libresoc.v:33980.3-33988.6" + process $proc$libresoc.v:33980$1290 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$1291 $1\alui_l_r_alui$next[0:0]$1292 + attribute \src "libresoc.v:33981.5-33981.29" + switch \initial + attribute \src "libresoc.v:33981.9-33981.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$1292 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$1292 \$87 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$1291 + end + attribute \src "libresoc.v:33989.3-33997.6" + process $proc$libresoc.v:33989$1293 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$1294 $1\alu_l_r_alu$next[0:0]$1295 + attribute \src "libresoc.v:33990.5-33990.29" + switch \initial + attribute \src "libresoc.v:33990.9-33990.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$1295 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$1295 \$89 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$1294 + end + attribute \src "libresoc.v:33998.3-34007.6" + process $proc$libresoc.v:33998$1296 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:33999.5-33999.29" + switch \initial + attribute \src "libresoc.v:33999.9-33999.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$111 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__fast1 + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "libresoc.v:34008.3-34017.6" + process $proc$libresoc.v:34008$1297 + assign { } { } + assign { } { } + assign $0\dest2_o[63:0] $1\dest2_o[63:0] + attribute \src "libresoc.v:34009.5-34009.29" + switch \initial + attribute \src "libresoc.v:34009.9-34009.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$113 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[63:0] \data_r1__fast2 + case + assign $1\dest2_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest2_o $0\dest2_o[63:0] + end + attribute \src "libresoc.v:34018.3-34027.6" + process $proc$libresoc.v:34018$1298 + assign { } { } + assign { } { } + assign $0\dest3_o[63:0] $1\dest3_o[63:0] + attribute \src "libresoc.v:34019.5-34019.29" + switch \initial + attribute \src "libresoc.v:34019.9-34019.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$115 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest3_o[63:0] \data_r2__nia + case + assign $1\dest3_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest3_o $0\dest3_o[63:0] + end + attribute \src "libresoc.v:34028.3-34036.6" + process $proc$libresoc.v:34028$1299 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[2:0]$1300 $1\prev_wr_go$next[2:0]$1301 + attribute \src "libresoc.v:34029.5-34029.29" + switch \initial + attribute \src "libresoc.v:34029.9-34029.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[2:0]$1301 3'000 + case + assign $1\prev_wr_go$next[2:0]$1301 \$21 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[2:0]$1300 + end + connect \$5 $reduce_and$libresoc.v:33565$1118_Y + connect \$99 $and$libresoc.v:33566$1119_Y + connect \$101 $and$libresoc.v:33567$1120_Y + connect \$103 $and$libresoc.v:33568$1121_Y + connect \$105 $and$libresoc.v:33569$1122_Y + connect \$107 $and$libresoc.v:33570$1123_Y + connect \$109 $and$libresoc.v:33571$1124_Y + connect \$111 $and$libresoc.v:33572$1125_Y + connect \$113 $and$libresoc.v:33573$1126_Y + connect \$115 $and$libresoc.v:33574$1127_Y + connect \$11 $and$libresoc.v:33575$1128_Y + connect \$13 $not$libresoc.v:33576$1129_Y + connect \$15 $and$libresoc.v:33577$1130_Y + connect \$17 $not$libresoc.v:33578$1131_Y + connect \$19 $and$libresoc.v:33579$1132_Y + connect \$21 $and$libresoc.v:33580$1133_Y + connect \$25 $not$libresoc.v:33581$1134_Y + connect \$27 $and$libresoc.v:33582$1135_Y + connect \$24 $reduce_or$libresoc.v:33583$1136_Y + connect \$23 $not$libresoc.v:33584$1137_Y + connect \$31 $and$libresoc.v:33585$1138_Y + connect \$33 $reduce_or$libresoc.v:33586$1139_Y + connect \$35 $reduce_or$libresoc.v:33587$1140_Y + connect \$37 $or$libresoc.v:33588$1141_Y + connect \$3 $and$libresoc.v:33589$1142_Y + connect \$39 $not$libresoc.v:33590$1143_Y + connect \$41 $and$libresoc.v:33591$1144_Y + connect \$43 $and$libresoc.v:33592$1145_Y + connect \$45 $eq$libresoc.v:33593$1146_Y + connect \$47 $and$libresoc.v:33594$1147_Y + connect \$49 $eq$libresoc.v:33595$1148_Y + connect \$51 $and$libresoc.v:33596$1149_Y + connect \$53 $and$libresoc.v:33597$1150_Y + connect \$55 $and$libresoc.v:33598$1151_Y + connect \$57 $or$libresoc.v:33599$1152_Y + connect \$59 $or$libresoc.v:33600$1153_Y + connect \$61 $or$libresoc.v:33601$1154_Y + connect \$63 $or$libresoc.v:33602$1155_Y + connect \$65 $and$libresoc.v:33603$1156_Y + connect \$67 $and$libresoc.v:33604$1157_Y + connect \$6 $not$libresoc.v:33605$1158_Y + connect \$69 $or$libresoc.v:33606$1159_Y + connect \$71 $and$libresoc.v:33607$1160_Y + connect \$73 $and$libresoc.v:33608$1161_Y + connect \$75 $and$libresoc.v:33609$1162_Y + connect \$77 $ternary$libresoc.v:33610$1163_Y + connect \$79 $ternary$libresoc.v:33611$1164_Y + connect \$81 $ternary$libresoc.v:33612$1165_Y + connect \$83 $ternary$libresoc.v:33613$1166_Y + connect \$85 $ternary$libresoc.v:33614$1167_Y + connect \$87 $and$libresoc.v:33615$1168_Y + connect \$8 $or$libresoc.v:33616$1169_Y + connect \$89 $and$libresoc.v:33617$1170_Y + connect \$91 $and$libresoc.v:33618$1171_Y + connect \$93 $not$libresoc.v:33619$1172_Y + connect \$95 $and$libresoc.v:33620$1173_Y + connect \$97 $not$libresoc.v:33621$1174_Y + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \cu_wr__rel_o \$109 + connect \cu_rd__rel_o \$99 + connect \cu_busy_o \opc_l_q_opc + connect \alu_l_s_alu \all_rd_pulse + connect \alu_branch0_n_ready_i \alu_l_q_alu + connect \alui_l_s_alui \all_rd_pulse + connect \alu_branch0_p_valid_i \alui_l_q_alui + connect \alu_branch0_cr_a \$85 + connect \alu_branch0_fast2$2 \$83 + connect \alu_branch0_fast1$1 \$81 + connect \src_or_imm \$79 + connect \src_sel \$77 + connect \cu_wrmask_o { \$75 \$73 \$71 } + connect \reset_r \$63 + connect \reset_w \$61 + connect \rst_r \$59 + connect \reset \$57 + connect \wr_any \$37 + connect \cu_done_o \$31 + connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } + connect \alu_pulse \alu_done_rise + connect \alu_done_rise \$19 + connect \alu_done_dly$next \alu_done + connect \alu_done \alu_branch0_n_valid_o + connect \all_rd_pulse \all_rd_rise + connect \all_rd_rise \$15 + connect \all_rd_dly$next \all_rd + connect \all_rd \$11 +end +attribute \src "libresoc.v:34071.1-34129.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.busy_l" +attribute \generator "nMigen" +module \busy_l + attribute \src "libresoc.v:34072.7-34072.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:34117.3-34125.6" + wire $0\q_int$next[0:0]$1345 + attribute \src "libresoc.v:34115.3-34116.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:34117.3-34125.6" + wire $1\q_int$next[0:0]$1346 + attribute \src "libresoc.v:34096.7-34096.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:34107.17-34107.96" + wire $and$libresoc.v:34107$1335_Y + attribute \src "libresoc.v:34112.17-34112.96" + wire $and$libresoc.v:34112$1340_Y + attribute \src "libresoc.v:34109.18-34109.94" + wire $not$libresoc.v:34109$1337_Y + attribute \src "libresoc.v:34111.17-34111.93" + wire $not$libresoc.v:34111$1339_Y + attribute \src "libresoc.v:34114.17-34114.93" + wire $not$libresoc.v:34114$1342_Y + attribute \src "libresoc.v:34108.18-34108.99" + wire $or$libresoc.v:34108$1336_Y + attribute \src "libresoc.v:34110.18-34110.100" + wire $or$libresoc.v:34110$1338_Y + attribute \src "libresoc.v:34113.17-34113.98" + wire $or$libresoc.v:34113$1341_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:34072.7-34072.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:34107$1335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:34107$1335_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:34112$1340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:34112$1340_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:34109$1337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_busy + connect \Y $not$libresoc.v:34109$1337_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:34111$1339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_busy + connect \Y $not$libresoc.v:34111$1339_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:34114$1342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_busy + connect \Y $not$libresoc.v:34114$1342_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:34108$1336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_busy + connect \Y $or$libresoc.v:34108$1336_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:34110$1338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_busy + connect \B \q_int + connect \Y $or$libresoc.v:34110$1338_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:34113$1341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_busy + connect \Y $or$libresoc.v:34113$1341_Y + end + attribute \src "libresoc.v:34072.7-34072.20" + process $proc$libresoc.v:34072$1347 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:34096.7-34096.19" + process $proc$libresoc.v:34096$1348 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:34115.3-34116.27" + process $proc$libresoc.v:34115$1343 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:34117.3-34125.6" + process $proc$libresoc.v:34117$1344 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1345 $1\q_int$next[0:0]$1346 + attribute \src "libresoc.v:34118.5-34118.29" + switch \initial + attribute \src "libresoc.v:34118.9-34118.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1346 1'0 + case + assign $1\q_int$next[0:0]$1346 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1345 + end + connect \$9 $and$libresoc.v:34107$1335_Y + connect \$11 $or$libresoc.v:34108$1336_Y + connect \$13 $not$libresoc.v:34109$1337_Y + connect \$15 $or$libresoc.v:34110$1338_Y + connect \$1 $not$libresoc.v:34111$1339_Y + connect \$3 $and$libresoc.v:34112$1340_Y + connect \$5 $or$libresoc.v:34113$1341_Y + connect \$7 $not$libresoc.v:34114$1342_Y + connect \qlq_busy \$15 + connect \qn_busy \$13 + connect \q_busy \$11 +end +attribute \src "libresoc.v:34133.1-35741.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.clz" +attribute \generator "nMigen" +module \clz + attribute \src "libresoc.v:34608.3-34622.6" + wire width 2 $0\cnt_1_0[1:0] + attribute \src "libresoc.v:34698.3-34712.6" + wire width 2 $0\cnt_1_10[1:0] + attribute \src "libresoc.v:34713.3-34727.6" + wire width 2 $0\cnt_1_11[1:0] + attribute \src "libresoc.v:34728.3-34742.6" + wire width 2 $0\cnt_1_12[1:0] + attribute \src "libresoc.v:34743.3-34757.6" + wire width 2 $0\cnt_1_13[1:0] + attribute \src "libresoc.v:34758.3-34772.6" + wire width 2 $0\cnt_1_14[1:0] + attribute \src "libresoc.v:34788.3-34802.6" + wire width 2 $0\cnt_1_15[1:0] + attribute \src "libresoc.v:34803.3-34817.6" + wire width 2 $0\cnt_1_16[1:0] + attribute \src "libresoc.v:34818.3-34832.6" + wire width 2 $0\cnt_1_17[1:0] + attribute \src "libresoc.v:34833.3-34847.6" + wire width 2 $0\cnt_1_18[1:0] + attribute \src "libresoc.v:34848.3-34862.6" + wire width 2 $0\cnt_1_19[1:0] + attribute \src "libresoc.v:34773.3-34787.6" + wire width 2 $0\cnt_1_1[1:0] + attribute \src "libresoc.v:34863.3-34877.6" + wire width 2 $0\cnt_1_20[1:0] + attribute \src "libresoc.v:34878.3-34892.6" + wire width 2 $0\cnt_1_21[1:0] + attribute \src "libresoc.v:34893.3-34907.6" + wire width 2 $0\cnt_1_22[1:0] + attribute \src "libresoc.v:34908.3-34922.6" + wire width 2 $0\cnt_1_23[1:0] + attribute \src "libresoc.v:34923.3-34937.6" + wire width 2 $0\cnt_1_24[1:0] + attribute \src "libresoc.v:34953.3-34967.6" + wire width 2 $0\cnt_1_25[1:0] + attribute \src "libresoc.v:34968.3-34982.6" + wire width 2 $0\cnt_1_26[1:0] + attribute \src "libresoc.v:34983.3-34997.6" + wire width 2 $0\cnt_1_27[1:0] + attribute \src "libresoc.v:34998.3-35012.6" + wire width 2 $0\cnt_1_28[1:0] + attribute \src "libresoc.v:35013.3-35027.6" + wire width 2 $0\cnt_1_29[1:0] + attribute \src "libresoc.v:34938.3-34952.6" + wire width 2 $0\cnt_1_2[1:0] + attribute \src "libresoc.v:35028.3-35042.6" + wire width 2 $0\cnt_1_30[1:0] + attribute \src "libresoc.v:35043.3-35057.6" + wire width 2 $0\cnt_1_31[1:0] + attribute \src "libresoc.v:35178.3-35192.6" + wire width 2 $0\cnt_1_3[1:0] + attribute \src "libresoc.v:35593.3-35607.6" + wire width 2 $0\cnt_1_4[1:0] + attribute \src "libresoc.v:34623.3-34637.6" + wire width 2 $0\cnt_1_5[1:0] + attribute \src "libresoc.v:34638.3-34652.6" + wire width 2 $0\cnt_1_6[1:0] + attribute \src "libresoc.v:34653.3-34667.6" + wire width 2 $0\cnt_1_7[1:0] + attribute \src "libresoc.v:34668.3-34682.6" + wire width 2 $0\cnt_1_8[1:0] + attribute \src "libresoc.v:34683.3-34697.6" + wire width 2 $0\cnt_1_9[1:0] + attribute \src "libresoc.v:35058.3-35077.6" + wire width 3 $0\cnt_2_0[2:0] + attribute \src "libresoc.v:35158.3-35177.6" + wire width 3 $0\cnt_2_10[2:0] + attribute \src "libresoc.v:35193.3-35212.6" + wire width 3 $0\cnt_2_12[2:0] + attribute \src "libresoc.v:35213.3-35232.6" + wire width 3 $0\cnt_2_14[2:0] + attribute \src "libresoc.v:35233.3-35252.6" + wire width 3 $0\cnt_2_16[2:0] + attribute \src "libresoc.v:35253.3-35272.6" + wire width 3 $0\cnt_2_18[2:0] + attribute \src "libresoc.v:35273.3-35292.6" + wire width 3 $0\cnt_2_20[2:0] + attribute \src "libresoc.v:35293.3-35312.6" + wire width 3 $0\cnt_2_22[2:0] + attribute \src "libresoc.v:35313.3-35332.6" + wire width 3 $0\cnt_2_24[2:0] + attribute \src "libresoc.v:35333.3-35352.6" + wire width 3 $0\cnt_2_26[2:0] + attribute \src "libresoc.v:35353.3-35372.6" + wire width 3 $0\cnt_2_28[2:0] + attribute \src "libresoc.v:35078.3-35097.6" + wire width 3 $0\cnt_2_2[2:0] + attribute \src "libresoc.v:35373.3-35392.6" + wire width 3 $0\cnt_2_30[2:0] + attribute \src "libresoc.v:35098.3-35117.6" + wire width 3 $0\cnt_2_4[2:0] + attribute \src "libresoc.v:35118.3-35137.6" + wire width 3 $0\cnt_2_6[2:0] + attribute \src "libresoc.v:35138.3-35157.6" + wire width 3 $0\cnt_2_8[2:0] + attribute \src "libresoc.v:35393.3-35412.6" + wire width 4 $0\cnt_3_0[3:0] + attribute \src "libresoc.v:35493.3-35512.6" + wire width 4 $0\cnt_3_10[3:0] + attribute \src "libresoc.v:35513.3-35532.6" + wire width 4 $0\cnt_3_12[3:0] + attribute \src "libresoc.v:35533.3-35552.6" + wire width 4 $0\cnt_3_14[3:0] + attribute \src "libresoc.v:35413.3-35432.6" + wire width 4 $0\cnt_3_2[3:0] + attribute \src "libresoc.v:35433.3-35452.6" + wire width 4 $0\cnt_3_4[3:0] + attribute \src "libresoc.v:35453.3-35472.6" + wire width 4 $0\cnt_3_6[3:0] + attribute \src "libresoc.v:35473.3-35492.6" + wire width 4 $0\cnt_3_8[3:0] + attribute \src "libresoc.v:35553.3-35572.6" + wire width 5 $0\cnt_4_0[4:0] + attribute \src "libresoc.v:35573.3-35592.6" + wire width 5 $0\cnt_4_2[4:0] + attribute \src "libresoc.v:35608.3-35627.6" + wire width 5 $0\cnt_4_4[4:0] + attribute \src "libresoc.v:35628.3-35647.6" + wire width 5 $0\cnt_4_6[4:0] + attribute \src "libresoc.v:35648.3-35667.6" + wire width 6 $0\cnt_5_0[5:0] + attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_18 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_18 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 4 \cnt_3_0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 4 \cnt_3_10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 4 \cnt_3_12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 4 \cnt_3_14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 4 \cnt_3_2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 4 \cnt_3_4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 4 \cnt_3_6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 4 \cnt_3_8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 5 \cnt_4_0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 5 \cnt_4_2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 5 \cnt_4_4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 5 \cnt_4_6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 6 \cnt_5_0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 6 \cnt_5_2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 7 \cnt_6_0 + attribute \src "libresoc.v:34134.7-34134.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" + wire width 7 output 1 \lz + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair18 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair34 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair36 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair38 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair40 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair42 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair44 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair46 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair48 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair50 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair52 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair54 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair56 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair58 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair60 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair62 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:11" + wire width 64 input 2 \sig_in + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34515$1349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_2 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34515$1349_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34516$1350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_0 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34516$1350_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34518$1352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_6 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34518$1352_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34519$1353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_4 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34519$1353_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34521$1355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_10 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34521$1355_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34522$1356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_8 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34522$1356_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34524$1358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_14 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34524$1358_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34525$1359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_12 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34525$1359_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34528$1362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_18 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34528$1362_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34529$1363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_16 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34529$1363_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34531$1365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_22 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34531$1365_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34532$1366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_20 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34532$1366_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34534$1368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_26 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34534$1368_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34535$1369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_24 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34535$1369_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34537$1371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_5 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34537$1371_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34538$1372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_30 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34538$1372_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34539$1373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_28 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34539$1373_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34541$1375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_2 [3] + connect \B 1'1 + connect \Y $eq$libresoc.v:34541$1375_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34542$1376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_0 [3] + connect \B 1'1 + connect \Y $eq$libresoc.v:34542$1376_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34544$1378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_6 [3] + connect \B 1'1 + connect \Y $eq$libresoc.v:34544$1378_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34545$1379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_4 [3] + connect \B 1'1 + connect \Y $eq$libresoc.v:34545$1379_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34547$1381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_10 [3] + connect \B 1'1 + connect \Y $eq$libresoc.v:34547$1381_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34548$1382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_4 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34548$1382_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34549$1383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_8 [3] + connect \B 1'1 + connect \Y $eq$libresoc.v:34549$1383_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34551$1385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_14 [3] + connect \B 1'1 + connect \Y $eq$libresoc.v:34551$1385_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34552$1386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_12 [3] + connect \B 1'1 + connect \Y $eq$libresoc.v:34552$1386_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34554$1388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_4_2 [4] + connect \B 1'1 + connect \Y $eq$libresoc.v:34554$1388_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34555$1389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_4_0 [4] + connect \B 1'1 + connect \Y $eq$libresoc.v:34555$1389_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34557$1391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_4_6 [4] + connect \B 1'1 + connect \Y $eq$libresoc.v:34557$1391_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34558$1392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_4_4 [4] + connect \B 1'1 + connect \Y $eq$libresoc.v:34558$1392_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34561$1395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_5_2 [5] + connect \B 1'1 + connect \Y $eq$libresoc.v:34561$1395_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34562$1396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_5_0 [5] + connect \B 1'1 + connect \Y $eq$libresoc.v:34562$1396_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34564$1398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_1 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34564$1398_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34565$1399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_7 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34565$1399_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34566$1400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_6 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34566$1400_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34568$1402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_9 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34568$1402_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34569$1403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_8 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34569$1403_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34571$1405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_11 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34571$1405_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34572$1406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_10 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34572$1406_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34574$1408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_13 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34574$1408_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34575$1409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_0 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34575$1409_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34576$1410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_12 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34576$1410_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34578$1412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_15 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34578$1412_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34579$1413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_14 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34579$1413_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34581$1415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_17 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34581$1415_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34582$1416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_16 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34582$1416_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34584$1418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_19 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34584$1418_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34585$1419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_18 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34585$1419_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34588$1422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_21 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34588$1422_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34589$1423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_20 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34589$1423_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34591$1425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_23 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34591$1425_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34592$1426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_22 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34592$1426_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34594$1428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_25 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34594$1428_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34595$1429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_24 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34595$1429_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34597$1431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_3 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34597$1431_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34598$1432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_27 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34598$1432_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34599$1433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_26 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34599$1433_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34601$1435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_29 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34601$1435_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34602$1436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_28 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34602$1436_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34604$1438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_31 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34604$1438_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34605$1439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_30 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34605$1439_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34607$1441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_2 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34607$1441_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34517$1351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_0 [1:0] } + connect \Y $pos$libresoc.v:34517$1351_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34520$1354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_4 [1:0] } + connect \Y $pos$libresoc.v:34520$1354_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34523$1357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_8 [1:0] } + connect \Y $pos$libresoc.v:34523$1357_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34526$1360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_2 [0] } + connect \Y $pos$libresoc.v:34526$1360_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34527$1361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_12 [1:0] } + connect \Y $pos$libresoc.v:34527$1361_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34530$1364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_16 [1:0] } + connect \Y $pos$libresoc.v:34530$1364_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34533$1367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_20 [1:0] } + connect \Y $pos$libresoc.v:34533$1367_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34536$1370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_24 [1:0] } + connect \Y $pos$libresoc.v:34536$1370_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34540$1374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_28 [1:0] } + connect \Y $pos$libresoc.v:34540$1374_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34543$1377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'01 \cnt_3_0 [2:0] } + connect \Y $pos$libresoc.v:34543$1377_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34546$1380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'01 \cnt_3_4 [2:0] } + connect \Y $pos$libresoc.v:34546$1380_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34550$1384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'01 \cnt_3_8 [2:0] } + connect \Y $pos$libresoc.v:34550$1384_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34553$1387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'01 \cnt_3_12 [2:0] } + connect \Y $pos$libresoc.v:34553$1387_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34556$1390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { 2'01 \cnt_4_0 [3:0] } + connect \Y $pos$libresoc.v:34556$1390_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34559$1393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_4 [0] } + connect \Y $pos$libresoc.v:34559$1393_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34560$1394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { 2'01 \cnt_4_4 [3:0] } + connect \Y $pos$libresoc.v:34560$1394_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34563$1397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A { 2'01 \cnt_5_0 [4:0] } + connect \Y $pos$libresoc.v:34563$1397_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34567$1401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_6 [0] } + connect \Y $pos$libresoc.v:34567$1401_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34570$1404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_8 [0] } + connect \Y $pos$libresoc.v:34570$1404_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34573$1407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_10 [0] } + connect \Y $pos$libresoc.v:34573$1407_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34577$1411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_12 [0] } + connect \Y $pos$libresoc.v:34577$1411_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34580$1414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_14 [0] } + connect \Y $pos$libresoc.v:34580$1414_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34583$1417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_16 [0] } + connect \Y $pos$libresoc.v:34583$1417_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34586$1420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_0 [0] } + connect \Y $pos$libresoc.v:34586$1420_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34587$1421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_18 [0] } + connect \Y $pos$libresoc.v:34587$1421_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34590$1424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_20 [0] } + connect \Y $pos$libresoc.v:34590$1424_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34593$1427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_22 [0] } + connect \Y $pos$libresoc.v:34593$1427_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34596$1430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_24 [0] } + connect \Y $pos$libresoc.v:34596$1430_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34600$1434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_26 [0] } + connect \Y $pos$libresoc.v:34600$1434_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34603$1437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_28 [0] } + connect \Y $pos$libresoc.v:34603$1437_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34606$1440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_30 [0] } + connect \Y $pos$libresoc.v:34606$1440_Y + end + attribute \src "libresoc.v:34134.7-34134.20" + process $proc$libresoc.v:34134$1505 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:34608.3-34622.6" + process $proc$libresoc.v:34608$1442 + assign { } { } + assign $0\cnt_1_0[1:0] $1\cnt_1_0[1:0] + attribute \src "libresoc.v:34609.5-34609.29" + switch \initial + attribute \src "libresoc.v:34609.9-34609.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair0 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_0[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_0[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_0[1:0] 2'00 + end + sync always + update \cnt_1_0 $0\cnt_1_0[1:0] + end + attribute \src "libresoc.v:34623.3-34637.6" + process $proc$libresoc.v:34623$1443 + assign { } { } + assign $0\cnt_1_5[1:0] $1\cnt_1_5[1:0] + attribute \src "libresoc.v:34624.5-34624.29" + switch \initial + attribute \src "libresoc.v:34624.9-34624.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair10 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_5[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_5[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_5[1:0] 2'00 + end + sync always + update \cnt_1_5 $0\cnt_1_5[1:0] + end + attribute \src "libresoc.v:34638.3-34652.6" + process $proc$libresoc.v:34638$1444 + assign { } { } + assign $0\cnt_1_6[1:0] $1\cnt_1_6[1:0] + attribute \src "libresoc.v:34639.5-34639.29" + switch \initial + attribute \src "libresoc.v:34639.9-34639.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair12 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_6[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_6[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_6[1:0] 2'00 + end + sync always + update \cnt_1_6 $0\cnt_1_6[1:0] + end + attribute \src "libresoc.v:34653.3-34667.6" + process $proc$libresoc.v:34653$1445 + assign { } { } + assign $0\cnt_1_7[1:0] $1\cnt_1_7[1:0] + attribute \src "libresoc.v:34654.5-34654.29" + switch \initial + attribute \src "libresoc.v:34654.9-34654.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair14 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_7[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_7[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_7[1:0] 2'00 + end + sync always + update \cnt_1_7 $0\cnt_1_7[1:0] + end + attribute \src "libresoc.v:34668.3-34682.6" + process $proc$libresoc.v:34668$1446 + assign { } { } + assign $0\cnt_1_8[1:0] $1\cnt_1_8[1:0] + attribute \src "libresoc.v:34669.5-34669.29" + switch \initial + attribute \src "libresoc.v:34669.9-34669.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair16 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_8[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_8[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_8[1:0] 2'00 + end + sync always + update \cnt_1_8 $0\cnt_1_8[1:0] + end + attribute \src "libresoc.v:34683.3-34697.6" + process $proc$libresoc.v:34683$1447 + assign { } { } + assign $0\cnt_1_9[1:0] $1\cnt_1_9[1:0] + attribute \src "libresoc.v:34684.5-34684.29" + switch \initial + attribute \src "libresoc.v:34684.9-34684.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair18 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_9[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_9[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_9[1:0] 2'00 + end + sync always + update \cnt_1_9 $0\cnt_1_9[1:0] + end + attribute \src "libresoc.v:34698.3-34712.6" + process $proc$libresoc.v:34698$1448 + assign { } { } + assign $0\cnt_1_10[1:0] $1\cnt_1_10[1:0] + attribute \src "libresoc.v:34699.5-34699.29" + switch \initial + attribute \src "libresoc.v:34699.9-34699.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair20 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_10[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_10[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_10[1:0] 2'00 + end + sync always + update \cnt_1_10 $0\cnt_1_10[1:0] + end + attribute \src "libresoc.v:34713.3-34727.6" + process $proc$libresoc.v:34713$1449 + assign { } { } + assign $0\cnt_1_11[1:0] $1\cnt_1_11[1:0] + attribute \src "libresoc.v:34714.5-34714.29" + switch \initial + attribute \src "libresoc.v:34714.9-34714.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair22 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_11[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_11[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_11[1:0] 2'00 + end + sync always + update \cnt_1_11 $0\cnt_1_11[1:0] + end + attribute \src "libresoc.v:34728.3-34742.6" + process $proc$libresoc.v:34728$1450 + assign { } { } + assign $0\cnt_1_12[1:0] $1\cnt_1_12[1:0] + attribute \src "libresoc.v:34729.5-34729.29" + switch \initial + attribute \src "libresoc.v:34729.9-34729.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair24 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_12[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_12[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_12[1:0] 2'00 + end + sync always + update \cnt_1_12 $0\cnt_1_12[1:0] + end + attribute \src "libresoc.v:34743.3-34757.6" + process $proc$libresoc.v:34743$1451 + assign { } { } + assign $0\cnt_1_13[1:0] $1\cnt_1_13[1:0] + attribute \src "libresoc.v:34744.5-34744.29" + switch \initial + attribute \src "libresoc.v:34744.9-34744.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair26 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_13[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_13[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_13[1:0] 2'00 + end + sync always + update \cnt_1_13 $0\cnt_1_13[1:0] + end + attribute \src "libresoc.v:34758.3-34772.6" + process $proc$libresoc.v:34758$1452 + assign { } { } + assign $0\cnt_1_14[1:0] $1\cnt_1_14[1:0] + attribute \src "libresoc.v:34759.5-34759.29" + switch \initial + attribute \src "libresoc.v:34759.9-34759.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair28 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_14[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_14[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_14[1:0] 2'00 + end + sync always + update \cnt_1_14 $0\cnt_1_14[1:0] + end + attribute \src "libresoc.v:34773.3-34787.6" + process $proc$libresoc.v:34773$1453 + assign { } { } + assign $0\cnt_1_1[1:0] $1\cnt_1_1[1:0] + attribute \src "libresoc.v:34774.5-34774.29" + switch \initial + attribute \src "libresoc.v:34774.9-34774.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair2 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_1[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_1[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_1[1:0] 2'00 + end + sync always + update \cnt_1_1 $0\cnt_1_1[1:0] + end + attribute \src "libresoc.v:34788.3-34802.6" + process $proc$libresoc.v:34788$1454 + assign { } { } + assign $0\cnt_1_15[1:0] $1\cnt_1_15[1:0] + attribute \src "libresoc.v:34789.5-34789.29" + switch \initial + attribute \src "libresoc.v:34789.9-34789.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair30 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_15[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_15[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_15[1:0] 2'00 + end + sync always + update \cnt_1_15 $0\cnt_1_15[1:0] + end + attribute \src "libresoc.v:34803.3-34817.6" + process $proc$libresoc.v:34803$1455 + assign { } { } + assign $0\cnt_1_16[1:0] $1\cnt_1_16[1:0] + attribute \src "libresoc.v:34804.5-34804.29" + switch \initial + attribute \src "libresoc.v:34804.9-34804.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair32 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_16[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_16[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_16[1:0] 2'00 + end + sync always + update \cnt_1_16 $0\cnt_1_16[1:0] + end + attribute \src "libresoc.v:34818.3-34832.6" + process $proc$libresoc.v:34818$1456 + assign { } { } + assign $0\cnt_1_17[1:0] $1\cnt_1_17[1:0] + attribute \src "libresoc.v:34819.5-34819.29" + switch \initial + attribute \src "libresoc.v:34819.9-34819.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair34 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_17[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_17[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_17[1:0] 2'00 + end + sync always + update \cnt_1_17 $0\cnt_1_17[1:0] + end + attribute \src "libresoc.v:34833.3-34847.6" + process $proc$libresoc.v:34833$1457 + assign { } { } + assign $0\cnt_1_18[1:0] $1\cnt_1_18[1:0] + attribute \src "libresoc.v:34834.5-34834.29" + switch \initial + attribute \src "libresoc.v:34834.9-34834.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair36 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_18[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_18[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_18[1:0] 2'00 + end + sync always + update \cnt_1_18 $0\cnt_1_18[1:0] + end + attribute \src "libresoc.v:34848.3-34862.6" + process $proc$libresoc.v:34848$1458 + assign { } { } + assign $0\cnt_1_19[1:0] $1\cnt_1_19[1:0] + attribute \src "libresoc.v:34849.5-34849.29" + switch \initial + attribute \src "libresoc.v:34849.9-34849.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair38 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_19[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_19[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_19[1:0] 2'00 + end + sync always + update \cnt_1_19 $0\cnt_1_19[1:0] + end + attribute \src "libresoc.v:34863.3-34877.6" + process $proc$libresoc.v:34863$1459 + assign { } { } + assign $0\cnt_1_20[1:0] $1\cnt_1_20[1:0] + attribute \src "libresoc.v:34864.5-34864.29" + switch \initial + attribute \src "libresoc.v:34864.9-34864.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair40 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_20[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_20[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_20[1:0] 2'00 + end + sync always + update \cnt_1_20 $0\cnt_1_20[1:0] + end + attribute \src "libresoc.v:34878.3-34892.6" + process $proc$libresoc.v:34878$1460 + assign { } { } + assign $0\cnt_1_21[1:0] $1\cnt_1_21[1:0] + attribute \src "libresoc.v:34879.5-34879.29" + switch \initial + attribute \src "libresoc.v:34879.9-34879.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair42 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_21[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_21[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_21[1:0] 2'00 + end + sync always + update \cnt_1_21 $0\cnt_1_21[1:0] + end + attribute \src "libresoc.v:34893.3-34907.6" + process $proc$libresoc.v:34893$1461 + assign { } { } + assign $0\cnt_1_22[1:0] $1\cnt_1_22[1:0] + attribute \src "libresoc.v:34894.5-34894.29" + switch \initial + attribute \src "libresoc.v:34894.9-34894.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair44 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_22[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_22[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_22[1:0] 2'00 + end + sync always + update \cnt_1_22 $0\cnt_1_22[1:0] + end + attribute \src "libresoc.v:34908.3-34922.6" + process $proc$libresoc.v:34908$1462 + assign { } { } + assign $0\cnt_1_23[1:0] $1\cnt_1_23[1:0] + attribute \src "libresoc.v:34909.5-34909.29" + switch \initial + attribute \src "libresoc.v:34909.9-34909.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair46 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_23[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_23[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_23[1:0] 2'00 + end + sync always + update \cnt_1_23 $0\cnt_1_23[1:0] + end + attribute \src "libresoc.v:34923.3-34937.6" + process $proc$libresoc.v:34923$1463 + assign { } { } + assign $0\cnt_1_24[1:0] $1\cnt_1_24[1:0] + attribute \src "libresoc.v:34924.5-34924.29" + switch \initial + attribute \src "libresoc.v:34924.9-34924.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair48 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_24[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_24[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_24[1:0] 2'00 + end + sync always + update \cnt_1_24 $0\cnt_1_24[1:0] + end + attribute \src "libresoc.v:34938.3-34952.6" + process $proc$libresoc.v:34938$1464 + assign { } { } + assign $0\cnt_1_2[1:0] $1\cnt_1_2[1:0] + attribute \src "libresoc.v:34939.5-34939.29" + switch \initial + attribute \src "libresoc.v:34939.9-34939.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair4 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_2[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_2[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_2[1:0] 2'00 + end + sync always + update \cnt_1_2 $0\cnt_1_2[1:0] + end + attribute \src "libresoc.v:34953.3-34967.6" + process $proc$libresoc.v:34953$1465 + assign { } { } + assign $0\cnt_1_25[1:0] $1\cnt_1_25[1:0] + attribute \src "libresoc.v:34954.5-34954.29" + switch \initial + attribute \src "libresoc.v:34954.9-34954.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair50 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_25[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_25[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_25[1:0] 2'00 + end + sync always + update \cnt_1_25 $0\cnt_1_25[1:0] + end + attribute \src "libresoc.v:34968.3-34982.6" + process $proc$libresoc.v:34968$1466 + assign { } { } + assign $0\cnt_1_26[1:0] $1\cnt_1_26[1:0] + attribute \src "libresoc.v:34969.5-34969.29" + switch \initial + attribute \src "libresoc.v:34969.9-34969.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair52 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_26[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_26[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_26[1:0] 2'00 + end + sync always + update \cnt_1_26 $0\cnt_1_26[1:0] + end + attribute \src "libresoc.v:34983.3-34997.6" + process $proc$libresoc.v:34983$1467 + assign { } { } + assign $0\cnt_1_27[1:0] $1\cnt_1_27[1:0] + attribute \src "libresoc.v:34984.5-34984.29" + switch \initial + attribute \src "libresoc.v:34984.9-34984.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair54 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_27[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_27[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_27[1:0] 2'00 + end + sync always + update \cnt_1_27 $0\cnt_1_27[1:0] + end + attribute \src "libresoc.v:34998.3-35012.6" + process $proc$libresoc.v:34998$1468 + assign { } { } + assign $0\cnt_1_28[1:0] $1\cnt_1_28[1:0] + attribute \src "libresoc.v:34999.5-34999.29" + switch \initial + attribute \src "libresoc.v:34999.9-34999.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair56 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_28[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_28[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_28[1:0] 2'00 + end + sync always + update \cnt_1_28 $0\cnt_1_28[1:0] + end + attribute \src "libresoc.v:35013.3-35027.6" + process $proc$libresoc.v:35013$1469 + assign { } { } + assign $0\cnt_1_29[1:0] $1\cnt_1_29[1:0] + attribute \src "libresoc.v:35014.5-35014.29" + switch \initial + attribute \src "libresoc.v:35014.9-35014.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair58 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_29[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_29[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_29[1:0] 2'00 + end + sync always + update \cnt_1_29 $0\cnt_1_29[1:0] + end + attribute \src "libresoc.v:35028.3-35042.6" + process $proc$libresoc.v:35028$1470 + assign { } { } + assign $0\cnt_1_30[1:0] $1\cnt_1_30[1:0] + attribute \src "libresoc.v:35029.5-35029.29" + switch \initial + attribute \src "libresoc.v:35029.9-35029.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair60 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_30[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_30[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_30[1:0] 2'00 + end + sync always + update \cnt_1_30 $0\cnt_1_30[1:0] + end + attribute \src "libresoc.v:35043.3-35057.6" + process $proc$libresoc.v:35043$1471 + assign { } { } + assign $0\cnt_1_31[1:0] $1\cnt_1_31[1:0] + attribute \src "libresoc.v:35044.5-35044.29" + switch \initial + attribute \src "libresoc.v:35044.9-35044.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair62 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_31[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_31[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_31[1:0] 2'00 + end + sync always + update \cnt_1_31 $0\cnt_1_31[1:0] + end + attribute \src "libresoc.v:35058.3-35077.6" + process $proc$libresoc.v:35058$1472 + assign { } { } + assign $0\cnt_2_0[2:0] $1\cnt_2_0[2:0] + attribute \src "libresoc.v:35059.5-35059.29" + switch \initial + attribute \src "libresoc.v:35059.9-35059.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_0[2:0] $2\cnt_2_0[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_0[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_0[2:0] \$5 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_0[2:0] { 1'0 \cnt_1_1 } + end + sync always + update \cnt_2_0 $0\cnt_2_0[2:0] + end + attribute \src "libresoc.v:35078.3-35097.6" + process $proc$libresoc.v:35078$1473 + assign { } { } + assign $0\cnt_2_2[2:0] $1\cnt_2_2[2:0] + attribute \src "libresoc.v:35079.5-35079.29" + switch \initial + attribute \src "libresoc.v:35079.9-35079.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_2[2:0] $2\cnt_2_2[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_2[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_2[2:0] \$11 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_2[2:0] { 1'0 \cnt_1_3 } + end + sync always + update \cnt_2_2 $0\cnt_2_2[2:0] + end + attribute \src "libresoc.v:35098.3-35117.6" + process $proc$libresoc.v:35098$1474 + assign { } { } + assign $0\cnt_2_4[2:0] $1\cnt_2_4[2:0] + attribute \src "libresoc.v:35099.5-35099.29" + switch \initial + attribute \src "libresoc.v:35099.9-35099.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_4[2:0] $2\cnt_2_4[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_4[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_4[2:0] \$17 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_4[2:0] { 1'0 \cnt_1_5 } + end + sync always + update \cnt_2_4 $0\cnt_2_4[2:0] + end + attribute \src "libresoc.v:35118.3-35137.6" + process $proc$libresoc.v:35118$1475 + assign { } { } + assign $0\cnt_2_6[2:0] $1\cnt_2_6[2:0] + attribute \src "libresoc.v:35119.5-35119.29" + switch \initial + attribute \src "libresoc.v:35119.9-35119.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_6[2:0] $2\cnt_2_6[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$21 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_6[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_6[2:0] \$23 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_6[2:0] { 1'0 \cnt_1_7 } + end + sync always + update \cnt_2_6 $0\cnt_2_6[2:0] + end + attribute \src "libresoc.v:35138.3-35157.6" + process $proc$libresoc.v:35138$1476 + assign { } { } + assign $0\cnt_2_8[2:0] $1\cnt_2_8[2:0] + attribute \src "libresoc.v:35139.5-35139.29" + switch \initial + attribute \src "libresoc.v:35139.9-35139.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_8[2:0] $2\cnt_2_8[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_8[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_8[2:0] \$29 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_8[2:0] { 1'0 \cnt_1_9 } + end + sync always + update \cnt_2_8 $0\cnt_2_8[2:0] + end + attribute \src "libresoc.v:35158.3-35177.6" + process $proc$libresoc.v:35158$1477 + assign { } { } + assign $0\cnt_2_10[2:0] $1\cnt_2_10[2:0] + attribute \src "libresoc.v:35159.5-35159.29" + switch \initial + attribute \src "libresoc.v:35159.9-35159.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$31 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_10[2:0] $2\cnt_2_10[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$33 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_10[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_10[2:0] \$35 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_10[2:0] { 1'0 \cnt_1_11 } + end + sync always + update \cnt_2_10 $0\cnt_2_10[2:0] + end + attribute \src "libresoc.v:35178.3-35192.6" + process $proc$libresoc.v:35178$1478 + assign { } { } + assign $0\cnt_1_3[1:0] $1\cnt_1_3[1:0] + attribute \src "libresoc.v:35179.5-35179.29" + switch \initial + attribute \src "libresoc.v:35179.9-35179.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair6 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_3[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_3[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_3[1:0] 2'00 + end + sync always + update \cnt_1_3 $0\cnt_1_3[1:0] + end + attribute \src "libresoc.v:35193.3-35212.6" + process $proc$libresoc.v:35193$1479 + assign { } { } + assign $0\cnt_2_12[2:0] $1\cnt_2_12[2:0] + attribute \src "libresoc.v:35194.5-35194.29" + switch \initial + attribute \src "libresoc.v:35194.9-35194.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$37 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_12[2:0] $2\cnt_2_12[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$39 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_12[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_12[2:0] \$41 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_12[2:0] { 1'0 \cnt_1_13 } + end + sync always + update \cnt_2_12 $0\cnt_2_12[2:0] + end + attribute \src "libresoc.v:35213.3-35232.6" + process $proc$libresoc.v:35213$1480 + assign { } { } + assign $0\cnt_2_14[2:0] $1\cnt_2_14[2:0] + attribute \src "libresoc.v:35214.5-35214.29" + switch \initial + attribute \src "libresoc.v:35214.9-35214.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$43 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_14[2:0] $2\cnt_2_14[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$45 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_14[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_14[2:0] \$47 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_14[2:0] { 1'0 \cnt_1_15 } + end + sync always + update \cnt_2_14 $0\cnt_2_14[2:0] + end + attribute \src "libresoc.v:35233.3-35252.6" + process $proc$libresoc.v:35233$1481 + assign { } { } + assign $0\cnt_2_16[2:0] $1\cnt_2_16[2:0] + attribute \src "libresoc.v:35234.5-35234.29" + switch \initial + attribute \src "libresoc.v:35234.9-35234.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$49 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_16[2:0] $2\cnt_2_16[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$51 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_16[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_16[2:0] \$53 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_16[2:0] { 1'0 \cnt_1_17 } + end + sync always + update \cnt_2_16 $0\cnt_2_16[2:0] + end + attribute \src "libresoc.v:35253.3-35272.6" + process $proc$libresoc.v:35253$1482 + assign { } { } + assign $0\cnt_2_18[2:0] $1\cnt_2_18[2:0] + attribute \src "libresoc.v:35254.5-35254.29" + switch \initial + attribute \src "libresoc.v:35254.9-35254.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$55 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_18[2:0] $2\cnt_2_18[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$57 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_18[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_18[2:0] \$59 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_18[2:0] { 1'0 \cnt_1_19 } + end + sync always + update \cnt_2_18 $0\cnt_2_18[2:0] + end + attribute \src "libresoc.v:35273.3-35292.6" + process $proc$libresoc.v:35273$1483 + assign { } { } + assign $0\cnt_2_20[2:0] $1\cnt_2_20[2:0] + attribute \src "libresoc.v:35274.5-35274.29" + switch \initial + attribute \src "libresoc.v:35274.9-35274.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$61 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_20[2:0] $2\cnt_2_20[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$63 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_20[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_20[2:0] \$65 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_20[2:0] { 1'0 \cnt_1_21 } + end + sync always + update \cnt_2_20 $0\cnt_2_20[2:0] + end + attribute \src "libresoc.v:35293.3-35312.6" + process $proc$libresoc.v:35293$1484 + assign { } { } + assign $0\cnt_2_22[2:0] $1\cnt_2_22[2:0] + attribute \src "libresoc.v:35294.5-35294.29" + switch \initial + attribute \src "libresoc.v:35294.9-35294.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$67 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_22[2:0] $2\cnt_2_22[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$69 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_22[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_22[2:0] \$71 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_22[2:0] { 1'0 \cnt_1_23 } + end + sync always + update \cnt_2_22 $0\cnt_2_22[2:0] + end + attribute \src "libresoc.v:35313.3-35332.6" + process $proc$libresoc.v:35313$1485 + assign { } { } + assign $0\cnt_2_24[2:0] $1\cnt_2_24[2:0] + attribute \src "libresoc.v:35314.5-35314.29" + switch \initial + attribute \src "libresoc.v:35314.9-35314.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$73 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_24[2:0] $2\cnt_2_24[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$75 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_24[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_24[2:0] \$77 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_24[2:0] { 1'0 \cnt_1_25 } + end + sync always + update \cnt_2_24 $0\cnt_2_24[2:0] + end + attribute \src "libresoc.v:35333.3-35352.6" + process $proc$libresoc.v:35333$1486 + assign { } { } + assign $0\cnt_2_26[2:0] $1\cnt_2_26[2:0] + attribute \src "libresoc.v:35334.5-35334.29" + switch \initial + attribute \src "libresoc.v:35334.9-35334.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$79 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_26[2:0] $2\cnt_2_26[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$81 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_26[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_26[2:0] \$83 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_26[2:0] { 1'0 \cnt_1_27 } + end + sync always + update \cnt_2_26 $0\cnt_2_26[2:0] + end + attribute \src "libresoc.v:35353.3-35372.6" + process $proc$libresoc.v:35353$1487 + assign { } { } + assign $0\cnt_2_28[2:0] $1\cnt_2_28[2:0] + attribute \src "libresoc.v:35354.5-35354.29" + switch \initial + attribute \src "libresoc.v:35354.9-35354.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$85 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_28[2:0] $2\cnt_2_28[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$87 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_28[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_28[2:0] \$89 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_28[2:0] { 1'0 \cnt_1_29 } + end + sync always + update \cnt_2_28 $0\cnt_2_28[2:0] + end + attribute \src "libresoc.v:35373.3-35392.6" + process $proc$libresoc.v:35373$1488 + assign { } { } + assign $0\cnt_2_30[2:0] $1\cnt_2_30[2:0] + attribute \src "libresoc.v:35374.5-35374.29" + switch \initial + attribute \src "libresoc.v:35374.9-35374.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$91 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_30[2:0] $2\cnt_2_30[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$93 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_30[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_30[2:0] \$95 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_30[2:0] { 1'0 \cnt_1_31 } + end + sync always + update \cnt_2_30 $0\cnt_2_30[2:0] + end + attribute \src "libresoc.v:35393.3-35412.6" + process $proc$libresoc.v:35393$1489 + assign { } { } + assign $0\cnt_3_0[3:0] $1\cnt_3_0[3:0] + attribute \src "libresoc.v:35394.5-35394.29" + switch \initial + attribute \src "libresoc.v:35394.9-35394.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$97 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_0[3:0] $2\cnt_3_0[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$99 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_0[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_0[3:0] \$101 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_0[3:0] { 1'0 \cnt_2_2 } + end + sync always + update \cnt_3_0 $0\cnt_3_0[3:0] + end + attribute \src "libresoc.v:35413.3-35432.6" + process $proc$libresoc.v:35413$1490 + assign { } { } + assign $0\cnt_3_2[3:0] $1\cnt_3_2[3:0] + attribute \src "libresoc.v:35414.5-35414.29" + switch \initial + attribute \src "libresoc.v:35414.9-35414.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$103 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_2[3:0] $2\cnt_3_2[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$105 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_2[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_2[3:0] \$107 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_2[3:0] { 1'0 \cnt_2_6 } + end + sync always + update \cnt_3_2 $0\cnt_3_2[3:0] + end + attribute \src "libresoc.v:35433.3-35452.6" + process $proc$libresoc.v:35433$1491 + assign { } { } + assign $0\cnt_3_4[3:0] $1\cnt_3_4[3:0] + attribute \src "libresoc.v:35434.5-35434.29" + switch \initial + attribute \src "libresoc.v:35434.9-35434.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$109 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_4[3:0] $2\cnt_3_4[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$111 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_4[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_4[3:0] \$113 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_4[3:0] { 1'0 \cnt_2_10 } + end + sync always + update \cnt_3_4 $0\cnt_3_4[3:0] + end + attribute \src "libresoc.v:35453.3-35472.6" + process $proc$libresoc.v:35453$1492 + assign { } { } + assign $0\cnt_3_6[3:0] $1\cnt_3_6[3:0] + attribute \src "libresoc.v:35454.5-35454.29" + switch \initial + attribute \src "libresoc.v:35454.9-35454.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$115 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_6[3:0] $2\cnt_3_6[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$117 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_6[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_6[3:0] \$119 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_6[3:0] { 1'0 \cnt_2_14 } + end + sync always + update \cnt_3_6 $0\cnt_3_6[3:0] + end + attribute \src "libresoc.v:35473.3-35492.6" + process $proc$libresoc.v:35473$1493 + assign { } { } + assign $0\cnt_3_8[3:0] $1\cnt_3_8[3:0] + attribute \src "libresoc.v:35474.5-35474.29" + switch \initial + attribute \src "libresoc.v:35474.9-35474.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$121 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_8[3:0] $2\cnt_3_8[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$123 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_8[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_8[3:0] \$125 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_8[3:0] { 1'0 \cnt_2_18 } + end + sync always + update \cnt_3_8 $0\cnt_3_8[3:0] + end + attribute \src "libresoc.v:35493.3-35512.6" + process $proc$libresoc.v:35493$1494 + assign { } { } + assign $0\cnt_3_10[3:0] $1\cnt_3_10[3:0] + attribute \src "libresoc.v:35494.5-35494.29" + switch \initial + attribute \src "libresoc.v:35494.9-35494.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$127 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_10[3:0] $2\cnt_3_10[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$129 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_10[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_10[3:0] \$131 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_10[3:0] { 1'0 \cnt_2_22 } + end + sync always + update \cnt_3_10 $0\cnt_3_10[3:0] + end + attribute \src "libresoc.v:35513.3-35532.6" + process $proc$libresoc.v:35513$1495 + assign { } { } + assign $0\cnt_3_12[3:0] $1\cnt_3_12[3:0] + attribute \src "libresoc.v:35514.5-35514.29" + switch \initial + attribute \src "libresoc.v:35514.9-35514.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$133 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_12[3:0] $2\cnt_3_12[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$135 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_12[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_12[3:0] \$137 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_12[3:0] { 1'0 \cnt_2_26 } + end + sync always + update \cnt_3_12 $0\cnt_3_12[3:0] + end + attribute \src "libresoc.v:35533.3-35552.6" + process $proc$libresoc.v:35533$1496 + assign { } { } + assign $0\cnt_3_14[3:0] $1\cnt_3_14[3:0] + attribute \src "libresoc.v:35534.5-35534.29" + switch \initial + attribute \src "libresoc.v:35534.9-35534.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$139 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_14[3:0] $2\cnt_3_14[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$141 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_14[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_14[3:0] \$143 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_14[3:0] { 1'0 \cnt_2_30 } + end + sync always + update \cnt_3_14 $0\cnt_3_14[3:0] + end + attribute \src "libresoc.v:35553.3-35572.6" + process $proc$libresoc.v:35553$1497 + assign { } { } + assign $0\cnt_4_0[4:0] $1\cnt_4_0[4:0] + attribute \src "libresoc.v:35554.5-35554.29" + switch \initial + attribute \src "libresoc.v:35554.9-35554.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$145 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_4_0[4:0] $2\cnt_4_0[4:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$147 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_4_0[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_4_0[4:0] \$149 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_4_0[4:0] { 1'0 \cnt_3_2 } + end + sync always + update \cnt_4_0 $0\cnt_4_0[4:0] + end + attribute \src "libresoc.v:35573.3-35592.6" + process $proc$libresoc.v:35573$1498 + assign { } { } + assign $0\cnt_4_2[4:0] $1\cnt_4_2[4:0] + attribute \src "libresoc.v:35574.5-35574.29" + switch \initial + attribute \src "libresoc.v:35574.9-35574.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$151 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_4_2[4:0] $2\cnt_4_2[4:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$153 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_4_2[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_4_2[4:0] \$155 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_4_2[4:0] { 1'0 \cnt_3_6 } + end + sync always + update \cnt_4_2 $0\cnt_4_2[4:0] + end + attribute \src "libresoc.v:35593.3-35607.6" + process $proc$libresoc.v:35593$1499 + assign { } { } + assign $0\cnt_1_4[1:0] $1\cnt_1_4[1:0] + attribute \src "libresoc.v:35594.5-35594.29" + switch \initial + attribute \src "libresoc.v:35594.9-35594.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair8 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_4[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_4[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_4[1:0] 2'00 + end + sync always + update \cnt_1_4 $0\cnt_1_4[1:0] + end + attribute \src "libresoc.v:35608.3-35627.6" + process $proc$libresoc.v:35608$1500 + assign { } { } + assign $0\cnt_4_4[4:0] $1\cnt_4_4[4:0] + attribute \src "libresoc.v:35609.5-35609.29" + switch \initial + attribute \src "libresoc.v:35609.9-35609.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$157 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_4_4[4:0] $2\cnt_4_4[4:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$159 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_4_4[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_4_4[4:0] \$161 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_4_4[4:0] { 1'0 \cnt_3_10 } + end + sync always + update \cnt_4_4 $0\cnt_4_4[4:0] + end + attribute \src "libresoc.v:35628.3-35647.6" + process $proc$libresoc.v:35628$1501 + assign { } { } + assign $0\cnt_4_6[4:0] $1\cnt_4_6[4:0] + attribute \src "libresoc.v:35629.5-35629.29" + switch \initial + attribute \src "libresoc.v:35629.9-35629.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$163 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_4_6[4:0] $2\cnt_4_6[4:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$165 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_4_6[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_4_6[4:0] \$167 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_4_6[4:0] { 1'0 \cnt_3_14 } + end + sync always + update \cnt_4_6 $0\cnt_4_6[4:0] + end + attribute \src "libresoc.v:35648.3-35667.6" + process $proc$libresoc.v:35648$1502 + assign { } { } + assign $0\cnt_5_0[5:0] $1\cnt_5_0[5:0] + attribute \src "libresoc.v:35649.5-35649.29" + switch \initial + attribute \src "libresoc.v:35649.9-35649.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$169 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_5_0[5:0] $2\cnt_5_0[5:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$171 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_5_0[5:0] 6'100000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_5_0[5:0] \$173 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_5_0[5:0] { 1'0 \cnt_4_2 } + end + sync always + update \cnt_5_0 $0\cnt_5_0[5:0] + end + attribute \src "libresoc.v:35668.3-35687.6" + process $proc$libresoc.v:35668$1503 + assign { } { } + assign $0\cnt_5_2[5:0] $1\cnt_5_2[5:0] + attribute \src "libresoc.v:35669.5-35669.29" + switch \initial + attribute \src "libresoc.v:35669.9-35669.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$175 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_5_2[5:0] $2\cnt_5_2[5:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$177 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_5_2[5:0] 6'100000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_5_2[5:0] \$179 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_5_2[5:0] { 1'0 \cnt_4_6 } + end + sync always + update \cnt_5_2 $0\cnt_5_2[5:0] + end + attribute \src "libresoc.v:35688.3-35707.6" + process $proc$libresoc.v:35688$1504 + assign { } { } + assign $0\cnt_6_0[6:0] $1\cnt_6_0[6:0] + attribute \src "libresoc.v:35689.5-35689.29" + switch \initial + attribute \src "libresoc.v:35689.9-35689.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$181 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_6_0[6:0] $2\cnt_6_0[6:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$183 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_6_0[6:0] 7'1000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_6_0[6:0] \$185 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_6_0[6:0] { 1'0 \cnt_5_2 } + end + sync always + update \cnt_6_0 $0\cnt_6_0[6:0] + end + connect \$9 $eq$libresoc.v:34515$1349_Y + connect \$99 $eq$libresoc.v:34516$1350_Y + connect \$101 $pos$libresoc.v:34517$1351_Y + connect \$103 $eq$libresoc.v:34518$1352_Y + connect \$105 $eq$libresoc.v:34519$1353_Y + connect \$107 $pos$libresoc.v:34520$1354_Y + connect \$109 $eq$libresoc.v:34521$1355_Y + connect \$111 $eq$libresoc.v:34522$1356_Y + connect \$113 $pos$libresoc.v:34523$1357_Y + connect \$115 $eq$libresoc.v:34524$1358_Y + connect \$117 $eq$libresoc.v:34525$1359_Y + connect \$11 $pos$libresoc.v:34526$1360_Y + connect \$119 $pos$libresoc.v:34527$1361_Y + connect \$121 $eq$libresoc.v:34528$1362_Y + connect \$123 $eq$libresoc.v:34529$1363_Y + connect \$125 $pos$libresoc.v:34530$1364_Y + connect \$127 $eq$libresoc.v:34531$1365_Y + connect \$129 $eq$libresoc.v:34532$1366_Y + connect \$131 $pos$libresoc.v:34533$1367_Y + connect \$133 $eq$libresoc.v:34534$1368_Y + connect \$135 $eq$libresoc.v:34535$1369_Y + connect \$137 $pos$libresoc.v:34536$1370_Y + connect \$13 $eq$libresoc.v:34537$1371_Y + connect \$139 $eq$libresoc.v:34538$1372_Y + connect \$141 $eq$libresoc.v:34539$1373_Y + connect \$143 $pos$libresoc.v:34540$1374_Y + connect \$145 $eq$libresoc.v:34541$1375_Y + connect \$147 $eq$libresoc.v:34542$1376_Y + connect \$149 $pos$libresoc.v:34543$1377_Y + connect \$151 $eq$libresoc.v:34544$1378_Y + connect \$153 $eq$libresoc.v:34545$1379_Y + connect \$155 $pos$libresoc.v:34546$1380_Y + connect \$157 $eq$libresoc.v:34547$1381_Y + connect \$15 $eq$libresoc.v:34548$1382_Y + connect \$159 $eq$libresoc.v:34549$1383_Y + connect \$161 $pos$libresoc.v:34550$1384_Y + connect \$163 $eq$libresoc.v:34551$1385_Y + connect \$165 $eq$libresoc.v:34552$1386_Y + connect \$167 $pos$libresoc.v:34553$1387_Y + connect \$169 $eq$libresoc.v:34554$1388_Y + connect \$171 $eq$libresoc.v:34555$1389_Y + connect \$173 $pos$libresoc.v:34556$1390_Y + connect \$175 $eq$libresoc.v:34557$1391_Y + connect \$177 $eq$libresoc.v:34558$1392_Y + connect \$17 $pos$libresoc.v:34559$1393_Y + connect \$179 $pos$libresoc.v:34560$1394_Y + connect \$181 $eq$libresoc.v:34561$1395_Y + connect \$183 $eq$libresoc.v:34562$1396_Y + connect \$185 $pos$libresoc.v:34563$1397_Y + connect \$1 $eq$libresoc.v:34564$1398_Y + connect \$19 $eq$libresoc.v:34565$1399_Y + connect \$21 $eq$libresoc.v:34566$1400_Y + connect \$23 $pos$libresoc.v:34567$1401_Y + connect \$25 $eq$libresoc.v:34568$1402_Y + connect \$27 $eq$libresoc.v:34569$1403_Y + connect \$29 $pos$libresoc.v:34570$1404_Y + connect \$31 $eq$libresoc.v:34571$1405_Y + connect \$33 $eq$libresoc.v:34572$1406_Y + connect \$35 $pos$libresoc.v:34573$1407_Y + connect \$37 $eq$libresoc.v:34574$1408_Y + connect \$3 $eq$libresoc.v:34575$1409_Y + connect \$39 $eq$libresoc.v:34576$1410_Y + connect \$41 $pos$libresoc.v:34577$1411_Y + connect \$43 $eq$libresoc.v:34578$1412_Y + connect \$45 $eq$libresoc.v:34579$1413_Y + connect \$47 $pos$libresoc.v:34580$1414_Y + connect \$49 $eq$libresoc.v:34581$1415_Y + connect \$51 $eq$libresoc.v:34582$1416_Y + connect \$53 $pos$libresoc.v:34583$1417_Y + connect \$55 $eq$libresoc.v:34584$1418_Y + connect \$57 $eq$libresoc.v:34585$1419_Y + connect \$5 $pos$libresoc.v:34586$1420_Y + connect \$59 $pos$libresoc.v:34587$1421_Y + connect \$61 $eq$libresoc.v:34588$1422_Y + connect \$63 $eq$libresoc.v:34589$1423_Y + connect \$65 $pos$libresoc.v:34590$1424_Y + connect \$67 $eq$libresoc.v:34591$1425_Y + connect \$69 $eq$libresoc.v:34592$1426_Y + connect \$71 $pos$libresoc.v:34593$1427_Y + connect \$73 $eq$libresoc.v:34594$1428_Y + connect \$75 $eq$libresoc.v:34595$1429_Y + connect \$77 $pos$libresoc.v:34596$1430_Y + connect \$7 $eq$libresoc.v:34597$1431_Y + connect \$79 $eq$libresoc.v:34598$1432_Y + connect \$81 $eq$libresoc.v:34599$1433_Y + connect \$83 $pos$libresoc.v:34600$1434_Y + connect \$85 $eq$libresoc.v:34601$1435_Y + connect \$87 $eq$libresoc.v:34602$1436_Y + connect \$89 $pos$libresoc.v:34603$1437_Y + connect \$91 $eq$libresoc.v:34604$1438_Y + connect \$93 $eq$libresoc.v:34605$1439_Y + connect \$95 $pos$libresoc.v:34606$1440_Y + connect \$97 $eq$libresoc.v:34607$1441_Y + connect \lz \cnt_6_0 + connect \pair62 \sig_in [63:62] + connect \pair60 \sig_in [61:60] + connect \pair58 \sig_in [59:58] + connect \pair56 \sig_in [57:56] + connect \pair54 \sig_in [55:54] + connect \pair52 \sig_in [53:52] + connect \pair50 \sig_in [51:50] + connect \pair48 \sig_in [49:48] + connect \pair46 \sig_in [47:46] + connect \pair44 \sig_in [45:44] + connect \pair42 \sig_in [43:42] + connect \pair40 \sig_in [41:40] + connect \pair38 \sig_in [39:38] + connect \pair36 \sig_in [37:36] + connect \pair34 \sig_in [35:34] + connect \pair32 \sig_in [33:32] + connect \pair30 \sig_in [31:30] + connect \pair28 \sig_in [29:28] + connect \pair26 \sig_in [27:26] + connect \pair24 \sig_in [25:24] + connect \pair22 \sig_in [23:22] + connect \pair20 \sig_in [21:20] + connect \pair18 \sig_in [19:18] + connect \pair16 \sig_in [17:16] + connect \pair14 \sig_in [15:14] + connect \pair12 \sig_in [13:12] + connect \pair10 \sig_in [11:10] + connect \pair8 \sig_in [9:8] + connect \pair6 \sig_in [7:6] + connect \pair4 \sig_in [5:4] + connect \pair2 \sig_in [3:2] + connect \pair0 \sig_in [1:0] +end +attribute \src "libresoc.v:35745.1-48550.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core" +attribute \generator "nMigen" +module \core + attribute \src "libresoc.v:45520.3-45540.6" + wire $0\core_terminate_o$next[0:0]$2588 + attribute \src "libresoc.v:42412.3-42413.49" + wire $0\core_terminate_o[0:0] + attribute \src "libresoc.v:45391.3-45481.6" + wire $0\corebusy_o[0:0] + attribute \src "libresoc.v:45345.3-45371.6" + wire width 2 $0\counter$next[1:0]$2565 + attribute \src "libresoc.v:42414.3-42415.31" + wire width 2 $0\counter[1:0] + attribute \src "libresoc.v:45830.3-45838.6" + wire $0\dp_CR_cr_a_branch0_1$next[0:0]$2647 + attribute \src "libresoc.v:42348.3-42349.57" + wire $0\dp_CR_cr_a_branch0_1[0:0] + attribute \src "libresoc.v:45811.3-45819.6" + wire $0\dp_CR_cr_a_cr0_0$next[0:0]$2641 + attribute \src "libresoc.v:42350.3-42351.49" + wire $0\dp_CR_cr_a_cr0_0[0:0] + attribute \src "libresoc.v:45849.3-45857.6" + wire $0\dp_CR_cr_b_cr0_0$next[0:0]$2653 + attribute \src "libresoc.v:42346.3-42347.49" + wire $0\dp_CR_cr_b_cr0_0[0:0] + attribute \src "libresoc.v:45898.3-45906.6" + wire $0\dp_CR_cr_c_cr0_0$next[0:0]$2660 + attribute \src "libresoc.v:42344.3-42345.49" + wire $0\dp_CR_cr_c_cr0_0[0:0] + attribute \src "libresoc.v:45762.3-45770.6" + wire $0\dp_CR_full_cr_cr0_0$next[0:0]$2634 + attribute \src "libresoc.v:42352.3-42353.55" + wire $0\dp_CR_full_cr_cr0_0[0:0] + attribute \src "libresoc.v:45917.3-45925.6" + wire $0\dp_FAST_fast1_branch0_0$next[0:0]$2666 + attribute \src "libresoc.v:42342.3-42343.63" + wire $0\dp_FAST_fast1_branch0_0[0:0] + attribute \src "libresoc.v:45984.3-45992.6" + wire $0\dp_FAST_fast1_spr0_2$next[0:0]$2679 + attribute \src "libresoc.v:42338.3-42339.57" + wire $0\dp_FAST_fast1_spr0_2[0:0] + attribute \src "libresoc.v:45936.3-45944.6" + wire $0\dp_FAST_fast1_trap0_1$next[0:0]$2672 + attribute \src "libresoc.v:42340.3-42341.59" + wire $0\dp_FAST_fast1_trap0_1[0:0] + attribute \src "libresoc.v:46032.3-46040.6" + wire $0\dp_FAST_fast2_branch0_0$next[0:0]$2686 + attribute \src "libresoc.v:42336.3-42337.63" + wire $0\dp_FAST_fast2_branch0_0[0:0] + attribute \src "libresoc.v:46051.3-46059.6" + wire $0\dp_FAST_fast2_trap0_1$next[0:0]$2692 + attribute \src "libresoc.v:42334.3-42335.59" + wire $0\dp_FAST_fast2_trap0_1[0:0] + attribute \src "libresoc.v:44984.3-44992.6" + wire $0\dp_INT_ra_alu0_0$next[0:0]$2457 + attribute \src "libresoc.v:42410.3-42411.49" + wire $0\dp_INT_ra_alu0_0[0:0] + attribute \src "libresoc.v:45003.3-45011.6" + wire $0\dp_INT_ra_cr0_1$next[0:0]$2461 + attribute \src "libresoc.v:42408.3-42409.47" + wire $0\dp_INT_ra_cr0_1[0:0] + attribute \src "libresoc.v:45079.3-45087.6" + wire $0\dp_INT_ra_div0_5$next[0:0]$2485 + attribute \src "libresoc.v:42400.3-42401.49" + wire $0\dp_INT_ra_div0_5[0:0] + attribute \src "libresoc.v:45136.3-45144.6" + wire $0\dp_INT_ra_ldst0_8$next[0:0]$2503 + attribute \src "libresoc.v:42394.3-42395.51" + wire $0\dp_INT_ra_ldst0_8[0:0] + attribute \src "libresoc.v:45041.3-45049.6" + wire $0\dp_INT_ra_logical0_3$next[0:0]$2473 + attribute \src "libresoc.v:42404.3-42405.57" + wire $0\dp_INT_ra_logical0_3[0:0] + attribute \src "libresoc.v:45098.3-45106.6" + wire $0\dp_INT_ra_mul0_6$next[0:0]$2491 + attribute \src "libresoc.v:42398.3-42399.49" + wire $0\dp_INT_ra_mul0_6[0:0] + attribute \src "libresoc.v:45117.3-45125.6" + wire $0\dp_INT_ra_shiftrot0_7$next[0:0]$2497 + attribute \src "libresoc.v:42396.3-42397.59" + wire $0\dp_INT_ra_shiftrot0_7[0:0] + attribute \src "libresoc.v:45060.3-45068.6" + wire $0\dp_INT_ra_spr0_4$next[0:0]$2479 + attribute \src "libresoc.v:42402.3-42403.49" + wire $0\dp_INT_ra_spr0_4[0:0] + attribute \src "libresoc.v:45022.3-45030.6" + wire $0\dp_INT_ra_trap0_2$next[0:0]$2467 + attribute \src "libresoc.v:42406.3-42407.51" + wire $0\dp_INT_ra_trap0_2[0:0] + attribute \src "libresoc.v:45155.3-45163.6" + wire $0\dp_INT_rb_alu0_0$next[0:0]$2509 + attribute \src "libresoc.v:42392.3-42393.49" + wire $0\dp_INT_rb_alu0_0[0:0] + attribute \src "libresoc.v:45174.3-45182.6" + wire $0\dp_INT_rb_cr0_1$next[0:0]$2513 + attribute \src "libresoc.v:42390.3-42391.47" + wire $0\dp_INT_rb_cr0_1[0:0] + attribute \src "libresoc.v:45231.3-45239.6" + wire $0\dp_INT_rb_div0_4$next[0:0]$2531 + attribute \src "libresoc.v:42384.3-42385.49" + wire $0\dp_INT_rb_div0_4[0:0] + attribute \src "libresoc.v:45288.3-45296.6" + wire $0\dp_INT_rb_ldst0_7$next[0:0]$2549 + attribute \src "libresoc.v:42378.3-42379.51" + wire $0\dp_INT_rb_ldst0_7[0:0] + attribute \src "libresoc.v:45212.3-45220.6" + wire $0\dp_INT_rb_logical0_3$next[0:0]$2525 + attribute \src "libresoc.v:42386.3-42387.57" + wire $0\dp_INT_rb_logical0_3[0:0] + attribute \src "libresoc.v:45250.3-45258.6" + wire $0\dp_INT_rb_mul0_5$next[0:0]$2537 + attribute \src "libresoc.v:42382.3-42383.49" + wire $0\dp_INT_rb_mul0_5[0:0] + attribute \src "libresoc.v:45269.3-45277.6" + wire $0\dp_INT_rb_shiftrot0_6$next[0:0]$2543 + attribute \src "libresoc.v:42380.3-42381.59" + wire $0\dp_INT_rb_shiftrot0_6[0:0] + attribute \src "libresoc.v:45193.3-45201.6" + wire $0\dp_INT_rb_trap0_2$next[0:0]$2519 + attribute \src "libresoc.v:42388.3-42389.51" + wire $0\dp_INT_rb_trap0_2[0:0] + attribute \src "libresoc.v:45326.3-45334.6" + wire $0\dp_INT_rc_ldst0_1$next[0:0]$2559 + attribute \src "libresoc.v:42374.3-42375.51" + wire $0\dp_INT_rc_ldst0_1[0:0] + attribute \src "libresoc.v:45307.3-45315.6" + wire $0\dp_INT_rc_shiftrot0_0$next[0:0]$2555 + attribute \src "libresoc.v:42376.3-42377.59" + wire $0\dp_INT_rc_shiftrot0_0[0:0] + attribute \src "libresoc.v:46099.3-46107.6" + wire $0\dp_SPR_spr1_spr0_0$next[0:0]$2699 + attribute \src "libresoc.v:42332.3-42333.53" + wire $0\dp_SPR_spr1_spr0_0[0:0] + attribute \src "libresoc.v:45627.3-45635.6" + wire $0\dp_XER_xer_ca_alu0_0$next[0:0]$2612 + attribute \src "libresoc.v:42360.3-42361.57" + wire $0\dp_XER_xer_ca_alu0_0[0:0] + attribute \src "libresoc.v:45694.3-45702.6" + wire $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2623 + attribute \src "libresoc.v:42356.3-42357.67" + wire $0\dp_XER_xer_ca_shiftrot0_2[0:0] + attribute \src "libresoc.v:45675.3-45683.6" + wire $0\dp_XER_xer_ca_spr0_1$next[0:0]$2619 + attribute \src "libresoc.v:42358.3-42359.57" + wire $0\dp_XER_xer_ca_spr0_1[0:0] + attribute \src "libresoc.v:45743.3-45751.6" + wire $0\dp_XER_xer_ov_spr0_0$next[0:0]$2628 + attribute \src "libresoc.v:42354.3-42355.57" + wire $0\dp_XER_xer_ov_spr0_0[0:0] + attribute \src "libresoc.v:45372.3-45380.6" + wire $0\dp_XER_xer_so_alu0_0$next[0:0]$2571 + attribute \src "libresoc.v:42372.3-42373.57" + wire $0\dp_XER_xer_so_alu0_0[0:0] + attribute \src "libresoc.v:45541.3-45549.6" + wire $0\dp_XER_xer_so_div0_3$next[0:0]$2593 + attribute \src "libresoc.v:42366.3-42367.57" + wire $0\dp_XER_xer_so_div0_3[0:0] + attribute \src "libresoc.v:45482.3-45490.6" + wire $0\dp_XER_xer_so_logical0_1$next[0:0]$2578 + attribute \src "libresoc.v:42370.3-42371.65" + wire $0\dp_XER_xer_so_logical0_1[0:0] + attribute \src "libresoc.v:45560.3-45568.6" + wire $0\dp_XER_xer_so_mul0_4$next[0:0]$2599 + attribute \src "libresoc.v:42364.3-42365.57" + wire $0\dp_XER_xer_so_mul0_4[0:0] + attribute \src "libresoc.v:45608.3-45616.6" + wire $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2606 + attribute \src "libresoc.v:42362.3-42363.67" + wire $0\dp_XER_xer_so_shiftrot0_5[0:0] + attribute \src "libresoc.v:45501.3-45509.6" + wire $0\dp_XER_xer_so_spr0_2$next[0:0]$2584 + attribute \src "libresoc.v:42368.3-42369.57" + wire $0\dp_XER_xer_so_spr0_2[0:0] + attribute \src "libresoc.v:46619.3-46647.6" + wire $0\fus_cu_issue_i$11[0:0]$2768 + attribute \src "libresoc.v:47016.3-47044.6" + wire $0\fus_cu_issue_i$14[0:0]$2830 + attribute \src "libresoc.v:47380.3-47408.6" + wire $0\fus_cu_issue_i$17[0:0]$2864 + attribute \src "libresoc.v:47876.3-47904.6" + wire $0\fus_cu_issue_i$20[0:0]$2889 + attribute \src "libresoc.v:43203.3-43231.6" + wire $0\fus_cu_issue_i$23[0:0]$2356 + attribute \src "libresoc.v:43699.3-43727.6" + wire $0\fus_cu_issue_i$26[0:0]$2381 + attribute \src "libresoc.v:44021.3-44049.6" + wire $0\fus_cu_issue_i$29[0:0]$2400 + attribute \src "libresoc.v:44488.3-44516.6" + wire $0\fus_cu_issue_i$32[0:0]$2424 + attribute \src "libresoc.v:44926.3-44954.6" + wire $0\fus_cu_issue_i$35[0:0]$2447 + attribute \src "libresoc.v:46411.3-46439.6" + wire $0\fus_cu_issue_i[0:0] + attribute \src "libresoc.v:46657.3-46685.6" + wire width 6 $0\fus_cu_rdmaskn_i$13[5:0]$2776 + attribute \src "libresoc.v:47054.3-47082.6" + wire width 3 $0\fus_cu_rdmaskn_i$16[2:0]$2838 + attribute \src "libresoc.v:47409.3-47437.6" + wire width 4 $0\fus_cu_rdmaskn_i$19[3:0]$2869 + attribute \src "libresoc.v:47905.3-47933.6" + wire width 3 $0\fus_cu_rdmaskn_i$22[2:0]$2894 + attribute \src "libresoc.v:43232.3-43260.6" + wire width 6 $0\fus_cu_rdmaskn_i$25[5:0]$2361 + attribute \src "libresoc.v:43728.3-43756.6" + wire width 3 $0\fus_cu_rdmaskn_i$28[2:0]$2386 + attribute \src "libresoc.v:44050.3-44078.6" + wire width 3 $0\fus_cu_rdmaskn_i$31[2:0]$2405 + attribute \src "libresoc.v:44517.3-44545.6" + wire width 5 $0\fus_cu_rdmaskn_i$34[4:0]$2429 + attribute \src "libresoc.v:44955.3-44983.6" + wire width 3 $0\fus_cu_rdmaskn_i$37[2:0]$2452 + attribute \src "libresoc.v:46449.3-46477.6" + wire width 4 $0\fus_cu_rdmaskn_i[3:0] + attribute \src "libresoc.v:46326.3-46354.6" + wire width 4 $0\fus_oper_i_alu_alu0__data_len[3:0] + attribute \src "libresoc.v:45636.3-45664.6" + wire width 12 $0\fus_oper_i_alu_alu0__fn_unit[11:0] + attribute \src "libresoc.v:45703.3-45732.6" + wire width 64 $0\fus_oper_i_alu_alu0__imm_data__data[63:0] + attribute \src "libresoc.v:45703.3-45732.6" + wire $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "libresoc.v:46156.3-46184.6" + wire width 2 $0\fus_oper_i_alu_alu0__input_carry[1:0] + attribute \src "libresoc.v:46373.3-46401.6" + wire width 32 $0\fus_oper_i_alu_alu0__insn[31:0] + attribute \src "libresoc.v:45579.3-45607.6" + wire width 7 $0\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "libresoc.v:45955.3-45983.6" + wire $0\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "libresoc.v:46070.3-46098.6" + wire $0\fus_oper_i_alu_alu0__invert_out[0:0] + attribute \src "libresoc.v:46241.3-46269.6" + wire $0\fus_oper_i_alu_alu0__is_32bit[0:0] + attribute \src "libresoc.v:46288.3-46316.6" + wire $0\fus_oper_i_alu_alu0__is_signed[0:0] + attribute \src "libresoc.v:45868.3-45897.6" + wire $0\fus_oper_i_alu_alu0__oe__oe[0:0] + attribute \src "libresoc.v:45868.3-45897.6" + wire $0\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "libresoc.v:46203.3-46231.6" + wire $0\fus_oper_i_alu_alu0__output_carry[0:0] + attribute \src "libresoc.v:45781.3-45810.6" + wire $0\fus_oper_i_alu_alu0__rc__ok[0:0] + attribute \src "libresoc.v:45781.3-45810.6" + wire $0\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "libresoc.v:46118.3-46146.6" + wire $0\fus_oper_i_alu_alu0__write_cr0[0:0] + attribute \src "libresoc.v:46003.3-46031.6" + wire $0\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "libresoc.v:46704.3-46732.6" + wire width 64 $0\fus_oper_i_alu_branch0__cia[63:0] + attribute \src "libresoc.v:46789.3-46817.6" + wire width 12 $0\fus_oper_i_alu_branch0__fn_unit[11:0] + attribute \src "libresoc.v:46874.3-46903.6" + wire width 64 $0\fus_oper_i_alu_branch0__imm_data__data[63:0] + attribute \src "libresoc.v:46874.3-46903.6" + wire $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] + attribute \src "libresoc.v:46827.3-46855.6" + wire width 32 $0\fus_oper_i_alu_branch0__insn[31:0] + attribute \src "libresoc.v:46742.3-46770.6" + wire width 7 $0\fus_oper_i_alu_branch0__insn_type[6:0] + attribute \src "libresoc.v:46969.3-46997.6" + wire $0\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "libresoc.v:46931.3-46959.6" + wire $0\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "libresoc.v:46534.3-46562.6" + wire width 12 $0\fus_oper_i_alu_cr0__fn_unit[11:0] + attribute \src "libresoc.v:46581.3-46609.6" + wire width 32 $0\fus_oper_i_alu_cr0__insn[31:0] + attribute \src "libresoc.v:46487.3-46515.6" + wire width 7 $0\fus_oper_i_alu_cr0__insn_type[6:0] + attribute \src "libresoc.v:43641.3-43669.6" + wire width 4 $0\fus_oper_i_alu_div0__data_len[3:0] + attribute \src "libresoc.v:43290.3-43318.6" + wire width 12 $0\fus_oper_i_alu_div0__fn_unit[11:0] + attribute \src "libresoc.v:43319.3-43348.6" + wire width 64 $0\fus_oper_i_alu_div0__imm_data__data[63:0] + attribute \src "libresoc.v:43319.3-43348.6" + wire $0\fus_oper_i_alu_div0__imm_data__ok[0:0] + attribute \src "libresoc.v:43467.3-43495.6" + wire width 2 $0\fus_oper_i_alu_div0__input_carry[1:0] + attribute \src "libresoc.v:43670.3-43698.6" + wire width 32 $0\fus_oper_i_alu_div0__insn[31:0] + attribute \src "libresoc.v:43261.3-43289.6" + wire width 7 $0\fus_oper_i_alu_div0__insn_type[6:0] + attribute \src "libresoc.v:43409.3-43437.6" + wire $0\fus_oper_i_alu_div0__invert_in[0:0] + attribute \src "libresoc.v:43496.3-43524.6" + wire $0\fus_oper_i_alu_div0__invert_out[0:0] + attribute \src "libresoc.v:43583.3-43611.6" + wire $0\fus_oper_i_alu_div0__is_32bit[0:0] + attribute \src "libresoc.v:43612.3-43640.6" + wire $0\fus_oper_i_alu_div0__is_signed[0:0] + attribute \src "libresoc.v:43379.3-43408.6" + wire $0\fus_oper_i_alu_div0__oe__oe[0:0] + attribute \src "libresoc.v:43379.3-43408.6" + wire $0\fus_oper_i_alu_div0__oe__ok[0:0] + attribute \src "libresoc.v:43554.3-43582.6" + wire $0\fus_oper_i_alu_div0__output_carry[0:0] + attribute \src "libresoc.v:43349.3-43378.6" + wire $0\fus_oper_i_alu_div0__rc__ok[0:0] + attribute \src "libresoc.v:43349.3-43378.6" + wire $0\fus_oper_i_alu_div0__rc__rc[0:0] + attribute \src "libresoc.v:43525.3-43553.6" + wire $0\fus_oper_i_alu_div0__write_cr0[0:0] + attribute \src "libresoc.v:43438.3-43466.6" + wire $0\fus_oper_i_alu_div0__zero_a[0:0] + attribute \src "libresoc.v:47818.3-47846.6" + wire width 4 $0\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "libresoc.v:47467.3-47495.6" + wire width 12 $0\fus_oper_i_alu_logical0__fn_unit[11:0] + attribute \src "libresoc.v:47496.3-47525.6" + wire width 64 $0\fus_oper_i_alu_logical0__imm_data__data[63:0] + attribute \src "libresoc.v:47496.3-47525.6" + wire $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] + attribute \src "libresoc.v:47644.3-47672.6" + wire width 2 $0\fus_oper_i_alu_logical0__input_carry[1:0] + attribute \src "libresoc.v:47847.3-47875.6" + wire width 32 $0\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "libresoc.v:47438.3-47466.6" + wire width 7 $0\fus_oper_i_alu_logical0__insn_type[6:0] + attribute \src "libresoc.v:47586.3-47614.6" + wire $0\fus_oper_i_alu_logical0__invert_in[0:0] + attribute \src "libresoc.v:47673.3-47701.6" + wire $0\fus_oper_i_alu_logical0__invert_out[0:0] + attribute \src "libresoc.v:47760.3-47788.6" + wire $0\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "libresoc.v:47789.3-47817.6" + wire $0\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "libresoc.v:47556.3-47585.6" + wire $0\fus_oper_i_alu_logical0__oe__oe[0:0] + attribute \src "libresoc.v:47556.3-47585.6" + wire $0\fus_oper_i_alu_logical0__oe__ok[0:0] + attribute \src "libresoc.v:47731.3-47759.6" + wire $0\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "libresoc.v:47526.3-47555.6" + wire $0\fus_oper_i_alu_logical0__rc__ok[0:0] + attribute \src "libresoc.v:47526.3-47555.6" + wire $0\fus_oper_i_alu_logical0__rc__rc[0:0] + attribute \src "libresoc.v:47702.3-47730.6" + wire $0\fus_oper_i_alu_logical0__write_cr0[0:0] + attribute \src "libresoc.v:47615.3-47643.6" + wire $0\fus_oper_i_alu_logical0__zero_a[0:0] + attribute \src "libresoc.v:43786.3-43814.6" + wire width 12 $0\fus_oper_i_alu_mul0__fn_unit[11:0] + attribute \src "libresoc.v:43815.3-43844.6" + wire width 64 $0\fus_oper_i_alu_mul0__imm_data__data[63:0] + attribute \src "libresoc.v:43815.3-43844.6" + wire $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] + attribute \src "libresoc.v:43992.3-44020.6" + wire width 32 $0\fus_oper_i_alu_mul0__insn[31:0] + attribute \src "libresoc.v:43757.3-43785.6" + wire width 7 $0\fus_oper_i_alu_mul0__insn_type[6:0] + attribute \src "libresoc.v:43934.3-43962.6" + wire $0\fus_oper_i_alu_mul0__is_32bit[0:0] + attribute \src "libresoc.v:43963.3-43991.6" + wire $0\fus_oper_i_alu_mul0__is_signed[0:0] + attribute \src "libresoc.v:43875.3-43904.6" + wire $0\fus_oper_i_alu_mul0__oe__oe[0:0] + attribute \src "libresoc.v:43875.3-43904.6" + wire $0\fus_oper_i_alu_mul0__oe__ok[0:0] + attribute \src "libresoc.v:43845.3-43874.6" + wire $0\fus_oper_i_alu_mul0__rc__ok[0:0] + attribute \src "libresoc.v:43845.3-43874.6" + wire $0\fus_oper_i_alu_mul0__rc__rc[0:0] + attribute \src "libresoc.v:43905.3-43933.6" + wire $0\fus_oper_i_alu_mul0__write_cr0[0:0] + attribute \src "libresoc.v:44108.3-44136.6" + wire width 12 $0\fus_oper_i_alu_shift_rot0__fn_unit[11:0] + attribute \src "libresoc.v:44137.3-44166.6" + wire width 64 $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + attribute \src "libresoc.v:44137.3-44166.6" + wire $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + attribute \src "libresoc.v:44285.3-44313.6" + wire width 2 $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] + attribute \src "libresoc.v:44343.3-44371.6" + wire $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] + attribute \src "libresoc.v:44459.3-44487.6" + wire width 32 $0\fus_oper_i_alu_shift_rot0__insn[31:0] + attribute \src "libresoc.v:44079.3-44107.6" + wire width 7 $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] + attribute \src "libresoc.v:44256.3-44284.6" + wire $0\fus_oper_i_alu_shift_rot0__invert_in[0:0] + attribute \src "libresoc.v:44401.3-44429.6" + wire $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + attribute \src "libresoc.v:44430.3-44458.6" + wire $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] + attribute \src "libresoc.v:44197.3-44226.6" + wire $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + attribute \src "libresoc.v:44197.3-44226.6" + wire $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + attribute \src "libresoc.v:44314.3-44342.6" + wire $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] + attribute \src "libresoc.v:44372.3-44400.6" + wire $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] + attribute \src "libresoc.v:44167.3-44196.6" + wire $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + attribute \src "libresoc.v:44167.3-44196.6" + wire $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + attribute \src "libresoc.v:44227.3-44255.6" + wire $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + attribute \src "libresoc.v:47963.3-47991.6" + wire width 12 $0\fus_oper_i_alu_spr0__fn_unit[11:0] + attribute \src "libresoc.v:43145.3-43173.6" + wire width 32 $0\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "libresoc.v:47934.3-47962.6" + wire width 7 $0\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "libresoc.v:43174.3-43202.6" + wire $0\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "libresoc.v:47235.3-47263.6" + wire width 64 $0\fus_oper_i_alu_trap0__cia[63:0] + attribute \src "libresoc.v:47139.3-47167.6" + wire width 12 $0\fus_oper_i_alu_trap0__fn_unit[11:0] + attribute \src "libresoc.v:47177.3-47205.6" + wire width 32 $0\fus_oper_i_alu_trap0__insn[31:0] + attribute \src "libresoc.v:47092.3-47120.6" + wire width 7 $0\fus_oper_i_alu_trap0__insn_type[6:0] + attribute \src "libresoc.v:47264.3-47292.6" + wire $0\fus_oper_i_alu_trap0__is_32bit[0:0] + attribute \src "libresoc.v:47351.3-47379.6" + wire width 8 $0\fus_oper_i_alu_trap0__ldst_exc[7:0] + attribute \src "libresoc.v:47206.3-47234.6" + wire width 64 $0\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "libresoc.v:47322.3-47350.6" + wire width 13 $0\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "libresoc.v:47293.3-47321.6" + wire width 8 $0\fus_oper_i_alu_trap0__traptype[7:0] + attribute \src "libresoc.v:44810.3-44838.6" + wire $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + attribute \src "libresoc.v:44781.3-44809.6" + wire width 4 $0\fus_oper_i_ldst_ldst0__data_len[3:0] + attribute \src "libresoc.v:44575.3-44603.6" + wire width 12 $0\fus_oper_i_ldst_ldst0__fn_unit[11:0] + attribute \src "libresoc.v:44604.3-44633.6" + wire width 64 $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + attribute \src "libresoc.v:44604.3-44633.6" + wire $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + attribute \src "libresoc.v:44897.3-44925.6" + wire width 32 $0\fus_oper_i_ldst_ldst0__insn[31:0] + attribute \src "libresoc.v:44546.3-44574.6" + wire width 7 $0\fus_oper_i_ldst_ldst0__insn_type[6:0] + attribute \src "libresoc.v:44723.3-44751.6" + wire $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] + attribute \src "libresoc.v:44752.3-44780.6" + wire $0\fus_oper_i_ldst_ldst0__is_signed[0:0] + attribute \src "libresoc.v:44868.3-44896.6" + wire width 2 $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + attribute \src "libresoc.v:44693.3-44722.6" + wire $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] + attribute \src "libresoc.v:44693.3-44722.6" + wire $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] + attribute \src "libresoc.v:44663.3-44692.6" + wire $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] + attribute \src "libresoc.v:44663.3-44692.6" + wire $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] + attribute \src "libresoc.v:44839.3-44867.6" + wire $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] + attribute \src "libresoc.v:44634.3-44662.6" + wire $0\fus_oper_i_ldst_ldst0__zero_a[0:0] + attribute \src "libresoc.v:45012.3-45021.6" + wire width 64 $0\fus_src1_i$40[63:0]$2464 + attribute \src "libresoc.v:45031.3-45040.6" + wire width 64 $0\fus_src1_i$43[63:0]$2470 + attribute \src "libresoc.v:45050.3-45059.6" + wire width 64 $0\fus_src1_i$46[63:0]$2476 + attribute \src "libresoc.v:45069.3-45078.6" + wire width 64 $0\fus_src1_i$49[63:0]$2482 + attribute \src "libresoc.v:45088.3-45097.6" + wire width 64 $0\fus_src1_i$52[63:0]$2488 + attribute \src "libresoc.v:45107.3-45116.6" + wire width 64 $0\fus_src1_i$55[63:0]$2494 + attribute \src "libresoc.v:45126.3-45135.6" + wire width 64 $0\fus_src1_i$58[63:0]$2500 + attribute \src "libresoc.v:45145.3-45154.6" + wire width 64 $0\fus_src1_i$61[63:0]$2506 + attribute \src "libresoc.v:45926.3-45935.6" + wire width 64 $0\fus_src1_i$84[63:0]$2669 + attribute \src "libresoc.v:44993.3-45002.6" + wire width 64 $0\fus_src1_i[63:0] + attribute \src "libresoc.v:45183.3-45192.6" + wire width 64 $0\fus_src2_i$62[63:0]$2516 + attribute \src "libresoc.v:45202.3-45211.6" + wire width 64 $0\fus_src2_i$63[63:0]$2522 + attribute \src "libresoc.v:45221.3-45230.6" + wire width 64 $0\fus_src2_i$64[63:0]$2528 + attribute \src "libresoc.v:45240.3-45249.6" + wire width 64 $0\fus_src2_i$65[63:0]$2534 + attribute \src "libresoc.v:45259.3-45268.6" + wire width 64 $0\fus_src2_i$66[63:0]$2540 + attribute \src "libresoc.v:45278.3-45287.6" + wire width 64 $0\fus_src2_i$67[63:0]$2546 + attribute \src "libresoc.v:45297.3-45306.6" + wire width 64 $0\fus_src2_i$68[63:0]$2552 + attribute \src "libresoc.v:46041.3-46050.6" + wire width 64 $0\fus_src2_i$87[63:0]$2689 + attribute \src "libresoc.v:46108.3-46117.6" + wire width 64 $0\fus_src2_i$89[63:0]$2702 + attribute \src "libresoc.v:45164.3-45173.6" + wire width 64 $0\fus_src2_i[63:0] + attribute \src "libresoc.v:45335.3-45344.6" + wire width 64 $0\fus_src3_i$69[63:0]$2562 + attribute \src "libresoc.v:45381.3-45390.6" + wire $0\fus_src3_i$70[0:0]$2574 + attribute \src "libresoc.v:45491.3-45500.6" + wire $0\fus_src3_i$71[0:0]$2581 + attribute \src "libresoc.v:45550.3-45559.6" + wire $0\fus_src3_i$72[0:0]$2596 + attribute \src "libresoc.v:45569.3-45578.6" + wire $0\fus_src3_i$73[0:0]$2602 + attribute \src "libresoc.v:45771.3-45780.6" + wire width 32 $0\fus_src3_i$77[31:0]$2637 + attribute \src "libresoc.v:45839.3-45848.6" + wire width 4 $0\fus_src3_i$81[3:0]$2650 + attribute \src "libresoc.v:45945.3-45954.6" + wire width 64 $0\fus_src3_i$85[63:0]$2675 + attribute \src "libresoc.v:45993.3-46002.6" + wire width 64 $0\fus_src3_i$86[63:0]$2682 + attribute \src "libresoc.v:45316.3-45325.6" + wire width 64 $0\fus_src3_i[63:0] + attribute \src "libresoc.v:45617.3-45626.6" + wire $0\fus_src4_i$74[0:0]$2609 + attribute \src "libresoc.v:45665.3-45674.6" + wire width 2 $0\fus_src4_i$75[1:0]$2616 + attribute \src "libresoc.v:45820.3-45829.6" + wire width 4 $0\fus_src4_i$78[3:0]$2644 + attribute \src "libresoc.v:46060.3-46069.6" + wire width 64 $0\fus_src4_i$88[63:0]$2695 + attribute \src "libresoc.v:45510.3-45519.6" + wire $0\fus_src4_i[0:0] + attribute \src "libresoc.v:45752.3-45761.6" + wire width 2 $0\fus_src5_i$76[1:0]$2631 + attribute \src "libresoc.v:45858.3-45867.6" + wire width 4 $0\fus_src5_i$82[3:0]$2656 + attribute \src "libresoc.v:45733.3-45742.6" + wire width 2 $0\fus_src5_i[1:0] + attribute \src "libresoc.v:45907.3-45916.6" + wire width 4 $0\fus_src6_i$83[3:0]$2663 + attribute \src "libresoc.v:45684.3-45693.6" + wire width 2 $0\fus_src6_i[1:0] + attribute \src "libresoc.v:35746.7-35746.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:46194.3-46202.6" + wire $0\wr_pick_dly$1000$next[0:0]$2713 + attribute \src "libresoc.v:42326.3-42327.51" + wire $0\wr_pick_dly$1000[0:0]$2307 + attribute \src "libresoc.v:41156.7-41156.32" + wire $0\wr_pick_dly$1000[0:0]$2945 + attribute \src "libresoc.v:46232.3-46240.6" + wire $0\wr_pick_dly$1021$next[0:0]$2717 + attribute \src "libresoc.v:42324.3-42325.51" + wire $0\wr_pick_dly$1021[0:0]$2305 + attribute \src "libresoc.v:41160.7-41160.32" + wire $0\wr_pick_dly$1021[0:0]$2947 + attribute \src "libresoc.v:46270.3-46278.6" + wire $0\wr_pick_dly$1039$next[0:0]$2721 + attribute \src "libresoc.v:42322.3-42323.51" + wire $0\wr_pick_dly$1039[0:0]$2303 + attribute \src "libresoc.v:41164.7-41164.32" + wire $0\wr_pick_dly$1039[0:0]$2949 + attribute \src "libresoc.v:46279.3-46287.6" + wire $0\wr_pick_dly$1061$next[0:0]$2724 + attribute \src "libresoc.v:42320.3-42321.51" + wire $0\wr_pick_dly$1061[0:0]$2301 + attribute \src "libresoc.v:41168.7-41168.32" + wire $0\wr_pick_dly$1061[0:0]$2951 + attribute \src "libresoc.v:46317.3-46325.6" + wire $0\wr_pick_dly$1081$next[0:0]$2728 + attribute \src "libresoc.v:42318.3-42319.51" + wire $0\wr_pick_dly$1081[0:0]$2299 + attribute \src "libresoc.v:41172.7-41172.32" + wire $0\wr_pick_dly$1081[0:0]$2953 + attribute \src "libresoc.v:46355.3-46363.6" + wire $0\wr_pick_dly$1101$next[0:0]$2732 + attribute \src "libresoc.v:42316.3-42317.51" + wire $0\wr_pick_dly$1101[0:0]$2297 + attribute \src "libresoc.v:41176.7-41176.32" + wire $0\wr_pick_dly$1101[0:0]$2955 + attribute \src "libresoc.v:46364.3-46372.6" + wire $0\wr_pick_dly$1120$next[0:0]$2735 + attribute \src "libresoc.v:42314.3-42315.51" + wire $0\wr_pick_dly$1120[0:0]$2295 + attribute \src "libresoc.v:41180.7-41180.32" + wire $0\wr_pick_dly$1120[0:0]$2957 + attribute \src "libresoc.v:46402.3-46410.6" + wire $0\wr_pick_dly$1138$next[0:0]$2739 + attribute \src "libresoc.v:42312.3-42313.51" + wire $0\wr_pick_dly$1138[0:0]$2293 + attribute \src "libresoc.v:41184.7-41184.32" + wire $0\wr_pick_dly$1138[0:0]$2959 + attribute \src "libresoc.v:46440.3-46448.6" + wire $0\wr_pick_dly$1211$next[0:0]$2743 + attribute \src "libresoc.v:42310.3-42311.51" + wire $0\wr_pick_dly$1211[0:0]$2291 + attribute \src "libresoc.v:41188.7-41188.32" + wire $0\wr_pick_dly$1211[0:0]$2961 + attribute \src "libresoc.v:46478.3-46486.6" + wire $0\wr_pick_dly$1239$next[0:0]$2747 + attribute \src "libresoc.v:42308.3-42309.51" + wire $0\wr_pick_dly$1239[0:0]$2289 + attribute \src "libresoc.v:41192.7-41192.32" + wire $0\wr_pick_dly$1239[0:0]$2963 + attribute \src "libresoc.v:46516.3-46524.6" + wire $0\wr_pick_dly$1259$next[0:0]$2751 + attribute \src "libresoc.v:42306.3-42307.51" + wire $0\wr_pick_dly$1259[0:0]$2287 + attribute \src "libresoc.v:41196.7-41196.32" + wire $0\wr_pick_dly$1259[0:0]$2965 + attribute \src "libresoc.v:46525.3-46533.6" + wire $0\wr_pick_dly$1279$next[0:0]$2754 + attribute \src "libresoc.v:42304.3-42305.51" + wire $0\wr_pick_dly$1279[0:0]$2285 + attribute \src "libresoc.v:41200.7-41200.32" + wire $0\wr_pick_dly$1279[0:0]$2967 + attribute \src "libresoc.v:46563.3-46571.6" + wire $0\wr_pick_dly$1299$next[0:0]$2758 + attribute \src "libresoc.v:42302.3-42303.51" + wire $0\wr_pick_dly$1299[0:0]$2283 + attribute \src "libresoc.v:41204.7-41204.32" + wire $0\wr_pick_dly$1299[0:0]$2969 + attribute \src "libresoc.v:46572.3-46580.6" + wire $0\wr_pick_dly$1319$next[0:0]$2761 + attribute \src "libresoc.v:42300.3-42301.51" + wire $0\wr_pick_dly$1319[0:0]$2281 + attribute \src "libresoc.v:41208.7-41208.32" + wire $0\wr_pick_dly$1319[0:0]$2971 + attribute \src "libresoc.v:46610.3-46618.6" + wire $0\wr_pick_dly$1339$next[0:0]$2765 + attribute \src "libresoc.v:42298.3-42299.51" + wire $0\wr_pick_dly$1339[0:0]$2279 + attribute \src "libresoc.v:41212.7-41212.32" + wire $0\wr_pick_dly$1339[0:0]$2973 + attribute \src "libresoc.v:46648.3-46656.6" + wire $0\wr_pick_dly$1386$next[0:0]$2773 + attribute \src "libresoc.v:42296.3-42297.51" + wire $0\wr_pick_dly$1386[0:0]$2277 + attribute \src "libresoc.v:41216.7-41216.32" + wire $0\wr_pick_dly$1386[0:0]$2975 + attribute \src "libresoc.v:46686.3-46694.6" + wire $0\wr_pick_dly$1402$next[0:0]$2781 + attribute \src "libresoc.v:42294.3-42295.51" + wire $0\wr_pick_dly$1402[0:0]$2275 + attribute \src "libresoc.v:41220.7-41220.32" + wire $0\wr_pick_dly$1402[0:0]$2977 + attribute \src "libresoc.v:46695.3-46703.6" + wire $0\wr_pick_dly$1418$next[0:0]$2784 + attribute \src "libresoc.v:42292.3-42293.51" + wire $0\wr_pick_dly$1418[0:0]$2273 + attribute \src "libresoc.v:41224.7-41224.32" + wire $0\wr_pick_dly$1418[0:0]$2979 + attribute \src "libresoc.v:46733.3-46741.6" + wire $0\wr_pick_dly$1452$next[0:0]$2788 + attribute \src "libresoc.v:42290.3-42291.51" + wire $0\wr_pick_dly$1452[0:0]$2271 + attribute \src "libresoc.v:41228.7-41228.32" + wire $0\wr_pick_dly$1452[0:0]$2981 + attribute \src "libresoc.v:46771.3-46779.6" + wire $0\wr_pick_dly$1468$next[0:0]$2792 + attribute \src "libresoc.v:42288.3-42289.51" + wire $0\wr_pick_dly$1468[0:0]$2269 + attribute \src "libresoc.v:41232.7-41232.32" + wire $0\wr_pick_dly$1468[0:0]$2983 + attribute \src "libresoc.v:46780.3-46788.6" + wire $0\wr_pick_dly$1484$next[0:0]$2795 + attribute \src "libresoc.v:42286.3-42287.51" + wire $0\wr_pick_dly$1484[0:0]$2267 + attribute \src "libresoc.v:41236.7-41236.32" + wire $0\wr_pick_dly$1484[0:0]$2985 + attribute \src "libresoc.v:46818.3-46826.6" + wire $0\wr_pick_dly$1500$next[0:0]$2799 + attribute \src "libresoc.v:42284.3-42285.51" + wire $0\wr_pick_dly$1500[0:0]$2265 + attribute \src "libresoc.v:41240.7-41240.32" + wire $0\wr_pick_dly$1500[0:0]$2987 + attribute \src "libresoc.v:46856.3-46864.6" + wire $0\wr_pick_dly$1536$next[0:0]$2803 + attribute \src "libresoc.v:42282.3-42283.51" + wire $0\wr_pick_dly$1536[0:0]$2263 + attribute \src "libresoc.v:41244.7-41244.32" + wire $0\wr_pick_dly$1536[0:0]$2989 + attribute \src "libresoc.v:46865.3-46873.6" + wire $0\wr_pick_dly$1552$next[0:0]$2806 + attribute \src "libresoc.v:42280.3-42281.51" + wire $0\wr_pick_dly$1552[0:0]$2261 + attribute \src "libresoc.v:41248.7-41248.32" + wire $0\wr_pick_dly$1552[0:0]$2991 + attribute \src "libresoc.v:46904.3-46912.6" + wire $0\wr_pick_dly$1568$next[0:0]$2810 + attribute \src "libresoc.v:42278.3-42279.51" + wire $0\wr_pick_dly$1568[0:0]$2259 + attribute \src "libresoc.v:41252.7-41252.32" + wire $0\wr_pick_dly$1568[0:0]$2993 + attribute \src "libresoc.v:46913.3-46921.6" + wire $0\wr_pick_dly$1584$next[0:0]$2813 + attribute \src "libresoc.v:42276.3-42277.51" + wire $0\wr_pick_dly$1584[0:0]$2257 + attribute \src "libresoc.v:41256.7-41256.32" + wire $0\wr_pick_dly$1584[0:0]$2995 + attribute \src "libresoc.v:46922.3-46930.6" + wire $0\wr_pick_dly$1626$next[0:0]$2816 + attribute \src "libresoc.v:42274.3-42275.51" + wire $0\wr_pick_dly$1626[0:0]$2255 + attribute \src "libresoc.v:41260.7-41260.32" + wire $0\wr_pick_dly$1626[0:0]$2997 + attribute \src "libresoc.v:46960.3-46968.6" + wire $0\wr_pick_dly$1645$next[0:0]$2820 + attribute \src "libresoc.v:42272.3-42273.51" + wire $0\wr_pick_dly$1645[0:0]$2253 + attribute \src "libresoc.v:41264.7-41264.32" + wire $0\wr_pick_dly$1645[0:0]$2999 + attribute \src "libresoc.v:46998.3-47006.6" + wire $0\wr_pick_dly$1661$next[0:0]$2824 + attribute \src "libresoc.v:42270.3-42271.51" + wire $0\wr_pick_dly$1661[0:0]$2251 + attribute \src "libresoc.v:41268.7-41268.32" + wire $0\wr_pick_dly$1661[0:0]$3001 + attribute \src "libresoc.v:47007.3-47015.6" + wire $0\wr_pick_dly$1677$next[0:0]$2827 + attribute \src "libresoc.v:42268.3-42269.51" + wire $0\wr_pick_dly$1677[0:0]$2249 + attribute \src "libresoc.v:41272.7-41272.32" + wire $0\wr_pick_dly$1677[0:0]$3003 + attribute \src "libresoc.v:47045.3-47053.6" + wire $0\wr_pick_dly$1693$next[0:0]$2835 + attribute \src "libresoc.v:42266.3-42267.51" + wire $0\wr_pick_dly$1693[0:0]$2247 + attribute \src "libresoc.v:41276.7-41276.32" + wire $0\wr_pick_dly$1693[0:0]$3005 + attribute \src "libresoc.v:47083.3-47091.6" + wire $0\wr_pick_dly$1737$next[0:0]$2843 + attribute \src "libresoc.v:42264.3-42265.51" + wire $0\wr_pick_dly$1737[0:0]$2245 + attribute \src "libresoc.v:41280.7-41280.32" + wire $0\wr_pick_dly$1737[0:0]$3007 + attribute \src "libresoc.v:47121.3-47129.6" + wire $0\wr_pick_dly$1753$next[0:0]$2847 + attribute \src "libresoc.v:42262.3-42263.51" + wire $0\wr_pick_dly$1753[0:0]$2243 + attribute \src "libresoc.v:41284.7-41284.32" + wire $0\wr_pick_dly$1753[0:0]$3009 + attribute \src "libresoc.v:47130.3-47138.6" + wire $0\wr_pick_dly$1777$next[0:0]$2850 + attribute \src "libresoc.v:42260.3-42261.51" + wire $0\wr_pick_dly$1777[0:0]$2241 + attribute \src "libresoc.v:41288.7-41288.32" + wire $0\wr_pick_dly$1777[0:0]$3011 + attribute \src "libresoc.v:47168.3-47176.6" + wire $0\wr_pick_dly$1797$next[0:0]$2854 + attribute \src "libresoc.v:42258.3-42259.51" + wire $0\wr_pick_dly$1797[0:0]$2239 + attribute \src "libresoc.v:41292.7-41292.32" + wire $0\wr_pick_dly$1797[0:0]$3013 + attribute \src "libresoc.v:46185.3-46193.6" + wire $0\wr_pick_dly$981$next[0:0]$2710 + attribute \src "libresoc.v:42328.3-42329.49" + wire $0\wr_pick_dly$981[0:0]$2309 + attribute \src "libresoc.v:41296.7-41296.31" + wire $0\wr_pick_dly$981[0:0]$3015 + attribute \src "libresoc.v:46147.3-46155.6" + wire $0\wr_pick_dly$next[0:0]$2706 + attribute \src "libresoc.v:42330.3-42331.39" + wire $0\wr_pick_dly[0:0] + attribute \src "libresoc.v:45391.3-45481.6" + wire $10\corebusy_o[0:0] + attribute \src "libresoc.v:45391.3-45481.6" + wire $11\corebusy_o[0:0] + attribute \src "libresoc.v:45391.3-45481.6" + wire $12\corebusy_o[0:0] + attribute \src "libresoc.v:45391.3-45481.6" + wire $13\corebusy_o[0:0] + attribute \src "libresoc.v:45520.3-45540.6" + wire $1\core_terminate_o$next[0:0]$2589 + attribute \src "libresoc.v:37778.7-37778.30" + wire $1\core_terminate_o[0:0] + attribute \src "libresoc.v:45391.3-45481.6" + wire $1\corebusy_o[0:0] + attribute \src "libresoc.v:45345.3-45371.6" + wire width 2 $1\counter$next[1:0]$2566 + attribute \src "libresoc.v:37791.13-37791.27" + wire width 2 $1\counter[1:0] + attribute \src "libresoc.v:45830.3-45838.6" + wire $1\dp_CR_cr_a_branch0_1$next[0:0]$2648 + attribute \src "libresoc.v:38921.7-38921.34" + wire $1\dp_CR_cr_a_branch0_1[0:0] + attribute \src "libresoc.v:45811.3-45819.6" + wire $1\dp_CR_cr_a_cr0_0$next[0:0]$2642 + attribute \src "libresoc.v:38925.7-38925.30" + wire $1\dp_CR_cr_a_cr0_0[0:0] + attribute \src "libresoc.v:45849.3-45857.6" + wire $1\dp_CR_cr_b_cr0_0$next[0:0]$2654 + attribute \src "libresoc.v:38929.7-38929.30" + wire $1\dp_CR_cr_b_cr0_0[0:0] + attribute \src "libresoc.v:45898.3-45906.6" + wire $1\dp_CR_cr_c_cr0_0$next[0:0]$2661 + attribute \src "libresoc.v:38933.7-38933.30" + wire $1\dp_CR_cr_c_cr0_0[0:0] + attribute \src "libresoc.v:45762.3-45770.6" + wire $1\dp_CR_full_cr_cr0_0$next[0:0]$2635 + attribute \src "libresoc.v:38937.7-38937.33" + wire $1\dp_CR_full_cr_cr0_0[0:0] + attribute \src "libresoc.v:45917.3-45925.6" + wire $1\dp_FAST_fast1_branch0_0$next[0:0]$2667 + attribute \src "libresoc.v:38941.7-38941.37" + wire $1\dp_FAST_fast1_branch0_0[0:0] + attribute \src "libresoc.v:45984.3-45992.6" + wire $1\dp_FAST_fast1_spr0_2$next[0:0]$2680 + attribute \src "libresoc.v:38945.7-38945.34" + wire $1\dp_FAST_fast1_spr0_2[0:0] + attribute \src "libresoc.v:45936.3-45944.6" + wire $1\dp_FAST_fast1_trap0_1$next[0:0]$2673 + attribute \src "libresoc.v:38949.7-38949.35" + wire $1\dp_FAST_fast1_trap0_1[0:0] + attribute \src "libresoc.v:46032.3-46040.6" + wire $1\dp_FAST_fast2_branch0_0$next[0:0]$2687 + attribute \src "libresoc.v:38953.7-38953.37" + wire $1\dp_FAST_fast2_branch0_0[0:0] + attribute \src "libresoc.v:46051.3-46059.6" + wire $1\dp_FAST_fast2_trap0_1$next[0:0]$2693 + attribute \src "libresoc.v:38957.7-38957.35" + wire $1\dp_FAST_fast2_trap0_1[0:0] + attribute \src "libresoc.v:44984.3-44992.6" + wire $1\dp_INT_ra_alu0_0$next[0:0]$2458 + attribute \src "libresoc.v:38961.7-38961.30" + wire $1\dp_INT_ra_alu0_0[0:0] + attribute \src "libresoc.v:45003.3-45011.6" + wire $1\dp_INT_ra_cr0_1$next[0:0]$2462 + attribute \src "libresoc.v:38965.7-38965.29" + wire $1\dp_INT_ra_cr0_1[0:0] + attribute \src "libresoc.v:45079.3-45087.6" + wire $1\dp_INT_ra_div0_5$next[0:0]$2486 + attribute \src "libresoc.v:38969.7-38969.30" + wire $1\dp_INT_ra_div0_5[0:0] + attribute \src "libresoc.v:45136.3-45144.6" + wire $1\dp_INT_ra_ldst0_8$next[0:0]$2504 + attribute \src "libresoc.v:38973.7-38973.31" + wire $1\dp_INT_ra_ldst0_8[0:0] + attribute \src "libresoc.v:45041.3-45049.6" + wire $1\dp_INT_ra_logical0_3$next[0:0]$2474 + attribute \src "libresoc.v:38977.7-38977.34" + wire $1\dp_INT_ra_logical0_3[0:0] + attribute \src "libresoc.v:45098.3-45106.6" + wire $1\dp_INT_ra_mul0_6$next[0:0]$2492 + attribute \src "libresoc.v:38981.7-38981.30" + wire $1\dp_INT_ra_mul0_6[0:0] + attribute \src "libresoc.v:45117.3-45125.6" + wire $1\dp_INT_ra_shiftrot0_7$next[0:0]$2498 + attribute \src "libresoc.v:38985.7-38985.35" + wire $1\dp_INT_ra_shiftrot0_7[0:0] + attribute \src "libresoc.v:45060.3-45068.6" + wire $1\dp_INT_ra_spr0_4$next[0:0]$2480 + attribute \src "libresoc.v:38989.7-38989.30" + wire $1\dp_INT_ra_spr0_4[0:0] + attribute \src "libresoc.v:45022.3-45030.6" + wire $1\dp_INT_ra_trap0_2$next[0:0]$2468 + attribute \src "libresoc.v:38993.7-38993.31" + wire $1\dp_INT_ra_trap0_2[0:0] + attribute \src "libresoc.v:45155.3-45163.6" + wire $1\dp_INT_rb_alu0_0$next[0:0]$2510 + attribute \src "libresoc.v:38997.7-38997.30" + wire $1\dp_INT_rb_alu0_0[0:0] + attribute \src "libresoc.v:45174.3-45182.6" + wire $1\dp_INT_rb_cr0_1$next[0:0]$2514 + attribute \src "libresoc.v:39001.7-39001.29" + wire $1\dp_INT_rb_cr0_1[0:0] + attribute \src "libresoc.v:45231.3-45239.6" + wire $1\dp_INT_rb_div0_4$next[0:0]$2532 + attribute \src "libresoc.v:39005.7-39005.30" + wire $1\dp_INT_rb_div0_4[0:0] + attribute \src "libresoc.v:45288.3-45296.6" + wire $1\dp_INT_rb_ldst0_7$next[0:0]$2550 + attribute \src "libresoc.v:39009.7-39009.31" + wire $1\dp_INT_rb_ldst0_7[0:0] + attribute \src "libresoc.v:45212.3-45220.6" + wire $1\dp_INT_rb_logical0_3$next[0:0]$2526 + attribute \src "libresoc.v:39013.7-39013.34" + wire $1\dp_INT_rb_logical0_3[0:0] + attribute \src "libresoc.v:45250.3-45258.6" + wire $1\dp_INT_rb_mul0_5$next[0:0]$2538 + attribute \src "libresoc.v:39017.7-39017.30" + wire $1\dp_INT_rb_mul0_5[0:0] + attribute \src "libresoc.v:45269.3-45277.6" + wire $1\dp_INT_rb_shiftrot0_6$next[0:0]$2544 + attribute \src "libresoc.v:39021.7-39021.35" + wire $1\dp_INT_rb_shiftrot0_6[0:0] + attribute \src "libresoc.v:45193.3-45201.6" + wire $1\dp_INT_rb_trap0_2$next[0:0]$2520 + attribute \src "libresoc.v:39025.7-39025.31" + wire $1\dp_INT_rb_trap0_2[0:0] + attribute \src "libresoc.v:45326.3-45334.6" + wire $1\dp_INT_rc_ldst0_1$next[0:0]$2560 + attribute \src "libresoc.v:39029.7-39029.31" + wire $1\dp_INT_rc_ldst0_1[0:0] + attribute \src "libresoc.v:45307.3-45315.6" + wire $1\dp_INT_rc_shiftrot0_0$next[0:0]$2556 + attribute \src "libresoc.v:39033.7-39033.35" + wire $1\dp_INT_rc_shiftrot0_0[0:0] + attribute \src "libresoc.v:46099.3-46107.6" + wire $1\dp_SPR_spr1_spr0_0$next[0:0]$2700 + attribute \src "libresoc.v:39037.7-39037.32" + wire $1\dp_SPR_spr1_spr0_0[0:0] + attribute \src "libresoc.v:45627.3-45635.6" + wire $1\dp_XER_xer_ca_alu0_0$next[0:0]$2613 + attribute \src "libresoc.v:39041.7-39041.34" + wire $1\dp_XER_xer_ca_alu0_0[0:0] + attribute \src "libresoc.v:45694.3-45702.6" + wire $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2624 + attribute \src "libresoc.v:39045.7-39045.39" + wire $1\dp_XER_xer_ca_shiftrot0_2[0:0] + attribute \src "libresoc.v:45675.3-45683.6" + wire $1\dp_XER_xer_ca_spr0_1$next[0:0]$2620 + attribute \src "libresoc.v:39049.7-39049.34" + wire $1\dp_XER_xer_ca_spr0_1[0:0] + attribute \src "libresoc.v:45743.3-45751.6" + wire $1\dp_XER_xer_ov_spr0_0$next[0:0]$2629 + attribute \src "libresoc.v:39053.7-39053.34" + wire $1\dp_XER_xer_ov_spr0_0[0:0] + attribute \src "libresoc.v:45372.3-45380.6" + wire $1\dp_XER_xer_so_alu0_0$next[0:0]$2572 + attribute \src "libresoc.v:39057.7-39057.34" + wire $1\dp_XER_xer_so_alu0_0[0:0] + attribute \src "libresoc.v:45541.3-45549.6" + wire $1\dp_XER_xer_so_div0_3$next[0:0]$2594 + attribute \src "libresoc.v:39061.7-39061.34" + wire $1\dp_XER_xer_so_div0_3[0:0] + attribute \src "libresoc.v:45482.3-45490.6" + wire $1\dp_XER_xer_so_logical0_1$next[0:0]$2579 + attribute \src "libresoc.v:39065.7-39065.38" + wire $1\dp_XER_xer_so_logical0_1[0:0] + attribute \src "libresoc.v:45560.3-45568.6" + wire $1\dp_XER_xer_so_mul0_4$next[0:0]$2600 + attribute \src "libresoc.v:39069.7-39069.34" + wire $1\dp_XER_xer_so_mul0_4[0:0] + attribute \src "libresoc.v:45608.3-45616.6" + wire $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2607 + attribute \src "libresoc.v:39073.7-39073.39" + wire $1\dp_XER_xer_so_shiftrot0_5[0:0] + attribute \src "libresoc.v:45501.3-45509.6" + wire $1\dp_XER_xer_so_spr0_2$next[0:0]$2585 + attribute \src "libresoc.v:39077.7-39077.34" + wire $1\dp_XER_xer_so_spr0_2[0:0] + attribute \src "libresoc.v:46619.3-46647.6" + wire $1\fus_cu_issue_i$11[0:0]$2769 + attribute \src "libresoc.v:47016.3-47044.6" + wire $1\fus_cu_issue_i$14[0:0]$2831 + attribute \src "libresoc.v:47380.3-47408.6" + wire $1\fus_cu_issue_i$17[0:0]$2865 + attribute \src "libresoc.v:47876.3-47904.6" + wire $1\fus_cu_issue_i$20[0:0]$2890 + attribute \src "libresoc.v:43203.3-43231.6" + wire $1\fus_cu_issue_i$23[0:0]$2357 + attribute \src "libresoc.v:43699.3-43727.6" + wire $1\fus_cu_issue_i$26[0:0]$2382 + attribute \src "libresoc.v:44021.3-44049.6" + wire $1\fus_cu_issue_i$29[0:0]$2401 + attribute \src "libresoc.v:44488.3-44516.6" + wire $1\fus_cu_issue_i$32[0:0]$2425 + attribute \src "libresoc.v:44926.3-44954.6" + wire $1\fus_cu_issue_i$35[0:0]$2448 + attribute \src "libresoc.v:46411.3-46439.6" + wire $1\fus_cu_issue_i[0:0] + attribute \src "libresoc.v:46657.3-46685.6" + wire width 6 $1\fus_cu_rdmaskn_i$13[5:0]$2777 + attribute \src "libresoc.v:47054.3-47082.6" + wire width 3 $1\fus_cu_rdmaskn_i$16[2:0]$2839 + attribute \src "libresoc.v:47409.3-47437.6" + wire width 4 $1\fus_cu_rdmaskn_i$19[3:0]$2870 + attribute \src "libresoc.v:47905.3-47933.6" + wire width 3 $1\fus_cu_rdmaskn_i$22[2:0]$2895 + attribute \src "libresoc.v:43232.3-43260.6" + wire width 6 $1\fus_cu_rdmaskn_i$25[5:0]$2362 + attribute \src "libresoc.v:43728.3-43756.6" + wire width 3 $1\fus_cu_rdmaskn_i$28[2:0]$2387 + attribute \src "libresoc.v:44050.3-44078.6" + wire width 3 $1\fus_cu_rdmaskn_i$31[2:0]$2406 + attribute \src "libresoc.v:44517.3-44545.6" + wire width 5 $1\fus_cu_rdmaskn_i$34[4:0]$2430 + attribute \src "libresoc.v:44955.3-44983.6" + wire width 3 $1\fus_cu_rdmaskn_i$37[2:0]$2453 + attribute \src "libresoc.v:46449.3-46477.6" + wire width 4 $1\fus_cu_rdmaskn_i[3:0] + attribute \src "libresoc.v:46326.3-46354.6" + wire width 4 $1\fus_oper_i_alu_alu0__data_len[3:0] + attribute \src "libresoc.v:45636.3-45664.6" + wire width 12 $1\fus_oper_i_alu_alu0__fn_unit[11:0] + attribute \src "libresoc.v:45703.3-45732.6" + wire width 64 $1\fus_oper_i_alu_alu0__imm_data__data[63:0] + attribute \src "libresoc.v:45703.3-45732.6" + wire $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "libresoc.v:46156.3-46184.6" + wire width 2 $1\fus_oper_i_alu_alu0__input_carry[1:0] + attribute \src "libresoc.v:46373.3-46401.6" + wire width 32 $1\fus_oper_i_alu_alu0__insn[31:0] + attribute \src "libresoc.v:45579.3-45607.6" + wire width 7 $1\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "libresoc.v:45955.3-45983.6" + wire $1\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "libresoc.v:46070.3-46098.6" + wire $1\fus_oper_i_alu_alu0__invert_out[0:0] + attribute \src "libresoc.v:46241.3-46269.6" + wire $1\fus_oper_i_alu_alu0__is_32bit[0:0] + attribute \src "libresoc.v:46288.3-46316.6" + wire $1\fus_oper_i_alu_alu0__is_signed[0:0] + attribute \src "libresoc.v:45868.3-45897.6" + wire $1\fus_oper_i_alu_alu0__oe__oe[0:0] + attribute \src "libresoc.v:45868.3-45897.6" + wire $1\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "libresoc.v:46203.3-46231.6" + wire $1\fus_oper_i_alu_alu0__output_carry[0:0] + attribute \src "libresoc.v:45781.3-45810.6" + wire $1\fus_oper_i_alu_alu0__rc__ok[0:0] + attribute \src "libresoc.v:45781.3-45810.6" + wire $1\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "libresoc.v:46118.3-46146.6" + wire $1\fus_oper_i_alu_alu0__write_cr0[0:0] + attribute \src "libresoc.v:46003.3-46031.6" + wire $1\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "libresoc.v:46704.3-46732.6" + wire width 64 $1\fus_oper_i_alu_branch0__cia[63:0] + attribute \src "libresoc.v:46789.3-46817.6" + wire width 12 $1\fus_oper_i_alu_branch0__fn_unit[11:0] + attribute \src "libresoc.v:46874.3-46903.6" + wire width 64 $1\fus_oper_i_alu_branch0__imm_data__data[63:0] + attribute \src "libresoc.v:46874.3-46903.6" + wire $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] + attribute \src "libresoc.v:46827.3-46855.6" + wire width 32 $1\fus_oper_i_alu_branch0__insn[31:0] + attribute \src "libresoc.v:46742.3-46770.6" + wire width 7 $1\fus_oper_i_alu_branch0__insn_type[6:0] + attribute \src "libresoc.v:46969.3-46997.6" + wire $1\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "libresoc.v:46931.3-46959.6" + wire $1\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "libresoc.v:46534.3-46562.6" + wire width 12 $1\fus_oper_i_alu_cr0__fn_unit[11:0] + attribute \src "libresoc.v:46581.3-46609.6" + wire width 32 $1\fus_oper_i_alu_cr0__insn[31:0] + attribute \src "libresoc.v:46487.3-46515.6" + wire width 7 $1\fus_oper_i_alu_cr0__insn_type[6:0] + attribute \src "libresoc.v:43641.3-43669.6" + wire width 4 $1\fus_oper_i_alu_div0__data_len[3:0] + attribute \src "libresoc.v:43290.3-43318.6" + wire width 12 $1\fus_oper_i_alu_div0__fn_unit[11:0] + attribute \src "libresoc.v:43319.3-43348.6" + wire width 64 $1\fus_oper_i_alu_div0__imm_data__data[63:0] + attribute \src "libresoc.v:43319.3-43348.6" + wire $1\fus_oper_i_alu_div0__imm_data__ok[0:0] + attribute \src "libresoc.v:43467.3-43495.6" + wire width 2 $1\fus_oper_i_alu_div0__input_carry[1:0] + attribute \src "libresoc.v:43670.3-43698.6" + wire width 32 $1\fus_oper_i_alu_div0__insn[31:0] + attribute \src "libresoc.v:43261.3-43289.6" + wire width 7 $1\fus_oper_i_alu_div0__insn_type[6:0] + attribute \src "libresoc.v:43409.3-43437.6" + wire $1\fus_oper_i_alu_div0__invert_in[0:0] + attribute \src "libresoc.v:43496.3-43524.6" + wire $1\fus_oper_i_alu_div0__invert_out[0:0] + attribute \src "libresoc.v:43583.3-43611.6" + wire $1\fus_oper_i_alu_div0__is_32bit[0:0] + attribute \src "libresoc.v:43612.3-43640.6" + wire $1\fus_oper_i_alu_div0__is_signed[0:0] + attribute \src "libresoc.v:43379.3-43408.6" + wire $1\fus_oper_i_alu_div0__oe__oe[0:0] + attribute \src "libresoc.v:43379.3-43408.6" + wire $1\fus_oper_i_alu_div0__oe__ok[0:0] + attribute \src "libresoc.v:43554.3-43582.6" + wire $1\fus_oper_i_alu_div0__output_carry[0:0] + attribute \src "libresoc.v:43349.3-43378.6" + wire $1\fus_oper_i_alu_div0__rc__ok[0:0] + attribute \src "libresoc.v:43349.3-43378.6" + wire $1\fus_oper_i_alu_div0__rc__rc[0:0] + attribute \src "libresoc.v:43525.3-43553.6" + wire $1\fus_oper_i_alu_div0__write_cr0[0:0] + attribute \src "libresoc.v:43438.3-43466.6" + wire $1\fus_oper_i_alu_div0__zero_a[0:0] + attribute \src "libresoc.v:47818.3-47846.6" + wire width 4 $1\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "libresoc.v:47467.3-47495.6" + wire width 12 $1\fus_oper_i_alu_logical0__fn_unit[11:0] + attribute \src "libresoc.v:47496.3-47525.6" + wire width 64 $1\fus_oper_i_alu_logical0__imm_data__data[63:0] + attribute \src "libresoc.v:47496.3-47525.6" + wire $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] + attribute \src "libresoc.v:47644.3-47672.6" + wire width 2 $1\fus_oper_i_alu_logical0__input_carry[1:0] + attribute \src "libresoc.v:47847.3-47875.6" + wire width 32 $1\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "libresoc.v:47438.3-47466.6" + wire width 7 $1\fus_oper_i_alu_logical0__insn_type[6:0] + attribute \src "libresoc.v:47586.3-47614.6" + wire $1\fus_oper_i_alu_logical0__invert_in[0:0] + attribute \src "libresoc.v:47673.3-47701.6" + wire $1\fus_oper_i_alu_logical0__invert_out[0:0] + attribute \src "libresoc.v:47760.3-47788.6" + wire $1\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "libresoc.v:47789.3-47817.6" + wire $1\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "libresoc.v:47556.3-47585.6" + wire $1\fus_oper_i_alu_logical0__oe__oe[0:0] + attribute \src "libresoc.v:47556.3-47585.6" + wire $1\fus_oper_i_alu_logical0__oe__ok[0:0] + attribute \src "libresoc.v:47731.3-47759.6" + wire $1\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "libresoc.v:47526.3-47555.6" + wire $1\fus_oper_i_alu_logical0__rc__ok[0:0] + attribute \src "libresoc.v:47526.3-47555.6" + wire $1\fus_oper_i_alu_logical0__rc__rc[0:0] + attribute \src "libresoc.v:47702.3-47730.6" + wire $1\fus_oper_i_alu_logical0__write_cr0[0:0] + attribute \src "libresoc.v:47615.3-47643.6" + wire $1\fus_oper_i_alu_logical0__zero_a[0:0] + attribute \src "libresoc.v:43786.3-43814.6" + wire width 12 $1\fus_oper_i_alu_mul0__fn_unit[11:0] + attribute \src "libresoc.v:43815.3-43844.6" + wire width 64 $1\fus_oper_i_alu_mul0__imm_data__data[63:0] + attribute \src "libresoc.v:43815.3-43844.6" + wire $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] + attribute \src "libresoc.v:43992.3-44020.6" + wire width 32 $1\fus_oper_i_alu_mul0__insn[31:0] + attribute \src "libresoc.v:43757.3-43785.6" + wire width 7 $1\fus_oper_i_alu_mul0__insn_type[6:0] + attribute \src "libresoc.v:43934.3-43962.6" + wire $1\fus_oper_i_alu_mul0__is_32bit[0:0] + attribute \src "libresoc.v:43963.3-43991.6" + wire $1\fus_oper_i_alu_mul0__is_signed[0:0] + attribute \src "libresoc.v:43875.3-43904.6" + wire $1\fus_oper_i_alu_mul0__oe__oe[0:0] + attribute \src "libresoc.v:43875.3-43904.6" + wire $1\fus_oper_i_alu_mul0__oe__ok[0:0] + attribute \src "libresoc.v:43845.3-43874.6" + wire $1\fus_oper_i_alu_mul0__rc__ok[0:0] + attribute \src "libresoc.v:43845.3-43874.6" + wire $1\fus_oper_i_alu_mul0__rc__rc[0:0] + attribute \src "libresoc.v:43905.3-43933.6" + wire $1\fus_oper_i_alu_mul0__write_cr0[0:0] + attribute \src "libresoc.v:44108.3-44136.6" + wire width 12 $1\fus_oper_i_alu_shift_rot0__fn_unit[11:0] + attribute \src "libresoc.v:44137.3-44166.6" + wire width 64 $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + attribute \src "libresoc.v:44137.3-44166.6" + wire $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + attribute \src "libresoc.v:44285.3-44313.6" + wire width 2 $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] + attribute \src "libresoc.v:44343.3-44371.6" + wire $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] + attribute \src "libresoc.v:44459.3-44487.6" + wire width 32 $1\fus_oper_i_alu_shift_rot0__insn[31:0] + attribute \src "libresoc.v:44079.3-44107.6" + wire width 7 $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] + attribute \src "libresoc.v:44256.3-44284.6" + wire $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] + attribute \src "libresoc.v:44401.3-44429.6" + wire $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + attribute \src "libresoc.v:44430.3-44458.6" + wire $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] + attribute \src "libresoc.v:44197.3-44226.6" + wire $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + attribute \src "libresoc.v:44197.3-44226.6" + wire $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + attribute \src "libresoc.v:44314.3-44342.6" + wire $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] + attribute \src "libresoc.v:44372.3-44400.6" + wire $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] + attribute \src "libresoc.v:44167.3-44196.6" + wire $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + attribute \src "libresoc.v:44167.3-44196.6" + wire $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + attribute \src "libresoc.v:44227.3-44255.6" + wire $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + attribute \src "libresoc.v:47963.3-47991.6" + wire width 12 $1\fus_oper_i_alu_spr0__fn_unit[11:0] + attribute \src "libresoc.v:43145.3-43173.6" + wire width 32 $1\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "libresoc.v:47934.3-47962.6" + wire width 7 $1\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "libresoc.v:43174.3-43202.6" + wire $1\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "libresoc.v:47235.3-47263.6" + wire width 64 $1\fus_oper_i_alu_trap0__cia[63:0] + attribute \src "libresoc.v:47139.3-47167.6" + wire width 12 $1\fus_oper_i_alu_trap0__fn_unit[11:0] + attribute \src "libresoc.v:47177.3-47205.6" + wire width 32 $1\fus_oper_i_alu_trap0__insn[31:0] + attribute \src "libresoc.v:47092.3-47120.6" + wire width 7 $1\fus_oper_i_alu_trap0__insn_type[6:0] + attribute \src "libresoc.v:47264.3-47292.6" + wire $1\fus_oper_i_alu_trap0__is_32bit[0:0] + attribute \src "libresoc.v:47351.3-47379.6" + wire width 8 $1\fus_oper_i_alu_trap0__ldst_exc[7:0] + attribute \src "libresoc.v:47206.3-47234.6" + wire width 64 $1\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "libresoc.v:47322.3-47350.6" + wire width 13 $1\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "libresoc.v:47293.3-47321.6" + wire width 8 $1\fus_oper_i_alu_trap0__traptype[7:0] + attribute \src "libresoc.v:44810.3-44838.6" + wire $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + attribute \src "libresoc.v:44781.3-44809.6" + wire width 4 $1\fus_oper_i_ldst_ldst0__data_len[3:0] + attribute \src "libresoc.v:44575.3-44603.6" + wire width 12 $1\fus_oper_i_ldst_ldst0__fn_unit[11:0] + attribute \src "libresoc.v:44604.3-44633.6" + wire width 64 $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + attribute \src "libresoc.v:44604.3-44633.6" + wire $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + attribute \src "libresoc.v:44897.3-44925.6" + wire width 32 $1\fus_oper_i_ldst_ldst0__insn[31:0] + attribute \src "libresoc.v:44546.3-44574.6" + wire width 7 $1\fus_oper_i_ldst_ldst0__insn_type[6:0] + attribute \src "libresoc.v:44723.3-44751.6" + wire $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] + attribute \src "libresoc.v:44752.3-44780.6" + wire $1\fus_oper_i_ldst_ldst0__is_signed[0:0] + attribute \src "libresoc.v:44868.3-44896.6" + wire width 2 $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + attribute \src "libresoc.v:44693.3-44722.6" + wire $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] + attribute \src "libresoc.v:44693.3-44722.6" + wire $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] + attribute \src "libresoc.v:44663.3-44692.6" + wire $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] + attribute \src "libresoc.v:44663.3-44692.6" + wire $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] + attribute \src "libresoc.v:44839.3-44867.6" + wire $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] + attribute \src "libresoc.v:44634.3-44662.6" + wire $1\fus_oper_i_ldst_ldst0__zero_a[0:0] + attribute \src "libresoc.v:45012.3-45021.6" + wire width 64 $1\fus_src1_i$40[63:0]$2465 + attribute \src "libresoc.v:45031.3-45040.6" + wire width 64 $1\fus_src1_i$43[63:0]$2471 + attribute \src "libresoc.v:45050.3-45059.6" + wire width 64 $1\fus_src1_i$46[63:0]$2477 + attribute \src "libresoc.v:45069.3-45078.6" + wire width 64 $1\fus_src1_i$49[63:0]$2483 + attribute \src "libresoc.v:45088.3-45097.6" + wire width 64 $1\fus_src1_i$52[63:0]$2489 + attribute \src "libresoc.v:45107.3-45116.6" + wire width 64 $1\fus_src1_i$55[63:0]$2495 + attribute \src "libresoc.v:45126.3-45135.6" + wire width 64 $1\fus_src1_i$58[63:0]$2501 + attribute \src "libresoc.v:45145.3-45154.6" + wire width 64 $1\fus_src1_i$61[63:0]$2507 + attribute \src "libresoc.v:45926.3-45935.6" + wire width 64 $1\fus_src1_i$84[63:0]$2670 + attribute \src "libresoc.v:44993.3-45002.6" + wire width 64 $1\fus_src1_i[63:0] + attribute \src "libresoc.v:45183.3-45192.6" + wire width 64 $1\fus_src2_i$62[63:0]$2517 + attribute \src "libresoc.v:45202.3-45211.6" + wire width 64 $1\fus_src2_i$63[63:0]$2523 + attribute \src "libresoc.v:45221.3-45230.6" + wire width 64 $1\fus_src2_i$64[63:0]$2529 + attribute \src "libresoc.v:45240.3-45249.6" + wire width 64 $1\fus_src2_i$65[63:0]$2535 + attribute \src "libresoc.v:45259.3-45268.6" + wire width 64 $1\fus_src2_i$66[63:0]$2541 + attribute \src "libresoc.v:45278.3-45287.6" + wire width 64 $1\fus_src2_i$67[63:0]$2547 + attribute \src "libresoc.v:45297.3-45306.6" + wire width 64 $1\fus_src2_i$68[63:0]$2553 + attribute \src "libresoc.v:46041.3-46050.6" + wire width 64 $1\fus_src2_i$87[63:0]$2690 + attribute \src "libresoc.v:46108.3-46117.6" + wire width 64 $1\fus_src2_i$89[63:0]$2703 + attribute \src "libresoc.v:45164.3-45173.6" + wire width 64 $1\fus_src2_i[63:0] + attribute \src "libresoc.v:45335.3-45344.6" + wire width 64 $1\fus_src3_i$69[63:0]$2563 + attribute \src "libresoc.v:45381.3-45390.6" + wire $1\fus_src3_i$70[0:0]$2575 + attribute \src "libresoc.v:45491.3-45500.6" + wire $1\fus_src3_i$71[0:0]$2582 + attribute \src "libresoc.v:45550.3-45559.6" + wire $1\fus_src3_i$72[0:0]$2597 + attribute \src "libresoc.v:45569.3-45578.6" + wire $1\fus_src3_i$73[0:0]$2603 + attribute \src "libresoc.v:45771.3-45780.6" + wire width 32 $1\fus_src3_i$77[31:0]$2638 + attribute \src "libresoc.v:45839.3-45848.6" + wire width 4 $1\fus_src3_i$81[3:0]$2651 + attribute \src "libresoc.v:45945.3-45954.6" + wire width 64 $1\fus_src3_i$85[63:0]$2676 + attribute \src "libresoc.v:45993.3-46002.6" + wire width 64 $1\fus_src3_i$86[63:0]$2683 + attribute \src "libresoc.v:45316.3-45325.6" + wire width 64 $1\fus_src3_i[63:0] + attribute \src "libresoc.v:45617.3-45626.6" + wire $1\fus_src4_i$74[0:0]$2610 + attribute \src "libresoc.v:45665.3-45674.6" + wire width 2 $1\fus_src4_i$75[1:0]$2617 + attribute \src "libresoc.v:45820.3-45829.6" + wire width 4 $1\fus_src4_i$78[3:0]$2645 + attribute \src "libresoc.v:46060.3-46069.6" + wire width 64 $1\fus_src4_i$88[63:0]$2696 + attribute \src "libresoc.v:45510.3-45519.6" + wire $1\fus_src4_i[0:0] + attribute \src "libresoc.v:45752.3-45761.6" + wire width 2 $1\fus_src5_i$76[1:0]$2632 + attribute \src "libresoc.v:45858.3-45867.6" + wire width 4 $1\fus_src5_i$82[3:0]$2657 + attribute \src "libresoc.v:45733.3-45742.6" + wire width 2 $1\fus_src5_i[1:0] + attribute \src "libresoc.v:45907.3-45916.6" + wire width 4 $1\fus_src6_i$83[3:0]$2664 + attribute \src "libresoc.v:45684.3-45693.6" + wire width 2 $1\fus_src6_i[1:0] + attribute \src "libresoc.v:46194.3-46202.6" + wire $1\wr_pick_dly$1000$next[0:0]$2714 + attribute \src "libresoc.v:46232.3-46240.6" + wire $1\wr_pick_dly$1021$next[0:0]$2718 + attribute \src "libresoc.v:46270.3-46278.6" + wire $1\wr_pick_dly$1039$next[0:0]$2722 + attribute \src "libresoc.v:46279.3-46287.6" + wire $1\wr_pick_dly$1061$next[0:0]$2725 + attribute \src "libresoc.v:46317.3-46325.6" + wire $1\wr_pick_dly$1081$next[0:0]$2729 + attribute \src "libresoc.v:46355.3-46363.6" + wire $1\wr_pick_dly$1101$next[0:0]$2733 + attribute \src "libresoc.v:46364.3-46372.6" + wire $1\wr_pick_dly$1120$next[0:0]$2736 + attribute \src "libresoc.v:46402.3-46410.6" + wire $1\wr_pick_dly$1138$next[0:0]$2740 + attribute \src "libresoc.v:46440.3-46448.6" + wire $1\wr_pick_dly$1211$next[0:0]$2744 + attribute \src "libresoc.v:46478.3-46486.6" + wire $1\wr_pick_dly$1239$next[0:0]$2748 + attribute \src "libresoc.v:46516.3-46524.6" + wire $1\wr_pick_dly$1259$next[0:0]$2752 + attribute \src "libresoc.v:46525.3-46533.6" + wire $1\wr_pick_dly$1279$next[0:0]$2755 + attribute \src "libresoc.v:46563.3-46571.6" + wire $1\wr_pick_dly$1299$next[0:0]$2759 + attribute \src "libresoc.v:46572.3-46580.6" + wire $1\wr_pick_dly$1319$next[0:0]$2762 + attribute \src "libresoc.v:46610.3-46618.6" + wire $1\wr_pick_dly$1339$next[0:0]$2766 + attribute \src "libresoc.v:46648.3-46656.6" + wire $1\wr_pick_dly$1386$next[0:0]$2774 + attribute \src "libresoc.v:46686.3-46694.6" + wire $1\wr_pick_dly$1402$next[0:0]$2782 + attribute \src "libresoc.v:46695.3-46703.6" + wire $1\wr_pick_dly$1418$next[0:0]$2785 + attribute \src "libresoc.v:46733.3-46741.6" + wire $1\wr_pick_dly$1452$next[0:0]$2789 + attribute \src "libresoc.v:46771.3-46779.6" + wire $1\wr_pick_dly$1468$next[0:0]$2793 + attribute \src "libresoc.v:46780.3-46788.6" + wire $1\wr_pick_dly$1484$next[0:0]$2796 + attribute \src "libresoc.v:46818.3-46826.6" + wire $1\wr_pick_dly$1500$next[0:0]$2800 + attribute \src "libresoc.v:46856.3-46864.6" + wire $1\wr_pick_dly$1536$next[0:0]$2804 + attribute \src "libresoc.v:46865.3-46873.6" + wire $1\wr_pick_dly$1552$next[0:0]$2807 + attribute \src "libresoc.v:46904.3-46912.6" + wire $1\wr_pick_dly$1568$next[0:0]$2811 + attribute \src "libresoc.v:46913.3-46921.6" + wire $1\wr_pick_dly$1584$next[0:0]$2814 + attribute \src "libresoc.v:46922.3-46930.6" + wire $1\wr_pick_dly$1626$next[0:0]$2817 + attribute \src "libresoc.v:46960.3-46968.6" + wire $1\wr_pick_dly$1645$next[0:0]$2821 + attribute \src "libresoc.v:46998.3-47006.6" + wire $1\wr_pick_dly$1661$next[0:0]$2825 + attribute \src "libresoc.v:47007.3-47015.6" + wire $1\wr_pick_dly$1677$next[0:0]$2828 + attribute \src "libresoc.v:47045.3-47053.6" + wire $1\wr_pick_dly$1693$next[0:0]$2836 + attribute \src "libresoc.v:47083.3-47091.6" + wire $1\wr_pick_dly$1737$next[0:0]$2844 + attribute \src "libresoc.v:47121.3-47129.6" + wire $1\wr_pick_dly$1753$next[0:0]$2848 + attribute \src "libresoc.v:47130.3-47138.6" + wire $1\wr_pick_dly$1777$next[0:0]$2851 + attribute \src "libresoc.v:47168.3-47176.6" + wire $1\wr_pick_dly$1797$next[0:0]$2855 + attribute \src "libresoc.v:46185.3-46193.6" + wire $1\wr_pick_dly$981$next[0:0]$2711 + attribute \src "libresoc.v:46147.3-46155.6" + wire $1\wr_pick_dly$next[0:0]$2707 + attribute \src "libresoc.v:41154.7-41154.25" + wire $1\wr_pick_dly[0:0] + attribute \src "libresoc.v:45520.3-45540.6" + wire $2\core_terminate_o$next[0:0]$2590 + attribute \src "libresoc.v:45391.3-45481.6" + wire $2\corebusy_o[0:0] + attribute \src "libresoc.v:45345.3-45371.6" + wire width 2 $2\counter$next[1:0]$2567 + attribute \src "libresoc.v:46619.3-46647.6" + wire $2\fus_cu_issue_i$11[0:0]$2770 + attribute \src "libresoc.v:47016.3-47044.6" + wire $2\fus_cu_issue_i$14[0:0]$2832 + attribute \src "libresoc.v:47380.3-47408.6" + wire $2\fus_cu_issue_i$17[0:0]$2866 + attribute \src "libresoc.v:47876.3-47904.6" + wire $2\fus_cu_issue_i$20[0:0]$2891 + attribute \src "libresoc.v:43203.3-43231.6" + wire $2\fus_cu_issue_i$23[0:0]$2358 + attribute \src "libresoc.v:43699.3-43727.6" + wire $2\fus_cu_issue_i$26[0:0]$2383 + attribute \src "libresoc.v:44021.3-44049.6" + wire $2\fus_cu_issue_i$29[0:0]$2402 + attribute \src "libresoc.v:44488.3-44516.6" + wire $2\fus_cu_issue_i$32[0:0]$2426 + attribute \src "libresoc.v:44926.3-44954.6" + wire $2\fus_cu_issue_i$35[0:0]$2449 + attribute \src "libresoc.v:46411.3-46439.6" + wire $2\fus_cu_issue_i[0:0] + attribute \src "libresoc.v:46657.3-46685.6" + wire width 6 $2\fus_cu_rdmaskn_i$13[5:0]$2778 + attribute \src "libresoc.v:47054.3-47082.6" + wire width 3 $2\fus_cu_rdmaskn_i$16[2:0]$2840 + attribute \src "libresoc.v:47409.3-47437.6" + wire width 4 $2\fus_cu_rdmaskn_i$19[3:0]$2871 + attribute \src "libresoc.v:47905.3-47933.6" + wire width 3 $2\fus_cu_rdmaskn_i$22[2:0]$2896 + attribute \src "libresoc.v:43232.3-43260.6" + wire width 6 $2\fus_cu_rdmaskn_i$25[5:0]$2363 + attribute \src "libresoc.v:43728.3-43756.6" + wire width 3 $2\fus_cu_rdmaskn_i$28[2:0]$2388 + attribute \src "libresoc.v:44050.3-44078.6" + wire width 3 $2\fus_cu_rdmaskn_i$31[2:0]$2407 + attribute \src "libresoc.v:44517.3-44545.6" + wire width 5 $2\fus_cu_rdmaskn_i$34[4:0]$2431 + attribute \src "libresoc.v:44955.3-44983.6" + wire width 3 $2\fus_cu_rdmaskn_i$37[2:0]$2454 + attribute \src "libresoc.v:46449.3-46477.6" + wire width 4 $2\fus_cu_rdmaskn_i[3:0] + attribute \src "libresoc.v:46326.3-46354.6" + wire width 4 $2\fus_oper_i_alu_alu0__data_len[3:0] + attribute \src "libresoc.v:45636.3-45664.6" + wire width 12 $2\fus_oper_i_alu_alu0__fn_unit[11:0] + attribute \src "libresoc.v:45703.3-45732.6" + wire width 64 $2\fus_oper_i_alu_alu0__imm_data__data[63:0] + attribute \src "libresoc.v:45703.3-45732.6" + wire $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "libresoc.v:46156.3-46184.6" + wire width 2 $2\fus_oper_i_alu_alu0__input_carry[1:0] + attribute \src "libresoc.v:46373.3-46401.6" + wire width 32 $2\fus_oper_i_alu_alu0__insn[31:0] + attribute \src "libresoc.v:45579.3-45607.6" + wire width 7 $2\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "libresoc.v:45955.3-45983.6" + wire $2\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "libresoc.v:46070.3-46098.6" + wire $2\fus_oper_i_alu_alu0__invert_out[0:0] + attribute \src "libresoc.v:46241.3-46269.6" + wire $2\fus_oper_i_alu_alu0__is_32bit[0:0] + attribute \src "libresoc.v:46288.3-46316.6" + wire $2\fus_oper_i_alu_alu0__is_signed[0:0] + attribute \src "libresoc.v:45868.3-45897.6" + wire $2\fus_oper_i_alu_alu0__oe__oe[0:0] + attribute \src "libresoc.v:45868.3-45897.6" + wire $2\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "libresoc.v:46203.3-46231.6" + wire $2\fus_oper_i_alu_alu0__output_carry[0:0] + attribute \src "libresoc.v:45781.3-45810.6" + wire $2\fus_oper_i_alu_alu0__rc__ok[0:0] + attribute \src "libresoc.v:45781.3-45810.6" + wire $2\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "libresoc.v:46118.3-46146.6" + wire $2\fus_oper_i_alu_alu0__write_cr0[0:0] + attribute \src "libresoc.v:46003.3-46031.6" + wire $2\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "libresoc.v:46704.3-46732.6" + wire width 64 $2\fus_oper_i_alu_branch0__cia[63:0] + attribute \src "libresoc.v:46789.3-46817.6" + wire width 12 $2\fus_oper_i_alu_branch0__fn_unit[11:0] + attribute \src "libresoc.v:46874.3-46903.6" + wire width 64 $2\fus_oper_i_alu_branch0__imm_data__data[63:0] + attribute \src "libresoc.v:46874.3-46903.6" + wire $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] + attribute \src "libresoc.v:46827.3-46855.6" + wire width 32 $2\fus_oper_i_alu_branch0__insn[31:0] + attribute \src "libresoc.v:46742.3-46770.6" + wire width 7 $2\fus_oper_i_alu_branch0__insn_type[6:0] + attribute \src "libresoc.v:46969.3-46997.6" + wire $2\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "libresoc.v:46931.3-46959.6" + wire $2\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "libresoc.v:46534.3-46562.6" + wire width 12 $2\fus_oper_i_alu_cr0__fn_unit[11:0] + attribute \src "libresoc.v:46581.3-46609.6" + wire width 32 $2\fus_oper_i_alu_cr0__insn[31:0] + attribute \src "libresoc.v:46487.3-46515.6" + wire width 7 $2\fus_oper_i_alu_cr0__insn_type[6:0] + attribute \src "libresoc.v:43641.3-43669.6" + wire width 4 $2\fus_oper_i_alu_div0__data_len[3:0] + attribute \src "libresoc.v:43290.3-43318.6" + wire width 12 $2\fus_oper_i_alu_div0__fn_unit[11:0] + attribute \src "libresoc.v:43319.3-43348.6" + wire width 64 $2\fus_oper_i_alu_div0__imm_data__data[63:0] + attribute \src "libresoc.v:43319.3-43348.6" + wire $2\fus_oper_i_alu_div0__imm_data__ok[0:0] + attribute \src "libresoc.v:43467.3-43495.6" + wire width 2 $2\fus_oper_i_alu_div0__input_carry[1:0] + attribute \src "libresoc.v:43670.3-43698.6" + wire width 32 $2\fus_oper_i_alu_div0__insn[31:0] + attribute \src "libresoc.v:43261.3-43289.6" + wire width 7 $2\fus_oper_i_alu_div0__insn_type[6:0] + attribute \src "libresoc.v:43409.3-43437.6" + wire $2\fus_oper_i_alu_div0__invert_in[0:0] + attribute \src "libresoc.v:43496.3-43524.6" + wire $2\fus_oper_i_alu_div0__invert_out[0:0] + attribute \src "libresoc.v:43583.3-43611.6" + wire $2\fus_oper_i_alu_div0__is_32bit[0:0] + attribute \src "libresoc.v:43612.3-43640.6" + wire $2\fus_oper_i_alu_div0__is_signed[0:0] + attribute \src "libresoc.v:43379.3-43408.6" + wire $2\fus_oper_i_alu_div0__oe__oe[0:0] + attribute \src "libresoc.v:43379.3-43408.6" + wire $2\fus_oper_i_alu_div0__oe__ok[0:0] + attribute \src "libresoc.v:43554.3-43582.6" + wire $2\fus_oper_i_alu_div0__output_carry[0:0] + attribute \src "libresoc.v:43349.3-43378.6" + wire $2\fus_oper_i_alu_div0__rc__ok[0:0] + attribute \src "libresoc.v:43349.3-43378.6" + wire $2\fus_oper_i_alu_div0__rc__rc[0:0] + attribute \src "libresoc.v:43525.3-43553.6" + wire $2\fus_oper_i_alu_div0__write_cr0[0:0] + attribute \src "libresoc.v:43438.3-43466.6" + wire $2\fus_oper_i_alu_div0__zero_a[0:0] + attribute \src "libresoc.v:47818.3-47846.6" + wire width 4 $2\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "libresoc.v:47467.3-47495.6" + wire width 12 $2\fus_oper_i_alu_logical0__fn_unit[11:0] + attribute \src "libresoc.v:47496.3-47525.6" + wire width 64 $2\fus_oper_i_alu_logical0__imm_data__data[63:0] + attribute \src "libresoc.v:47496.3-47525.6" + wire $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] + attribute \src "libresoc.v:47644.3-47672.6" + wire width 2 $2\fus_oper_i_alu_logical0__input_carry[1:0] + attribute \src "libresoc.v:47847.3-47875.6" + wire width 32 $2\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "libresoc.v:47438.3-47466.6" + wire width 7 $2\fus_oper_i_alu_logical0__insn_type[6:0] + attribute \src "libresoc.v:47586.3-47614.6" + wire $2\fus_oper_i_alu_logical0__invert_in[0:0] + attribute \src "libresoc.v:47673.3-47701.6" + wire $2\fus_oper_i_alu_logical0__invert_out[0:0] + attribute \src "libresoc.v:47760.3-47788.6" + wire $2\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "libresoc.v:47789.3-47817.6" + wire $2\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "libresoc.v:47556.3-47585.6" + wire $2\fus_oper_i_alu_logical0__oe__oe[0:0] + attribute \src "libresoc.v:47556.3-47585.6" + wire $2\fus_oper_i_alu_logical0__oe__ok[0:0] + attribute \src "libresoc.v:47731.3-47759.6" + wire $2\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "libresoc.v:47526.3-47555.6" + wire $2\fus_oper_i_alu_logical0__rc__ok[0:0] + attribute \src "libresoc.v:47526.3-47555.6" + wire $2\fus_oper_i_alu_logical0__rc__rc[0:0] + attribute \src "libresoc.v:47702.3-47730.6" + wire $2\fus_oper_i_alu_logical0__write_cr0[0:0] + attribute \src "libresoc.v:47615.3-47643.6" + wire $2\fus_oper_i_alu_logical0__zero_a[0:0] + attribute \src "libresoc.v:43786.3-43814.6" + wire width 12 $2\fus_oper_i_alu_mul0__fn_unit[11:0] + attribute \src "libresoc.v:43815.3-43844.6" + wire width 64 $2\fus_oper_i_alu_mul0__imm_data__data[63:0] + attribute \src "libresoc.v:43815.3-43844.6" + wire $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] + attribute \src "libresoc.v:43992.3-44020.6" + wire width 32 $2\fus_oper_i_alu_mul0__insn[31:0] + attribute \src "libresoc.v:43757.3-43785.6" + wire width 7 $2\fus_oper_i_alu_mul0__insn_type[6:0] + attribute \src "libresoc.v:43934.3-43962.6" + wire $2\fus_oper_i_alu_mul0__is_32bit[0:0] + attribute \src "libresoc.v:43963.3-43991.6" + wire $2\fus_oper_i_alu_mul0__is_signed[0:0] + attribute \src "libresoc.v:43875.3-43904.6" + wire $2\fus_oper_i_alu_mul0__oe__oe[0:0] + attribute \src "libresoc.v:43875.3-43904.6" + wire $2\fus_oper_i_alu_mul0__oe__ok[0:0] + attribute \src "libresoc.v:43845.3-43874.6" + wire $2\fus_oper_i_alu_mul0__rc__ok[0:0] + attribute \src "libresoc.v:43845.3-43874.6" + wire $2\fus_oper_i_alu_mul0__rc__rc[0:0] + attribute \src "libresoc.v:43905.3-43933.6" + wire $2\fus_oper_i_alu_mul0__write_cr0[0:0] + attribute \src "libresoc.v:44108.3-44136.6" + wire width 12 $2\fus_oper_i_alu_shift_rot0__fn_unit[11:0] + attribute \src "libresoc.v:44137.3-44166.6" + wire width 64 $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + attribute \src "libresoc.v:44137.3-44166.6" + wire $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + attribute \src "libresoc.v:44285.3-44313.6" + wire width 2 $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] + attribute \src "libresoc.v:44343.3-44371.6" + wire $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] + attribute \src "libresoc.v:44459.3-44487.6" + wire width 32 $2\fus_oper_i_alu_shift_rot0__insn[31:0] + attribute \src "libresoc.v:44079.3-44107.6" + wire width 7 $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] + attribute \src "libresoc.v:44256.3-44284.6" + wire $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] + attribute \src "libresoc.v:44401.3-44429.6" + wire $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + attribute \src "libresoc.v:44430.3-44458.6" + wire $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] + attribute \src "libresoc.v:44197.3-44226.6" + wire $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + attribute \src "libresoc.v:44197.3-44226.6" + wire $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + attribute \src "libresoc.v:44314.3-44342.6" + wire $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] + attribute \src "libresoc.v:44372.3-44400.6" + wire $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] + attribute \src "libresoc.v:44167.3-44196.6" + wire $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + attribute \src "libresoc.v:44167.3-44196.6" + wire $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + attribute \src "libresoc.v:44227.3-44255.6" + wire $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + attribute \src "libresoc.v:47963.3-47991.6" + wire width 12 $2\fus_oper_i_alu_spr0__fn_unit[11:0] + attribute \src "libresoc.v:43145.3-43173.6" + wire width 32 $2\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "libresoc.v:47934.3-47962.6" + wire width 7 $2\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "libresoc.v:43174.3-43202.6" + wire $2\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "libresoc.v:47235.3-47263.6" + wire width 64 $2\fus_oper_i_alu_trap0__cia[63:0] + attribute \src "libresoc.v:47139.3-47167.6" + wire width 12 $2\fus_oper_i_alu_trap0__fn_unit[11:0] + attribute \src "libresoc.v:47177.3-47205.6" + wire width 32 $2\fus_oper_i_alu_trap0__insn[31:0] + attribute \src "libresoc.v:47092.3-47120.6" + wire width 7 $2\fus_oper_i_alu_trap0__insn_type[6:0] + attribute \src "libresoc.v:47264.3-47292.6" + wire $2\fus_oper_i_alu_trap0__is_32bit[0:0] + attribute \src "libresoc.v:47351.3-47379.6" + wire width 8 $2\fus_oper_i_alu_trap0__ldst_exc[7:0] + attribute \src "libresoc.v:47206.3-47234.6" + wire width 64 $2\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "libresoc.v:47322.3-47350.6" + wire width 13 $2\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "libresoc.v:47293.3-47321.6" + wire width 8 $2\fus_oper_i_alu_trap0__traptype[7:0] + attribute \src "libresoc.v:44810.3-44838.6" + wire $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + attribute \src "libresoc.v:44781.3-44809.6" + wire width 4 $2\fus_oper_i_ldst_ldst0__data_len[3:0] + attribute \src "libresoc.v:44575.3-44603.6" + wire width 12 $2\fus_oper_i_ldst_ldst0__fn_unit[11:0] + attribute \src "libresoc.v:44604.3-44633.6" + wire width 64 $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + attribute \src "libresoc.v:44604.3-44633.6" + wire $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + attribute \src "libresoc.v:44897.3-44925.6" + wire width 32 $2\fus_oper_i_ldst_ldst0__insn[31:0] + attribute \src "libresoc.v:44546.3-44574.6" + wire width 7 $2\fus_oper_i_ldst_ldst0__insn_type[6:0] + attribute \src "libresoc.v:44723.3-44751.6" + wire $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] + attribute \src "libresoc.v:44752.3-44780.6" + wire $2\fus_oper_i_ldst_ldst0__is_signed[0:0] + attribute \src "libresoc.v:44868.3-44896.6" + wire width 2 $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + attribute \src "libresoc.v:44693.3-44722.6" + wire $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] + attribute \src "libresoc.v:44693.3-44722.6" + wire $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] + attribute \src "libresoc.v:44663.3-44692.6" + wire $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] + attribute \src "libresoc.v:44663.3-44692.6" + wire $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] + attribute \src "libresoc.v:44839.3-44867.6" + wire $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] + attribute \src "libresoc.v:44634.3-44662.6" + wire $2\fus_oper_i_ldst_ldst0__zero_a[0:0] + attribute \src "libresoc.v:45520.3-45540.6" + wire $3\core_terminate_o$next[0:0]$2591 + attribute \src "libresoc.v:45391.3-45481.6" + wire $3\corebusy_o[0:0] + attribute \src "libresoc.v:45345.3-45371.6" + wire width 2 $3\counter$next[1:0]$2568 + attribute \src "libresoc.v:46619.3-46647.6" + wire $3\fus_cu_issue_i$11[0:0]$2771 + attribute \src "libresoc.v:47016.3-47044.6" + wire $3\fus_cu_issue_i$14[0:0]$2833 + attribute \src "libresoc.v:47380.3-47408.6" + wire $3\fus_cu_issue_i$17[0:0]$2867 + attribute \src "libresoc.v:47876.3-47904.6" + wire $3\fus_cu_issue_i$20[0:0]$2892 + attribute \src "libresoc.v:43203.3-43231.6" + wire $3\fus_cu_issue_i$23[0:0]$2359 + attribute \src "libresoc.v:43699.3-43727.6" + wire $3\fus_cu_issue_i$26[0:0]$2384 + attribute \src "libresoc.v:44021.3-44049.6" + wire $3\fus_cu_issue_i$29[0:0]$2403 + attribute \src "libresoc.v:44488.3-44516.6" + wire $3\fus_cu_issue_i$32[0:0]$2427 + attribute \src "libresoc.v:44926.3-44954.6" + wire $3\fus_cu_issue_i$35[0:0]$2450 + attribute \src "libresoc.v:46411.3-46439.6" + wire $3\fus_cu_issue_i[0:0] + attribute \src "libresoc.v:46657.3-46685.6" + wire width 6 $3\fus_cu_rdmaskn_i$13[5:0]$2779 + attribute \src "libresoc.v:47054.3-47082.6" + wire width 3 $3\fus_cu_rdmaskn_i$16[2:0]$2841 + attribute \src "libresoc.v:47409.3-47437.6" + wire width 4 $3\fus_cu_rdmaskn_i$19[3:0]$2872 + attribute \src "libresoc.v:47905.3-47933.6" + wire width 3 $3\fus_cu_rdmaskn_i$22[2:0]$2897 + attribute \src "libresoc.v:43232.3-43260.6" + wire width 6 $3\fus_cu_rdmaskn_i$25[5:0]$2364 + attribute \src "libresoc.v:43728.3-43756.6" + wire width 3 $3\fus_cu_rdmaskn_i$28[2:0]$2389 + attribute \src "libresoc.v:44050.3-44078.6" + wire width 3 $3\fus_cu_rdmaskn_i$31[2:0]$2408 + attribute \src "libresoc.v:44517.3-44545.6" + wire width 5 $3\fus_cu_rdmaskn_i$34[4:0]$2432 + attribute \src "libresoc.v:44955.3-44983.6" + wire width 3 $3\fus_cu_rdmaskn_i$37[2:0]$2455 + attribute \src "libresoc.v:46449.3-46477.6" + wire width 4 $3\fus_cu_rdmaskn_i[3:0] + attribute \src "libresoc.v:46326.3-46354.6" + wire width 4 $3\fus_oper_i_alu_alu0__data_len[3:0] + attribute \src "libresoc.v:45636.3-45664.6" + wire width 12 $3\fus_oper_i_alu_alu0__fn_unit[11:0] + attribute \src "libresoc.v:45703.3-45732.6" + wire width 64 $3\fus_oper_i_alu_alu0__imm_data__data[63:0] + attribute \src "libresoc.v:45703.3-45732.6" + wire $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "libresoc.v:46156.3-46184.6" + wire width 2 $3\fus_oper_i_alu_alu0__input_carry[1:0] + attribute \src "libresoc.v:46373.3-46401.6" + wire width 32 $3\fus_oper_i_alu_alu0__insn[31:0] + attribute \src "libresoc.v:45579.3-45607.6" + wire width 7 $3\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "libresoc.v:45955.3-45983.6" + wire $3\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "libresoc.v:46070.3-46098.6" + wire $3\fus_oper_i_alu_alu0__invert_out[0:0] + attribute \src "libresoc.v:46241.3-46269.6" + wire $3\fus_oper_i_alu_alu0__is_32bit[0:0] + attribute \src "libresoc.v:46288.3-46316.6" + wire $3\fus_oper_i_alu_alu0__is_signed[0:0] + attribute \src "libresoc.v:45868.3-45897.6" + wire $3\fus_oper_i_alu_alu0__oe__oe[0:0] + attribute \src "libresoc.v:45868.3-45897.6" + wire $3\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "libresoc.v:46203.3-46231.6" + wire $3\fus_oper_i_alu_alu0__output_carry[0:0] + attribute \src "libresoc.v:45781.3-45810.6" + wire $3\fus_oper_i_alu_alu0__rc__ok[0:0] + attribute \src "libresoc.v:45781.3-45810.6" + wire $3\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "libresoc.v:46118.3-46146.6" + wire $3\fus_oper_i_alu_alu0__write_cr0[0:0] + attribute \src "libresoc.v:46003.3-46031.6" + wire $3\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "libresoc.v:46704.3-46732.6" + wire width 64 $3\fus_oper_i_alu_branch0__cia[63:0] + attribute \src "libresoc.v:46789.3-46817.6" + wire width 12 $3\fus_oper_i_alu_branch0__fn_unit[11:0] + attribute \src "libresoc.v:46874.3-46903.6" + wire width 64 $3\fus_oper_i_alu_branch0__imm_data__data[63:0] + attribute \src "libresoc.v:46874.3-46903.6" + wire $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] + attribute \src "libresoc.v:46827.3-46855.6" + wire width 32 $3\fus_oper_i_alu_branch0__insn[31:0] + attribute \src "libresoc.v:46742.3-46770.6" + wire width 7 $3\fus_oper_i_alu_branch0__insn_type[6:0] + attribute \src "libresoc.v:46969.3-46997.6" + wire $3\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "libresoc.v:46931.3-46959.6" + wire $3\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "libresoc.v:46534.3-46562.6" + wire width 12 $3\fus_oper_i_alu_cr0__fn_unit[11:0] + attribute \src "libresoc.v:46581.3-46609.6" + wire width 32 $3\fus_oper_i_alu_cr0__insn[31:0] + attribute \src "libresoc.v:46487.3-46515.6" + wire width 7 $3\fus_oper_i_alu_cr0__insn_type[6:0] + attribute \src "libresoc.v:43641.3-43669.6" + wire width 4 $3\fus_oper_i_alu_div0__data_len[3:0] + attribute \src "libresoc.v:43290.3-43318.6" + wire width 12 $3\fus_oper_i_alu_div0__fn_unit[11:0] + attribute \src "libresoc.v:43319.3-43348.6" + wire width 64 $3\fus_oper_i_alu_div0__imm_data__data[63:0] + attribute \src "libresoc.v:43319.3-43348.6" + wire $3\fus_oper_i_alu_div0__imm_data__ok[0:0] + attribute \src "libresoc.v:43467.3-43495.6" + wire width 2 $3\fus_oper_i_alu_div0__input_carry[1:0] + attribute \src "libresoc.v:43670.3-43698.6" + wire width 32 $3\fus_oper_i_alu_div0__insn[31:0] + attribute \src "libresoc.v:43261.3-43289.6" + wire width 7 $3\fus_oper_i_alu_div0__insn_type[6:0] + attribute \src "libresoc.v:43409.3-43437.6" + wire $3\fus_oper_i_alu_div0__invert_in[0:0] + attribute \src "libresoc.v:43496.3-43524.6" + wire $3\fus_oper_i_alu_div0__invert_out[0:0] + attribute \src "libresoc.v:43583.3-43611.6" + wire $3\fus_oper_i_alu_div0__is_32bit[0:0] + attribute \src "libresoc.v:43612.3-43640.6" + wire $3\fus_oper_i_alu_div0__is_signed[0:0] + attribute \src "libresoc.v:43379.3-43408.6" + wire $3\fus_oper_i_alu_div0__oe__oe[0:0] + attribute \src "libresoc.v:43379.3-43408.6" + wire $3\fus_oper_i_alu_div0__oe__ok[0:0] + attribute \src "libresoc.v:43554.3-43582.6" + wire $3\fus_oper_i_alu_div0__output_carry[0:0] + attribute \src "libresoc.v:43349.3-43378.6" + wire $3\fus_oper_i_alu_div0__rc__ok[0:0] + attribute \src "libresoc.v:43349.3-43378.6" + wire $3\fus_oper_i_alu_div0__rc__rc[0:0] + attribute \src "libresoc.v:43525.3-43553.6" + wire $3\fus_oper_i_alu_div0__write_cr0[0:0] + attribute \src "libresoc.v:43438.3-43466.6" + wire $3\fus_oper_i_alu_div0__zero_a[0:0] + attribute \src "libresoc.v:47818.3-47846.6" + wire width 4 $3\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "libresoc.v:47467.3-47495.6" + wire width 12 $3\fus_oper_i_alu_logical0__fn_unit[11:0] + attribute \src "libresoc.v:47496.3-47525.6" + wire width 64 $3\fus_oper_i_alu_logical0__imm_data__data[63:0] + attribute \src "libresoc.v:47496.3-47525.6" + wire $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] + attribute \src "libresoc.v:47644.3-47672.6" + wire width 2 $3\fus_oper_i_alu_logical0__input_carry[1:0] + attribute \src "libresoc.v:47847.3-47875.6" + wire width 32 $3\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "libresoc.v:47438.3-47466.6" + wire width 7 $3\fus_oper_i_alu_logical0__insn_type[6:0] + attribute \src "libresoc.v:47586.3-47614.6" + wire $3\fus_oper_i_alu_logical0__invert_in[0:0] + attribute \src "libresoc.v:47673.3-47701.6" + wire $3\fus_oper_i_alu_logical0__invert_out[0:0] + attribute \src "libresoc.v:47760.3-47788.6" + wire $3\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "libresoc.v:47789.3-47817.6" + wire $3\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "libresoc.v:47556.3-47585.6" + wire $3\fus_oper_i_alu_logical0__oe__oe[0:0] + attribute \src "libresoc.v:47556.3-47585.6" + wire $3\fus_oper_i_alu_logical0__oe__ok[0:0] + attribute \src "libresoc.v:47731.3-47759.6" + wire $3\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "libresoc.v:47526.3-47555.6" + wire $3\fus_oper_i_alu_logical0__rc__ok[0:0] + attribute \src "libresoc.v:47526.3-47555.6" + wire $3\fus_oper_i_alu_logical0__rc__rc[0:0] + attribute \src "libresoc.v:47702.3-47730.6" + wire $3\fus_oper_i_alu_logical0__write_cr0[0:0] + attribute \src "libresoc.v:47615.3-47643.6" + wire $3\fus_oper_i_alu_logical0__zero_a[0:0] + attribute \src "libresoc.v:43786.3-43814.6" + wire width 12 $3\fus_oper_i_alu_mul0__fn_unit[11:0] + attribute \src "libresoc.v:43815.3-43844.6" + wire width 64 $3\fus_oper_i_alu_mul0__imm_data__data[63:0] + attribute \src "libresoc.v:43815.3-43844.6" + wire $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] + attribute \src "libresoc.v:43992.3-44020.6" + wire width 32 $3\fus_oper_i_alu_mul0__insn[31:0] + attribute \src "libresoc.v:43757.3-43785.6" + wire width 7 $3\fus_oper_i_alu_mul0__insn_type[6:0] + attribute \src "libresoc.v:43934.3-43962.6" + wire $3\fus_oper_i_alu_mul0__is_32bit[0:0] + attribute \src "libresoc.v:43963.3-43991.6" + wire $3\fus_oper_i_alu_mul0__is_signed[0:0] + attribute \src "libresoc.v:43875.3-43904.6" + wire $3\fus_oper_i_alu_mul0__oe__oe[0:0] + attribute \src "libresoc.v:43875.3-43904.6" + wire $3\fus_oper_i_alu_mul0__oe__ok[0:0] + attribute \src "libresoc.v:43845.3-43874.6" + wire $3\fus_oper_i_alu_mul0__rc__ok[0:0] + attribute \src "libresoc.v:43845.3-43874.6" + wire $3\fus_oper_i_alu_mul0__rc__rc[0:0] + attribute \src "libresoc.v:43905.3-43933.6" + wire $3\fus_oper_i_alu_mul0__write_cr0[0:0] + attribute \src "libresoc.v:44108.3-44136.6" + wire width 12 $3\fus_oper_i_alu_shift_rot0__fn_unit[11:0] + attribute \src "libresoc.v:44137.3-44166.6" + wire width 64 $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + attribute \src "libresoc.v:44137.3-44166.6" + wire $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + attribute \src "libresoc.v:44285.3-44313.6" + wire width 2 $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] + attribute \src "libresoc.v:44343.3-44371.6" + wire $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] + attribute \src "libresoc.v:44459.3-44487.6" + wire width 32 $3\fus_oper_i_alu_shift_rot0__insn[31:0] + attribute \src "libresoc.v:44079.3-44107.6" + wire width 7 $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] + attribute \src "libresoc.v:44256.3-44284.6" + wire $3\fus_oper_i_alu_shift_rot0__invert_in[0:0] + attribute \src "libresoc.v:44401.3-44429.6" + wire $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + attribute \src "libresoc.v:44430.3-44458.6" + wire $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] + attribute \src "libresoc.v:44197.3-44226.6" + wire $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + attribute \src "libresoc.v:44197.3-44226.6" + wire $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + attribute \src "libresoc.v:44314.3-44342.6" + wire $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] + attribute \src "libresoc.v:44372.3-44400.6" + wire $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] + attribute \src "libresoc.v:44167.3-44196.6" + wire $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + attribute \src "libresoc.v:44167.3-44196.6" + wire $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + attribute \src "libresoc.v:44227.3-44255.6" + wire $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + attribute \src "libresoc.v:47963.3-47991.6" + wire width 12 $3\fus_oper_i_alu_spr0__fn_unit[11:0] + attribute \src "libresoc.v:43145.3-43173.6" + wire width 32 $3\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "libresoc.v:47934.3-47962.6" + wire width 7 $3\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "libresoc.v:43174.3-43202.6" + wire $3\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "libresoc.v:47235.3-47263.6" + wire width 64 $3\fus_oper_i_alu_trap0__cia[63:0] + attribute \src "libresoc.v:47139.3-47167.6" + wire width 12 $3\fus_oper_i_alu_trap0__fn_unit[11:0] + attribute \src "libresoc.v:47177.3-47205.6" + wire width 32 $3\fus_oper_i_alu_trap0__insn[31:0] + attribute \src "libresoc.v:47092.3-47120.6" + wire width 7 $3\fus_oper_i_alu_trap0__insn_type[6:0] + attribute \src "libresoc.v:47264.3-47292.6" + wire $3\fus_oper_i_alu_trap0__is_32bit[0:0] + attribute \src "libresoc.v:47351.3-47379.6" + wire width 8 $3\fus_oper_i_alu_trap0__ldst_exc[7:0] + attribute \src "libresoc.v:47206.3-47234.6" + wire width 64 $3\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "libresoc.v:47322.3-47350.6" + wire width 13 $3\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "libresoc.v:47293.3-47321.6" + wire width 8 $3\fus_oper_i_alu_trap0__traptype[7:0] + attribute \src "libresoc.v:44810.3-44838.6" + wire $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + attribute \src "libresoc.v:44781.3-44809.6" + wire width 4 $3\fus_oper_i_ldst_ldst0__data_len[3:0] + attribute \src "libresoc.v:44575.3-44603.6" + wire width 12 $3\fus_oper_i_ldst_ldst0__fn_unit[11:0] + attribute \src "libresoc.v:44604.3-44633.6" + wire width 64 $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + attribute \src "libresoc.v:44604.3-44633.6" + wire $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + attribute \src "libresoc.v:44897.3-44925.6" + wire width 32 $3\fus_oper_i_ldst_ldst0__insn[31:0] + attribute \src "libresoc.v:44546.3-44574.6" + wire width 7 $3\fus_oper_i_ldst_ldst0__insn_type[6:0] + attribute \src "libresoc.v:44723.3-44751.6" + wire $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] + attribute \src "libresoc.v:44752.3-44780.6" + wire $3\fus_oper_i_ldst_ldst0__is_signed[0:0] + attribute \src "libresoc.v:44868.3-44896.6" + wire width 2 $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + attribute \src "libresoc.v:44693.3-44722.6" + wire $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] + attribute \src "libresoc.v:44693.3-44722.6" + wire $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] + attribute \src "libresoc.v:44663.3-44692.6" + wire $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] + attribute \src "libresoc.v:44663.3-44692.6" + wire $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] + attribute \src "libresoc.v:44839.3-44867.6" + wire $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] + attribute \src "libresoc.v:44634.3-44662.6" + wire $3\fus_oper_i_ldst_ldst0__zero_a[0:0] + attribute \src "libresoc.v:45391.3-45481.6" + wire $4\corebusy_o[0:0] + attribute \src "libresoc.v:45345.3-45371.6" + wire width 2 $4\counter$next[1:0]$2569 + attribute \src "libresoc.v:45391.3-45481.6" + wire $5\corebusy_o[0:0] + attribute \src "libresoc.v:45391.3-45481.6" + wire $6\corebusy_o[0:0] + attribute \src "libresoc.v:45391.3-45481.6" + wire $7\corebusy_o[0:0] + attribute \src "libresoc.v:45391.3-45481.6" + wire $8\corebusy_o[0:0] + attribute \src "libresoc.v:45391.3-45481.6" + wire $9\corebusy_o[0:0] + attribute \src "libresoc.v:41534.20-41534.109" + wire $and$libresoc.v:41534$1507_Y + attribute \src "libresoc.v:41535.20-41535.122" + wire $and$libresoc.v:41535$1508_Y + attribute \src "libresoc.v:41537.20-41537.122" + wire $and$libresoc.v:41537$1510_Y + attribute \src "libresoc.v:41538.20-41538.126" + wire $and$libresoc.v:41538$1511_Y + attribute \src "libresoc.v:41540.20-41540.110" + wire $and$libresoc.v:41540$1513_Y + attribute \src "libresoc.v:41541.20-41541.123" + wire $and$libresoc.v:41541$1514_Y + attribute \src "libresoc.v:41543.20-41543.122" + wire $and$libresoc.v:41543$1516_Y + attribute \src "libresoc.v:41544.20-41544.126" + wire $and$libresoc.v:41544$1517_Y + attribute \src "libresoc.v:41546.20-41546.110" + wire $and$libresoc.v:41546$1519_Y + attribute \src "libresoc.v:41547.20-41547.123" + wire $and$libresoc.v:41547$1520_Y + attribute \src "libresoc.v:41549.20-41549.123" + wire $and$libresoc.v:41549$1522_Y + attribute \src "libresoc.v:41550.20-41550.126" + wire $and$libresoc.v:41550$1523_Y + attribute \src "libresoc.v:41552.20-41552.110" + wire $and$libresoc.v:41552$1525_Y + attribute \src "libresoc.v:41553.20-41553.123" + wire $and$libresoc.v:41553$1526_Y + attribute \src "libresoc.v:41555.20-41555.123" + wire $and$libresoc.v:41555$1528_Y + attribute \src "libresoc.v:41556.20-41556.126" + wire $and$libresoc.v:41556$1529_Y + attribute \src "libresoc.v:41558.20-41558.110" + wire $and$libresoc.v:41558$1531_Y + attribute \src "libresoc.v:41559.20-41559.123" + wire $and$libresoc.v:41559$1532_Y + attribute \src "libresoc.v:41561.20-41561.123" + wire $and$libresoc.v:41561$1534_Y + attribute \src "libresoc.v:41562.20-41562.126" + wire $and$libresoc.v:41562$1535_Y + attribute \src "libresoc.v:41564.20-41564.110" + wire $and$libresoc.v:41564$1537_Y + attribute \src "libresoc.v:41565.20-41565.123" + wire $and$libresoc.v:41565$1538_Y + attribute \src "libresoc.v:41567.20-41567.113" + wire $and$libresoc.v:41567$1540_Y + attribute \src "libresoc.v:41568.20-41568.126" + wire $and$libresoc.v:41568$1541_Y + attribute \src "libresoc.v:41570.20-41570.110" + wire $and$libresoc.v:41570$1543_Y + attribute \src "libresoc.v:41571.20-41571.123" + wire $and$libresoc.v:41571$1544_Y + attribute \src "libresoc.v:41573.20-41573.114" + wire $and$libresoc.v:41573$1546_Y + attribute \src "libresoc.v:41574.20-41574.126" + wire $and$libresoc.v:41574$1547_Y + attribute \src "libresoc.v:41576.20-41576.110" + wire $and$libresoc.v:41576$1549_Y + attribute \src "libresoc.v:41577.20-41577.123" + wire $and$libresoc.v:41577$1550_Y + attribute \src "libresoc.v:41606.20-41606.123" + wire $and$libresoc.v:41606$1579_Y + attribute \src "libresoc.v:41607.20-41607.128" + wire $and$libresoc.v:41607$1580_Y + attribute \src "libresoc.v:41608.20-41608.133" + wire $and$libresoc.v:41608$1581_Y + attribute \src "libresoc.v:41610.20-41610.110" + wire $and$libresoc.v:41610$1583_Y + attribute \src "libresoc.v:41611.20-41611.128" + wire $and$libresoc.v:41611$1584_Y + attribute \src "libresoc.v:41613.20-41613.116" + wire $and$libresoc.v:41613$1586_Y + attribute \src "libresoc.v:41614.20-41614.123" + wire $and$libresoc.v:41614$1587_Y + attribute \src "libresoc.v:41615.20-41615.128" + wire $and$libresoc.v:41615$1588_Y + attribute \src "libresoc.v:41616.20-41616.128" + wire $and$libresoc.v:41616$1589_Y + attribute \src "libresoc.v:41617.20-41617.129" + wire $and$libresoc.v:41617$1590_Y + attribute \src "libresoc.v:41618.20-41618.129" + wire $and$libresoc.v:41618$1591_Y + attribute \src "libresoc.v:41619.20-41619.129" + wire $and$libresoc.v:41619$1592_Y + attribute \src "libresoc.v:41620.20-41620.130" + wire $and$libresoc.v:41620$1593_Y + attribute \src "libresoc.v:41622.20-41622.110" + wire $and$libresoc.v:41622$1595_Y + attribute \src "libresoc.v:41623.20-41623.125" + wire $and$libresoc.v:41623$1596_Y + attribute \src "libresoc.v:41627.20-41627.126" + wire $and$libresoc.v:41627$1600_Y + attribute \src "libresoc.v:41628.20-41628.130" + wire $and$libresoc.v:41628$1601_Y + attribute \src "libresoc.v:41630.20-41630.110" + wire $and$libresoc.v:41630$1603_Y + attribute \src "libresoc.v:41631.20-41631.125" + wire $and$libresoc.v:41631$1604_Y + attribute \src "libresoc.v:41635.20-41635.126" + wire $and$libresoc.v:41635$1608_Y + attribute \src "libresoc.v:41636.20-41636.130" + wire $and$libresoc.v:41636$1609_Y + attribute \src "libresoc.v:41638.20-41638.110" + wire $and$libresoc.v:41638$1611_Y + attribute \src "libresoc.v:41639.20-41639.125" + wire $and$libresoc.v:41639$1612_Y + attribute \src "libresoc.v:41643.20-41643.126" + wire $and$libresoc.v:41643$1616_Y + attribute \src "libresoc.v:41644.20-41644.130" + wire $and$libresoc.v:41644$1617_Y + attribute \src "libresoc.v:41646.20-41646.110" + wire $and$libresoc.v:41646$1619_Y + attribute \src "libresoc.v:41647.20-41647.125" + wire $and$libresoc.v:41647$1620_Y + attribute \src "libresoc.v:41651.20-41651.126" + wire $and$libresoc.v:41651$1624_Y + attribute \src "libresoc.v:41652.20-41652.130" + wire $and$libresoc.v:41652$1625_Y + attribute \src "libresoc.v:41654.20-41654.110" + wire $and$libresoc.v:41654$1627_Y + attribute \src "libresoc.v:41655.20-41655.125" + wire $and$libresoc.v:41655$1628_Y + attribute \src "libresoc.v:41659.20-41659.126" + wire $and$libresoc.v:41659$1632_Y + attribute \src "libresoc.v:41660.20-41660.130" + wire $and$libresoc.v:41660$1633_Y + attribute \src "libresoc.v:41662.20-41662.110" + wire $and$libresoc.v:41662$1635_Y + attribute \src "libresoc.v:41663.20-41663.125" + wire $and$libresoc.v:41663$1636_Y + attribute \src "libresoc.v:41677.20-41677.118" + wire $and$libresoc.v:41677$1650_Y + attribute \src "libresoc.v:41678.20-41678.123" + wire $and$libresoc.v:41678$1651_Y + attribute \src "libresoc.v:41679.20-41679.129" + wire $and$libresoc.v:41679$1652_Y + attribute \src "libresoc.v:41680.20-41680.129" + wire $and$libresoc.v:41680$1653_Y + attribute \src "libresoc.v:41681.20-41681.136" + wire $and$libresoc.v:41681$1654_Y + attribute \src "libresoc.v:41683.20-41683.110" + wire $and$libresoc.v:41683$1656_Y + attribute \src "libresoc.v:41684.20-41684.128" + wire $and$libresoc.v:41684$1657_Y + attribute \src "libresoc.v:41686.20-41686.128" + wire $and$libresoc.v:41686$1659_Y + attribute \src "libresoc.v:41687.20-41687.136" + wire $and$libresoc.v:41687$1660_Y + attribute \src "libresoc.v:41689.20-41689.110" + wire $and$libresoc.v:41689$1662_Y + attribute \src "libresoc.v:41690.20-41690.128" + wire $and$libresoc.v:41690$1663_Y + attribute \src "libresoc.v:41692.20-41692.128" + wire $and$libresoc.v:41692$1665_Y + attribute \src "libresoc.v:41693.20-41693.136" + wire $and$libresoc.v:41693$1666_Y + attribute \src "libresoc.v:41695.20-41695.110" + wire $and$libresoc.v:41695$1668_Y + attribute \src "libresoc.v:41696.20-41696.128" + wire $and$libresoc.v:41696$1669_Y + attribute \src "libresoc.v:41703.20-41703.118" + wire $and$libresoc.v:41703$1677_Y + attribute \src "libresoc.v:41704.20-41704.123" + wire $and$libresoc.v:41704$1678_Y + attribute \src "libresoc.v:41705.20-41705.129" + wire $and$libresoc.v:41705$1679_Y + attribute \src "libresoc.v:41706.20-41706.129" + wire $and$libresoc.v:41706$1680_Y + attribute \src "libresoc.v:41707.20-41707.129" + wire $and$libresoc.v:41707$1681_Y + attribute \src "libresoc.v:41708.20-41708.136" + wire $and$libresoc.v:41708$1682_Y + attribute \src "libresoc.v:41710.20-41710.110" + wire $and$libresoc.v:41710$1684_Y + attribute \src "libresoc.v:41711.20-41711.128" + wire $and$libresoc.v:41711$1685_Y + attribute \src "libresoc.v:41713.20-41713.128" + wire $and$libresoc.v:41713$1687_Y + attribute \src "libresoc.v:41714.20-41714.136" + wire $and$libresoc.v:41714$1688_Y + attribute \src "libresoc.v:41716.20-41716.110" + wire $and$libresoc.v:41716$1690_Y + attribute \src "libresoc.v:41717.20-41717.128" + wire $and$libresoc.v:41717$1691_Y + attribute \src "libresoc.v:41719.20-41719.128" + wire $and$libresoc.v:41719$1693_Y + attribute \src "libresoc.v:41720.20-41720.136" + wire $and$libresoc.v:41720$1694_Y + attribute \src "libresoc.v:41722.20-41722.110" + wire $and$libresoc.v:41722$1696_Y + attribute \src "libresoc.v:41723.20-41723.128" + wire $and$libresoc.v:41723$1697_Y + attribute \src "libresoc.v:41725.20-41725.128" + wire $and$libresoc.v:41725$1699_Y + attribute \src "libresoc.v:41726.20-41726.136" + wire $and$libresoc.v:41726$1700_Y + attribute \src "libresoc.v:41728.20-41728.110" + wire $and$libresoc.v:41728$1702_Y + attribute \src "libresoc.v:41729.20-41729.128" + wire $and$libresoc.v:41729$1703_Y + attribute \src "libresoc.v:41737.20-41737.118" + wire $and$libresoc.v:41737$1711_Y + attribute \src "libresoc.v:41738.20-41738.123" + wire $and$libresoc.v:41738$1712_Y + attribute \src "libresoc.v:41739.20-41739.129" + wire $and$libresoc.v:41739$1713_Y + attribute \src "libresoc.v:41740.20-41740.129" + wire $and$libresoc.v:41740$1714_Y + attribute \src "libresoc.v:41741.20-41741.129" + wire $and$libresoc.v:41741$1715_Y + attribute \src "libresoc.v:41742.20-41742.136" + wire $and$libresoc.v:41742$1716_Y + attribute \src "libresoc.v:41744.20-41744.110" + wire $and$libresoc.v:41744$1718_Y + attribute \src "libresoc.v:41745.20-41745.128" + wire $and$libresoc.v:41745$1719_Y + attribute \src "libresoc.v:41747.20-41747.128" + wire $and$libresoc.v:41747$1721_Y + attribute \src "libresoc.v:41748.20-41748.136" + wire $and$libresoc.v:41748$1722_Y + attribute \src "libresoc.v:41750.20-41750.110" + wire $and$libresoc.v:41750$1724_Y + attribute \src "libresoc.v:41751.20-41751.128" + wire $and$libresoc.v:41751$1725_Y + attribute \src "libresoc.v:41753.20-41753.128" + wire $and$libresoc.v:41753$1727_Y + attribute \src "libresoc.v:41754.20-41754.136" + wire $and$libresoc.v:41754$1728_Y + attribute \src "libresoc.v:41756.20-41756.110" + wire $and$libresoc.v:41756$1730_Y + attribute \src "libresoc.v:41757.20-41757.128" + wire $and$libresoc.v:41757$1731_Y + attribute \src "libresoc.v:41759.20-41759.128" + wire $and$libresoc.v:41759$1733_Y + attribute \src "libresoc.v:41760.20-41760.136" + wire $and$libresoc.v:41760$1734_Y + attribute \src "libresoc.v:41762.20-41762.110" + wire $and$libresoc.v:41762$1736_Y + attribute \src "libresoc.v:41763.20-41763.128" + wire $and$libresoc.v:41763$1737_Y + attribute \src "libresoc.v:41773.20-41773.121" + wire $and$libresoc.v:41773$1749_Y + attribute \src "libresoc.v:41774.20-41774.129" + wire $and$libresoc.v:41774$1750_Y + attribute \src "libresoc.v:41775.20-41775.128" + wire $and$libresoc.v:41775$1751_Y + attribute \src "libresoc.v:41776.20-41776.129" + wire $and$libresoc.v:41776$1752_Y + attribute \src "libresoc.v:41777.20-41777.129" + wire $and$libresoc.v:41777$1753_Y + attribute \src "libresoc.v:41778.20-41778.128" + wire $and$libresoc.v:41778$1754_Y + attribute \src "libresoc.v:41779.20-41779.136" + wire $and$libresoc.v:41779$1755_Y + attribute \src "libresoc.v:41781.20-41781.110" + wire $and$libresoc.v:41781$1757_Y + attribute \src "libresoc.v:41782.20-41782.128" + wire $and$libresoc.v:41782$1758_Y + attribute \src "libresoc.v:41784.20-41784.127" + wire $and$libresoc.v:41784$1760_Y + attribute \src "libresoc.v:41785.20-41785.136" + wire $and$libresoc.v:41785$1761_Y + attribute \src "libresoc.v:41787.20-41787.110" + wire $and$libresoc.v:41787$1763_Y + attribute \src "libresoc.v:41788.20-41788.128" + wire $and$libresoc.v:41788$1764_Y + attribute \src "libresoc.v:41790.20-41790.127" + wire $and$libresoc.v:41790$1766_Y + attribute \src "libresoc.v:41791.20-41791.136" + wire $and$libresoc.v:41791$1767_Y + attribute \src "libresoc.v:41793.20-41793.110" + wire $and$libresoc.v:41793$1769_Y + attribute \src "libresoc.v:41794.20-41794.128" + wire $and$libresoc.v:41794$1770_Y + attribute \src "libresoc.v:41796.20-41796.121" + wire $and$libresoc.v:41796$1772_Y + attribute \src "libresoc.v:41797.20-41797.136" + wire $and$libresoc.v:41797$1773_Y + attribute \src "libresoc.v:41799.20-41799.110" + wire $and$libresoc.v:41799$1775_Y + attribute \src "libresoc.v:41800.20-41800.128" + wire $and$libresoc.v:41800$1776_Y + attribute \src "libresoc.v:41802.20-41802.127" + wire $and$libresoc.v:41802$1778_Y + attribute \src "libresoc.v:41803.20-41803.136" + wire $and$libresoc.v:41803$1779_Y + attribute \src "libresoc.v:41805.20-41805.110" + wire $and$libresoc.v:41805$1781_Y + attribute \src "libresoc.v:41806.20-41806.128" + wire $and$libresoc.v:41806$1782_Y + attribute \src "libresoc.v:41820.20-41820.119" + wire $and$libresoc.v:41820$1796_Y + attribute \src "libresoc.v:41821.20-41821.129" + wire $and$libresoc.v:41821$1797_Y + attribute \src "libresoc.v:41822.20-41822.128" + wire $and$libresoc.v:41822$1798_Y + attribute \src "libresoc.v:41823.20-41823.134" + wire $and$libresoc.v:41823$1799_Y + attribute \src "libresoc.v:41825.20-41825.110" + wire $and$libresoc.v:41825$1801_Y + attribute \src "libresoc.v:41826.20-41826.127" + wire $and$libresoc.v:41826$1802_Y + attribute \src "libresoc.v:41828.20-41828.125" + wire $and$libresoc.v:41828$1804_Y + attribute \src "libresoc.v:41829.20-41829.134" + wire $and$libresoc.v:41829$1805_Y + attribute \src "libresoc.v:41831.20-41831.110" + wire $and$libresoc.v:41831$1807_Y + attribute \src "libresoc.v:41832.19-41832.112" + wire width 12 $and$libresoc.v:41832$1808_Y + attribute \src "libresoc.v:41833.20-41833.127" + wire $and$libresoc.v:41833$1809_Y + attribute \src "libresoc.v:41839.20-41839.119" + wire $and$libresoc.v:41839$1816_Y + attribute \src "libresoc.v:41840.20-41840.128" + wire $and$libresoc.v:41840$1817_Y + attribute \src "libresoc.v:41841.20-41841.131" + wire $and$libresoc.v:41841$1818_Y + attribute \src "libresoc.v:41843.20-41843.110" + wire $and$libresoc.v:41843$1820_Y + attribute \src "libresoc.v:41844.20-41844.127" + wire $and$libresoc.v:41844$1821_Y + attribute \src "libresoc.v:41847.20-41847.120" + wire $and$libresoc.v:41847$1825_Y + attribute \src "libresoc.v:41848.20-41848.129" + wire $and$libresoc.v:41848$1826_Y + attribute \src "libresoc.v:41849.20-41849.129" + wire $and$libresoc.v:41849$1827_Y + attribute \src "libresoc.v:41851.19-41851.113" + wire width 12 $and$libresoc.v:41851$1829_Y + attribute \src "libresoc.v:41852.20-41852.110" + wire $and$libresoc.v:41852$1830_Y + attribute \src "libresoc.v:41853.20-41853.126" + wire $and$libresoc.v:41853$1831_Y + attribute \src "libresoc.v:41856.19-41856.113" + wire width 12 $and$libresoc.v:41856$1834_Y + attribute \src "libresoc.v:41858.19-41858.113" + wire width 12 $and$libresoc.v:41858$1836_Y + attribute \src "libresoc.v:41860.19-41860.113" + wire width 12 $and$libresoc.v:41860$1838_Y + attribute \src "libresoc.v:41862.19-41862.115" + wire width 12 $and$libresoc.v:41862$1840_Y + attribute \src "libresoc.v:41864.19-41864.115" + wire width 12 $and$libresoc.v:41864$1842_Y + attribute \src "libresoc.v:41866.19-41866.114" + wire width 12 $and$libresoc.v:41866$1844_Y + attribute \src "libresoc.v:41868.19-41868.112" + wire width 12 $and$libresoc.v:41868$1846_Y + attribute \src "libresoc.v:41870.19-41870.112" + wire width 12 $and$libresoc.v:41870$1848_Y + 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"libresoc.v:41903.19-41903.119" + wire width 3 $and$libresoc.v:41903$1881_Y + attribute \src "libresoc.v:41907.19-41907.119" + wire width 3 $and$libresoc.v:41907$1885_Y + attribute \src "libresoc.v:41911.19-41911.131" + wire $and$libresoc.v:41911$1889_Y + attribute \src "libresoc.v:41912.19-41912.119" + wire width 3 $and$libresoc.v:41912$1890_Y + attribute \src "libresoc.v:41915.19-41915.131" + wire $and$libresoc.v:41915$1893_Y + attribute \src "libresoc.v:41918.19-41918.131" + wire $and$libresoc.v:41918$1896_Y + attribute \src "libresoc.v:41919.19-41919.119" + wire width 3 $and$libresoc.v:41919$1897_Y + attribute \src "libresoc.v:41922.19-41922.131" + wire $and$libresoc.v:41922$1900_Y + attribute \src "libresoc.v:41925.19-41925.131" + wire $and$libresoc.v:41925$1903_Y + attribute \src "libresoc.v:41926.19-41926.119" + wire width 3 $and$libresoc.v:41926$1904_Y + attribute \src "libresoc.v:41929.19-41929.131" + wire $and$libresoc.v:41929$1907_Y + attribute \src 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"PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 input 21 \core_spro + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:103" + wire output 12 \core_terminate_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:103" + wire \core_terminate_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104" + wire width 3 input 24 \core_xer_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:99" + wire output 2 \corebusy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 92 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" + wire width 2 \counter + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" + wire width 2 \counter$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \cr_data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 32 \cr_full_rd__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \cr_full_rd__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 32 \cr_full_wr__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \cr_full_wr__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \cr_src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \cr_src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \cr_src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \cr_src2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \cr_src3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \cr_src3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \cr_wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire input 4 \cu_ad__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire output 5 \cu_ad__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire input 6 \cu_st__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire output 3 \cu_st__rel_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 10 \data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 84 \dbus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 45 output 89 \dbus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 83 \dbus__cyc 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attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \dec_ALU_ALU__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \dec_ALU_ALU__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_ALU_ALU__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \dec_ALU_ALU__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dec_ALU_ALU__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute 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"OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \dec_ALU_ALU__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_ALU_ALU__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_ALU_ALU__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_ALU_ALU__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_ALU_ALU__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_ALU_ALU__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_ALU_ALU__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_ALU_ALU__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_ALU_ALU__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_ALU_ALU__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_ALU_ALU__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_ALU_ALU__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + wire \dec_ALU_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + wire width 32 \dec_ALU_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 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attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute 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12 \dec_DIV_DIV__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \dec_DIV_DIV__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \dec_DIV_DIV__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dec_DIV_DIV__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + wire \dec_DIV_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + wire width 32 \dec_DIV_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LDST_LDST__byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \dec_LDST_LDST__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 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attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \dec_LOGICAL_LOGICAL__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + wire \dec_LOGICAL_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + wire width 32 \dec_LOGICAL_raw_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \dec_MUL_MUL__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \dec_MUL_MUL__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_MUL_MUL__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dec_MUL_MUL__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \dec_MUL_MUL__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_MUL_MUL__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_MUL_MUL__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_MUL_MUL__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_MUL_MUL__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_MUL_MUL__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_MUL_MUL__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_MUL_MUL__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + wire \dec_MUL_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + wire width 32 \dec_MUL_raw_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \dec_SHIFT_ROT_SHIFT_ROT__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \dec_SHIFT_ROT_SHIFT_ROT__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \dec_SHIFT_ROT_SHIFT_ROT__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dec_SHIFT_ROT_SHIFT_ROT__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \dec_SHIFT_ROT_SHIFT_ROT__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + wire \dec_SHIFT_ROT_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + wire width 32 \dec_SHIFT_ROT_raw_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \dec_SPR_SPR__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dec_SPR_SPR__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \dec_SPR_SPR__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SPR_SPR__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + wire \dec_SPR_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + wire width 32 \dec_SPR_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 input 69 \dmi__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 71 \dmi__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 70 \dmi__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \dp_CR_cr_a_branch0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \dp_CR_cr_a_branch0_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \dp_CR_cr_a_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \dp_CR_cr_a_cr0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \dp_CR_cr_b_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \dp_CR_cr_b_cr0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \dp_CR_cr_c_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \dp_CR_cr_c_cr0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \dp_CR_full_cr_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \dp_CR_full_cr_cr0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \dp_FAST_fast1_branch0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \dp_FAST_fast1_branch0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \dp_FAST_fast1_spr0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \dp_FAST_fast1_spr0_2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" 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attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_alu_branch0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_branch0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_branch0__lk + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \fus_oper_i_alu_cr0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_alu_cr0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute 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\fus_oper_i_alu_div0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute 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"OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_alu_div0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_div0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_div0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_div0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_div0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_div0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire 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attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__zero_a + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \fus_oper_i_alu_mul0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \fus_oper_i_alu_mul0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_mul0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_alu_mul0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_alu_mul0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_mul0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_mul0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_mul0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_mul0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_mul0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_mul0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_mul0__write_cr0 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \fus_oper_i_alu_shift_rot0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \fus_oper_i_alu_shift_rot0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \fus_oper_i_alu_shift_rot0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_alu_shift_rot0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_alu_shift_rot0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__write_cr0 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \fus_oper_i_alu_spr0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_alu_spr0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute 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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \rdpick_FAST_fast1_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 3 \rdpick_FAST_fast1_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 3 \rdpick_FAST_fast1_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \rdpick_FAST_fast2_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 2 \rdpick_FAST_fast2_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 2 \rdpick_FAST_fast2_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \rdpick_INT_ra_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 9 \rdpick_INT_ra_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 9 \rdpick_INT_ra_o + attribute \src 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\rp_INT_ra_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \rp_INT_ra_cr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \rp_INT_ra_div0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \rp_INT_ra_ldst0_8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \rp_INT_ra_logical0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \rp_INT_ra_mul0_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \rp_INT_ra_shiftrot0_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \rp_INT_ra_spr0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \rp_INT_ra_trap0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \rp_INT_rb_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + wire \wrflag_ldst0_o_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + wire \wrflag_logical0_cr_a_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + wire \wrflag_logical0_o_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + wire \wrflag_mul0_cr_a_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + wire \wrflag_mul0_o_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + wire \wrflag_mul0_xer_ov_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + wire \wrflag_mul0_xer_so_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + wire \wrflag_shiftrot0_cr_a_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + wire \wrflag_shiftrot0_o_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + wire \wrflag_shiftrot0_xer_ca_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + wire \wrflag_spr0_fast1_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + wire \wrflag_spr0_o_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + wire \wrflag_spr0_spr1_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + wire \wrflag_spr0_xer_ca_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + wire \wrflag_spr0_xer_ov_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + wire \wrflag_spr0_xer_so_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + wire \wrflag_trap0_fast1_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + wire \wrflag_trap0_fast1_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" + wire \wrflag_trap0_msr_4 + attribute \src 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5 \wrpick_FAST_fast1_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 5 \wrpick_FAST_fast1_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \wrpick_INT_o_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 10 \wrpick_INT_o_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 10 \wrpick_INT_o_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \wrpick_SPR_spr1_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire \wrpick_SPR_spr1_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire \wrpick_SPR_spr1_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \wrpick_STATE_msr_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire \wrpick_STATE_msr_i + attribute \src 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$and$libresoc.v:41714$1688 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_ov_o [1] + connect \B \wrpick_XER_xer_ov_en_o + connect \Y $and$libresoc.v:41714$1688_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41716$1690 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1465 + connect \B \$1469 + connect \Y $and$libresoc.v:41716$1690_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41717$1691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1465 + connect \B \wrpick_XER_xer_ov_en_o + connect \Y $and$libresoc.v:41717$1691_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:41719$1693 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_xer_ov_ok$135 + connect \B \fus_cu_busy_o$27 + connect \Y $and$libresoc.v:41719$1693_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:41720$1694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_ov_o [2] + connect \B \wrpick_XER_xer_ov_en_o + connect \Y $and$libresoc.v:41720$1694_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41722$1696 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1481 + connect \B \$1485 + connect \Y $and$libresoc.v:41722$1696_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41723$1697 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1481 + connect \B \wrpick_XER_xer_ov_en_o + connect \Y $and$libresoc.v:41723$1697_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:41725$1699 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_xer_ov_ok$136 + connect \B \fus_cu_busy_o$30 + connect \Y $and$libresoc.v:41725$1699_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:41726$1700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_ov_o [3] + connect \B \wrpick_XER_xer_ov_en_o + connect \Y $and$libresoc.v:41726$1700_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41728$1702 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1497 + connect \B \$1501 + connect \Y $and$libresoc.v:41728$1702_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41729$1703 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1497 + connect \B \wrpick_XER_xer_ov_en_o + connect \Y $and$libresoc.v:41729$1703_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:41737$1711 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_xer_so_ok + connect \B \fus_cu_busy_o + connect \Y $and$libresoc.v:41737$1711_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:41738$1712 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o [4] + connect \B \fu_enable [0] + connect \Y $and$libresoc.v:41738$1712_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:41739$1713 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$100 [3] + connect \B \fu_enable [5] + connect \Y $and$libresoc.v:41739$1713_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:41740$1714 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$103 [3] + connect \B \fu_enable [6] + connect \Y $and$libresoc.v:41740$1714_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:41741$1715 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$106 [3] + connect \B \fu_enable [7] + connect \Y $and$libresoc.v:41741$1715_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:41742$1716 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_so_o [0] + connect \B \wrpick_XER_xer_so_en_o + connect \Y $and$libresoc.v:41742$1716_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41744$1718 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + 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"/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42133$2112 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S \rp_XER_xer_ca_spr0_1 + connect \Y $ternary$libresoc.v:42133$2112_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42139$2118 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S \rp_XER_xer_ca_shiftrot0_2 + connect \Y $ternary$libresoc.v:42139$2118_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42152$2132 + parameter \WIDTH 3 + connect \A 3'000 + connect \B 3'100 + connect \S \rp_XER_xer_ov_spr0_0 + connect \Y $ternary$libresoc.v:42152$2132_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42158$2138 + parameter \WIDTH 8 + connect \A 8'00000000 + connect \B \core_core_cr_rd + connect \S \rp_CR_full_cr_cr0_0 + connect \Y $ternary$libresoc.v:42158$2138_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42166$2146 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B \$801 + connect \S \rp_CR_cr_a_cr0_0 + connect \Y $ternary$libresoc.v:42166$2146_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42174$2154 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B \$817 + connect \S \rp_CR_cr_a_branch0_1 + connect \Y $ternary$libresoc.v:42174$2154_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42183$2163 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B \$836 + connect \S \rp_CR_cr_b_cr0_0 + connect \Y $ternary$libresoc.v:42183$2163_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42191$2171 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B \$852 + connect \S \rp_CR_cr_c_cr0_0 + connect \Y $ternary$libresoc.v:42191$2171_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42197$2177 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fast1 + connect \S \rp_FAST_fast1_branch0_0 + connect \Y $ternary$libresoc.v:42197$2177_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42203$2183 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fast1 + connect \S \rp_FAST_fast1_trap0_1 + connect \Y $ternary$libresoc.v:42203$2183_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42209$2189 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fast1 + connect \S \rp_FAST_fast1_spr0_2 + connect \Y $ternary$libresoc.v:42209$2189_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42218$2198 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fast2 + connect \S \rp_FAST_fast2_branch0_0 + connect \Y $ternary$libresoc.v:42218$2198_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42224$2204 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fast2 + connect \S \rp_FAST_fast2_trap0_1 + connect \Y $ternary$libresoc.v:42224$2204_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42232$2212 + parameter \WIDTH 10 + connect \A 10'0000000000 + connect \B \core_spr1 + connect \S \rp_SPR_spr1_spr0_0 + connect \Y $ternary$libresoc.v:42232$2212_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:42249$2229 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_rego + connect \S \wp + connect \Y $ternary$libresoc.v:42249$2229_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:42255$2235 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_rego + connect \S \wp$989 + connect \Y $ternary$libresoc.v:42255$2235_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42416.6-42433.4" + cell \cr \cr + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \data_i \cr_data_i + connect \full_rd2__data_o \full_rd2__data_o + connect \full_rd2__ren \full_rd2__ren + connect \full_rd__data_o \cr_full_rd__data_o + connect \full_rd__ren \cr_full_rd__ren + connect \full_wr__data_i \cr_full_wr__data_i + connect \full_wr__wen \cr_full_wr__wen + connect \src1__data_o \cr_src1__data_o + connect \src1__ren \cr_src1__ren + connect \src2__data_o \cr_src2__data_o + connect \src2__ren \cr_src2__ren + connect \src3__data_o \cr_src3__data_o + connect \src3__ren \cr_src3__ren + connect \wen \cr_wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42434.11-42455.4" + cell \dec_ALU \dec_ALU + connect \ALU__data_len \dec_ALU_ALU__data_len + connect \ALU__fn_unit \dec_ALU_ALU__fn_unit + connect \ALU__imm_data__data \dec_ALU_ALU__imm_data__data + connect \ALU__imm_data__ok \dec_ALU_ALU__imm_data__ok + connect \ALU__input_carry \dec_ALU_ALU__input_carry + connect \ALU__insn \dec_ALU_ALU__insn + connect \ALU__insn_type \dec_ALU_ALU__insn_type + connect \ALU__invert_in \dec_ALU_ALU__invert_in + connect \ALU__invert_out \dec_ALU_ALU__invert_out + connect \ALU__is_32bit \dec_ALU_ALU__is_32bit + connect \ALU__is_signed \dec_ALU_ALU__is_signed + connect \ALU__oe__oe \dec_ALU_ALU__oe__oe + connect \ALU__oe__ok \dec_ALU_ALU__oe__ok + connect \ALU__output_carry \dec_ALU_ALU__output_carry + connect \ALU__rc__ok \dec_ALU_ALU__rc__ok + connect \ALU__rc__rc \dec_ALU_ALU__rc__rc + connect \ALU__write_cr0 \dec_ALU_ALU__write_cr0 + connect \ALU__zero_a \dec_ALU_ALU__zero_a + connect \bigendian \dec_ALU_bigendian + connect \raw_opcode_in \dec_ALU_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42456.14-42468.4" + cell \dec_BRANCH \dec_BRANCH + connect \BRANCH__cia \dec_BRANCH_BRANCH__cia + connect \BRANCH__fn_unit \dec_BRANCH_BRANCH__fn_unit + connect \BRANCH__imm_data__data \dec_BRANCH_BRANCH__imm_data__data + connect \BRANCH__imm_data__ok \dec_BRANCH_BRANCH__imm_data__ok + connect \BRANCH__insn \dec_BRANCH_BRANCH__insn + connect \BRANCH__insn_type \dec_BRANCH_BRANCH__insn_type + connect \BRANCH__is_32bit \dec_BRANCH_BRANCH__is_32bit + connect \BRANCH__lk \dec_BRANCH_BRANCH__lk + connect \bigendian \dec_BRANCH_bigendian + connect \core_pc \core_pc + connect \raw_opcode_in \dec_BRANCH_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42469.10-42475.4" + cell \dec_CR \dec_CR + connect \CR__fn_unit \dec_CR_CR__fn_unit + connect \CR__insn \dec_CR_CR__insn + connect \CR__insn_type \dec_CR_CR__insn_type + connect \bigendian \dec_CR_bigendian + connect \raw_opcode_in \dec_CR_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42476.11-42497.4" + cell \dec_DIV \dec_DIV + connect \DIV__data_len \dec_DIV_DIV__data_len + connect \DIV__fn_unit \dec_DIV_DIV__fn_unit + connect \DIV__imm_data__data \dec_DIV_DIV__imm_data__data + connect \DIV__imm_data__ok \dec_DIV_DIV__imm_data__ok + connect \DIV__input_carry \dec_DIV_DIV__input_carry + connect \DIV__insn \dec_DIV_DIV__insn + connect \DIV__insn_type \dec_DIV_DIV__insn_type + connect \DIV__invert_in \dec_DIV_DIV__invert_in + connect \DIV__invert_out \dec_DIV_DIV__invert_out + connect \DIV__is_32bit \dec_DIV_DIV__is_32bit + connect \DIV__is_signed \dec_DIV_DIV__is_signed + connect \DIV__oe__oe \dec_DIV_DIV__oe__oe + connect \DIV__oe__ok \dec_DIV_DIV__oe__ok + connect \DIV__output_carry \dec_DIV_DIV__output_carry + connect \DIV__rc__ok \dec_DIV_DIV__rc__ok + connect \DIV__rc__rc \dec_DIV_DIV__rc__rc + connect \DIV__write_cr0 \dec_DIV_DIV__write_cr0 + connect \DIV__zero_a \dec_DIV_DIV__zero_a + connect \bigendian \dec_DIV_bigendian + connect \raw_opcode_in \dec_DIV_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42498.12-42517.4" + cell \dec_LDST \dec_LDST + connect \LDST__byte_reverse \dec_LDST_LDST__byte_reverse + connect \LDST__data_len \dec_LDST_LDST__data_len + connect \LDST__fn_unit \dec_LDST_LDST__fn_unit + connect \LDST__imm_data__data \dec_LDST_LDST__imm_data__data + connect \LDST__imm_data__ok \dec_LDST_LDST__imm_data__ok + connect \LDST__insn \dec_LDST_LDST__insn + connect \LDST__insn_type \dec_LDST_LDST__insn_type + connect \LDST__is_32bit \dec_LDST_LDST__is_32bit + connect \LDST__is_signed \dec_LDST_LDST__is_signed + connect \LDST__ldst_mode \dec_LDST_LDST__ldst_mode + connect \LDST__oe__oe \dec_LDST_LDST__oe__oe + connect \LDST__oe__ok \dec_LDST_LDST__oe__ok + connect \LDST__rc__ok \dec_LDST_LDST__rc__ok + connect \LDST__rc__rc \dec_LDST_LDST__rc__rc + connect \LDST__sign_extend \dec_LDST_LDST__sign_extend + connect \LDST__zero_a \dec_LDST_LDST__zero_a + connect \bigendian \dec_LDST_bigendian + connect \raw_opcode_in \dec_LDST_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42518.15-42539.4" + cell \dec_LOGICAL \dec_LOGICAL + connect \LOGICAL__data_len \dec_LOGICAL_LOGICAL__data_len + connect \LOGICAL__fn_unit \dec_LOGICAL_LOGICAL__fn_unit + connect \LOGICAL__imm_data__data \dec_LOGICAL_LOGICAL__imm_data__data + connect \LOGICAL__imm_data__ok \dec_LOGICAL_LOGICAL__imm_data__ok + connect \LOGICAL__input_carry \dec_LOGICAL_LOGICAL__input_carry + connect \LOGICAL__insn \dec_LOGICAL_LOGICAL__insn + connect \LOGICAL__insn_type \dec_LOGICAL_LOGICAL__insn_type + connect \LOGICAL__invert_in \dec_LOGICAL_LOGICAL__invert_in + connect \LOGICAL__invert_out \dec_LOGICAL_LOGICAL__invert_out + connect \LOGICAL__is_32bit \dec_LOGICAL_LOGICAL__is_32bit + connect \LOGICAL__is_signed \dec_LOGICAL_LOGICAL__is_signed + connect \LOGICAL__oe__oe \dec_LOGICAL_LOGICAL__oe__oe + connect \LOGICAL__oe__ok \dec_LOGICAL_LOGICAL__oe__ok + connect \LOGICAL__output_carry \dec_LOGICAL_LOGICAL__output_carry + connect \LOGICAL__rc__ok \dec_LOGICAL_LOGICAL__rc__ok + connect \LOGICAL__rc__rc \dec_LOGICAL_LOGICAL__rc__rc + connect \LOGICAL__write_cr0 \dec_LOGICAL_LOGICAL__write_cr0 + connect \LOGICAL__zero_a \dec_LOGICAL_LOGICAL__zero_a + connect \bigendian \dec_LOGICAL_bigendian + connect \raw_opcode_in \dec_LOGICAL_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42540.11-42555.4" + cell \dec_MUL \dec_MUL + connect \MUL__fn_unit \dec_MUL_MUL__fn_unit + connect \MUL__imm_data__data \dec_MUL_MUL__imm_data__data + connect \MUL__imm_data__ok \dec_MUL_MUL__imm_data__ok + connect \MUL__insn \dec_MUL_MUL__insn + connect \MUL__insn_type \dec_MUL_MUL__insn_type + connect \MUL__is_32bit \dec_MUL_MUL__is_32bit + connect \MUL__is_signed \dec_MUL_MUL__is_signed + connect \MUL__oe__oe \dec_MUL_MUL__oe__oe + connect \MUL__oe__ok \dec_MUL_MUL__oe__ok + connect \MUL__rc__ok \dec_MUL_MUL__rc__ok + connect \MUL__rc__rc \dec_MUL_MUL__rc__rc + connect \MUL__write_cr0 \dec_MUL_MUL__write_cr0 + connect \bigendian \dec_MUL_bigendian + connect \raw_opcode_in \dec_MUL_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42556.17-42576.4" + cell \dec_SHIFT_ROT \dec_SHIFT_ROT + connect \SHIFT_ROT__fn_unit \dec_SHIFT_ROT_SHIFT_ROT__fn_unit + connect \SHIFT_ROT__imm_data__data \dec_SHIFT_ROT_SHIFT_ROT__imm_data__data + connect \SHIFT_ROT__imm_data__ok \dec_SHIFT_ROT_SHIFT_ROT__imm_data__ok + connect \SHIFT_ROT__input_carry \dec_SHIFT_ROT_SHIFT_ROT__input_carry + connect \SHIFT_ROT__input_cr \dec_SHIFT_ROT_SHIFT_ROT__input_cr + connect \SHIFT_ROT__insn \dec_SHIFT_ROT_SHIFT_ROT__insn + connect \SHIFT_ROT__insn_type \dec_SHIFT_ROT_SHIFT_ROT__insn_type + connect \SHIFT_ROT__invert_in \dec_SHIFT_ROT_SHIFT_ROT__invert_in + connect \SHIFT_ROT__is_32bit \dec_SHIFT_ROT_SHIFT_ROT__is_32bit + connect \SHIFT_ROT__is_signed \dec_SHIFT_ROT_SHIFT_ROT__is_signed + connect \SHIFT_ROT__oe__oe \dec_SHIFT_ROT_SHIFT_ROT__oe__oe + connect \SHIFT_ROT__oe__ok \dec_SHIFT_ROT_SHIFT_ROT__oe__ok + connect \SHIFT_ROT__output_carry \dec_SHIFT_ROT_SHIFT_ROT__output_carry + connect \SHIFT_ROT__output_cr \dec_SHIFT_ROT_SHIFT_ROT__output_cr + connect \SHIFT_ROT__rc__ok \dec_SHIFT_ROT_SHIFT_ROT__rc__ok + connect \SHIFT_ROT__rc__rc \dec_SHIFT_ROT_SHIFT_ROT__rc__rc + connect \SHIFT_ROT__write_cr0 \dec_SHIFT_ROT_SHIFT_ROT__write_cr0 + connect \bigendian \dec_SHIFT_ROT_bigendian + connect \raw_opcode_in \dec_SHIFT_ROT_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42577.11-42584.4" + cell \dec_SPR \dec_SPR + connect \SPR__fn_unit \dec_SPR_SPR__fn_unit + connect \SPR__insn \dec_SPR_SPR__insn + connect \SPR__insn_type \dec_SPR_SPR__insn_type + connect \SPR__is_32bit \dec_SPR_SPR__is_32bit + connect \bigendian \dec_SPR_bigendian + connect \raw_opcode_in \dec_SPR_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42585.8-42603.4" + cell \fast \fast + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest1__addr \fast_dest1__addr + connect \dest1__data_i \fast_dest1__data_i + connect \dest1__wen \fast_dest1__wen + connect \issue__addr \issue__addr + connect \issue__addr$1 \issue__addr$10 + connect \issue__data_i \issue__data_i + connect \issue__data_o \issue__data_o + connect \issue__ren \issue__ren + connect \issue__wen \issue__wen + connect \src1__addr \fast_src1__addr + connect \src1__data_o \fast_src1__data_o + connect \src1__ren \fast_src1__ren + connect \src2__addr \fast_src2__addr + connect \src2__data_o \fast_src2__data_o + connect \src2__ren \fast_src2__ren + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42604.7-42935.4" + cell \fus \fus + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \fus_cr_a_ok + connect \cr_a_ok$110 \fus_cr_a_ok$120 + connect \cr_a_ok$111 \fus_cr_a_ok$121 + connect \cr_a_ok$112 \fus_cr_a_ok$122 + connect \cr_a_ok$113 \fus_cr_a_ok$123 + connect \cr_a_ok$114 \fus_cr_a_ok$124 + connect \cu_ad__go_i \cu_ad__go_i + connect \cu_ad__rel_o \cu_ad__rel_o + connect \cu_busy_o \fus_cu_busy_o + connect \cu_busy_o$11 \fus_cu_busy_o$21 + connect \cu_busy_o$14 \fus_cu_busy_o$24 + connect \cu_busy_o$17 \fus_cu_busy_o$27 + connect \cu_busy_o$2 \fus_cu_busy_o$12 + connect \cu_busy_o$20 \fus_cu_busy_o$30 + connect \cu_busy_o$23 \fus_cu_busy_o$33 + connect \cu_busy_o$26 \fus_cu_busy_o$36 + connect \cu_busy_o$5 \fus_cu_busy_o$15 + connect \cu_busy_o$8 \fus_cu_busy_o$18 + connect \cu_issue_i \fus_cu_issue_i + connect \cu_issue_i$1 \fus_cu_issue_i$11 + connect \cu_issue_i$10 \fus_cu_issue_i$20 + connect \cu_issue_i$13 \fus_cu_issue_i$23 + connect \cu_issue_i$16 \fus_cu_issue_i$26 + connect \cu_issue_i$19 \fus_cu_issue_i$29 + connect \cu_issue_i$22 \fus_cu_issue_i$32 + connect \cu_issue_i$25 \fus_cu_issue_i$35 + connect \cu_issue_i$4 \fus_cu_issue_i$14 + connect \cu_issue_i$7 \fus_cu_issue_i$17 + connect \cu_rd__go_i \fus_cu_rd__go_i + connect \cu_rd__go_i$29 \fus_cu_rd__go_i$39 + connect \cu_rd__go_i$32 \fus_cu_rd__go_i$42 + connect \cu_rd__go_i$35 \fus_cu_rd__go_i$45 + connect \cu_rd__go_i$38 \fus_cu_rd__go_i$48 + connect \cu_rd__go_i$41 \fus_cu_rd__go_i$51 + connect \cu_rd__go_i$44 \fus_cu_rd__go_i$54 + connect \cu_rd__go_i$47 \fus_cu_rd__go_i$57 + connect \cu_rd__go_i$50 \fus_cu_rd__go_i$60 + connect \cu_rd__go_i$70 \fus_cu_rd__go_i$80 + connect \cu_rd__rel_o \fus_cu_rd__rel_o + connect \cu_rd__rel_o$28 \fus_cu_rd__rel_o$38 + connect \cu_rd__rel_o$31 \fus_cu_rd__rel_o$41 + connect \cu_rd__rel_o$34 \fus_cu_rd__rel_o$44 + connect \cu_rd__rel_o$37 \fus_cu_rd__rel_o$47 + connect \cu_rd__rel_o$40 \fus_cu_rd__rel_o$50 + connect \cu_rd__rel_o$43 \fus_cu_rd__rel_o$53 + connect \cu_rd__rel_o$46 \fus_cu_rd__rel_o$56 + connect \cu_rd__rel_o$49 \fus_cu_rd__rel_o$59 + connect \cu_rd__rel_o$69 \fus_cu_rd__rel_o$79 + connect \cu_rdmaskn_i \fus_cu_rdmaskn_i + connect \cu_rdmaskn_i$12 \fus_cu_rdmaskn_i$22 + connect \cu_rdmaskn_i$15 \fus_cu_rdmaskn_i$25 + connect \cu_rdmaskn_i$18 \fus_cu_rdmaskn_i$28 + connect \cu_rdmaskn_i$21 \fus_cu_rdmaskn_i$31 + connect \cu_rdmaskn_i$24 \fus_cu_rdmaskn_i$34 + connect \cu_rdmaskn_i$27 \fus_cu_rdmaskn_i$37 + connect \cu_rdmaskn_i$3 \fus_cu_rdmaskn_i$13 + connect \cu_rdmaskn_i$6 \fus_cu_rdmaskn_i$16 + connect \cu_rdmaskn_i$9 \fus_cu_rdmaskn_i$19 + connect \cu_st__go_i \cu_st__go_i + connect \cu_st__rel_o \cu_st__rel_o + connect \cu_wr__go_i \fus_cu_wr__go_i + connect \cu_wr__go_i$100 \fus_cu_wr__go_i$110 + connect \cu_wr__go_i$102 \fus_cu_wr__go_i$112 + connect \cu_wr__go_i$137 \fus_cu_wr__go_i$147 + connect \cu_wr__go_i$82 \fus_cu_wr__go_i$92 + connect \cu_wr__go_i$85 \fus_cu_wr__go_i$95 + connect \cu_wr__go_i$88 \fus_cu_wr__go_i$98 + connect \cu_wr__go_i$91 \fus_cu_wr__go_i$101 + connect \cu_wr__go_i$94 \fus_cu_wr__go_i$104 + connect \cu_wr__go_i$97 \fus_cu_wr__go_i$107 + connect \cu_wr__rel_o \fus_cu_wr__rel_o + connect \cu_wr__rel_o$101 \fus_cu_wr__rel_o$111 + connect \cu_wr__rel_o$136 \fus_cu_wr__rel_o$146 + connect \cu_wr__rel_o$81 \fus_cu_wr__rel_o$91 + connect \cu_wr__rel_o$84 \fus_cu_wr__rel_o$94 + connect \cu_wr__rel_o$87 \fus_cu_wr__rel_o$97 + connect \cu_wr__rel_o$90 \fus_cu_wr__rel_o$100 + connect \cu_wr__rel_o$93 \fus_cu_wr__rel_o$103 + connect \cu_wr__rel_o$96 \fus_cu_wr__rel_o$106 + connect \cu_wr__rel_o$99 \fus_cu_wr__rel_o$109 + connect \dest1_o \fus_dest1_o + connect \dest1_o$103 \fus_dest1_o$113 + connect \dest1_o$104 \fus_dest1_o$114 + connect \dest1_o$105 \fus_dest1_o$115 + connect \dest1_o$106 \fus_dest1_o$116 + connect \dest1_o$107 \fus_dest1_o$117 + connect \dest1_o$108 \fus_dest1_o$118 + connect \dest1_o$109 \fus_dest1_o$119 + connect \dest1_o$141 \fus_dest1_o$151 + connect \dest2_o \fus_dest2_o + connect \dest2_o$115 \fus_dest2_o$125 + connect \dest2_o$116 \fus_dest2_o$126 + connect \dest2_o$117 \fus_dest2_o$127 + connect \dest2_o$118 \fus_dest2_o$128 + connect \dest2_o$119 \fus_dest2_o$129 + connect \dest2_o$142 \fus_dest2_o$152 + connect \dest2_o$144 \fus_dest2_o$154 + connect \dest2_o$150 \fus_dest2_o$160 + connect \dest3_o \fus_dest3_o + connect \dest3_o$122 \fus_dest3_o$132 + connect \dest3_o$123 \fus_dest3_o$133 + connect \dest3_o$127 \fus_dest3_o$137 + connect \dest3_o$128 \fus_dest3_o$138 + connect \dest3_o$143 \fus_dest3_o$153 + connect \dest3_o$145 \fus_dest3_o$155 + connect \dest3_o$147 \fus_dest3_o$157 + connect \dest4_o \fus_dest4_o + connect \dest4_o$133 \fus_dest4_o$143 + connect \dest4_o$134 \fus_dest4_o$144 + connect \dest4_o$135 \fus_dest4_o$145 + connect \dest4_o$148 \fus_dest4_o$158 + connect \dest5_o \fus_dest5_o + connect \dest5_o$132 \fus_dest5_o$142 + connect \dest5_o$149 \fus_dest5_o$159 + connect \dest6_o \fus_dest6_o + connect \ea \fus_ea + connect \fast1_ok \fus_fast1_ok + connect \fast1_ok$138 \fus_fast1_ok$148 + connect \fast1_ok$139 \fus_fast1_ok$149 + connect \fast2_ok \fus_fast2_ok + connect \fast2_ok$140 \fus_fast2_ok$150 + connect \full_cr_ok \fus_full_cr_ok + connect \ldst_port0_addr_i \fus_ldst_port0_addr_i + connect \ldst_port0_addr_i_ok \fus_ldst_port0_addr_i_ok + connect \ldst_port0_addr_ok_o \fus_ldst_port0_addr_ok_o + connect \ldst_port0_busy_o \fus_ldst_port0_busy_o + connect \ldst_port0_data_len \fus_ldst_port0_data_len + connect \ldst_port0_exc_$signal \fus_ldst_port0_exc_$signal + connect \ldst_port0_exc_$signal$151 \fus_ldst_port0_exc_$signal$161 + connect \ldst_port0_exc_$signal$152 \fus_ldst_port0_exc_$signal$162 + connect \ldst_port0_exc_$signal$153 \fus_ldst_port0_exc_$signal$163 + connect \ldst_port0_exc_$signal$154 \fus_ldst_port0_exc_$signal$164 + connect \ldst_port0_exc_$signal$155 \fus_ldst_port0_exc_$signal$165 + connect \ldst_port0_exc_$signal$156 \fus_ldst_port0_exc_$signal$166 + connect \ldst_port0_exc_$signal$157 \fus_ldst_port0_exc_$signal$167 + connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i + connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i + connect \ldst_port0_ld_data_o \fus_ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o_ok \fus_ldst_port0_ld_data_o_ok + connect \ldst_port0_st_data_i \fus_ldst_port0_st_data_i + connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok + connect \msr_ok \fus_msr_ok + connect \nia_ok \fus_nia_ok + connect \nia_ok$146 \fus_nia_ok$156 + connect \o \fus_o + connect \o_ok \fus_o_ok + connect \o_ok$80 \fus_o_ok$90 + connect \o_ok$83 \fus_o_ok$93 + connect \o_ok$86 \fus_o_ok$96 + connect \o_ok$89 \fus_o_ok$99 + connect \o_ok$92 \fus_o_ok$102 + connect \o_ok$95 \fus_o_ok$105 + connect \o_ok$98 \fus_o_ok$108 + connect \oper_i_alu_alu0__data_len \fus_oper_i_alu_alu0__data_len + connect \oper_i_alu_alu0__fn_unit \fus_oper_i_alu_alu0__fn_unit + connect \oper_i_alu_alu0__imm_data__data \fus_oper_i_alu_alu0__imm_data__data + connect \oper_i_alu_alu0__imm_data__ok \fus_oper_i_alu_alu0__imm_data__ok + connect \oper_i_alu_alu0__input_carry \fus_oper_i_alu_alu0__input_carry + connect \oper_i_alu_alu0__insn \fus_oper_i_alu_alu0__insn + connect \oper_i_alu_alu0__insn_type \fus_oper_i_alu_alu0__insn_type + connect \oper_i_alu_alu0__invert_in \fus_oper_i_alu_alu0__invert_in + connect \oper_i_alu_alu0__invert_out \fus_oper_i_alu_alu0__invert_out + connect \oper_i_alu_alu0__is_32bit \fus_oper_i_alu_alu0__is_32bit + connect \oper_i_alu_alu0__is_signed \fus_oper_i_alu_alu0__is_signed + connect \oper_i_alu_alu0__oe__oe \fus_oper_i_alu_alu0__oe__oe + connect \oper_i_alu_alu0__oe__ok \fus_oper_i_alu_alu0__oe__ok + connect \oper_i_alu_alu0__output_carry \fus_oper_i_alu_alu0__output_carry + connect \oper_i_alu_alu0__rc__ok \fus_oper_i_alu_alu0__rc__ok + connect \oper_i_alu_alu0__rc__rc \fus_oper_i_alu_alu0__rc__rc + connect \oper_i_alu_alu0__write_cr0 \fus_oper_i_alu_alu0__write_cr0 + connect \oper_i_alu_alu0__zero_a \fus_oper_i_alu_alu0__zero_a + connect \oper_i_alu_branch0__cia \fus_oper_i_alu_branch0__cia + connect \oper_i_alu_branch0__fn_unit \fus_oper_i_alu_branch0__fn_unit + connect \oper_i_alu_branch0__imm_data__data \fus_oper_i_alu_branch0__imm_data__data + connect \oper_i_alu_branch0__imm_data__ok \fus_oper_i_alu_branch0__imm_data__ok + connect \oper_i_alu_branch0__insn \fus_oper_i_alu_branch0__insn + connect \oper_i_alu_branch0__insn_type \fus_oper_i_alu_branch0__insn_type + connect \oper_i_alu_branch0__is_32bit \fus_oper_i_alu_branch0__is_32bit + connect \oper_i_alu_branch0__lk \fus_oper_i_alu_branch0__lk + connect \oper_i_alu_cr0__fn_unit \fus_oper_i_alu_cr0__fn_unit + connect \oper_i_alu_cr0__insn \fus_oper_i_alu_cr0__insn + connect \oper_i_alu_cr0__insn_type \fus_oper_i_alu_cr0__insn_type + connect \oper_i_alu_div0__data_len \fus_oper_i_alu_div0__data_len + connect \oper_i_alu_div0__fn_unit \fus_oper_i_alu_div0__fn_unit + connect \oper_i_alu_div0__imm_data__data \fus_oper_i_alu_div0__imm_data__data + connect \oper_i_alu_div0__imm_data__ok \fus_oper_i_alu_div0__imm_data__ok + connect \oper_i_alu_div0__input_carry \fus_oper_i_alu_div0__input_carry + connect \oper_i_alu_div0__insn \fus_oper_i_alu_div0__insn + connect \oper_i_alu_div0__insn_type \fus_oper_i_alu_div0__insn_type + connect \oper_i_alu_div0__invert_in \fus_oper_i_alu_div0__invert_in + connect \oper_i_alu_div0__invert_out \fus_oper_i_alu_div0__invert_out + connect \oper_i_alu_div0__is_32bit \fus_oper_i_alu_div0__is_32bit + connect \oper_i_alu_div0__is_signed \fus_oper_i_alu_div0__is_signed + connect \oper_i_alu_div0__oe__oe \fus_oper_i_alu_div0__oe__oe + connect \oper_i_alu_div0__oe__ok \fus_oper_i_alu_div0__oe__ok + connect \oper_i_alu_div0__output_carry \fus_oper_i_alu_div0__output_carry + connect \oper_i_alu_div0__rc__ok \fus_oper_i_alu_div0__rc__ok + connect \oper_i_alu_div0__rc__rc \fus_oper_i_alu_div0__rc__rc + connect \oper_i_alu_div0__write_cr0 \fus_oper_i_alu_div0__write_cr0 + connect \oper_i_alu_div0__zero_a \fus_oper_i_alu_div0__zero_a + connect \oper_i_alu_logical0__data_len \fus_oper_i_alu_logical0__data_len + connect \oper_i_alu_logical0__fn_unit \fus_oper_i_alu_logical0__fn_unit + connect \oper_i_alu_logical0__imm_data__data \fus_oper_i_alu_logical0__imm_data__data + connect \oper_i_alu_logical0__imm_data__ok \fus_oper_i_alu_logical0__imm_data__ok + connect \oper_i_alu_logical0__input_carry \fus_oper_i_alu_logical0__input_carry + connect \oper_i_alu_logical0__insn \fus_oper_i_alu_logical0__insn + connect \oper_i_alu_logical0__insn_type \fus_oper_i_alu_logical0__insn_type + connect \oper_i_alu_logical0__invert_in \fus_oper_i_alu_logical0__invert_in + connect \oper_i_alu_logical0__invert_out \fus_oper_i_alu_logical0__invert_out + connect \oper_i_alu_logical0__is_32bit \fus_oper_i_alu_logical0__is_32bit + connect \oper_i_alu_logical0__is_signed \fus_oper_i_alu_logical0__is_signed + connect \oper_i_alu_logical0__oe__oe \fus_oper_i_alu_logical0__oe__oe + connect \oper_i_alu_logical0__oe__ok \fus_oper_i_alu_logical0__oe__ok + connect \oper_i_alu_logical0__output_carry \fus_oper_i_alu_logical0__output_carry + connect \oper_i_alu_logical0__rc__ok \fus_oper_i_alu_logical0__rc__ok + connect \oper_i_alu_logical0__rc__rc \fus_oper_i_alu_logical0__rc__rc + connect \oper_i_alu_logical0__write_cr0 \fus_oper_i_alu_logical0__write_cr0 + connect \oper_i_alu_logical0__zero_a \fus_oper_i_alu_logical0__zero_a + connect \oper_i_alu_mul0__fn_unit \fus_oper_i_alu_mul0__fn_unit + connect \oper_i_alu_mul0__imm_data__data \fus_oper_i_alu_mul0__imm_data__data + connect \oper_i_alu_mul0__imm_data__ok \fus_oper_i_alu_mul0__imm_data__ok + connect \oper_i_alu_mul0__insn \fus_oper_i_alu_mul0__insn + connect \oper_i_alu_mul0__insn_type \fus_oper_i_alu_mul0__insn_type + connect \oper_i_alu_mul0__is_32bit \fus_oper_i_alu_mul0__is_32bit + connect \oper_i_alu_mul0__is_signed \fus_oper_i_alu_mul0__is_signed + connect \oper_i_alu_mul0__oe__oe \fus_oper_i_alu_mul0__oe__oe + connect \oper_i_alu_mul0__oe__ok \fus_oper_i_alu_mul0__oe__ok + connect \oper_i_alu_mul0__rc__ok \fus_oper_i_alu_mul0__rc__ok + connect \oper_i_alu_mul0__rc__rc \fus_oper_i_alu_mul0__rc__rc + connect \oper_i_alu_mul0__write_cr0 \fus_oper_i_alu_mul0__write_cr0 + connect \oper_i_alu_shift_rot0__fn_unit \fus_oper_i_alu_shift_rot0__fn_unit + connect \oper_i_alu_shift_rot0__imm_data__data \fus_oper_i_alu_shift_rot0__imm_data__data + connect \oper_i_alu_shift_rot0__imm_data__ok \fus_oper_i_alu_shift_rot0__imm_data__ok + connect \oper_i_alu_shift_rot0__input_carry \fus_oper_i_alu_shift_rot0__input_carry + connect \oper_i_alu_shift_rot0__input_cr \fus_oper_i_alu_shift_rot0__input_cr + connect \oper_i_alu_shift_rot0__insn \fus_oper_i_alu_shift_rot0__insn + connect \oper_i_alu_shift_rot0__insn_type \fus_oper_i_alu_shift_rot0__insn_type + connect \oper_i_alu_shift_rot0__invert_in \fus_oper_i_alu_shift_rot0__invert_in + connect \oper_i_alu_shift_rot0__is_32bit \fus_oper_i_alu_shift_rot0__is_32bit + connect \oper_i_alu_shift_rot0__is_signed \fus_oper_i_alu_shift_rot0__is_signed + connect \oper_i_alu_shift_rot0__oe__oe \fus_oper_i_alu_shift_rot0__oe__oe + connect \oper_i_alu_shift_rot0__oe__ok \fus_oper_i_alu_shift_rot0__oe__ok + connect \oper_i_alu_shift_rot0__output_carry \fus_oper_i_alu_shift_rot0__output_carry + connect \oper_i_alu_shift_rot0__output_cr \fus_oper_i_alu_shift_rot0__output_cr + connect \oper_i_alu_shift_rot0__rc__ok \fus_oper_i_alu_shift_rot0__rc__ok + connect \oper_i_alu_shift_rot0__rc__rc \fus_oper_i_alu_shift_rot0__rc__rc + connect \oper_i_alu_shift_rot0__write_cr0 \fus_oper_i_alu_shift_rot0__write_cr0 + connect \oper_i_alu_spr0__fn_unit \fus_oper_i_alu_spr0__fn_unit + connect \oper_i_alu_spr0__insn \fus_oper_i_alu_spr0__insn + connect \oper_i_alu_spr0__insn_type \fus_oper_i_alu_spr0__insn_type + connect \oper_i_alu_spr0__is_32bit \fus_oper_i_alu_spr0__is_32bit + connect \oper_i_alu_trap0__cia \fus_oper_i_alu_trap0__cia + connect \oper_i_alu_trap0__fn_unit \fus_oper_i_alu_trap0__fn_unit + connect \oper_i_alu_trap0__insn \fus_oper_i_alu_trap0__insn + connect \oper_i_alu_trap0__insn_type \fus_oper_i_alu_trap0__insn_type + connect \oper_i_alu_trap0__is_32bit \fus_oper_i_alu_trap0__is_32bit + connect \oper_i_alu_trap0__ldst_exc \fus_oper_i_alu_trap0__ldst_exc + connect \oper_i_alu_trap0__msr \fus_oper_i_alu_trap0__msr + connect \oper_i_alu_trap0__trapaddr \fus_oper_i_alu_trap0__trapaddr + connect \oper_i_alu_trap0__traptype \fus_oper_i_alu_trap0__traptype + connect \oper_i_ldst_ldst0__byte_reverse \fus_oper_i_ldst_ldst0__byte_reverse + connect \oper_i_ldst_ldst0__data_len \fus_oper_i_ldst_ldst0__data_len + connect \oper_i_ldst_ldst0__fn_unit \fus_oper_i_ldst_ldst0__fn_unit + connect \oper_i_ldst_ldst0__imm_data__data \fus_oper_i_ldst_ldst0__imm_data__data + connect \oper_i_ldst_ldst0__imm_data__ok \fus_oper_i_ldst_ldst0__imm_data__ok + connect \oper_i_ldst_ldst0__insn \fus_oper_i_ldst_ldst0__insn + connect \oper_i_ldst_ldst0__insn_type \fus_oper_i_ldst_ldst0__insn_type + connect \oper_i_ldst_ldst0__is_32bit \fus_oper_i_ldst_ldst0__is_32bit + connect \oper_i_ldst_ldst0__is_signed \fus_oper_i_ldst_ldst0__is_signed + connect \oper_i_ldst_ldst0__ldst_mode \fus_oper_i_ldst_ldst0__ldst_mode + connect \oper_i_ldst_ldst0__oe__oe \fus_oper_i_ldst_ldst0__oe__oe + connect \oper_i_ldst_ldst0__oe__ok \fus_oper_i_ldst_ldst0__oe__ok + connect \oper_i_ldst_ldst0__rc__ok \fus_oper_i_ldst_ldst0__rc__ok + connect \oper_i_ldst_ldst0__rc__rc \fus_oper_i_ldst_ldst0__rc__rc + connect \oper_i_ldst_ldst0__sign_extend \fus_oper_i_ldst_ldst0__sign_extend + connect \oper_i_ldst_ldst0__zero_a \fus_oper_i_ldst_ldst0__zero_a + connect \spr1_ok \fus_spr1_ok + connect \src1_i \fus_src1_i + connect \src1_i$30 \fus_src1_i$40 + connect \src1_i$33 \fus_src1_i$43 + connect \src1_i$36 \fus_src1_i$46 + connect \src1_i$39 \fus_src1_i$49 + connect \src1_i$42 \fus_src1_i$52 + connect \src1_i$45 \fus_src1_i$55 + connect \src1_i$48 \fus_src1_i$58 + connect \src1_i$51 \fus_src1_i$61 + connect \src1_i$74 \fus_src1_i$84 + connect \src2_i \fus_src2_i + connect \src2_i$52 \fus_src2_i$62 + connect \src2_i$53 \fus_src2_i$63 + connect \src2_i$54 \fus_src2_i$64 + connect \src2_i$55 \fus_src2_i$65 + connect \src2_i$56 \fus_src2_i$66 + connect \src2_i$57 \fus_src2_i$67 + connect \src2_i$58 \fus_src2_i$68 + connect \src2_i$77 \fus_src2_i$87 + connect \src2_i$79 \fus_src2_i$89 + connect \src3_i \fus_src3_i + connect \src3_i$59 \fus_src3_i$69 + connect \src3_i$60 \fus_src3_i$70 + connect \src3_i$61 \fus_src3_i$71 + connect \src3_i$62 \fus_src3_i$72 + connect \src3_i$63 \fus_src3_i$73 + connect \src3_i$67 \fus_src3_i$77 + connect \src3_i$71 \fus_src3_i$81 + connect \src3_i$75 \fus_src3_i$85 + connect \src3_i$76 \fus_src3_i$86 + connect \src4_i \fus_src4_i + connect \src4_i$64 \fus_src4_i$74 + connect \src4_i$65 \fus_src4_i$75 + connect \src4_i$68 \fus_src4_i$78 + connect \src4_i$78 \fus_src4_i$88 + connect \src5_i \fus_src5_i + connect \src5_i$66 \fus_src5_i$76 + connect \src5_i$72 \fus_src5_i$82 + connect \src6_i \fus_src6_i + connect \src6_i$73 \fus_src6_i$83 + connect \xer_ca_ok \fus_xer_ca_ok + connect \xer_ca_ok$120 \fus_xer_ca_ok$130 + connect \xer_ca_ok$121 \fus_xer_ca_ok$131 + connect \xer_ov_ok \fus_xer_ov_ok + connect \xer_ov_ok$124 \fus_xer_ov_ok$134 + connect \xer_ov_ok$125 \fus_xer_ov_ok$135 + connect \xer_ov_ok$126 \fus_xer_ov_ok$136 + connect \xer_so_ok \fus_xer_so_ok + connect \xer_so_ok$129 \fus_xer_so_ok$139 + connect \xer_so_ok$130 \fus_xer_so_ok$140 + connect \xer_so_ok$131 \fus_xer_so_ok$141 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42936.9-42954.4" + cell \int \int + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest1__addr \int_dest1__addr + connect \dest1__data_i \int_dest1__data_i + connect \dest1__wen \int_dest1__wen + connect \dmi__addr \dmi__addr + connect \dmi__data_o \dmi__data_o + connect \dmi__ren \dmi__ren + connect \src1__addr \int_src1__addr + connect \src1__data_o \int_src1__data_o + connect \src1__ren \int_src1__ren + connect \src2__addr \int_src2__addr + connect \src2__data_o \int_src2__data_o + connect \src2__ren \int_src2__ren + connect \src3__addr \int_src3__addr + connect \src3__data_o \int_src3__data_o + connect \src3__ren \int_src3__ren + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42955.6-42987.4" + cell \l0 \l0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dbus__ack \dbus__ack + connect \dbus__adr \dbus__adr + connect \dbus__cyc \dbus__cyc + connect \dbus__dat_r \dbus__dat_r + connect \dbus__dat_w \dbus__dat_w + connect \dbus__err \dbus__err + connect \dbus__sel \dbus__sel + connect \dbus__stb \dbus__stb + connect \dbus__we \dbus__we + connect \ldst_port0_addr_i \fus_ldst_port0_addr_i + connect \ldst_port0_addr_i_ok \fus_ldst_port0_addr_i_ok + connect \ldst_port0_addr_ok_o \fus_ldst_port0_addr_ok_o + connect \ldst_port0_busy_o \fus_ldst_port0_busy_o + connect \ldst_port0_data_len \fus_ldst_port0_data_len + connect \ldst_port0_exc_$signal \fus_ldst_port0_exc_$signal + connect \ldst_port0_exc_$signal$1 \fus_ldst_port0_exc_$signal$161 + connect \ldst_port0_exc_$signal$2 \fus_ldst_port0_exc_$signal$162 + connect \ldst_port0_exc_$signal$3 \fus_ldst_port0_exc_$signal$163 + connect \ldst_port0_exc_$signal$4 \fus_ldst_port0_exc_$signal$164 + connect \ldst_port0_exc_$signal$5 \fus_ldst_port0_exc_$signal$165 + connect \ldst_port0_exc_$signal$6 \fus_ldst_port0_exc_$signal$166 + connect \ldst_port0_exc_$signal$7 \fus_ldst_port0_exc_$signal$167 + connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i + connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i + connect \ldst_port0_ld_data_o \fus_ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o_ok \fus_ldst_port0_ld_data_o_ok + connect \ldst_port0_st_data_i \fus_ldst_port0_st_data_i + connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok + connect \wb_dcache_en \wb_dcache_en + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42988.18-42992.4" + cell \rdpick_CR_cr_a \rdpick_CR_cr_a + connect \en_o \rdpick_CR_cr_a_en_o + connect \i \rdpick_CR_cr_a_i + connect \o \rdpick_CR_cr_a_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42993.18-42997.4" + cell \rdpick_CR_cr_b \rdpick_CR_cr_b + connect \en_o \rdpick_CR_cr_b_en_o + connect \i \rdpick_CR_cr_b_i + connect \o \rdpick_CR_cr_b_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42998.18-43002.4" + cell \rdpick_CR_cr_c \rdpick_CR_cr_c + connect \en_o \rdpick_CR_cr_c_en_o + connect \i \rdpick_CR_cr_c_i + connect \o \rdpick_CR_cr_c_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43003.21-43007.4" + cell \rdpick_CR_full_cr \rdpick_CR_full_cr + connect \en_o \rdpick_CR_full_cr_en_o + connect \i \rdpick_CR_full_cr_i + connect \o \rdpick_CR_full_cr_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43008.21-43012.4" + cell \rdpick_FAST_fast1 \rdpick_FAST_fast1 + connect \en_o \rdpick_FAST_fast1_en_o + connect \i \rdpick_FAST_fast1_i + connect \o \rdpick_FAST_fast1_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43013.21-43017.4" + cell \rdpick_FAST_fast2 \rdpick_FAST_fast2 + connect \en_o \rdpick_FAST_fast2_en_o + connect \i \rdpick_FAST_fast2_i + connect \o \rdpick_FAST_fast2_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43018.17-43022.4" + cell \rdpick_INT_ra \rdpick_INT_ra + connect \en_o \rdpick_INT_ra_en_o + connect \i \rdpick_INT_ra_i + connect \o \rdpick_INT_ra_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43023.17-43027.4" + cell \rdpick_INT_rb \rdpick_INT_rb + connect \en_o \rdpick_INT_rb_en_o + connect \i \rdpick_INT_rb_i + connect \o \rdpick_INT_rb_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43028.17-43032.4" + cell \rdpick_INT_rc \rdpick_INT_rc + connect \en_o \rdpick_INT_rc_en_o + connect \i \rdpick_INT_rc_i + connect \o \rdpick_INT_rc_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43033.19-43037.4" + cell \rdpick_SPR_spr1 \rdpick_SPR_spr1 + connect \en_o \rdpick_SPR_spr1_en_o + connect \i \rdpick_SPR_spr1_i + connect \o \rdpick_SPR_spr1_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43038.21-43042.4" + cell \rdpick_XER_xer_ca \rdpick_XER_xer_ca + connect \en_o \rdpick_XER_xer_ca_en_o + connect \i \rdpick_XER_xer_ca_i + connect \o \rdpick_XER_xer_ca_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43043.21-43047.4" + cell \rdpick_XER_xer_ov \rdpick_XER_xer_ov + connect \en_o \rdpick_XER_xer_ov_en_o + connect \i \rdpick_XER_xer_ov_i + connect \o \rdpick_XER_xer_ov_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43048.21-43052.4" + cell \rdpick_XER_xer_so \rdpick_XER_xer_so + connect \en_o \rdpick_XER_xer_so_en_o + connect \i \rdpick_XER_xer_so_i + connect \o \rdpick_XER_xer_so_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43053.7-43062.4" + cell \spr \spr + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \spr1__addr \spr_spr1__addr + connect \spr1__addr$1 \spr_spr1__addr$173 + connect \spr1__data_i \spr_spr1__data_i + connect \spr1__data_o \spr_spr1__data_o + connect \spr1__ren \spr_spr1__ren + connect \spr1__wen \spr_spr1__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43063.9-43076.4" + cell \state \state + connect \cia__data_o \cia__data_o + connect \cia__ren \cia__ren + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \data_i \data_i + connect \data_i$1 \state_data_i + connect \data_i$2 \state_data_i$172 + connect \msr__data_o \msr__data_o + connect \msr__ren \msr__ren + connect \state_nia_wen \state_nia_wen + connect \wen \wen + connect \wen$3 \state_wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43077.18-43081.4" + cell \wrpick_CR_cr_a \wrpick_CR_cr_a + connect \en_o \wrpick_CR_cr_a_en_o + connect \i \wrpick_CR_cr_a_i + connect \o \wrpick_CR_cr_a_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43082.21-43086.4" + cell \wrpick_CR_full_cr \wrpick_CR_full_cr + connect \en_o \wrpick_CR_full_cr_en_o + connect \i \wrpick_CR_full_cr_i + connect \o \wrpick_CR_full_cr_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43087.21-43091.4" + cell \wrpick_FAST_fast1 \wrpick_FAST_fast1 + connect \en_o \wrpick_FAST_fast1_en_o + connect \i \wrpick_FAST_fast1_i + connect \o \wrpick_FAST_fast1_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43092.16-43096.4" + cell \wrpick_INT_o \wrpick_INT_o + connect \en_o \wrpick_INT_o_en_o + connect \i \wrpick_INT_o_i + connect \o \wrpick_INT_o_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43097.19-43101.4" + cell \wrpick_SPR_spr1 \wrpick_SPR_spr1 + connect \en_o \wrpick_SPR_spr1_en_o + connect \i \wrpick_SPR_spr1_i + connect \o \wrpick_SPR_spr1_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43102.20-43106.4" + cell \wrpick_STATE_msr \wrpick_STATE_msr + connect \en_o \wrpick_STATE_msr_en_o + connect \i \wrpick_STATE_msr_i + connect \o \wrpick_STATE_msr_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43107.20-43111.4" + cell \wrpick_STATE_nia \wrpick_STATE_nia + connect \en_o \wrpick_STATE_nia_en_o + connect \i \wrpick_STATE_nia_i + connect \o \wrpick_STATE_nia_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43112.21-43116.4" + cell \wrpick_XER_xer_ca \wrpick_XER_xer_ca + connect \en_o \wrpick_XER_xer_ca_en_o + connect \i \wrpick_XER_xer_ca_i + connect \o \wrpick_XER_xer_ca_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43117.21-43121.4" + cell \wrpick_XER_xer_ov \wrpick_XER_xer_ov + connect \en_o \wrpick_XER_xer_ov_en_o + connect \i \wrpick_XER_xer_ov_i + connect \o \wrpick_XER_xer_ov_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43122.21-43126.4" + cell \wrpick_XER_xer_so \wrpick_XER_xer_so + connect \en_o \wrpick_XER_xer_so_en_o + connect \i \wrpick_XER_xer_so_i + connect \o \wrpick_XER_xer_so_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43127.7-43144.4" + cell \xer \xer + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \data_i \xer_data_i + connect \data_i$1 \xer_data_i$168 + connect \data_i$3 \xer_data_i$170 + connect \full_rd__data_o \full_rd__data_o + connect \full_rd__ren \full_rd__ren + connect \src1__data_o \xer_src1__data_o + connect \src1__ren \xer_src1__ren + connect \src2__data_o \xer_src2__data_o + connect \src2__ren \xer_src2__ren + connect \src3__data_o \xer_src3__data_o + connect \src3__ren \xer_src3__ren + connect \wen \xer_wen + connect \wen$2 \xer_wen$169 + connect \wen$4 \xer_wen$171 + end + attribute \src "libresoc.v:35746.7-35746.20" + process $proc$libresoc.v:35746$2900 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:37778.7-37778.30" + process $proc$libresoc.v:37778$2901 + assign { } { } + assign $1\core_terminate_o[0:0] 1'0 + sync always + sync init + update \core_terminate_o $1\core_terminate_o[0:0] + end + attribute \src "libresoc.v:37791.13-37791.27" + process $proc$libresoc.v:37791$2902 + assign { } { } + assign $1\counter[1:0] 2'00 + sync always + sync init + update \counter $1\counter[1:0] + end + attribute \src "libresoc.v:38921.7-38921.34" + process $proc$libresoc.v:38921$2903 + assign { } { } + assign $1\dp_CR_cr_a_branch0_1[0:0] 1'0 + sync always + sync init + update \dp_CR_cr_a_branch0_1 $1\dp_CR_cr_a_branch0_1[0:0] + end + attribute \src "libresoc.v:38925.7-38925.30" + process $proc$libresoc.v:38925$2904 + assign { } { } + assign $1\dp_CR_cr_a_cr0_0[0:0] 1'0 + sync always + sync init + update \dp_CR_cr_a_cr0_0 $1\dp_CR_cr_a_cr0_0[0:0] + end + attribute \src "libresoc.v:38929.7-38929.30" + process $proc$libresoc.v:38929$2905 + assign { } { } + assign $1\dp_CR_cr_b_cr0_0[0:0] 1'0 + sync always + sync init + update \dp_CR_cr_b_cr0_0 $1\dp_CR_cr_b_cr0_0[0:0] + end + attribute \src "libresoc.v:38933.7-38933.30" + process $proc$libresoc.v:38933$2906 + assign { } { } + assign $1\dp_CR_cr_c_cr0_0[0:0] 1'0 + sync always + sync init + update \dp_CR_cr_c_cr0_0 $1\dp_CR_cr_c_cr0_0[0:0] + end + attribute \src "libresoc.v:38937.7-38937.33" + process $proc$libresoc.v:38937$2907 + assign { } { } + assign $1\dp_CR_full_cr_cr0_0[0:0] 1'0 + sync always + sync init + update \dp_CR_full_cr_cr0_0 $1\dp_CR_full_cr_cr0_0[0:0] + end + attribute \src "libresoc.v:38941.7-38941.37" + process $proc$libresoc.v:38941$2908 + assign { } { } + assign $1\dp_FAST_fast1_branch0_0[0:0] 1'0 + sync always + sync init + update \dp_FAST_fast1_branch0_0 $1\dp_FAST_fast1_branch0_0[0:0] + end + attribute \src "libresoc.v:38945.7-38945.34" + process $proc$libresoc.v:38945$2909 + assign { } { } + assign $1\dp_FAST_fast1_spr0_2[0:0] 1'0 + sync always + sync init + update \dp_FAST_fast1_spr0_2 $1\dp_FAST_fast1_spr0_2[0:0] + end + attribute \src "libresoc.v:38949.7-38949.35" + process $proc$libresoc.v:38949$2910 + assign { } { } + assign $1\dp_FAST_fast1_trap0_1[0:0] 1'0 + sync always + sync init + update \dp_FAST_fast1_trap0_1 $1\dp_FAST_fast1_trap0_1[0:0] + end + attribute \src "libresoc.v:38953.7-38953.37" + process $proc$libresoc.v:38953$2911 + assign { } { } + assign $1\dp_FAST_fast2_branch0_0[0:0] 1'0 + sync always + sync init + update \dp_FAST_fast2_branch0_0 $1\dp_FAST_fast2_branch0_0[0:0] + end + attribute \src "libresoc.v:38957.7-38957.35" + process $proc$libresoc.v:38957$2912 + assign { } { } + assign $1\dp_FAST_fast2_trap0_1[0:0] 1'0 + sync always + sync init + update \dp_FAST_fast2_trap0_1 $1\dp_FAST_fast2_trap0_1[0:0] + end + attribute \src "libresoc.v:38961.7-38961.30" + process $proc$libresoc.v:38961$2913 + assign { } { } + assign $1\dp_INT_ra_alu0_0[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_alu0_0 $1\dp_INT_ra_alu0_0[0:0] + end + attribute \src "libresoc.v:38965.7-38965.29" + process $proc$libresoc.v:38965$2914 + assign { } { } + assign $1\dp_INT_ra_cr0_1[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_cr0_1 $1\dp_INT_ra_cr0_1[0:0] + end + attribute \src "libresoc.v:38969.7-38969.30" + process $proc$libresoc.v:38969$2915 + assign { } { } + assign $1\dp_INT_ra_div0_5[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_div0_5 $1\dp_INT_ra_div0_5[0:0] + end + attribute \src "libresoc.v:38973.7-38973.31" + process $proc$libresoc.v:38973$2916 + assign { } { } + assign $1\dp_INT_ra_ldst0_8[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_ldst0_8 $1\dp_INT_ra_ldst0_8[0:0] + end + attribute \src "libresoc.v:38977.7-38977.34" + process $proc$libresoc.v:38977$2917 + assign { } { } + assign $1\dp_INT_ra_logical0_3[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_logical0_3 $1\dp_INT_ra_logical0_3[0:0] + end + attribute \src "libresoc.v:38981.7-38981.30" + process $proc$libresoc.v:38981$2918 + assign { } { } + assign $1\dp_INT_ra_mul0_6[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_mul0_6 $1\dp_INT_ra_mul0_6[0:0] + end + attribute \src "libresoc.v:38985.7-38985.35" + process $proc$libresoc.v:38985$2919 + assign { } { } + assign $1\dp_INT_ra_shiftrot0_7[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_shiftrot0_7 $1\dp_INT_ra_shiftrot0_7[0:0] + end + attribute \src "libresoc.v:38989.7-38989.30" + process $proc$libresoc.v:38989$2920 + assign { } { } + assign $1\dp_INT_ra_spr0_4[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_spr0_4 $1\dp_INT_ra_spr0_4[0:0] + end + attribute \src "libresoc.v:38993.7-38993.31" + process $proc$libresoc.v:38993$2921 + assign { } { } + assign $1\dp_INT_ra_trap0_2[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_trap0_2 $1\dp_INT_ra_trap0_2[0:0] + end + attribute \src "libresoc.v:38997.7-38997.30" + process $proc$libresoc.v:38997$2922 + assign { } { } + assign $1\dp_INT_rb_alu0_0[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_alu0_0 $1\dp_INT_rb_alu0_0[0:0] + end + attribute \src "libresoc.v:39001.7-39001.29" + process $proc$libresoc.v:39001$2923 + assign { } { } + assign $1\dp_INT_rb_cr0_1[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_cr0_1 $1\dp_INT_rb_cr0_1[0:0] + end + attribute \src "libresoc.v:39005.7-39005.30" + process $proc$libresoc.v:39005$2924 + assign { } { } + assign $1\dp_INT_rb_div0_4[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_div0_4 $1\dp_INT_rb_div0_4[0:0] + end + attribute \src "libresoc.v:39009.7-39009.31" + process $proc$libresoc.v:39009$2925 + assign { } { } + assign $1\dp_INT_rb_ldst0_7[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_ldst0_7 $1\dp_INT_rb_ldst0_7[0:0] + end + attribute \src "libresoc.v:39013.7-39013.34" + process $proc$libresoc.v:39013$2926 + assign { } { } + assign $1\dp_INT_rb_logical0_3[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_logical0_3 $1\dp_INT_rb_logical0_3[0:0] + end + attribute \src "libresoc.v:39017.7-39017.30" + process $proc$libresoc.v:39017$2927 + assign { } { } + assign $1\dp_INT_rb_mul0_5[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_mul0_5 $1\dp_INT_rb_mul0_5[0:0] + end + attribute \src "libresoc.v:39021.7-39021.35" + process $proc$libresoc.v:39021$2928 + assign { } { } + assign $1\dp_INT_rb_shiftrot0_6[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_shiftrot0_6 $1\dp_INT_rb_shiftrot0_6[0:0] + end + attribute \src "libresoc.v:39025.7-39025.31" + process $proc$libresoc.v:39025$2929 + assign { } { } + assign $1\dp_INT_rb_trap0_2[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_trap0_2 $1\dp_INT_rb_trap0_2[0:0] + end + attribute \src "libresoc.v:39029.7-39029.31" + process $proc$libresoc.v:39029$2930 + assign { } { } + assign $1\dp_INT_rc_ldst0_1[0:0] 1'0 + sync always + sync init + update \dp_INT_rc_ldst0_1 $1\dp_INT_rc_ldst0_1[0:0] + end + attribute \src "libresoc.v:39033.7-39033.35" + process $proc$libresoc.v:39033$2931 + assign { } { } + assign $1\dp_INT_rc_shiftrot0_0[0:0] 1'0 + sync always + sync init + update \dp_INT_rc_shiftrot0_0 $1\dp_INT_rc_shiftrot0_0[0:0] + end + attribute \src "libresoc.v:39037.7-39037.32" + process $proc$libresoc.v:39037$2932 + assign { } { } + assign $1\dp_SPR_spr1_spr0_0[0:0] 1'0 + sync always + sync init + update \dp_SPR_spr1_spr0_0 $1\dp_SPR_spr1_spr0_0[0:0] + end + attribute \src "libresoc.v:39041.7-39041.34" + process $proc$libresoc.v:39041$2933 + assign { } { } + assign $1\dp_XER_xer_ca_alu0_0[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_ca_alu0_0 $1\dp_XER_xer_ca_alu0_0[0:0] + end + attribute \src "libresoc.v:39045.7-39045.39" + process $proc$libresoc.v:39045$2934 + assign { } { } + assign $1\dp_XER_xer_ca_shiftrot0_2[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_ca_shiftrot0_2 $1\dp_XER_xer_ca_shiftrot0_2[0:0] + end + attribute \src "libresoc.v:39049.7-39049.34" + process $proc$libresoc.v:39049$2935 + assign { } { } + assign $1\dp_XER_xer_ca_spr0_1[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_ca_spr0_1 $1\dp_XER_xer_ca_spr0_1[0:0] + end + attribute \src "libresoc.v:39053.7-39053.34" + process $proc$libresoc.v:39053$2936 + assign { } { } + assign $1\dp_XER_xer_ov_spr0_0[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_ov_spr0_0 $1\dp_XER_xer_ov_spr0_0[0:0] + end + attribute \src "libresoc.v:39057.7-39057.34" + process $proc$libresoc.v:39057$2937 + assign { } { } + assign $1\dp_XER_xer_so_alu0_0[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_so_alu0_0 $1\dp_XER_xer_so_alu0_0[0:0] + end + attribute \src "libresoc.v:39061.7-39061.34" + process $proc$libresoc.v:39061$2938 + assign { } { } + assign $1\dp_XER_xer_so_div0_3[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_so_div0_3 $1\dp_XER_xer_so_div0_3[0:0] + end + attribute \src "libresoc.v:39065.7-39065.38" + process $proc$libresoc.v:39065$2939 + assign { } { } + assign $1\dp_XER_xer_so_logical0_1[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_so_logical0_1 $1\dp_XER_xer_so_logical0_1[0:0] + end + attribute \src "libresoc.v:39069.7-39069.34" + process $proc$libresoc.v:39069$2940 + assign { } { } + assign $1\dp_XER_xer_so_mul0_4[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_so_mul0_4 $1\dp_XER_xer_so_mul0_4[0:0] + end + attribute \src "libresoc.v:39073.7-39073.39" + process $proc$libresoc.v:39073$2941 + assign { } { } + assign $1\dp_XER_xer_so_shiftrot0_5[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_so_shiftrot0_5 $1\dp_XER_xer_so_shiftrot0_5[0:0] + end + attribute \src "libresoc.v:39077.7-39077.34" + process $proc$libresoc.v:39077$2942 + assign { } { } + assign $1\dp_XER_xer_so_spr0_2[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_so_spr0_2 $1\dp_XER_xer_so_spr0_2[0:0] + end + attribute \src "libresoc.v:41154.7-41154.25" + process $proc$libresoc.v:41154$2943 + assign { } { } + assign $1\wr_pick_dly[0:0] 1'0 + sync always + sync init + update \wr_pick_dly $1\wr_pick_dly[0:0] + end + attribute \src "libresoc.v:41156.7-41156.32" + process $proc$libresoc.v:41156$2944 + assign { } { } + assign $0\wr_pick_dly$1000[0:0]$2945 1'0 + sync always + sync init + update \wr_pick_dly$1000 $0\wr_pick_dly$1000[0:0]$2945 + end + attribute \src "libresoc.v:41160.7-41160.32" + process $proc$libresoc.v:41160$2946 + assign { } { } + assign $0\wr_pick_dly$1021[0:0]$2947 1'0 + sync always + sync init + update \wr_pick_dly$1021 $0\wr_pick_dly$1021[0:0]$2947 + end + attribute \src "libresoc.v:41164.7-41164.32" + process $proc$libresoc.v:41164$2948 + assign { } { } + assign $0\wr_pick_dly$1039[0:0]$2949 1'0 + sync always + sync init + update \wr_pick_dly$1039 $0\wr_pick_dly$1039[0:0]$2949 + end + attribute \src "libresoc.v:41168.7-41168.32" + process $proc$libresoc.v:41168$2950 + assign { } { } + assign $0\wr_pick_dly$1061[0:0]$2951 1'0 + sync always + sync init + update \wr_pick_dly$1061 $0\wr_pick_dly$1061[0:0]$2951 + end + attribute \src "libresoc.v:41172.7-41172.32" + process $proc$libresoc.v:41172$2952 + assign { } { } + assign $0\wr_pick_dly$1081[0:0]$2953 1'0 + sync always + sync init + update \wr_pick_dly$1081 $0\wr_pick_dly$1081[0:0]$2953 + end + attribute \src "libresoc.v:41176.7-41176.32" + process $proc$libresoc.v:41176$2954 + assign { } { } + assign $0\wr_pick_dly$1101[0:0]$2955 1'0 + sync always + sync init + update \wr_pick_dly$1101 $0\wr_pick_dly$1101[0:0]$2955 + end + attribute \src "libresoc.v:41180.7-41180.32" + process $proc$libresoc.v:41180$2956 + assign { } { } + assign $0\wr_pick_dly$1120[0:0]$2957 1'0 + sync always + sync init + update \wr_pick_dly$1120 $0\wr_pick_dly$1120[0:0]$2957 + end + attribute \src "libresoc.v:41184.7-41184.32" + process $proc$libresoc.v:41184$2958 + assign { } { } + assign $0\wr_pick_dly$1138[0:0]$2959 1'0 + sync always + sync init + update \wr_pick_dly$1138 $0\wr_pick_dly$1138[0:0]$2959 + end + attribute \src "libresoc.v:41188.7-41188.32" + process $proc$libresoc.v:41188$2960 + assign { } { } + assign $0\wr_pick_dly$1211[0:0]$2961 1'0 + sync always + sync init + update \wr_pick_dly$1211 $0\wr_pick_dly$1211[0:0]$2961 + end + attribute \src "libresoc.v:41192.7-41192.32" + process $proc$libresoc.v:41192$2962 + assign { } { } + assign $0\wr_pick_dly$1239[0:0]$2963 1'0 + sync always + sync init + update \wr_pick_dly$1239 $0\wr_pick_dly$1239[0:0]$2963 + end + attribute \src "libresoc.v:41196.7-41196.32" + process $proc$libresoc.v:41196$2964 + assign { } { } + assign $0\wr_pick_dly$1259[0:0]$2965 1'0 + sync always + sync init + update \wr_pick_dly$1259 $0\wr_pick_dly$1259[0:0]$2965 + end + attribute \src "libresoc.v:41200.7-41200.32" + process $proc$libresoc.v:41200$2966 + assign { } { } + assign $0\wr_pick_dly$1279[0:0]$2967 1'0 + sync always + sync init + update \wr_pick_dly$1279 $0\wr_pick_dly$1279[0:0]$2967 + end + attribute \src "libresoc.v:41204.7-41204.32" + process $proc$libresoc.v:41204$2968 + assign { } { } + assign $0\wr_pick_dly$1299[0:0]$2969 1'0 + sync always + sync init + update \wr_pick_dly$1299 $0\wr_pick_dly$1299[0:0]$2969 + end + attribute \src "libresoc.v:41208.7-41208.32" + process $proc$libresoc.v:41208$2970 + assign { } { } + assign $0\wr_pick_dly$1319[0:0]$2971 1'0 + sync always + sync init + update \wr_pick_dly$1319 $0\wr_pick_dly$1319[0:0]$2971 + end + attribute \src "libresoc.v:41212.7-41212.32" + process $proc$libresoc.v:41212$2972 + assign { } { } + assign $0\wr_pick_dly$1339[0:0]$2973 1'0 + sync always + sync init + update \wr_pick_dly$1339 $0\wr_pick_dly$1339[0:0]$2973 + end + attribute \src "libresoc.v:41216.7-41216.32" + process $proc$libresoc.v:41216$2974 + assign { } { } + assign $0\wr_pick_dly$1386[0:0]$2975 1'0 + sync always + sync init + update \wr_pick_dly$1386 $0\wr_pick_dly$1386[0:0]$2975 + end + attribute \src "libresoc.v:41220.7-41220.32" + process $proc$libresoc.v:41220$2976 + assign { } { } + assign $0\wr_pick_dly$1402[0:0]$2977 1'0 + sync always + sync init + update \wr_pick_dly$1402 $0\wr_pick_dly$1402[0:0]$2977 + end + attribute \src "libresoc.v:41224.7-41224.32" + process $proc$libresoc.v:41224$2978 + assign { } { } + assign $0\wr_pick_dly$1418[0:0]$2979 1'0 + sync always + sync init + update \wr_pick_dly$1418 $0\wr_pick_dly$1418[0:0]$2979 + end + attribute \src "libresoc.v:41228.7-41228.32" + process $proc$libresoc.v:41228$2980 + assign { } { } + assign $0\wr_pick_dly$1452[0:0]$2981 1'0 + sync always + sync init + update \wr_pick_dly$1452 $0\wr_pick_dly$1452[0:0]$2981 + end + attribute \src "libresoc.v:41232.7-41232.32" + process $proc$libresoc.v:41232$2982 + assign { } { } + assign $0\wr_pick_dly$1468[0:0]$2983 1'0 + sync always + sync init + update \wr_pick_dly$1468 $0\wr_pick_dly$1468[0:0]$2983 + end + attribute \src "libresoc.v:41236.7-41236.32" + process $proc$libresoc.v:41236$2984 + assign { } { } + assign $0\wr_pick_dly$1484[0:0]$2985 1'0 + sync always + sync init + update \wr_pick_dly$1484 $0\wr_pick_dly$1484[0:0]$2985 + end + attribute \src "libresoc.v:41240.7-41240.32" + process $proc$libresoc.v:41240$2986 + assign { } { } + assign $0\wr_pick_dly$1500[0:0]$2987 1'0 + sync always + sync init + update \wr_pick_dly$1500 $0\wr_pick_dly$1500[0:0]$2987 + end + attribute \src "libresoc.v:41244.7-41244.32" + process $proc$libresoc.v:41244$2988 + assign { } { } + assign $0\wr_pick_dly$1536[0:0]$2989 1'0 + sync always + sync init + update \wr_pick_dly$1536 $0\wr_pick_dly$1536[0:0]$2989 + end + attribute \src "libresoc.v:41248.7-41248.32" + process $proc$libresoc.v:41248$2990 + assign { } { } + assign $0\wr_pick_dly$1552[0:0]$2991 1'0 + sync always + sync init + update \wr_pick_dly$1552 $0\wr_pick_dly$1552[0:0]$2991 + end + attribute \src "libresoc.v:41252.7-41252.32" + process $proc$libresoc.v:41252$2992 + assign { } { } + assign $0\wr_pick_dly$1568[0:0]$2993 1'0 + sync always + sync init + update \wr_pick_dly$1568 $0\wr_pick_dly$1568[0:0]$2993 + end + attribute \src "libresoc.v:41256.7-41256.32" + process $proc$libresoc.v:41256$2994 + assign { } { } + assign $0\wr_pick_dly$1584[0:0]$2995 1'0 + sync always + sync init + update \wr_pick_dly$1584 $0\wr_pick_dly$1584[0:0]$2995 + end + attribute \src "libresoc.v:41260.7-41260.32" + process $proc$libresoc.v:41260$2996 + assign { } { } + assign $0\wr_pick_dly$1626[0:0]$2997 1'0 + sync always + sync init + update \wr_pick_dly$1626 $0\wr_pick_dly$1626[0:0]$2997 + end + attribute \src "libresoc.v:41264.7-41264.32" + process $proc$libresoc.v:41264$2998 + assign { } { } + assign $0\wr_pick_dly$1645[0:0]$2999 1'0 + sync always + sync init + update \wr_pick_dly$1645 $0\wr_pick_dly$1645[0:0]$2999 + end + attribute \src "libresoc.v:41268.7-41268.32" + process $proc$libresoc.v:41268$3000 + assign { } { } + assign $0\wr_pick_dly$1661[0:0]$3001 1'0 + sync always + sync init + update \wr_pick_dly$1661 $0\wr_pick_dly$1661[0:0]$3001 + end + attribute \src "libresoc.v:41272.7-41272.32" + process $proc$libresoc.v:41272$3002 + assign { } { } + assign $0\wr_pick_dly$1677[0:0]$3003 1'0 + sync always + sync init + update \wr_pick_dly$1677 $0\wr_pick_dly$1677[0:0]$3003 + end + attribute \src "libresoc.v:41276.7-41276.32" + process $proc$libresoc.v:41276$3004 + assign { } { } + assign $0\wr_pick_dly$1693[0:0]$3005 1'0 + sync always + sync init + update \wr_pick_dly$1693 $0\wr_pick_dly$1693[0:0]$3005 + end + attribute \src "libresoc.v:41280.7-41280.32" + process $proc$libresoc.v:41280$3006 + assign { } { } + assign $0\wr_pick_dly$1737[0:0]$3007 1'0 + sync always + sync init + update \wr_pick_dly$1737 $0\wr_pick_dly$1737[0:0]$3007 + end + attribute \src "libresoc.v:41284.7-41284.32" + process $proc$libresoc.v:41284$3008 + assign { } { } + assign $0\wr_pick_dly$1753[0:0]$3009 1'0 + sync always + sync init + update \wr_pick_dly$1753 $0\wr_pick_dly$1753[0:0]$3009 + end + attribute \src "libresoc.v:41288.7-41288.32" + process $proc$libresoc.v:41288$3010 + assign { } { } + assign $0\wr_pick_dly$1777[0:0]$3011 1'0 + sync always + sync init + update \wr_pick_dly$1777 $0\wr_pick_dly$1777[0:0]$3011 + end + attribute \src "libresoc.v:41292.7-41292.32" + process $proc$libresoc.v:41292$3012 + assign { } { } + assign $0\wr_pick_dly$1797[0:0]$3013 1'0 + sync always + sync init + update \wr_pick_dly$1797 $0\wr_pick_dly$1797[0:0]$3013 + end + attribute \src "libresoc.v:41296.7-41296.31" + process $proc$libresoc.v:41296$3014 + assign { } { } + assign $0\wr_pick_dly$981[0:0]$3015 1'0 + sync always + sync init + update \wr_pick_dly$981 $0\wr_pick_dly$981[0:0]$3015 + end + attribute \src "libresoc.v:42258.3-42259.51" + process $proc$libresoc.v:42258$2238 + assign { } { } + assign $0\wr_pick_dly$1797[0:0]$2239 \wr_pick_dly$1797$next + sync posedge \coresync_clk + update \wr_pick_dly$1797 $0\wr_pick_dly$1797[0:0]$2239 + end + attribute \src "libresoc.v:42260.3-42261.51" + process $proc$libresoc.v:42260$2240 + assign { } { } + assign $0\wr_pick_dly$1777[0:0]$2241 \wr_pick_dly$1777$next + sync posedge \coresync_clk + update \wr_pick_dly$1777 $0\wr_pick_dly$1777[0:0]$2241 + end + attribute \src "libresoc.v:42262.3-42263.51" + process $proc$libresoc.v:42262$2242 + assign { } { } + assign $0\wr_pick_dly$1753[0:0]$2243 \wr_pick_dly$1753$next + sync posedge \coresync_clk + update \wr_pick_dly$1753 $0\wr_pick_dly$1753[0:0]$2243 + end + attribute \src "libresoc.v:42264.3-42265.51" + process $proc$libresoc.v:42264$2244 + assign { } { } + assign $0\wr_pick_dly$1737[0:0]$2245 \wr_pick_dly$1737$next + sync posedge \coresync_clk + update \wr_pick_dly$1737 $0\wr_pick_dly$1737[0:0]$2245 + end + attribute \src "libresoc.v:42266.3-42267.51" + process $proc$libresoc.v:42266$2246 + assign { } { } + assign $0\wr_pick_dly$1693[0:0]$2247 \wr_pick_dly$1693$next + sync posedge \coresync_clk + update \wr_pick_dly$1693 $0\wr_pick_dly$1693[0:0]$2247 + end + attribute \src "libresoc.v:42268.3-42269.51" + process $proc$libresoc.v:42268$2248 + assign { } { } + assign $0\wr_pick_dly$1677[0:0]$2249 \wr_pick_dly$1677$next + sync posedge \coresync_clk + update \wr_pick_dly$1677 $0\wr_pick_dly$1677[0:0]$2249 + end + attribute \src "libresoc.v:42270.3-42271.51" + process $proc$libresoc.v:42270$2250 + assign { } { } + assign $0\wr_pick_dly$1661[0:0]$2251 \wr_pick_dly$1661$next + sync posedge \coresync_clk + update \wr_pick_dly$1661 $0\wr_pick_dly$1661[0:0]$2251 + end + attribute \src "libresoc.v:42272.3-42273.51" + process $proc$libresoc.v:42272$2252 + assign { } { } + assign $0\wr_pick_dly$1645[0:0]$2253 \wr_pick_dly$1645$next + sync posedge \coresync_clk + update \wr_pick_dly$1645 $0\wr_pick_dly$1645[0:0]$2253 + end + attribute \src "libresoc.v:42274.3-42275.51" + process $proc$libresoc.v:42274$2254 + assign { } { } + assign $0\wr_pick_dly$1626[0:0]$2255 \wr_pick_dly$1626$next + sync posedge \coresync_clk + update \wr_pick_dly$1626 $0\wr_pick_dly$1626[0:0]$2255 + end + attribute \src "libresoc.v:42276.3-42277.51" + process $proc$libresoc.v:42276$2256 + assign { } { } + assign $0\wr_pick_dly$1584[0:0]$2257 \wr_pick_dly$1584$next + sync posedge \coresync_clk + update \wr_pick_dly$1584 $0\wr_pick_dly$1584[0:0]$2257 + end + attribute \src "libresoc.v:42278.3-42279.51" + process $proc$libresoc.v:42278$2258 + assign { } { } + assign $0\wr_pick_dly$1568[0:0]$2259 \wr_pick_dly$1568$next + sync posedge \coresync_clk + update \wr_pick_dly$1568 $0\wr_pick_dly$1568[0:0]$2259 + end + attribute \src "libresoc.v:42280.3-42281.51" + process $proc$libresoc.v:42280$2260 + assign { } { } + assign $0\wr_pick_dly$1552[0:0]$2261 \wr_pick_dly$1552$next + sync posedge \coresync_clk + update \wr_pick_dly$1552 $0\wr_pick_dly$1552[0:0]$2261 + end + attribute \src "libresoc.v:42282.3-42283.51" + process $proc$libresoc.v:42282$2262 + assign { } { } + assign $0\wr_pick_dly$1536[0:0]$2263 \wr_pick_dly$1536$next + sync posedge \coresync_clk + update \wr_pick_dly$1536 $0\wr_pick_dly$1536[0:0]$2263 + end + attribute \src "libresoc.v:42284.3-42285.51" + process $proc$libresoc.v:42284$2264 + assign { } { } + assign $0\wr_pick_dly$1500[0:0]$2265 \wr_pick_dly$1500$next + sync posedge \coresync_clk + update \wr_pick_dly$1500 $0\wr_pick_dly$1500[0:0]$2265 + end + attribute \src "libresoc.v:42286.3-42287.51" + process $proc$libresoc.v:42286$2266 + assign { } { } + assign $0\wr_pick_dly$1484[0:0]$2267 \wr_pick_dly$1484$next + sync posedge \coresync_clk + update \wr_pick_dly$1484 $0\wr_pick_dly$1484[0:0]$2267 + end + attribute \src "libresoc.v:42288.3-42289.51" + process $proc$libresoc.v:42288$2268 + assign { } { } + assign $0\wr_pick_dly$1468[0:0]$2269 \wr_pick_dly$1468$next + sync posedge \coresync_clk + update \wr_pick_dly$1468 $0\wr_pick_dly$1468[0:0]$2269 + end + attribute \src "libresoc.v:42290.3-42291.51" + process $proc$libresoc.v:42290$2270 + assign { } { } + assign $0\wr_pick_dly$1452[0:0]$2271 \wr_pick_dly$1452$next + sync posedge \coresync_clk + update \wr_pick_dly$1452 $0\wr_pick_dly$1452[0:0]$2271 + end + attribute \src "libresoc.v:42292.3-42293.51" + process $proc$libresoc.v:42292$2272 + assign { } { } + assign $0\wr_pick_dly$1418[0:0]$2273 \wr_pick_dly$1418$next + sync posedge \coresync_clk + update \wr_pick_dly$1418 $0\wr_pick_dly$1418[0:0]$2273 + end + attribute \src "libresoc.v:42294.3-42295.51" + process $proc$libresoc.v:42294$2274 + assign { } { } + assign $0\wr_pick_dly$1402[0:0]$2275 \wr_pick_dly$1402$next + sync posedge \coresync_clk + update \wr_pick_dly$1402 $0\wr_pick_dly$1402[0:0]$2275 + end + attribute \src "libresoc.v:42296.3-42297.51" + process $proc$libresoc.v:42296$2276 + assign { } { } + assign $0\wr_pick_dly$1386[0:0]$2277 \wr_pick_dly$1386$next + sync posedge \coresync_clk + update \wr_pick_dly$1386 $0\wr_pick_dly$1386[0:0]$2277 + end + attribute \src "libresoc.v:42298.3-42299.51" + process $proc$libresoc.v:42298$2278 + assign { } { } + assign $0\wr_pick_dly$1339[0:0]$2279 \wr_pick_dly$1339$next + sync posedge \coresync_clk + update \wr_pick_dly$1339 $0\wr_pick_dly$1339[0:0]$2279 + end + attribute \src "libresoc.v:42300.3-42301.51" + process $proc$libresoc.v:42300$2280 + assign { } { } + assign $0\wr_pick_dly$1319[0:0]$2281 \wr_pick_dly$1319$next + sync posedge \coresync_clk + update \wr_pick_dly$1319 $0\wr_pick_dly$1319[0:0]$2281 + end + attribute \src "libresoc.v:42302.3-42303.51" + process $proc$libresoc.v:42302$2282 + assign { } { } + assign $0\wr_pick_dly$1299[0:0]$2283 \wr_pick_dly$1299$next + sync posedge \coresync_clk + update \wr_pick_dly$1299 $0\wr_pick_dly$1299[0:0]$2283 + end + attribute \src "libresoc.v:42304.3-42305.51" + process $proc$libresoc.v:42304$2284 + assign { } { } + assign $0\wr_pick_dly$1279[0:0]$2285 \wr_pick_dly$1279$next + sync posedge \coresync_clk + update \wr_pick_dly$1279 $0\wr_pick_dly$1279[0:0]$2285 + end + attribute \src "libresoc.v:42306.3-42307.51" + process $proc$libresoc.v:42306$2286 + assign { } { } + assign $0\wr_pick_dly$1259[0:0]$2287 \wr_pick_dly$1259$next + sync posedge \coresync_clk + update \wr_pick_dly$1259 $0\wr_pick_dly$1259[0:0]$2287 + end + attribute \src "libresoc.v:42308.3-42309.51" + process $proc$libresoc.v:42308$2288 + assign { } { } + assign $0\wr_pick_dly$1239[0:0]$2289 \wr_pick_dly$1239$next + sync posedge \coresync_clk + update \wr_pick_dly$1239 $0\wr_pick_dly$1239[0:0]$2289 + end + attribute \src "libresoc.v:42310.3-42311.51" + process $proc$libresoc.v:42310$2290 + assign { } { } + assign $0\wr_pick_dly$1211[0:0]$2291 \wr_pick_dly$1211$next + sync posedge \coresync_clk + update \wr_pick_dly$1211 $0\wr_pick_dly$1211[0:0]$2291 + end + attribute \src "libresoc.v:42312.3-42313.51" + process $proc$libresoc.v:42312$2292 + assign { } { } + assign $0\wr_pick_dly$1138[0:0]$2293 \wr_pick_dly$1138$next + sync posedge \coresync_clk + update \wr_pick_dly$1138 $0\wr_pick_dly$1138[0:0]$2293 + end + attribute \src "libresoc.v:42314.3-42315.51" + process $proc$libresoc.v:42314$2294 + assign { } { } + assign $0\wr_pick_dly$1120[0:0]$2295 \wr_pick_dly$1120$next + sync posedge \coresync_clk + update \wr_pick_dly$1120 $0\wr_pick_dly$1120[0:0]$2295 + end + attribute \src "libresoc.v:42316.3-42317.51" + process $proc$libresoc.v:42316$2296 + assign { } { } + assign $0\wr_pick_dly$1101[0:0]$2297 \wr_pick_dly$1101$next + sync posedge \coresync_clk + update \wr_pick_dly$1101 $0\wr_pick_dly$1101[0:0]$2297 + end + attribute \src "libresoc.v:42318.3-42319.51" + process $proc$libresoc.v:42318$2298 + assign { } { } + assign $0\wr_pick_dly$1081[0:0]$2299 \wr_pick_dly$1081$next + sync posedge \coresync_clk + update \wr_pick_dly$1081 $0\wr_pick_dly$1081[0:0]$2299 + end + attribute \src "libresoc.v:42320.3-42321.51" + process $proc$libresoc.v:42320$2300 + assign { } { } + assign $0\wr_pick_dly$1061[0:0]$2301 \wr_pick_dly$1061$next + sync posedge \coresync_clk + update \wr_pick_dly$1061 $0\wr_pick_dly$1061[0:0]$2301 + end + attribute \src "libresoc.v:42322.3-42323.51" + process $proc$libresoc.v:42322$2302 + assign { } { } + assign $0\wr_pick_dly$1039[0:0]$2303 \wr_pick_dly$1039$next + sync posedge \coresync_clk + update \wr_pick_dly$1039 $0\wr_pick_dly$1039[0:0]$2303 + end + attribute \src "libresoc.v:42324.3-42325.51" + process $proc$libresoc.v:42324$2304 + assign { } { } + assign $0\wr_pick_dly$1021[0:0]$2305 \wr_pick_dly$1021$next + sync posedge \coresync_clk + update \wr_pick_dly$1021 $0\wr_pick_dly$1021[0:0]$2305 + end + attribute \src "libresoc.v:42326.3-42327.51" + process $proc$libresoc.v:42326$2306 + assign { } { } + assign $0\wr_pick_dly$1000[0:0]$2307 \wr_pick_dly$1000$next + sync posedge \coresync_clk + update \wr_pick_dly$1000 $0\wr_pick_dly$1000[0:0]$2307 + end + attribute \src "libresoc.v:42328.3-42329.49" + process $proc$libresoc.v:42328$2308 + assign { } { } + assign $0\wr_pick_dly$981[0:0]$2309 \wr_pick_dly$981$next + sync posedge \coresync_clk + update \wr_pick_dly$981 $0\wr_pick_dly$981[0:0]$2309 + end + attribute \src "libresoc.v:42330.3-42331.39" + process $proc$libresoc.v:42330$2310 + assign { } { } + assign $0\wr_pick_dly[0:0] \wr_pick_dly$next + sync posedge \coresync_clk + update \wr_pick_dly $0\wr_pick_dly[0:0] + end + attribute \src "libresoc.v:42332.3-42333.53" + process $proc$libresoc.v:42332$2311 + assign { } { } + assign $0\dp_SPR_spr1_spr0_0[0:0] \dp_SPR_spr1_spr0_0$next + sync posedge \coresync_clk + update \dp_SPR_spr1_spr0_0 $0\dp_SPR_spr1_spr0_0[0:0] + end + attribute \src "libresoc.v:42334.3-42335.59" + process $proc$libresoc.v:42334$2312 + assign { } { } + assign $0\dp_FAST_fast2_trap0_1[0:0] \dp_FAST_fast2_trap0_1$next + sync posedge \coresync_clk + update \dp_FAST_fast2_trap0_1 $0\dp_FAST_fast2_trap0_1[0:0] + end + attribute \src "libresoc.v:42336.3-42337.63" + process $proc$libresoc.v:42336$2313 + assign { } { } + assign $0\dp_FAST_fast2_branch0_0[0:0] \dp_FAST_fast2_branch0_0$next + sync posedge \coresync_clk + update \dp_FAST_fast2_branch0_0 $0\dp_FAST_fast2_branch0_0[0:0] + end + attribute \src "libresoc.v:42338.3-42339.57" + process $proc$libresoc.v:42338$2314 + assign { } { } + assign $0\dp_FAST_fast1_spr0_2[0:0] \dp_FAST_fast1_spr0_2$next + sync posedge \coresync_clk + update \dp_FAST_fast1_spr0_2 $0\dp_FAST_fast1_spr0_2[0:0] + end + attribute \src "libresoc.v:42340.3-42341.59" + process $proc$libresoc.v:42340$2315 + assign { } { } + assign $0\dp_FAST_fast1_trap0_1[0:0] \dp_FAST_fast1_trap0_1$next + sync posedge \coresync_clk + update \dp_FAST_fast1_trap0_1 $0\dp_FAST_fast1_trap0_1[0:0] + end + attribute \src "libresoc.v:42342.3-42343.63" + process $proc$libresoc.v:42342$2316 + assign { } { } + assign $0\dp_FAST_fast1_branch0_0[0:0] \dp_FAST_fast1_branch0_0$next + sync posedge \coresync_clk + update \dp_FAST_fast1_branch0_0 $0\dp_FAST_fast1_branch0_0[0:0] + end + attribute \src "libresoc.v:42344.3-42345.49" + process $proc$libresoc.v:42344$2317 + assign { } { } + assign $0\dp_CR_cr_c_cr0_0[0:0] \dp_CR_cr_c_cr0_0$next + sync posedge \coresync_clk + update \dp_CR_cr_c_cr0_0 $0\dp_CR_cr_c_cr0_0[0:0] + end + attribute \src "libresoc.v:42346.3-42347.49" + process $proc$libresoc.v:42346$2318 + assign { } { } + assign $0\dp_CR_cr_b_cr0_0[0:0] \dp_CR_cr_b_cr0_0$next + sync posedge \coresync_clk + update \dp_CR_cr_b_cr0_0 $0\dp_CR_cr_b_cr0_0[0:0] + end + attribute \src "libresoc.v:42348.3-42349.57" + process $proc$libresoc.v:42348$2319 + assign { } { } + assign $0\dp_CR_cr_a_branch0_1[0:0] \dp_CR_cr_a_branch0_1$next + sync posedge \coresync_clk + update \dp_CR_cr_a_branch0_1 $0\dp_CR_cr_a_branch0_1[0:0] + end + attribute \src "libresoc.v:42350.3-42351.49" + process $proc$libresoc.v:42350$2320 + assign { } { } + assign $0\dp_CR_cr_a_cr0_0[0:0] \dp_CR_cr_a_cr0_0$next + sync posedge \coresync_clk + update \dp_CR_cr_a_cr0_0 $0\dp_CR_cr_a_cr0_0[0:0] + end + attribute \src "libresoc.v:42352.3-42353.55" + process $proc$libresoc.v:42352$2321 + assign { } { } + assign $0\dp_CR_full_cr_cr0_0[0:0] \dp_CR_full_cr_cr0_0$next + sync posedge \coresync_clk + update \dp_CR_full_cr_cr0_0 $0\dp_CR_full_cr_cr0_0[0:0] + end + attribute \src "libresoc.v:42354.3-42355.57" + process $proc$libresoc.v:42354$2322 + assign { } { } + assign $0\dp_XER_xer_ov_spr0_0[0:0] \dp_XER_xer_ov_spr0_0$next + sync posedge \coresync_clk + update \dp_XER_xer_ov_spr0_0 $0\dp_XER_xer_ov_spr0_0[0:0] + end + attribute \src "libresoc.v:42356.3-42357.67" + process $proc$libresoc.v:42356$2323 + assign { } { } + assign $0\dp_XER_xer_ca_shiftrot0_2[0:0] \dp_XER_xer_ca_shiftrot0_2$next + sync posedge \coresync_clk + update \dp_XER_xer_ca_shiftrot0_2 $0\dp_XER_xer_ca_shiftrot0_2[0:0] + end + attribute \src "libresoc.v:42358.3-42359.57" + process $proc$libresoc.v:42358$2324 + assign { } { } + assign $0\dp_XER_xer_ca_spr0_1[0:0] \dp_XER_xer_ca_spr0_1$next + sync posedge \coresync_clk + update \dp_XER_xer_ca_spr0_1 $0\dp_XER_xer_ca_spr0_1[0:0] + end + attribute \src "libresoc.v:42360.3-42361.57" + process $proc$libresoc.v:42360$2325 + assign { } { } + assign $0\dp_XER_xer_ca_alu0_0[0:0] \dp_XER_xer_ca_alu0_0$next + sync posedge \coresync_clk + update \dp_XER_xer_ca_alu0_0 $0\dp_XER_xer_ca_alu0_0[0:0] + end + attribute \src "libresoc.v:42362.3-42363.67" + process $proc$libresoc.v:42362$2326 + assign { } { } + assign $0\dp_XER_xer_so_shiftrot0_5[0:0] \dp_XER_xer_so_shiftrot0_5$next + sync posedge \coresync_clk + update \dp_XER_xer_so_shiftrot0_5 $0\dp_XER_xer_so_shiftrot0_5[0:0] + end + attribute \src "libresoc.v:42364.3-42365.57" + process $proc$libresoc.v:42364$2327 + assign { } { } + assign $0\dp_XER_xer_so_mul0_4[0:0] \dp_XER_xer_so_mul0_4$next + sync posedge \coresync_clk + update \dp_XER_xer_so_mul0_4 $0\dp_XER_xer_so_mul0_4[0:0] + end + attribute \src "libresoc.v:42366.3-42367.57" + process $proc$libresoc.v:42366$2328 + assign { } { } + assign $0\dp_XER_xer_so_div0_3[0:0] \dp_XER_xer_so_div0_3$next + sync posedge \coresync_clk + update \dp_XER_xer_so_div0_3 $0\dp_XER_xer_so_div0_3[0:0] + end + attribute \src "libresoc.v:42368.3-42369.57" + process $proc$libresoc.v:42368$2329 + assign { } { } + assign $0\dp_XER_xer_so_spr0_2[0:0] \dp_XER_xer_so_spr0_2$next + sync posedge \coresync_clk + update \dp_XER_xer_so_spr0_2 $0\dp_XER_xer_so_spr0_2[0:0] + end + attribute \src "libresoc.v:42370.3-42371.65" + process $proc$libresoc.v:42370$2330 + assign { } { } + assign $0\dp_XER_xer_so_logical0_1[0:0] \dp_XER_xer_so_logical0_1$next + sync posedge \coresync_clk + update \dp_XER_xer_so_logical0_1 $0\dp_XER_xer_so_logical0_1[0:0] + end + attribute \src "libresoc.v:42372.3-42373.57" + process $proc$libresoc.v:42372$2331 + assign { } { } + assign $0\dp_XER_xer_so_alu0_0[0:0] \dp_XER_xer_so_alu0_0$next + sync posedge \coresync_clk + update \dp_XER_xer_so_alu0_0 $0\dp_XER_xer_so_alu0_0[0:0] + end + attribute \src "libresoc.v:42374.3-42375.51" + process $proc$libresoc.v:42374$2332 + assign { } { } + assign $0\dp_INT_rc_ldst0_1[0:0] \dp_INT_rc_ldst0_1$next + sync posedge \coresync_clk + update \dp_INT_rc_ldst0_1 $0\dp_INT_rc_ldst0_1[0:0] + end + attribute \src "libresoc.v:42376.3-42377.59" + process $proc$libresoc.v:42376$2333 + assign { } { } + assign $0\dp_INT_rc_shiftrot0_0[0:0] \dp_INT_rc_shiftrot0_0$next + sync posedge \coresync_clk + update \dp_INT_rc_shiftrot0_0 $0\dp_INT_rc_shiftrot0_0[0:0] + end + attribute \src "libresoc.v:42378.3-42379.51" + process $proc$libresoc.v:42378$2334 + assign { } { } + assign $0\dp_INT_rb_ldst0_7[0:0] \dp_INT_rb_ldst0_7$next + sync posedge \coresync_clk + update \dp_INT_rb_ldst0_7 $0\dp_INT_rb_ldst0_7[0:0] + end + attribute \src "libresoc.v:42380.3-42381.59" + process $proc$libresoc.v:42380$2335 + assign { } { } + assign $0\dp_INT_rb_shiftrot0_6[0:0] \dp_INT_rb_shiftrot0_6$next + sync posedge \coresync_clk + update \dp_INT_rb_shiftrot0_6 $0\dp_INT_rb_shiftrot0_6[0:0] + end + attribute \src "libresoc.v:42382.3-42383.49" + process $proc$libresoc.v:42382$2336 + assign { } { } + assign $0\dp_INT_rb_mul0_5[0:0] \dp_INT_rb_mul0_5$next + sync posedge \coresync_clk + update \dp_INT_rb_mul0_5 $0\dp_INT_rb_mul0_5[0:0] + end + attribute \src "libresoc.v:42384.3-42385.49" + process $proc$libresoc.v:42384$2337 + assign { } { } + assign $0\dp_INT_rb_div0_4[0:0] \dp_INT_rb_div0_4$next + sync posedge \coresync_clk + update \dp_INT_rb_div0_4 $0\dp_INT_rb_div0_4[0:0] + end + attribute \src "libresoc.v:42386.3-42387.57" + process $proc$libresoc.v:42386$2338 + assign { } { } + assign $0\dp_INT_rb_logical0_3[0:0] \dp_INT_rb_logical0_3$next + sync posedge \coresync_clk + update \dp_INT_rb_logical0_3 $0\dp_INT_rb_logical0_3[0:0] + end + attribute \src "libresoc.v:42388.3-42389.51" + process $proc$libresoc.v:42388$2339 + assign { } { } + assign $0\dp_INT_rb_trap0_2[0:0] \dp_INT_rb_trap0_2$next + sync posedge \coresync_clk + update \dp_INT_rb_trap0_2 $0\dp_INT_rb_trap0_2[0:0] + end + attribute \src "libresoc.v:42390.3-42391.47" + process $proc$libresoc.v:42390$2340 + assign { } { } + assign $0\dp_INT_rb_cr0_1[0:0] \dp_INT_rb_cr0_1$next + sync posedge \coresync_clk + update \dp_INT_rb_cr0_1 $0\dp_INT_rb_cr0_1[0:0] + end + attribute \src "libresoc.v:42392.3-42393.49" + process $proc$libresoc.v:42392$2341 + assign { } { } + assign $0\dp_INT_rb_alu0_0[0:0] \dp_INT_rb_alu0_0$next + sync posedge \coresync_clk + update \dp_INT_rb_alu0_0 $0\dp_INT_rb_alu0_0[0:0] + end + attribute \src "libresoc.v:42394.3-42395.51" + process $proc$libresoc.v:42394$2342 + assign { } { } + assign $0\dp_INT_ra_ldst0_8[0:0] \dp_INT_ra_ldst0_8$next + sync posedge \coresync_clk + update \dp_INT_ra_ldst0_8 $0\dp_INT_ra_ldst0_8[0:0] + end + attribute \src "libresoc.v:42396.3-42397.59" + process $proc$libresoc.v:42396$2343 + assign { } { } + assign $0\dp_INT_ra_shiftrot0_7[0:0] \dp_INT_ra_shiftrot0_7$next + sync posedge \coresync_clk + update \dp_INT_ra_shiftrot0_7 $0\dp_INT_ra_shiftrot0_7[0:0] + end + attribute \src "libresoc.v:42398.3-42399.49" + process $proc$libresoc.v:42398$2344 + assign { } { } + assign $0\dp_INT_ra_mul0_6[0:0] \dp_INT_ra_mul0_6$next + sync posedge \coresync_clk + update \dp_INT_ra_mul0_6 $0\dp_INT_ra_mul0_6[0:0] + end + attribute \src "libresoc.v:42400.3-42401.49" + process $proc$libresoc.v:42400$2345 + assign { } { } + assign $0\dp_INT_ra_div0_5[0:0] \dp_INT_ra_div0_5$next + sync posedge \coresync_clk + update \dp_INT_ra_div0_5 $0\dp_INT_ra_div0_5[0:0] + end + attribute \src "libresoc.v:42402.3-42403.49" + process $proc$libresoc.v:42402$2346 + assign { } { } + assign $0\dp_INT_ra_spr0_4[0:0] \dp_INT_ra_spr0_4$next + sync posedge \coresync_clk + update \dp_INT_ra_spr0_4 $0\dp_INT_ra_spr0_4[0:0] + end + attribute \src "libresoc.v:42404.3-42405.57" + process $proc$libresoc.v:42404$2347 + assign { } { } + assign $0\dp_INT_ra_logical0_3[0:0] \dp_INT_ra_logical0_3$next + sync posedge \coresync_clk + update \dp_INT_ra_logical0_3 $0\dp_INT_ra_logical0_3[0:0] + end + attribute \src "libresoc.v:42406.3-42407.51" + process $proc$libresoc.v:42406$2348 + assign { } { } + assign $0\dp_INT_ra_trap0_2[0:0] \dp_INT_ra_trap0_2$next + sync posedge \coresync_clk + update \dp_INT_ra_trap0_2 $0\dp_INT_ra_trap0_2[0:0] + end + attribute \src "libresoc.v:42408.3-42409.47" + process $proc$libresoc.v:42408$2349 + assign { } { } + assign $0\dp_INT_ra_cr0_1[0:0] \dp_INT_ra_cr0_1$next + sync posedge \coresync_clk + update \dp_INT_ra_cr0_1 $0\dp_INT_ra_cr0_1[0:0] + end + attribute \src "libresoc.v:42410.3-42411.49" + process $proc$libresoc.v:42410$2350 + assign { } { } + assign $0\dp_INT_ra_alu0_0[0:0] \dp_INT_ra_alu0_0$next + sync posedge \coresync_clk + update \dp_INT_ra_alu0_0 $0\dp_INT_ra_alu0_0[0:0] + end + attribute \src "libresoc.v:42412.3-42413.49" + process $proc$libresoc.v:42412$2351 + assign { } { } + assign $0\core_terminate_o[0:0] \core_terminate_o$next + sync posedge \coresync_clk + update \core_terminate_o $0\core_terminate_o[0:0] + end + attribute \src "libresoc.v:42414.3-42415.31" + process $proc$libresoc.v:42414$2352 + assign { } { } + assign $0\counter[1:0] \counter$next + sync posedge \coresync_clk + update \counter $0\counter[1:0] + end + attribute \src "libresoc.v:43145.3-43173.6" + process $proc$libresoc.v:43145$2353 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_spr0__insn[31:0] $1\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "libresoc.v:43146.5-43146.29" + switch \initial + attribute \src "libresoc.v:43146.9-43146.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_spr0__insn[31:0] $2\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_spr0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_spr0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_spr0__insn[31:0] $3\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_spr0__insn[31:0] \dec_SPR_SPR__insn + case + assign $3\fus_oper_i_alu_spr0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_spr0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_spr0__insn $0\fus_oper_i_alu_spr0__insn[31:0] + end + attribute \src "libresoc.v:43174.3-43202.6" + process $proc$libresoc.v:43174$2354 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_spr0__is_32bit[0:0] $1\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "libresoc.v:43175.5-43175.29" + switch \initial + attribute \src "libresoc.v:43175.9-43175.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_spr0__is_32bit[0:0] $2\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] $3\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_spr0__is_32bit[0:0] \dec_SPR_SPR__is_32bit + case + assign $3\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_spr0__is_32bit $0\fus_oper_i_alu_spr0__is_32bit[0:0] + end + attribute \src "libresoc.v:43203.3-43231.6" + process $proc$libresoc.v:43203$2355 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$23[0:0]$2356 $1\fus_cu_issue_i$23[0:0]$2357 + attribute \src "libresoc.v:43204.5-43204.29" + switch \initial + attribute \src "libresoc.v:43204.9-43204.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$23[0:0]$2357 $2\fus_cu_issue_i$23[0:0]$2358 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$23[0:0]$2358 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$23[0:0]$2358 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$23[0:0]$2358 $3\fus_cu_issue_i$23[0:0]$2359 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$23[0:0]$2359 \issue_i + case + assign $3\fus_cu_issue_i$23[0:0]$2359 1'0 + end + end + case + assign $1\fus_cu_issue_i$23[0:0]$2357 1'0 + end + sync always + update \fus_cu_issue_i$23 $0\fus_cu_issue_i$23[0:0]$2356 + end + attribute \src "libresoc.v:43232.3-43260.6" + process $proc$libresoc.v:43232$2360 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$25[5:0]$2361 $1\fus_cu_rdmaskn_i$25[5:0]$2362 + attribute \src "libresoc.v:43233.5-43233.29" + switch \initial + attribute \src "libresoc.v:43233.9-43233.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$25[5:0]$2362 $2\fus_cu_rdmaskn_i$25[5:0]$2363 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$25[5:0]$2363 6'000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$25[5:0]$2363 6'000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$25[5:0]$2363 $3\fus_cu_rdmaskn_i$25[5:0]$2364 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$25[5:0]$2364 \$263 + case + assign $3\fus_cu_rdmaskn_i$25[5:0]$2364 6'000000 + end + end + case + assign $1\fus_cu_rdmaskn_i$25[5:0]$2362 6'000000 + end + sync always + update \fus_cu_rdmaskn_i$25 $0\fus_cu_rdmaskn_i$25[5:0]$2361 + end + attribute \src "libresoc.v:43261.3-43289.6" + process $proc$libresoc.v:43261$2365 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__insn_type[6:0] $1\fus_oper_i_alu_div0__insn_type[6:0] + attribute \src "libresoc.v:43262.5-43262.29" + switch \initial + attribute \src "libresoc.v:43262.9-43262.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__insn_type[6:0] $2\fus_oper_i_alu_div0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__insn_type[6:0] $3\fus_oper_i_alu_div0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__insn_type[6:0] \dec_DIV_DIV__insn_type + case + assign $3\fus_oper_i_alu_div0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_div0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_div0__insn_type $0\fus_oper_i_alu_div0__insn_type[6:0] + end + attribute \src "libresoc.v:43290.3-43318.6" + process $proc$libresoc.v:43290$2366 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__fn_unit[11:0] $1\fus_oper_i_alu_div0__fn_unit[11:0] + attribute \src "libresoc.v:43291.5-43291.29" + switch \initial + attribute \src "libresoc.v:43291.9-43291.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__fn_unit[11:0] $2\fus_oper_i_alu_div0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__fn_unit[11:0] $3\fus_oper_i_alu_div0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__fn_unit[11:0] \dec_DIV_DIV__fn_unit + case + assign $3\fus_oper_i_alu_div0__fn_unit[11:0] 12'000000000000 + end + end + case + assign $1\fus_oper_i_alu_div0__fn_unit[11:0] 12'000000000000 + end + sync always + update \fus_oper_i_alu_div0__fn_unit $0\fus_oper_i_alu_div0__fn_unit[11:0] + end + attribute \src "libresoc.v:43319.3-43348.6" + process $proc$libresoc.v:43319$2367 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__imm_data__data[63:0] $1\fus_oper_i_alu_div0__imm_data__data[63:0] + assign $0\fus_oper_i_alu_div0__imm_data__ok[0:0] $1\fus_oper_i_alu_div0__imm_data__ok[0:0] + attribute \src "libresoc.v:43320.5-43320.29" + switch \initial + attribute \src "libresoc.v:43320.9-43320.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_div0__imm_data__data[63:0] $2\fus_oper_i_alu_div0__imm_data__data[63:0] + assign $1\fus_oper_i_alu_div0__imm_data__ok[0:0] $2\fus_oper_i_alu_div0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_div0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_div0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_div0__imm_data__data[63:0] $3\fus_oper_i_alu_div0__imm_data__data[63:0] + assign $2\fus_oper_i_alu_div0__imm_data__ok[0:0] $3\fus_oper_i_alu_div0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_div0__imm_data__ok[0:0] $3\fus_oper_i_alu_div0__imm_data__data[63:0] } { \dec_DIV_DIV__imm_data__ok \dec_DIV_DIV__imm_data__data } + case + assign $3\fus_oper_i_alu_div0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\fus_oper_i_alu_div0__imm_data__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_alu_div0__imm_data__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__imm_data__data $0\fus_oper_i_alu_div0__imm_data__data[63:0] + update \fus_oper_i_alu_div0__imm_data__ok $0\fus_oper_i_alu_div0__imm_data__ok[0:0] + end + attribute \src "libresoc.v:43349.3-43378.6" + process $proc$libresoc.v:43349$2368 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__rc__ok[0:0] $1\fus_oper_i_alu_div0__rc__ok[0:0] + assign $0\fus_oper_i_alu_div0__rc__rc[0:0] $1\fus_oper_i_alu_div0__rc__rc[0:0] + attribute \src "libresoc.v:43350.5-43350.29" + switch \initial + attribute \src "libresoc.v:43350.9-43350.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_div0__rc__ok[0:0] $2\fus_oper_i_alu_div0__rc__ok[0:0] + assign $1\fus_oper_i_alu_div0__rc__rc[0:0] $2\fus_oper_i_alu_div0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_div0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_div0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_div0__rc__ok[0:0] $3\fus_oper_i_alu_div0__rc__ok[0:0] + assign $2\fus_oper_i_alu_div0__rc__rc[0:0] $3\fus_oper_i_alu_div0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_div0__rc__ok[0:0] $3\fus_oper_i_alu_div0__rc__rc[0:0] } { \dec_DIV_DIV__rc__ok \dec_DIV_DIV__rc__rc } + case + assign $3\fus_oper_i_alu_div0__rc__ok[0:0] 1'0 + assign $3\fus_oper_i_alu_div0__rc__rc[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__rc__ok[0:0] 1'0 + assign $1\fus_oper_i_alu_div0__rc__rc[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__rc__ok $0\fus_oper_i_alu_div0__rc__ok[0:0] + update \fus_oper_i_alu_div0__rc__rc $0\fus_oper_i_alu_div0__rc__rc[0:0] + end + attribute \src "libresoc.v:43379.3-43408.6" + process $proc$libresoc.v:43379$2369 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__oe__oe[0:0] $1\fus_oper_i_alu_div0__oe__oe[0:0] + assign $0\fus_oper_i_alu_div0__oe__ok[0:0] $1\fus_oper_i_alu_div0__oe__ok[0:0] + attribute \src "libresoc.v:43380.5-43380.29" + switch \initial + attribute \src "libresoc.v:43380.9-43380.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_div0__oe__oe[0:0] $2\fus_oper_i_alu_div0__oe__oe[0:0] + assign $1\fus_oper_i_alu_div0__oe__ok[0:0] $2\fus_oper_i_alu_div0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_div0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_div0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_div0__oe__oe[0:0] $3\fus_oper_i_alu_div0__oe__oe[0:0] + assign $2\fus_oper_i_alu_div0__oe__ok[0:0] $3\fus_oper_i_alu_div0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_div0__oe__ok[0:0] $3\fus_oper_i_alu_div0__oe__oe[0:0] } { \dec_DIV_DIV__oe__ok \dec_DIV_DIV__oe__oe } + case + assign $3\fus_oper_i_alu_div0__oe__oe[0:0] 1'0 + assign $3\fus_oper_i_alu_div0__oe__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__oe__oe[0:0] 1'0 + assign $1\fus_oper_i_alu_div0__oe__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__oe__oe $0\fus_oper_i_alu_div0__oe__oe[0:0] + update \fus_oper_i_alu_div0__oe__ok $0\fus_oper_i_alu_div0__oe__ok[0:0] + end + attribute \src "libresoc.v:43409.3-43437.6" + process $proc$libresoc.v:43409$2370 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__invert_in[0:0] $1\fus_oper_i_alu_div0__invert_in[0:0] + attribute \src "libresoc.v:43410.5-43410.29" + switch \initial + attribute \src "libresoc.v:43410.9-43410.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__invert_in[0:0] $2\fus_oper_i_alu_div0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__invert_in[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__invert_in[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__invert_in[0:0] $3\fus_oper_i_alu_div0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__invert_in[0:0] \dec_DIV_DIV__invert_in + case + assign $3\fus_oper_i_alu_div0__invert_in[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__invert_in[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__invert_in $0\fus_oper_i_alu_div0__invert_in[0:0] + end + attribute \src "libresoc.v:43438.3-43466.6" + process $proc$libresoc.v:43438$2371 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__zero_a[0:0] $1\fus_oper_i_alu_div0__zero_a[0:0] + attribute \src "libresoc.v:43439.5-43439.29" + switch \initial + attribute \src "libresoc.v:43439.9-43439.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__zero_a[0:0] $2\fus_oper_i_alu_div0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__zero_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__zero_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__zero_a[0:0] $3\fus_oper_i_alu_div0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__zero_a[0:0] \dec_DIV_DIV__zero_a + case + assign $3\fus_oper_i_alu_div0__zero_a[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__zero_a[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__zero_a $0\fus_oper_i_alu_div0__zero_a[0:0] + end + attribute \src "libresoc.v:43467.3-43495.6" + process $proc$libresoc.v:43467$2372 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__input_carry[1:0] $1\fus_oper_i_alu_div0__input_carry[1:0] + attribute \src "libresoc.v:43468.5-43468.29" + switch \initial + attribute \src "libresoc.v:43468.9-43468.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__input_carry[1:0] $2\fus_oper_i_alu_div0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__input_carry[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__input_carry[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__input_carry[1:0] $3\fus_oper_i_alu_div0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__input_carry[1:0] \dec_DIV_DIV__input_carry + case + assign $3\fus_oper_i_alu_div0__input_carry[1:0] 2'00 + end + end + case + assign $1\fus_oper_i_alu_div0__input_carry[1:0] 2'00 + end + sync always + update \fus_oper_i_alu_div0__input_carry $0\fus_oper_i_alu_div0__input_carry[1:0] + end + attribute \src "libresoc.v:43496.3-43524.6" + process $proc$libresoc.v:43496$2373 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__invert_out[0:0] $1\fus_oper_i_alu_div0__invert_out[0:0] + attribute \src "libresoc.v:43497.5-43497.29" + switch \initial + attribute \src "libresoc.v:43497.9-43497.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__invert_out[0:0] $2\fus_oper_i_alu_div0__invert_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__invert_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__invert_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__invert_out[0:0] $3\fus_oper_i_alu_div0__invert_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__invert_out[0:0] \dec_DIV_DIV__invert_out + case + assign $3\fus_oper_i_alu_div0__invert_out[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__invert_out[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__invert_out $0\fus_oper_i_alu_div0__invert_out[0:0] + end + attribute \src "libresoc.v:43525.3-43553.6" + process $proc$libresoc.v:43525$2374 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__write_cr0[0:0] $1\fus_oper_i_alu_div0__write_cr0[0:0] + attribute \src "libresoc.v:43526.5-43526.29" + switch \initial + attribute \src "libresoc.v:43526.9-43526.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__write_cr0[0:0] $2\fus_oper_i_alu_div0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__write_cr0[0:0] $3\fus_oper_i_alu_div0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__write_cr0[0:0] \dec_DIV_DIV__write_cr0 + case + assign $3\fus_oper_i_alu_div0__write_cr0[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__write_cr0[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__write_cr0 $0\fus_oper_i_alu_div0__write_cr0[0:0] + end + attribute \src "libresoc.v:43554.3-43582.6" + process $proc$libresoc.v:43554$2375 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__output_carry[0:0] $1\fus_oper_i_alu_div0__output_carry[0:0] + attribute \src "libresoc.v:43555.5-43555.29" + switch \initial + attribute \src "libresoc.v:43555.9-43555.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__output_carry[0:0] $2\fus_oper_i_alu_div0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__output_carry[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__output_carry[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__output_carry[0:0] $3\fus_oper_i_alu_div0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__output_carry[0:0] \dec_DIV_DIV__output_carry + case + assign $3\fus_oper_i_alu_div0__output_carry[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__output_carry[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__output_carry $0\fus_oper_i_alu_div0__output_carry[0:0] + end + attribute \src "libresoc.v:43583.3-43611.6" + process $proc$libresoc.v:43583$2376 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__is_32bit[0:0] $1\fus_oper_i_alu_div0__is_32bit[0:0] + attribute \src "libresoc.v:43584.5-43584.29" + switch \initial + attribute \src "libresoc.v:43584.9-43584.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__is_32bit[0:0] $2\fus_oper_i_alu_div0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__is_32bit[0:0] $3\fus_oper_i_alu_div0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__is_32bit[0:0] \dec_DIV_DIV__is_32bit + case + assign $3\fus_oper_i_alu_div0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__is_32bit $0\fus_oper_i_alu_div0__is_32bit[0:0] + end + attribute \src "libresoc.v:43612.3-43640.6" + process $proc$libresoc.v:43612$2377 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__is_signed[0:0] $1\fus_oper_i_alu_div0__is_signed[0:0] + attribute \src "libresoc.v:43613.5-43613.29" + switch \initial + attribute \src "libresoc.v:43613.9-43613.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__is_signed[0:0] $2\fus_oper_i_alu_div0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__is_signed[0:0] $3\fus_oper_i_alu_div0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__is_signed[0:0] \dec_DIV_DIV__is_signed + case + assign $3\fus_oper_i_alu_div0__is_signed[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__is_signed[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__is_signed $0\fus_oper_i_alu_div0__is_signed[0:0] + end + attribute \src "libresoc.v:43641.3-43669.6" + process $proc$libresoc.v:43641$2378 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__data_len[3:0] $1\fus_oper_i_alu_div0__data_len[3:0] + attribute \src "libresoc.v:43642.5-43642.29" + switch \initial + attribute \src "libresoc.v:43642.9-43642.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__data_len[3:0] $2\fus_oper_i_alu_div0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__data_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__data_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__data_len[3:0] $3\fus_oper_i_alu_div0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__data_len[3:0] \dec_DIV_DIV__data_len + case + assign $3\fus_oper_i_alu_div0__data_len[3:0] 4'0000 + end + end + case + assign $1\fus_oper_i_alu_div0__data_len[3:0] 4'0000 + end + sync always + update \fus_oper_i_alu_div0__data_len $0\fus_oper_i_alu_div0__data_len[3:0] + end + attribute \src "libresoc.v:43670.3-43698.6" + process $proc$libresoc.v:43670$2379 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__insn[31:0] $1\fus_oper_i_alu_div0__insn[31:0] + attribute \src "libresoc.v:43671.5-43671.29" + switch \initial + attribute \src "libresoc.v:43671.9-43671.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__insn[31:0] $2\fus_oper_i_alu_div0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__insn[31:0] $3\fus_oper_i_alu_div0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__insn[31:0] \dec_DIV_DIV__insn + case + assign $3\fus_oper_i_alu_div0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_div0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_div0__insn $0\fus_oper_i_alu_div0__insn[31:0] + end + attribute \src "libresoc.v:43699.3-43727.6" + process $proc$libresoc.v:43699$2380 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$26[0:0]$2381 $1\fus_cu_issue_i$26[0:0]$2382 + attribute \src "libresoc.v:43700.5-43700.29" + switch \initial + attribute \src "libresoc.v:43700.9-43700.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$26[0:0]$2382 $2\fus_cu_issue_i$26[0:0]$2383 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$26[0:0]$2383 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$26[0:0]$2383 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$26[0:0]$2383 $3\fus_cu_issue_i$26[0:0]$2384 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$26[0:0]$2384 \issue_i + case + assign $3\fus_cu_issue_i$26[0:0]$2384 1'0 + end + end + case + assign $1\fus_cu_issue_i$26[0:0]$2382 1'0 + end + sync always + update \fus_cu_issue_i$26 $0\fus_cu_issue_i$26[0:0]$2381 + end + attribute \src "libresoc.v:43728.3-43756.6" + process $proc$libresoc.v:43728$2385 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$28[2:0]$2386 $1\fus_cu_rdmaskn_i$28[2:0]$2387 + attribute \src "libresoc.v:43729.5-43729.29" + switch \initial + attribute \src "libresoc.v:43729.9-43729.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$28[2:0]$2387 $2\fus_cu_rdmaskn_i$28[2:0]$2388 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$28[2:0]$2388 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$28[2:0]$2388 3'000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$28[2:0]$2388 $3\fus_cu_rdmaskn_i$28[2:0]$2389 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$28[2:0]$2389 \$293 + case + assign $3\fus_cu_rdmaskn_i$28[2:0]$2389 3'000 + end + end + case + assign $1\fus_cu_rdmaskn_i$28[2:0]$2387 3'000 + end + sync always + update \fus_cu_rdmaskn_i$28 $0\fus_cu_rdmaskn_i$28[2:0]$2386 + end + attribute \src "libresoc.v:43757.3-43785.6" + process $proc$libresoc.v:43757$2390 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__insn_type[6:0] $1\fus_oper_i_alu_mul0__insn_type[6:0] + attribute \src "libresoc.v:43758.5-43758.29" + switch \initial + attribute \src "libresoc.v:43758.9-43758.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_mul0__insn_type[6:0] $2\fus_oper_i_alu_mul0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_mul0__insn_type[6:0] $3\fus_oper_i_alu_mul0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_mul0__insn_type[6:0] \dec_MUL_MUL__insn_type + case + assign $3\fus_oper_i_alu_mul0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_mul0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_mul0__insn_type $0\fus_oper_i_alu_mul0__insn_type[6:0] + end + attribute \src "libresoc.v:43786.3-43814.6" + process $proc$libresoc.v:43786$2391 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__fn_unit[11:0] $1\fus_oper_i_alu_mul0__fn_unit[11:0] + attribute \src "libresoc.v:43787.5-43787.29" + switch \initial + attribute \src "libresoc.v:43787.9-43787.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_mul0__fn_unit[11:0] $2\fus_oper_i_alu_mul0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_mul0__fn_unit[11:0] $3\fus_oper_i_alu_mul0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_mul0__fn_unit[11:0] \dec_MUL_MUL__fn_unit + case + assign $3\fus_oper_i_alu_mul0__fn_unit[11:0] 12'000000000000 + end + end + case + assign $1\fus_oper_i_alu_mul0__fn_unit[11:0] 12'000000000000 + end + sync always + update \fus_oper_i_alu_mul0__fn_unit $0\fus_oper_i_alu_mul0__fn_unit[11:0] + end + attribute \src "libresoc.v:43815.3-43844.6" + process $proc$libresoc.v:43815$2392 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__imm_data__data[63:0] $1\fus_oper_i_alu_mul0__imm_data__data[63:0] + assign $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] + attribute \src "libresoc.v:43816.5-43816.29" + switch \initial + attribute \src "libresoc.v:43816.9-43816.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_mul0__imm_data__data[63:0] $2\fus_oper_i_alu_mul0__imm_data__data[63:0] + assign $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_mul0__imm_data__data[63:0] $3\fus_oper_i_alu_mul0__imm_data__data[63:0] + assign $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] $3\fus_oper_i_alu_mul0__imm_data__data[63:0] } { \dec_MUL_MUL__imm_data__ok \dec_MUL_MUL__imm_data__data } + case + assign $3\fus_oper_i_alu_mul0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_mul0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_mul0__imm_data__data $0\fus_oper_i_alu_mul0__imm_data__data[63:0] + update \fus_oper_i_alu_mul0__imm_data__ok $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] + end + attribute \src "libresoc.v:43845.3-43874.6" + process $proc$libresoc.v:43845$2393 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__rc__ok[0:0] $1\fus_oper_i_alu_mul0__rc__ok[0:0] + assign $0\fus_oper_i_alu_mul0__rc__rc[0:0] $1\fus_oper_i_alu_mul0__rc__rc[0:0] + attribute \src "libresoc.v:43846.5-43846.29" + switch \initial + attribute \src "libresoc.v:43846.9-43846.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_mul0__rc__ok[0:0] $2\fus_oper_i_alu_mul0__rc__ok[0:0] + assign $1\fus_oper_i_alu_mul0__rc__rc[0:0] $2\fus_oper_i_alu_mul0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_mul0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_mul0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_mul0__rc__ok[0:0] $3\fus_oper_i_alu_mul0__rc__ok[0:0] + assign $2\fus_oper_i_alu_mul0__rc__rc[0:0] $3\fus_oper_i_alu_mul0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_mul0__rc__ok[0:0] $3\fus_oper_i_alu_mul0__rc__rc[0:0] } { \dec_MUL_MUL__rc__ok \dec_MUL_MUL__rc__rc } + case + assign $3\fus_oper_i_alu_mul0__rc__ok[0:0] 1'0 + assign $3\fus_oper_i_alu_mul0__rc__rc[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_mul0__rc__ok[0:0] 1'0 + assign $1\fus_oper_i_alu_mul0__rc__rc[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_mul0__rc__ok $0\fus_oper_i_alu_mul0__rc__ok[0:0] + update \fus_oper_i_alu_mul0__rc__rc $0\fus_oper_i_alu_mul0__rc__rc[0:0] + end + attribute \src "libresoc.v:43875.3-43904.6" + process $proc$libresoc.v:43875$2394 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__oe__oe[0:0] $1\fus_oper_i_alu_mul0__oe__oe[0:0] + assign $0\fus_oper_i_alu_mul0__oe__ok[0:0] $1\fus_oper_i_alu_mul0__oe__ok[0:0] + attribute \src "libresoc.v:43876.5-43876.29" + switch \initial + attribute \src "libresoc.v:43876.9-43876.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_mul0__oe__oe[0:0] $2\fus_oper_i_alu_mul0__oe__oe[0:0] + assign $1\fus_oper_i_alu_mul0__oe__ok[0:0] $2\fus_oper_i_alu_mul0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_mul0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_mul0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_mul0__oe__oe[0:0] $3\fus_oper_i_alu_mul0__oe__oe[0:0] + assign $2\fus_oper_i_alu_mul0__oe__ok[0:0] $3\fus_oper_i_alu_mul0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_mul0__oe__ok[0:0] $3\fus_oper_i_alu_mul0__oe__oe[0:0] } { \dec_MUL_MUL__oe__ok \dec_MUL_MUL__oe__oe } + case + assign $3\fus_oper_i_alu_mul0__oe__oe[0:0] 1'0 + assign $3\fus_oper_i_alu_mul0__oe__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_mul0__oe__oe[0:0] 1'0 + assign $1\fus_oper_i_alu_mul0__oe__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_mul0__oe__oe $0\fus_oper_i_alu_mul0__oe__oe[0:0] + update \fus_oper_i_alu_mul0__oe__ok $0\fus_oper_i_alu_mul0__oe__ok[0:0] + end + attribute \src "libresoc.v:43905.3-43933.6" + process $proc$libresoc.v:43905$2395 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__write_cr0[0:0] $1\fus_oper_i_alu_mul0__write_cr0[0:0] + attribute \src "libresoc.v:43906.5-43906.29" + switch \initial + attribute \src "libresoc.v:43906.9-43906.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_mul0__write_cr0[0:0] $2\fus_oper_i_alu_mul0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_mul0__write_cr0[0:0] $3\fus_oper_i_alu_mul0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_mul0__write_cr0[0:0] \dec_MUL_MUL__write_cr0 + case + assign $3\fus_oper_i_alu_mul0__write_cr0[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_mul0__write_cr0[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_mul0__write_cr0 $0\fus_oper_i_alu_mul0__write_cr0[0:0] + end + attribute \src "libresoc.v:43934.3-43962.6" + process $proc$libresoc.v:43934$2396 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__is_32bit[0:0] $1\fus_oper_i_alu_mul0__is_32bit[0:0] + attribute \src "libresoc.v:43935.5-43935.29" + switch \initial + attribute \src "libresoc.v:43935.9-43935.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_mul0__is_32bit[0:0] $2\fus_oper_i_alu_mul0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_mul0__is_32bit[0:0] $3\fus_oper_i_alu_mul0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_mul0__is_32bit[0:0] \dec_MUL_MUL__is_32bit + case + assign $3\fus_oper_i_alu_mul0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_mul0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_mul0__is_32bit $0\fus_oper_i_alu_mul0__is_32bit[0:0] + end + attribute \src "libresoc.v:43963.3-43991.6" + process $proc$libresoc.v:43963$2397 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__is_signed[0:0] $1\fus_oper_i_alu_mul0__is_signed[0:0] + attribute \src "libresoc.v:43964.5-43964.29" + switch \initial + attribute \src "libresoc.v:43964.9-43964.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_mul0__is_signed[0:0] $2\fus_oper_i_alu_mul0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_mul0__is_signed[0:0] $3\fus_oper_i_alu_mul0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_mul0__is_signed[0:0] \dec_MUL_MUL__is_signed + case + assign $3\fus_oper_i_alu_mul0__is_signed[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_mul0__is_signed[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_mul0__is_signed $0\fus_oper_i_alu_mul0__is_signed[0:0] + end + attribute \src "libresoc.v:43992.3-44020.6" + process $proc$libresoc.v:43992$2398 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__insn[31:0] $1\fus_oper_i_alu_mul0__insn[31:0] + attribute \src "libresoc.v:43993.5-43993.29" + switch \initial + attribute \src "libresoc.v:43993.9-43993.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_mul0__insn[31:0] $2\fus_oper_i_alu_mul0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_mul0__insn[31:0] $3\fus_oper_i_alu_mul0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_mul0__insn[31:0] \dec_MUL_MUL__insn + case + assign $3\fus_oper_i_alu_mul0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_mul0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_mul0__insn $0\fus_oper_i_alu_mul0__insn[31:0] + end + attribute \src "libresoc.v:44021.3-44049.6" + process $proc$libresoc.v:44021$2399 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$29[0:0]$2400 $1\fus_cu_issue_i$29[0:0]$2401 + attribute \src "libresoc.v:44022.5-44022.29" + switch \initial + attribute \src "libresoc.v:44022.9-44022.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$29[0:0]$2401 $2\fus_cu_issue_i$29[0:0]$2402 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$29[0:0]$2402 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$29[0:0]$2402 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$29[0:0]$2402 $3\fus_cu_issue_i$29[0:0]$2403 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$29[0:0]$2403 \issue_i + case + assign $3\fus_cu_issue_i$29[0:0]$2403 1'0 + end + end + case + assign $1\fus_cu_issue_i$29[0:0]$2401 1'0 + end + sync always + update \fus_cu_issue_i$29 $0\fus_cu_issue_i$29[0:0]$2400 + end + attribute \src "libresoc.v:44050.3-44078.6" + process $proc$libresoc.v:44050$2404 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$31[2:0]$2405 $1\fus_cu_rdmaskn_i$31[2:0]$2406 + attribute \src "libresoc.v:44051.5-44051.29" + switch \initial + attribute \src "libresoc.v:44051.9-44051.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$31[2:0]$2406 $2\fus_cu_rdmaskn_i$31[2:0]$2407 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$31[2:0]$2407 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$31[2:0]$2407 3'000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$31[2:0]$2407 $3\fus_cu_rdmaskn_i$31[2:0]$2408 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$31[2:0]$2408 \$307 + case + assign $3\fus_cu_rdmaskn_i$31[2:0]$2408 3'000 + end + end + case + assign $1\fus_cu_rdmaskn_i$31[2:0]$2406 3'000 + end + sync always + update \fus_cu_rdmaskn_i$31 $0\fus_cu_rdmaskn_i$31[2:0]$2405 + end + attribute \src "libresoc.v:44079.3-44107.6" + process $proc$libresoc.v:44079$2409 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] + attribute \src "libresoc.v:44080.5-44080.29" + switch \initial + attribute \src "libresoc.v:44080.9-44080.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] \dec_SHIFT_ROT_SHIFT_ROT__insn_type + case + assign $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_shift_rot0__insn_type $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] + end + attribute \src "libresoc.v:44108.3-44136.6" + process $proc$libresoc.v:44108$2410 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__fn_unit[11:0] $1\fus_oper_i_alu_shift_rot0__fn_unit[11:0] + attribute \src "libresoc.v:44109.5-44109.29" + switch \initial + attribute \src "libresoc.v:44109.9-44109.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__fn_unit[11:0] $2\fus_oper_i_alu_shift_rot0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__fn_unit[11:0] $3\fus_oper_i_alu_shift_rot0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__fn_unit[11:0] \dec_SHIFT_ROT_SHIFT_ROT__fn_unit + case + assign $3\fus_oper_i_alu_shift_rot0__fn_unit[11:0] 12'000000000000 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__fn_unit[11:0] 12'000000000000 + end + sync always + update \fus_oper_i_alu_shift_rot0__fn_unit $0\fus_oper_i_alu_shift_rot0__fn_unit[11:0] + end + attribute \src "libresoc.v:44137.3-44166.6" + process $proc$libresoc.v:44137$2411 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + assign $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + attribute \src "libresoc.v:44138.5-44138.29" + switch \initial + attribute \src "libresoc.v:44138.9-44138.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + assign $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + assign $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] } { \dec_SHIFT_ROT_SHIFT_ROT__imm_data__ok \dec_SHIFT_ROT_SHIFT_ROT__imm_data__data } + case + assign $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__imm_data__data $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + update \fus_oper_i_alu_shift_rot0__imm_data__ok $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + end + attribute \src "libresoc.v:44167.3-44196.6" + process $proc$libresoc.v:44167$2412 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + assign $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + attribute \src "libresoc.v:44168.5-44168.29" + switch \initial + attribute \src "libresoc.v:44168.9-44168.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + assign $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + assign $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] } { \dec_SHIFT_ROT_SHIFT_ROT__rc__ok \dec_SHIFT_ROT_SHIFT_ROT__rc__rc } + case + assign $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] 1'0 + assign $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] 1'0 + assign $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__rc__ok $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + update \fus_oper_i_alu_shift_rot0__rc__rc $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + end + attribute \src "libresoc.v:44197.3-44226.6" + process $proc$libresoc.v:44197$2413 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + assign $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + attribute \src "libresoc.v:44198.5-44198.29" + switch \initial + attribute \src "libresoc.v:44198.9-44198.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + assign $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + assign $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] } { \dec_SHIFT_ROT_SHIFT_ROT__oe__ok \dec_SHIFT_ROT_SHIFT_ROT__oe__oe } + case + assign $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] 1'0 + assign $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] 1'0 + assign $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__oe__oe $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + update \fus_oper_i_alu_shift_rot0__oe__ok $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + end + attribute \src "libresoc.v:44227.3-44255.6" + process $proc$libresoc.v:44227$2414 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + attribute \src "libresoc.v:44228.5-44228.29" + switch \initial + attribute \src "libresoc.v:44228.9-44228.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] \dec_SHIFT_ROT_SHIFT_ROT__write_cr0 + case + assign $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__write_cr0 $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + end + attribute \src "libresoc.v:44256.3-44284.6" + process $proc$libresoc.v:44256$2415 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__invert_in[0:0] $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] + attribute \src "libresoc.v:44257.5-44257.29" + switch \initial + attribute \src "libresoc.v:44257.9-44257.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] $3\fus_oper_i_alu_shift_rot0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__invert_in[0:0] \dec_SHIFT_ROT_SHIFT_ROT__invert_in + case + assign $3\fus_oper_i_alu_shift_rot0__invert_in[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__invert_in $0\fus_oper_i_alu_shift_rot0__invert_in[0:0] + end + attribute \src "libresoc.v:44285.3-44313.6" + process $proc$libresoc.v:44285$2416 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] + attribute \src "libresoc.v:44286.5-44286.29" + switch \initial + attribute \src "libresoc.v:44286.9-44286.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] \dec_SHIFT_ROT_SHIFT_ROT__input_carry + case + assign $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] 2'00 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] 2'00 + end + sync always + update \fus_oper_i_alu_shift_rot0__input_carry $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] + end + attribute \src "libresoc.v:44314.3-44342.6" + process $proc$libresoc.v:44314$2417 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] + attribute \src "libresoc.v:44315.5-44315.29" + switch \initial + attribute \src "libresoc.v:44315.9-44315.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] \dec_SHIFT_ROT_SHIFT_ROT__output_carry + case + assign $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__output_carry $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] + end + attribute \src "libresoc.v:44343.3-44371.6" + process $proc$libresoc.v:44343$2418 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] + attribute \src "libresoc.v:44344.5-44344.29" + switch \initial + attribute \src "libresoc.v:44344.9-44344.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] \dec_SHIFT_ROT_SHIFT_ROT__input_cr + case + assign $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__input_cr $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] + end + attribute \src "libresoc.v:44372.3-44400.6" + process $proc$libresoc.v:44372$2419 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] + attribute \src "libresoc.v:44373.5-44373.29" + switch \initial + attribute \src "libresoc.v:44373.9-44373.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] \dec_SHIFT_ROT_SHIFT_ROT__output_cr + case + assign $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__output_cr $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] + end + attribute \src "libresoc.v:44401.3-44429.6" + process $proc$libresoc.v:44401$2420 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + attribute \src "libresoc.v:44402.5-44402.29" + switch \initial + attribute \src "libresoc.v:44402.9-44402.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] \dec_SHIFT_ROT_SHIFT_ROT__is_32bit + case + assign $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__is_32bit $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + end + attribute \src "libresoc.v:44430.3-44458.6" + process $proc$libresoc.v:44430$2421 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] + attribute \src "libresoc.v:44431.5-44431.29" + switch \initial + attribute \src "libresoc.v:44431.9-44431.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] \dec_SHIFT_ROT_SHIFT_ROT__is_signed + case + assign $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__is_signed $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] + end + attribute \src "libresoc.v:44459.3-44487.6" + process $proc$libresoc.v:44459$2422 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__insn[31:0] $1\fus_oper_i_alu_shift_rot0__insn[31:0] + attribute \src "libresoc.v:44460.5-44460.29" + switch \initial + attribute \src "libresoc.v:44460.9-44460.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__insn[31:0] $2\fus_oper_i_alu_shift_rot0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__insn[31:0] $3\fus_oper_i_alu_shift_rot0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__insn[31:0] \dec_SHIFT_ROT_SHIFT_ROT__insn + case + assign $3\fus_oper_i_alu_shift_rot0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_shift_rot0__insn $0\fus_oper_i_alu_shift_rot0__insn[31:0] + end + attribute \src "libresoc.v:44488.3-44516.6" + process $proc$libresoc.v:44488$2423 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$32[0:0]$2424 $1\fus_cu_issue_i$32[0:0]$2425 + attribute \src "libresoc.v:44489.5-44489.29" + switch \initial + attribute \src "libresoc.v:44489.9-44489.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$32[0:0]$2425 $2\fus_cu_issue_i$32[0:0]$2426 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$32[0:0]$2426 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$32[0:0]$2426 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$32[0:0]$2426 $3\fus_cu_issue_i$32[0:0]$2427 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$32[0:0]$2427 \issue_i + case + assign $3\fus_cu_issue_i$32[0:0]$2427 1'0 + end + end + case + assign $1\fus_cu_issue_i$32[0:0]$2425 1'0 + end + sync always + update \fus_cu_issue_i$32 $0\fus_cu_issue_i$32[0:0]$2424 + end + attribute \src "libresoc.v:44517.3-44545.6" + process $proc$libresoc.v:44517$2428 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$34[4:0]$2429 $1\fus_cu_rdmaskn_i$34[4:0]$2430 + attribute \src "libresoc.v:44518.5-44518.29" + switch \initial + attribute \src "libresoc.v:44518.9-44518.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$34[4:0]$2430 $2\fus_cu_rdmaskn_i$34[4:0]$2431 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$34[4:0]$2431 5'00000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$34[4:0]$2431 5'00000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$34[4:0]$2431 $3\fus_cu_rdmaskn_i$34[4:0]$2432 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$34[4:0]$2432 \$321 + case + assign $3\fus_cu_rdmaskn_i$34[4:0]$2432 5'00000 + end + end + case + assign $1\fus_cu_rdmaskn_i$34[4:0]$2430 5'00000 + end + sync always + update \fus_cu_rdmaskn_i$34 $0\fus_cu_rdmaskn_i$34[4:0]$2429 + end + attribute \src "libresoc.v:44546.3-44574.6" + process $proc$libresoc.v:44546$2433 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__insn_type[6:0] $1\fus_oper_i_ldst_ldst0__insn_type[6:0] + attribute \src "libresoc.v:44547.5-44547.29" + switch \initial + attribute \src "libresoc.v:44547.9-44547.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__insn_type[6:0] $2\fus_oper_i_ldst_ldst0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__insn_type[6:0] $3\fus_oper_i_ldst_ldst0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__insn_type[6:0] \dec_LDST_LDST__insn_type + case + assign $3\fus_oper_i_ldst_ldst0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_ldst_ldst0__insn_type $0\fus_oper_i_ldst_ldst0__insn_type[6:0] + end + attribute \src "libresoc.v:44575.3-44603.6" + process $proc$libresoc.v:44575$2434 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__fn_unit[11:0] $1\fus_oper_i_ldst_ldst0__fn_unit[11:0] + attribute \src "libresoc.v:44576.5-44576.29" + switch \initial + attribute \src "libresoc.v:44576.9-44576.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__fn_unit[11:0] $2\fus_oper_i_ldst_ldst0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__fn_unit[11:0] $3\fus_oper_i_ldst_ldst0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__fn_unit[11:0] \dec_LDST_LDST__fn_unit + case + assign $3\fus_oper_i_ldst_ldst0__fn_unit[11:0] 12'000000000000 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__fn_unit[11:0] 12'000000000000 + end + sync always + update \fus_oper_i_ldst_ldst0__fn_unit $0\fus_oper_i_ldst_ldst0__fn_unit[11:0] + end + attribute \src "libresoc.v:44604.3-44633.6" + process $proc$libresoc.v:44604$2435 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + assign $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + attribute \src "libresoc.v:44605.5-44605.29" + switch \initial + attribute \src "libresoc.v:44605.9-44605.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + assign $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + assign $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] } { \dec_LDST_LDST__imm_data__ok \dec_LDST_LDST__imm_data__data } + case + assign $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__imm_data__data $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + update \fus_oper_i_ldst_ldst0__imm_data__ok $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + end + attribute \src "libresoc.v:44634.3-44662.6" + process $proc$libresoc.v:44634$2436 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__zero_a[0:0] $1\fus_oper_i_ldst_ldst0__zero_a[0:0] + attribute \src "libresoc.v:44635.5-44635.29" + switch \initial + attribute \src "libresoc.v:44635.9-44635.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__zero_a[0:0] $2\fus_oper_i_ldst_ldst0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__zero_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__zero_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__zero_a[0:0] $3\fus_oper_i_ldst_ldst0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__zero_a[0:0] \dec_LDST_LDST__zero_a + case + assign $3\fus_oper_i_ldst_ldst0__zero_a[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__zero_a[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__zero_a $0\fus_oper_i_ldst_ldst0__zero_a[0:0] + end + attribute \src "libresoc.v:44663.3-44692.6" + process $proc$libresoc.v:44663$2437 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] + assign $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] + attribute \src "libresoc.v:44664.5-44664.29" + switch \initial + attribute \src "libresoc.v:44664.9-44664.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] + assign $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] + assign $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] } { \dec_LDST_LDST__rc__ok \dec_LDST_LDST__rc__rc } + case + assign $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] 1'0 + assign $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] 1'0 + assign $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__rc__ok $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] + update \fus_oper_i_ldst_ldst0__rc__rc $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] + end + attribute \src "libresoc.v:44693.3-44722.6" + process $proc$libresoc.v:44693$2438 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] + assign $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] + attribute \src "libresoc.v:44694.5-44694.29" + switch \initial + attribute \src "libresoc.v:44694.9-44694.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] + assign $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] + assign $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] } { \dec_LDST_LDST__oe__ok \dec_LDST_LDST__oe__oe } + case + assign $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] 1'0 + assign $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] 1'0 + assign $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__oe__oe $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] + update \fus_oper_i_ldst_ldst0__oe__ok $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] + end + attribute \src "libresoc.v:44723.3-44751.6" + process $proc$libresoc.v:44723$2439 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] + attribute \src "libresoc.v:44724.5-44724.29" + switch \initial + attribute \src "libresoc.v:44724.9-44724.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] \dec_LDST_LDST__is_32bit + case + assign $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__is_32bit $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] + end + attribute \src "libresoc.v:44752.3-44780.6" + process $proc$libresoc.v:44752$2440 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__is_signed[0:0] $1\fus_oper_i_ldst_ldst0__is_signed[0:0] + attribute \src "libresoc.v:44753.5-44753.29" + switch \initial + attribute \src "libresoc.v:44753.9-44753.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__is_signed[0:0] $2\fus_oper_i_ldst_ldst0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__is_signed[0:0] $3\fus_oper_i_ldst_ldst0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__is_signed[0:0] \dec_LDST_LDST__is_signed + case + assign $3\fus_oper_i_ldst_ldst0__is_signed[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__is_signed[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__is_signed $0\fus_oper_i_ldst_ldst0__is_signed[0:0] + end + attribute \src "libresoc.v:44781.3-44809.6" + process $proc$libresoc.v:44781$2441 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__data_len[3:0] $1\fus_oper_i_ldst_ldst0__data_len[3:0] + attribute \src "libresoc.v:44782.5-44782.29" + switch \initial + attribute \src "libresoc.v:44782.9-44782.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__data_len[3:0] $2\fus_oper_i_ldst_ldst0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__data_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__data_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__data_len[3:0] $3\fus_oper_i_ldst_ldst0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__data_len[3:0] \dec_LDST_LDST__data_len + case + assign $3\fus_oper_i_ldst_ldst0__data_len[3:0] 4'0000 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__data_len[3:0] 4'0000 + end + sync always + update \fus_oper_i_ldst_ldst0__data_len $0\fus_oper_i_ldst_ldst0__data_len[3:0] + end + attribute \src "libresoc.v:44810.3-44838.6" + process $proc$libresoc.v:44810$2442 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + attribute \src "libresoc.v:44811.5-44811.29" + switch \initial + attribute \src "libresoc.v:44811.9-44811.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] \dec_LDST_LDST__byte_reverse + case + assign $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__byte_reverse $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + end + attribute \src "libresoc.v:44839.3-44867.6" + process $proc$libresoc.v:44839$2443 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] + attribute \src "libresoc.v:44840.5-44840.29" + switch \initial + attribute \src "libresoc.v:44840.9-44840.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] \dec_LDST_LDST__sign_extend + case + assign $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__sign_extend $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] + end + attribute \src "libresoc.v:44868.3-44896.6" + process $proc$libresoc.v:44868$2444 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + attribute \src "libresoc.v:44869.5-44869.29" + switch \initial + attribute \src "libresoc.v:44869.9-44869.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] \dec_LDST_LDST__ldst_mode + case + assign $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] 2'00 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] 2'00 + end + sync always + update \fus_oper_i_ldst_ldst0__ldst_mode $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + end + attribute \src "libresoc.v:44897.3-44925.6" + process $proc$libresoc.v:44897$2445 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__insn[31:0] $1\fus_oper_i_ldst_ldst0__insn[31:0] + attribute \src "libresoc.v:44898.5-44898.29" + switch \initial + attribute \src "libresoc.v:44898.9-44898.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__insn[31:0] $2\fus_oper_i_ldst_ldst0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__insn[31:0] $3\fus_oper_i_ldst_ldst0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__insn[31:0] \dec_LDST_LDST__insn + case + assign $3\fus_oper_i_ldst_ldst0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__insn[31:0] 0 + end + sync always + update \fus_oper_i_ldst_ldst0__insn $0\fus_oper_i_ldst_ldst0__insn[31:0] + end + attribute \src "libresoc.v:44926.3-44954.6" + process $proc$libresoc.v:44926$2446 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$35[0:0]$2447 $1\fus_cu_issue_i$35[0:0]$2448 + attribute \src "libresoc.v:44927.5-44927.29" + switch \initial + attribute \src "libresoc.v:44927.9-44927.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$35[0:0]$2448 $2\fus_cu_issue_i$35[0:0]$2449 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$35[0:0]$2449 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$35[0:0]$2449 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$35[0:0]$2449 $3\fus_cu_issue_i$35[0:0]$2450 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$35[0:0]$2450 \issue_i + case + assign $3\fus_cu_issue_i$35[0:0]$2450 1'0 + end + end + case + assign $1\fus_cu_issue_i$35[0:0]$2448 1'0 + end + sync always + update \fus_cu_issue_i$35 $0\fus_cu_issue_i$35[0:0]$2447 + end + attribute \src "libresoc.v:44955.3-44983.6" + process $proc$libresoc.v:44955$2451 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$37[2:0]$2452 $1\fus_cu_rdmaskn_i$37[2:0]$2453 + attribute \src "libresoc.v:44956.5-44956.29" + switch \initial + attribute \src "libresoc.v:44956.9-44956.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$37[2:0]$2453 $2\fus_cu_rdmaskn_i$37[2:0]$2454 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$37[2:0]$2454 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$37[2:0]$2454 3'000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$37[2:0]$2454 $3\fus_cu_rdmaskn_i$37[2:0]$2455 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$37[2:0]$2455 \$343 + case + assign $3\fus_cu_rdmaskn_i$37[2:0]$2455 3'000 + end + end + case + assign $1\fus_cu_rdmaskn_i$37[2:0]$2453 3'000 + end + sync always + update \fus_cu_rdmaskn_i$37 $0\fus_cu_rdmaskn_i$37[2:0]$2452 + end + attribute \src "libresoc.v:44984.3-44992.6" + process $proc$libresoc.v:44984$2456 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_alu0_0$next[0:0]$2457 $1\dp_INT_ra_alu0_0$next[0:0]$2458 + attribute \src "libresoc.v:44985.5-44985.29" + switch \initial + attribute \src "libresoc.v:44985.9-44985.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_alu0_0$next[0:0]$2458 1'0 + case + assign $1\dp_INT_ra_alu0_0$next[0:0]$2458 \rp_INT_ra_alu0_0 + end + sync always + update \dp_INT_ra_alu0_0$next $0\dp_INT_ra_alu0_0$next[0:0]$2457 + end + attribute \src "libresoc.v:44993.3-45002.6" + process $proc$libresoc.v:44993$2459 + assign { } { } + assign { } { } + assign $0\fus_src1_i[63:0] $1\fus_src1_i[63:0] + attribute \src "libresoc.v:44994.5-44994.29" + switch \initial + attribute \src "libresoc.v:44994.9-44994.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_INT_ra_alu0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i[63:0] \int_src1__data_o + case + assign $1\fus_src1_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i $0\fus_src1_i[63:0] + end + attribute \src "libresoc.v:45003.3-45011.6" + process $proc$libresoc.v:45003$2460 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_cr0_1$next[0:0]$2461 $1\dp_INT_ra_cr0_1$next[0:0]$2462 + attribute \src "libresoc.v:45004.5-45004.29" + switch \initial + attribute \src "libresoc.v:45004.9-45004.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_cr0_1$next[0:0]$2462 1'0 + case + assign $1\dp_INT_ra_cr0_1$next[0:0]$2462 \rp_INT_ra_cr0_1 + end + sync always + update \dp_INT_ra_cr0_1$next $0\dp_INT_ra_cr0_1$next[0:0]$2461 + end + attribute \src "libresoc.v:45012.3-45021.6" + process $proc$libresoc.v:45012$2463 + assign { } { } + assign { } { } + assign $0\fus_src1_i$40[63:0]$2464 $1\fus_src1_i$40[63:0]$2465 + attribute \src "libresoc.v:45013.5-45013.29" + switch \initial + attribute \src "libresoc.v:45013.9-45013.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_INT_ra_cr0_1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$40[63:0]$2465 \int_src1__data_o + case + assign $1\fus_src1_i$40[63:0]$2465 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$40 $0\fus_src1_i$40[63:0]$2464 + end + attribute \src "libresoc.v:45022.3-45030.6" + process $proc$libresoc.v:45022$2466 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_trap0_2$next[0:0]$2467 $1\dp_INT_ra_trap0_2$next[0:0]$2468 + attribute \src "libresoc.v:45023.5-45023.29" + switch \initial + attribute \src "libresoc.v:45023.9-45023.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_trap0_2$next[0:0]$2468 1'0 + case + assign $1\dp_INT_ra_trap0_2$next[0:0]$2468 \rp_INT_ra_trap0_2 + end + sync always + update \dp_INT_ra_trap0_2$next $0\dp_INT_ra_trap0_2$next[0:0]$2467 + end + attribute \src "libresoc.v:45031.3-45040.6" + process $proc$libresoc.v:45031$2469 + assign { } { } + assign { } { } + assign $0\fus_src1_i$43[63:0]$2470 $1\fus_src1_i$43[63:0]$2471 + attribute \src "libresoc.v:45032.5-45032.29" + switch \initial + attribute \src "libresoc.v:45032.9-45032.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_INT_ra_trap0_2 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$43[63:0]$2471 \int_src1__data_o + case + assign $1\fus_src1_i$43[63:0]$2471 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$43 $0\fus_src1_i$43[63:0]$2470 + end + attribute \src "libresoc.v:45041.3-45049.6" + process $proc$libresoc.v:45041$2472 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_logical0_3$next[0:0]$2473 $1\dp_INT_ra_logical0_3$next[0:0]$2474 + attribute \src "libresoc.v:45042.5-45042.29" + switch \initial + attribute \src "libresoc.v:45042.9-45042.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_logical0_3$next[0:0]$2474 1'0 + case + assign $1\dp_INT_ra_logical0_3$next[0:0]$2474 \rp_INT_ra_logical0_3 + end + sync always + update \dp_INT_ra_logical0_3$next $0\dp_INT_ra_logical0_3$next[0:0]$2473 + end + attribute \src "libresoc.v:45050.3-45059.6" + process $proc$libresoc.v:45050$2475 + assign { } { } + assign { } { } + assign $0\fus_src1_i$46[63:0]$2476 $1\fus_src1_i$46[63:0]$2477 + attribute \src "libresoc.v:45051.5-45051.29" + switch \initial + attribute \src "libresoc.v:45051.9-45051.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_INT_ra_logical0_3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$46[63:0]$2477 \int_src1__data_o + case + assign $1\fus_src1_i$46[63:0]$2477 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$46 $0\fus_src1_i$46[63:0]$2476 + end + attribute \src "libresoc.v:45060.3-45068.6" + process $proc$libresoc.v:45060$2478 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_spr0_4$next[0:0]$2479 $1\dp_INT_ra_spr0_4$next[0:0]$2480 + attribute \src "libresoc.v:45061.5-45061.29" + switch \initial + attribute \src "libresoc.v:45061.9-45061.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_spr0_4$next[0:0]$2480 1'0 + case + assign $1\dp_INT_ra_spr0_4$next[0:0]$2480 \rp_INT_ra_spr0_4 + end + sync always + update \dp_INT_ra_spr0_4$next $0\dp_INT_ra_spr0_4$next[0:0]$2479 + end + attribute \src "libresoc.v:45069.3-45078.6" + process $proc$libresoc.v:45069$2481 + assign { } { } + assign { } { } + assign $0\fus_src1_i$49[63:0]$2482 $1\fus_src1_i$49[63:0]$2483 + attribute \src "libresoc.v:45070.5-45070.29" + switch \initial + attribute \src "libresoc.v:45070.9-45070.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_INT_ra_spr0_4 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$49[63:0]$2483 \int_src1__data_o + case + assign $1\fus_src1_i$49[63:0]$2483 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$49 $0\fus_src1_i$49[63:0]$2482 + end + attribute \src "libresoc.v:45079.3-45087.6" + process $proc$libresoc.v:45079$2484 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_div0_5$next[0:0]$2485 $1\dp_INT_ra_div0_5$next[0:0]$2486 + attribute \src "libresoc.v:45080.5-45080.29" + switch \initial + attribute \src "libresoc.v:45080.9-45080.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_div0_5$next[0:0]$2486 1'0 + case + assign $1\dp_INT_ra_div0_5$next[0:0]$2486 \rp_INT_ra_div0_5 + end + sync always + update \dp_INT_ra_div0_5$next $0\dp_INT_ra_div0_5$next[0:0]$2485 + end + attribute \src "libresoc.v:45088.3-45097.6" + process $proc$libresoc.v:45088$2487 + assign { } { } + assign { } { } + assign $0\fus_src1_i$52[63:0]$2488 $1\fus_src1_i$52[63:0]$2489 + attribute \src "libresoc.v:45089.5-45089.29" + switch \initial + attribute \src "libresoc.v:45089.9-45089.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_INT_ra_div0_5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$52[63:0]$2489 \int_src1__data_o + case + assign $1\fus_src1_i$52[63:0]$2489 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$52 $0\fus_src1_i$52[63:0]$2488 + end + attribute \src "libresoc.v:45098.3-45106.6" + process $proc$libresoc.v:45098$2490 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_mul0_6$next[0:0]$2491 $1\dp_INT_ra_mul0_6$next[0:0]$2492 + attribute \src "libresoc.v:45099.5-45099.29" + switch \initial + attribute \src "libresoc.v:45099.9-45099.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_mul0_6$next[0:0]$2492 1'0 + case + assign $1\dp_INT_ra_mul0_6$next[0:0]$2492 \rp_INT_ra_mul0_6 + end + sync always + update \dp_INT_ra_mul0_6$next $0\dp_INT_ra_mul0_6$next[0:0]$2491 + end + attribute \src "libresoc.v:45107.3-45116.6" + process $proc$libresoc.v:45107$2493 + assign { } { } + assign { } { } + assign $0\fus_src1_i$55[63:0]$2494 $1\fus_src1_i$55[63:0]$2495 + attribute \src "libresoc.v:45108.5-45108.29" + switch \initial + attribute \src "libresoc.v:45108.9-45108.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_INT_ra_mul0_6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$55[63:0]$2495 \int_src1__data_o + case + assign $1\fus_src1_i$55[63:0]$2495 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$55 $0\fus_src1_i$55[63:0]$2494 + end + attribute \src "libresoc.v:45117.3-45125.6" + process $proc$libresoc.v:45117$2496 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_shiftrot0_7$next[0:0]$2497 $1\dp_INT_ra_shiftrot0_7$next[0:0]$2498 + attribute \src "libresoc.v:45118.5-45118.29" + switch \initial + attribute \src "libresoc.v:45118.9-45118.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_shiftrot0_7$next[0:0]$2498 1'0 + case + assign $1\dp_INT_ra_shiftrot0_7$next[0:0]$2498 \rp_INT_ra_shiftrot0_7 + end + sync always + update \dp_INT_ra_shiftrot0_7$next $0\dp_INT_ra_shiftrot0_7$next[0:0]$2497 + end + attribute \src "libresoc.v:45126.3-45135.6" + process $proc$libresoc.v:45126$2499 + assign { } { } + assign { } { } + assign $0\fus_src1_i$58[63:0]$2500 $1\fus_src1_i$58[63:0]$2501 + attribute \src "libresoc.v:45127.5-45127.29" + switch \initial + attribute \src "libresoc.v:45127.9-45127.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_INT_ra_shiftrot0_7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$58[63:0]$2501 \int_src1__data_o + case + assign $1\fus_src1_i$58[63:0]$2501 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$58 $0\fus_src1_i$58[63:0]$2500 + end + attribute \src "libresoc.v:45136.3-45144.6" + process $proc$libresoc.v:45136$2502 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_ldst0_8$next[0:0]$2503 $1\dp_INT_ra_ldst0_8$next[0:0]$2504 + attribute \src "libresoc.v:45137.5-45137.29" + switch \initial + attribute \src "libresoc.v:45137.9-45137.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_ldst0_8$next[0:0]$2504 1'0 + case + assign $1\dp_INT_ra_ldst0_8$next[0:0]$2504 \rp_INT_ra_ldst0_8 + end + sync always + update \dp_INT_ra_ldst0_8$next $0\dp_INT_ra_ldst0_8$next[0:0]$2503 + end + attribute \src "libresoc.v:45145.3-45154.6" + process $proc$libresoc.v:45145$2505 + assign { } { } + assign { } { } + assign $0\fus_src1_i$61[63:0]$2506 $1\fus_src1_i$61[63:0]$2507 + attribute \src "libresoc.v:45146.5-45146.29" + switch \initial + attribute \src "libresoc.v:45146.9-45146.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_INT_ra_ldst0_8 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$61[63:0]$2507 \int_src1__data_o + case + assign $1\fus_src1_i$61[63:0]$2507 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$61 $0\fus_src1_i$61[63:0]$2506 + end + attribute \src "libresoc.v:45155.3-45163.6" + process $proc$libresoc.v:45155$2508 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_alu0_0$next[0:0]$2509 $1\dp_INT_rb_alu0_0$next[0:0]$2510 + attribute \src "libresoc.v:45156.5-45156.29" + switch \initial + attribute \src "libresoc.v:45156.9-45156.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_alu0_0$next[0:0]$2510 1'0 + case + assign $1\dp_INT_rb_alu0_0$next[0:0]$2510 \rp_INT_rb_alu0_0 + end + sync always + update \dp_INT_rb_alu0_0$next $0\dp_INT_rb_alu0_0$next[0:0]$2509 + end + attribute \src "libresoc.v:45164.3-45173.6" + process $proc$libresoc.v:45164$2511 + assign { } { } + assign { } { } + assign $0\fus_src2_i[63:0] $1\fus_src2_i[63:0] + attribute \src "libresoc.v:45165.5-45165.29" + switch \initial + attribute \src "libresoc.v:45165.9-45165.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_INT_rb_alu0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i[63:0] \int_src2__data_o + case + assign $1\fus_src2_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i $0\fus_src2_i[63:0] + end + attribute \src "libresoc.v:45174.3-45182.6" + process $proc$libresoc.v:45174$2512 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_cr0_1$next[0:0]$2513 $1\dp_INT_rb_cr0_1$next[0:0]$2514 + attribute \src "libresoc.v:45175.5-45175.29" + switch \initial + attribute \src "libresoc.v:45175.9-45175.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_cr0_1$next[0:0]$2514 1'0 + case + assign $1\dp_INT_rb_cr0_1$next[0:0]$2514 \rp_INT_rb_cr0_1 + end + sync always + update \dp_INT_rb_cr0_1$next $0\dp_INT_rb_cr0_1$next[0:0]$2513 + end + attribute \src "libresoc.v:45183.3-45192.6" + process $proc$libresoc.v:45183$2515 + assign { } { } + assign { } { } + assign $0\fus_src2_i$62[63:0]$2516 $1\fus_src2_i$62[63:0]$2517 + attribute \src "libresoc.v:45184.5-45184.29" + switch \initial + attribute \src "libresoc.v:45184.9-45184.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_INT_rb_cr0_1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$62[63:0]$2517 \int_src2__data_o + case + assign $1\fus_src2_i$62[63:0]$2517 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$62 $0\fus_src2_i$62[63:0]$2516 + end + attribute \src "libresoc.v:45193.3-45201.6" + process $proc$libresoc.v:45193$2518 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_trap0_2$next[0:0]$2519 $1\dp_INT_rb_trap0_2$next[0:0]$2520 + attribute \src "libresoc.v:45194.5-45194.29" + switch \initial + attribute \src "libresoc.v:45194.9-45194.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_trap0_2$next[0:0]$2520 1'0 + case + assign $1\dp_INT_rb_trap0_2$next[0:0]$2520 \rp_INT_rb_trap0_2 + end + sync always + update \dp_INT_rb_trap0_2$next $0\dp_INT_rb_trap0_2$next[0:0]$2519 + end + attribute \src "libresoc.v:45202.3-45211.6" + process $proc$libresoc.v:45202$2521 + assign { } { } + assign { } { } + assign $0\fus_src2_i$63[63:0]$2522 $1\fus_src2_i$63[63:0]$2523 + attribute \src "libresoc.v:45203.5-45203.29" + switch \initial + attribute \src "libresoc.v:45203.9-45203.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_INT_rb_trap0_2 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$63[63:0]$2523 \int_src2__data_o + case + assign $1\fus_src2_i$63[63:0]$2523 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$63 $0\fus_src2_i$63[63:0]$2522 + end + attribute \src "libresoc.v:45212.3-45220.6" + process $proc$libresoc.v:45212$2524 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_logical0_3$next[0:0]$2525 $1\dp_INT_rb_logical0_3$next[0:0]$2526 + attribute \src "libresoc.v:45213.5-45213.29" + switch \initial + attribute \src "libresoc.v:45213.9-45213.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_logical0_3$next[0:0]$2526 1'0 + case + assign $1\dp_INT_rb_logical0_3$next[0:0]$2526 \rp_INT_rb_logical0_3 + end + sync always + update \dp_INT_rb_logical0_3$next $0\dp_INT_rb_logical0_3$next[0:0]$2525 + end + attribute \src "libresoc.v:45221.3-45230.6" + process $proc$libresoc.v:45221$2527 + assign { } { } + assign { } { } + assign $0\fus_src2_i$64[63:0]$2528 $1\fus_src2_i$64[63:0]$2529 + attribute \src "libresoc.v:45222.5-45222.29" + switch \initial + attribute \src "libresoc.v:45222.9-45222.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_INT_rb_logical0_3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$64[63:0]$2529 \int_src2__data_o + case + assign $1\fus_src2_i$64[63:0]$2529 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$64 $0\fus_src2_i$64[63:0]$2528 + end + attribute \src "libresoc.v:45231.3-45239.6" + process $proc$libresoc.v:45231$2530 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_div0_4$next[0:0]$2531 $1\dp_INT_rb_div0_4$next[0:0]$2532 + attribute \src "libresoc.v:45232.5-45232.29" + switch \initial + attribute \src "libresoc.v:45232.9-45232.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_div0_4$next[0:0]$2532 1'0 + case + assign $1\dp_INT_rb_div0_4$next[0:0]$2532 \rp_INT_rb_div0_4 + end + sync always + update \dp_INT_rb_div0_4$next $0\dp_INT_rb_div0_4$next[0:0]$2531 + end + attribute \src "libresoc.v:45240.3-45249.6" + process $proc$libresoc.v:45240$2533 + assign { } { } + assign { } { } + assign $0\fus_src2_i$65[63:0]$2534 $1\fus_src2_i$65[63:0]$2535 + attribute \src "libresoc.v:45241.5-45241.29" + switch \initial + attribute \src "libresoc.v:45241.9-45241.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_INT_rb_div0_4 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$65[63:0]$2535 \int_src2__data_o + case + assign $1\fus_src2_i$65[63:0]$2535 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$65 $0\fus_src2_i$65[63:0]$2534 + end + attribute \src "libresoc.v:45250.3-45258.6" + process $proc$libresoc.v:45250$2536 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_mul0_5$next[0:0]$2537 $1\dp_INT_rb_mul0_5$next[0:0]$2538 + attribute \src "libresoc.v:45251.5-45251.29" + switch \initial + attribute \src "libresoc.v:45251.9-45251.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_mul0_5$next[0:0]$2538 1'0 + case + assign $1\dp_INT_rb_mul0_5$next[0:0]$2538 \rp_INT_rb_mul0_5 + end + sync always + update \dp_INT_rb_mul0_5$next $0\dp_INT_rb_mul0_5$next[0:0]$2537 + end + attribute \src "libresoc.v:45259.3-45268.6" + process $proc$libresoc.v:45259$2539 + assign { } { } + assign { } { } + assign $0\fus_src2_i$66[63:0]$2540 $1\fus_src2_i$66[63:0]$2541 + attribute \src "libresoc.v:45260.5-45260.29" + switch \initial + attribute \src "libresoc.v:45260.9-45260.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_INT_rb_mul0_5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$66[63:0]$2541 \int_src2__data_o + case + assign $1\fus_src2_i$66[63:0]$2541 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$66 $0\fus_src2_i$66[63:0]$2540 + end + attribute \src "libresoc.v:45269.3-45277.6" + process $proc$libresoc.v:45269$2542 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_shiftrot0_6$next[0:0]$2543 $1\dp_INT_rb_shiftrot0_6$next[0:0]$2544 + attribute \src "libresoc.v:45270.5-45270.29" + switch \initial + attribute \src "libresoc.v:45270.9-45270.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_shiftrot0_6$next[0:0]$2544 1'0 + case + assign $1\dp_INT_rb_shiftrot0_6$next[0:0]$2544 \rp_INT_rb_shiftrot0_6 + end + sync always + update \dp_INT_rb_shiftrot0_6$next $0\dp_INT_rb_shiftrot0_6$next[0:0]$2543 + end + attribute \src "libresoc.v:45278.3-45287.6" + process $proc$libresoc.v:45278$2545 + assign { } { } + assign { } { } + assign $0\fus_src2_i$67[63:0]$2546 $1\fus_src2_i$67[63:0]$2547 + attribute \src "libresoc.v:45279.5-45279.29" + switch \initial + attribute \src "libresoc.v:45279.9-45279.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_INT_rb_shiftrot0_6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$67[63:0]$2547 \int_src2__data_o + case + assign $1\fus_src2_i$67[63:0]$2547 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$67 $0\fus_src2_i$67[63:0]$2546 + end + attribute \src "libresoc.v:45288.3-45296.6" + process $proc$libresoc.v:45288$2548 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_ldst0_7$next[0:0]$2549 $1\dp_INT_rb_ldst0_7$next[0:0]$2550 + attribute \src "libresoc.v:45289.5-45289.29" + switch \initial + attribute \src "libresoc.v:45289.9-45289.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_ldst0_7$next[0:0]$2550 1'0 + case + assign $1\dp_INT_rb_ldst0_7$next[0:0]$2550 \rp_INT_rb_ldst0_7 + end + sync always + update \dp_INT_rb_ldst0_7$next $0\dp_INT_rb_ldst0_7$next[0:0]$2549 + end + attribute \src "libresoc.v:45297.3-45306.6" + process $proc$libresoc.v:45297$2551 + assign { } { } + assign { } { } + assign $0\fus_src2_i$68[63:0]$2552 $1\fus_src2_i$68[63:0]$2553 + attribute \src "libresoc.v:45298.5-45298.29" + switch \initial + attribute \src "libresoc.v:45298.9-45298.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_INT_rb_ldst0_7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$68[63:0]$2553 \int_src2__data_o + case + assign $1\fus_src2_i$68[63:0]$2553 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$68 $0\fus_src2_i$68[63:0]$2552 + end + attribute \src "libresoc.v:45307.3-45315.6" + process $proc$libresoc.v:45307$2554 + assign { } { } + assign { } { } + assign $0\dp_INT_rc_shiftrot0_0$next[0:0]$2555 $1\dp_INT_rc_shiftrot0_0$next[0:0]$2556 + attribute \src "libresoc.v:45308.5-45308.29" + switch \initial + attribute \src "libresoc.v:45308.9-45308.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rc_shiftrot0_0$next[0:0]$2556 1'0 + case + assign $1\dp_INT_rc_shiftrot0_0$next[0:0]$2556 \rp_INT_rc_shiftrot0_0 + end + sync always + update \dp_INT_rc_shiftrot0_0$next $0\dp_INT_rc_shiftrot0_0$next[0:0]$2555 + end + attribute \src "libresoc.v:45316.3-45325.6" + process $proc$libresoc.v:45316$2557 + assign { } { } + assign { } { } + assign $0\fus_src3_i[63:0] $1\fus_src3_i[63:0] + attribute \src "libresoc.v:45317.5-45317.29" + switch \initial + attribute \src "libresoc.v:45317.9-45317.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_INT_rc_shiftrot0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i[63:0] \int_src3__data_o + case + assign $1\fus_src3_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src3_i $0\fus_src3_i[63:0] + end + attribute \src "libresoc.v:45326.3-45334.6" + process $proc$libresoc.v:45326$2558 + assign { } { } + assign { } { } + assign $0\dp_INT_rc_ldst0_1$next[0:0]$2559 $1\dp_INT_rc_ldst0_1$next[0:0]$2560 + attribute \src "libresoc.v:45327.5-45327.29" + switch \initial + attribute \src "libresoc.v:45327.9-45327.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rc_ldst0_1$next[0:0]$2560 1'0 + case + assign $1\dp_INT_rc_ldst0_1$next[0:0]$2560 \rp_INT_rc_ldst0_1 + end + sync always + update \dp_INT_rc_ldst0_1$next $0\dp_INT_rc_ldst0_1$next[0:0]$2559 + end + attribute \src "libresoc.v:45335.3-45344.6" + process $proc$libresoc.v:45335$2561 + assign { } { } + assign { } { } + assign $0\fus_src3_i$69[63:0]$2562 $1\fus_src3_i$69[63:0]$2563 + attribute \src "libresoc.v:45336.5-45336.29" + switch \initial + attribute \src "libresoc.v:45336.9-45336.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_INT_rc_ldst0_1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$69[63:0]$2563 \int_src3__data_o + case + assign $1\fus_src3_i$69[63:0]$2563 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src3_i$69 $0\fus_src3_i$69[63:0]$2562 + end + attribute \src "libresoc.v:45345.3-45371.6" + process $proc$libresoc.v:45345$2564 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\counter$next[1:0]$2565 $4\counter$next[1:0]$2569 + attribute \src "libresoc.v:45346.5-45346.29" + switch \initial + attribute \src "libresoc.v:45346.9-45346.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + switch \$214 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\counter$next[1:0]$2566 \$216 [1:0] + case + assign $1\counter$next[1:0]$2566 \counter + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\counter$next[1:0]$2567 $3\counter$next[1:0]$2568 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign { } { } + assign $3\counter$next[1:0]$2568 2'10 + case + assign $3\counter$next[1:0]$2568 $1\counter$next[1:0]$2566 + end + case + assign $2\counter$next[1:0]$2567 $1\counter$next[1:0]$2566 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\counter$next[1:0]$2569 2'00 + case + assign $4\counter$next[1:0]$2569 $2\counter$next[1:0]$2567 + end + sync always + update \counter$next $0\counter$next[1:0]$2565 + end + attribute \src "libresoc.v:45372.3-45380.6" + process $proc$libresoc.v:45372$2570 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_so_alu0_0$next[0:0]$2571 $1\dp_XER_xer_so_alu0_0$next[0:0]$2572 + attribute \src "libresoc.v:45373.5-45373.29" + switch \initial + attribute \src "libresoc.v:45373.9-45373.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_so_alu0_0$next[0:0]$2572 1'0 + case + assign $1\dp_XER_xer_so_alu0_0$next[0:0]$2572 \rp_XER_xer_so_alu0_0 + end + sync always + update \dp_XER_xer_so_alu0_0$next $0\dp_XER_xer_so_alu0_0$next[0:0]$2571 + end + attribute \src "libresoc.v:45381.3-45390.6" + process $proc$libresoc.v:45381$2573 + assign { } { } + assign { } { } + assign $0\fus_src3_i$70[0:0]$2574 $1\fus_src3_i$70[0:0]$2575 + attribute \src "libresoc.v:45382.5-45382.29" + switch \initial + attribute \src "libresoc.v:45382.9-45382.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_XER_xer_so_alu0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$70[0:0]$2575 \xer_src1__data_o [0] + case + assign $1\fus_src3_i$70[0:0]$2575 1'0 + end + sync always + update \fus_src3_i$70 $0\fus_src3_i$70[0:0]$2574 + end + attribute \src "libresoc.v:45391.3-45481.6" + process $proc$libresoc.v:45391$2576 + assign { } { } + assign { } { } + assign { } { } + assign $0\corebusy_o[0:0] $2\corebusy_o[0:0] + attribute \src "libresoc.v:45392.5-45392.29" + switch \initial + attribute \src "libresoc.v:45392.9-45392.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + switch \$219 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\corebusy_o[0:0] 1'1 + case + assign $1\corebusy_o[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\corebusy_o[0:0] $3\corebusy_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $3\corebusy_o[0:0] $1\corebusy_o[0:0] + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign { } { } + assign $3\corebusy_o[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $3\corebusy_o[0:0] $13\corebusy_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\corebusy_o[0:0] \fus_cu_busy_o + case + assign $4\corebusy_o[0:0] $1\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\corebusy_o[0:0] \fus_cu_busy_o$12 + case + assign $5\corebusy_o[0:0] $4\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\corebusy_o[0:0] \fus_cu_busy_o$15 + case + assign $6\corebusy_o[0:0] $5\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\corebusy_o[0:0] \fus_cu_busy_o$18 + case + assign $7\corebusy_o[0:0] $6\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\corebusy_o[0:0] \fus_cu_busy_o$21 + case + assign $8\corebusy_o[0:0] $7\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\corebusy_o[0:0] \fus_cu_busy_o$24 + case + assign $9\corebusy_o[0:0] $8\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $10\corebusy_o[0:0] \fus_cu_busy_o$27 + case + assign $10\corebusy_o[0:0] $9\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $11\corebusy_o[0:0] \fus_cu_busy_o$30 + case + assign $11\corebusy_o[0:0] $10\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $12\corebusy_o[0:0] \fus_cu_busy_o$33 + case + assign $12\corebusy_o[0:0] $11\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $13\corebusy_o[0:0] \fus_cu_busy_o$36 + case + assign $13\corebusy_o[0:0] $12\corebusy_o[0:0] + end + end + case + assign $2\corebusy_o[0:0] $1\corebusy_o[0:0] + end + sync always + update \corebusy_o $0\corebusy_o[0:0] + end + attribute \src "libresoc.v:45482.3-45490.6" + process $proc$libresoc.v:45482$2577 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_so_logical0_1$next[0:0]$2578 $1\dp_XER_xer_so_logical0_1$next[0:0]$2579 + attribute \src "libresoc.v:45483.5-45483.29" + switch \initial + attribute \src "libresoc.v:45483.9-45483.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_so_logical0_1$next[0:0]$2579 1'0 + case + assign $1\dp_XER_xer_so_logical0_1$next[0:0]$2579 \rp_XER_xer_so_logical0_1 + end + sync always + update \dp_XER_xer_so_logical0_1$next $0\dp_XER_xer_so_logical0_1$next[0:0]$2578 + end + attribute \src "libresoc.v:45491.3-45500.6" + process $proc$libresoc.v:45491$2580 + assign { } { } + assign { } { } + assign $0\fus_src3_i$71[0:0]$2581 $1\fus_src3_i$71[0:0]$2582 + attribute \src "libresoc.v:45492.5-45492.29" + switch \initial + attribute \src "libresoc.v:45492.9-45492.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_XER_xer_so_logical0_1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$71[0:0]$2582 \xer_src1__data_o [0] + case + assign $1\fus_src3_i$71[0:0]$2582 1'0 + end + sync always + update \fus_src3_i$71 $0\fus_src3_i$71[0:0]$2581 + end + attribute \src "libresoc.v:45501.3-45509.6" + process $proc$libresoc.v:45501$2583 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_so_spr0_2$next[0:0]$2584 $1\dp_XER_xer_so_spr0_2$next[0:0]$2585 + attribute \src "libresoc.v:45502.5-45502.29" + switch \initial + attribute \src "libresoc.v:45502.9-45502.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_so_spr0_2$next[0:0]$2585 1'0 + case + assign $1\dp_XER_xer_so_spr0_2$next[0:0]$2585 \rp_XER_xer_so_spr0_2 + end + sync always + update \dp_XER_xer_so_spr0_2$next $0\dp_XER_xer_so_spr0_2$next[0:0]$2584 + end + attribute \src "libresoc.v:45510.3-45519.6" + process $proc$libresoc.v:45510$2586 + assign { } { } + assign { } { } + assign $0\fus_src4_i[0:0] $1\fus_src4_i[0:0] + attribute \src "libresoc.v:45511.5-45511.29" + switch \initial + attribute \src "libresoc.v:45511.9-45511.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_XER_xer_so_spr0_2 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src4_i[0:0] \xer_src1__data_o [0] + case + assign $1\fus_src4_i[0:0] 1'0 + end + sync always + update \fus_src4_i $0\fus_src4_i[0:0] + end + attribute \src "libresoc.v:45520.3-45540.6" + process $proc$libresoc.v:45520$2587 + assign { } { } + assign { } { } + assign { } { } + assign $0\core_terminate_o$next[0:0]$2588 $3\core_terminate_o$next[0:0]$2591 + attribute \src "libresoc.v:45521.5-45521.29" + switch \initial + attribute \src "libresoc.v:45521.9-45521.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_terminate_o$next[0:0]$2589 $2\core_terminate_o$next[0:0]$2590 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign { } { } + assign $2\core_terminate_o$next[0:0]$2590 1'1 + case + assign $2\core_terminate_o$next[0:0]$2590 \core_terminate_o + end + case + assign $1\core_terminate_o$next[0:0]$2589 \core_terminate_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_terminate_o$next[0:0]$2591 1'0 + case + assign $3\core_terminate_o$next[0:0]$2591 $1\core_terminate_o$next[0:0]$2589 + end + sync always + update \core_terminate_o$next $0\core_terminate_o$next[0:0]$2588 + end + attribute \src "libresoc.v:45541.3-45549.6" + process $proc$libresoc.v:45541$2592 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_so_div0_3$next[0:0]$2593 $1\dp_XER_xer_so_div0_3$next[0:0]$2594 + attribute \src "libresoc.v:45542.5-45542.29" + switch \initial + attribute \src "libresoc.v:45542.9-45542.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_so_div0_3$next[0:0]$2594 1'0 + case + assign $1\dp_XER_xer_so_div0_3$next[0:0]$2594 \rp_XER_xer_so_div0_3 + end + sync always + update \dp_XER_xer_so_div0_3$next $0\dp_XER_xer_so_div0_3$next[0:0]$2593 + end + attribute \src "libresoc.v:45550.3-45559.6" + process $proc$libresoc.v:45550$2595 + assign { } { } + assign { } { } + assign $0\fus_src3_i$72[0:0]$2596 $1\fus_src3_i$72[0:0]$2597 + attribute \src "libresoc.v:45551.5-45551.29" + switch \initial + attribute \src "libresoc.v:45551.9-45551.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_XER_xer_so_div0_3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$72[0:0]$2597 \xer_src1__data_o [0] + case + assign $1\fus_src3_i$72[0:0]$2597 1'0 + end + sync always + update \fus_src3_i$72 $0\fus_src3_i$72[0:0]$2596 + end + attribute \src "libresoc.v:45560.3-45568.6" + process $proc$libresoc.v:45560$2598 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_so_mul0_4$next[0:0]$2599 $1\dp_XER_xer_so_mul0_4$next[0:0]$2600 + attribute \src "libresoc.v:45561.5-45561.29" + switch \initial + attribute \src "libresoc.v:45561.9-45561.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_so_mul0_4$next[0:0]$2600 1'0 + case + assign $1\dp_XER_xer_so_mul0_4$next[0:0]$2600 \rp_XER_xer_so_mul0_4 + end + sync always + update \dp_XER_xer_so_mul0_4$next $0\dp_XER_xer_so_mul0_4$next[0:0]$2599 + end + attribute \src "libresoc.v:45569.3-45578.6" + process $proc$libresoc.v:45569$2601 + assign { } { } + assign { } { } + assign $0\fus_src3_i$73[0:0]$2602 $1\fus_src3_i$73[0:0]$2603 + attribute \src "libresoc.v:45570.5-45570.29" + switch \initial + attribute \src "libresoc.v:45570.9-45570.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_XER_xer_so_mul0_4 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$73[0:0]$2603 \xer_src1__data_o [0] + case + assign $1\fus_src3_i$73[0:0]$2603 1'0 + end + sync always + update \fus_src3_i$73 $0\fus_src3_i$73[0:0]$2602 + end + attribute \src "libresoc.v:45579.3-45607.6" + process $proc$libresoc.v:45579$2604 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__insn_type[6:0] $1\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "libresoc.v:45580.5-45580.29" + switch \initial + attribute \src "libresoc.v:45580.9-45580.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__insn_type[6:0] $2\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__insn_type[6:0] $3\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__insn_type[6:0] \dec_ALU_ALU__insn_type + case + assign $3\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_alu0__insn_type $0\fus_oper_i_alu_alu0__insn_type[6:0] + end + attribute \src "libresoc.v:45608.3-45616.6" + process $proc$libresoc.v:45608$2605 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2606 $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2607 + attribute \src "libresoc.v:45609.5-45609.29" + switch \initial + attribute \src "libresoc.v:45609.9-45609.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2607 1'0 + case + assign $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2607 \rp_XER_xer_so_shiftrot0_5 + end + sync always + update \dp_XER_xer_so_shiftrot0_5$next $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2606 + end + attribute \src "libresoc.v:45617.3-45626.6" + process $proc$libresoc.v:45617$2608 + assign { } { } + assign { } { } + assign $0\fus_src4_i$74[0:0]$2609 $1\fus_src4_i$74[0:0]$2610 + attribute \src "libresoc.v:45618.5-45618.29" + switch \initial + attribute \src "libresoc.v:45618.9-45618.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_XER_xer_so_shiftrot0_5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src4_i$74[0:0]$2610 \xer_src1__data_o [0] + case + assign $1\fus_src4_i$74[0:0]$2610 1'0 + end + sync always + update \fus_src4_i$74 $0\fus_src4_i$74[0:0]$2609 + end + attribute \src "libresoc.v:45627.3-45635.6" + process $proc$libresoc.v:45627$2611 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_ca_alu0_0$next[0:0]$2612 $1\dp_XER_xer_ca_alu0_0$next[0:0]$2613 + attribute \src "libresoc.v:45628.5-45628.29" + switch \initial + attribute \src "libresoc.v:45628.9-45628.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_ca_alu0_0$next[0:0]$2613 1'0 + case + assign $1\dp_XER_xer_ca_alu0_0$next[0:0]$2613 \rp_XER_xer_ca_alu0_0 + end + sync always + update \dp_XER_xer_ca_alu0_0$next $0\dp_XER_xer_ca_alu0_0$next[0:0]$2612 + end + attribute \src "libresoc.v:45636.3-45664.6" + process $proc$libresoc.v:45636$2614 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__fn_unit[11:0] $1\fus_oper_i_alu_alu0__fn_unit[11:0] + attribute \src "libresoc.v:45637.5-45637.29" + switch \initial + attribute \src "libresoc.v:45637.9-45637.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__fn_unit[11:0] $2\fus_oper_i_alu_alu0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__fn_unit[11:0] $3\fus_oper_i_alu_alu0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__fn_unit[11:0] \dec_ALU_ALU__fn_unit + case + assign $3\fus_oper_i_alu_alu0__fn_unit[11:0] 12'000000000000 + end + end + case + assign $1\fus_oper_i_alu_alu0__fn_unit[11:0] 12'000000000000 + end + sync always + update \fus_oper_i_alu_alu0__fn_unit $0\fus_oper_i_alu_alu0__fn_unit[11:0] + end + attribute \src "libresoc.v:45665.3-45674.6" + process $proc$libresoc.v:45665$2615 + assign { } { } + assign { } { } + assign $0\fus_src4_i$75[1:0]$2616 $1\fus_src4_i$75[1:0]$2617 + attribute \src "libresoc.v:45666.5-45666.29" + switch \initial + attribute \src "libresoc.v:45666.9-45666.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_XER_xer_ca_alu0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src4_i$75[1:0]$2617 \xer_src2__data_o + case + assign $1\fus_src4_i$75[1:0]$2617 2'00 + end + sync always + update \fus_src4_i$75 $0\fus_src4_i$75[1:0]$2616 + end + attribute \src "libresoc.v:45675.3-45683.6" + process $proc$libresoc.v:45675$2618 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_ca_spr0_1$next[0:0]$2619 $1\dp_XER_xer_ca_spr0_1$next[0:0]$2620 + attribute \src "libresoc.v:45676.5-45676.29" + switch \initial + attribute \src "libresoc.v:45676.9-45676.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_ca_spr0_1$next[0:0]$2620 1'0 + case + assign $1\dp_XER_xer_ca_spr0_1$next[0:0]$2620 \rp_XER_xer_ca_spr0_1 + end + sync always + update \dp_XER_xer_ca_spr0_1$next $0\dp_XER_xer_ca_spr0_1$next[0:0]$2619 + end + attribute \src "libresoc.v:45684.3-45693.6" + process $proc$libresoc.v:45684$2621 + assign { } { } + assign { } { } + assign $0\fus_src6_i[1:0] $1\fus_src6_i[1:0] + attribute \src "libresoc.v:45685.5-45685.29" + switch \initial + attribute \src "libresoc.v:45685.9-45685.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_XER_xer_ca_spr0_1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src6_i[1:0] \xer_src2__data_o + case + assign $1\fus_src6_i[1:0] 2'00 + end + sync always + update \fus_src6_i $0\fus_src6_i[1:0] + end + attribute \src "libresoc.v:45694.3-45702.6" + process $proc$libresoc.v:45694$2622 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2623 $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2624 + attribute \src "libresoc.v:45695.5-45695.29" + switch \initial + attribute \src "libresoc.v:45695.9-45695.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2624 1'0 + case + assign $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2624 \rp_XER_xer_ca_shiftrot0_2 + end + sync always + update \dp_XER_xer_ca_shiftrot0_2$next $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2623 + end + attribute \src "libresoc.v:45703.3-45732.6" + process $proc$libresoc.v:45703$2625 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__imm_data__data[63:0] $1\fus_oper_i_alu_alu0__imm_data__data[63:0] + assign $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "libresoc.v:45704.5-45704.29" + switch \initial + attribute \src "libresoc.v:45704.9-45704.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_alu0__imm_data__data[63:0] $2\fus_oper_i_alu_alu0__imm_data__data[63:0] + assign $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] $3\fus_oper_i_alu_alu0__imm_data__data[63:0] + assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] $3\fus_oper_i_alu_alu0__imm_data__data[63:0] } { \dec_ALU_ALU__imm_data__ok \dec_ALU_ALU__imm_data__data } + case + assign $3\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__imm_data__data $0\fus_oper_i_alu_alu0__imm_data__data[63:0] + update \fus_oper_i_alu_alu0__imm_data__ok $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] + end + attribute \src "libresoc.v:45733.3-45742.6" + process $proc$libresoc.v:45733$2626 + assign { } { } + assign { } { } + assign $0\fus_src5_i[1:0] $1\fus_src5_i[1:0] + attribute \src "libresoc.v:45734.5-45734.29" + switch \initial + attribute \src "libresoc.v:45734.9-45734.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_XER_xer_ca_shiftrot0_2 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src5_i[1:0] \xer_src2__data_o + case + assign $1\fus_src5_i[1:0] 2'00 + end + sync always + update \fus_src5_i $0\fus_src5_i[1:0] + end + attribute \src "libresoc.v:45743.3-45751.6" + process $proc$libresoc.v:45743$2627 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_ov_spr0_0$next[0:0]$2628 $1\dp_XER_xer_ov_spr0_0$next[0:0]$2629 + attribute \src "libresoc.v:45744.5-45744.29" + switch \initial + attribute \src "libresoc.v:45744.9-45744.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_ov_spr0_0$next[0:0]$2629 1'0 + case + assign $1\dp_XER_xer_ov_spr0_0$next[0:0]$2629 \rp_XER_xer_ov_spr0_0 + end + sync always + update \dp_XER_xer_ov_spr0_0$next $0\dp_XER_xer_ov_spr0_0$next[0:0]$2628 + end + attribute \src "libresoc.v:45752.3-45761.6" + process $proc$libresoc.v:45752$2630 + assign { } { } + assign { } { } + assign $0\fus_src5_i$76[1:0]$2631 $1\fus_src5_i$76[1:0]$2632 + attribute \src "libresoc.v:45753.5-45753.29" + switch \initial + attribute \src "libresoc.v:45753.9-45753.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_XER_xer_ov_spr0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src5_i$76[1:0]$2632 \xer_src3__data_o + case + assign $1\fus_src5_i$76[1:0]$2632 2'00 + end + sync always + update \fus_src5_i$76 $0\fus_src5_i$76[1:0]$2631 + end + attribute \src "libresoc.v:45762.3-45770.6" + process $proc$libresoc.v:45762$2633 + assign { } { } + assign { } { } + assign $0\dp_CR_full_cr_cr0_0$next[0:0]$2634 $1\dp_CR_full_cr_cr0_0$next[0:0]$2635 + attribute \src "libresoc.v:45763.5-45763.29" + switch \initial + attribute \src "libresoc.v:45763.9-45763.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_CR_full_cr_cr0_0$next[0:0]$2635 1'0 + case + assign $1\dp_CR_full_cr_cr0_0$next[0:0]$2635 \rp_CR_full_cr_cr0_0 + end + sync always + update \dp_CR_full_cr_cr0_0$next $0\dp_CR_full_cr_cr0_0$next[0:0]$2634 + end + attribute \src "libresoc.v:45771.3-45780.6" + process $proc$libresoc.v:45771$2636 + assign { } { } + assign { } { } + assign $0\fus_src3_i$77[31:0]$2637 $1\fus_src3_i$77[31:0]$2638 + attribute \src "libresoc.v:45772.5-45772.29" + switch \initial + attribute \src "libresoc.v:45772.9-45772.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_CR_full_cr_cr0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$77[31:0]$2638 \cr_full_rd__data_o + case + assign $1\fus_src3_i$77[31:0]$2638 0 + end + sync always + update \fus_src3_i$77 $0\fus_src3_i$77[31:0]$2637 + end + attribute \src "libresoc.v:45781.3-45810.6" + process $proc$libresoc.v:45781$2639 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__rc__ok[0:0] $1\fus_oper_i_alu_alu0__rc__ok[0:0] + assign $0\fus_oper_i_alu_alu0__rc__rc[0:0] $1\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "libresoc.v:45782.5-45782.29" + switch \initial + attribute \src "libresoc.v:45782.9-45782.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_alu0__rc__ok[0:0] $2\fus_oper_i_alu_alu0__rc__ok[0:0] + assign $1\fus_oper_i_alu_alu0__rc__rc[0:0] $2\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] $3\fus_oper_i_alu_alu0__rc__ok[0:0] + assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] $3\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_alu0__rc__ok[0:0] $3\fus_oper_i_alu_alu0__rc__rc[0:0] } { \dec_ALU_ALU__rc__ok \dec_ALU_ALU__rc__rc } + case + assign $3\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 + assign $3\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 + assign $1\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__rc__ok $0\fus_oper_i_alu_alu0__rc__ok[0:0] + update \fus_oper_i_alu_alu0__rc__rc $0\fus_oper_i_alu_alu0__rc__rc[0:0] + end + attribute \src "libresoc.v:45811.3-45819.6" + process $proc$libresoc.v:45811$2640 + assign { } { } + assign { } { } + assign $0\dp_CR_cr_a_cr0_0$next[0:0]$2641 $1\dp_CR_cr_a_cr0_0$next[0:0]$2642 + attribute \src "libresoc.v:45812.5-45812.29" + switch \initial + attribute \src "libresoc.v:45812.9-45812.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_CR_cr_a_cr0_0$next[0:0]$2642 1'0 + case + assign $1\dp_CR_cr_a_cr0_0$next[0:0]$2642 \rp_CR_cr_a_cr0_0 + end + sync always + update \dp_CR_cr_a_cr0_0$next $0\dp_CR_cr_a_cr0_0$next[0:0]$2641 + end + attribute \src "libresoc.v:45820.3-45829.6" + process $proc$libresoc.v:45820$2643 + assign { } { } + assign { } { } + assign $0\fus_src4_i$78[3:0]$2644 $1\fus_src4_i$78[3:0]$2645 + attribute \src "libresoc.v:45821.5-45821.29" + switch \initial + attribute \src "libresoc.v:45821.9-45821.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_CR_cr_a_cr0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src4_i$78[3:0]$2645 \cr_src1__data_o + case + assign $1\fus_src4_i$78[3:0]$2645 4'0000 + end + sync always + update \fus_src4_i$78 $0\fus_src4_i$78[3:0]$2644 + end + attribute \src "libresoc.v:45830.3-45838.6" + process $proc$libresoc.v:45830$2646 + assign { } { } + assign { } { } + assign $0\dp_CR_cr_a_branch0_1$next[0:0]$2647 $1\dp_CR_cr_a_branch0_1$next[0:0]$2648 + attribute \src "libresoc.v:45831.5-45831.29" + switch \initial + attribute \src "libresoc.v:45831.9-45831.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_CR_cr_a_branch0_1$next[0:0]$2648 1'0 + case + assign $1\dp_CR_cr_a_branch0_1$next[0:0]$2648 \rp_CR_cr_a_branch0_1 + end + sync always + update \dp_CR_cr_a_branch0_1$next $0\dp_CR_cr_a_branch0_1$next[0:0]$2647 + end + attribute \src "libresoc.v:45839.3-45848.6" + process $proc$libresoc.v:45839$2649 + assign { } { } + assign { } { } + assign $0\fus_src3_i$81[3:0]$2650 $1\fus_src3_i$81[3:0]$2651 + attribute \src "libresoc.v:45840.5-45840.29" + switch \initial + attribute \src "libresoc.v:45840.9-45840.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_CR_cr_a_branch0_1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$81[3:0]$2651 \cr_src1__data_o + case + assign $1\fus_src3_i$81[3:0]$2651 4'0000 + end + sync always + update \fus_src3_i$81 $0\fus_src3_i$81[3:0]$2650 + end + attribute \src "libresoc.v:45849.3-45857.6" + process $proc$libresoc.v:45849$2652 + assign { } { } + assign { } { } + assign $0\dp_CR_cr_b_cr0_0$next[0:0]$2653 $1\dp_CR_cr_b_cr0_0$next[0:0]$2654 + attribute \src "libresoc.v:45850.5-45850.29" + switch \initial + attribute \src "libresoc.v:45850.9-45850.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_CR_cr_b_cr0_0$next[0:0]$2654 1'0 + case + assign $1\dp_CR_cr_b_cr0_0$next[0:0]$2654 \rp_CR_cr_b_cr0_0 + end + sync always + update \dp_CR_cr_b_cr0_0$next $0\dp_CR_cr_b_cr0_0$next[0:0]$2653 + end + attribute \src "libresoc.v:45858.3-45867.6" + process $proc$libresoc.v:45858$2655 + assign { } { } + assign { } { } + assign $0\fus_src5_i$82[3:0]$2656 $1\fus_src5_i$82[3:0]$2657 + attribute \src "libresoc.v:45859.5-45859.29" + switch \initial + attribute \src "libresoc.v:45859.9-45859.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_CR_cr_b_cr0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src5_i$82[3:0]$2657 \cr_src2__data_o + case + assign $1\fus_src5_i$82[3:0]$2657 4'0000 + end + sync always + update \fus_src5_i$82 $0\fus_src5_i$82[3:0]$2656 + end + attribute \src "libresoc.v:45868.3-45897.6" + process $proc$libresoc.v:45868$2658 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__oe__oe[0:0] $1\fus_oper_i_alu_alu0__oe__oe[0:0] + assign $0\fus_oper_i_alu_alu0__oe__ok[0:0] $1\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "libresoc.v:45869.5-45869.29" + switch \initial + attribute \src "libresoc.v:45869.9-45869.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_alu0__oe__oe[0:0] $2\fus_oper_i_alu_alu0__oe__oe[0:0] + assign $1\fus_oper_i_alu_alu0__oe__ok[0:0] $2\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] $3\fus_oper_i_alu_alu0__oe__oe[0:0] + assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] $3\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_alu0__oe__ok[0:0] $3\fus_oper_i_alu_alu0__oe__oe[0:0] } { \dec_ALU_ALU__oe__ok \dec_ALU_ALU__oe__oe } + case + assign $3\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 + assign $3\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 + assign $1\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__oe__oe $0\fus_oper_i_alu_alu0__oe__oe[0:0] + update \fus_oper_i_alu_alu0__oe__ok $0\fus_oper_i_alu_alu0__oe__ok[0:0] + end + attribute \src "libresoc.v:45898.3-45906.6" + process $proc$libresoc.v:45898$2659 + assign { } { } + assign { } { } + assign $0\dp_CR_cr_c_cr0_0$next[0:0]$2660 $1\dp_CR_cr_c_cr0_0$next[0:0]$2661 + attribute \src "libresoc.v:45899.5-45899.29" + switch \initial + attribute \src "libresoc.v:45899.9-45899.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_CR_cr_c_cr0_0$next[0:0]$2661 1'0 + case + assign $1\dp_CR_cr_c_cr0_0$next[0:0]$2661 \rp_CR_cr_c_cr0_0 + end + sync always + update \dp_CR_cr_c_cr0_0$next $0\dp_CR_cr_c_cr0_0$next[0:0]$2660 + end + attribute \src "libresoc.v:45907.3-45916.6" + process $proc$libresoc.v:45907$2662 + assign { } { } + assign { } { } + assign $0\fus_src6_i$83[3:0]$2663 $1\fus_src6_i$83[3:0]$2664 + attribute \src "libresoc.v:45908.5-45908.29" + switch \initial + attribute \src "libresoc.v:45908.9-45908.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_CR_cr_c_cr0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src6_i$83[3:0]$2664 \cr_src3__data_o + case + assign $1\fus_src6_i$83[3:0]$2664 4'0000 + end + sync always + update \fus_src6_i$83 $0\fus_src6_i$83[3:0]$2663 + end + attribute \src "libresoc.v:45917.3-45925.6" + process $proc$libresoc.v:45917$2665 + assign { } { } + assign { } { } + assign $0\dp_FAST_fast1_branch0_0$next[0:0]$2666 $1\dp_FAST_fast1_branch0_0$next[0:0]$2667 + attribute \src "libresoc.v:45918.5-45918.29" + switch \initial + attribute \src "libresoc.v:45918.9-45918.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_FAST_fast1_branch0_0$next[0:0]$2667 1'0 + case + assign $1\dp_FAST_fast1_branch0_0$next[0:0]$2667 \rp_FAST_fast1_branch0_0 + end + sync always + update \dp_FAST_fast1_branch0_0$next $0\dp_FAST_fast1_branch0_0$next[0:0]$2666 + end + attribute \src "libresoc.v:45926.3-45935.6" + process $proc$libresoc.v:45926$2668 + assign { } { } + assign { } { } + assign $0\fus_src1_i$84[63:0]$2669 $1\fus_src1_i$84[63:0]$2670 + attribute \src "libresoc.v:45927.5-45927.29" + switch \initial + attribute \src "libresoc.v:45927.9-45927.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_FAST_fast1_branch0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$84[63:0]$2670 \fast_src1__data_o + case + assign $1\fus_src1_i$84[63:0]$2670 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$84 $0\fus_src1_i$84[63:0]$2669 + end + attribute \src "libresoc.v:45936.3-45944.6" + process $proc$libresoc.v:45936$2671 + assign { } { } + assign { } { } + assign $0\dp_FAST_fast1_trap0_1$next[0:0]$2672 $1\dp_FAST_fast1_trap0_1$next[0:0]$2673 + attribute \src "libresoc.v:45937.5-45937.29" + switch \initial + attribute \src "libresoc.v:45937.9-45937.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_FAST_fast1_trap0_1$next[0:0]$2673 1'0 + case + assign $1\dp_FAST_fast1_trap0_1$next[0:0]$2673 \rp_FAST_fast1_trap0_1 + end + sync always + update \dp_FAST_fast1_trap0_1$next $0\dp_FAST_fast1_trap0_1$next[0:0]$2672 + end + attribute \src "libresoc.v:45945.3-45954.6" + process $proc$libresoc.v:45945$2674 + assign { } { } + assign { } { } + assign $0\fus_src3_i$85[63:0]$2675 $1\fus_src3_i$85[63:0]$2676 + attribute \src "libresoc.v:45946.5-45946.29" + switch \initial + attribute \src "libresoc.v:45946.9-45946.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_FAST_fast1_trap0_1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$85[63:0]$2676 \fast_src1__data_o + case + assign $1\fus_src3_i$85[63:0]$2676 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src3_i$85 $0\fus_src3_i$85[63:0]$2675 + end + attribute \src "libresoc.v:45955.3-45983.6" + process $proc$libresoc.v:45955$2677 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__invert_in[0:0] $1\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "libresoc.v:45956.5-45956.29" + switch \initial + attribute \src "libresoc.v:45956.9-45956.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__invert_in[0:0] $2\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__invert_in[0:0] $3\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__invert_in[0:0] \dec_ALU_ALU__invert_in + case + assign $3\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__invert_in $0\fus_oper_i_alu_alu0__invert_in[0:0] + end + attribute \src "libresoc.v:45984.3-45992.6" + process $proc$libresoc.v:45984$2678 + assign { } { } + assign { } { } + assign $0\dp_FAST_fast1_spr0_2$next[0:0]$2679 $1\dp_FAST_fast1_spr0_2$next[0:0]$2680 + attribute \src "libresoc.v:45985.5-45985.29" + switch \initial + attribute \src "libresoc.v:45985.9-45985.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_FAST_fast1_spr0_2$next[0:0]$2680 1'0 + case + assign $1\dp_FAST_fast1_spr0_2$next[0:0]$2680 \rp_FAST_fast1_spr0_2 + end + sync always + update \dp_FAST_fast1_spr0_2$next $0\dp_FAST_fast1_spr0_2$next[0:0]$2679 + end + attribute \src "libresoc.v:45993.3-46002.6" + process $proc$libresoc.v:45993$2681 + assign { } { } + assign { } { } + assign $0\fus_src3_i$86[63:0]$2682 $1\fus_src3_i$86[63:0]$2683 + attribute \src "libresoc.v:45994.5-45994.29" + switch \initial + attribute \src "libresoc.v:45994.9-45994.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_FAST_fast1_spr0_2 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$86[63:0]$2683 \fast_src1__data_o + case + assign $1\fus_src3_i$86[63:0]$2683 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src3_i$86 $0\fus_src3_i$86[63:0]$2682 + end + attribute \src "libresoc.v:46003.3-46031.6" + process $proc$libresoc.v:46003$2684 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__zero_a[0:0] $1\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "libresoc.v:46004.5-46004.29" + switch \initial + attribute \src "libresoc.v:46004.9-46004.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__zero_a[0:0] $2\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__zero_a[0:0] $3\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__zero_a[0:0] \dec_ALU_ALU__zero_a + case + assign $3\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__zero_a $0\fus_oper_i_alu_alu0__zero_a[0:0] + end + attribute \src "libresoc.v:46032.3-46040.6" + process $proc$libresoc.v:46032$2685 + assign { } { } + assign { } { } + assign $0\dp_FAST_fast2_branch0_0$next[0:0]$2686 $1\dp_FAST_fast2_branch0_0$next[0:0]$2687 + attribute \src "libresoc.v:46033.5-46033.29" + switch \initial + attribute \src "libresoc.v:46033.9-46033.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_FAST_fast2_branch0_0$next[0:0]$2687 1'0 + case + assign $1\dp_FAST_fast2_branch0_0$next[0:0]$2687 \rp_FAST_fast2_branch0_0 + end + sync always + update \dp_FAST_fast2_branch0_0$next $0\dp_FAST_fast2_branch0_0$next[0:0]$2686 + end + attribute \src "libresoc.v:46041.3-46050.6" + process $proc$libresoc.v:46041$2688 + assign { } { } + assign { } { } + assign $0\fus_src2_i$87[63:0]$2689 $1\fus_src2_i$87[63:0]$2690 + attribute \src "libresoc.v:46042.5-46042.29" + switch \initial + attribute \src "libresoc.v:46042.9-46042.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_FAST_fast2_branch0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$87[63:0]$2690 \fast_src2__data_o + case + assign $1\fus_src2_i$87[63:0]$2690 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$87 $0\fus_src2_i$87[63:0]$2689 + end + attribute \src "libresoc.v:46051.3-46059.6" + process $proc$libresoc.v:46051$2691 + assign { } { } + assign { } { } + assign $0\dp_FAST_fast2_trap0_1$next[0:0]$2692 $1\dp_FAST_fast2_trap0_1$next[0:0]$2693 + attribute \src "libresoc.v:46052.5-46052.29" + switch \initial + attribute \src "libresoc.v:46052.9-46052.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_FAST_fast2_trap0_1$next[0:0]$2693 1'0 + case + assign $1\dp_FAST_fast2_trap0_1$next[0:0]$2693 \rp_FAST_fast2_trap0_1 + end + sync always + update \dp_FAST_fast2_trap0_1$next $0\dp_FAST_fast2_trap0_1$next[0:0]$2692 + end + attribute \src "libresoc.v:46060.3-46069.6" + process $proc$libresoc.v:46060$2694 + assign { } { } + assign { } { } + assign $0\fus_src4_i$88[63:0]$2695 $1\fus_src4_i$88[63:0]$2696 + attribute \src "libresoc.v:46061.5-46061.29" + switch \initial + attribute \src "libresoc.v:46061.9-46061.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_FAST_fast2_trap0_1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src4_i$88[63:0]$2696 \fast_src2__data_o + case + assign $1\fus_src4_i$88[63:0]$2696 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src4_i$88 $0\fus_src4_i$88[63:0]$2695 + end + attribute \src "libresoc.v:46070.3-46098.6" + process $proc$libresoc.v:46070$2697 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__invert_out[0:0] $1\fus_oper_i_alu_alu0__invert_out[0:0] + attribute \src "libresoc.v:46071.5-46071.29" + switch \initial + attribute \src "libresoc.v:46071.9-46071.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__invert_out[0:0] $2\fus_oper_i_alu_alu0__invert_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__invert_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__invert_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__invert_out[0:0] $3\fus_oper_i_alu_alu0__invert_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__invert_out[0:0] \dec_ALU_ALU__invert_out + case + assign $3\fus_oper_i_alu_alu0__invert_out[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__invert_out[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__invert_out $0\fus_oper_i_alu_alu0__invert_out[0:0] + end + attribute \src "libresoc.v:46099.3-46107.6" + process $proc$libresoc.v:46099$2698 + assign { } { } + assign { } { } + assign $0\dp_SPR_spr1_spr0_0$next[0:0]$2699 $1\dp_SPR_spr1_spr0_0$next[0:0]$2700 + attribute \src "libresoc.v:46100.5-46100.29" + switch \initial + attribute \src "libresoc.v:46100.9-46100.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_SPR_spr1_spr0_0$next[0:0]$2700 1'0 + case + assign $1\dp_SPR_spr1_spr0_0$next[0:0]$2700 \rp_SPR_spr1_spr0_0 + end + sync always + update \dp_SPR_spr1_spr0_0$next $0\dp_SPR_spr1_spr0_0$next[0:0]$2699 + end + attribute \src "libresoc.v:46108.3-46117.6" + process $proc$libresoc.v:46108$2701 + assign { } { } + assign { } { } + assign $0\fus_src2_i$89[63:0]$2702 $1\fus_src2_i$89[63:0]$2703 + attribute \src "libresoc.v:46109.5-46109.29" + switch \initial + attribute \src "libresoc.v:46109.9-46109.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_SPR_spr1_spr0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$89[63:0]$2703 \spr_spr1__data_o + case + assign $1\fus_src2_i$89[63:0]$2703 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$89 $0\fus_src2_i$89[63:0]$2702 + end + attribute \src "libresoc.v:46118.3-46146.6" + process $proc$libresoc.v:46118$2704 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__write_cr0[0:0] $1\fus_oper_i_alu_alu0__write_cr0[0:0] + attribute \src "libresoc.v:46119.5-46119.29" + switch \initial + attribute \src "libresoc.v:46119.9-46119.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__write_cr0[0:0] $2\fus_oper_i_alu_alu0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__write_cr0[0:0] $3\fus_oper_i_alu_alu0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__write_cr0[0:0] \dec_ALU_ALU__write_cr0 + case + assign $3\fus_oper_i_alu_alu0__write_cr0[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__write_cr0[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__write_cr0 $0\fus_oper_i_alu_alu0__write_cr0[0:0] + end + attribute \src "libresoc.v:46147.3-46155.6" + process $proc$libresoc.v:46147$2705 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$next[0:0]$2706 $1\wr_pick_dly$next[0:0]$2707 + attribute \src "libresoc.v:46148.5-46148.29" + switch \initial + attribute \src "libresoc.v:46148.9-46148.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$next[0:0]$2707 1'0 + case + assign $1\wr_pick_dly$next[0:0]$2707 \wr_pick + end + sync always + update \wr_pick_dly$next $0\wr_pick_dly$next[0:0]$2706 + end + attribute \src "libresoc.v:46156.3-46184.6" + process $proc$libresoc.v:46156$2708 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__input_carry[1:0] $1\fus_oper_i_alu_alu0__input_carry[1:0] + attribute \src "libresoc.v:46157.5-46157.29" + switch \initial + attribute \src "libresoc.v:46157.9-46157.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__input_carry[1:0] $2\fus_oper_i_alu_alu0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__input_carry[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__input_carry[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__input_carry[1:0] $3\fus_oper_i_alu_alu0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__input_carry[1:0] \dec_ALU_ALU__input_carry + case + assign $3\fus_oper_i_alu_alu0__input_carry[1:0] 2'00 + end + end + case + assign $1\fus_oper_i_alu_alu0__input_carry[1:0] 2'00 + end + sync always + update \fus_oper_i_alu_alu0__input_carry $0\fus_oper_i_alu_alu0__input_carry[1:0] + end + attribute \src "libresoc.v:46185.3-46193.6" + process $proc$libresoc.v:46185$2709 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$981$next[0:0]$2710 $1\wr_pick_dly$981$next[0:0]$2711 + attribute \src "libresoc.v:46186.5-46186.29" + switch \initial + attribute \src "libresoc.v:46186.9-46186.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$981$next[0:0]$2711 1'0 + case + assign $1\wr_pick_dly$981$next[0:0]$2711 \wr_pick$978 + end + sync always + update \wr_pick_dly$981$next $0\wr_pick_dly$981$next[0:0]$2710 + end + attribute \src "libresoc.v:46194.3-46202.6" + process $proc$libresoc.v:46194$2712 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1000$next[0:0]$2713 $1\wr_pick_dly$1000$next[0:0]$2714 + attribute \src "libresoc.v:46195.5-46195.29" + switch \initial + attribute \src "libresoc.v:46195.9-46195.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1000$next[0:0]$2714 1'0 + case + assign $1\wr_pick_dly$1000$next[0:0]$2714 \wr_pick$997 + end + sync always + update \wr_pick_dly$1000$next $0\wr_pick_dly$1000$next[0:0]$2713 + end + attribute \src "libresoc.v:46203.3-46231.6" + process $proc$libresoc.v:46203$2715 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__output_carry[0:0] $1\fus_oper_i_alu_alu0__output_carry[0:0] + attribute \src "libresoc.v:46204.5-46204.29" + switch \initial + attribute \src "libresoc.v:46204.9-46204.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__output_carry[0:0] $2\fus_oper_i_alu_alu0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__output_carry[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__output_carry[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__output_carry[0:0] $3\fus_oper_i_alu_alu0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__output_carry[0:0] \dec_ALU_ALU__output_carry + case + assign $3\fus_oper_i_alu_alu0__output_carry[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__output_carry[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__output_carry $0\fus_oper_i_alu_alu0__output_carry[0:0] + end + attribute \src "libresoc.v:46232.3-46240.6" + process $proc$libresoc.v:46232$2716 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1021$next[0:0]$2717 $1\wr_pick_dly$1021$next[0:0]$2718 + attribute \src "libresoc.v:46233.5-46233.29" + switch \initial + attribute \src "libresoc.v:46233.9-46233.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1021$next[0:0]$2718 1'0 + case + assign $1\wr_pick_dly$1021$next[0:0]$2718 \wr_pick$1018 + end + sync always + update \wr_pick_dly$1021$next $0\wr_pick_dly$1021$next[0:0]$2717 + end + attribute \src "libresoc.v:46241.3-46269.6" + process $proc$libresoc.v:46241$2719 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__is_32bit[0:0] $1\fus_oper_i_alu_alu0__is_32bit[0:0] + attribute \src "libresoc.v:46242.5-46242.29" + switch \initial + attribute \src "libresoc.v:46242.9-46242.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__is_32bit[0:0] $2\fus_oper_i_alu_alu0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__is_32bit[0:0] $3\fus_oper_i_alu_alu0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__is_32bit[0:0] \dec_ALU_ALU__is_32bit + case + assign $3\fus_oper_i_alu_alu0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__is_32bit $0\fus_oper_i_alu_alu0__is_32bit[0:0] + end + attribute \src "libresoc.v:46270.3-46278.6" + process $proc$libresoc.v:46270$2720 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1039$next[0:0]$2721 $1\wr_pick_dly$1039$next[0:0]$2722 + attribute \src "libresoc.v:46271.5-46271.29" + switch \initial + attribute \src "libresoc.v:46271.9-46271.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1039$next[0:0]$2722 1'0 + case + assign $1\wr_pick_dly$1039$next[0:0]$2722 \wr_pick$1036 + end + sync always + update \wr_pick_dly$1039$next $0\wr_pick_dly$1039$next[0:0]$2721 + end + attribute \src "libresoc.v:46279.3-46287.6" + process $proc$libresoc.v:46279$2723 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1061$next[0:0]$2724 $1\wr_pick_dly$1061$next[0:0]$2725 + attribute \src "libresoc.v:46280.5-46280.29" + switch \initial + attribute \src "libresoc.v:46280.9-46280.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1061$next[0:0]$2725 1'0 + case + assign $1\wr_pick_dly$1061$next[0:0]$2725 \wr_pick$1058 + end + sync always + update \wr_pick_dly$1061$next $0\wr_pick_dly$1061$next[0:0]$2724 + end + attribute \src "libresoc.v:46288.3-46316.6" + process $proc$libresoc.v:46288$2726 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__is_signed[0:0] $1\fus_oper_i_alu_alu0__is_signed[0:0] + attribute \src "libresoc.v:46289.5-46289.29" + switch \initial + attribute \src "libresoc.v:46289.9-46289.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__is_signed[0:0] $2\fus_oper_i_alu_alu0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__is_signed[0:0] $3\fus_oper_i_alu_alu0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__is_signed[0:0] \dec_ALU_ALU__is_signed + case + assign $3\fus_oper_i_alu_alu0__is_signed[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__is_signed[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__is_signed $0\fus_oper_i_alu_alu0__is_signed[0:0] + end + attribute \src "libresoc.v:46317.3-46325.6" + process $proc$libresoc.v:46317$2727 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1081$next[0:0]$2728 $1\wr_pick_dly$1081$next[0:0]$2729 + attribute \src "libresoc.v:46318.5-46318.29" + switch \initial + attribute \src "libresoc.v:46318.9-46318.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1081$next[0:0]$2729 1'0 + case + assign $1\wr_pick_dly$1081$next[0:0]$2729 \wr_pick$1078 + end + sync always + update \wr_pick_dly$1081$next $0\wr_pick_dly$1081$next[0:0]$2728 + end + attribute \src "libresoc.v:46326.3-46354.6" + process $proc$libresoc.v:46326$2730 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__data_len[3:0] $1\fus_oper_i_alu_alu0__data_len[3:0] + attribute \src "libresoc.v:46327.5-46327.29" + switch \initial + attribute \src "libresoc.v:46327.9-46327.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__data_len[3:0] $2\fus_oper_i_alu_alu0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__data_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__data_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__data_len[3:0] $3\fus_oper_i_alu_alu0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__data_len[3:0] \dec_ALU_ALU__data_len + case + assign $3\fus_oper_i_alu_alu0__data_len[3:0] 4'0000 + end + end + case + assign $1\fus_oper_i_alu_alu0__data_len[3:0] 4'0000 + end + sync always + update \fus_oper_i_alu_alu0__data_len $0\fus_oper_i_alu_alu0__data_len[3:0] + end + attribute \src "libresoc.v:46355.3-46363.6" + process $proc$libresoc.v:46355$2731 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1101$next[0:0]$2732 $1\wr_pick_dly$1101$next[0:0]$2733 + attribute \src "libresoc.v:46356.5-46356.29" + switch \initial + attribute \src "libresoc.v:46356.9-46356.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1101$next[0:0]$2733 1'0 + case + assign $1\wr_pick_dly$1101$next[0:0]$2733 \wr_pick$1098 + end + sync always + update \wr_pick_dly$1101$next $0\wr_pick_dly$1101$next[0:0]$2732 + end + attribute \src "libresoc.v:46364.3-46372.6" + process $proc$libresoc.v:46364$2734 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1120$next[0:0]$2735 $1\wr_pick_dly$1120$next[0:0]$2736 + attribute \src "libresoc.v:46365.5-46365.29" + switch \initial + attribute \src "libresoc.v:46365.9-46365.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1120$next[0:0]$2736 1'0 + case + assign $1\wr_pick_dly$1120$next[0:0]$2736 \wr_pick$1117 + end + sync always + update \wr_pick_dly$1120$next $0\wr_pick_dly$1120$next[0:0]$2735 + end + attribute \src "libresoc.v:46373.3-46401.6" + process $proc$libresoc.v:46373$2737 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__insn[31:0] $1\fus_oper_i_alu_alu0__insn[31:0] + attribute \src "libresoc.v:46374.5-46374.29" + switch \initial + attribute \src "libresoc.v:46374.9-46374.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__insn[31:0] $2\fus_oper_i_alu_alu0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__insn[31:0] $3\fus_oper_i_alu_alu0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__insn[31:0] \dec_ALU_ALU__insn + case + assign $3\fus_oper_i_alu_alu0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_alu0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_alu0__insn $0\fus_oper_i_alu_alu0__insn[31:0] + end + attribute \src "libresoc.v:46402.3-46410.6" + process $proc$libresoc.v:46402$2738 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1138$next[0:0]$2739 $1\wr_pick_dly$1138$next[0:0]$2740 + attribute \src "libresoc.v:46403.5-46403.29" + switch \initial + attribute \src "libresoc.v:46403.9-46403.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1138$next[0:0]$2740 1'0 + case + assign $1\wr_pick_dly$1138$next[0:0]$2740 \wr_pick$1135 + end + sync always + update \wr_pick_dly$1138$next $0\wr_pick_dly$1138$next[0:0]$2739 + end + attribute \src "libresoc.v:46411.3-46439.6" + process $proc$libresoc.v:46411$2741 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i[0:0] $1\fus_cu_issue_i[0:0] + attribute \src "libresoc.v:46412.5-46412.29" + switch \initial + attribute \src "libresoc.v:46412.9-46412.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i[0:0] $2\fus_cu_issue_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i[0:0] $3\fus_cu_issue_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i[0:0] \issue_i + case + assign $3\fus_cu_issue_i[0:0] 1'0 + end + end + case + assign $1\fus_cu_issue_i[0:0] 1'0 + end + sync always + update \fus_cu_issue_i $0\fus_cu_issue_i[0:0] + end + attribute \src "libresoc.v:46440.3-46448.6" + process $proc$libresoc.v:46440$2742 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1211$next[0:0]$2743 $1\wr_pick_dly$1211$next[0:0]$2744 + attribute \src "libresoc.v:46441.5-46441.29" + switch \initial + attribute \src "libresoc.v:46441.9-46441.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1211$next[0:0]$2744 1'0 + case + assign $1\wr_pick_dly$1211$next[0:0]$2744 \wr_pick$1208 + end + sync always + update \wr_pick_dly$1211$next $0\wr_pick_dly$1211$next[0:0]$2743 + end + attribute \src "libresoc.v:46449.3-46477.6" + process $proc$libresoc.v:46449$2745 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i[3:0] $1\fus_cu_rdmaskn_i[3:0] + attribute \src "libresoc.v:46450.5-46450.29" + switch \initial + attribute \src "libresoc.v:46450.9-46450.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i[3:0] $2\fus_cu_rdmaskn_i[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i[3:0] $3\fus_cu_rdmaskn_i[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i[3:0] \$221 + case + assign $3\fus_cu_rdmaskn_i[3:0] 4'0000 + end + end + case + assign $1\fus_cu_rdmaskn_i[3:0] 4'0000 + end + sync always + update \fus_cu_rdmaskn_i $0\fus_cu_rdmaskn_i[3:0] + end + attribute \src "libresoc.v:46478.3-46486.6" + process $proc$libresoc.v:46478$2746 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1239$next[0:0]$2747 $1\wr_pick_dly$1239$next[0:0]$2748 + attribute \src "libresoc.v:46479.5-46479.29" + switch \initial + attribute \src "libresoc.v:46479.9-46479.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1239$next[0:0]$2748 1'0 + case + assign $1\wr_pick_dly$1239$next[0:0]$2748 \wr_pick$1236 + end + sync always + update \wr_pick_dly$1239$next $0\wr_pick_dly$1239$next[0:0]$2747 + end + attribute \src "libresoc.v:46487.3-46515.6" + process $proc$libresoc.v:46487$2749 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_cr0__insn_type[6:0] $1\fus_oper_i_alu_cr0__insn_type[6:0] + attribute \src "libresoc.v:46488.5-46488.29" + switch \initial + attribute \src "libresoc.v:46488.9-46488.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_cr0__insn_type[6:0] $2\fus_oper_i_alu_cr0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_cr0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_cr0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_cr0__insn_type[6:0] $3\fus_oper_i_alu_cr0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_cr0__insn_type[6:0] \dec_CR_CR__insn_type + case + assign $3\fus_oper_i_alu_cr0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_cr0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_cr0__insn_type $0\fus_oper_i_alu_cr0__insn_type[6:0] + end + attribute \src "libresoc.v:46516.3-46524.6" + process $proc$libresoc.v:46516$2750 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1259$next[0:0]$2751 $1\wr_pick_dly$1259$next[0:0]$2752 + attribute \src "libresoc.v:46517.5-46517.29" + switch \initial + attribute \src "libresoc.v:46517.9-46517.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1259$next[0:0]$2752 1'0 + case + assign $1\wr_pick_dly$1259$next[0:0]$2752 \wr_pick$1256 + end + sync always + update \wr_pick_dly$1259$next $0\wr_pick_dly$1259$next[0:0]$2751 + end + attribute \src "libresoc.v:46525.3-46533.6" + process $proc$libresoc.v:46525$2753 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1279$next[0:0]$2754 $1\wr_pick_dly$1279$next[0:0]$2755 + attribute \src "libresoc.v:46526.5-46526.29" + switch \initial + attribute \src "libresoc.v:46526.9-46526.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1279$next[0:0]$2755 1'0 + case + assign $1\wr_pick_dly$1279$next[0:0]$2755 \wr_pick$1276 + end + sync always + update \wr_pick_dly$1279$next $0\wr_pick_dly$1279$next[0:0]$2754 + end + attribute \src "libresoc.v:46534.3-46562.6" + process $proc$libresoc.v:46534$2756 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_cr0__fn_unit[11:0] $1\fus_oper_i_alu_cr0__fn_unit[11:0] + attribute \src "libresoc.v:46535.5-46535.29" + switch \initial + attribute \src "libresoc.v:46535.9-46535.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_cr0__fn_unit[11:0] $2\fus_oper_i_alu_cr0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_cr0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_cr0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_cr0__fn_unit[11:0] $3\fus_oper_i_alu_cr0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_cr0__fn_unit[11:0] \dec_CR_CR__fn_unit + case + assign $3\fus_oper_i_alu_cr0__fn_unit[11:0] 12'000000000000 + end + end + case + assign $1\fus_oper_i_alu_cr0__fn_unit[11:0] 12'000000000000 + end + sync always + update \fus_oper_i_alu_cr0__fn_unit $0\fus_oper_i_alu_cr0__fn_unit[11:0] + end + attribute \src "libresoc.v:46563.3-46571.6" + process $proc$libresoc.v:46563$2757 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1299$next[0:0]$2758 $1\wr_pick_dly$1299$next[0:0]$2759 + attribute \src "libresoc.v:46564.5-46564.29" + switch \initial + attribute \src "libresoc.v:46564.9-46564.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1299$next[0:0]$2759 1'0 + case + assign $1\wr_pick_dly$1299$next[0:0]$2759 \wr_pick$1296 + end + sync always + update \wr_pick_dly$1299$next $0\wr_pick_dly$1299$next[0:0]$2758 + end + attribute \src "libresoc.v:46572.3-46580.6" + process $proc$libresoc.v:46572$2760 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1319$next[0:0]$2761 $1\wr_pick_dly$1319$next[0:0]$2762 + attribute \src "libresoc.v:46573.5-46573.29" + switch \initial + attribute \src "libresoc.v:46573.9-46573.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1319$next[0:0]$2762 1'0 + case + assign $1\wr_pick_dly$1319$next[0:0]$2762 \wr_pick$1316 + end + sync always + update \wr_pick_dly$1319$next $0\wr_pick_dly$1319$next[0:0]$2761 + end + attribute \src "libresoc.v:46581.3-46609.6" + process $proc$libresoc.v:46581$2763 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_cr0__insn[31:0] $1\fus_oper_i_alu_cr0__insn[31:0] + attribute \src "libresoc.v:46582.5-46582.29" + switch \initial + attribute \src "libresoc.v:46582.9-46582.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_cr0__insn[31:0] $2\fus_oper_i_alu_cr0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_cr0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_cr0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_cr0__insn[31:0] $3\fus_oper_i_alu_cr0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_cr0__insn[31:0] \dec_CR_CR__insn + case + assign $3\fus_oper_i_alu_cr0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_cr0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_cr0__insn $0\fus_oper_i_alu_cr0__insn[31:0] + end + attribute \src "libresoc.v:46610.3-46618.6" + process $proc$libresoc.v:46610$2764 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1339$next[0:0]$2765 $1\wr_pick_dly$1339$next[0:0]$2766 + attribute \src "libresoc.v:46611.5-46611.29" + switch \initial + attribute \src "libresoc.v:46611.9-46611.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1339$next[0:0]$2766 1'0 + case + assign $1\wr_pick_dly$1339$next[0:0]$2766 \wr_pick$1336 + end + sync always + update \wr_pick_dly$1339$next $0\wr_pick_dly$1339$next[0:0]$2765 + end + attribute \src "libresoc.v:46619.3-46647.6" + process $proc$libresoc.v:46619$2767 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$11[0:0]$2768 $1\fus_cu_issue_i$11[0:0]$2769 + attribute \src "libresoc.v:46620.5-46620.29" + switch \initial + attribute \src "libresoc.v:46620.9-46620.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$11[0:0]$2769 $2\fus_cu_issue_i$11[0:0]$2770 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$11[0:0]$2770 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$11[0:0]$2770 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$11[0:0]$2770 $3\fus_cu_issue_i$11[0:0]$2771 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$11[0:0]$2771 \issue_i + case + assign $3\fus_cu_issue_i$11[0:0]$2771 1'0 + end + end + case + assign $1\fus_cu_issue_i$11[0:0]$2769 1'0 + end + sync always + update \fus_cu_issue_i$11 $0\fus_cu_issue_i$11[0:0]$2768 + end + attribute \src "libresoc.v:46648.3-46656.6" + process $proc$libresoc.v:46648$2772 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1386$next[0:0]$2773 $1\wr_pick_dly$1386$next[0:0]$2774 + attribute \src "libresoc.v:46649.5-46649.29" + switch \initial + attribute \src "libresoc.v:46649.9-46649.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1386$next[0:0]$2774 1'0 + case + assign $1\wr_pick_dly$1386$next[0:0]$2774 \wr_pick$1383 + end + sync always + update \wr_pick_dly$1386$next $0\wr_pick_dly$1386$next[0:0]$2773 + end + attribute \src "libresoc.v:46657.3-46685.6" + process $proc$libresoc.v:46657$2775 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$13[5:0]$2776 $1\fus_cu_rdmaskn_i$13[5:0]$2777 + attribute \src "libresoc.v:46658.5-46658.29" + switch \initial + attribute \src "libresoc.v:46658.9-46658.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$13[5:0]$2777 $2\fus_cu_rdmaskn_i$13[5:0]$2778 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$13[5:0]$2778 6'000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$13[5:0]$2778 6'000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$13[5:0]$2778 $3\fus_cu_rdmaskn_i$13[5:0]$2779 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$13[5:0]$2779 \$243 + case + assign $3\fus_cu_rdmaskn_i$13[5:0]$2779 6'000000 + end + end + case + assign $1\fus_cu_rdmaskn_i$13[5:0]$2777 6'000000 + end + sync always + update \fus_cu_rdmaskn_i$13 $0\fus_cu_rdmaskn_i$13[5:0]$2776 + end + attribute \src "libresoc.v:46686.3-46694.6" + process $proc$libresoc.v:46686$2780 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1402$next[0:0]$2781 $1\wr_pick_dly$1402$next[0:0]$2782 + attribute \src "libresoc.v:46687.5-46687.29" + switch \initial + attribute \src "libresoc.v:46687.9-46687.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1402$next[0:0]$2782 1'0 + case + assign $1\wr_pick_dly$1402$next[0:0]$2782 \wr_pick$1399 + end + sync always + update \wr_pick_dly$1402$next $0\wr_pick_dly$1402$next[0:0]$2781 + end + attribute \src "libresoc.v:46695.3-46703.6" + process $proc$libresoc.v:46695$2783 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1418$next[0:0]$2784 $1\wr_pick_dly$1418$next[0:0]$2785 + attribute \src "libresoc.v:46696.5-46696.29" + switch \initial + attribute \src "libresoc.v:46696.9-46696.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1418$next[0:0]$2785 1'0 + case + assign $1\wr_pick_dly$1418$next[0:0]$2785 \wr_pick$1415 + end + sync always + update \wr_pick_dly$1418$next $0\wr_pick_dly$1418$next[0:0]$2784 + end + attribute \src "libresoc.v:46704.3-46732.6" + process $proc$libresoc.v:46704$2786 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_branch0__cia[63:0] $1\fus_oper_i_alu_branch0__cia[63:0] + attribute \src "libresoc.v:46705.5-46705.29" + switch \initial + attribute \src "libresoc.v:46705.9-46705.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_branch0__cia[63:0] $2\fus_oper_i_alu_branch0__cia[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_branch0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_branch0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_branch0__cia[63:0] $3\fus_oper_i_alu_branch0__cia[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_branch0__cia[63:0] \dec_BRANCH_BRANCH__cia + case + assign $3\fus_oper_i_alu_branch0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + end + case + assign $1\fus_oper_i_alu_branch0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_oper_i_alu_branch0__cia $0\fus_oper_i_alu_branch0__cia[63:0] + end + attribute \src "libresoc.v:46733.3-46741.6" + process $proc$libresoc.v:46733$2787 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1452$next[0:0]$2788 $1\wr_pick_dly$1452$next[0:0]$2789 + attribute \src "libresoc.v:46734.5-46734.29" + switch \initial + attribute \src "libresoc.v:46734.9-46734.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1452$next[0:0]$2789 1'0 + case + assign $1\wr_pick_dly$1452$next[0:0]$2789 \wr_pick$1449 + end + sync always + update \wr_pick_dly$1452$next $0\wr_pick_dly$1452$next[0:0]$2788 + end + attribute \src "libresoc.v:46742.3-46770.6" + process $proc$libresoc.v:46742$2790 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_branch0__insn_type[6:0] $1\fus_oper_i_alu_branch0__insn_type[6:0] + attribute \src "libresoc.v:46743.5-46743.29" + switch \initial + attribute \src "libresoc.v:46743.9-46743.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_branch0__insn_type[6:0] $2\fus_oper_i_alu_branch0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_branch0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_branch0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_branch0__insn_type[6:0] $3\fus_oper_i_alu_branch0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_branch0__insn_type[6:0] \dec_BRANCH_BRANCH__insn_type + case + assign $3\fus_oper_i_alu_branch0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_branch0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_branch0__insn_type $0\fus_oper_i_alu_branch0__insn_type[6:0] + end + attribute \src "libresoc.v:46771.3-46779.6" + process $proc$libresoc.v:46771$2791 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1468$next[0:0]$2792 $1\wr_pick_dly$1468$next[0:0]$2793 + attribute \src "libresoc.v:46772.5-46772.29" + switch \initial + attribute \src "libresoc.v:46772.9-46772.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1468$next[0:0]$2793 1'0 + case + assign $1\wr_pick_dly$1468$next[0:0]$2793 \wr_pick$1465 + end + sync always + update \wr_pick_dly$1468$next $0\wr_pick_dly$1468$next[0:0]$2792 + end + attribute \src "libresoc.v:46780.3-46788.6" + process $proc$libresoc.v:46780$2794 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1484$next[0:0]$2795 $1\wr_pick_dly$1484$next[0:0]$2796 + attribute \src "libresoc.v:46781.5-46781.29" + switch \initial + attribute \src "libresoc.v:46781.9-46781.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1484$next[0:0]$2796 1'0 + case + assign $1\wr_pick_dly$1484$next[0:0]$2796 \wr_pick$1481 + end + sync always + update \wr_pick_dly$1484$next $0\wr_pick_dly$1484$next[0:0]$2795 + end + attribute \src "libresoc.v:46789.3-46817.6" + process $proc$libresoc.v:46789$2797 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_branch0__fn_unit[11:0] $1\fus_oper_i_alu_branch0__fn_unit[11:0] + attribute \src "libresoc.v:46790.5-46790.29" + switch \initial + attribute \src "libresoc.v:46790.9-46790.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_branch0__fn_unit[11:0] $2\fus_oper_i_alu_branch0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_branch0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_branch0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_branch0__fn_unit[11:0] $3\fus_oper_i_alu_branch0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_branch0__fn_unit[11:0] \dec_BRANCH_BRANCH__fn_unit + case + assign $3\fus_oper_i_alu_branch0__fn_unit[11:0] 12'000000000000 + end + end + case + assign $1\fus_oper_i_alu_branch0__fn_unit[11:0] 12'000000000000 + end + sync always + update \fus_oper_i_alu_branch0__fn_unit $0\fus_oper_i_alu_branch0__fn_unit[11:0] + end + attribute \src "libresoc.v:46818.3-46826.6" + process $proc$libresoc.v:46818$2798 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1500$next[0:0]$2799 $1\wr_pick_dly$1500$next[0:0]$2800 + attribute \src "libresoc.v:46819.5-46819.29" + switch \initial + attribute \src "libresoc.v:46819.9-46819.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1500$next[0:0]$2800 1'0 + case + assign $1\wr_pick_dly$1500$next[0:0]$2800 \wr_pick$1497 + end + sync always + update \wr_pick_dly$1500$next $0\wr_pick_dly$1500$next[0:0]$2799 + end + attribute \src "libresoc.v:46827.3-46855.6" + process $proc$libresoc.v:46827$2801 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_branch0__insn[31:0] $1\fus_oper_i_alu_branch0__insn[31:0] + attribute \src "libresoc.v:46828.5-46828.29" + switch \initial + attribute \src "libresoc.v:46828.9-46828.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_branch0__insn[31:0] $2\fus_oper_i_alu_branch0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_branch0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_branch0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_branch0__insn[31:0] $3\fus_oper_i_alu_branch0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_branch0__insn[31:0] \dec_BRANCH_BRANCH__insn + case + assign $3\fus_oper_i_alu_branch0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_branch0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_branch0__insn $0\fus_oper_i_alu_branch0__insn[31:0] + end + attribute \src "libresoc.v:46856.3-46864.6" + process $proc$libresoc.v:46856$2802 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1536$next[0:0]$2803 $1\wr_pick_dly$1536$next[0:0]$2804 + attribute \src "libresoc.v:46857.5-46857.29" + switch \initial + attribute \src "libresoc.v:46857.9-46857.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1536$next[0:0]$2804 1'0 + case + assign $1\wr_pick_dly$1536$next[0:0]$2804 \wr_pick$1533 + end + sync always + update \wr_pick_dly$1536$next $0\wr_pick_dly$1536$next[0:0]$2803 + end + attribute \src "libresoc.v:46865.3-46873.6" + process $proc$libresoc.v:46865$2805 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1552$next[0:0]$2806 $1\wr_pick_dly$1552$next[0:0]$2807 + attribute \src "libresoc.v:46866.5-46866.29" + switch \initial + attribute \src "libresoc.v:46866.9-46866.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1552$next[0:0]$2807 1'0 + case + assign $1\wr_pick_dly$1552$next[0:0]$2807 \wr_pick$1549 + end + sync always + update \wr_pick_dly$1552$next $0\wr_pick_dly$1552$next[0:0]$2806 + end + attribute \src "libresoc.v:46874.3-46903.6" + process $proc$libresoc.v:46874$2808 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_branch0__imm_data__data[63:0] $1\fus_oper_i_alu_branch0__imm_data__data[63:0] + assign $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] + attribute \src "libresoc.v:46875.5-46875.29" + switch \initial + attribute \src "libresoc.v:46875.9-46875.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_branch0__imm_data__data[63:0] $2\fus_oper_i_alu_branch0__imm_data__data[63:0] + assign $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_branch0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_branch0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_branch0__imm_data__data[63:0] $3\fus_oper_i_alu_branch0__imm_data__data[63:0] + assign $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] $3\fus_oper_i_alu_branch0__imm_data__data[63:0] } { \dec_BRANCH_BRANCH__imm_data__ok \dec_BRANCH_BRANCH__imm_data__data } + case + assign $3\fus_oper_i_alu_branch0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_branch0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_branch0__imm_data__data $0\fus_oper_i_alu_branch0__imm_data__data[63:0] + update \fus_oper_i_alu_branch0__imm_data__ok $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] + end + attribute \src "libresoc.v:46904.3-46912.6" + process $proc$libresoc.v:46904$2809 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1568$next[0:0]$2810 $1\wr_pick_dly$1568$next[0:0]$2811 + attribute \src "libresoc.v:46905.5-46905.29" + switch \initial + attribute \src "libresoc.v:46905.9-46905.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1568$next[0:0]$2811 1'0 + case + assign $1\wr_pick_dly$1568$next[0:0]$2811 \wr_pick$1565 + end + sync always + update \wr_pick_dly$1568$next $0\wr_pick_dly$1568$next[0:0]$2810 + end + attribute \src "libresoc.v:46913.3-46921.6" + process $proc$libresoc.v:46913$2812 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1584$next[0:0]$2813 $1\wr_pick_dly$1584$next[0:0]$2814 + attribute \src "libresoc.v:46914.5-46914.29" + switch \initial + attribute \src "libresoc.v:46914.9-46914.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1584$next[0:0]$2814 1'0 + case + assign $1\wr_pick_dly$1584$next[0:0]$2814 \wr_pick$1581 + end + sync always + update \wr_pick_dly$1584$next $0\wr_pick_dly$1584$next[0:0]$2813 + end + attribute \src "libresoc.v:46922.3-46930.6" + process $proc$libresoc.v:46922$2815 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1626$next[0:0]$2816 $1\wr_pick_dly$1626$next[0:0]$2817 + attribute \src "libresoc.v:46923.5-46923.29" + switch \initial + attribute \src "libresoc.v:46923.9-46923.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1626$next[0:0]$2817 1'0 + case + assign $1\wr_pick_dly$1626$next[0:0]$2817 \wr_pick$1623 + end + sync always + update \wr_pick_dly$1626$next $0\wr_pick_dly$1626$next[0:0]$2816 + end + attribute \src "libresoc.v:46931.3-46959.6" + process $proc$libresoc.v:46931$2818 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_branch0__lk[0:0] $1\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "libresoc.v:46932.5-46932.29" + switch \initial + attribute \src "libresoc.v:46932.9-46932.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_branch0__lk[0:0] $2\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_branch0__lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_branch0__lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_branch0__lk[0:0] $3\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_branch0__lk[0:0] \dec_BRANCH_BRANCH__lk + case + assign $3\fus_oper_i_alu_branch0__lk[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_branch0__lk[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_branch0__lk $0\fus_oper_i_alu_branch0__lk[0:0] + end + attribute \src "libresoc.v:46960.3-46968.6" + process $proc$libresoc.v:46960$2819 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1645$next[0:0]$2820 $1\wr_pick_dly$1645$next[0:0]$2821 + attribute \src "libresoc.v:46961.5-46961.29" + switch \initial + attribute \src "libresoc.v:46961.9-46961.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1645$next[0:0]$2821 1'0 + case + assign $1\wr_pick_dly$1645$next[0:0]$2821 \wr_pick$1642 + end + sync always + update \wr_pick_dly$1645$next $0\wr_pick_dly$1645$next[0:0]$2820 + end + attribute \src "libresoc.v:46969.3-46997.6" + process $proc$libresoc.v:46969$2822 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_branch0__is_32bit[0:0] $1\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "libresoc.v:46970.5-46970.29" + switch \initial + attribute \src "libresoc.v:46970.9-46970.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_branch0__is_32bit[0:0] $2\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_branch0__is_32bit[0:0] $3\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_branch0__is_32bit[0:0] \dec_BRANCH_BRANCH__is_32bit + case + assign $3\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_branch0__is_32bit $0\fus_oper_i_alu_branch0__is_32bit[0:0] + end + attribute \src "libresoc.v:46998.3-47006.6" + process $proc$libresoc.v:46998$2823 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1661$next[0:0]$2824 $1\wr_pick_dly$1661$next[0:0]$2825 + attribute \src "libresoc.v:46999.5-46999.29" + switch \initial + attribute \src "libresoc.v:46999.9-46999.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1661$next[0:0]$2825 1'0 + case + assign $1\wr_pick_dly$1661$next[0:0]$2825 \wr_pick$1658 + end + sync always + update \wr_pick_dly$1661$next $0\wr_pick_dly$1661$next[0:0]$2824 + end + attribute \src "libresoc.v:47007.3-47015.6" + process $proc$libresoc.v:47007$2826 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1677$next[0:0]$2827 $1\wr_pick_dly$1677$next[0:0]$2828 + attribute \src "libresoc.v:47008.5-47008.29" + switch \initial + attribute \src "libresoc.v:47008.9-47008.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1677$next[0:0]$2828 1'0 + case + assign $1\wr_pick_dly$1677$next[0:0]$2828 \wr_pick$1674 + end + sync always + update \wr_pick_dly$1677$next $0\wr_pick_dly$1677$next[0:0]$2827 + end + attribute \src "libresoc.v:47016.3-47044.6" + process $proc$libresoc.v:47016$2829 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$14[0:0]$2830 $1\fus_cu_issue_i$14[0:0]$2831 + attribute \src "libresoc.v:47017.5-47017.29" + switch \initial + attribute \src "libresoc.v:47017.9-47017.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$14[0:0]$2831 $2\fus_cu_issue_i$14[0:0]$2832 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$14[0:0]$2832 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$14[0:0]$2832 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$14[0:0]$2832 $3\fus_cu_issue_i$14[0:0]$2833 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$14[0:0]$2833 \issue_i + case + assign $3\fus_cu_issue_i$14[0:0]$2833 1'0 + end + end + case + assign $1\fus_cu_issue_i$14[0:0]$2831 1'0 + end + sync always + update \fus_cu_issue_i$14 $0\fus_cu_issue_i$14[0:0]$2830 + end + attribute \src "libresoc.v:47045.3-47053.6" + process $proc$libresoc.v:47045$2834 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1693$next[0:0]$2835 $1\wr_pick_dly$1693$next[0:0]$2836 + attribute \src "libresoc.v:47046.5-47046.29" + switch \initial + attribute \src "libresoc.v:47046.9-47046.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1693$next[0:0]$2836 1'0 + case + assign $1\wr_pick_dly$1693$next[0:0]$2836 \wr_pick$1690 + end + sync always + update \wr_pick_dly$1693$next $0\wr_pick_dly$1693$next[0:0]$2835 + end + attribute \src "libresoc.v:47054.3-47082.6" + process $proc$libresoc.v:47054$2837 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$16[2:0]$2838 $1\fus_cu_rdmaskn_i$16[2:0]$2839 + attribute \src "libresoc.v:47055.5-47055.29" + switch \initial + attribute \src "libresoc.v:47055.9-47055.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$16[2:0]$2839 $2\fus_cu_rdmaskn_i$16[2:0]$2840 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$16[2:0]$2840 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$16[2:0]$2840 3'000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$16[2:0]$2840 $3\fus_cu_rdmaskn_i$16[2:0]$2841 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$16[2:0]$2841 \$245 + case + assign $3\fus_cu_rdmaskn_i$16[2:0]$2841 3'000 + end + end + case + assign $1\fus_cu_rdmaskn_i$16[2:0]$2839 3'000 + end + sync always + update \fus_cu_rdmaskn_i$16 $0\fus_cu_rdmaskn_i$16[2:0]$2838 + end + attribute \src "libresoc.v:47083.3-47091.6" + process $proc$libresoc.v:47083$2842 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1737$next[0:0]$2843 $1\wr_pick_dly$1737$next[0:0]$2844 + attribute \src "libresoc.v:47084.5-47084.29" + switch \initial + attribute \src "libresoc.v:47084.9-47084.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1737$next[0:0]$2844 1'0 + case + assign $1\wr_pick_dly$1737$next[0:0]$2844 \wr_pick$1734 + end + sync always + update \wr_pick_dly$1737$next $0\wr_pick_dly$1737$next[0:0]$2843 + end + attribute \src "libresoc.v:47092.3-47120.6" + process $proc$libresoc.v:47092$2845 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__insn_type[6:0] $1\fus_oper_i_alu_trap0__insn_type[6:0] + attribute \src "libresoc.v:47093.5-47093.29" + switch \initial + attribute \src "libresoc.v:47093.9-47093.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__insn_type[6:0] $2\fus_oper_i_alu_trap0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__insn_type[6:0] $3\fus_oper_i_alu_trap0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__insn_type[6:0] \core_core_insn_type + case + assign $3\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_trap0__insn_type $0\fus_oper_i_alu_trap0__insn_type[6:0] + end + attribute \src "libresoc.v:47121.3-47129.6" + process $proc$libresoc.v:47121$2846 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1753$next[0:0]$2847 $1\wr_pick_dly$1753$next[0:0]$2848 + attribute \src "libresoc.v:47122.5-47122.29" + switch \initial + attribute \src "libresoc.v:47122.9-47122.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1753$next[0:0]$2848 1'0 + case + assign $1\wr_pick_dly$1753$next[0:0]$2848 \wr_pick$1750 + end + sync always + update \wr_pick_dly$1753$next $0\wr_pick_dly$1753$next[0:0]$2847 + end + attribute \src "libresoc.v:47130.3-47138.6" + process $proc$libresoc.v:47130$2849 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1777$next[0:0]$2850 $1\wr_pick_dly$1777$next[0:0]$2851 + attribute \src "libresoc.v:47131.5-47131.29" + switch \initial + attribute \src "libresoc.v:47131.9-47131.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1777$next[0:0]$2851 1'0 + case + assign $1\wr_pick_dly$1777$next[0:0]$2851 \wr_pick$1774 + end + sync always + update \wr_pick_dly$1777$next $0\wr_pick_dly$1777$next[0:0]$2850 + end + attribute \src "libresoc.v:47139.3-47167.6" + process $proc$libresoc.v:47139$2852 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__fn_unit[11:0] $1\fus_oper_i_alu_trap0__fn_unit[11:0] + attribute \src "libresoc.v:47140.5-47140.29" + switch \initial + attribute \src "libresoc.v:47140.9-47140.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__fn_unit[11:0] $2\fus_oper_i_alu_trap0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__fn_unit[11:0] $3\fus_oper_i_alu_trap0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__fn_unit[11:0] \core_core_fn_unit + case + assign $3\fus_oper_i_alu_trap0__fn_unit[11:0] 12'000000000000 + end + end + case + assign $1\fus_oper_i_alu_trap0__fn_unit[11:0] 12'000000000000 + end + sync always + update \fus_oper_i_alu_trap0__fn_unit $0\fus_oper_i_alu_trap0__fn_unit[11:0] + end + attribute \src "libresoc.v:47168.3-47176.6" + process $proc$libresoc.v:47168$2853 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1797$next[0:0]$2854 $1\wr_pick_dly$1797$next[0:0]$2855 + attribute \src "libresoc.v:47169.5-47169.29" + switch \initial + attribute \src "libresoc.v:47169.9-47169.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1797$next[0:0]$2855 1'0 + case + assign $1\wr_pick_dly$1797$next[0:0]$2855 \wr_pick$1794 + end + sync always + update \wr_pick_dly$1797$next $0\wr_pick_dly$1797$next[0:0]$2854 + end + attribute \src "libresoc.v:47177.3-47205.6" + process $proc$libresoc.v:47177$2856 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__insn[31:0] $1\fus_oper_i_alu_trap0__insn[31:0] + attribute \src "libresoc.v:47178.5-47178.29" + switch \initial + attribute \src "libresoc.v:47178.9-47178.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__insn[31:0] $2\fus_oper_i_alu_trap0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__insn[31:0] $3\fus_oper_i_alu_trap0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__insn[31:0] \core_core_insn + case + assign $3\fus_oper_i_alu_trap0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_trap0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_trap0__insn $0\fus_oper_i_alu_trap0__insn[31:0] + end + attribute \src "libresoc.v:47206.3-47234.6" + process $proc$libresoc.v:47206$2857 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__msr[63:0] $1\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "libresoc.v:47207.5-47207.29" + switch \initial + attribute \src "libresoc.v:47207.9-47207.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__msr[63:0] $2\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__msr[63:0] $3\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__msr[63:0] \core_core_msr + case + assign $3\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + end + case + assign $1\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_oper_i_alu_trap0__msr $0\fus_oper_i_alu_trap0__msr[63:0] + end + attribute \src "libresoc.v:47235.3-47263.6" + process $proc$libresoc.v:47235$2858 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__cia[63:0] $1\fus_oper_i_alu_trap0__cia[63:0] + attribute \src "libresoc.v:47236.5-47236.29" + switch \initial + attribute \src "libresoc.v:47236.9-47236.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__cia[63:0] $2\fus_oper_i_alu_trap0__cia[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__cia[63:0] $3\fus_oper_i_alu_trap0__cia[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__cia[63:0] \core_core_cia + case + assign $3\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + end + case + assign $1\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_oper_i_alu_trap0__cia $0\fus_oper_i_alu_trap0__cia[63:0] + end + attribute \src "libresoc.v:47264.3-47292.6" + process $proc$libresoc.v:47264$2859 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__is_32bit[0:0] $1\fus_oper_i_alu_trap0__is_32bit[0:0] + attribute \src "libresoc.v:47265.5-47265.29" + switch \initial + attribute \src "libresoc.v:47265.9-47265.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__is_32bit[0:0] $2\fus_oper_i_alu_trap0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__is_32bit[0:0] $3\fus_oper_i_alu_trap0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__is_32bit[0:0] \core_core_is_32bit + case + assign $3\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_trap0__is_32bit $0\fus_oper_i_alu_trap0__is_32bit[0:0] + end + attribute \src "libresoc.v:47293.3-47321.6" + process $proc$libresoc.v:47293$2860 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__traptype[7:0] $1\fus_oper_i_alu_trap0__traptype[7:0] + attribute \src "libresoc.v:47294.5-47294.29" + switch \initial + attribute \src "libresoc.v:47294.9-47294.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__traptype[7:0] $2\fus_oper_i_alu_trap0__traptype[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__traptype[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__traptype[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__traptype[7:0] $3\fus_oper_i_alu_trap0__traptype[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__traptype[7:0] \core_core_traptype + case + assign $3\fus_oper_i_alu_trap0__traptype[7:0] 8'00000000 + end + end + case + assign $1\fus_oper_i_alu_trap0__traptype[7:0] 8'00000000 + end + sync always + update \fus_oper_i_alu_trap0__traptype $0\fus_oper_i_alu_trap0__traptype[7:0] + end + attribute \src "libresoc.v:47322.3-47350.6" + process $proc$libresoc.v:47322$2861 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__trapaddr[12:0] $1\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "libresoc.v:47323.5-47323.29" + switch \initial + attribute \src "libresoc.v:47323.9-47323.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__trapaddr[12:0] $2\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__trapaddr[12:0] $3\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__trapaddr[12:0] \core_core_trapaddr + case + assign $3\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 + end + end + case + assign $1\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 + end + sync always + update \fus_oper_i_alu_trap0__trapaddr $0\fus_oper_i_alu_trap0__trapaddr[12:0] + end + attribute \src "libresoc.v:47351.3-47379.6" + process $proc$libresoc.v:47351$2862 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__ldst_exc[7:0] $1\fus_oper_i_alu_trap0__ldst_exc[7:0] + attribute \src "libresoc.v:47352.5-47352.29" + switch \initial + attribute \src "libresoc.v:47352.9-47352.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__ldst_exc[7:0] $2\fus_oper_i_alu_trap0__ldst_exc[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__ldst_exc[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__ldst_exc[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__ldst_exc[7:0] $3\fus_oper_i_alu_trap0__ldst_exc[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__ldst_exc[7:0] { \core_core_exc_$signal$9 \core_core_exc_$signal$8 \core_core_exc_$signal$7 \core_core_exc_$signal$6 \core_core_exc_$signal$5 \core_core_exc_$signal$4 \core_core_exc_$signal$3 \core_core_exc_$signal } + case + assign $3\fus_oper_i_alu_trap0__ldst_exc[7:0] 8'00000000 + end + end + case + assign $1\fus_oper_i_alu_trap0__ldst_exc[7:0] 8'00000000 + end + sync always + update \fus_oper_i_alu_trap0__ldst_exc $0\fus_oper_i_alu_trap0__ldst_exc[7:0] + end + attribute \src "libresoc.v:47380.3-47408.6" + process $proc$libresoc.v:47380$2863 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$17[0:0]$2864 $1\fus_cu_issue_i$17[0:0]$2865 + attribute \src "libresoc.v:47381.5-47381.29" + switch \initial + attribute \src "libresoc.v:47381.9-47381.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$17[0:0]$2865 $2\fus_cu_issue_i$17[0:0]$2866 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$17[0:0]$2866 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$17[0:0]$2866 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$17[0:0]$2866 $3\fus_cu_issue_i$17[0:0]$2867 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$17[0:0]$2867 \issue_i + case + assign $3\fus_cu_issue_i$17[0:0]$2867 1'0 + end + end + case + assign $1\fus_cu_issue_i$17[0:0]$2865 1'0 + end + sync always + update \fus_cu_issue_i$17 $0\fus_cu_issue_i$17[0:0]$2864 + end + attribute \src "libresoc.v:47409.3-47437.6" + process $proc$libresoc.v:47409$2868 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$19[3:0]$2869 $1\fus_cu_rdmaskn_i$19[3:0]$2870 + attribute \src "libresoc.v:47410.5-47410.29" + switch \initial + attribute \src "libresoc.v:47410.9-47410.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$19[3:0]$2870 $2\fus_cu_rdmaskn_i$19[3:0]$2871 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$19[3:0]$2871 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$19[3:0]$2871 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$19[3:0]$2871 $3\fus_cu_rdmaskn_i$19[3:0]$2872 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$19[3:0]$2872 \$247 + case + assign $3\fus_cu_rdmaskn_i$19[3:0]$2872 4'0000 + end + end + case + assign $1\fus_cu_rdmaskn_i$19[3:0]$2870 4'0000 + end + sync always + update \fus_cu_rdmaskn_i$19 $0\fus_cu_rdmaskn_i$19[3:0]$2869 + end + attribute \src "libresoc.v:47438.3-47466.6" + process $proc$libresoc.v:47438$2873 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__insn_type[6:0] $1\fus_oper_i_alu_logical0__insn_type[6:0] + attribute \src "libresoc.v:47439.5-47439.29" + switch \initial + attribute \src "libresoc.v:47439.9-47439.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__insn_type[6:0] $2\fus_oper_i_alu_logical0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__insn_type[6:0] $3\fus_oper_i_alu_logical0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__insn_type[6:0] \dec_LOGICAL_LOGICAL__insn_type + case + assign $3\fus_oper_i_alu_logical0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_logical0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_logical0__insn_type $0\fus_oper_i_alu_logical0__insn_type[6:0] + end + attribute \src "libresoc.v:47467.3-47495.6" + process $proc$libresoc.v:47467$2874 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__fn_unit[11:0] $1\fus_oper_i_alu_logical0__fn_unit[11:0] + attribute \src "libresoc.v:47468.5-47468.29" + switch \initial + attribute \src "libresoc.v:47468.9-47468.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__fn_unit[11:0] $2\fus_oper_i_alu_logical0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__fn_unit[11:0] $3\fus_oper_i_alu_logical0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__fn_unit[11:0] \dec_LOGICAL_LOGICAL__fn_unit + case + assign $3\fus_oper_i_alu_logical0__fn_unit[11:0] 12'000000000000 + end + end + case + assign $1\fus_oper_i_alu_logical0__fn_unit[11:0] 12'000000000000 + end + sync always + update \fus_oper_i_alu_logical0__fn_unit $0\fus_oper_i_alu_logical0__fn_unit[11:0] + end + attribute \src "libresoc.v:47496.3-47525.6" + process $proc$libresoc.v:47496$2875 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__imm_data__data[63:0] $1\fus_oper_i_alu_logical0__imm_data__data[63:0] + assign $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] + attribute \src "libresoc.v:47497.5-47497.29" + switch \initial + attribute \src "libresoc.v:47497.9-47497.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_logical0__imm_data__data[63:0] $2\fus_oper_i_alu_logical0__imm_data__data[63:0] + assign $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_logical0__imm_data__data[63:0] $3\fus_oper_i_alu_logical0__imm_data__data[63:0] + assign $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] $3\fus_oper_i_alu_logical0__imm_data__data[63:0] } { \dec_LOGICAL_LOGICAL__imm_data__ok \dec_LOGICAL_LOGICAL__imm_data__data } + case + assign $3\fus_oper_i_alu_logical0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__imm_data__data $0\fus_oper_i_alu_logical0__imm_data__data[63:0] + update \fus_oper_i_alu_logical0__imm_data__ok $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] + end + attribute \src "libresoc.v:47526.3-47555.6" + process $proc$libresoc.v:47526$2876 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__rc__ok[0:0] $1\fus_oper_i_alu_logical0__rc__ok[0:0] + assign $0\fus_oper_i_alu_logical0__rc__rc[0:0] $1\fus_oper_i_alu_logical0__rc__rc[0:0] + attribute \src "libresoc.v:47527.5-47527.29" + switch \initial + attribute \src "libresoc.v:47527.9-47527.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_logical0__rc__ok[0:0] $2\fus_oper_i_alu_logical0__rc__ok[0:0] + assign $1\fus_oper_i_alu_logical0__rc__rc[0:0] $2\fus_oper_i_alu_logical0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_logical0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_logical0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_logical0__rc__ok[0:0] $3\fus_oper_i_alu_logical0__rc__ok[0:0] + assign $2\fus_oper_i_alu_logical0__rc__rc[0:0] $3\fus_oper_i_alu_logical0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_logical0__rc__ok[0:0] $3\fus_oper_i_alu_logical0__rc__rc[0:0] } { \dec_LOGICAL_LOGICAL__rc__ok \dec_LOGICAL_LOGICAL__rc__rc } + case + assign $3\fus_oper_i_alu_logical0__rc__ok[0:0] 1'0 + assign $3\fus_oper_i_alu_logical0__rc__rc[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__rc__ok[0:0] 1'0 + assign $1\fus_oper_i_alu_logical0__rc__rc[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__rc__ok $0\fus_oper_i_alu_logical0__rc__ok[0:0] + update \fus_oper_i_alu_logical0__rc__rc $0\fus_oper_i_alu_logical0__rc__rc[0:0] + end + attribute \src "libresoc.v:47556.3-47585.6" + process $proc$libresoc.v:47556$2877 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__oe__oe[0:0] $1\fus_oper_i_alu_logical0__oe__oe[0:0] + assign $0\fus_oper_i_alu_logical0__oe__ok[0:0] $1\fus_oper_i_alu_logical0__oe__ok[0:0] + attribute \src "libresoc.v:47557.5-47557.29" + switch \initial + attribute \src "libresoc.v:47557.9-47557.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_logical0__oe__oe[0:0] $2\fus_oper_i_alu_logical0__oe__oe[0:0] + assign $1\fus_oper_i_alu_logical0__oe__ok[0:0] $2\fus_oper_i_alu_logical0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_logical0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_logical0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_logical0__oe__oe[0:0] $3\fus_oper_i_alu_logical0__oe__oe[0:0] + assign $2\fus_oper_i_alu_logical0__oe__ok[0:0] $3\fus_oper_i_alu_logical0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_logical0__oe__ok[0:0] $3\fus_oper_i_alu_logical0__oe__oe[0:0] } { \dec_LOGICAL_LOGICAL__oe__ok \dec_LOGICAL_LOGICAL__oe__oe } + case + assign $3\fus_oper_i_alu_logical0__oe__oe[0:0] 1'0 + assign $3\fus_oper_i_alu_logical0__oe__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__oe__oe[0:0] 1'0 + assign $1\fus_oper_i_alu_logical0__oe__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__oe__oe $0\fus_oper_i_alu_logical0__oe__oe[0:0] + update \fus_oper_i_alu_logical0__oe__ok $0\fus_oper_i_alu_logical0__oe__ok[0:0] + end + attribute \src "libresoc.v:47586.3-47614.6" + process $proc$libresoc.v:47586$2878 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__invert_in[0:0] $1\fus_oper_i_alu_logical0__invert_in[0:0] + attribute \src "libresoc.v:47587.5-47587.29" + switch \initial + attribute \src "libresoc.v:47587.9-47587.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__invert_in[0:0] $2\fus_oper_i_alu_logical0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__invert_in[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__invert_in[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__invert_in[0:0] $3\fus_oper_i_alu_logical0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__invert_in[0:0] \dec_LOGICAL_LOGICAL__invert_in + case + assign $3\fus_oper_i_alu_logical0__invert_in[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__invert_in[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__invert_in $0\fus_oper_i_alu_logical0__invert_in[0:0] + end + attribute \src "libresoc.v:47615.3-47643.6" + process $proc$libresoc.v:47615$2879 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__zero_a[0:0] $1\fus_oper_i_alu_logical0__zero_a[0:0] + attribute \src "libresoc.v:47616.5-47616.29" + switch \initial + attribute \src "libresoc.v:47616.9-47616.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__zero_a[0:0] $2\fus_oper_i_alu_logical0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__zero_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__zero_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__zero_a[0:0] $3\fus_oper_i_alu_logical0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__zero_a[0:0] \dec_LOGICAL_LOGICAL__zero_a + case + assign $3\fus_oper_i_alu_logical0__zero_a[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__zero_a[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__zero_a $0\fus_oper_i_alu_logical0__zero_a[0:0] + end + attribute \src "libresoc.v:47644.3-47672.6" + process $proc$libresoc.v:47644$2880 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__input_carry[1:0] $1\fus_oper_i_alu_logical0__input_carry[1:0] + attribute \src "libresoc.v:47645.5-47645.29" + switch \initial + attribute \src "libresoc.v:47645.9-47645.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__input_carry[1:0] $2\fus_oper_i_alu_logical0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__input_carry[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__input_carry[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__input_carry[1:0] $3\fus_oper_i_alu_logical0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__input_carry[1:0] \dec_LOGICAL_LOGICAL__input_carry + case + assign $3\fus_oper_i_alu_logical0__input_carry[1:0] 2'00 + end + end + case + assign $1\fus_oper_i_alu_logical0__input_carry[1:0] 2'00 + end + sync always + update \fus_oper_i_alu_logical0__input_carry $0\fus_oper_i_alu_logical0__input_carry[1:0] + end + attribute \src "libresoc.v:47673.3-47701.6" + process $proc$libresoc.v:47673$2881 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__invert_out[0:0] $1\fus_oper_i_alu_logical0__invert_out[0:0] + attribute \src "libresoc.v:47674.5-47674.29" + switch \initial + attribute \src "libresoc.v:47674.9-47674.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__invert_out[0:0] $2\fus_oper_i_alu_logical0__invert_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__invert_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__invert_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__invert_out[0:0] $3\fus_oper_i_alu_logical0__invert_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__invert_out[0:0] \dec_LOGICAL_LOGICAL__invert_out + case + assign $3\fus_oper_i_alu_logical0__invert_out[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__invert_out[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__invert_out $0\fus_oper_i_alu_logical0__invert_out[0:0] + end + attribute \src "libresoc.v:47702.3-47730.6" + process $proc$libresoc.v:47702$2882 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__write_cr0[0:0] $1\fus_oper_i_alu_logical0__write_cr0[0:0] + attribute \src "libresoc.v:47703.5-47703.29" + switch \initial + attribute \src "libresoc.v:47703.9-47703.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__write_cr0[0:0] $2\fus_oper_i_alu_logical0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__write_cr0[0:0] $3\fus_oper_i_alu_logical0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__write_cr0[0:0] \dec_LOGICAL_LOGICAL__write_cr0 + case + assign $3\fus_oper_i_alu_logical0__write_cr0[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__write_cr0[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__write_cr0 $0\fus_oper_i_alu_logical0__write_cr0[0:0] + end + attribute \src "libresoc.v:47731.3-47759.6" + process $proc$libresoc.v:47731$2883 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__output_carry[0:0] $1\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "libresoc.v:47732.5-47732.29" + switch \initial + attribute \src "libresoc.v:47732.9-47732.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__output_carry[0:0] $2\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__output_carry[0:0] $3\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__output_carry[0:0] \dec_LOGICAL_LOGICAL__output_carry + case + assign $3\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__output_carry $0\fus_oper_i_alu_logical0__output_carry[0:0] + end + attribute \src "libresoc.v:47760.3-47788.6" + process $proc$libresoc.v:47760$2884 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__is_32bit[0:0] $1\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "libresoc.v:47761.5-47761.29" + switch \initial + attribute \src "libresoc.v:47761.9-47761.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__is_32bit[0:0] $2\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] $3\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__is_32bit[0:0] \dec_LOGICAL_LOGICAL__is_32bit + case + assign $3\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__is_32bit $0\fus_oper_i_alu_logical0__is_32bit[0:0] + end + attribute \src "libresoc.v:47789.3-47817.6" + process $proc$libresoc.v:47789$2885 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__is_signed[0:0] $1\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "libresoc.v:47790.5-47790.29" + switch \initial + attribute \src "libresoc.v:47790.9-47790.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__is_signed[0:0] $2\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__is_signed[0:0] $3\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__is_signed[0:0] \dec_LOGICAL_LOGICAL__is_signed + case + assign $3\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__is_signed $0\fus_oper_i_alu_logical0__is_signed[0:0] + end + attribute \src "libresoc.v:47818.3-47846.6" + process $proc$libresoc.v:47818$2886 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__data_len[3:0] $1\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "libresoc.v:47819.5-47819.29" + switch \initial + attribute \src "libresoc.v:47819.9-47819.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__data_len[3:0] $2\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__data_len[3:0] $3\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__data_len[3:0] \dec_LOGICAL_LOGICAL__data_len + case + assign $3\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 + end + end + case + assign $1\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 + end + sync always + update \fus_oper_i_alu_logical0__data_len $0\fus_oper_i_alu_logical0__data_len[3:0] + end + attribute \src "libresoc.v:47847.3-47875.6" + process $proc$libresoc.v:47847$2887 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__insn[31:0] $1\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "libresoc.v:47848.5-47848.29" + switch \initial + attribute \src "libresoc.v:47848.9-47848.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__insn[31:0] $2\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__insn[31:0] $3\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__insn[31:0] \dec_LOGICAL_LOGICAL__insn + case + assign $3\fus_oper_i_alu_logical0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_logical0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_logical0__insn $0\fus_oper_i_alu_logical0__insn[31:0] + end + attribute \src "libresoc.v:47876.3-47904.6" + process $proc$libresoc.v:47876$2888 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$20[0:0]$2889 $1\fus_cu_issue_i$20[0:0]$2890 + attribute \src "libresoc.v:47877.5-47877.29" + switch \initial + attribute \src "libresoc.v:47877.9-47877.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$20[0:0]$2890 $2\fus_cu_issue_i$20[0:0]$2891 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$20[0:0]$2891 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$20[0:0]$2891 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$20[0:0]$2891 $3\fus_cu_issue_i$20[0:0]$2892 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$20[0:0]$2892 \issue_i + case + assign $3\fus_cu_issue_i$20[0:0]$2892 1'0 + end + end + case + assign $1\fus_cu_issue_i$20[0:0]$2890 1'0 + end + sync always + update \fus_cu_issue_i$20 $0\fus_cu_issue_i$20[0:0]$2889 + end + attribute \src "libresoc.v:47905.3-47933.6" + process $proc$libresoc.v:47905$2893 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$22[2:0]$2894 $1\fus_cu_rdmaskn_i$22[2:0]$2895 + attribute \src "libresoc.v:47906.5-47906.29" + switch \initial + attribute \src "libresoc.v:47906.9-47906.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$22[2:0]$2895 $2\fus_cu_rdmaskn_i$22[2:0]$2896 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$22[2:0]$2896 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$22[2:0]$2896 3'000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$22[2:0]$2896 $3\fus_cu_rdmaskn_i$22[2:0]$2897 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$22[2:0]$2897 \$249 + case + assign $3\fus_cu_rdmaskn_i$22[2:0]$2897 3'000 + end + end + case + assign $1\fus_cu_rdmaskn_i$22[2:0]$2895 3'000 + end + sync always + update \fus_cu_rdmaskn_i$22 $0\fus_cu_rdmaskn_i$22[2:0]$2894 + end + attribute \src "libresoc.v:47934.3-47962.6" + process $proc$libresoc.v:47934$2898 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_spr0__insn_type[6:0] $1\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "libresoc.v:47935.5-47935.29" + switch \initial + attribute \src "libresoc.v:47935.9-47935.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_spr0__insn_type[6:0] $2\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_spr0__insn_type[6:0] $3\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_spr0__insn_type[6:0] \dec_SPR_SPR__insn_type + case + assign $3\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_spr0__insn_type $0\fus_oper_i_alu_spr0__insn_type[6:0] + end + attribute \src "libresoc.v:47963.3-47991.6" + process $proc$libresoc.v:47963$2899 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_spr0__fn_unit[11:0] $1\fus_oper_i_alu_spr0__fn_unit[11:0] + attribute \src "libresoc.v:47964.5-47964.29" + switch \initial + attribute \src "libresoc.v:47964.9-47964.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_spr0__fn_unit[11:0] $2\fus_oper_i_alu_spr0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_spr0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_spr0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_spr0__fn_unit[11:0] $3\fus_oper_i_alu_spr0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_spr0__fn_unit[11:0] \dec_SPR_SPR__fn_unit + case + assign $3\fus_oper_i_alu_spr0__fn_unit[11:0] 12'000000000000 + end + end + case + assign $1\fus_oper_i_alu_spr0__fn_unit[11:0] 12'000000000000 + end + sync always + update \fus_oper_i_alu_spr0__fn_unit $0\fus_oper_i_alu_spr0__fn_unit[11:0] + end + connect \$1002 $not$libresoc.v:41533$1506_Y + connect \$1004 $and$libresoc.v:41534$1507_Y + connect \$1011 $and$libresoc.v:41535$1508_Y + connect \$1014 $ternary$libresoc.v:41536$1509_Y + connect \$1016 $and$libresoc.v:41537$1510_Y + connect \$1019 $and$libresoc.v:41538$1511_Y + connect \$1023 $not$libresoc.v:41539$1512_Y + connect \$1025 $and$libresoc.v:41540$1513_Y + connect \$1029 $and$libresoc.v:41541$1514_Y + connect \$1032 $ternary$libresoc.v:41542$1515_Y + connect \$1034 $and$libresoc.v:41543$1516_Y + connect \$1037 $and$libresoc.v:41544$1517_Y + connect \$1041 $not$libresoc.v:41545$1518_Y + connect \$1043 $and$libresoc.v:41546$1519_Y + connect \$1051 $and$libresoc.v:41547$1520_Y + connect \$1054 $ternary$libresoc.v:41548$1521_Y + connect \$1056 $and$libresoc.v:41549$1522_Y + connect \$1059 $and$libresoc.v:41550$1523_Y + connect \$1063 $not$libresoc.v:41551$1524_Y + connect \$1065 $and$libresoc.v:41552$1525_Y + connect \$1071 $and$libresoc.v:41553$1526_Y + connect \$1074 $ternary$libresoc.v:41554$1527_Y + connect \$1076 $and$libresoc.v:41555$1528_Y + connect \$1079 $and$libresoc.v:41556$1529_Y + connect \$1083 $not$libresoc.v:41557$1530_Y + connect \$1085 $and$libresoc.v:41558$1531_Y + connect \$1091 $and$libresoc.v:41559$1532_Y + connect \$1094 $ternary$libresoc.v:41560$1533_Y + connect \$1096 $and$libresoc.v:41561$1534_Y + connect \$1099 $and$libresoc.v:41562$1535_Y + connect \$1103 $not$libresoc.v:41563$1536_Y + connect \$1105 $and$libresoc.v:41564$1537_Y + connect \$1110 $and$libresoc.v:41565$1538_Y + connect \$1113 $ternary$libresoc.v:41566$1539_Y + connect \$1115 $and$libresoc.v:41567$1540_Y + connect \$1118 $and$libresoc.v:41568$1541_Y + connect \$1122 $not$libresoc.v:41569$1542_Y + connect \$1124 $and$libresoc.v:41570$1543_Y + connect \$1128 $and$libresoc.v:41571$1544_Y + connect \$1131 $ternary$libresoc.v:41572$1545_Y + connect \$1133 $and$libresoc.v:41573$1546_Y + connect \$1136 $and$libresoc.v:41574$1547_Y + connect \$1139 $not$libresoc.v:41575$1548_Y + connect \$1141 $and$libresoc.v:41576$1549_Y + connect \$1144 $and$libresoc.v:41577$1550_Y + connect \$1147 $ternary$libresoc.v:41578$1551_Y + connect \$1150 $or$libresoc.v:41579$1552_Y + connect \$1152 $or$libresoc.v:41580$1553_Y + connect \$1154 $or$libresoc.v:41581$1554_Y + connect \$1156 $or$libresoc.v:41582$1555_Y + connect \$1158 $or$libresoc.v:41583$1556_Y + connect \$1160 $or$libresoc.v:41584$1557_Y + connect \$1162 $or$libresoc.v:41585$1558_Y + connect \$1164 $or$libresoc.v:41586$1559_Y + connect \$1166 $or$libresoc.v:41587$1560_Y + connect \$1168 $or$libresoc.v:41588$1561_Y + connect \$1170 $or$libresoc.v:41589$1562_Y + connect \$1172 $or$libresoc.v:41590$1563_Y + connect \$1174 $or$libresoc.v:41591$1564_Y + connect \$1176 $or$libresoc.v:41592$1565_Y + connect \$1178 $or$libresoc.v:41593$1566_Y + connect \$1180 $or$libresoc.v:41594$1567_Y + connect \$1182 $or$libresoc.v:41595$1568_Y + connect \$1184 $or$libresoc.v:41596$1569_Y + connect \$1186 $or$libresoc.v:41597$1570_Y + connect \$1188 $or$libresoc.v:41598$1571_Y + connect \$1190 $or$libresoc.v:41599$1572_Y + connect \$1192 $or$libresoc.v:41600$1573_Y + connect \$1194 $or$libresoc.v:41601$1574_Y + connect \$1196 $or$libresoc.v:41602$1575_Y + connect \$1198 $or$libresoc.v:41603$1576_Y + connect \$1200 $or$libresoc.v:41604$1577_Y + connect \$1202 $or$libresoc.v:41605$1578_Y + connect \$1204 $and$libresoc.v:41606$1579_Y + connect \$1206 $and$libresoc.v:41607$1580_Y + connect \$1209 $and$libresoc.v:41608$1581_Y + connect \$1212 $not$libresoc.v:41609$1582_Y + connect \$1214 $and$libresoc.v:41610$1583_Y + connect \$1217 $and$libresoc.v:41611$1584_Y + connect \$1220 $ternary$libresoc.v:41612$1585_Y + connect \$1222 $and$libresoc.v:41613$1586_Y + connect \$1224 $and$libresoc.v:41614$1587_Y + connect \$1226 $and$libresoc.v:41615$1588_Y + connect \$1228 $and$libresoc.v:41616$1589_Y + connect \$1230 $and$libresoc.v:41617$1590_Y + connect \$1232 $and$libresoc.v:41618$1591_Y + connect \$1234 $and$libresoc.v:41619$1592_Y + connect \$1237 $and$libresoc.v:41620$1593_Y + connect \$1240 $not$libresoc.v:41621$1594_Y + connect \$1242 $and$libresoc.v:41622$1595_Y + connect \$1245 $and$libresoc.v:41623$1596_Y + connect \$1248 $sub$libresoc.v:41624$1597_Y + connect \$1250 $sshl$libresoc.v:41625$1598_Y + connect \$1252 $ternary$libresoc.v:41626$1599_Y + connect \$1254 $and$libresoc.v:41627$1600_Y + connect \$1257 $and$libresoc.v:41628$1601_Y + connect \$1260 $not$libresoc.v:41629$1602_Y + connect \$1262 $and$libresoc.v:41630$1603_Y + connect \$1265 $and$libresoc.v:41631$1604_Y + connect \$1268 $sub$libresoc.v:41632$1605_Y + connect \$1270 $sshl$libresoc.v:41633$1606_Y + connect \$1272 $ternary$libresoc.v:41634$1607_Y + connect \$1274 $and$libresoc.v:41635$1608_Y + connect \$1277 $and$libresoc.v:41636$1609_Y + connect \$1280 $not$libresoc.v:41637$1610_Y + connect \$1282 $and$libresoc.v:41638$1611_Y + connect \$1285 $and$libresoc.v:41639$1612_Y + connect \$1288 $sub$libresoc.v:41640$1613_Y + connect \$1290 $sshl$libresoc.v:41641$1614_Y + connect \$1292 $ternary$libresoc.v:41642$1615_Y + connect \$1294 $and$libresoc.v:41643$1616_Y + connect \$1297 $and$libresoc.v:41644$1617_Y + connect \$1300 $not$libresoc.v:41645$1618_Y + connect \$1302 $and$libresoc.v:41646$1619_Y + connect \$1305 $and$libresoc.v:41647$1620_Y + connect \$1308 $sub$libresoc.v:41648$1621_Y + connect \$1310 $sshl$libresoc.v:41649$1622_Y + connect \$1312 $ternary$libresoc.v:41650$1623_Y + connect \$1314 $and$libresoc.v:41651$1624_Y + connect \$1317 $and$libresoc.v:41652$1625_Y + connect \$1320 $not$libresoc.v:41653$1626_Y + connect \$1322 $and$libresoc.v:41654$1627_Y + connect \$1325 $and$libresoc.v:41655$1628_Y + connect \$1328 $sub$libresoc.v:41656$1629_Y + connect \$1330 $sshl$libresoc.v:41657$1630_Y + connect \$1332 $ternary$libresoc.v:41658$1631_Y + connect \$1334 $and$libresoc.v:41659$1632_Y + connect \$1337 $and$libresoc.v:41660$1633_Y + connect \$1340 $not$libresoc.v:41661$1634_Y + connect \$1342 $and$libresoc.v:41662$1635_Y + connect \$1345 $and$libresoc.v:41663$1636_Y + connect \$1348 $sub$libresoc.v:41664$1637_Y + connect \$1350 $sshl$libresoc.v:41665$1638_Y + connect \$1352 $ternary$libresoc.v:41666$1639_Y + connect \$1354 $or$libresoc.v:41667$1640_Y + connect \$1356 $or$libresoc.v:41668$1641_Y + connect \$1358 $or$libresoc.v:41669$1642_Y + connect \$1360 $or$libresoc.v:41670$1643_Y + connect \$1362 $or$libresoc.v:41671$1644_Y + connect \$1365 $or$libresoc.v:41672$1645_Y + connect \$1367 $or$libresoc.v:41673$1646_Y + connect \$1369 $or$libresoc.v:41674$1647_Y + connect \$1371 $or$libresoc.v:41675$1648_Y + connect \$1373 $or$libresoc.v:41676$1649_Y + connect \$1375 $and$libresoc.v:41677$1650_Y + connect \$1377 $and$libresoc.v:41678$1651_Y + connect \$1379 $and$libresoc.v:41679$1652_Y + connect \$1381 $and$libresoc.v:41680$1653_Y + connect \$1384 $and$libresoc.v:41681$1654_Y + connect \$1387 $not$libresoc.v:41682$1655_Y + connect \$1389 $and$libresoc.v:41683$1656_Y + connect \$1392 $and$libresoc.v:41684$1657_Y + connect \$1395 $ternary$libresoc.v:41685$1658_Y + connect \$1397 $and$libresoc.v:41686$1659_Y + connect \$1400 $and$libresoc.v:41687$1660_Y + connect \$1403 $not$libresoc.v:41688$1661_Y + connect \$1405 $and$libresoc.v:41689$1662_Y + connect \$1408 $and$libresoc.v:41690$1663_Y + connect \$1411 $ternary$libresoc.v:41691$1664_Y + connect \$1413 $and$libresoc.v:41692$1665_Y + connect \$1416 $and$libresoc.v:41693$1666_Y + connect \$1419 $not$libresoc.v:41694$1667_Y + connect \$1421 $and$libresoc.v:41695$1668_Y + connect \$1424 $and$libresoc.v:41696$1669_Y + connect \$1427 $ternary$libresoc.v:41697$1670_Y + connect \$1429 $or$libresoc.v:41698$1671_Y + connect \$1431 $or$libresoc.v:41699$1672_Y + connect \$1434 $or$libresoc.v:41700$1673_Y + connect \$1436 $or$libresoc.v:41701$1674_Y + connect \$1433 $pos$libresoc.v:41702$1676_Y + connect \$1439 $and$libresoc.v:41703$1677_Y + connect \$1441 $and$libresoc.v:41704$1678_Y + connect \$1443 $and$libresoc.v:41705$1679_Y + connect \$1445 $and$libresoc.v:41706$1680_Y + connect \$1447 $and$libresoc.v:41707$1681_Y + connect \$1450 $and$libresoc.v:41708$1682_Y + connect \$1453 $not$libresoc.v:41709$1683_Y + connect \$1455 $and$libresoc.v:41710$1684_Y + connect \$1458 $and$libresoc.v:41711$1685_Y + connect \$1461 $ternary$libresoc.v:41712$1686_Y + connect \$1463 $and$libresoc.v:41713$1687_Y + connect \$1466 $and$libresoc.v:41714$1688_Y + connect \$1469 $not$libresoc.v:41715$1689_Y + connect \$1471 $and$libresoc.v:41716$1690_Y + connect \$1474 $and$libresoc.v:41717$1691_Y + connect \$1477 $ternary$libresoc.v:41718$1692_Y + connect \$1479 $and$libresoc.v:41719$1693_Y + connect \$1482 $and$libresoc.v:41720$1694_Y + connect \$1485 $not$libresoc.v:41721$1695_Y + connect \$1487 $and$libresoc.v:41722$1696_Y + connect \$1490 $and$libresoc.v:41723$1697_Y + connect \$1493 $ternary$libresoc.v:41724$1698_Y + connect \$1495 $and$libresoc.v:41725$1699_Y + connect \$1498 $and$libresoc.v:41726$1700_Y + connect \$1501 $not$libresoc.v:41727$1701_Y + connect \$1503 $and$libresoc.v:41728$1702_Y + connect \$1506 $and$libresoc.v:41729$1703_Y + connect \$1509 $ternary$libresoc.v:41730$1704_Y + connect \$1511 $or$libresoc.v:41731$1705_Y + connect \$1513 $or$libresoc.v:41732$1706_Y + connect \$1515 $or$libresoc.v:41733$1707_Y + connect \$1517 $or$libresoc.v:41734$1708_Y + connect \$1519 $or$libresoc.v:41735$1709_Y + connect \$1521 $or$libresoc.v:41736$1710_Y + connect \$1523 $and$libresoc.v:41737$1711_Y + connect \$1525 $and$libresoc.v:41738$1712_Y + connect \$1527 $and$libresoc.v:41739$1713_Y + connect \$1529 $and$libresoc.v:41740$1714_Y + connect \$1531 $and$libresoc.v:41741$1715_Y + connect \$1534 $and$libresoc.v:41742$1716_Y + connect \$1537 $not$libresoc.v:41743$1717_Y + connect \$1539 $and$libresoc.v:41744$1718_Y + connect \$1542 $and$libresoc.v:41745$1719_Y + connect \$1545 $ternary$libresoc.v:41746$1720_Y + connect \$1547 $and$libresoc.v:41747$1721_Y + connect \$1550 $and$libresoc.v:41748$1722_Y + connect \$1553 $not$libresoc.v:41749$1723_Y + connect \$1555 $and$libresoc.v:41750$1724_Y + connect \$1558 $and$libresoc.v:41751$1725_Y + connect \$1561 $ternary$libresoc.v:41752$1726_Y + connect \$1563 $and$libresoc.v:41753$1727_Y + connect \$1566 $and$libresoc.v:41754$1728_Y + connect \$1569 $not$libresoc.v:41755$1729_Y + connect \$1571 $and$libresoc.v:41756$1730_Y + connect \$1574 $and$libresoc.v:41757$1731_Y + connect \$1577 $ternary$libresoc.v:41758$1732_Y + connect \$1579 $and$libresoc.v:41759$1733_Y + connect \$1582 $and$libresoc.v:41760$1734_Y + connect \$1585 $not$libresoc.v:41761$1735_Y + connect \$1587 $and$libresoc.v:41762$1736_Y + connect \$1590 $and$libresoc.v:41763$1737_Y + connect \$1593 $ternary$libresoc.v:41764$1738_Y + connect \$1596 $or$libresoc.v:41765$1739_Y + connect \$1598 $or$libresoc.v:41766$1740_Y + connect \$1600 $or$libresoc.v:41767$1741_Y + connect \$1595 $pos$libresoc.v:41768$1743_Y + connect \$1604 $or$libresoc.v:41769$1744_Y + connect \$1606 $or$libresoc.v:41770$1745_Y + connect \$1608 $or$libresoc.v:41771$1746_Y + connect \$1603 $pos$libresoc.v:41772$1748_Y + connect \$1611 $and$libresoc.v:41773$1749_Y + connect \$1613 $and$libresoc.v:41774$1750_Y + connect \$1615 $and$libresoc.v:41775$1751_Y + connect \$1617 $and$libresoc.v:41776$1752_Y + connect \$1619 $and$libresoc.v:41777$1753_Y + connect \$1621 $and$libresoc.v:41778$1754_Y + connect \$1624 $and$libresoc.v:41779$1755_Y + connect \$1628 $not$libresoc.v:41780$1756_Y + connect \$1630 $and$libresoc.v:41781$1757_Y + connect \$1635 $and$libresoc.v:41782$1758_Y + connect \$1638 $ternary$libresoc.v:41783$1759_Y + connect \$1640 $and$libresoc.v:41784$1760_Y + connect \$1643 $and$libresoc.v:41785$1761_Y + connect \$1646 $not$libresoc.v:41786$1762_Y + connect \$1648 $and$libresoc.v:41787$1763_Y + connect \$1651 $and$libresoc.v:41788$1764_Y + connect \$1654 $ternary$libresoc.v:41789$1765_Y + connect \$1656 $and$libresoc.v:41790$1766_Y + connect \$1659 $and$libresoc.v:41791$1767_Y + connect \$1662 $not$libresoc.v:41792$1768_Y + connect \$1664 $and$libresoc.v:41793$1769_Y + connect \$1667 $and$libresoc.v:41794$1770_Y + connect \$1670 $ternary$libresoc.v:41795$1771_Y + connect \$1672 $and$libresoc.v:41796$1772_Y + connect \$1675 $and$libresoc.v:41797$1773_Y + connect \$1678 $not$libresoc.v:41798$1774_Y + connect \$1680 $and$libresoc.v:41799$1775_Y + connect \$1683 $and$libresoc.v:41800$1776_Y + connect \$1686 $ternary$libresoc.v:41801$1777_Y + connect \$1688 $and$libresoc.v:41802$1778_Y + connect \$1691 $and$libresoc.v:41803$1779_Y + connect \$1694 $not$libresoc.v:41804$1780_Y + connect \$1696 $and$libresoc.v:41805$1781_Y + connect \$1699 $and$libresoc.v:41806$1782_Y + connect \$1702 $ternary$libresoc.v:41807$1783_Y + connect \$1704 $or$libresoc.v:41808$1784_Y + connect \$1706 $or$libresoc.v:41809$1785_Y + connect \$1708 $or$libresoc.v:41810$1786_Y + connect \$1710 $or$libresoc.v:41811$1787_Y + connect \$1712 $or$libresoc.v:41812$1788_Y + connect \$1714 $or$libresoc.v:41813$1789_Y + connect \$1716 $or$libresoc.v:41814$1790_Y + connect \$1718 $or$libresoc.v:41815$1791_Y + connect \$1720 $or$libresoc.v:41816$1792_Y + connect \$1722 $or$libresoc.v:41817$1793_Y + connect \$1724 $or$libresoc.v:41818$1794_Y + connect \$1726 $or$libresoc.v:41819$1795_Y + connect \$1728 $and$libresoc.v:41820$1796_Y + connect \$1730 $and$libresoc.v:41821$1797_Y + connect \$1732 $and$libresoc.v:41822$1798_Y + connect \$1735 $and$libresoc.v:41823$1799_Y + connect \$1738 $not$libresoc.v:41824$1800_Y + connect \$1740 $and$libresoc.v:41825$1801_Y + connect \$1743 $and$libresoc.v:41826$1802_Y + connect \$1746 $ternary$libresoc.v:41827$1803_Y + connect \$1748 $and$libresoc.v:41828$1804_Y + connect \$1751 $and$libresoc.v:41829$1805_Y + connect \$1754 $not$libresoc.v:41830$1806_Y + connect \$1756 $and$libresoc.v:41831$1807_Y + connect \$175 $and$libresoc.v:41832$1808_Y + connect \$1759 $and$libresoc.v:41833$1809_Y + connect \$1762 $ternary$libresoc.v:41834$1810_Y + connect \$1764 $or$libresoc.v:41835$1811_Y + connect \$1767 $or$libresoc.v:41836$1812_Y + connect \$1766 $pos$libresoc.v:41837$1814_Y + connect \$174 $reduce_or$libresoc.v:41838$1815_Y + connect \$1770 $and$libresoc.v:41839$1816_Y + connect \$1772 $and$libresoc.v:41840$1817_Y + connect \$1775 $and$libresoc.v:41841$1818_Y + connect \$1778 $not$libresoc.v:41842$1819_Y + connect \$1780 $and$libresoc.v:41843$1820_Y + connect \$1783 $and$libresoc.v:41844$1821_Y + connect \$1786 $ternary$libresoc.v:41845$1822_Y + connect \$1788 $pos$libresoc.v:41846$1824_Y + connect \$1790 $and$libresoc.v:41847$1825_Y + connect \$1792 $and$libresoc.v:41848$1826_Y + connect \$1795 $and$libresoc.v:41849$1827_Y + connect \$1798 $not$libresoc.v:41850$1828_Y + connect \$179 $and$libresoc.v:41851$1829_Y + connect \$1800 $and$libresoc.v:41852$1830_Y + connect \$1803 $and$libresoc.v:41853$1831_Y + connect \$1806 $ternary$libresoc.v:41854$1832_Y + connect \$178 $reduce_or$libresoc.v:41855$1833_Y + connect \$183 $and$libresoc.v:41856$1834_Y + connect \$182 $reduce_or$libresoc.v:41857$1835_Y + connect \$187 $and$libresoc.v:41858$1836_Y + connect \$186 $reduce_or$libresoc.v:41859$1837_Y + connect \$191 $and$libresoc.v:41860$1838_Y + connect \$190 $reduce_or$libresoc.v:41861$1839_Y + connect \$195 $and$libresoc.v:41862$1840_Y + connect \$194 $reduce_or$libresoc.v:41863$1841_Y + connect \$199 $and$libresoc.v:41864$1842_Y + connect \$198 $reduce_or$libresoc.v:41865$1843_Y + connect \$203 $and$libresoc.v:41866$1844_Y + connect \$202 $reduce_or$libresoc.v:41867$1845_Y + connect \$207 $and$libresoc.v:41868$1846_Y + connect \$206 $reduce_or$libresoc.v:41869$1847_Y + connect \$211 $and$libresoc.v:41870$1848_Y + connect \$210 $reduce_or$libresoc.v:41871$1849_Y + connect \$214 $ne$libresoc.v:41872$1850_Y + connect \$217 $sub$libresoc.v:41873$1851_Y + connect \$219 $ne$libresoc.v:41874$1852_Y + connect \$222 $and$libresoc.v:41875$1853_Y + connect \$224 $and$libresoc.v:41876$1854_Y + connect \$226 $eq$libresoc.v:41877$1855_Y + connect \$228 $or$libresoc.v:41878$1856_Y + connect \$230 $and$libresoc.v:41879$1857_Y + connect \$232 $or$libresoc.v:41880$1858_Y + connect \$234 $eq$libresoc.v:41881$1859_Y + connect \$236 $and$libresoc.v:41882$1860_Y + connect \$238 $eq$libresoc.v:41883$1861_Y + connect \$240 $or$libresoc.v:41884$1862_Y + connect \$221 $not$libresoc.v:41885$1863_Y + connect \$243 $not$libresoc.v:41886$1864_Y + connect \$245 $not$libresoc.v:41887$1865_Y + connect \$247 $not$libresoc.v:41888$1866_Y + connect \$250 $and$libresoc.v:41889$1867_Y + connect \$252 $and$libresoc.v:41890$1868_Y + connect \$254 $eq$libresoc.v:41891$1869_Y + connect \$256 $or$libresoc.v:41892$1870_Y + connect \$258 $and$libresoc.v:41893$1871_Y + connect \$260 $or$libresoc.v:41894$1872_Y + connect \$249 $not$libresoc.v:41895$1873_Y + connect \$264 $and$libresoc.v:41896$1874_Y + connect \$266 $and$libresoc.v:41897$1875_Y + connect \$268 $eq$libresoc.v:41898$1876_Y + connect \$270 $or$libresoc.v:41899$1877_Y + connect \$272 $and$libresoc.v:41900$1878_Y + connect \$274 $or$libresoc.v:41901$1879_Y + connect \$276 $and$libresoc.v:41902$1880_Y + connect \$278 $and$libresoc.v:41903$1881_Y + connect \$280 $eq$libresoc.v:41904$1882_Y + connect \$282 $or$libresoc.v:41905$1883_Y + connect \$284 $eq$libresoc.v:41906$1884_Y + connect \$286 $and$libresoc.v:41907$1885_Y + connect \$288 $eq$libresoc.v:41908$1886_Y + connect \$290 $or$libresoc.v:41909$1887_Y + connect \$263 $not$libresoc.v:41910$1888_Y + connect \$294 $and$libresoc.v:41911$1889_Y + connect \$296 $and$libresoc.v:41912$1890_Y + connect \$298 $eq$libresoc.v:41913$1891_Y + connect \$300 $or$libresoc.v:41914$1892_Y + connect \$302 $and$libresoc.v:41915$1893_Y + connect \$304 $or$libresoc.v:41916$1894_Y + connect \$293 $not$libresoc.v:41917$1895_Y + connect \$308 $and$libresoc.v:41918$1896_Y + connect \$310 $and$libresoc.v:41919$1897_Y + connect \$312 $eq$libresoc.v:41920$1898_Y + connect \$314 $or$libresoc.v:41921$1899_Y + connect \$316 $and$libresoc.v:41922$1900_Y + connect \$318 $or$libresoc.v:41923$1901_Y + connect \$307 $not$libresoc.v:41924$1902_Y + connect \$322 $and$libresoc.v:41925$1903_Y + connect \$324 $and$libresoc.v:41926$1904_Y + connect \$326 $eq$libresoc.v:41927$1905_Y + connect \$328 $or$libresoc.v:41928$1906_Y + connect \$330 $and$libresoc.v:41929$1907_Y + connect \$332 $or$libresoc.v:41930$1908_Y + connect \$334 $eq$libresoc.v:41931$1909_Y + connect \$336 $and$libresoc.v:41932$1910_Y + connect \$338 $eq$libresoc.v:41933$1911_Y + connect \$340 $or$libresoc.v:41934$1912_Y + connect \$321 $not$libresoc.v:41935$1913_Y + connect \$343 $not$libresoc.v:41936$1914_Y + connect \$345 $and$libresoc.v:41937$1915_Y + connect \$347 $and$libresoc.v:41938$1916_Y + connect \$349 $not$libresoc.v:41939$1917_Y + connect \$351 $and$libresoc.v:41940$1918_Y + connect \$353 $and$libresoc.v:41941$1919_Y + connect \$355 $ternary$libresoc.v:41942$1920_Y + connect \$357 $and$libresoc.v:41943$1921_Y + connect \$359 $and$libresoc.v:41944$1922_Y + connect \$361 $not$libresoc.v:41945$1923_Y + connect \$363 $and$libresoc.v:41946$1924_Y + connect \$365 $and$libresoc.v:41947$1925_Y + connect \$367 $ternary$libresoc.v:41948$1926_Y + connect \$369 $and$libresoc.v:41949$1927_Y + connect \$371 $and$libresoc.v:41950$1928_Y + connect \$373 $not$libresoc.v:41951$1929_Y + connect \$375 $and$libresoc.v:41952$1930_Y + connect \$377 $and$libresoc.v:41953$1931_Y + connect \$379 $ternary$libresoc.v:41954$1932_Y + connect \$381 $and$libresoc.v:41955$1933_Y + connect \$383 $and$libresoc.v:41956$1934_Y + connect \$385 $not$libresoc.v:41957$1935_Y + connect \$387 $and$libresoc.v:41958$1936_Y + connect \$389 $and$libresoc.v:41959$1937_Y + connect \$391 $ternary$libresoc.v:41960$1938_Y + connect \$393 $and$libresoc.v:41961$1939_Y + connect \$395 $and$libresoc.v:41962$1940_Y + connect \$397 $not$libresoc.v:41963$1941_Y + connect \$399 $and$libresoc.v:41964$1942_Y + connect \$401 $and$libresoc.v:41965$1943_Y + connect \$403 $ternary$libresoc.v:41966$1944_Y + connect \$405 $and$libresoc.v:41967$1945_Y + connect \$407 $and$libresoc.v:41968$1946_Y + connect \$409 $not$libresoc.v:41969$1947_Y + connect \$411 $and$libresoc.v:41970$1948_Y + connect \$413 $and$libresoc.v:41971$1949_Y + connect \$415 $ternary$libresoc.v:41972$1950_Y + connect \$417 $and$libresoc.v:41973$1951_Y + connect \$419 $and$libresoc.v:41974$1952_Y + connect \$421 $not$libresoc.v:41975$1953_Y + connect \$423 $and$libresoc.v:41976$1954_Y + connect \$425 $and$libresoc.v:41977$1955_Y + connect \$427 $ternary$libresoc.v:41978$1956_Y + connect \$429 $and$libresoc.v:41979$1957_Y + connect \$431 $and$libresoc.v:41980$1958_Y + connect \$433 $not$libresoc.v:41981$1959_Y + connect \$435 $and$libresoc.v:41982$1960_Y + connect \$437 $and$libresoc.v:41983$1961_Y + connect \$439 $ternary$libresoc.v:41984$1962_Y + connect \$441 $and$libresoc.v:41985$1963_Y + connect \$443 $and$libresoc.v:41986$1964_Y + connect \$445 $not$libresoc.v:41987$1965_Y + connect \$447 $and$libresoc.v:41988$1966_Y + connect \$449 $and$libresoc.v:41989$1967_Y + connect \$451 $ternary$libresoc.v:41990$1968_Y + connect \$453 $or$libresoc.v:41991$1969_Y + connect \$455 $or$libresoc.v:41992$1970_Y + connect \$457 $or$libresoc.v:41993$1971_Y + connect \$459 $or$libresoc.v:41994$1972_Y + connect \$461 $or$libresoc.v:41995$1973_Y + connect \$463 $or$libresoc.v:41996$1974_Y + connect \$465 $or$libresoc.v:41997$1975_Y + connect \$467 $or$libresoc.v:41998$1976_Y + connect \$469 $reduce_or$libresoc.v:41999$1977_Y + connect \$471 $and$libresoc.v:42000$1978_Y + connect \$473 $and$libresoc.v:42001$1979_Y + connect \$475 $not$libresoc.v:42002$1980_Y + connect \$477 $and$libresoc.v:42003$1981_Y + connect \$479 $and$libresoc.v:42004$1982_Y + connect \$481 $ternary$libresoc.v:42005$1983_Y + connect \$483 $and$libresoc.v:42006$1984_Y + connect \$485 $and$libresoc.v:42007$1985_Y + connect \$487 $not$libresoc.v:42008$1986_Y + connect \$489 $and$libresoc.v:42009$1987_Y + connect \$491 $and$libresoc.v:42010$1988_Y + connect \$493 $ternary$libresoc.v:42011$1989_Y + connect \$495 $and$libresoc.v:42012$1990_Y + connect \$497 $and$libresoc.v:42013$1991_Y + connect \$499 $not$libresoc.v:42014$1992_Y + connect \$501 $and$libresoc.v:42015$1993_Y + connect \$503 $and$libresoc.v:42016$1994_Y + connect \$505 $ternary$libresoc.v:42017$1995_Y + connect \$507 $and$libresoc.v:42018$1996_Y + connect \$509 $and$libresoc.v:42019$1997_Y + connect \$511 $not$libresoc.v:42020$1998_Y + connect \$513 $and$libresoc.v:42021$1999_Y + connect \$515 $and$libresoc.v:42022$2000_Y + connect \$517 $ternary$libresoc.v:42023$2001_Y + connect \$519 $and$libresoc.v:42024$2002_Y + connect \$521 $and$libresoc.v:42025$2003_Y + connect \$523 $not$libresoc.v:42026$2004_Y + connect \$525 $and$libresoc.v:42027$2005_Y + connect \$527 $and$libresoc.v:42028$2006_Y + connect \$529 $ternary$libresoc.v:42029$2007_Y + connect \$531 $and$libresoc.v:42030$2008_Y + connect \$533 $and$libresoc.v:42031$2009_Y + connect \$535 $not$libresoc.v:42032$2010_Y + connect \$537 $and$libresoc.v:42033$2011_Y + connect \$539 $and$libresoc.v:42034$2012_Y + connect \$541 $ternary$libresoc.v:42035$2013_Y + connect \$543 $and$libresoc.v:42036$2014_Y + connect \$545 $and$libresoc.v:42037$2015_Y + connect \$547 $not$libresoc.v:42038$2016_Y + connect \$549 $and$libresoc.v:42039$2017_Y + connect \$551 $and$libresoc.v:42040$2018_Y + connect \$553 $ternary$libresoc.v:42041$2019_Y + connect \$555 $and$libresoc.v:42042$2020_Y + connect \$557 $and$libresoc.v:42043$2021_Y + connect \$559 $not$libresoc.v:42044$2022_Y + connect \$561 $and$libresoc.v:42045$2023_Y + connect \$563 $and$libresoc.v:42046$2024_Y + connect \$565 $ternary$libresoc.v:42047$2025_Y + connect \$567 $or$libresoc.v:42048$2026_Y + connect \$569 $or$libresoc.v:42049$2027_Y + connect \$571 $or$libresoc.v:42050$2028_Y + connect \$573 $or$libresoc.v:42051$2029_Y + connect \$575 $or$libresoc.v:42052$2030_Y + connect \$577 $or$libresoc.v:42053$2031_Y + connect \$579 $or$libresoc.v:42054$2032_Y + connect \$581 $reduce_or$libresoc.v:42055$2033_Y + connect \$583 $and$libresoc.v:42056$2034_Y + connect \$585 $and$libresoc.v:42057$2035_Y + connect \$587 $not$libresoc.v:42058$2036_Y + connect \$589 $and$libresoc.v:42059$2037_Y + connect \$591 $and$libresoc.v:42060$2038_Y + connect \$593 $ternary$libresoc.v:42061$2039_Y + connect \$595 $and$libresoc.v:42062$2040_Y + connect \$597 $and$libresoc.v:42063$2041_Y + connect \$599 $not$libresoc.v:42064$2042_Y + connect \$601 $and$libresoc.v:42065$2043_Y + connect \$603 $and$libresoc.v:42066$2044_Y + connect \$605 $ternary$libresoc.v:42067$2045_Y + connect \$607 $or$libresoc.v:42068$2046_Y + connect \$609 $reduce_or$libresoc.v:42069$2047_Y + connect \$611 $and$libresoc.v:42070$2048_Y + connect \$613 $and$libresoc.v:42071$2049_Y + connect \$615 $eq$libresoc.v:42072$2050_Y + connect \$617 $or$libresoc.v:42073$2051_Y + connect \$619 $and$libresoc.v:42074$2052_Y + connect \$621 $or$libresoc.v:42075$2053_Y + connect \$623 $and$libresoc.v:42076$2054_Y + connect \$625 $and$libresoc.v:42077$2055_Y + connect \$627 $not$libresoc.v:42078$2056_Y + connect \$629 $and$libresoc.v:42079$2057_Y + connect \$631 $and$libresoc.v:42080$2058_Y + connect \$633 $ternary$libresoc.v:42081$2059_Y + connect \$635 $and$libresoc.v:42082$2060_Y + connect \$637 $and$libresoc.v:42083$2061_Y + connect \$639 $not$libresoc.v:42084$2062_Y + connect \$641 $and$libresoc.v:42085$2063_Y + connect \$643 $and$libresoc.v:42086$2064_Y + connect \$645 $ternary$libresoc.v:42087$2065_Y + connect \$647 $and$libresoc.v:42088$2066_Y + connect \$649 $and$libresoc.v:42089$2067_Y + connect \$651 $not$libresoc.v:42090$2068_Y + connect \$653 $and$libresoc.v:42091$2069_Y + connect \$655 $and$libresoc.v:42092$2070_Y + connect \$657 $ternary$libresoc.v:42093$2071_Y + connect \$659 $and$libresoc.v:42094$2072_Y + connect \$661 $and$libresoc.v:42095$2073_Y + connect \$663 $not$libresoc.v:42096$2074_Y + connect \$665 $and$libresoc.v:42097$2075_Y + connect \$667 $and$libresoc.v:42098$2076_Y + connect \$669 $ternary$libresoc.v:42099$2077_Y + connect \$671 $and$libresoc.v:42100$2078_Y + connect \$673 $and$libresoc.v:42101$2079_Y + connect \$675 $not$libresoc.v:42102$2080_Y + connect \$677 $and$libresoc.v:42103$2081_Y + connect \$679 $and$libresoc.v:42104$2082_Y + connect \$681 $ternary$libresoc.v:42105$2083_Y + connect \$683 $and$libresoc.v:42106$2084_Y + connect \$685 $and$libresoc.v:42107$2085_Y + connect \$687 $not$libresoc.v:42108$2086_Y + connect \$689 $and$libresoc.v:42109$2087_Y + connect \$691 $and$libresoc.v:42110$2088_Y + connect \$693 $ternary$libresoc.v:42111$2089_Y + connect \$696 $or$libresoc.v:42112$2090_Y + connect \$698 $or$libresoc.v:42113$2091_Y + connect \$700 $or$libresoc.v:42114$2092_Y + connect \$702 $or$libresoc.v:42115$2093_Y + connect \$704 $or$libresoc.v:42116$2094_Y + connect \$695 $pos$libresoc.v:42117$2096_Y + connect \$707 $eq$libresoc.v:42118$2097_Y + connect \$709 $and$libresoc.v:42119$2098_Y + connect \$711 $eq$libresoc.v:42120$2099_Y + connect \$713 $or$libresoc.v:42121$2100_Y + connect \$715 $and$libresoc.v:42122$2101_Y + connect \$717 $and$libresoc.v:42123$2102_Y + connect \$719 $not$libresoc.v:42124$2103_Y + connect \$721 $and$libresoc.v:42125$2104_Y + connect \$723 $and$libresoc.v:42126$2105_Y + connect \$725 $ternary$libresoc.v:42127$2106_Y + connect \$727 $and$libresoc.v:42128$2107_Y + connect \$729 $and$libresoc.v:42129$2108_Y + connect \$731 $not$libresoc.v:42130$2109_Y + connect \$733 $and$libresoc.v:42131$2110_Y + connect \$735 $and$libresoc.v:42132$2111_Y + connect \$737 $ternary$libresoc.v:42133$2112_Y + connect \$739 $and$libresoc.v:42134$2113_Y + connect \$741 $and$libresoc.v:42135$2114_Y + connect \$743 $not$libresoc.v:42136$2115_Y + connect \$745 $and$libresoc.v:42137$2116_Y + connect \$747 $and$libresoc.v:42138$2117_Y + connect \$749 $ternary$libresoc.v:42139$2118_Y + connect \$752 $or$libresoc.v:42140$2119_Y + connect \$754 $or$libresoc.v:42141$2120_Y + connect \$751 $pos$libresoc.v:42142$2122_Y + connect \$757 $and$libresoc.v:42143$2123_Y + connect \$759 $and$libresoc.v:42144$2124_Y + connect \$761 $eq$libresoc.v:42145$2125_Y + connect \$763 $or$libresoc.v:42146$2126_Y + connect \$765 $and$libresoc.v:42147$2127_Y + connect \$767 $and$libresoc.v:42148$2128_Y + connect \$769 $not$libresoc.v:42149$2129_Y + connect \$771 $and$libresoc.v:42150$2130_Y + connect \$773 $and$libresoc.v:42151$2131_Y + connect \$775 $ternary$libresoc.v:42152$2132_Y + connect \$777 $and$libresoc.v:42153$2133_Y + connect \$779 $and$libresoc.v:42154$2134_Y + connect \$781 $not$libresoc.v:42155$2135_Y + connect \$783 $and$libresoc.v:42156$2136_Y + connect \$785 $and$libresoc.v:42157$2137_Y + connect \$787 $ternary$libresoc.v:42158$2138_Y + connect \$789 $and$libresoc.v:42159$2139_Y + connect \$791 $and$libresoc.v:42160$2140_Y + connect \$793 $not$libresoc.v:42161$2141_Y + connect \$795 $and$libresoc.v:42162$2142_Y + connect \$797 $and$libresoc.v:42163$2143_Y + connect \$799 $sub$libresoc.v:42164$2144_Y + connect \$801 $sshl$libresoc.v:42165$2145_Y + connect \$803 $ternary$libresoc.v:42166$2146_Y + connect \$805 $and$libresoc.v:42167$2147_Y + connect \$807 $and$libresoc.v:42168$2148_Y + connect \$809 $not$libresoc.v:42169$2149_Y + connect \$811 $and$libresoc.v:42170$2150_Y + connect \$813 $and$libresoc.v:42171$2151_Y + connect \$815 $sub$libresoc.v:42172$2152_Y + connect \$817 $sshl$libresoc.v:42173$2153_Y + connect \$819 $ternary$libresoc.v:42174$2154_Y + connect \$822 $or$libresoc.v:42175$2155_Y + connect \$824 $and$libresoc.v:42176$2156_Y + connect \$826 $and$libresoc.v:42177$2157_Y + connect \$828 $not$libresoc.v:42178$2158_Y + connect \$830 $and$libresoc.v:42179$2159_Y + connect \$832 $and$libresoc.v:42180$2160_Y + connect \$834 $sub$libresoc.v:42181$2161_Y + connect \$836 $sshl$libresoc.v:42182$2162_Y + connect \$838 $ternary$libresoc.v:42183$2163_Y + connect \$840 $and$libresoc.v:42184$2164_Y + connect \$842 $and$libresoc.v:42185$2165_Y + connect \$844 $not$libresoc.v:42186$2166_Y + connect \$846 $and$libresoc.v:42187$2167_Y + connect \$848 $and$libresoc.v:42188$2168_Y + connect \$850 $sub$libresoc.v:42189$2169_Y + connect \$852 $sshl$libresoc.v:42190$2170_Y + connect \$854 $ternary$libresoc.v:42191$2171_Y + connect \$856 $and$libresoc.v:42192$2172_Y + connect \$858 $and$libresoc.v:42193$2173_Y + connect \$860 $not$libresoc.v:42194$2174_Y + connect \$862 $and$libresoc.v:42195$2175_Y + connect \$864 $and$libresoc.v:42196$2176_Y + connect \$866 $ternary$libresoc.v:42197$2177_Y + connect \$868 $and$libresoc.v:42198$2178_Y + connect \$870 $and$libresoc.v:42199$2179_Y + connect \$872 $not$libresoc.v:42200$2180_Y + connect \$874 $and$libresoc.v:42201$2181_Y + connect \$876 $and$libresoc.v:42202$2182_Y + connect \$878 $ternary$libresoc.v:42203$2183_Y + connect \$880 $and$libresoc.v:42204$2184_Y + connect \$882 $and$libresoc.v:42205$2185_Y + connect \$884 $not$libresoc.v:42206$2186_Y + connect \$886 $and$libresoc.v:42207$2187_Y + connect \$888 $and$libresoc.v:42208$2188_Y + connect \$890 $ternary$libresoc.v:42209$2189_Y + connect \$892 $or$libresoc.v:42210$2190_Y + connect \$894 $or$libresoc.v:42211$2191_Y + connect \$896 $reduce_or$libresoc.v:42212$2192_Y + connect \$898 $and$libresoc.v:42213$2193_Y + connect \$900 $and$libresoc.v:42214$2194_Y + connect \$902 $not$libresoc.v:42215$2195_Y + connect \$904 $and$libresoc.v:42216$2196_Y + connect \$906 $and$libresoc.v:42217$2197_Y + connect \$908 $ternary$libresoc.v:42218$2198_Y + connect \$910 $and$libresoc.v:42219$2199_Y + connect \$912 $and$libresoc.v:42220$2200_Y + connect \$914 $not$libresoc.v:42221$2201_Y + connect \$916 $and$libresoc.v:42222$2202_Y + connect \$918 $and$libresoc.v:42223$2203_Y + connect \$920 $ternary$libresoc.v:42224$2204_Y + connect \$922 $or$libresoc.v:42225$2205_Y + connect \$924 $reduce_or$libresoc.v:42226$2206_Y + connect \$926 $and$libresoc.v:42227$2207_Y + connect \$928 $and$libresoc.v:42228$2208_Y + connect \$930 $not$libresoc.v:42229$2209_Y + connect \$932 $and$libresoc.v:42230$2210_Y + connect \$934 $and$libresoc.v:42231$2211_Y + connect \$936 $ternary$libresoc.v:42232$2212_Y + connect \$938 $reduce_or$libresoc.v:42233$2213_Y + connect \$940 $and$libresoc.v:42234$2214_Y + connect \$942 $and$libresoc.v:42235$2215_Y + connect \$944 $and$libresoc.v:42236$2216_Y + connect \$946 $and$libresoc.v:42237$2217_Y + connect \$948 $and$libresoc.v:42238$2218_Y + connect \$950 $and$libresoc.v:42239$2219_Y + connect \$952 $and$libresoc.v:42240$2220_Y + connect \$954 $and$libresoc.v:42241$2221_Y + connect \$956 $and$libresoc.v:42242$2222_Y + connect \$958 $and$libresoc.v:42243$2223_Y + connect \$960 $and$libresoc.v:42244$2224_Y + connect \$962 $and$libresoc.v:42245$2225_Y + connect \$964 $not$libresoc.v:42246$2226_Y + connect \$966 $and$libresoc.v:42247$2227_Y + connect \$972 $and$libresoc.v:42248$2228_Y + connect \$974 $ternary$libresoc.v:42249$2229_Y + connect \$976 $and$libresoc.v:42250$2230_Y + connect \$979 $and$libresoc.v:42251$2231_Y + connect \$983 $not$libresoc.v:42252$2232_Y + connect \$985 $and$libresoc.v:42253$2233_Y + connect \$990 $and$libresoc.v:42254$2234_Y + connect \$993 $ternary$libresoc.v:42255$2235_Y + connect \$995 $and$libresoc.v:42256$2236_Y + connect \$998 $and$libresoc.v:42257$2237_Y + connect \$216 \$217 + connect \$821 \$822 + connect \$1149 \$1166 + connect \$1364 \$1373 + connect \o_ok 1'0 + connect \ea_ok 1'0 + connect \spr_spr1__wen \wp$1802 + connect \spr_spr1__addr$173 \addr_en$1805 [6:0] + connect \spr_spr1__data_i \fus_dest2_o$160 + connect \addr_en$1805 \$1806 + connect \wp$1802 \$1803 + connect \wr_pick_rise$1049 \$1800 + connect \wr_pick$1794 \$1795 + connect \wrpick_SPR_spr1_i \$1792 + connect \wrflag_spr0_spr1_1 \$1790 + connect \state_wen \$1788 + connect \state_data_i$172 \fus_dest5_o$159 + connect \addr_en$1785 \$1786 + connect \wp$1782 \$1783 + connect \wr_pick_rise$1009 \$1780 + connect \wr_pick$1774 \$1775 + connect \wrpick_STATE_msr_i \$1772 + connect \wrflag_trap0_msr_4 \$1770 + connect \state_nia_wen \$1766 + connect \state_data_i \$1764 + connect \addr_en$1761 \$1762 + connect \wp$1758 \$1759 + connect \wr_pick_rise$1008 \$1756 + connect \wr_pick$1750 \$1751 + connect \wrflag_trap0_nia_3 \$1748 + connect \addr_en$1745 \$1746 + connect \wp$1742 \$1743 + connect \wr_pick_rise$1633 \$1740 + connect \wr_pick$1734 \$1735 + connect \wrpick_STATE_nia_i [1] \$1732 + connect \wrpick_STATE_nia_i [0] \$1730 + connect \wrflag_branch0_nia_2 \$1728 + connect \fast_dest1__wen \$1726 + connect \fast_dest1__addr \$1718 + connect \fast_dest1__data_i \$1710 + connect \addr_en$1701 \$1702 + connect \wp$1698 \$1699 + connect \wr_pick_rise$1007 \$1696 + connect \wr_pick$1690 \$1691 + connect \wrflag_trap0_fast1_2 \$1688 + connect \addr_en$1685 \$1686 + connect \wp$1682 \$1683 + connect \wr_pick_rise$1632 \$1680 + connect \wr_pick$1674 \$1675 + connect \wrflag_branch0_fast1_1 \$1672 + connect \addr_en$1669 \$1670 + connect \wp$1666 \$1667 + connect \wr_pick_rise$1048 \$1664 + connect \wr_pick$1658 \$1659 + connect \wrflag_spr0_fast1_2 \$1656 + connect \addr_en$1653 \$1654 + connect \wp$1650 \$1651 + connect \wr_pick_rise$1006 \$1648 + connect \wr_pick$1642 \$1643 + connect \wrflag_trap0_fast1_1 \$1640 + connect \addr_en$1637 \$1638 + connect \wp$1634 \$1635 + connect \fus_cu_wr__go_i$147 [2] \wr_pick_rise$1633 + connect \fus_cu_wr__go_i$147 [1] \wr_pick_rise$1632 + connect \fus_cu_wr__go_i$147 [0] \wr_pick_rise$1627 + connect \wr_pick_rise$1627 \$1630 + connect \wr_pick$1623 \$1624 + connect \wrpick_FAST_fast1_i [4] \$1621 + connect \wrpick_FAST_fast1_i [3] \$1619 + connect \wrpick_FAST_fast1_i [2] \$1617 + connect \wrpick_FAST_fast1_i [1] \$1615 + connect \wrpick_FAST_fast1_i [0] \$1613 + connect \wrflag_branch0_fast1_0 \$1611 + connect \xer_wen$171 \$1603 + connect \xer_data_i$170 \$1595 + connect \addr_en$1592 \$1593 + connect \wp$1589 \$1590 + connect \wr_pick_rise$1089 \$1587 + connect \wr_pick$1581 \$1582 + connect \wrflag_mul0_xer_so_3 \$1579 + connect \addr_en$1576 \$1577 + connect \wp$1573 \$1574 + connect \wr_pick_rise$1069 \$1571 + connect \wr_pick$1565 \$1566 + connect \wrflag_div0_xer_so_3 \$1563 + connect \addr_en$1560 \$1561 + connect \wp$1557 \$1558 + connect \wr_pick_rise$1047 \$1555 + connect \wr_pick$1549 \$1550 + connect \wrflag_spr0_xer_so_3 \$1547 + connect \addr_en$1544 \$1545 + connect \wp$1541 \$1542 + connect \wr_pick_rise$971 \$1539 + connect \wr_pick$1533 \$1534 + connect \wrpick_XER_xer_so_i [3] \$1531 + connect \wrpick_XER_xer_so_i [2] \$1529 + connect \wrpick_XER_xer_so_i [1] \$1527 + connect \wrpick_XER_xer_so_i [0] \$1525 + connect \wrflag_alu0_xer_so_4 \$1523 + connect \xer_wen$169 \$1521 + connect \xer_data_i$168 \$1515 + connect \addr_en$1508 \$1509 + connect \wp$1505 \$1506 + connect \wr_pick_rise$1088 \$1503 + connect \wr_pick$1497 \$1498 + connect \wrflag_mul0_xer_ov_2 \$1495 + connect \addr_en$1492 \$1493 + connect \wp$1489 \$1490 + connect \wr_pick_rise$1068 \$1487 + connect \wr_pick$1481 \$1482 + connect \wrflag_div0_xer_ov_2 \$1479 + connect \addr_en$1476 \$1477 + connect \wp$1473 \$1474 + connect \wr_pick_rise$1046 \$1471 + connect \wr_pick$1465 \$1466 + connect \wrflag_spr0_xer_ov_4 \$1463 + connect \addr_en$1460 \$1461 + connect \wp$1457 \$1458 + connect \wr_pick_rise$970 \$1455 + connect \wr_pick$1449 \$1450 + connect \wrpick_XER_xer_ov_i [3] \$1447 + connect \wrpick_XER_xer_ov_i [2] \$1445 + connect \wrpick_XER_xer_ov_i [1] \$1443 + connect \wrpick_XER_xer_ov_i [0] \$1441 + connect \wrflag_alu0_xer_ov_3 \$1439 + connect \xer_wen \$1433 + connect \xer_data_i \$1431 + connect \addr_en$1426 \$1427 + connect \wp$1423 \$1424 + connect \wr_pick_rise$1108 \$1421 + connect \wr_pick$1415 \$1416 + connect \wrflag_shiftrot0_xer_ca_2 \$1413 + connect \addr_en$1410 \$1411 + connect \wp$1407 \$1408 + connect \wr_pick_rise$1045 \$1405 + connect \wr_pick$1399 \$1400 + connect \wrflag_spr0_xer_ca_5 \$1397 + connect \addr_en$1394 \$1395 + connect \wp$1391 \$1392 + connect \wr_pick_rise$969 \$1389 + connect \wr_pick$1383 \$1384 + connect \wrpick_XER_xer_ca_i [2] \$1381 + connect \wrpick_XER_xer_ca_i [1] \$1379 + connect \wrpick_XER_xer_ca_i [0] \$1377 + connect \wrflag_alu0_xer_ca_2 \$1375 + connect \cr_wen \$1373 [7:0] + connect \cr_data_i \$1362 + connect \addr_en$1347 \$1352 + connect \wp$1344 \$1345 + connect \wr_pick_rise$1107 \$1342 + connect \wr_pick$1336 \$1337 + connect \wrflag_shiftrot0_cr_a_1 \$1334 + connect \addr_en$1327 \$1332 + connect \wp$1324 \$1325 + connect \wr_pick_rise$1087 \$1322 + connect \wr_pick$1316 \$1317 + connect \wrflag_mul0_cr_a_1 \$1314 + connect \addr_en$1307 \$1312 + connect \wp$1304 \$1305 + connect \wr_pick_rise$1067 \$1302 + connect \wr_pick$1296 \$1297 + connect \wrflag_div0_cr_a_1 \$1294 + connect \addr_en$1287 \$1292 + connect \wp$1284 \$1285 + connect \wr_pick_rise$1027 \$1282 + connect \wr_pick$1276 \$1277 + connect \wrflag_logical0_cr_a_1 \$1274 + connect \addr_en$1267 \$1272 + connect \wp$1264 \$1265 + connect \wr_pick_rise$988 \$1262 + connect \wr_pick$1256 \$1257 + connect \wrflag_cr0_cr_a_2 \$1254 + connect \addr_en$1247 \$1252 + connect \wp$1244 \$1245 + connect \wr_pick_rise$968 \$1242 + connect \wr_pick$1236 \$1237 + connect \wrpick_CR_cr_a_i [5] \$1234 + connect \wrpick_CR_cr_a_i [4] \$1232 + connect \wrpick_CR_cr_a_i [3] \$1230 + connect \wrpick_CR_cr_a_i [2] \$1228 + connect \wrpick_CR_cr_a_i [1] \$1226 + connect \wrpick_CR_cr_a_i [0] \$1224 + connect \wrflag_alu0_cr_a_1 \$1222 + connect \cr_full_wr__wen \addr_en$1219 + connect \cr_full_wr__data_i \fus_dest2_o + connect \addr_en$1219 \$1220 + connect \wp$1216 \$1217 + connect \wr_pick_rise$987 \$1214 + connect \wr_pick$1208 \$1209 + connect \wrpick_CR_full_cr_i \$1206 + connect \wrflag_cr0_full_cr_1 \$1204 + connect \int_dest1__wen \$1202 + connect \int_dest1__addr \$1184 + connect \int_dest1__data_i \$1166 [63:0] + connect \addr_en$1146 \$1147 + connect \wp$1143 \$1144 + connect \wr_pick_rise$1126 \$1141 + connect \wr_pick$1135 \$1136 + connect \wrflag_ldst0_o_1 \$1133 + connect \addr_en$1130 \$1131 + connect \wp$1127 \$1128 + connect \fus_cu_wr__go_i$112 [1] \wr_pick_rise$1126 + connect \fus_cu_wr__go_i$112 [0] \wr_pick_rise$1121 + connect \wr_pick_rise$1121 \$1124 + connect \wr_pick$1117 \$1118 + connect \wrflag_ldst0_o_0 \$1115 + connect \addr_en$1112 \$1113 + connect \wp$1109 \$1110 + connect \fus_cu_wr__go_i$110 [2] \wr_pick_rise$1108 + connect \fus_cu_wr__go_i$110 [1] \wr_pick_rise$1107 + connect \fus_cu_wr__go_i$110 [0] \wr_pick_rise$1102 + connect \wr_pick_rise$1102 \$1105 + connect \wr_pick$1098 \$1099 + connect \wrflag_shiftrot0_o_0 \$1096 + connect \addr_en$1093 \$1094 + connect \wp$1090 \$1091 + connect \fus_cu_wr__go_i$107 [3] \wr_pick_rise$1089 + connect \fus_cu_wr__go_i$107 [2] \wr_pick_rise$1088 + connect \fus_cu_wr__go_i$107 [1] \wr_pick_rise$1087 + connect \fus_cu_wr__go_i$107 [0] \wr_pick_rise$1082 + connect \wr_pick_rise$1082 \$1085 + connect \wr_pick$1078 \$1079 + connect \wrflag_mul0_o_0 \$1076 + connect \addr_en$1073 \$1074 + connect \wp$1070 \$1071 + connect \fus_cu_wr__go_i$104 [3] \wr_pick_rise$1069 + connect \fus_cu_wr__go_i$104 [2] \wr_pick_rise$1068 + connect \fus_cu_wr__go_i$104 [1] \wr_pick_rise$1067 + connect \fus_cu_wr__go_i$104 [0] \wr_pick_rise$1062 + connect \wr_pick_rise$1062 \$1065 + connect \wr_pick$1058 \$1059 + connect \wrflag_div0_o_0 \$1056 + connect \addr_en$1053 \$1054 + connect \wp$1050 \$1051 + connect \fus_cu_wr__go_i$101 [1] \wr_pick_rise$1049 + connect \fus_cu_wr__go_i$101 [2] \wr_pick_rise$1048 + connect \fus_cu_wr__go_i$101 [3] \wr_pick_rise$1047 + connect \fus_cu_wr__go_i$101 [4] \wr_pick_rise$1046 + connect \fus_cu_wr__go_i$101 [5] \wr_pick_rise$1045 + connect \fus_cu_wr__go_i$101 [0] \wr_pick_rise$1040 + connect \wr_pick_rise$1040 \$1043 + connect \wr_pick$1036 \$1037 + connect \wrflag_spr0_o_0 \$1034 + connect \addr_en$1031 \$1032 + connect \wp$1028 \$1029 + connect \fus_cu_wr__go_i$98 [1] \wr_pick_rise$1027 + connect \fus_cu_wr__go_i$98 [0] \wr_pick_rise$1022 + connect \wr_pick_rise$1022 \$1025 + connect \wr_pick$1018 \$1019 + connect \wrflag_logical0_o_0 \$1016 + connect \addr_en$1013 \$1014 + connect \wp$1010 \$1011 + connect \fus_cu_wr__go_i$95 [4] \wr_pick_rise$1009 + connect \fus_cu_wr__go_i$95 [3] \wr_pick_rise$1008 + connect \fus_cu_wr__go_i$95 [2] \wr_pick_rise$1007 + connect \fus_cu_wr__go_i$95 [1] \wr_pick_rise$1006 + connect \fus_cu_wr__go_i$95 [0] \wr_pick_rise$1001 + connect \wr_pick_rise$1001 \$1004 + connect \wr_pick$997 \$998 + connect \wrflag_trap0_o_0 \$995 + connect \addr_en$992 \$993 + connect \wp$989 \$990 + connect \fus_cu_wr__go_i$92 [2] \wr_pick_rise$988 + connect \fus_cu_wr__go_i$92 [1] \wr_pick_rise$987 + connect \fus_cu_wr__go_i$92 [0] \wr_pick_rise$982 + connect \wr_pick_rise$982 \$985 + connect \wr_pick$978 \$979 + connect \wrflag_cr0_o_0 \$976 + connect \addr_en \$974 + connect \wp \$972 + connect \fus_cu_wr__go_i [4] \wr_pick_rise$971 + connect \fus_cu_wr__go_i [3] \wr_pick_rise$970 + connect \fus_cu_wr__go_i [2] \wr_pick_rise$969 + connect \fus_cu_wr__go_i [1] \wr_pick_rise$968 + connect \fus_cu_wr__go_i [0] \wr_pick_rise + connect \wr_pick_rise \$966 + connect \wr_pick \$962 + connect \wrpick_INT_o_i [9] \$960 + connect \wrpick_INT_o_i [8] \$958 + connect \wrpick_INT_o_i [7] \$956 + connect \wrpick_INT_o_i [6] \$954 + connect \wrpick_INT_o_i [5] \$952 + connect \wrpick_INT_o_i [4] \$950 + connect \wrpick_INT_o_i [3] \$948 + connect \wrpick_INT_o_i [2] \$946 + connect \wrpick_INT_o_i [1] \$944 + connect \wrpick_INT_o_i [0] \$942 + connect \wrflag_alu0_o_0 \$940 + connect \spr_spr1__ren \$938 + connect \spr_spr1__addr \addr_en_SPR_spr1_spr0_0 [6:0] + connect \addr_en_SPR_spr1_spr0_0 \$936 + connect \rp_SPR_spr1_spr0_0 \$934 + connect \rdpick_SPR_spr1_i \pick_SPR_spr1_spr0_0 + connect \pick_SPR_spr1_spr0_0 \$932 + connect \rdflag_SPR_spr1_0 \core_spr1_ok + connect \fast_src2__ren \$924 + connect \fast_src2__addr \$922 + connect \addr_en_FAST_fast2_trap0_1 \$920 + connect \rp_FAST_fast2_trap0_1 \$918 + connect \pick_FAST_fast2_trap0_1 \$916 + connect \addr_en_FAST_fast2_branch0_0 \$908 + connect \rp_FAST_fast2_branch0_0 \$906 + connect \rdpick_FAST_fast2_i [1] \pick_FAST_fast2_trap0_1 + connect \rdpick_FAST_fast2_i [0] \pick_FAST_fast2_branch0_0 + connect \pick_FAST_fast2_branch0_0 \$904 + connect \rdflag_FAST_fast2_0 \core_fast2_ok + connect \fast_src1__ren \$896 + connect \fast_src1__addr \$894 + connect \addr_en_FAST_fast1_spr0_2 \$890 + connect \rp_FAST_fast1_spr0_2 \$888 + connect \pick_FAST_fast1_spr0_2 \$886 + connect \addr_en_FAST_fast1_trap0_1 \$878 + connect \rp_FAST_fast1_trap0_1 \$876 + connect \pick_FAST_fast1_trap0_1 \$874 + connect \addr_en_FAST_fast1_branch0_0 \$866 + connect \rp_FAST_fast1_branch0_0 \$864 + connect \rdpick_FAST_fast1_i [2] \pick_FAST_fast1_spr0_2 + connect \rdpick_FAST_fast1_i [1] \pick_FAST_fast1_trap0_1 + connect \rdpick_FAST_fast1_i [0] \pick_FAST_fast1_branch0_0 + connect \pick_FAST_fast1_branch0_0 \$862 + connect \rdflag_FAST_fast1_0 \core_fast1_ok + connect \cr_src3__ren \addr_en_CR_cr_c_cr0_0 [7:0] + connect \addr_en_CR_cr_c_cr0_0 \$854 + connect \rp_CR_cr_c_cr0_0 \$848 + connect \rdpick_CR_cr_c_i \pick_CR_cr_c_cr0_0 + connect \pick_CR_cr_c_cr0_0 \$846 + connect \rdflag_CR_cr_c_0 \core_cr_in2_ok$2 + connect \cr_src2__ren \addr_en_CR_cr_b_cr0_0 [7:0] + connect \addr_en_CR_cr_b_cr0_0 \$838 + connect \rp_CR_cr_b_cr0_0 \$832 + connect \rdpick_CR_cr_b_i \pick_CR_cr_b_cr0_0 + connect \pick_CR_cr_b_cr0_0 \$830 + connect \rdflag_CR_cr_b_0 \core_cr_in2_ok + connect \cr_src1__ren \$822 [7:0] + connect \addr_en_CR_cr_a_branch0_1 \$819 + connect \rp_CR_cr_a_branch0_1 \$813 + connect \fus_cu_rd__go_i$80 [1] \dp_FAST_fast2_branch0_0 + connect \fus_cu_rd__go_i$80 [0] \dp_FAST_fast1_branch0_0 + connect \fus_cu_rd__go_i$80 [2] \dp_CR_cr_a_branch0_1 + connect \pick_CR_cr_a_branch0_1 \$811 + connect \addr_en_CR_cr_a_cr0_0 \$803 + connect \rp_CR_cr_a_cr0_0 \$797 + connect \rdpick_CR_cr_a_i [1] \pick_CR_cr_a_branch0_1 + connect \rdpick_CR_cr_a_i [0] \pick_CR_cr_a_cr0_0 + connect \pick_CR_cr_a_cr0_0 \$795 + connect \rdflag_CR_cr_a_0 \core_cr_in1_ok + connect \cr_full_rd__ren \addr_en_CR_full_cr_cr0_0 + connect \addr_en_CR_full_cr_cr0_0 \$787 + connect \rp_CR_full_cr_cr0_0 \$785 + connect \rdpick_CR_full_cr_i \pick_CR_full_cr_cr0_0 + connect \pick_CR_full_cr_cr0_0 \$783 + connect \rdflag_CR_full_cr_0 \core_core_cr_rd_ok + connect \xer_src3__ren \addr_en_XER_xer_ov_spr0_0 + connect \addr_en_XER_xer_ov_spr0_0 \$775 + connect \rp_XER_xer_ov_spr0_0 \$773 + connect \rdpick_XER_xer_ov_i \pick_XER_xer_ov_spr0_0 + connect \pick_XER_xer_ov_spr0_0 \$771 + connect \rdflag_XER_xer_ov_0 \$763 + connect \xer_src2__ren \$751 + connect \addr_en_XER_xer_ca_shiftrot0_2 \$749 + connect \rp_XER_xer_ca_shiftrot0_2 \$747 + connect \pick_XER_xer_ca_shiftrot0_2 \$745 + connect \addr_en_XER_xer_ca_spr0_1 \$737 + connect \rp_XER_xer_ca_spr0_1 \$735 + connect \pick_XER_xer_ca_spr0_1 \$733 + connect \addr_en_XER_xer_ca_alu0_0 \$725 + connect \rp_XER_xer_ca_alu0_0 \$723 + connect \rdpick_XER_xer_ca_i [2] \pick_XER_xer_ca_shiftrot0_2 + connect \rdpick_XER_xer_ca_i [1] \pick_XER_xer_ca_spr0_1 + connect \rdpick_XER_xer_ca_i [0] \pick_XER_xer_ca_alu0_0 + connect \pick_XER_xer_ca_alu0_0 \$721 + connect \rdflag_XER_xer_ca_0 \$713 + connect \xer_src1__ren \$695 + connect \addr_en_XER_xer_so_shiftrot0_5 \$693 + connect \rp_XER_xer_so_shiftrot0_5 \$691 + connect \pick_XER_xer_so_shiftrot0_5 \$689 + connect \addr_en_XER_xer_so_mul0_4 \$681 + connect \rp_XER_xer_so_mul0_4 \$679 + connect \pick_XER_xer_so_mul0_4 \$677 + connect \addr_en_XER_xer_so_div0_3 \$669 + connect \rp_XER_xer_so_div0_3 \$667 + connect \pick_XER_xer_so_div0_3 \$665 + connect \addr_en_XER_xer_so_spr0_2 \$657 + connect \rp_XER_xer_so_spr0_2 \$655 + connect \pick_XER_xer_so_spr0_2 \$653 + connect \addr_en_XER_xer_so_logical0_1 \$645 + connect \rp_XER_xer_so_logical0_1 \$643 + connect \pick_XER_xer_so_logical0_1 \$641 + connect \addr_en_XER_xer_so_alu0_0 \$633 + connect \rp_XER_xer_so_alu0_0 \$631 + connect \rdpick_XER_xer_so_i [5] \pick_XER_xer_so_shiftrot0_5 + connect \rdpick_XER_xer_so_i [4] \pick_XER_xer_so_mul0_4 + connect \rdpick_XER_xer_so_i [3] \pick_XER_xer_so_div0_3 + connect \rdpick_XER_xer_so_i [2] \pick_XER_xer_so_spr0_2 + connect \rdpick_XER_xer_so_i [1] \pick_XER_xer_so_logical0_1 + connect \rdpick_XER_xer_so_i [0] \pick_XER_xer_so_alu0_0 + connect \pick_XER_xer_so_alu0_0 \$629 + connect \rdflag_XER_xer_so_0 \$621 + connect \int_src3__ren \$609 + connect \int_src3__addr \$607 + connect \addr_en_INT_rc_ldst0_1 \$605 + connect \rp_INT_rc_ldst0_1 \$603 + connect \pick_INT_rc_ldst0_1 \$601 + connect \addr_en_INT_rc_shiftrot0_0 \$593 + connect \rp_INT_rc_shiftrot0_0 \$591 + connect \rdpick_INT_rc_i [1] \pick_INT_rc_ldst0_1 + connect \rdpick_INT_rc_i [0] \pick_INT_rc_shiftrot0_0 + connect \pick_INT_rc_shiftrot0_0 \$589 + connect \rdflag_INT_rc_0 \core_reg3_ok + connect \int_src2__ren \$581 + connect \int_src2__addr \$579 + connect \addr_en_INT_rb_ldst0_7 \$565 + connect \rp_INT_rb_ldst0_7 \$563 + connect \pick_INT_rb_ldst0_7 \$561 + connect \addr_en_INT_rb_shiftrot0_6 \$553 + connect \rp_INT_rb_shiftrot0_6 \$551 + connect \pick_INT_rb_shiftrot0_6 \$549 + connect \addr_en_INT_rb_mul0_5 \$541 + connect \rp_INT_rb_mul0_5 \$539 + connect \pick_INT_rb_mul0_5 \$537 + connect \addr_en_INT_rb_div0_4 \$529 + connect \rp_INT_rb_div0_4 \$527 + connect \pick_INT_rb_div0_4 \$525 + connect \addr_en_INT_rb_logical0_3 \$517 + connect \rp_INT_rb_logical0_3 \$515 + connect \pick_INT_rb_logical0_3 \$513 + connect \addr_en_INT_rb_trap0_2 \$505 + connect \rp_INT_rb_trap0_2 \$503 + connect \pick_INT_rb_trap0_2 \$501 + connect \addr_en_INT_rb_cr0_1 \$493 + connect \rp_INT_rb_cr0_1 \$491 + connect \pick_INT_rb_cr0_1 \$489 + connect \addr_en_INT_rb_alu0_0 \$481 + connect \rp_INT_rb_alu0_0 \$479 + connect \rdpick_INT_rb_i [7] \pick_INT_rb_ldst0_7 + connect \rdpick_INT_rb_i [6] \pick_INT_rb_shiftrot0_6 + connect \rdpick_INT_rb_i [5] \pick_INT_rb_mul0_5 + connect \rdpick_INT_rb_i [4] \pick_INT_rb_div0_4 + connect \rdpick_INT_rb_i [3] \pick_INT_rb_logical0_3 + connect \rdpick_INT_rb_i [2] \pick_INT_rb_trap0_2 + connect \rdpick_INT_rb_i [1] \pick_INT_rb_cr0_1 + connect \rdpick_INT_rb_i [0] \pick_INT_rb_alu0_0 + connect \pick_INT_rb_alu0_0 \$477 + connect \rdflag_INT_rb_0 \core_reg2_ok + connect \int_src1__ren \$469 + connect \int_src1__addr \$467 + connect \addr_en_INT_ra_ldst0_8 \$451 + connect \rp_INT_ra_ldst0_8 \$449 + connect \fus_cu_rd__go_i$60 [2] \dp_INT_rc_ldst0_1 + connect \fus_cu_rd__go_i$60 [1] \dp_INT_rb_ldst0_7 + connect \fus_cu_rd__go_i$60 [0] \dp_INT_ra_ldst0_8 + connect \pick_INT_ra_ldst0_8 \$447 + connect \addr_en_INT_ra_shiftrot0_7 \$439 + connect \rp_INT_ra_shiftrot0_7 \$437 + connect \fus_cu_rd__go_i$57 [4] \dp_XER_xer_ca_shiftrot0_2 + connect \fus_cu_rd__go_i$57 [3] \dp_XER_xer_so_shiftrot0_5 + connect \fus_cu_rd__go_i$57 [2] \dp_INT_rc_shiftrot0_0 + connect \fus_cu_rd__go_i$57 [1] \dp_INT_rb_shiftrot0_6 + connect \fus_cu_rd__go_i$57 [0] \dp_INT_ra_shiftrot0_7 + connect \pick_INT_ra_shiftrot0_7 \$435 + connect \addr_en_INT_ra_mul0_6 \$427 + connect \rp_INT_ra_mul0_6 \$425 + connect \fus_cu_rd__go_i$54 [2] \dp_XER_xer_so_mul0_4 + connect \fus_cu_rd__go_i$54 [1] \dp_INT_rb_mul0_5 + connect \fus_cu_rd__go_i$54 [0] \dp_INT_ra_mul0_6 + connect \pick_INT_ra_mul0_6 \$423 + connect \addr_en_INT_ra_div0_5 \$415 + connect \rp_INT_ra_div0_5 \$413 + connect \fus_cu_rd__go_i$51 [2] \dp_XER_xer_so_div0_3 + connect \fus_cu_rd__go_i$51 [1] \dp_INT_rb_div0_4 + connect \fus_cu_rd__go_i$51 [0] \dp_INT_ra_div0_5 + connect \pick_INT_ra_div0_5 \$411 + connect \addr_en_INT_ra_spr0_4 \$403 + connect \rp_INT_ra_spr0_4 \$401 + connect \fus_cu_rd__go_i$48 [1] \dp_SPR_spr1_spr0_0 + connect \fus_cu_rd__go_i$48 [2] \dp_FAST_fast1_spr0_2 + connect \fus_cu_rd__go_i$48 [4] \dp_XER_xer_ov_spr0_0 + connect \fus_cu_rd__go_i$48 [5] \dp_XER_xer_ca_spr0_1 + connect \fus_cu_rd__go_i$48 [3] \dp_XER_xer_so_spr0_2 + connect \fus_cu_rd__go_i$48 [0] \dp_INT_ra_spr0_4 + connect \pick_INT_ra_spr0_4 \$399 + connect \addr_en_INT_ra_logical0_3 \$391 + connect \rp_INT_ra_logical0_3 \$389 + connect \fus_cu_rd__go_i$45 [2] \dp_XER_xer_so_logical0_1 + connect \fus_cu_rd__go_i$45 [1] \dp_INT_rb_logical0_3 + connect \fus_cu_rd__go_i$45 [0] \dp_INT_ra_logical0_3 + connect \pick_INT_ra_logical0_3 \$387 + connect \addr_en_INT_ra_trap0_2 \$379 + connect \rp_INT_ra_trap0_2 \$377 + connect \fus_cu_rd__go_i$42 [3] \dp_FAST_fast2_trap0_1 + connect \fus_cu_rd__go_i$42 [2] \dp_FAST_fast1_trap0_1 + connect \fus_cu_rd__go_i$42 [1] \dp_INT_rb_trap0_2 + connect \fus_cu_rd__go_i$42 [0] \dp_INT_ra_trap0_2 + connect \pick_INT_ra_trap0_2 \$375 + connect \addr_en_INT_ra_cr0_1 \$367 + connect \rp_INT_ra_cr0_1 \$365 + connect \fus_cu_rd__go_i$39 [5] \dp_CR_cr_c_cr0_0 + connect \fus_cu_rd__go_i$39 [4] \dp_CR_cr_b_cr0_0 + connect \fus_cu_rd__go_i$39 [3] \dp_CR_cr_a_cr0_0 + connect \fus_cu_rd__go_i$39 [2] \dp_CR_full_cr_cr0_0 + connect \fus_cu_rd__go_i$39 [1] \dp_INT_rb_cr0_1 + connect \fus_cu_rd__go_i$39 [0] \dp_INT_ra_cr0_1 + connect \pick_INT_ra_cr0_1 \$363 + connect \addr_en_INT_ra_alu0_0 \$355 + connect \rp_INT_ra_alu0_0 \$353 + connect \fus_cu_rd__go_i [3] \dp_XER_xer_ca_alu0_0 + connect \fus_cu_rd__go_i [2] \dp_XER_xer_so_alu0_0 + connect \fus_cu_rd__go_i [1] \dp_INT_rb_alu0_0 + connect \fus_cu_rd__go_i [0] \dp_INT_ra_alu0_0 + connect \rdpick_INT_ra_i [8] \pick_INT_ra_ldst0_8 + connect \rdpick_INT_ra_i [7] \pick_INT_ra_shiftrot0_7 + connect \rdpick_INT_ra_i [6] \pick_INT_ra_mul0_6 + connect \rdpick_INT_ra_i [5] \pick_INT_ra_div0_5 + connect \rdpick_INT_ra_i [4] \pick_INT_ra_spr0_4 + connect \rdpick_INT_ra_i [3] \pick_INT_ra_logical0_3 + connect \rdpick_INT_ra_i [2] \pick_INT_ra_trap0_2 + connect \rdpick_INT_ra_i [1] \pick_INT_ra_cr0_1 + connect \rdpick_INT_ra_i [0] \pick_INT_ra_alu0_0 + connect \pick_INT_ra_alu0_0 \$351 + connect \rdflag_INT_ra_0 \core_reg1_ok + connect \en_ldst0 \$210 + connect \en_shiftrot0 \$206 + connect \en_mul0 \$202 + connect \en_div0 \$198 + connect \en_spr0 \$194 + connect \en_logical0 \$190 + connect \en_trap0 \$186 + connect \en_branch0 \$182 + connect \en_cr0 \$178 + connect \fu_enable [9] \en_ldst0 + connect \fu_enable [8] \en_shiftrot0 + connect \fu_enable [7] \en_mul0 + connect \fu_enable [6] \en_div0 + connect \fu_enable [5] \en_spr0 + connect \fu_enable [4] \en_logical0 + connect \fu_enable [3] \en_trap0 + connect \fu_enable [2] \en_branch0 + connect \fu_enable [1] \en_cr0 + connect \fu_enable [0] \en_alu0 + connect \en_alu0 \$174 + connect \dec_LDST_bigendian \bigendian_i + connect \dec_LDST_raw_opcode_in \raw_insn_i + connect \dec_SHIFT_ROT_bigendian \bigendian_i + connect \dec_SHIFT_ROT_raw_opcode_in \raw_insn_i + connect \dec_MUL_bigendian \bigendian_i + connect \dec_MUL_raw_opcode_in \raw_insn_i + connect \dec_DIV_bigendian \bigendian_i + connect \dec_DIV_raw_opcode_in \raw_insn_i + connect \dec_SPR_bigendian \bigendian_i + connect \dec_SPR_raw_opcode_in \raw_insn_i + connect \dec_LOGICAL_bigendian \bigendian_i + connect \dec_LOGICAL_raw_opcode_in \raw_insn_i + connect \dec_BRANCH_bigendian \bigendian_i + connect \dec_BRANCH_raw_opcode_in \raw_insn_i + connect \dec_CR_bigendian \bigendian_i + connect \dec_CR_raw_opcode_in \raw_insn_i + connect \dec_ALU_bigendian \bigendian_i + connect \dec_ALU_raw_opcode_in \raw_insn_i +end +attribute \src "libresoc.v:48554.1-49187.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.cr" +attribute \generator "nMigen" +module \cr + attribute \src "libresoc.v:48555.7-48555.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:49101.3-49109.6" + wire width 8 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wire width 8 input 13 \full_wr__wen + attribute \src "libresoc.v:48555.7-48555.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_0_dest10__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_0_dest10__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_0_dest20__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_0_dest20__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_0_r0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_0_r0__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_0_r20__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_0_r20__ren + attribute \src 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4 + parameter \Y_WIDTH 4 + connect \A \reg_4_src34__data_o + connect \B \reg_5_src35__data_o + connect \Y $or$libresoc.v:48929$3034_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:48930$3035 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_6_src36__data_o + connect \B \reg_7_src37__data_o + connect \Y $or$libresoc.v:48930$3035_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:48931$3036 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$43 + connect \B \$45 + connect \Y $or$libresoc.v:48931$3036_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:48932$3037 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$41 + connect \B \$47 + connect \Y $or$libresoc.v:48932$3037_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:48933$3038 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_2_src12__data_o + connect \B \reg_3_src13__data_o + connect \Y $or$libresoc.v:48933$3038_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:48934$3039 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$3 + connect \B \$5 + connect \Y $or$libresoc.v:48934$3039_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:48915$3020 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ren_delay$17 + connect \Y $reduce_or$libresoc.v:48915$3020_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:48916$3021 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ren_delay + connect \Y $reduce_or$libresoc.v:48916$3021_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:48924$3029 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ren_delay$34 + connect \Y $reduce_or$libresoc.v:48924$3029_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:48941.9-48960.4" + cell \reg_0 \reg_0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest10__data_i \reg_0_dest10__data_i + connect \dest10__wen \reg_0_dest10__wen + connect \dest20__data_i \reg_0_dest20__data_i + connect \dest20__wen \reg_0_dest20__wen + connect \r0__data_o \reg_0_r0__data_o + connect \r0__ren \reg_0_r0__ren + connect \r20__data_o \reg_0_r20__data_o + connect \r20__ren \reg_0_r20__ren + connect \src10__data_o \reg_0_src10__data_o + connect \src10__ren \reg_0_src10__ren + connect \src20__data_o \reg_0_src20__data_o + connect \src20__ren \reg_0_src20__ren + connect \src30__data_o \reg_0_src30__data_o + connect \src30__ren \reg_0_src30__ren + connect \w0__data_i \reg_0_w0__data_i + connect \w0__wen \reg_0_w0__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:48961.9-48980.4" + cell \reg_1 \reg_1 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest11__data_i \reg_1_dest11__data_i + connect \dest11__wen \reg_1_dest11__wen + connect \dest21__data_i \reg_1_dest21__data_i + connect \dest21__wen \reg_1_dest21__wen + connect \r1__data_o \reg_1_r1__data_o + connect \r1__ren \reg_1_r1__ren + connect \r21__data_o \reg_1_r21__data_o + connect \r21__ren \reg_1_r21__ren + connect \src11__data_o \reg_1_src11__data_o + connect \src11__ren \reg_1_src11__ren + connect \src21__data_o \reg_1_src21__data_o + connect \src21__ren \reg_1_src21__ren + connect \src31__data_o \reg_1_src31__data_o + connect \src31__ren \reg_1_src31__ren + connect \w1__data_i \reg_1_w1__data_i + connect \w1__wen \reg_1_w1__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:48981.9-49000.4" + cell \reg_2 \reg_2 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest12__data_i \reg_2_dest12__data_i + connect \dest12__wen \reg_2_dest12__wen + connect \dest22__data_i \reg_2_dest22__data_i + connect \dest22__wen \reg_2_dest22__wen + connect \r22__data_o \reg_2_r22__data_o + connect \r22__ren \reg_2_r22__ren + connect \r2__data_o \reg_2_r2__data_o + connect \r2__ren \reg_2_r2__ren + connect \src12__data_o \reg_2_src12__data_o + connect \src12__ren \reg_2_src12__ren + connect \src22__data_o \reg_2_src22__data_o + connect \src22__ren \reg_2_src22__ren + connect \src32__data_o \reg_2_src32__data_o + connect \src32__ren \reg_2_src32__ren + connect \w2__data_i \reg_2_w2__data_i + connect \w2__wen \reg_2_w2__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49001.9-49020.4" + cell \reg_3 \reg_3 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest13__data_i \reg_3_dest13__data_i + connect \dest13__wen \reg_3_dest13__wen + connect \dest23__data_i \reg_3_dest23__data_i + connect \dest23__wen \reg_3_dest23__wen + connect \r23__data_o \reg_3_r23__data_o + connect \r23__ren \reg_3_r23__ren + connect \r3__data_o \reg_3_r3__data_o + connect \r3__ren \reg_3_r3__ren + connect \src13__data_o \reg_3_src13__data_o + connect \src13__ren \reg_3_src13__ren + connect \src23__data_o \reg_3_src23__data_o + connect \src23__ren \reg_3_src23__ren + connect \src33__data_o \reg_3_src33__data_o + connect \src33__ren \reg_3_src33__ren + connect \w3__data_i \reg_3_w3__data_i + connect \w3__wen \reg_3_w3__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49021.9-49040.4" + cell \reg_4 \reg_4 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest14__data_i \reg_4_dest14__data_i + connect \dest14__wen \reg_4_dest14__wen + connect \dest24__data_i \reg_4_dest24__data_i + connect \dest24__wen \reg_4_dest24__wen + connect \r24__data_o \reg_4_r24__data_o + connect \r24__ren \reg_4_r24__ren + connect \r4__data_o \reg_4_r4__data_o + connect \r4__ren \reg_4_r4__ren + connect \src14__data_o \reg_4_src14__data_o + connect \src14__ren \reg_4_src14__ren + connect \src24__data_o \reg_4_src24__data_o + connect \src24__ren \reg_4_src24__ren + connect \src34__data_o \reg_4_src34__data_o + connect \src34__ren \reg_4_src34__ren + connect \w4__data_i \reg_4_w4__data_i + connect \w4__wen \reg_4_w4__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49041.9-49060.4" + cell \reg_5 \reg_5 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest15__data_i \reg_5_dest15__data_i + connect \dest15__wen \reg_5_dest15__wen + connect \dest25__data_i \reg_5_dest25__data_i + connect \dest25__wen \reg_5_dest25__wen + connect \r25__data_o \reg_5_r25__data_o + connect \r25__ren \reg_5_r25__ren + connect \r5__data_o \reg_5_r5__data_o + connect \r5__ren \reg_5_r5__ren + connect \src15__data_o \reg_5_src15__data_o + connect \src15__ren \reg_5_src15__ren + connect \src25__data_o \reg_5_src25__data_o + connect \src25__ren \reg_5_src25__ren + connect \src35__data_o \reg_5_src35__data_o + connect \src35__ren \reg_5_src35__ren + connect \w5__data_i \reg_5_w5__data_i + connect \w5__wen \reg_5_w5__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49061.9-49080.4" + cell \reg_6 \reg_6 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest16__data_i \reg_6_dest16__data_i + connect \dest16__wen \reg_6_dest16__wen + connect \dest26__data_i \reg_6_dest26__data_i + connect \dest26__wen \reg_6_dest26__wen + connect \r26__data_o \reg_6_r26__data_o + connect \r26__ren \reg_6_r26__ren + connect \r6__data_o \reg_6_r6__data_o + connect \r6__ren \reg_6_r6__ren + connect \src16__data_o \reg_6_src16__data_o + connect \src16__ren \reg_6_src16__ren + connect \src26__data_o \reg_6_src26__data_o + connect \src26__ren \reg_6_src26__ren + connect \src36__data_o \reg_6_src36__data_o + connect \src36__ren \reg_6_src36__ren + connect \w6__data_i \reg_6_w6__data_i + connect \w6__wen \reg_6_w6__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49081.9-49100.4" + cell \reg_7 \reg_7 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest17__data_i \reg_7_dest17__data_i + connect \dest17__wen \reg_7_dest17__wen + connect \dest27__data_i \reg_7_dest27__data_i + connect \dest27__wen \reg_7_dest27__wen + connect \r27__data_o \reg_7_r27__data_o + connect \r27__ren \reg_7_r27__ren + connect \r7__data_o \reg_7_r7__data_o + connect \r7__ren \reg_7_r7__ren + connect \src17__data_o \reg_7_src17__data_o + connect \src17__ren \reg_7_src17__ren + connect \src27__data_o \reg_7_src27__data_o + connect \src27__ren \reg_7_src27__ren + connect \src37__data_o \reg_7_src37__data_o + connect \src37__ren \reg_7_src37__ren + connect \w7__data_i \reg_7_w7__data_i + connect \w7__wen \reg_7_w7__wen + end + attribute \src "libresoc.v:48555.7-48555.20" + process $proc$libresoc.v:48555$3057 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:48881.13-48881.30" + process $proc$libresoc.v:48881$3058 + assign { } { } + assign $1\ren_delay[7:0] 8'00000000 + sync always + sync init + update \ren_delay $1\ren_delay[7:0] + end + attribute \src "libresoc.v:48883.13-48883.35" + process $proc$libresoc.v:48883$3059 + assign { } { } + assign $0\ren_delay$17[7:0]$3060 8'00000000 + sync always + sync init + update \ren_delay$17 $0\ren_delay$17[7:0]$3060 + end + attribute \src "libresoc.v:48887.13-48887.35" + process $proc$libresoc.v:48887$3061 + assign { } { } + assign $0\ren_delay$34[7:0]$3062 8'00000000 + sync always + sync init + update \ren_delay$34 $0\ren_delay$34[7:0]$3062 + end + attribute \src "libresoc.v:48935.3-48936.43" + process $proc$libresoc.v:48935$3040 + assign { } { } + assign $0\ren_delay$34[7:0]$3041 \ren_delay$34$next + sync posedge \coresync_clk + update \ren_delay$34 $0\ren_delay$34[7:0]$3041 + end + attribute \src "libresoc.v:48937.3-48938.43" + process $proc$libresoc.v:48937$3042 + assign { } { } + assign $0\ren_delay$17[7:0]$3043 \ren_delay$17$next + sync posedge \coresync_clk + update \ren_delay$17 $0\ren_delay$17[7:0]$3043 + end + attribute \src "libresoc.v:48939.3-48940.35" + process $proc$libresoc.v:48939$3044 + assign { } { } + assign $0\ren_delay[7:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[7:0] + end + attribute \src "libresoc.v:49101.3-49109.6" + process $proc$libresoc.v:49101$3045 + assign { } { } + assign { } { } + assign $0\ren_delay$17$next[7:0]$3046 $1\ren_delay$17$next[7:0]$3047 + attribute \src "libresoc.v:49102.5-49102.29" + switch \initial + attribute \src "libresoc.v:49102.9-49102.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$17$next[7:0]$3047 8'00000000 + case + assign $1\ren_delay$17$next[7:0]$3047 \src2__ren + end + sync always + update \ren_delay$17$next $0\ren_delay$17$next[7:0]$3046 + end + attribute \src "libresoc.v:49110.3-49119.6" + process $proc$libresoc.v:49110$3048 + assign { } { } + assign { } { } + assign $0\src2__data_o[3:0] $1\src2__data_o[3:0] + attribute \src "libresoc.v:49111.5-49111.29" + switch \initial + attribute \src "libresoc.v:49111.9-49111.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$18 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src2__data_o[3:0] \$32 + case + assign $1\src2__data_o[3:0] 4'0000 + end + sync always + update \src2__data_o $0\src2__data_o[3:0] + end + attribute \src "libresoc.v:49120.3-49128.6" + process $proc$libresoc.v:49120$3049 + assign { } { } + assign { } { } + assign $0\ren_delay$34$next[7:0]$3050 $1\ren_delay$34$next[7:0]$3051 + attribute \src "libresoc.v:49121.5-49121.29" + switch \initial + attribute \src "libresoc.v:49121.9-49121.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$34$next[7:0]$3051 8'00000000 + case + assign $1\ren_delay$34$next[7:0]$3051 \src3__ren + end + sync always + update \ren_delay$34$next $0\ren_delay$34$next[7:0]$3050 + end + attribute \src "libresoc.v:49129.3-49138.6" + process $proc$libresoc.v:49129$3052 + assign { } { } + assign { } { } + assign $0\src3__data_o[3:0] $1\src3__data_o[3:0] + attribute \src "libresoc.v:49130.5-49130.29" + switch \initial + attribute \src "libresoc.v:49130.9-49130.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$35 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src3__data_o[3:0] \$49 + case + assign $1\src3__data_o[3:0] 4'0000 + end + sync always + update \src3__data_o $0\src3__data_o[3:0] + end + attribute \src "libresoc.v:49139.3-49147.6" + process $proc$libresoc.v:49139$3053 + assign { } { } + assign { } { } + assign $0\ren_delay$next[7:0]$3054 $1\ren_delay$next[7:0]$3055 + attribute \src "libresoc.v:49140.5-49140.29" + switch \initial + attribute \src "libresoc.v:49140.9-49140.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$next[7:0]$3055 8'00000000 + case + assign $1\ren_delay$next[7:0]$3055 \src1__ren + end + sync always + update \ren_delay$next $0\ren_delay$next[7:0]$3054 + end + attribute \src "libresoc.v:49148.3-49157.6" + process $proc$libresoc.v:49148$3056 + assign { } { } + assign { } { } + assign $0\src1__data_o[3:0] $1\src1__data_o[3:0] + attribute \src "libresoc.v:49149.5-49149.29" + switch \initial + attribute \src "libresoc.v:49149.9-49149.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src1__data_o[3:0] \$15 + case + assign $1\src1__data_o[3:0] 4'0000 + end + sync always + update \src1__data_o $0\src1__data_o[3:0] + end + connect \$9 $or$libresoc.v:48911$3016_Y + connect \$11 $or$libresoc.v:48912$3017_Y + connect \$13 $or$libresoc.v:48913$3018_Y + connect \$15 $or$libresoc.v:48914$3019_Y + connect \$18 $reduce_or$libresoc.v:48915$3020_Y + connect \$1 $reduce_or$libresoc.v:48916$3021_Y + connect \$20 $or$libresoc.v:48917$3022_Y + connect \$22 $or$libresoc.v:48918$3023_Y + connect \$24 $or$libresoc.v:48919$3024_Y + connect \$26 $or$libresoc.v:48920$3025_Y + connect \$28 $or$libresoc.v:48921$3026_Y + connect \$30 $or$libresoc.v:48922$3027_Y + connect \$32 $or$libresoc.v:48923$3028_Y + connect \$35 $reduce_or$libresoc.v:48924$3029_Y + connect \$37 $or$libresoc.v:48925$3030_Y + connect \$3 $or$libresoc.v:48926$3031_Y + connect \$39 $or$libresoc.v:48927$3032_Y + connect \$41 $or$libresoc.v:48928$3033_Y + connect \$43 $or$libresoc.v:48929$3034_Y + connect \$45 $or$libresoc.v:48930$3035_Y + connect \$47 $or$libresoc.v:48931$3036_Y + connect \$49 $or$libresoc.v:48932$3037_Y + connect \$5 $or$libresoc.v:48933$3038_Y + connect \$7 $or$libresoc.v:48934$3039_Y + connect \wen$51 8'00000000 + connect \data_i$52 4'0000 + connect { \reg_7_w7__wen \reg_6_w6__wen \reg_5_w5__wen \reg_4_w4__wen \reg_3_w3__wen \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } \full_wr__wen + connect { \reg_7_w7__data_i \reg_6_w6__data_i \reg_5_w5__data_i \reg_4_w4__data_i \reg_3_w3__data_i \reg_2_w2__data_i \reg_1_w1__data_i \reg_0_w0__data_i } \full_wr__data_i + connect { \reg_7_r27__ren \reg_6_r26__ren \reg_5_r25__ren \reg_4_r24__ren \reg_3_r23__ren \reg_2_r22__ren \reg_1_r21__ren \reg_0_r20__ren } \full_rd2__ren + connect \full_rd2__data_o { \reg_7_r27__data_o \reg_6_r26__data_o \reg_5_r25__data_o \reg_4_r24__data_o \reg_3_r23__data_o \reg_2_r22__data_o \reg_1_r21__data_o \reg_0_r20__data_o } + connect { \reg_7_r7__ren \reg_6_r6__ren \reg_5_r5__ren \reg_4_r4__ren \reg_3_r3__ren \reg_2_r2__ren \reg_1_r1__ren \reg_0_r0__ren } \full_rd__ren + connect \full_rd__data_o { \reg_7_r7__data_o \reg_6_r6__data_o \reg_5_r5__data_o \reg_4_r4__data_o \reg_3_r3__data_o \reg_2_r2__data_o \reg_1_r1__data_o \reg_0_r0__data_o } + connect \reg_7_dest27__data_i 4'0000 + connect \reg_6_dest26__data_i 4'0000 + connect \reg_5_dest25__data_i 4'0000 + connect \reg_4_dest24__data_i 4'0000 + connect \reg_3_dest23__data_i 4'0000 + connect \reg_2_dest22__data_i 4'0000 + connect \reg_1_dest21__data_i 4'0000 + connect \reg_0_dest20__data_i 4'0000 + connect { \reg_7_dest27__wen \reg_6_dest26__wen \reg_5_dest25__wen \reg_4_dest24__wen \reg_3_dest23__wen \reg_2_dest22__wen \reg_1_dest21__wen \reg_0_dest20__wen } 8'00000000 + connect \reg_7_dest17__data_i \data_i + connect \reg_6_dest16__data_i \data_i + connect \reg_5_dest15__data_i \data_i + connect \reg_4_dest14__data_i \data_i + connect \reg_3_dest13__data_i \data_i + connect \reg_2_dest12__data_i \data_i + connect \reg_1_dest11__data_i \data_i + connect \reg_0_dest10__data_i \data_i + connect { \reg_7_dest17__wen \reg_6_dest16__wen \reg_5_dest15__wen \reg_4_dest14__wen \reg_3_dest13__wen \reg_2_dest12__wen \reg_1_dest11__wen \reg_0_dest10__wen } \wen + connect { \reg_7_src37__ren \reg_6_src36__ren \reg_5_src35__ren \reg_4_src34__ren \reg_3_src33__ren \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren + connect { \reg_7_src27__ren \reg_6_src26__ren \reg_5_src25__ren \reg_4_src24__ren \reg_3_src23__ren \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren + connect { \reg_7_src17__ren \reg_6_src16__ren \reg_5_src15__ren \reg_4_src14__ren \reg_3_src13__ren \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren +end +attribute \src "libresoc.v:49191.1-50242.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0" +attribute \generator "nMigen" +module \cr0 + attribute \src "libresoc.v:49843.3-49844.25" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:50016.3-50027.6" + wire width 12 $0\alu_cr0_cr_op__fn_unit$next[11:0]$3182 + attribute \src "libresoc.v:49815.3-49816.61" + wire width 12 $0\alu_cr0_cr_op__fn_unit[11:0] + attribute \src "libresoc.v:50016.3-50027.6" + wire width 32 $0\alu_cr0_cr_op__insn$next[31:0]$3183 + attribute \src "libresoc.v:49817.3-49818.55" + wire width 32 $0\alu_cr0_cr_op__insn[31:0] + attribute \src "libresoc.v:50016.3-50027.6" + wire width 7 $0\alu_cr0_cr_op__insn_type$next[6:0]$3184 + attribute \src "libresoc.v:49813.3-49814.65" + wire width 7 $0\alu_cr0_cr_op__insn_type[6:0] + attribute \src "libresoc.v:49841.3-49842.39" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:50163.3-50171.6" + wire $0\alu_l_r_alu$next[0:0]$3234 + attribute \src "libresoc.v:49785.3-49786.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:50154.3-50162.6" + wire $0\alui_l_r_alui$next[0:0]$3231 + attribute \src "libresoc.v:49787.3-49788.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:50028.3-50049.6" + wire width 64 $0\data_r0__o$next[63:0]$3189 + attribute \src "libresoc.v:49809.3-49810.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "libresoc.v:50028.3-50049.6" + wire $0\data_r0__o_ok$next[0:0]$3190 + attribute \src "libresoc.v:49811.3-49812.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "libresoc.v:50050.3-50071.6" + wire width 32 $0\data_r1__full_cr$next[31:0]$3197 + attribute \src "libresoc.v:49805.3-49806.49" + wire width 32 $0\data_r1__full_cr[31:0] + attribute \src "libresoc.v:50050.3-50071.6" + wire $0\data_r1__full_cr_ok$next[0:0]$3198 + attribute \src "libresoc.v:49807.3-49808.55" + wire $0\data_r1__full_cr_ok[0:0] + attribute \src "libresoc.v:50072.3-50093.6" + wire width 4 $0\data_r2__cr_a$next[3:0]$3205 + attribute \src "libresoc.v:49801.3-49802.43" + wire width 4 $0\data_r2__cr_a[3:0] + attribute \src "libresoc.v:50072.3-50093.6" + wire $0\data_r2__cr_a_ok$next[0:0]$3206 + attribute \src "libresoc.v:49803.3-49804.49" + wire $0\data_r2__cr_a_ok[0:0] + attribute \src "libresoc.v:50172.3-50181.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:50182.3-50191.6" + wire width 32 $0\dest2_o[31:0] + attribute \src "libresoc.v:50192.3-50201.6" + wire width 4 $0\dest3_o[3:0] + attribute \src "libresoc.v:49192.7-49192.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:49971.3-49979.6" + wire $0\opc_l_r_opc$next[0:0]$3167 + attribute \src "libresoc.v:49827.3-49828.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:49962.3-49970.6" + wire $0\opc_l_s_opc$next[0:0]$3164 + attribute \src "libresoc.v:49829.3-49830.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:50202.3-50210.6" + wire width 3 $0\prev_wr_go$next[2:0]$3240 + attribute \src "libresoc.v:49839.3-49840.37" + wire width 3 $0\prev_wr_go[2:0] + attribute \src "libresoc.v:49916.3-49925.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:50007.3-50015.6" + wire width 3 $0\req_l_r_req$next[2:0]$3179 + attribute \src "libresoc.v:49819.3-49820.39" + wire width 3 $0\req_l_r_req[2:0] + attribute \src "libresoc.v:49998.3-50006.6" + wire width 3 $0\req_l_s_req$next[2:0]$3176 + attribute \src "libresoc.v:49821.3-49822.39" + wire width 3 $0\req_l_s_req[2:0] + attribute \src "libresoc.v:49935.3-49943.6" + wire $0\rok_l_r_rdok$next[0:0]$3155 + attribute \src "libresoc.v:49835.3-49836.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:49926.3-49934.6" + wire $0\rok_l_s_rdok$next[0:0]$3152 + attribute \src "libresoc.v:49837.3-49838.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:49953.3-49961.6" + wire $0\rst_l_r_rst$next[0:0]$3161 + attribute \src "libresoc.v:49831.3-49832.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:49944.3-49952.6" + wire $0\rst_l_s_rst$next[0:0]$3158 + attribute \src "libresoc.v:49833.3-49834.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:49989.3-49997.6" + wire width 6 $0\src_l_r_src$next[5:0]$3173 + attribute \src "libresoc.v:49823.3-49824.39" + wire width 6 $0\src_l_r_src[5:0] + attribute \src "libresoc.v:49980.3-49988.6" + wire width 6 $0\src_l_s_src$next[5:0]$3170 + attribute \src "libresoc.v:49825.3-49826.39" + wire width 6 $0\src_l_s_src[5:0] + attribute \src "libresoc.v:50094.3-50103.6" + wire width 64 $0\src_r0$next[63:0]$3213 + attribute \src "libresoc.v:49799.3-49800.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:50104.3-50113.6" + wire width 64 $0\src_r1$next[63:0]$3216 + attribute \src "libresoc.v:49797.3-49798.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:50114.3-50123.6" + wire width 32 $0\src_r2$next[31:0]$3219 + attribute \src "libresoc.v:49795.3-49796.29" + wire width 32 $0\src_r2[31:0] + attribute \src "libresoc.v:50124.3-50133.6" + wire width 4 $0\src_r3$next[3:0]$3222 + attribute \src "libresoc.v:49793.3-49794.29" + wire width 4 $0\src_r3[3:0] + attribute \src "libresoc.v:50134.3-50143.6" + wire width 4 $0\src_r4$next[3:0]$3225 + attribute \src "libresoc.v:49791.3-49792.29" + wire width 4 $0\src_r4[3:0] + attribute \src "libresoc.v:50144.3-50153.6" + wire width 4 $0\src_r5$next[3:0]$3228 + attribute \src "libresoc.v:49789.3-49790.29" + wire width 4 $0\src_r5[3:0] + attribute \src "libresoc.v:49310.7-49310.24" + wire $1\all_rd_dly[0:0] + attribute \src "libresoc.v:50016.3-50027.6" + wire width 12 $1\alu_cr0_cr_op__fn_unit$next[11:0]$3185 + attribute \src "libresoc.v:49339.14-49339.46" + wire width 12 $1\alu_cr0_cr_op__fn_unit[11:0] + attribute \src "libresoc.v:50016.3-50027.6" + wire width 32 $1\alu_cr0_cr_op__insn$next[31:0]$3186 + attribute \src "libresoc.v:49343.14-49343.41" + wire width 32 $1\alu_cr0_cr_op__insn[31:0] + attribute \src "libresoc.v:50016.3-50027.6" + wire width 7 $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 + attribute \src "libresoc.v:49421.13-49421.45" + wire width 7 $1\alu_cr0_cr_op__insn_type[6:0] + attribute \src "libresoc.v:49445.7-49445.26" + wire $1\alu_done_dly[0:0] + attribute \src "libresoc.v:50163.3-50171.6" + wire $1\alu_l_r_alu$next[0:0]$3235 + attribute \src "libresoc.v:49453.7-49453.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "libresoc.v:50154.3-50162.6" + wire $1\alui_l_r_alui$next[0:0]$3232 + attribute \src "libresoc.v:49465.7-49465.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "libresoc.v:50028.3-50049.6" + wire width 64 $1\data_r0__o$next[63:0]$3191 + attribute \src "libresoc.v:49499.14-49499.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "libresoc.v:50028.3-50049.6" + wire $1\data_r0__o_ok$next[0:0]$3192 + attribute \src "libresoc.v:49503.7-49503.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "libresoc.v:50050.3-50071.6" + wire width 32 $1\data_r1__full_cr$next[31:0]$3199 + attribute \src "libresoc.v:49507.14-49507.38" + wire width 32 $1\data_r1__full_cr[31:0] + attribute \src "libresoc.v:50050.3-50071.6" + wire $1\data_r1__full_cr_ok$next[0:0]$3200 + attribute \src "libresoc.v:49511.7-49511.33" + wire $1\data_r1__full_cr_ok[0:0] + attribute \src "libresoc.v:50072.3-50093.6" + wire width 4 $1\data_r2__cr_a$next[3:0]$3207 + attribute \src "libresoc.v:49515.13-49515.33" + wire width 4 $1\data_r2__cr_a[3:0] + attribute \src "libresoc.v:50072.3-50093.6" + wire $1\data_r2__cr_a_ok$next[0:0]$3208 + attribute \src "libresoc.v:49519.7-49519.30" + wire $1\data_r2__cr_a_ok[0:0] + attribute \src "libresoc.v:50172.3-50181.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "libresoc.v:50182.3-50191.6" + wire width 32 $1\dest2_o[31:0] + attribute \src "libresoc.v:50192.3-50201.6" + wire width 4 $1\dest3_o[3:0] + attribute \src "libresoc.v:49971.3-49979.6" + wire $1\opc_l_r_opc$next[0:0]$3168 + attribute \src "libresoc.v:49538.7-49538.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "libresoc.v:49962.3-49970.6" + wire $1\opc_l_s_opc$next[0:0]$3165 + attribute \src "libresoc.v:49542.7-49542.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "libresoc.v:50202.3-50210.6" + wire width 3 $1\prev_wr_go$next[2:0]$3241 + attribute \src "libresoc.v:49639.13-49639.30" + wire width 3 $1\prev_wr_go[2:0] + attribute \src "libresoc.v:49916.3-49925.6" + wire $1\req_done[0:0] + attribute \src "libresoc.v:50007.3-50015.6" + wire width 3 $1\req_l_r_req$next[2:0]$3180 + attribute \src "libresoc.v:49647.13-49647.31" + wire width 3 $1\req_l_r_req[2:0] + attribute \src "libresoc.v:49998.3-50006.6" + wire width 3 $1\req_l_s_req$next[2:0]$3177 + attribute \src "libresoc.v:49651.13-49651.31" + wire width 3 $1\req_l_s_req[2:0] + attribute \src "libresoc.v:49935.3-49943.6" + wire $1\rok_l_r_rdok$next[0:0]$3156 + attribute \src "libresoc.v:49663.7-49663.26" + wire $1\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:49926.3-49934.6" + wire $1\rok_l_s_rdok$next[0:0]$3153 + attribute \src "libresoc.v:49667.7-49667.26" + wire $1\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:49953.3-49961.6" + wire $1\rst_l_r_rst$next[0:0]$3162 + attribute \src "libresoc.v:49671.7-49671.25" + wire $1\rst_l_r_rst[0:0] + attribute \src "libresoc.v:49944.3-49952.6" + wire $1\rst_l_s_rst$next[0:0]$3159 + attribute \src "libresoc.v:49675.7-49675.25" + wire $1\rst_l_s_rst[0:0] + attribute \src "libresoc.v:49989.3-49997.6" + wire width 6 $1\src_l_r_src$next[5:0]$3174 + attribute \src "libresoc.v:49695.13-49695.32" + wire width 6 $1\src_l_r_src[5:0] + attribute \src "libresoc.v:49980.3-49988.6" + wire width 6 $1\src_l_s_src$next[5:0]$3171 + attribute \src "libresoc.v:49699.13-49699.32" + wire width 6 $1\src_l_s_src[5:0] + attribute \src "libresoc.v:50094.3-50103.6" + wire width 64 $1\src_r0$next[63:0]$3214 + attribute \src "libresoc.v:49703.14-49703.43" + wire width 64 $1\src_r0[63:0] + attribute \src "libresoc.v:50104.3-50113.6" + wire width 64 $1\src_r1$next[63:0]$3217 + attribute \src "libresoc.v:49707.14-49707.43" + wire width 64 $1\src_r1[63:0] + attribute \src "libresoc.v:50114.3-50123.6" + wire width 32 $1\src_r2$next[31:0]$3220 + attribute \src "libresoc.v:49711.14-49711.28" + wire width 32 $1\src_r2[31:0] + attribute \src "libresoc.v:50124.3-50133.6" + wire width 4 $1\src_r3$next[3:0]$3223 + attribute \src "libresoc.v:49715.13-49715.26" + wire width 4 $1\src_r3[3:0] + attribute \src "libresoc.v:50134.3-50143.6" + wire width 4 $1\src_r4$next[3:0]$3226 + attribute \src "libresoc.v:49719.13-49719.26" + wire width 4 $1\src_r4[3:0] + attribute \src "libresoc.v:50144.3-50153.6" + wire width 4 $1\src_r5$next[3:0]$3229 + attribute \src "libresoc.v:49723.13-49723.26" + wire width 4 $1\src_r5[3:0] + attribute \src "libresoc.v:50028.3-50049.6" + wire width 64 $2\data_r0__o$next[63:0]$3193 + attribute \src "libresoc.v:50028.3-50049.6" + wire $2\data_r0__o_ok$next[0:0]$3194 + attribute \src "libresoc.v:50050.3-50071.6" + wire width 32 $2\data_r1__full_cr$next[31:0]$3201 + attribute \src "libresoc.v:50050.3-50071.6" + wire $2\data_r1__full_cr_ok$next[0:0]$3202 + attribute \src "libresoc.v:50072.3-50093.6" + wire width 4 $2\data_r2__cr_a$next[3:0]$3209 + attribute \src "libresoc.v:50072.3-50093.6" + wire $2\data_r2__cr_a_ok$next[0:0]$3210 + attribute \src "libresoc.v:50028.3-50049.6" + wire $3\data_r0__o_ok$next[0:0]$3195 + attribute \src "libresoc.v:50050.3-50071.6" + wire $3\data_r1__full_cr_ok$next[0:0]$3203 + attribute \src "libresoc.v:50072.3-50093.6" + wire $3\data_r2__cr_a_ok$next[0:0]$3211 + attribute \src "libresoc.v:49729.18-49729.112" + wire width 6 $and$libresoc.v:49729$3064_Y + attribute \src "libresoc.v:49730.19-49730.125" + wire $and$libresoc.v:49730$3065_Y + attribute \src "libresoc.v:49731.19-49731.125" + wire $and$libresoc.v:49731$3066_Y + attribute \src "libresoc.v:49732.19-49732.125" + wire $and$libresoc.v:49732$3067_Y + attribute \src "libresoc.v:49733.19-49733.141" + wire width 3 $and$libresoc.v:49733$3068_Y + attribute \src "libresoc.v:49734.19-49734.121" + wire width 3 $and$libresoc.v:49734$3069_Y + attribute \src "libresoc.v:49735.19-49735.127" + wire $and$libresoc.v:49735$3070_Y + attribute \src "libresoc.v:49736.19-49736.127" + wire $and$libresoc.v:49736$3071_Y + attribute \src "libresoc.v:49737.19-49737.127" + wire $and$libresoc.v:49737$3072_Y + attribute \src "libresoc.v:49738.18-49738.110" + wire $and$libresoc.v:49738$3073_Y + attribute \src "libresoc.v:49740.18-49740.98" + wire $and$libresoc.v:49740$3075_Y + attribute \src "libresoc.v:49742.18-49742.100" + wire $and$libresoc.v:49742$3077_Y + attribute \src "libresoc.v:49743.18-49743.149" + wire width 3 $and$libresoc.v:49743$3078_Y + attribute \src "libresoc.v:49745.18-49745.119" + wire width 3 $and$libresoc.v:49745$3080_Y + attribute \src "libresoc.v:49748.18-49748.116" + wire $and$libresoc.v:49748$3083_Y + attribute \src "libresoc.v:49752.17-49752.123" + wire $and$libresoc.v:49752$3087_Y + attribute \src "libresoc.v:49754.18-49754.113" + wire $and$libresoc.v:49754$3089_Y + attribute \src "libresoc.v:49755.18-49755.125" + wire width 3 $and$libresoc.v:49755$3090_Y + attribute \src "libresoc.v:49757.18-49757.112" + wire $and$libresoc.v:49757$3092_Y + attribute \src "libresoc.v:49759.18-49759.125" + wire $and$libresoc.v:49759$3094_Y + attribute \src "libresoc.v:49760.18-49760.125" + wire $and$libresoc.v:49760$3095_Y + attribute \src "libresoc.v:49761.18-49761.117" + wire $and$libresoc.v:49761$3096_Y + attribute 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$and$libresoc.v:49767$3102_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:49770$3105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:49770$3105_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:49771$3106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \full_cr_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:49771$3106_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:49772$3107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cr_a_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:49772$3107_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + cell $and $and$libresoc.v:49780$3115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_cr0_p_ready_o + connect \B \alui_l_q_alui + connect \Y $and$libresoc.v:49780$3115_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + cell $and $and$libresoc.v:49781$3116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_cr0_n_valid_o + connect \B \alu_l_q_alu + connect \Y $and$libresoc.v:49781$3116_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:49782$3117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \src_l_q_src + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$libresoc.v:49782$3117_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:49783$3118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$93 + connect \B 6'111111 + connect \Y $and$libresoc.v:49783$3118_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $eq$libresoc.v:49756$3091 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$43 + connect \B 1'0 + connect \Y $eq$libresoc.v:49756$3091_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $eq$libresoc.v:49758$3093 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $eq$libresoc.v:49758$3093_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:49739$3074 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $not$libresoc.v:49739$3074_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:49741$3076 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $not$libresoc.v:49741$3076_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:49744$3079 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wrmask_o + connect \Y $not$libresoc.v:49744$3079_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:49747$3082 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:49747$3082_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$libresoc.v:49753$3088 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_cr0_n_ready_i + connect \Y $not$libresoc.v:49753$3088_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$libresoc.v:49768$3103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_rd__rel_o + connect \Y $not$libresoc.v:49768$3103_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$libresoc.v:49784$3119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_rdmaskn_i + connect \Y $not$libresoc.v:49784$3119_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$libresoc.v:49751$3086 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$33 + connect \B \$35 + connect \Y $or$libresoc.v:49751$3086_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$libresoc.v:49762$3097 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:49762$3097_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$libresoc.v:49763$3098 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:49763$3098_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$libresoc.v:49764$3099 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:49764$3099_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$libresoc.v:49765$3100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:49765$3100_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:49769$3104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$libresoc.v:49769$3104_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:49779$3114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$6 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:49779$3114_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:49728$3063 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $reduce_and$libresoc.v:49728$3063_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:49746$3081 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$27 + connect \Y $reduce_or$libresoc.v:49746$3081_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:49749$3084 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:49749$3084_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:49750$3085 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:49750$3085_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:49773$3108 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $ternary$libresoc.v:49773$3108_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:49774$3109 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src2_i + connect \S \src_l_q_src [1] + connect \Y $ternary$libresoc.v:49774$3109_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:49775$3110 + parameter \WIDTH 32 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:49775$3110_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:49776$3111 + parameter \WIDTH 4 + connect \A \src_r3 + connect \B \src4_i + connect \S \src_l_q_src [3] + connect \Y $ternary$libresoc.v:49776$3111_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:49777$3112 + parameter \WIDTH 4 + connect \A \src_r4 + connect \B \src5_i + connect \S \src_l_q_src [4] + connect \Y $ternary$libresoc.v:49777$3112_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:49778$3113 + parameter \WIDTH 4 + connect \A \src_r5 + connect \B \src6_i + connect \S \src_l_q_src [5] + connect \Y $ternary$libresoc.v:49778$3113_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49845.11-49867.4" + cell \alu_cr0 \alu_cr0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \alu_cr0_cr_a + connect \cr_a$2 \alu_cr0_cr_a$2 + connect \cr_a_ok \cr_a_ok + connect \cr_b \alu_cr0_cr_b + connect \cr_c \alu_cr0_cr_c + connect \cr_op__fn_unit \alu_cr0_cr_op__fn_unit + connect \cr_op__insn \alu_cr0_cr_op__insn + connect \cr_op__insn_type \alu_cr0_cr_op__insn_type + connect \full_cr \alu_cr0_full_cr + connect \full_cr$1 \alu_cr0_full_cr$1 + connect \full_cr_ok \full_cr_ok + connect \n_ready_i \alu_cr0_n_ready_i + connect \n_valid_o \alu_cr0_n_valid_o + connect \o \alu_cr0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_cr0_p_ready_o + connect \p_valid_i \alu_cr0_p_valid_i + connect \ra \alu_cr0_ra + connect \rb \alu_cr0_rb + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49868.14-49874.4" + cell \alu_l$16 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49875.15-49881.4" + cell \alui_l$15 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49882.14-49888.4" + cell \opc_l$11 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49889.14-49895.4" + cell \req_l$12 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49896.14-49902.4" + cell \rok_l$14 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49903.14-49908.4" + cell \rst_l$13 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49909.14-49915.4" + cell \src_l$10 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "libresoc.v:49192.7-49192.20" + process $proc$libresoc.v:49192$3242 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:49310.7-49310.24" + process $proc$libresoc.v:49310$3243 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "libresoc.v:49339.14-49339.46" + process $proc$libresoc.v:49339$3244 + assign { } { } + assign $1\alu_cr0_cr_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \alu_cr0_cr_op__fn_unit $1\alu_cr0_cr_op__fn_unit[11:0] + end + attribute \src "libresoc.v:49343.14-49343.41" + process $proc$libresoc.v:49343$3245 + assign { } { } + assign $1\alu_cr0_cr_op__insn[31:0] 0 + sync always + sync init + update \alu_cr0_cr_op__insn $1\alu_cr0_cr_op__insn[31:0] + end + attribute \src "libresoc.v:49421.13-49421.45" + process $proc$libresoc.v:49421$3246 + assign { } { } + assign $1\alu_cr0_cr_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_cr0_cr_op__insn_type $1\alu_cr0_cr_op__insn_type[6:0] + end + attribute \src "libresoc.v:49445.7-49445.26" + process $proc$libresoc.v:49445$3247 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "libresoc.v:49453.7-49453.25" + process $proc$libresoc.v:49453$3248 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:49465.7-49465.27" + process $proc$libresoc.v:49465$3249 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:49499.14-49499.47" + process $proc$libresoc.v:49499$3250 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "libresoc.v:49503.7-49503.27" + process $proc$libresoc.v:49503$3251 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:49507.14-49507.38" + process $proc$libresoc.v:49507$3252 + assign { } { } + assign $1\data_r1__full_cr[31:0] 0 + sync always + sync init + update \data_r1__full_cr $1\data_r1__full_cr[31:0] + end + attribute \src "libresoc.v:49511.7-49511.33" + process $proc$libresoc.v:49511$3253 + assign { } { } + assign $1\data_r1__full_cr_ok[0:0] 1'0 + sync always + sync init + update \data_r1__full_cr_ok $1\data_r1__full_cr_ok[0:0] + end + attribute \src "libresoc.v:49515.13-49515.33" + process $proc$libresoc.v:49515$3254 + assign { } { } + assign $1\data_r2__cr_a[3:0] 4'0000 + sync always + sync init + update \data_r2__cr_a $1\data_r2__cr_a[3:0] + end + attribute \src "libresoc.v:49519.7-49519.30" + process $proc$libresoc.v:49519$3255 + assign { } { } + assign $1\data_r2__cr_a_ok[0:0] 1'0 + sync always + sync init + update \data_r2__cr_a_ok $1\data_r2__cr_a_ok[0:0] + end + attribute \src "libresoc.v:49538.7-49538.25" + process $proc$libresoc.v:49538$3256 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:49542.7-49542.25" + process $proc$libresoc.v:49542$3257 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:49639.13-49639.30" + process $proc$libresoc.v:49639$3258 + assign { } { } + assign $1\prev_wr_go[2:0] 3'000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[2:0] + end + attribute \src "libresoc.v:49647.13-49647.31" + process $proc$libresoc.v:49647$3259 + assign { } { } + assign $1\req_l_r_req[2:0] 3'111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[2:0] + end + attribute \src "libresoc.v:49651.13-49651.31" + process $proc$libresoc.v:49651$3260 + assign { } { } + assign $1\req_l_s_req[2:0] 3'000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[2:0] + end + attribute \src "libresoc.v:49663.7-49663.26" + process $proc$libresoc.v:49663$3261 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:49667.7-49667.26" + process $proc$libresoc.v:49667$3262 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:49671.7-49671.25" + process $proc$libresoc.v:49671$3263 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:49675.7-49675.25" + process $proc$libresoc.v:49675$3264 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:49695.13-49695.32" + process $proc$libresoc.v:49695$3265 + assign { } { } + assign $1\src_l_r_src[5:0] 6'111111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[5:0] + end + attribute \src "libresoc.v:49699.13-49699.32" + process $proc$libresoc.v:49699$3266 + assign { } { } + assign $1\src_l_s_src[5:0] 6'000000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[5:0] + end + attribute \src "libresoc.v:49703.14-49703.43" + process $proc$libresoc.v:49703$3267 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:49707.14-49707.43" + process $proc$libresoc.v:49707$3268 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:49711.14-49711.28" + process $proc$libresoc.v:49711$3269 + assign { } { } + assign $1\src_r2[31:0] 0 + sync always + sync init + update \src_r2 $1\src_r2[31:0] + end + attribute \src "libresoc.v:49715.13-49715.26" + process $proc$libresoc.v:49715$3270 + assign { } { } + assign $1\src_r3[3:0] 4'0000 + sync always + sync init + update \src_r3 $1\src_r3[3:0] + end + attribute \src "libresoc.v:49719.13-49719.26" + process $proc$libresoc.v:49719$3271 + assign { } { } + assign $1\src_r4[3:0] 4'0000 + sync always + sync init + update \src_r4 $1\src_r4[3:0] + end + attribute \src "libresoc.v:49723.13-49723.26" + process $proc$libresoc.v:49723$3272 + assign { } { } + assign $1\src_r5[3:0] 4'0000 + sync always + sync init + update \src_r5 $1\src_r5[3:0] + end + attribute \src "libresoc.v:49785.3-49786.39" + process $proc$libresoc.v:49785$3120 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:49787.3-49788.43" + process $proc$libresoc.v:49787$3121 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:49789.3-49790.29" + process $proc$libresoc.v:49789$3122 + assign { } { } + assign $0\src_r5[3:0] \src_r5$next + sync posedge \coresync_clk + update \src_r5 $0\src_r5[3:0] + end + attribute \src "libresoc.v:49791.3-49792.29" + process $proc$libresoc.v:49791$3123 + assign { } { } + assign $0\src_r4[3:0] \src_r4$next + sync posedge \coresync_clk + update \src_r4 $0\src_r4[3:0] + end + attribute \src "libresoc.v:49793.3-49794.29" + process $proc$libresoc.v:49793$3124 + assign { } { } + assign $0\src_r3[3:0] \src_r3$next + sync posedge \coresync_clk + update \src_r3 $0\src_r3[3:0] + end + attribute \src "libresoc.v:49795.3-49796.29" + process $proc$libresoc.v:49795$3125 + assign { } { } + assign $0\src_r2[31:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[31:0] + end + attribute \src "libresoc.v:49797.3-49798.29" + process $proc$libresoc.v:49797$3126 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:49799.3-49800.29" + process $proc$libresoc.v:49799$3127 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:49801.3-49802.43" + process $proc$libresoc.v:49801$3128 + assign { } { } + assign $0\data_r2__cr_a[3:0] \data_r2__cr_a$next + sync posedge \coresync_clk + update \data_r2__cr_a $0\data_r2__cr_a[3:0] + end + attribute \src "libresoc.v:49803.3-49804.49" + process $proc$libresoc.v:49803$3129 + assign { } { } + assign $0\data_r2__cr_a_ok[0:0] \data_r2__cr_a_ok$next + sync posedge \coresync_clk + update \data_r2__cr_a_ok $0\data_r2__cr_a_ok[0:0] + end + attribute \src "libresoc.v:49805.3-49806.49" + process $proc$libresoc.v:49805$3130 + assign { } { } + assign $0\data_r1__full_cr[31:0] \data_r1__full_cr$next + sync posedge \coresync_clk + update \data_r1__full_cr $0\data_r1__full_cr[31:0] + end + attribute \src "libresoc.v:49807.3-49808.55" + process $proc$libresoc.v:49807$3131 + assign { } { } + assign $0\data_r1__full_cr_ok[0:0] \data_r1__full_cr_ok$next + sync posedge \coresync_clk + update \data_r1__full_cr_ok $0\data_r1__full_cr_ok[0:0] + end + attribute \src "libresoc.v:49809.3-49810.37" + process $proc$libresoc.v:49809$3132 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "libresoc.v:49811.3-49812.43" + process $proc$libresoc.v:49811$3133 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:49813.3-49814.65" + process $proc$libresoc.v:49813$3134 + assign { } { } + assign $0\alu_cr0_cr_op__insn_type[6:0] \alu_cr0_cr_op__insn_type$next + sync posedge \coresync_clk + update \alu_cr0_cr_op__insn_type $0\alu_cr0_cr_op__insn_type[6:0] + end + attribute \src "libresoc.v:49815.3-49816.61" + process $proc$libresoc.v:49815$3135 + assign { } { } + assign $0\alu_cr0_cr_op__fn_unit[11:0] \alu_cr0_cr_op__fn_unit$next + sync posedge \coresync_clk + update \alu_cr0_cr_op__fn_unit $0\alu_cr0_cr_op__fn_unit[11:0] + end + attribute \src "libresoc.v:49817.3-49818.55" + process $proc$libresoc.v:49817$3136 + assign { } { } + assign $0\alu_cr0_cr_op__insn[31:0] \alu_cr0_cr_op__insn$next + sync posedge \coresync_clk + update \alu_cr0_cr_op__insn $0\alu_cr0_cr_op__insn[31:0] + end + attribute \src "libresoc.v:49819.3-49820.39" + process $proc$libresoc.v:49819$3137 + assign { } { } + assign $0\req_l_r_req[2:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[2:0] + end + attribute \src "libresoc.v:49821.3-49822.39" + process $proc$libresoc.v:49821$3138 + assign { } { } + assign $0\req_l_s_req[2:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[2:0] + end + attribute \src "libresoc.v:49823.3-49824.39" + process $proc$libresoc.v:49823$3139 + assign { } { } + assign $0\src_l_r_src[5:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[5:0] + end + attribute \src "libresoc.v:49825.3-49826.39" + process $proc$libresoc.v:49825$3140 + assign { } { } + assign $0\src_l_s_src[5:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[5:0] + end + attribute \src "libresoc.v:49827.3-49828.39" + process $proc$libresoc.v:49827$3141 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:49829.3-49830.39" + process $proc$libresoc.v:49829$3142 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:49831.3-49832.39" + process $proc$libresoc.v:49831$3143 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:49833.3-49834.39" + process $proc$libresoc.v:49833$3144 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:49835.3-49836.41" + process $proc$libresoc.v:49835$3145 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:49837.3-49838.41" + process $proc$libresoc.v:49837$3146 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:49839.3-49840.37" + process $proc$libresoc.v:49839$3147 + assign { } { } + assign $0\prev_wr_go[2:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[2:0] + end + attribute \src "libresoc.v:49841.3-49842.39" + process $proc$libresoc.v:49841$3148 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_cr0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "libresoc.v:49843.3-49844.25" + process $proc$libresoc.v:49843$3149 + assign { } { } + assign $0\all_rd_dly[0:0] \$11 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "libresoc.v:49916.3-49925.6" + process $proc$libresoc.v:49916$3150 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:49917.5-49917.29" + switch \initial + attribute \src "libresoc.v:49917.9-49917.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$55 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$47 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "libresoc.v:49926.3-49934.6" + process $proc$libresoc.v:49926$3151 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$3152 $1\rok_l_s_rdok$next[0:0]$3153 + attribute \src "libresoc.v:49927.5-49927.29" + switch \initial + attribute \src "libresoc.v:49927.9-49927.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$3153 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$3153 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$3152 + end + attribute \src "libresoc.v:49935.3-49943.6" + process $proc$libresoc.v:49935$3154 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$3155 $1\rok_l_r_rdok$next[0:0]$3156 + attribute \src "libresoc.v:49936.5-49936.29" + switch \initial + attribute \src "libresoc.v:49936.9-49936.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$3156 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$3156 \$65 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$3155 + end + attribute \src "libresoc.v:49944.3-49952.6" + process $proc$libresoc.v:49944$3157 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$3158 $1\rst_l_s_rst$next[0:0]$3159 + attribute \src "libresoc.v:49945.5-49945.29" + switch \initial + attribute \src "libresoc.v:49945.9-49945.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$3159 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$3159 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$3158 + end + attribute \src "libresoc.v:49953.3-49961.6" + process $proc$libresoc.v:49953$3160 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$3161 $1\rst_l_r_rst$next[0:0]$3162 + attribute \src "libresoc.v:49954.5-49954.29" + switch \initial + attribute \src "libresoc.v:49954.9-49954.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$3162 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$3162 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$3161 + end + attribute \src "libresoc.v:49962.3-49970.6" + process $proc$libresoc.v:49962$3163 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$3164 $1\opc_l_s_opc$next[0:0]$3165 + attribute \src "libresoc.v:49963.5-49963.29" + switch \initial + attribute \src "libresoc.v:49963.9-49963.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$3165 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$3165 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$3164 + end + attribute \src "libresoc.v:49971.3-49979.6" + process $proc$libresoc.v:49971$3166 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$3167 $1\opc_l_r_opc$next[0:0]$3168 + attribute \src "libresoc.v:49972.5-49972.29" + switch \initial + attribute \src "libresoc.v:49972.9-49972.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$3168 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$3168 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$3167 + end + attribute \src "libresoc.v:49980.3-49988.6" + process $proc$libresoc.v:49980$3169 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[5:0]$3170 $1\src_l_s_src$next[5:0]$3171 + attribute \src "libresoc.v:49981.5-49981.29" + switch \initial + attribute \src "libresoc.v:49981.9-49981.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[5:0]$3171 6'000000 + case + assign $1\src_l_s_src$next[5:0]$3171 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[5:0]$3170 + end + attribute \src "libresoc.v:49989.3-49997.6" + process $proc$libresoc.v:49989$3172 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[5:0]$3173 $1\src_l_r_src$next[5:0]$3174 + attribute \src "libresoc.v:49990.5-49990.29" + switch \initial + attribute \src "libresoc.v:49990.9-49990.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[5:0]$3174 6'111111 + case + assign $1\src_l_r_src$next[5:0]$3174 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[5:0]$3173 + end + attribute \src "libresoc.v:49998.3-50006.6" + process $proc$libresoc.v:49998$3175 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[2:0]$3176 $1\req_l_s_req$next[2:0]$3177 + attribute \src "libresoc.v:49999.5-49999.29" + switch \initial + attribute \src "libresoc.v:49999.9-49999.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[2:0]$3177 3'000 + case + assign $1\req_l_s_req$next[2:0]$3177 \$67 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[2:0]$3176 + end + attribute \src "libresoc.v:50007.3-50015.6" + process $proc$libresoc.v:50007$3178 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[2:0]$3179 $1\req_l_r_req$next[2:0]$3180 + attribute \src "libresoc.v:50008.5-50008.29" + switch \initial + attribute \src "libresoc.v:50008.9-50008.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[2:0]$3180 3'111 + case + assign $1\req_l_r_req$next[2:0]$3180 \$69 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[2:0]$3179 + end + attribute \src "libresoc.v:50016.3-50027.6" + process $proc$libresoc.v:50016$3181 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_cr0_cr_op__fn_unit$next[11:0]$3182 $1\alu_cr0_cr_op__fn_unit$next[11:0]$3185 + assign $0\alu_cr0_cr_op__insn$next[31:0]$3183 $1\alu_cr0_cr_op__insn$next[31:0]$3186 + assign $0\alu_cr0_cr_op__insn_type$next[6:0]$3184 $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 + attribute \src "libresoc.v:50017.5-50017.29" + switch \initial + attribute \src "libresoc.v:50017.9-50017.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_cr0_cr_op__insn$next[31:0]$3186 $1\alu_cr0_cr_op__fn_unit$next[11:0]$3185 $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 } { \oper_i_alu_cr0__insn \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__insn_type } + case + assign $1\alu_cr0_cr_op__fn_unit$next[11:0]$3185 \alu_cr0_cr_op__fn_unit + assign $1\alu_cr0_cr_op__insn$next[31:0]$3186 \alu_cr0_cr_op__insn + assign $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 \alu_cr0_cr_op__insn_type + end + sync always + update \alu_cr0_cr_op__fn_unit$next $0\alu_cr0_cr_op__fn_unit$next[11:0]$3182 + update \alu_cr0_cr_op__insn$next $0\alu_cr0_cr_op__insn$next[31:0]$3183 + update \alu_cr0_cr_op__insn_type$next $0\alu_cr0_cr_op__insn_type$next[6:0]$3184 + end + attribute \src "libresoc.v:50028.3-50049.6" + process $proc$libresoc.v:50028$3188 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$3189 $2\data_r0__o$next[63:0]$3193 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$3190 $3\data_r0__o_ok$next[0:0]$3195 + attribute \src "libresoc.v:50029.5-50029.29" + switch \initial + attribute \src "libresoc.v:50029.9-50029.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$3192 $1\data_r0__o$next[63:0]$3191 } { \o_ok \alu_cr0_o } + case + assign $1\data_r0__o$next[63:0]$3191 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$3192 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$3194 $2\data_r0__o$next[63:0]$3193 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$3193 $1\data_r0__o$next[63:0]$3191 + assign $2\data_r0__o_ok$next[0:0]$3194 $1\data_r0__o_ok$next[0:0]$3192 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$3195 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$3195 $2\data_r0__o_ok$next[0:0]$3194 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$3189 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$3190 + end + attribute \src "libresoc.v:50050.3-50071.6" + process $proc$libresoc.v:50050$3196 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__full_cr$next[31:0]$3197 $2\data_r1__full_cr$next[31:0]$3201 + assign { } { } + assign $0\data_r1__full_cr_ok$next[0:0]$3198 $3\data_r1__full_cr_ok$next[0:0]$3203 + attribute \src "libresoc.v:50051.5-50051.29" + switch \initial + attribute \src "libresoc.v:50051.9-50051.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__full_cr_ok$next[0:0]$3200 $1\data_r1__full_cr$next[31:0]$3199 } { \full_cr_ok \alu_cr0_full_cr } + case + assign $1\data_r1__full_cr$next[31:0]$3199 \data_r1__full_cr + assign $1\data_r1__full_cr_ok$next[0:0]$3200 \data_r1__full_cr_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__full_cr_ok$next[0:0]$3202 $2\data_r1__full_cr$next[31:0]$3201 } 33'000000000000000000000000000000000 + case + assign $2\data_r1__full_cr$next[31:0]$3201 $1\data_r1__full_cr$next[31:0]$3199 + assign $2\data_r1__full_cr_ok$next[0:0]$3202 $1\data_r1__full_cr_ok$next[0:0]$3200 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__full_cr_ok$next[0:0]$3203 1'0 + case + assign $3\data_r1__full_cr_ok$next[0:0]$3203 $2\data_r1__full_cr_ok$next[0:0]$3202 + end + sync always + update \data_r1__full_cr$next $0\data_r1__full_cr$next[31:0]$3197 + update \data_r1__full_cr_ok$next $0\data_r1__full_cr_ok$next[0:0]$3198 + end + attribute \src "libresoc.v:50072.3-50093.6" + process $proc$libresoc.v:50072$3204 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__cr_a$next[3:0]$3205 $2\data_r2__cr_a$next[3:0]$3209 + assign { } { } + assign $0\data_r2__cr_a_ok$next[0:0]$3206 $3\data_r2__cr_a_ok$next[0:0]$3211 + attribute \src "libresoc.v:50073.5-50073.29" + switch \initial + attribute \src "libresoc.v:50073.9-50073.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__cr_a_ok$next[0:0]$3208 $1\data_r2__cr_a$next[3:0]$3207 } { \cr_a_ok \alu_cr0_cr_a } + case + assign $1\data_r2__cr_a$next[3:0]$3207 \data_r2__cr_a + assign $1\data_r2__cr_a_ok$next[0:0]$3208 \data_r2__cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__cr_a_ok$next[0:0]$3210 $2\data_r2__cr_a$next[3:0]$3209 } 5'00000 + case + assign $2\data_r2__cr_a$next[3:0]$3209 $1\data_r2__cr_a$next[3:0]$3207 + assign $2\data_r2__cr_a_ok$next[0:0]$3210 $1\data_r2__cr_a_ok$next[0:0]$3208 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__cr_a_ok$next[0:0]$3211 1'0 + case + assign $3\data_r2__cr_a_ok$next[0:0]$3211 $2\data_r2__cr_a_ok$next[0:0]$3210 + end + sync always + update \data_r2__cr_a$next $0\data_r2__cr_a$next[3:0]$3205 + update \data_r2__cr_a_ok$next $0\data_r2__cr_a_ok$next[0:0]$3206 + end + attribute \src "libresoc.v:50094.3-50103.6" + process $proc$libresoc.v:50094$3212 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$3213 $1\src_r0$next[63:0]$3214 + attribute \src "libresoc.v:50095.5-50095.29" + switch \initial + attribute \src "libresoc.v:50095.9-50095.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$3214 \src1_i + case + assign $1\src_r0$next[63:0]$3214 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$3213 + end + attribute \src "libresoc.v:50104.3-50113.6" + process $proc$libresoc.v:50104$3215 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$3216 $1\src_r1$next[63:0]$3217 + attribute \src "libresoc.v:50105.5-50105.29" + switch \initial + attribute \src "libresoc.v:50105.9-50105.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$3217 \src2_i + case + assign $1\src_r1$next[63:0]$3217 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$3216 + end + attribute \src "libresoc.v:50114.3-50123.6" + process $proc$libresoc.v:50114$3218 + assign { } { } + assign { } { } + assign $0\src_r2$next[31:0]$3219 $1\src_r2$next[31:0]$3220 + attribute \src "libresoc.v:50115.5-50115.29" + switch \initial + attribute \src "libresoc.v:50115.9-50115.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[31:0]$3220 \src3_i + case + assign $1\src_r2$next[31:0]$3220 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[31:0]$3219 + end + attribute \src "libresoc.v:50124.3-50133.6" + process $proc$libresoc.v:50124$3221 + assign { } { } + assign { } { } + assign $0\src_r3$next[3:0]$3222 $1\src_r3$next[3:0]$3223 + attribute \src "libresoc.v:50125.5-50125.29" + switch \initial + attribute \src "libresoc.v:50125.9-50125.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r3$next[3:0]$3223 \src4_i + case + assign $1\src_r3$next[3:0]$3223 \src_r3 + end + sync always + update \src_r3$next $0\src_r3$next[3:0]$3222 + end + attribute \src "libresoc.v:50134.3-50143.6" + process $proc$libresoc.v:50134$3224 + assign { } { } + assign { } { } + assign $0\src_r4$next[3:0]$3225 $1\src_r4$next[3:0]$3226 + attribute \src "libresoc.v:50135.5-50135.29" + switch \initial + attribute \src "libresoc.v:50135.9-50135.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r4$next[3:0]$3226 \src5_i + case + assign $1\src_r4$next[3:0]$3226 \src_r4 + end + sync always + update \src_r4$next $0\src_r4$next[3:0]$3225 + end + attribute \src "libresoc.v:50144.3-50153.6" + process $proc$libresoc.v:50144$3227 + assign { } { } + assign { } { } + assign $0\src_r5$next[3:0]$3228 $1\src_r5$next[3:0]$3229 + attribute \src "libresoc.v:50145.5-50145.29" + switch \initial + attribute \src "libresoc.v:50145.9-50145.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r5$next[3:0]$3229 \src6_i + case + assign $1\src_r5$next[3:0]$3229 \src_r5 + end + sync always + update \src_r5$next $0\src_r5$next[3:0]$3228 + end + attribute \src "libresoc.v:50154.3-50162.6" + process $proc$libresoc.v:50154$3230 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$3231 $1\alui_l_r_alui$next[0:0]$3232 + attribute \src "libresoc.v:50155.5-50155.29" + switch \initial + attribute \src "libresoc.v:50155.9-50155.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$3232 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$3232 \$89 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$3231 + end + attribute \src "libresoc.v:50163.3-50171.6" + process $proc$libresoc.v:50163$3233 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$3234 $1\alu_l_r_alu$next[0:0]$3235 + attribute \src "libresoc.v:50164.5-50164.29" + switch \initial + attribute \src "libresoc.v:50164.9-50164.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$3235 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$3235 \$91 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$3234 + end + attribute \src "libresoc.v:50172.3-50181.6" + process $proc$libresoc.v:50172$3236 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:50173.5-50173.29" + switch \initial + attribute \src "libresoc.v:50173.9-50173.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$111 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__o + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "libresoc.v:50182.3-50191.6" + process $proc$libresoc.v:50182$3237 + assign { } { } + assign { } { } + assign $0\dest2_o[31:0] $1\dest2_o[31:0] + attribute \src "libresoc.v:50183.5-50183.29" + switch \initial + attribute \src "libresoc.v:50183.9-50183.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$113 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[31:0] \data_r1__full_cr + case + assign $1\dest2_o[31:0] 0 + end + sync always + update \dest2_o $0\dest2_o[31:0] + end + attribute \src "libresoc.v:50192.3-50201.6" + process $proc$libresoc.v:50192$3238 + assign { } { } + assign { } { } + assign $0\dest3_o[3:0] $1\dest3_o[3:0] + attribute \src "libresoc.v:50193.5-50193.29" + switch \initial + attribute \src "libresoc.v:50193.9-50193.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$115 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest3_o[3:0] \data_r2__cr_a + case + assign $1\dest3_o[3:0] 4'0000 + end + sync always + update \dest3_o $0\dest3_o[3:0] + end + attribute \src "libresoc.v:50202.3-50210.6" + process $proc$libresoc.v:50202$3239 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[2:0]$3240 $1\prev_wr_go$next[2:0]$3241 + attribute \src "libresoc.v:50203.5-50203.29" + switch \initial + attribute \src "libresoc.v:50203.9-50203.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[2:0]$3241 3'000 + case + assign $1\prev_wr_go$next[2:0]$3241 \$21 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[2:0]$3240 + end + connect \$5 $reduce_and$libresoc.v:49728$3063_Y + connect \$99 $and$libresoc.v:49729$3064_Y + connect \$101 $and$libresoc.v:49730$3065_Y + connect \$103 $and$libresoc.v:49731$3066_Y + connect \$105 $and$libresoc.v:49732$3067_Y + connect \$107 $and$libresoc.v:49733$3068_Y + connect \$109 $and$libresoc.v:49734$3069_Y + connect \$111 $and$libresoc.v:49735$3070_Y + connect \$113 $and$libresoc.v:49736$3071_Y + connect \$115 $and$libresoc.v:49737$3072_Y + connect \$11 $and$libresoc.v:49738$3073_Y + connect \$13 $not$libresoc.v:49739$3074_Y + connect \$15 $and$libresoc.v:49740$3075_Y + connect \$17 $not$libresoc.v:49741$3076_Y + connect \$19 $and$libresoc.v:49742$3077_Y + connect \$21 $and$libresoc.v:49743$3078_Y + connect \$25 $not$libresoc.v:49744$3079_Y + connect \$27 $and$libresoc.v:49745$3080_Y + connect \$24 $reduce_or$libresoc.v:49746$3081_Y + connect \$23 $not$libresoc.v:49747$3082_Y + connect \$31 $and$libresoc.v:49748$3083_Y + connect \$33 $reduce_or$libresoc.v:49749$3084_Y + connect \$35 $reduce_or$libresoc.v:49750$3085_Y + connect \$37 $or$libresoc.v:49751$3086_Y + connect \$3 $and$libresoc.v:49752$3087_Y + connect \$39 $not$libresoc.v:49753$3088_Y + connect \$41 $and$libresoc.v:49754$3089_Y + connect \$43 $and$libresoc.v:49755$3090_Y + connect \$45 $eq$libresoc.v:49756$3091_Y + connect \$47 $and$libresoc.v:49757$3092_Y + connect \$49 $eq$libresoc.v:49758$3093_Y + connect \$51 $and$libresoc.v:49759$3094_Y + connect \$53 $and$libresoc.v:49760$3095_Y + connect \$55 $and$libresoc.v:49761$3096_Y + connect \$57 $or$libresoc.v:49762$3097_Y + connect \$59 $or$libresoc.v:49763$3098_Y + connect \$61 $or$libresoc.v:49764$3099_Y + connect \$63 $or$libresoc.v:49765$3100_Y + connect \$65 $and$libresoc.v:49766$3101_Y + connect \$67 $and$libresoc.v:49767$3102_Y + connect \$6 $not$libresoc.v:49768$3103_Y + connect \$69 $or$libresoc.v:49769$3104_Y + connect \$71 $and$libresoc.v:49770$3105_Y + connect \$73 $and$libresoc.v:49771$3106_Y + connect \$75 $and$libresoc.v:49772$3107_Y + connect \$77 $ternary$libresoc.v:49773$3108_Y + connect \$79 $ternary$libresoc.v:49774$3109_Y + connect \$81 $ternary$libresoc.v:49775$3110_Y + connect \$83 $ternary$libresoc.v:49776$3111_Y + connect \$85 $ternary$libresoc.v:49777$3112_Y + connect \$87 $ternary$libresoc.v:49778$3113_Y + connect \$8 $or$libresoc.v:49779$3114_Y + connect \$89 $and$libresoc.v:49780$3115_Y + connect \$91 $and$libresoc.v:49781$3116_Y + connect \$93 $and$libresoc.v:49782$3117_Y + connect \$95 $and$libresoc.v:49783$3118_Y + connect \$97 $not$libresoc.v:49784$3119_Y + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \cu_wr__rel_o \$109 + connect \cu_rd__rel_o \$99 + connect \cu_busy_o \opc_l_q_opc + connect \alu_l_s_alu \all_rd_pulse + connect \alu_cr0_n_ready_i \alu_l_q_alu + connect \alui_l_s_alui \all_rd_pulse + connect \alu_cr0_p_valid_i \alui_l_q_alui + connect \alu_cr0_cr_c \$87 + connect \alu_cr0_cr_b \$85 + connect \alu_cr0_cr_a$2 \$83 + connect \alu_cr0_full_cr$1 \$81 + connect \alu_cr0_rb \$79 + connect \alu_cr0_ra \$77 + connect \cu_wrmask_o { \$75 \$73 \$71 } + connect \reset_r \$63 + connect \reset_w \$61 + connect \rst_r \$59 + connect \reset \$57 + connect \wr_any \$37 + connect \cu_done_o \$31 + connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } + connect \alu_pulse \alu_done_rise + connect \alu_done_rise \$19 + connect \alu_done_dly$next \alu_done + connect \alu_done \alu_cr0_n_valid_o + connect \all_rd_pulse \all_rd_rise + connect \all_rd_rise \$15 + connect \all_rd_dly$next \all_rd + connect \all_rd \$11 +end +attribute \src "libresoc.v:50246.1-50295.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.cyc_l" +attribute \generator "nMigen" +module \cyc_l + attribute \src "libresoc.v:50247.7-50247.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:50283.3-50291.6" + wire $0\q_int$next[0:0]$3280 + attribute \src "libresoc.v:50281.3-50282.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:50283.3-50291.6" + wire $1\q_int$next[0:0]$3281 + attribute \src "libresoc.v:50265.7-50265.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:50278.17-50278.96" + wire $and$libresoc.v:50278$3275_Y + attribute \src "libresoc.v:50277.17-50277.92" + wire $not$libresoc.v:50277$3274_Y + attribute \src "libresoc.v:50280.17-50280.92" + wire $not$libresoc.v:50280$3277_Y + attribute \src "libresoc.v:50276.17-50276.98" + wire $or$libresoc.v:50276$3273_Y + attribute \src "libresoc.v:50279.17-50279.97" + wire $or$libresoc.v:50279$3276_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:50247.7-50247.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:50278$3275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:50278$3275_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:50277$3274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_cyc + connect \Y $not$libresoc.v:50277$3274_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:50280$3277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_cyc + connect \Y $not$libresoc.v:50280$3277_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:50276$3273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_cyc + connect \B \q_int + connect \Y $or$libresoc.v:50276$3273_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:50279$3276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_cyc + connect \Y $or$libresoc.v:50279$3276_Y + end + attribute \src "libresoc.v:50247.7-50247.20" + process $proc$libresoc.v:50247$3282 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:50265.7-50265.19" + process $proc$libresoc.v:50265$3283 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:50281.3-50282.27" + process $proc$libresoc.v:50281$3278 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:50283.3-50291.6" + process $proc$libresoc.v:50283$3279 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$3280 $1\q_int$next[0:0]$3281 + attribute \src "libresoc.v:50284.5-50284.29" + switch \initial + attribute \src "libresoc.v:50284.9-50284.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$3281 1'0 + case + assign $1\q_int$next[0:0]$3281 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$3280 + end + connect \$9 $or$libresoc.v:50276$3273_Y + connect \$1 $not$libresoc.v:50277$3274_Y + connect \$3 $and$libresoc.v:50278$3275_Y + connect \$5 $or$libresoc.v:50279$3276_Y + connect \$7 $not$libresoc.v:50280$3277_Y + connect \qlq_cyc \$9 + connect \qn_cyc \$7 + connect \q_cyc \q_int +end +attribute \src "libresoc.v:50299.1-51013.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dbg" +attribute \generator "nMigen" +module \dbg + attribute \src "libresoc.v:50829.3-50838.6" + wire $0\d_cr_req[0:0] + attribute \src "libresoc.v:50636.3-50645.6" + wire $0\d_gpr_req[0:0] + attribute \src "libresoc.v:50839.3-50848.6" + wire $0\d_xer_req[0:0] + attribute \src "libresoc.v:50618.3-50635.6" + wire $0\dmi_ack_o[0:0] + attribute \src "libresoc.v:50849.3-50879.6" + wire width 64 $0\dmi_dout[63:0] + attribute \src "libresoc.v:50820.3-50828.6" + wire $0\dmi_read_log_data$next[0:0]$3397 + attribute \src "libresoc.v:50596.3-50597.51" + wire $0\dmi_read_log_data[0:0] + attribute \src "libresoc.v:50811.3-50819.6" + wire $0\dmi_read_log_data_1$next[0:0]$3394 + attribute \src "libresoc.v:50598.3-50599.55" + wire $0\dmi_read_log_data_1[0:0] + attribute \src "libresoc.v:50646.3-50654.6" + wire $0\dmi_req_i_1$next[0:0]$3360 + attribute \src "libresoc.v:50608.3-50609.39" + wire $0\dmi_req_i_1[0:0] + attribute \src "libresoc.v:50970.3-51003.6" + wire $0\do_dmi_log_rd$next[0:0]$3424 + attribute \src "libresoc.v:50610.3-50611.43" + wire $0\do_dmi_log_rd[0:0] + attribute \src "libresoc.v:50940.3-50969.6" + wire $0\do_icreset$next[0:0]$3417 + attribute \src "libresoc.v:50612.3-50613.37" + wire $0\do_icreset[0:0] + attribute \src "libresoc.v:50910.3-50939.6" + wire $0\do_reset$next[0:0]$3410 + attribute \src "libresoc.v:50614.3-50615.33" + wire $0\do_reset[0:0] + attribute \src "libresoc.v:50880.3-50909.6" + wire $0\do_step$next[0:0]$3403 + attribute \src "libresoc.v:50616.3-50617.31" + wire $0\do_step[0:0] + attribute \src "libresoc.v:50749.3-50776.6" + wire width 7 $0\gspr_index$next[6:0]$3382 + attribute \src "libresoc.v:50602.3-50603.37" + wire width 7 $0\gspr_index[6:0] + attribute \src "libresoc.v:50300.7-50300.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:50777.3-50810.6" + wire width 32 $0\log_dmi_addr$next[31:0]$3388 + attribute \src "libresoc.v:50600.3-50601.41" + wire width 32 $0\log_dmi_addr[31:0] + attribute \src "libresoc.v:50705.3-50748.6" + wire $0\stopping$next[0:0]$3373 + attribute \src "libresoc.v:50604.3-50605.33" + wire $0\stopping[0:0] + attribute \src "libresoc.v:50655.3-50704.6" + wire $0\terminated$next[0:0]$3363 + attribute \src "libresoc.v:50606.3-50607.37" + wire $0\terminated[0:0] + attribute \src "libresoc.v:50829.3-50838.6" + wire $1\d_cr_req[0:0] + attribute \src "libresoc.v:50636.3-50645.6" + wire $1\d_gpr_req[0:0] + attribute \src "libresoc.v:50839.3-50848.6" + wire $1\d_xer_req[0:0] + attribute \src "libresoc.v:50618.3-50635.6" + wire $1\dmi_ack_o[0:0] + attribute \src "libresoc.v:50849.3-50879.6" + wire width 64 $1\dmi_dout[63:0] + attribute \src "libresoc.v:50820.3-50828.6" + wire $1\dmi_read_log_data$next[0:0]$3398 + attribute \src "libresoc.v:50473.7-50473.31" + wire $1\dmi_read_log_data[0:0] + attribute \src "libresoc.v:50811.3-50819.6" + wire $1\dmi_read_log_data_1$next[0:0]$3395 + attribute \src "libresoc.v:50477.7-50477.33" + wire $1\dmi_read_log_data_1[0:0] + attribute \src "libresoc.v:50646.3-50654.6" + wire $1\dmi_req_i_1$next[0:0]$3361 + attribute \src "libresoc.v:50483.7-50483.25" + wire $1\dmi_req_i_1[0:0] + attribute \src "libresoc.v:50970.3-51003.6" + wire $1\do_dmi_log_rd$next[0:0]$3425 + attribute \src "libresoc.v:50489.7-50489.27" + wire $1\do_dmi_log_rd[0:0] + attribute \src "libresoc.v:50940.3-50969.6" + wire $1\do_icreset$next[0:0]$3418 + attribute \src "libresoc.v:50493.7-50493.24" + wire $1\do_icreset[0:0] + attribute \src "libresoc.v:50910.3-50939.6" + wire $1\do_reset$next[0:0]$3411 + attribute \src "libresoc.v:50497.7-50497.22" + wire $1\do_reset[0:0] + attribute \src "libresoc.v:50880.3-50909.6" + wire $1\do_step$next[0:0]$3404 + attribute \src "libresoc.v:50501.7-50501.21" + wire $1\do_step[0:0] + attribute \src "libresoc.v:50749.3-50776.6" + wire width 7 $1\gspr_index$next[6:0]$3383 + attribute \src "libresoc.v:50505.13-50505.31" + wire width 7 $1\gspr_index[6:0] + attribute \src "libresoc.v:50777.3-50810.6" + wire width 32 $1\log_dmi_addr$next[31:0]$3389 + attribute \src "libresoc.v:50511.14-50511.34" + wire width 32 $1\log_dmi_addr[31:0] + attribute \src "libresoc.v:50705.3-50748.6" + wire $1\stopping$next[0:0]$3374 + attribute \src "libresoc.v:50523.7-50523.22" + wire $1\stopping[0:0] + attribute \src "libresoc.v:50655.3-50704.6" + wire $1\terminated$next[0:0]$3364 + attribute \src "libresoc.v:50529.7-50529.24" + wire $1\terminated[0:0] + attribute \src "libresoc.v:50970.3-51003.6" + wire $2\do_dmi_log_rd$next[0:0]$3426 + attribute \src "libresoc.v:50940.3-50969.6" + wire $2\do_icreset$next[0:0]$3419 + attribute \src "libresoc.v:50910.3-50939.6" + wire $2\do_reset$next[0:0]$3412 + attribute \src "libresoc.v:50880.3-50909.6" + wire $2\do_step$next[0:0]$3405 + attribute \src "libresoc.v:50749.3-50776.6" + wire width 7 $2\gspr_index$next[6:0]$3384 + attribute \src "libresoc.v:50777.3-50810.6" + wire width 32 $2\log_dmi_addr$next[31:0]$3390 + attribute \src "libresoc.v:50705.3-50748.6" + wire $2\stopping$next[0:0]$3375 + attribute \src "libresoc.v:50655.3-50704.6" + wire $2\terminated$next[0:0]$3365 + attribute \src "libresoc.v:50970.3-51003.6" + wire $3\do_dmi_log_rd$next[0:0]$3427 + attribute \src "libresoc.v:50940.3-50969.6" + wire $3\do_icreset$next[0:0]$3420 + attribute \src "libresoc.v:50910.3-50939.6" + wire $3\do_reset$next[0:0]$3413 + attribute \src "libresoc.v:50880.3-50909.6" + wire $3\do_step$next[0:0]$3406 + attribute \src "libresoc.v:50749.3-50776.6" + wire width 7 $3\gspr_index$next[6:0]$3385 + attribute \src "libresoc.v:50777.3-50810.6" + wire width 32 $3\log_dmi_addr$next[31:0]$3391 + attribute \src "libresoc.v:50705.3-50748.6" + wire $3\stopping$next[0:0]$3376 + attribute \src "libresoc.v:50655.3-50704.6" + wire $3\terminated$next[0:0]$3366 + attribute \src "libresoc.v:50970.3-51003.6" + wire $4\do_dmi_log_rd$next[0:0]$3428 + attribute \src "libresoc.v:50940.3-50969.6" + wire $4\do_icreset$next[0:0]$3421 + attribute \src "libresoc.v:50910.3-50939.6" + wire $4\do_reset$next[0:0]$3414 + attribute \src "libresoc.v:50880.3-50909.6" + wire $4\do_step$next[0:0]$3407 + attribute \src "libresoc.v:50749.3-50776.6" + wire width 7 $4\gspr_index$next[6:0]$3386 + attribute \src "libresoc.v:50777.3-50810.6" + wire width 32 $4\log_dmi_addr$next[31:0]$3392 + attribute \src "libresoc.v:50705.3-50748.6" + wire $4\stopping$next[0:0]$3377 + attribute \src "libresoc.v:50655.3-50704.6" + wire $4\terminated$next[0:0]$3367 + attribute \src "libresoc.v:50940.3-50969.6" + wire $5\do_icreset$next[0:0]$3422 + attribute \src "libresoc.v:50910.3-50939.6" + wire $5\do_reset$next[0:0]$3415 + attribute \src "libresoc.v:50880.3-50909.6" + wire $5\do_step$next[0:0]$3408 + attribute \src "libresoc.v:50705.3-50748.6" + wire $5\stopping$next[0:0]$3378 + attribute \src "libresoc.v:50655.3-50704.6" + wire $5\terminated$next[0:0]$3368 + attribute \src "libresoc.v:50705.3-50748.6" + wire $6\stopping$next[0:0]$3379 + attribute \src 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$eq$libresoc.v:50535$3285_Y + attribute \src "libresoc.v:50540.19-50540.104" + wire $eq$libresoc.v:50540$3290_Y + attribute \src "libresoc.v:50541.19-50541.104" + wire $eq$libresoc.v:50541$3291_Y + attribute \src "libresoc.v:50542.19-50542.104" + wire $eq$libresoc.v:50542$3292_Y + attribute \src "libresoc.v:50544.19-50544.104" + wire $eq$libresoc.v:50544$3294_Y + attribute \src "libresoc.v:50545.18-50545.103" + wire $eq$libresoc.v:50545$3295_Y + attribute \src "libresoc.v:50549.18-50549.103" + wire $eq$libresoc.v:50549$3299_Y + attribute \src "libresoc.v:50550.18-50550.103" + wire $eq$libresoc.v:50550$3300_Y + attribute \src "libresoc.v:50556.18-50556.103" + wire $eq$libresoc.v:50556$3306_Y + attribute \src "libresoc.v:50557.18-50557.103" + wire $eq$libresoc.v:50557$3307_Y + attribute \src "libresoc.v:50558.18-50558.103" + wire $eq$libresoc.v:50558$3308_Y + attribute \src "libresoc.v:50564.18-50564.103" + wire $eq$libresoc.v:50564$3314_Y + attribute \src "libresoc.v:50565.18-50565.103" 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"/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + wire \$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + wire \$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + wire \$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" + wire width 3 \$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" + wire width 3 \$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242" + wire \$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242" + wire \$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254" + wire \$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254" + wire \$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + wire \$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" wire \$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" @@ -1590,2548 +89751,50956 @@ module \dbg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" wire \$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - wire \$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - wire \$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - wire \$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - wire \$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 24 \clk + wire \$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + wire \$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + wire \$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 24 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + wire width 64 input 11 \core_dbg_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + wire width 64 input 10 \core_dbg_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:98" + wire output 8 \core_rst_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:97" + wire output 12 \core_stop_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:103" + wire input 13 \core_stopped_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" + wire input 20 \d_cr_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" + wire width 64 input 19 \d_cr_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" + wire output 18 \d_cr_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" + wire input 17 \d_gpr_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" + wire width 7 output 15 \d_gpr_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" + wire width 64 input 16 \d_gpr_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" + wire output 14 \d_gpr_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" + wire input 23 \d_xer_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" + wire width 64 input 22 \d_xer_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" + wire output 21 \d_xer_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" + wire output 6 \dmi_ack_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" + wire width 4 input 2 \dmi_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" + wire width 64 input 5 \dmi_din + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" + wire width 64 output 7 \dmi_dout + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148" + wire \dmi_read_log_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148" + wire \dmi_read_log_data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149" + wire \dmi_read_log_data_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149" + wire \dmi_read_log_data_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" + wire input 3 \dmi_req_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131" + wire \dmi_req_i_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131" + wire \dmi_req_i_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" + wire input 4 \dmi_we_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147" + wire \do_dmi_log_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147" + wire \do_dmi_log_rd$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140" + wire \do_icreset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140" + wire \do_icreset$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139" + wire \do_reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139" + wire \do_reset$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138" + wire \do_step + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138" + wire \do_step$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:143" + wire width 7 \gspr_index + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:143" + wire width 7 \gspr_index$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:99" + wire \icache_rst_o + attribute \src "libresoc.v:50300.7-50300.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:145" + wire width 32 \log_dmi_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:145" + wire width 32 \log_dmi_addr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" + wire width 64 \log_dmi_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:119" + wire width 32 \log_write_addr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:134" + wire width 64 \stat_reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137" + wire \stopping + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137" + wire \stopping$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:102" + wire input 9 \terminate_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141" + wire \terminated + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141" + wire \terminated$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:122" + wire \terminated_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" + cell $add $add$libresoc.v:50543$3293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \log_dmi_addr [1:0] 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\A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:50575$3325_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:50577$3327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:50577$3327_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:50582$3332 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:50582$3332_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:50584$3334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:50584$3334_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:50585$3335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:50585$3335_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:50590$3340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:50590$3340_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:50592$3342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:50592$3342_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:170" + cell $pos $pos$libresoc.v:50552$3302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 61'0000000000000000000000000000000000000000000000000000000000000 \terminated \core_stopped_i \stopping } + connect \Y $pos$libresoc.v:50552$3302_Y + end + attribute \src "libresoc.v:50300.7-50300.20" + process $proc$libresoc.v:50300$3429 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:50473.7-50473.31" + process $proc$libresoc.v:50473$3430 + assign { } { } + assign $1\dmi_read_log_data[0:0] 1'0 + sync always + sync init + update \dmi_read_log_data $1\dmi_read_log_data[0:0] + end + attribute \src "libresoc.v:50477.7-50477.33" + process $proc$libresoc.v:50477$3431 + assign { } { } + assign $1\dmi_read_log_data_1[0:0] 1'0 + sync always + sync init + update \dmi_read_log_data_1 $1\dmi_read_log_data_1[0:0] + end + attribute \src "libresoc.v:50483.7-50483.25" + process $proc$libresoc.v:50483$3432 + assign { } { } + assign $1\dmi_req_i_1[0:0] 1'0 + sync always + sync init + update \dmi_req_i_1 $1\dmi_req_i_1[0:0] + end + attribute \src "libresoc.v:50489.7-50489.27" + process $proc$libresoc.v:50489$3433 + assign { } { } + assign $1\do_dmi_log_rd[0:0] 1'0 + sync always + sync init + update \do_dmi_log_rd $1\do_dmi_log_rd[0:0] + end + attribute \src "libresoc.v:50493.7-50493.24" + process $proc$libresoc.v:50493$3434 + assign { } { } + assign $1\do_icreset[0:0] 1'0 + sync always + sync init + update \do_icreset $1\do_icreset[0:0] + end + attribute \src "libresoc.v:50497.7-50497.22" + process $proc$libresoc.v:50497$3435 + assign { } { } + assign $1\do_reset[0:0] 1'0 + sync always + sync init + update \do_reset $1\do_reset[0:0] + end + attribute \src "libresoc.v:50501.7-50501.21" + process $proc$libresoc.v:50501$3436 + assign { } { } + assign $1\do_step[0:0] 1'0 + sync always + sync init + update \do_step $1\do_step[0:0] + end + attribute \src "libresoc.v:50505.13-50505.31" + process $proc$libresoc.v:50505$3437 + assign { } { } + assign $1\gspr_index[6:0] 7'0000000 + sync always + sync init + update \gspr_index $1\gspr_index[6:0] + end + attribute \src "libresoc.v:50511.14-50511.34" + process $proc$libresoc.v:50511$3438 + assign { } { } + assign $1\log_dmi_addr[31:0] 0 + sync always + sync init + update \log_dmi_addr $1\log_dmi_addr[31:0] + end + attribute \src "libresoc.v:50523.7-50523.22" + process $proc$libresoc.v:50523$3439 + assign { } { } + assign $1\stopping[0:0] 1'0 + sync always + sync init + update \stopping $1\stopping[0:0] + end + attribute \src "libresoc.v:50529.7-50529.24" + process $proc$libresoc.v:50529$3440 + assign { } { } + assign $1\terminated[0:0] 1'0 + sync always + sync init + update \terminated $1\terminated[0:0] + end + attribute \src "libresoc.v:50596.3-50597.51" + process $proc$libresoc.v:50596$3346 + assign { } { } + assign $0\dmi_read_log_data[0:0] \dmi_read_log_data$next + sync posedge \clk + update \dmi_read_log_data $0\dmi_read_log_data[0:0] + end + attribute \src "libresoc.v:50598.3-50599.55" + process $proc$libresoc.v:50598$3347 + assign { } { } + assign $0\dmi_read_log_data_1[0:0] \dmi_read_log_data_1$next + sync posedge \clk + update \dmi_read_log_data_1 $0\dmi_read_log_data_1[0:0] + end + attribute \src "libresoc.v:50600.3-50601.41" + process $proc$libresoc.v:50600$3348 + assign { } { } + assign $0\log_dmi_addr[31:0] \log_dmi_addr$next + sync posedge \clk + update \log_dmi_addr $0\log_dmi_addr[31:0] + end + attribute \src "libresoc.v:50602.3-50603.37" + process $proc$libresoc.v:50602$3349 + assign { } { } + assign $0\gspr_index[6:0] \gspr_index$next + sync posedge \clk + update \gspr_index $0\gspr_index[6:0] + end + attribute \src "libresoc.v:50604.3-50605.33" + process $proc$libresoc.v:50604$3350 + assign { } { } + assign $0\stopping[0:0] \stopping$next + sync posedge \clk + update \stopping $0\stopping[0:0] + end + attribute \src "libresoc.v:50606.3-50607.37" + process $proc$libresoc.v:50606$3351 + assign { } { } + assign $0\terminated[0:0] \terminated$next + sync posedge \clk + update \terminated $0\terminated[0:0] + end + attribute \src "libresoc.v:50608.3-50609.39" + process $proc$libresoc.v:50608$3352 + assign { } { } + assign $0\dmi_req_i_1[0:0] \dmi_req_i_1$next + sync posedge \clk + update \dmi_req_i_1 $0\dmi_req_i_1[0:0] + end + attribute \src "libresoc.v:50610.3-50611.43" + process $proc$libresoc.v:50610$3353 + assign { } { } + assign $0\do_dmi_log_rd[0:0] \do_dmi_log_rd$next + sync posedge \clk + update \do_dmi_log_rd $0\do_dmi_log_rd[0:0] + end + attribute \src "libresoc.v:50612.3-50613.37" + process $proc$libresoc.v:50612$3354 + assign { } { } + assign $0\do_icreset[0:0] \do_icreset$next + sync posedge \clk + update \do_icreset $0\do_icreset[0:0] + end + attribute \src "libresoc.v:50614.3-50615.33" + process $proc$libresoc.v:50614$3355 + assign { } { } + assign $0\do_reset[0:0] \do_reset$next + sync posedge \clk + update \do_reset $0\do_reset[0:0] + end + attribute \src "libresoc.v:50616.3-50617.31" + process $proc$libresoc.v:50616$3356 + assign { } { } + assign $0\do_step[0:0] \do_step$next + sync posedge \clk + update \do_step $0\do_step[0:0] + end + attribute \src "libresoc.v:50618.3-50635.6" + process $proc$libresoc.v:50618$3357 + assign { } { } + assign $0\dmi_ack_o[0:0] $1\dmi_ack_o[0:0] + attribute \src "libresoc.v:50619.5-50619.29" + switch \initial + attribute \src "libresoc.v:50619.9-50619.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" + switch \dmi_addr_i + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dmi_ack_o[0:0] \d_gpr_ack + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dmi_ack_o[0:0] \d_cr_ack + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dmi_ack_o[0:0] \d_xer_ack + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\dmi_ack_o[0:0] \dmi_req_i + end + sync always + update \dmi_ack_o $0\dmi_ack_o[0:0] + end + attribute \src "libresoc.v:50636.3-50645.6" + process $proc$libresoc.v:50636$3358 + assign { } { } + assign { } { } + assign $0\d_gpr_req[0:0] $1\d_gpr_req[0:0] + attribute \src "libresoc.v:50637.5-50637.29" + switch \initial + attribute \src "libresoc.v:50637.9-50637.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" + switch \dmi_addr_i + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\d_gpr_req[0:0] \dmi_req_i + case + assign $1\d_gpr_req[0:0] 1'0 + end + sync always + update \d_gpr_req $0\d_gpr_req[0:0] + end + attribute \src "libresoc.v:50646.3-50654.6" + process $proc$libresoc.v:50646$3359 + assign { } { } + assign { } { } + assign $0\dmi_req_i_1$next[0:0]$3360 $1\dmi_req_i_1$next[0:0]$3361 + attribute \src "libresoc.v:50647.5-50647.29" + switch \initial + attribute \src "libresoc.v:50647.9-50647.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi_req_i_1$next[0:0]$3361 1'0 + case + assign $1\dmi_req_i_1$next[0:0]$3361 \dmi_req_i + end + sync always + update \dmi_req_i_1$next $0\dmi_req_i_1$next[0:0]$3360 + end + attribute \src "libresoc.v:50655.3-50704.6" + process $proc$libresoc.v:50655$3362 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\terminated$next[0:0]$3363 $8\terminated$next[0:0]$3371 + attribute \src "libresoc.v:50656.5-50656.29" + switch \initial + attribute \src "libresoc.v:50656.9-50656.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$65 \$61 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\terminated$next[0:0]$3364 $2\terminated$next[0:0]$3365 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\terminated$next[0:0]$3365 $3\terminated$next[0:0]$3366 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$71 \$69 \$67 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign { } { } + assign { } { } + assign $3\terminated$next[0:0]$3366 $6\terminated$next[0:0]$3369 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208" + switch \dmi_din [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\terminated$next[0:0]$3367 1'0 + case + assign $4\terminated$next[0:0]$3367 \terminated + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:213" + switch \dmi_din [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\terminated$next[0:0]$3368 1'0 + case + assign $5\terminated$next[0:0]$3368 $4\terminated$next[0:0]$3367 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" + switch \dmi_din [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\terminated$next[0:0]$3369 1'0 + case + assign $6\terminated$next[0:0]$3369 $5\terminated$next[0:0]$3368 + end + case + assign $3\terminated$next[0:0]$3366 \terminated + end + case + assign $2\terminated$next[0:0]$3365 \terminated + end + case + assign $1\terminated$next[0:0]$3364 \terminated + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:247" + switch \terminate_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\terminated$next[0:0]$3370 1'1 + case + assign $7\terminated$next[0:0]$3370 $1\terminated$next[0:0]$3364 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\terminated$next[0:0]$3371 1'0 + case + assign $8\terminated$next[0:0]$3371 $7\terminated$next[0:0]$3370 + end + sync always + update \terminated$next $0\terminated$next[0:0]$3363 + end + attribute \src "libresoc.v:50705.3-50748.6" + process $proc$libresoc.v:50705$3372 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\stopping$next[0:0]$3373 $7\stopping$next[0:0]$3380 + attribute \src "libresoc.v:50706.5-50706.29" + switch \initial + attribute \src "libresoc.v:50706.9-50706.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$79 \$75 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\stopping$next[0:0]$3374 $2\stopping$next[0:0]$3375 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\stopping$next[0:0]$3375 $3\stopping$next[0:0]$3376 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$85 \$83 \$81 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign { } { } + assign $3\stopping$next[0:0]$3376 $5\stopping$next[0:0]$3378 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" + switch \dmi_din [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\stopping$next[0:0]$3377 1'1 + case + assign $4\stopping$next[0:0]$3377 \stopping + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" + switch \dmi_din [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\stopping$next[0:0]$3378 1'0 + case + assign $5\stopping$next[0:0]$3378 $4\stopping$next[0:0]$3377 + end + case + assign $3\stopping$next[0:0]$3376 \stopping + end + case + assign $2\stopping$next[0:0]$3375 \stopping + end + case + assign $1\stopping$next[0:0]$3374 \stopping + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:247" + switch \terminate_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\stopping$next[0:0]$3379 1'1 + case + assign $6\stopping$next[0:0]$3379 $1\stopping$next[0:0]$3374 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\stopping$next[0:0]$3380 1'0 + case + assign $7\stopping$next[0:0]$3380 $6\stopping$next[0:0]$3379 + end + sync always + update \stopping$next $0\stopping$next[0:0]$3373 + end + attribute \src "libresoc.v:50749.3-50776.6" + process $proc$libresoc.v:50749$3381 + assign { } { } + assign { } { } + assign { } { } + assign $0\gspr_index$next[6:0]$3382 $4\gspr_index$next[6:0]$3386 + attribute \src "libresoc.v:50750.5-50750.29" + switch \initial + attribute \src "libresoc.v:50750.9-50750.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$93 \$89 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\gspr_index$next[6:0]$3383 $2\gspr_index$next[6:0]$3384 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\gspr_index$next[6:0]$3384 $3\gspr_index$next[6:0]$3385 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$99 \$97 \$95 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $3\gspr_index$next[6:0]$3385 \gspr_index + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $3\gspr_index$next[6:0]$3385 \dmi_din [6:0] + case + assign $3\gspr_index$next[6:0]$3385 \gspr_index + end + case + assign $2\gspr_index$next[6:0]$3384 \gspr_index + end + case + assign $1\gspr_index$next[6:0]$3383 \gspr_index + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\gspr_index$next[6:0]$3386 7'0000000 + case + assign $4\gspr_index$next[6:0]$3386 $1\gspr_index$next[6:0]$3383 + end + sync always + update \gspr_index$next $0\gspr_index$next[6:0]$3382 + end + attribute \src "libresoc.v:50777.3-50810.6" + process $proc$libresoc.v:50777$3387 + assign { } { } + assign { } { } + assign { } { } + assign $0\log_dmi_addr$next[31:0]$3388 $4\log_dmi_addr$next[31:0]$3392 + attribute \src "libresoc.v:50778.5-50778.29" + switch \initial + attribute \src "libresoc.v:50778.9-50778.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$107 \$103 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\log_dmi_addr$next[31:0]$3389 $2\log_dmi_addr$next[31:0]$3390 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\log_dmi_addr$next[31:0]$3390 $3\log_dmi_addr$next[31:0]$3391 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$113 \$111 \$109 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $3\log_dmi_addr$next[31:0]$3391 \log_dmi_addr + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $3\log_dmi_addr$next[31:0]$3391 \log_dmi_addr + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $3\log_dmi_addr$next[31:0]$3391 \dmi_din [31:0] + case + assign $3\log_dmi_addr$next[31:0]$3391 \log_dmi_addr + end + case + assign $2\log_dmi_addr$next[31:0]$3390 \log_dmi_addr + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign $1\log_dmi_addr$next[31:0]$3389 [31:2] \log_dmi_addr [31:2] + assign $1\log_dmi_addr$next[31:0]$3389 [1:0] \$115 [1:0] + case + assign $1\log_dmi_addr$next[31:0]$3389 \log_dmi_addr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\log_dmi_addr$next[31:0]$3392 0 + case + assign $4\log_dmi_addr$next[31:0]$3392 $1\log_dmi_addr$next[31:0]$3389 + end + sync always + update \log_dmi_addr$next $0\log_dmi_addr$next[31:0]$3388 + end + attribute \src "libresoc.v:50811.3-50819.6" + process $proc$libresoc.v:50811$3393 + assign { } { } + assign { } { } + assign $0\dmi_read_log_data_1$next[0:0]$3394 $1\dmi_read_log_data_1$next[0:0]$3395 + attribute \src "libresoc.v:50812.5-50812.29" + switch \initial + attribute \src "libresoc.v:50812.9-50812.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi_read_log_data_1$next[0:0]$3395 1'0 + case + assign $1\dmi_read_log_data_1$next[0:0]$3395 \dmi_read_log_data + end + sync always + update \dmi_read_log_data_1$next $0\dmi_read_log_data_1$next[0:0]$3394 + end + attribute \src "libresoc.v:50820.3-50828.6" + process $proc$libresoc.v:50820$3396 + assign { } { } + assign { } { } + assign $0\dmi_read_log_data$next[0:0]$3397 $1\dmi_read_log_data$next[0:0]$3398 + attribute \src "libresoc.v:50821.5-50821.29" + switch \initial + attribute \src "libresoc.v:50821.9-50821.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi_read_log_data$next[0:0]$3398 1'0 + case + assign $1\dmi_read_log_data$next[0:0]$3398 \$120 + end + sync always + update \dmi_read_log_data$next $0\dmi_read_log_data$next[0:0]$3397 + end + attribute \src "libresoc.v:50829.3-50838.6" + process $proc$libresoc.v:50829$3399 + assign { } { } + assign { } { } + assign $0\d_cr_req[0:0] $1\d_cr_req[0:0] + attribute \src "libresoc.v:50830.5-50830.29" + switch \initial + attribute \src "libresoc.v:50830.9-50830.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" + switch \dmi_addr_i + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\d_cr_req[0:0] \dmi_req_i + case + assign $1\d_cr_req[0:0] 1'0 + end + sync always + update \d_cr_req $0\d_cr_req[0:0] + end + attribute \src "libresoc.v:50839.3-50848.6" + process $proc$libresoc.v:50839$3400 + assign { } { } + assign { } { } + assign $0\d_xer_req[0:0] $1\d_xer_req[0:0] + attribute \src "libresoc.v:50840.5-50840.29" + switch \initial + attribute \src "libresoc.v:50840.9-50840.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" + switch \dmi_addr_i + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\d_xer_req[0:0] \dmi_req_i + case + assign $1\d_xer_req[0:0] 1'0 + end + sync always + update \d_xer_req $0\d_xer_req[0:0] + end + attribute \src "libresoc.v:50849.3-50879.6" + process $proc$libresoc.v:50849$3401 + assign { } { } + assign { } { } + assign $0\dmi_dout[63:0] $1\dmi_dout[63:0] + attribute \src "libresoc.v:50850.5-50850.29" + switch \initial + attribute \src "libresoc.v:50850.9-50850.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:173" + switch \dmi_addr_i + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dmi_dout[63:0] \stat_reg + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dmi_dout[63:0] \core_dbg_pc + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dmi_dout[63:0] \core_dbg_msr + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dmi_dout[63:0] \d_gpr_data + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dmi_dout[63:0] { \log_write_addr_o \log_dmi_addr } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dmi_dout[63:0] \log_dmi_data + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dmi_dout[63:0] \d_cr_data + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dmi_dout[63:0] \d_xer_data + case + assign $1\dmi_dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dmi_dout $0\dmi_dout[63:0] + end + attribute \src "libresoc.v:50880.3-50909.6" + process $proc$libresoc.v:50880$3402 + assign { } { } + assign { } { } + assign { } { } + assign $0\do_step$next[0:0]$3403 $5\do_step$next[0:0]$3408 + attribute \src "libresoc.v:50881.5-50881.29" + switch \initial + attribute \src "libresoc.v:50881.9-50881.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$9 \$5 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\do_step$next[0:0]$3404 $2\do_step$next[0:0]$3405 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\do_step$next[0:0]$3405 $3\do_step$next[0:0]$3406 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$15 \$13 \$11 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $3\do_step$next[0:0]$3406 $4\do_step$next[0:0]$3407 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:213" + switch \dmi_din [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\do_step$next[0:0]$3407 1'1 + case + assign $4\do_step$next[0:0]$3407 1'0 + end + case + assign $3\do_step$next[0:0]$3406 1'0 + end + case + assign $2\do_step$next[0:0]$3405 1'0 + end + case + assign $1\do_step$next[0:0]$3404 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\do_step$next[0:0]$3408 1'0 + case + assign $5\do_step$next[0:0]$3408 $1\do_step$next[0:0]$3404 + end + sync always + update \do_step$next $0\do_step$next[0:0]$3403 + end + attribute \src "libresoc.v:50910.3-50939.6" + process $proc$libresoc.v:50910$3409 + assign { } { } + assign { } { } + assign { } { } + assign $0\do_reset$next[0:0]$3410 $5\do_reset$next[0:0]$3415 + attribute \src "libresoc.v:50911.5-50911.29" + switch \initial + attribute \src "libresoc.v:50911.9-50911.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$23 \$19 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\do_reset$next[0:0]$3411 $2\do_reset$next[0:0]$3412 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\do_reset$next[0:0]$3412 $3\do_reset$next[0:0]$3413 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$29 \$27 \$25 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $3\do_reset$next[0:0]$3413 $4\do_reset$next[0:0]$3414 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208" + switch \dmi_din [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\do_reset$next[0:0]$3414 1'1 + case + assign $4\do_reset$next[0:0]$3414 1'0 + end + case + assign $3\do_reset$next[0:0]$3413 1'0 + end + case + assign $2\do_reset$next[0:0]$3412 1'0 + end + case + assign $1\do_reset$next[0:0]$3411 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\do_reset$next[0:0]$3415 1'0 + case + assign $5\do_reset$next[0:0]$3415 $1\do_reset$next[0:0]$3411 + end + sync always + update \do_reset$next $0\do_reset$next[0:0]$3410 + end + attribute \src "libresoc.v:50940.3-50969.6" + process $proc$libresoc.v:50940$3416 + assign { } { } + assign { } { } + assign { } { } + assign $0\do_icreset$next[0:0]$3417 $5\do_icreset$next[0:0]$3422 + attribute \src "libresoc.v:50941.5-50941.29" + switch \initial + attribute \src "libresoc.v:50941.9-50941.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$37 \$33 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\do_icreset$next[0:0]$3418 $2\do_icreset$next[0:0]$3419 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\do_icreset$next[0:0]$3419 $3\do_icreset$next[0:0]$3420 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$43 \$41 \$39 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $3\do_icreset$next[0:0]$3420 $4\do_icreset$next[0:0]$3421 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216" + switch \dmi_din [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\do_icreset$next[0:0]$3421 1'1 + case + assign $4\do_icreset$next[0:0]$3421 1'0 + end + case + assign $3\do_icreset$next[0:0]$3420 1'0 + end + case + assign $2\do_icreset$next[0:0]$3419 1'0 + end + case + assign $1\do_icreset$next[0:0]$3418 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\do_icreset$next[0:0]$3422 1'0 + case + assign $5\do_icreset$next[0:0]$3422 $1\do_icreset$next[0:0]$3418 + end + sync always + update \do_icreset$next $0\do_icreset$next[0:0]$3417 + end + attribute \src "libresoc.v:50970.3-51003.6" + process $proc$libresoc.v:50970$3423 + assign { } { } + assign { } { } + assign { } { } + assign $0\do_dmi_log_rd$next[0:0]$3424 $4\do_dmi_log_rd$next[0:0]$3428 + attribute \src "libresoc.v:50971.5-50971.29" + switch \initial + attribute \src "libresoc.v:50971.9-50971.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$51 \$47 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\do_dmi_log_rd$next[0:0]$3425 $2\do_dmi_log_rd$next[0:0]$3426 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\do_dmi_log_rd$next[0:0]$3426 $3\do_dmi_log_rd$next[0:0]$3427 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$57 \$55 \$53 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $3\do_dmi_log_rd$next[0:0]$3427 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $3\do_dmi_log_rd$next[0:0]$3427 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $3\do_dmi_log_rd$next[0:0]$3427 1'1 + case + assign $3\do_dmi_log_rd$next[0:0]$3427 1'0 + end + case + assign $2\do_dmi_log_rd$next[0:0]$3426 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\do_dmi_log_rd$next[0:0]$3425 1'1 + case + assign $1\do_dmi_log_rd$next[0:0]$3425 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\do_dmi_log_rd$next[0:0]$3428 1'0 + case + assign $4\do_dmi_log_rd$next[0:0]$3428 $1\do_dmi_log_rd$next[0:0]$3425 + end + sync always + update \do_dmi_log_rd$next $0\do_dmi_log_rd$next[0:0]$3424 + end + connect \$9 $and$libresoc.v:50534$3284_Y + connect \$99 $eq$libresoc.v:50535$3285_Y + connect \$101 $not$libresoc.v:50536$3286_Y + connect \$103 $and$libresoc.v:50537$3287_Y + connect \$105 $not$libresoc.v:50538$3288_Y + connect \$107 $and$libresoc.v:50539$3289_Y + connect \$109 $eq$libresoc.v:50540$3290_Y + connect \$111 $eq$libresoc.v:50541$3291_Y + connect \$113 $eq$libresoc.v:50542$3292_Y + connect \$116 $add$libresoc.v:50543$3293_Y + connect \$118 $eq$libresoc.v:50544$3294_Y + connect \$11 $eq$libresoc.v:50545$3295_Y + connect \$120 $and$libresoc.v:50546$3296_Y + connect \$122 $not$libresoc.v:50547$3297_Y + connect \$124 $and$libresoc.v:50548$3298_Y + connect \$13 $eq$libresoc.v:50549$3299_Y + connect \$15 $eq$libresoc.v:50550$3300_Y + connect \$17 $not$libresoc.v:50551$3301_Y + connect \$1 $pos$libresoc.v:50552$3302_Y + connect \$19 $and$libresoc.v:50553$3303_Y + connect \$21 $not$libresoc.v:50554$3304_Y + connect \$23 $and$libresoc.v:50555$3305_Y + connect \$25 $eq$libresoc.v:50556$3306_Y + connect \$27 $eq$libresoc.v:50557$3307_Y + connect \$29 $eq$libresoc.v:50558$3308_Y + connect \$31 $not$libresoc.v:50559$3309_Y + connect \$33 $and$libresoc.v:50560$3310_Y + connect \$35 $not$libresoc.v:50561$3311_Y + connect \$37 $and$libresoc.v:50562$3312_Y + connect \$3 $not$libresoc.v:50563$3313_Y + connect \$39 $eq$libresoc.v:50564$3314_Y + connect \$41 $eq$libresoc.v:50565$3315_Y + connect \$43 $eq$libresoc.v:50566$3316_Y + connect \$45 $not$libresoc.v:50567$3317_Y + connect \$47 $and$libresoc.v:50568$3318_Y + connect \$49 $not$libresoc.v:50569$3319_Y + connect \$51 $and$libresoc.v:50570$3320_Y + connect \$53 $eq$libresoc.v:50571$3321_Y + connect \$55 $eq$libresoc.v:50572$3322_Y + connect \$57 $eq$libresoc.v:50573$3323_Y + connect \$5 $and$libresoc.v:50574$3324_Y + connect \$59 $not$libresoc.v:50575$3325_Y + connect \$61 $and$libresoc.v:50576$3326_Y + connect \$63 $not$libresoc.v:50577$3327_Y + connect \$65 $and$libresoc.v:50578$3328_Y + connect \$67 $eq$libresoc.v:50579$3329_Y + connect \$69 $eq$libresoc.v:50580$3330_Y + connect \$71 $eq$libresoc.v:50581$3331_Y + connect \$73 $not$libresoc.v:50582$3332_Y + connect \$75 $and$libresoc.v:50583$3333_Y + connect \$77 $not$libresoc.v:50584$3334_Y + connect \$7 $not$libresoc.v:50585$3335_Y + connect \$79 $and$libresoc.v:50586$3336_Y + connect \$81 $eq$libresoc.v:50587$3337_Y + connect \$83 $eq$libresoc.v:50588$3338_Y + connect \$85 $eq$libresoc.v:50589$3339_Y + connect \$87 $not$libresoc.v:50590$3340_Y + connect \$89 $and$libresoc.v:50591$3341_Y + connect \$91 $not$libresoc.v:50592$3342_Y + connect \$93 $and$libresoc.v:50593$3343_Y + connect \$95 $eq$libresoc.v:50594$3344_Y + connect \$97 $eq$libresoc.v:50595$3345_Y + connect \$115 \$116 + connect \log_write_addr_o 0 + connect \log_dmi_data 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \terminated_o \terminated + connect \icache_rst_o \do_icreset + connect \core_rst_o \do_reset + connect \core_stop_o \$124 + connect \d_gpr_addr \gspr_index + connect \stat_reg \$1 +end +attribute \src "libresoc.v:51017.1-53032.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec" +attribute \generator "nMigen" +module \dec + attribute \src "libresoc.v:52600.3-52633.6" + wire width 3 $0\ALU_cr_in[2:0] + attribute \src "libresoc.v:52634.3-52667.6" + wire width 3 $0\ALU_cr_out[2:0] + attribute \src "libresoc.v:52260.3-52293.6" + wire width 2 $0\ALU_cry_in[1:0] + attribute \src "libresoc.v:52362.3-52395.6" + wire $0\ALU_cry_out[0:0] + attribute \src "libresoc.v:52464.3-52497.6" + wire width 12 $0\ALU_function_unit[11:0] + attribute \src "libresoc.v:52532.3-52565.6" + wire width 3 $0\ALU_in1_sel[2:0] + attribute \src "libresoc.v:52566.3-52599.6" + wire width 4 $0\ALU_in2_sel[3:0] + attribute \src "libresoc.v:52498.3-52531.6" + wire width 7 $0\ALU_internal_op[6:0] + attribute \src "libresoc.v:52294.3-52327.6" + wire $0\ALU_inv_a[0:0] + attribute \src "libresoc.v:52328.3-52361.6" + wire $0\ALU_inv_out[0:0] + attribute \src "libresoc.v:52396.3-52429.6" + wire $0\ALU_is_32b[0:0] + attribute \src "libresoc.v:52668.3-52701.6" + wire width 4 $0\ALU_ldst_len[3:0] + attribute \src "libresoc.v:52226.3-52259.6" + wire width 2 $0\ALU_rc_sel[1:0] + attribute \src "libresoc.v:52430.3-52463.6" + wire $0\ALU_sgn[0:0] + attribute \src "libresoc.v:51018.7-51018.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:52600.3-52633.6" + wire width 3 $1\ALU_cr_in[2:0] + attribute \src "libresoc.v:52634.3-52667.6" + wire width 3 $1\ALU_cr_out[2:0] + attribute \src "libresoc.v:52260.3-52293.6" + wire width 2 $1\ALU_cry_in[1:0] + attribute \src "libresoc.v:52362.3-52395.6" + wire $1\ALU_cry_out[0:0] + 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \ALU_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 27 \ALU_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 26 \ALU_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 32 \ALU_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 output 25 \ALU_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 3 \ALU_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 2 \ALU_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 30 \ALU_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \ALU_BO + attribute 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \ALU_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \ALU_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \ALU_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire output 24 \ALU_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 17 \ALU_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \ALU_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \ALU_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \ALU_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire output 23 \ALU_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \ALU_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 20 \ALU_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 output 18 \ALU_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 10 \ALU_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \ALU_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 output 19 \ALU_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 4 \ALU_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \ALU_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \ALU_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 14 \ALU_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute 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\enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 \ALU_dec19_ALU_dec19_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \ALU_dec19_ALU_dec19_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \ALU_dec19_ALU_dec19_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \ALU_dec19_ALU_dec19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \ALU_dec19_ALU_dec19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \ALU_dec19_ALU_dec19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \ALU_dec19_ALU_dec19_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \ALU_dec19_ALU_dec19_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \ALU_dec19_ALU_dec19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \ALU_dec19_ALU_dec19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \ALU_dec19_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \ALU_dec31_ALU_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \ALU_dec31_ALU_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \ALU_dec31_ALU_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \ALU_dec31_ALU_dec31_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 \ALU_dec31_ALU_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \ALU_dec31_ALU_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \ALU_dec31_ALU_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \ALU_dec31_ALU_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \ALU_dec31_ALU_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \ALU_dec31_ALU_dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \ALU_dec31_ALU_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \ALU_dec31_ALU_dec31_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \ALU_dec31_ALU_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \ALU_dec31_ALU_dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \ALU_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 7 \ALU_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 8 \ALU_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 9 \ALU_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 6 \ALU_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 11 \ALU_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 12 \ALU_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \ALU_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 10 \ALU_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 3 \ALU_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \ALU_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 6 output 21 \ALU_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XL_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 output 35 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 15 \XL_OC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XO_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XO_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX2_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \XX2_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XX2_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \XX2_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XX2_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_dm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX3_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX3_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX3_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XX3_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX3_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XX3_DM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XX3_SHW + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX3_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX3_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \XX3_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \XX3_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XX3_XO_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX4_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX4_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX4_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX4_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX4_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX4_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX4_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX4_CX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX4_CX_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX4_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX4_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX4_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XX4_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 output 33 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 output 34 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \X_CT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \X_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \X_DRM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_E + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_EO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_EX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \X_E_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \X_IH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \X_IMM8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_L1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_L2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_L3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_MO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_NB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_PRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_RIC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_RM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_RO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_R_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_SP + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + wire input 1 \bigendian + attribute \src "libresoc.v:51018.7-51018.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + wire width 32 input 36 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + cell $mux $ternary$libresoc.v:52191$3441 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:52191$3441_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:52192.13-52208.4" + cell \ALU_dec19 \ALU_dec19 + connect \ALU_dec19_cr_in \ALU_dec19_ALU_dec19_cr_in + connect \ALU_dec19_cr_out \ALU_dec19_ALU_dec19_cr_out + connect \ALU_dec19_cry_in \ALU_dec19_ALU_dec19_cry_in + connect \ALU_dec19_cry_out \ALU_dec19_ALU_dec19_cry_out + connect \ALU_dec19_function_unit \ALU_dec19_ALU_dec19_function_unit + connect \ALU_dec19_in1_sel \ALU_dec19_ALU_dec19_in1_sel + connect \ALU_dec19_in2_sel \ALU_dec19_ALU_dec19_in2_sel + connect \ALU_dec19_internal_op \ALU_dec19_ALU_dec19_internal_op + connect \ALU_dec19_inv_a \ALU_dec19_ALU_dec19_inv_a + connect \ALU_dec19_inv_out \ALU_dec19_ALU_dec19_inv_out + connect \ALU_dec19_is_32b \ALU_dec19_ALU_dec19_is_32b + connect \ALU_dec19_ldst_len \ALU_dec19_ALU_dec19_ldst_len + connect \ALU_dec19_rc_sel \ALU_dec19_ALU_dec19_rc_sel + connect \ALU_dec19_sgn \ALU_dec19_ALU_dec19_sgn + connect \opcode_in \ALU_dec19_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:52209.13-52225.4" + cell \ALU_dec31 \ALU_dec31 + connect \ALU_dec31_cr_in \ALU_dec31_ALU_dec31_cr_in + connect \ALU_dec31_cr_out \ALU_dec31_ALU_dec31_cr_out + connect \ALU_dec31_cry_in \ALU_dec31_ALU_dec31_cry_in + connect \ALU_dec31_cry_out \ALU_dec31_ALU_dec31_cry_out + connect \ALU_dec31_function_unit \ALU_dec31_ALU_dec31_function_unit + connect \ALU_dec31_in1_sel \ALU_dec31_ALU_dec31_in1_sel + connect \ALU_dec31_in2_sel \ALU_dec31_ALU_dec31_in2_sel + connect \ALU_dec31_internal_op \ALU_dec31_ALU_dec31_internal_op + connect \ALU_dec31_inv_a \ALU_dec31_ALU_dec31_inv_a + connect \ALU_dec31_inv_out \ALU_dec31_ALU_dec31_inv_out + connect \ALU_dec31_is_32b \ALU_dec31_ALU_dec31_is_32b + connect \ALU_dec31_ldst_len \ALU_dec31_ALU_dec31_ldst_len + connect \ALU_dec31_rc_sel \ALU_dec31_ALU_dec31_rc_sel + connect \ALU_dec31_sgn \ALU_dec31_ALU_dec31_sgn + connect \opcode_in \ALU_dec31_opcode_in + end + attribute \src "libresoc.v:51018.7-51018.20" + process $proc$libresoc.v:51018$3456 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:52226.3-52259.6" + process $proc$libresoc.v:52226$3442 + assign { } { } + assign { } { } + assign $0\ALU_rc_sel[1:0] $1\ALU_rc_sel[1:0] + attribute \src "libresoc.v:52227.5-52227.29" + switch \initial + attribute \src "libresoc.v:52227.9-52227.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_rc_sel[1:0] \ALU_dec19_ALU_dec19_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_rc_sel[1:0] \ALU_dec31_ALU_dec31_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_rc_sel[1:0] 2'00 + case + assign $1\ALU_rc_sel[1:0] 2'00 + end + sync always + update \ALU_rc_sel $0\ALU_rc_sel[1:0] + end + attribute \src "libresoc.v:52260.3-52293.6" + process $proc$libresoc.v:52260$3443 + assign { } { } + assign { } { } + assign $0\ALU_cry_in[1:0] $1\ALU_cry_in[1:0] + attribute \src "libresoc.v:52261.5-52261.29" + switch \initial + attribute \src "libresoc.v:52261.9-52261.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_cry_in[1:0] \ALU_dec19_ALU_dec19_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_cry_in[1:0] \ALU_dec31_ALU_dec31_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_cry_in[1:0] 2'01 + case + assign $1\ALU_cry_in[1:0] 2'00 + end + sync always + update \ALU_cry_in $0\ALU_cry_in[1:0] + end + attribute \src "libresoc.v:52294.3-52327.6" + process $proc$libresoc.v:52294$3444 + assign { } { } + assign { } { } + assign $0\ALU_inv_a[0:0] $1\ALU_inv_a[0:0] + attribute \src "libresoc.v:52295.5-52295.29" + switch \initial + attribute \src "libresoc.v:52295.9-52295.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_inv_a[0:0] \ALU_dec19_ALU_dec19_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_inv_a[0:0] \ALU_dec31_ALU_dec31_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_inv_a[0:0] 1'1 + case + assign $1\ALU_inv_a[0:0] 1'0 + end + sync always + update \ALU_inv_a $0\ALU_inv_a[0:0] + end + attribute \src "libresoc.v:52328.3-52361.6" + process $proc$libresoc.v:52328$3445 + assign { } { } + assign { } { } + assign $0\ALU_inv_out[0:0] $1\ALU_inv_out[0:0] + attribute \src "libresoc.v:52329.5-52329.29" + switch \initial + attribute \src "libresoc.v:52329.9-52329.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_inv_out[0:0] \ALU_dec19_ALU_dec19_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_inv_out[0:0] \ALU_dec31_ALU_dec31_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_inv_out[0:0] 1'0 + case + assign $1\ALU_inv_out[0:0] 1'0 + end + sync always + update \ALU_inv_out $0\ALU_inv_out[0:0] + end + attribute \src "libresoc.v:52362.3-52395.6" + process $proc$libresoc.v:52362$3446 + assign { } { } + assign { } { } + assign $0\ALU_cry_out[0:0] $1\ALU_cry_out[0:0] + attribute \src "libresoc.v:52363.5-52363.29" + switch \initial + attribute \src "libresoc.v:52363.9-52363.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_cry_out[0:0] \ALU_dec19_ALU_dec19_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_cry_out[0:0] \ALU_dec31_ALU_dec31_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_cry_out[0:0] 1'1 + case + assign $1\ALU_cry_out[0:0] 1'0 + end + sync always + update \ALU_cry_out $0\ALU_cry_out[0:0] + end + attribute \src "libresoc.v:52396.3-52429.6" + process $proc$libresoc.v:52396$3447 + assign { } { } + assign { } { } + assign $0\ALU_is_32b[0:0] $1\ALU_is_32b[0:0] + attribute \src "libresoc.v:52397.5-52397.29" + switch \initial + attribute \src "libresoc.v:52397.9-52397.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_is_32b[0:0] \ALU_dec19_ALU_dec19_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_is_32b[0:0] \ALU_dec31_ALU_dec31_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_is_32b[0:0] 1'0 + case + assign $1\ALU_is_32b[0:0] 1'0 + end + sync always + update \ALU_is_32b $0\ALU_is_32b[0:0] + end + attribute \src "libresoc.v:52430.3-52463.6" + process $proc$libresoc.v:52430$3448 + assign { } { } + assign { } { } + assign $0\ALU_sgn[0:0] $1\ALU_sgn[0:0] + attribute \src "libresoc.v:52431.5-52431.29" + switch \initial + attribute \src "libresoc.v:52431.9-52431.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_sgn[0:0] \ALU_dec19_ALU_dec19_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_sgn[0:0] \ALU_dec31_ALU_dec31_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_sgn[0:0] 1'0 + case + assign $1\ALU_sgn[0:0] 1'0 + end + sync always + update \ALU_sgn $0\ALU_sgn[0:0] + end + attribute \src "libresoc.v:52464.3-52497.6" + process $proc$libresoc.v:52464$3449 + assign { } { } + assign { } { } + assign $0\ALU_function_unit[11:0] $1\ALU_function_unit[11:0] + attribute \src "libresoc.v:52465.5-52465.29" + switch \initial + attribute \src "libresoc.v:52465.9-52465.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_function_unit[11:0] \ALU_dec19_ALU_dec19_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_function_unit[11:0] \ALU_dec31_ALU_dec31_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_function_unit[11:0] 12'000000000010 + case + assign $1\ALU_function_unit[11:0] 12'000000000000 + end + sync always + update \ALU_function_unit $0\ALU_function_unit[11:0] + end + attribute \src "libresoc.v:52498.3-52531.6" + process $proc$libresoc.v:52498$3450 + assign { } { } + assign { } { } + assign $0\ALU_internal_op[6:0] $1\ALU_internal_op[6:0] + attribute \src "libresoc.v:52499.5-52499.29" + switch \initial + attribute \src "libresoc.v:52499.9-52499.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_internal_op[6:0] \ALU_dec19_ALU_dec19_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_internal_op[6:0] \ALU_dec31_ALU_dec31_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_internal_op[6:0] 7'0000010 + case + assign $1\ALU_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_internal_op $0\ALU_internal_op[6:0] + end + attribute \src "libresoc.v:52532.3-52565.6" + process $proc$libresoc.v:52532$3451 + assign { } { } + assign { } { } + assign $0\ALU_in1_sel[2:0] $1\ALU_in1_sel[2:0] + attribute \src "libresoc.v:52533.5-52533.29" + switch \initial + attribute \src "libresoc.v:52533.9-52533.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_in1_sel[2:0] \ALU_dec19_ALU_dec19_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_in1_sel[2:0] \ALU_dec31_ALU_dec31_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_in1_sel[2:0] 3'001 + case + assign $1\ALU_in1_sel[2:0] 3'000 + end + sync always + update \ALU_in1_sel $0\ALU_in1_sel[2:0] + end + attribute \src "libresoc.v:52566.3-52599.6" + process $proc$libresoc.v:52566$3452 + assign { } { } + assign { } { } + assign $0\ALU_in2_sel[3:0] $1\ALU_in2_sel[3:0] + attribute \src "libresoc.v:52567.5-52567.29" + switch \initial + attribute \src "libresoc.v:52567.9-52567.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_in2_sel[3:0] \ALU_dec19_ALU_dec19_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_in2_sel[3:0] \ALU_dec31_ALU_dec31_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_in2_sel[3:0] 4'0101 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_in2_sel[3:0] 4'0011 + case + assign $1\ALU_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_in2_sel $0\ALU_in2_sel[3:0] + end + attribute \src "libresoc.v:52600.3-52633.6" + process $proc$libresoc.v:52600$3453 + assign { } { } + assign { } { } + assign $0\ALU_cr_in[2:0] $1\ALU_cr_in[2:0] + attribute \src "libresoc.v:52601.5-52601.29" + switch \initial + attribute \src "libresoc.v:52601.9-52601.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_cr_in[2:0] \ALU_dec19_ALU_dec19_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_cr_in[2:0] \ALU_dec31_ALU_dec31_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_cr_in[2:0] 3'000 + case + assign $1\ALU_cr_in[2:0] 3'000 + end + sync always + update \ALU_cr_in $0\ALU_cr_in[2:0] + end + attribute \src "libresoc.v:52634.3-52667.6" + process $proc$libresoc.v:52634$3454 + assign { } { } + assign { } { } + assign $0\ALU_cr_out[2:0] $1\ALU_cr_out[2:0] + attribute \src "libresoc.v:52635.5-52635.29" + switch \initial + attribute \src "libresoc.v:52635.9-52635.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_cr_out[2:0] \ALU_dec19_ALU_dec19_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_cr_out[2:0] \ALU_dec31_ALU_dec31_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_cr_out[2:0] 3'000 + case + assign $1\ALU_cr_out[2:0] 3'000 + end + sync always + update \ALU_cr_out $0\ALU_cr_out[2:0] + end + attribute \src "libresoc.v:52668.3-52701.6" + process $proc$libresoc.v:52668$3455 + assign { } { } + assign { } { } + assign $0\ALU_ldst_len[3:0] $1\ALU_ldst_len[3:0] + attribute \src "libresoc.v:52669.5-52669.29" + switch \initial + attribute \src "libresoc.v:52669.9-52669.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_ldst_len[3:0] \ALU_dec19_ALU_dec19_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_ldst_len[3:0] \ALU_dec31_ALU_dec31_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_ldst_len[3:0] 4'0000 + case + assign $1\ALU_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_ldst_len $0\ALU_ldst_len[3:0] + end + connect \$1 $ternary$libresoc.v:52191$3441_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \ALU_SPR \opcode_in [20:11] + connect \ALU_MB \opcode_in [10:6] + connect \ALU_ME \opcode_in [5:1] + connect \ALU_SH \opcode_in [15:11] + connect \ALU_BC \opcode_in [10:6] + connect \ALU_TO \opcode_in [25:21] + connect \ALU_DS \opcode_in [15:2] + connect \ALU_D \opcode_in [15:0] + connect \ALU_BH \opcode_in [12:11] + connect \ALU_BI \opcode_in [20:16] + connect \ALU_BO \opcode_in [25:21] + connect \ALU_FXM \opcode_in [19:12] + connect \ALU_BT \opcode_in [25:21] + connect \ALU_BA \opcode_in [20:16] + connect \ALU_BB \opcode_in [15:11] + connect \ALU_CR \opcode_in [10:1] + connect \ALU_BF \opcode_in [25:23] + connect \ALU_BD \opcode_in [15:2] + connect \ALU_OE \opcode_in [10] + connect \ALU_Rc \opcode_in [0] + connect \ALU_AA \opcode_in [1] + connect \ALU_LK \opcode_in [0] + connect \ALU_LI \opcode_in [25:2] + connect \ALU_ME32 \opcode_in [5:1] + connect \ALU_MB32 \opcode_in [10:6] + connect \ALU_sh { \opcode_in [1] \opcode_in [15:11] } + connect \ALU_SH32 \opcode_in [15:11] + connect \ALU_L \opcode_in [21] + connect \ALU_UI \opcode_in [15:0] + connect \ALU_SI \opcode_in [15:0] + connect \ALU_RB \opcode_in [15:11] + connect \ALU_RA \opcode_in [20:16] + connect \ALU_RT \opcode_in [25:21] + connect \ALU_RS \opcode_in [25:21] + connect \opcode_in \$1 + connect \ALU_dec31_opcode_in \opcode_in + connect \ALU_dec19_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:53036.1-54466.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec" +attribute \generator "nMigen" +module \dec$140 + attribute \src "libresoc.v:54097.3-54109.6" + wire width 3 $0\CR_cr_in[2:0] + attribute \src "libresoc.v:54110.3-54122.6" + wire width 3 $0\CR_cr_out[2:0] + attribute \src "libresoc.v:54071.3-54083.6" + wire width 12 $0\CR_function_unit[11:0] + attribute \src "libresoc.v:54084.3-54096.6" + wire width 7 $0\CR_internal_op[6:0] + attribute \src "libresoc.v:54123.3-54135.6" + wire width 2 $0\CR_rc_sel[1:0] + attribute \src "libresoc.v:53037.7-53037.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:54097.3-54109.6" + wire width 3 $1\CR_cr_in[2:0] + attribute \src "libresoc.v:54110.3-54122.6" + wire width 3 $1\CR_cr_out[2:0] + attribute \src "libresoc.v:54071.3-54083.6" + wire width 12 $1\CR_function_unit[11:0] + attribute \src "libresoc.v:54084.3-54096.6" + wire width 7 $1\CR_internal_op[6:0] + attribute \src "libresoc.v:54123.3-54135.6" + wire width 2 $1\CR_rc_sel[1:0] + attribute \src "libresoc.v:54054.17-54054.211" + wire width 32 $ternary$libresoc.v:54054$3457_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \CR_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 11 \CR_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 10 \CR_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 15 \CR_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 \CR_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 3 \CR_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 2 \CR_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 14 \CR_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \CR_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 12 \CR_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 10 \CR_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 \CR_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 \CR_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 output 13 \CR_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \CR_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 24 \CR_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \CR_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \CR_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \CR_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \CR_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \CR_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire output 9 \CR_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \CR_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \CR_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \CR_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \CR_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire output 8 \CR_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \CR_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \CR_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 \CR_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 10 \CR_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \CR_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 \CR_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 4 \CR_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \CR_cr_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \CR_dec19_CR_dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \CR_dec19_CR_dec19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 \CR_dec19_CR_dec19_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute 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wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \XX2_DCMX + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_dm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX3_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX3_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX3_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XX3_BF + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_SP + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + wire input 1 \bigendian + attribute \src "libresoc.v:53037.7-53037.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + wire width 32 input 19 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + cell $mux $ternary$libresoc.v:54054$3457 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:54054$3457_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:54055.12-54062.4" + cell \CR_dec19 \CR_dec19 + connect \CR_dec19_cr_in \CR_dec19_CR_dec19_cr_in + connect \CR_dec19_cr_out \CR_dec19_CR_dec19_cr_out + connect \CR_dec19_function_unit \CR_dec19_CR_dec19_function_unit + connect \CR_dec19_internal_op \CR_dec19_CR_dec19_internal_op + connect \CR_dec19_rc_sel \CR_dec19_CR_dec19_rc_sel + connect \opcode_in \CR_dec19_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:54063.12-54070.4" + cell \CR_dec31 \CR_dec31 + connect \CR_dec31_cr_in \CR_dec31_CR_dec31_cr_in + connect \CR_dec31_cr_out \CR_dec31_CR_dec31_cr_out + connect \CR_dec31_function_unit \CR_dec31_CR_dec31_function_unit + connect \CR_dec31_internal_op \CR_dec31_CR_dec31_internal_op + connect \CR_dec31_rc_sel \CR_dec31_CR_dec31_rc_sel + connect \opcode_in \CR_dec31_opcode_in + end + attribute \src "libresoc.v:53037.7-53037.20" + process $proc$libresoc.v:53037$3463 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:54071.3-54083.6" + process $proc$libresoc.v:54071$3458 + assign { } { } + assign { } { } + assign $0\CR_function_unit[11:0] $1\CR_function_unit[11:0] + attribute \src "libresoc.v:54072.5-54072.29" + switch \initial + attribute \src "libresoc.v:54072.9-54072.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\CR_function_unit[11:0] \CR_dec19_CR_dec19_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\CR_function_unit[11:0] \CR_dec31_CR_dec31_function_unit + case + assign $1\CR_function_unit[11:0] 12'000000000000 + end + sync always + update \CR_function_unit $0\CR_function_unit[11:0] + end + attribute \src "libresoc.v:54084.3-54096.6" + process $proc$libresoc.v:54084$3459 + assign { } { } + assign { } { } + assign $0\CR_internal_op[6:0] $1\CR_internal_op[6:0] + attribute \src "libresoc.v:54085.5-54085.29" + switch \initial + attribute \src "libresoc.v:54085.9-54085.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\CR_internal_op[6:0] \CR_dec19_CR_dec19_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\CR_internal_op[6:0] \CR_dec31_CR_dec31_internal_op + case + assign $1\CR_internal_op[6:0] 7'0000000 + end + sync always + update \CR_internal_op $0\CR_internal_op[6:0] + end + attribute \src "libresoc.v:54097.3-54109.6" + process $proc$libresoc.v:54097$3460 + assign { } { } + assign { } { } + assign $0\CR_cr_in[2:0] $1\CR_cr_in[2:0] + attribute \src "libresoc.v:54098.5-54098.29" + switch \initial + attribute \src "libresoc.v:54098.9-54098.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\CR_cr_in[2:0] \CR_dec19_CR_dec19_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\CR_cr_in[2:0] \CR_dec31_CR_dec31_cr_in + case + assign $1\CR_cr_in[2:0] 3'000 + end + sync always + update \CR_cr_in $0\CR_cr_in[2:0] + end + attribute \src "libresoc.v:54110.3-54122.6" + process $proc$libresoc.v:54110$3461 + assign { } { } + assign { } { } + assign $0\CR_cr_out[2:0] $1\CR_cr_out[2:0] + attribute \src "libresoc.v:54111.5-54111.29" + switch \initial + attribute \src "libresoc.v:54111.9-54111.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\CR_cr_out[2:0] \CR_dec19_CR_dec19_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\CR_cr_out[2:0] \CR_dec31_CR_dec31_cr_out + case + assign $1\CR_cr_out[2:0] 3'000 + end + sync always + update \CR_cr_out $0\CR_cr_out[2:0] + end + attribute \src "libresoc.v:54123.3-54135.6" + process $proc$libresoc.v:54123$3462 + assign { } { } + assign { } { } + assign $0\CR_rc_sel[1:0] $1\CR_rc_sel[1:0] + attribute \src "libresoc.v:54124.5-54124.29" + switch \initial + attribute \src "libresoc.v:54124.9-54124.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\CR_rc_sel[1:0] \CR_dec19_CR_dec19_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\CR_rc_sel[1:0] \CR_dec31_CR_dec31_rc_sel + case + assign $1\CR_rc_sel[1:0] 2'00 + end + sync always + update \CR_rc_sel $0\CR_rc_sel[1:0] + end + connect \$1 $ternary$libresoc.v:54054$3457_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \CR_SPR \opcode_in [20:11] + connect \CR_MB \opcode_in [10:6] + connect \CR_ME \opcode_in [5:1] + connect \CR_SH \opcode_in [15:11] + connect \CR_BC \opcode_in [10:6] + connect \CR_TO \opcode_in [25:21] + connect \CR_DS \opcode_in [15:2] + connect \CR_D \opcode_in [15:0] + connect \CR_BH \opcode_in [12:11] + connect \CR_BI \opcode_in [20:16] + connect \CR_BO \opcode_in [25:21] + connect \CR_FXM \opcode_in [19:12] + connect \CR_BT \opcode_in [25:21] + connect \CR_BA \opcode_in [20:16] + connect \CR_BB \opcode_in [15:11] + connect \CR_CR \opcode_in [10:1] + connect \CR_BF \opcode_in [25:23] + connect \CR_BD \opcode_in [15:2] + connect \CR_OE \opcode_in [10] + connect \CR_Rc \opcode_in [0] + connect \CR_AA \opcode_in [1] + connect \CR_LK \opcode_in [0] + connect \CR_LI \opcode_in [25:2] + connect \CR_ME32 \opcode_in [5:1] + connect \CR_MB32 \opcode_in [10:6] + connect \CR_sh { \opcode_in [1] \opcode_in [15:11] } + connect \CR_SH32 \opcode_in [15:11] + connect \CR_L \opcode_in [21] + connect \CR_UI \opcode_in [15:0] + connect \CR_SI \opcode_in [15:0] + connect \CR_RB \opcode_in [15:11] + connect \CR_RA \opcode_in [20:16] + connect \CR_RT \opcode_in [25:21] + connect \CR_RS \opcode_in [25:21] + connect \opcode_in \$1 + connect \CR_dec31_opcode_in \opcode_in + connect \CR_dec19_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:54470.1-55885.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec" +attribute \generator "nMigen" +module \dec$147 + attribute \src "libresoc.v:55476.3-55491.6" + wire width 3 $0\BRANCH_cr_in[2:0] + attribute \src "libresoc.v:55492.3-55507.6" + wire width 3 $0\BRANCH_cr_out[2:0] + attribute \src "libresoc.v:55428.3-55443.6" + wire width 12 $0\BRANCH_function_unit[11:0] + attribute \src "libresoc.v:55460.3-55475.6" + wire width 4 $0\BRANCH_in2_sel[3:0] + attribute \src "libresoc.v:55444.3-55459.6" + wire width 7 $0\BRANCH_internal_op[6:0] + attribute \src "libresoc.v:55524.3-55539.6" + wire $0\BRANCH_is_32b[0:0] + attribute \src "libresoc.v:55540.3-55555.6" + wire $0\BRANCH_lk[0:0] + attribute \src "libresoc.v:55508.3-55523.6" + wire width 2 $0\BRANCH_rc_sel[1:0] + attribute \src "libresoc.v:54471.7-54471.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:55476.3-55491.6" + wire width 3 $1\BRANCH_cr_in[2:0] + attribute \src "libresoc.v:55492.3-55507.6" + wire width 3 $1\BRANCH_cr_out[2:0] + attribute \src "libresoc.v:55428.3-55443.6" + wire width 12 $1\BRANCH_function_unit[11:0] + attribute \src "libresoc.v:55460.3-55475.6" + wire width 4 $1\BRANCH_in2_sel[3:0] + attribute \src "libresoc.v:55444.3-55459.6" + wire width 7 $1\BRANCH_internal_op[6:0] + attribute \src "libresoc.v:55524.3-55539.6" + wire $1\BRANCH_is_32b[0:0] + attribute \src "libresoc.v:55540.3-55555.6" + wire $1\BRANCH_lk[0:0] + attribute \src "libresoc.v:55508.3-55523.6" + wire width 2 $1\BRANCH_rc_sel[1:0] + attribute \src "libresoc.v:55416.17-55416.211" + wire width 32 $ternary$libresoc.v:55416$3464_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \BRANCH_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 21 \BRANCH_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 20 \BRANCH_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 26 \BRANCH_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 output 19 \BRANCH_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 3 \BRANCH_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 2 \BRANCH_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 24 \BRANCH_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \BRANCH_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 22 \BRANCH_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 10 \BRANCH_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 \BRANCH_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 output 25 \BRANCH_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 output 23 \BRANCH_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \BRANCH_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 24 output 16 \BRANCH_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire output 11 \BRANCH_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \BRANCH_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \BRANCH_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \BRANCH_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \BRANCH_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire output 18 \BRANCH_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \BRANCH_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \BRANCH_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \BRANCH_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \BRANCH_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire output 17 \BRANCH_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \BRANCH_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 14 \BRANCH_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 output 12 \BRANCH_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 10 \BRANCH_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \BRANCH_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 output 13 \BRANCH_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 4 \BRANCH_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \BRANCH_cr_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \BRANCH_dec19_BRANCH_dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \BRANCH_dec19_BRANCH_dec19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 \BRANCH_dec19_BRANCH_dec19_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \BRANCH_dec19_BRANCH_dec19_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \BRANCH_dec19_BRANCH_dec19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \BRANCH_dec19_BRANCH_dec19_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \BRANCH_dec19_BRANCH_dec19_lk + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \BRANCH_dec19_BRANCH_dec19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \BRANCH_dec19_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 7 \BRANCH_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 8 \BRANCH_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 6 \BRANCH_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 9 \BRANCH_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 10 \BRANCH_lk + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 3 \BRANCH_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 6 output 15 \BRANCH_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XL_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 output 29 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 15 \XL_OC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XO_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XO_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX2_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \XX2_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XX2_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \XX2_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XX2_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_dm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX3_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX3_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX3_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XX3_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX3_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XX3_DM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XX3_SHW + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX3_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX3_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \XX3_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \XX3_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XX3_XO_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX4_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX4_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX4_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX4_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX4_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX4_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX4_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX4_CX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX4_CX_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX4_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX4_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX4_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XX4_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 output 27 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 output 28 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \X_CT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \X_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \X_DRM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_E + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_EO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_EX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \X_E_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \X_IH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \X_IMM8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_L1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_L2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_L3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_MO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_NB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_PRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_RIC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_RM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_RO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_R_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_SP + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + wire input 1 \bigendian + attribute \src "libresoc.v:54471.7-54471.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + wire width 32 input 30 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + cell $mux $ternary$libresoc.v:55416$3464 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:55416$3464_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:55417.16-55427.4" + cell \BRANCH_dec19 \BRANCH_dec19 + connect \BRANCH_dec19_cr_in \BRANCH_dec19_BRANCH_dec19_cr_in + connect \BRANCH_dec19_cr_out \BRANCH_dec19_BRANCH_dec19_cr_out + connect \BRANCH_dec19_function_unit \BRANCH_dec19_BRANCH_dec19_function_unit + connect \BRANCH_dec19_in2_sel \BRANCH_dec19_BRANCH_dec19_in2_sel + connect \BRANCH_dec19_internal_op \BRANCH_dec19_BRANCH_dec19_internal_op + connect \BRANCH_dec19_is_32b \BRANCH_dec19_BRANCH_dec19_is_32b + connect \BRANCH_dec19_lk \BRANCH_dec19_BRANCH_dec19_lk + connect \BRANCH_dec19_rc_sel \BRANCH_dec19_BRANCH_dec19_rc_sel + connect \opcode_in \BRANCH_dec19_opcode_in + end + attribute \src "libresoc.v:54471.7-54471.20" + process $proc$libresoc.v:54471$3473 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:55428.3-55443.6" + process $proc$libresoc.v:55428$3465 + assign { } { } + assign { } { } + assign $0\BRANCH_function_unit[11:0] $1\BRANCH_function_unit[11:0] + attribute \src "libresoc.v:55429.5-55429.29" + switch \initial + attribute \src "libresoc.v:55429.9-55429.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_function_unit[11:0] \BRANCH_dec19_BRANCH_dec19_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_function_unit[11:0] 12'000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_function_unit[11:0] 12'000000100000 + case + assign $1\BRANCH_function_unit[11:0] 12'000000000000 + end + sync always + update \BRANCH_function_unit $0\BRANCH_function_unit[11:0] + end + attribute \src "libresoc.v:55444.3-55459.6" + process $proc$libresoc.v:55444$3466 + assign { } { } + assign { } { } + assign $0\BRANCH_internal_op[6:0] $1\BRANCH_internal_op[6:0] + attribute \src "libresoc.v:55445.5-55445.29" + switch \initial + attribute \src "libresoc.v:55445.9-55445.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_internal_op[6:0] \BRANCH_dec19_BRANCH_dec19_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_internal_op[6:0] 7'0000110 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_internal_op[6:0] 7'0000111 + case + assign $1\BRANCH_internal_op[6:0] 7'0000000 + end + sync always + update \BRANCH_internal_op $0\BRANCH_internal_op[6:0] + end + attribute \src "libresoc.v:55460.3-55475.6" + process $proc$libresoc.v:55460$3467 + assign { } { } + assign { } { } + assign $0\BRANCH_in2_sel[3:0] $1\BRANCH_in2_sel[3:0] + attribute \src "libresoc.v:55461.5-55461.29" + switch \initial + attribute \src "libresoc.v:55461.9-55461.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_in2_sel[3:0] \BRANCH_dec19_BRANCH_dec19_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_in2_sel[3:0] 4'0110 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_in2_sel[3:0] 4'0111 + case + assign $1\BRANCH_in2_sel[3:0] 4'0000 + end + sync always + update \BRANCH_in2_sel $0\BRANCH_in2_sel[3:0] + end + attribute \src "libresoc.v:55476.3-55491.6" + process $proc$libresoc.v:55476$3468 + assign { } { } + assign { } { } + assign $0\BRANCH_cr_in[2:0] $1\BRANCH_cr_in[2:0] + attribute \src "libresoc.v:55477.5-55477.29" + switch \initial + attribute \src "libresoc.v:55477.9-55477.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_cr_in[2:0] \BRANCH_dec19_BRANCH_dec19_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_cr_in[2:0] 3'010 + case + assign $1\BRANCH_cr_in[2:0] 3'000 + end + sync always + update \BRANCH_cr_in $0\BRANCH_cr_in[2:0] + end + attribute \src "libresoc.v:55492.3-55507.6" + process $proc$libresoc.v:55492$3469 + assign { } { } + assign { } { } + assign $0\BRANCH_cr_out[2:0] $1\BRANCH_cr_out[2:0] + attribute \src "libresoc.v:55493.5-55493.29" + switch \initial + attribute \src "libresoc.v:55493.9-55493.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_cr_out[2:0] \BRANCH_dec19_BRANCH_dec19_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_cr_out[2:0] 3'000 + case + assign $1\BRANCH_cr_out[2:0] 3'000 + end + sync always + update \BRANCH_cr_out $0\BRANCH_cr_out[2:0] + end + attribute \src "libresoc.v:55508.3-55523.6" + process $proc$libresoc.v:55508$3470 + assign { } { } + assign { } { } + assign $0\BRANCH_rc_sel[1:0] $1\BRANCH_rc_sel[1:0] + attribute \src "libresoc.v:55509.5-55509.29" + switch \initial + attribute \src "libresoc.v:55509.9-55509.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_rc_sel[1:0] \BRANCH_dec19_BRANCH_dec19_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_rc_sel[1:0] 2'00 + case + assign $1\BRANCH_rc_sel[1:0] 2'00 + end + sync always + update \BRANCH_rc_sel $0\BRANCH_rc_sel[1:0] + end + attribute \src "libresoc.v:55524.3-55539.6" + process $proc$libresoc.v:55524$3471 + assign { } { } + assign { } { } + assign $0\BRANCH_is_32b[0:0] $1\BRANCH_is_32b[0:0] + attribute \src "libresoc.v:55525.5-55525.29" + switch \initial + attribute \src "libresoc.v:55525.9-55525.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_is_32b[0:0] \BRANCH_dec19_BRANCH_dec19_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_is_32b[0:0] 1'0 + case + assign $1\BRANCH_is_32b[0:0] 1'0 + end + sync always + update \BRANCH_is_32b $0\BRANCH_is_32b[0:0] + end + attribute \src "libresoc.v:55540.3-55555.6" + process $proc$libresoc.v:55540$3472 + assign { } { } + assign { } { } + assign $0\BRANCH_lk[0:0] $1\BRANCH_lk[0:0] + attribute \src "libresoc.v:55541.5-55541.29" + switch \initial + attribute \src "libresoc.v:55541.9-55541.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_lk[0:0] \BRANCH_dec19_BRANCH_dec19_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_lk[0:0] 1'1 + case + assign $1\BRANCH_lk[0:0] 1'0 + end + sync always + update \BRANCH_lk $0\BRANCH_lk[0:0] + end + connect \$1 $ternary$libresoc.v:55416$3464_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \BRANCH_SPR \opcode_in [20:11] + connect \BRANCH_MB \opcode_in [10:6] + connect \BRANCH_ME \opcode_in [5:1] + connect \BRANCH_SH \opcode_in [15:11] + connect \BRANCH_BC \opcode_in [10:6] + connect \BRANCH_TO \opcode_in [25:21] + connect \BRANCH_DS \opcode_in [15:2] + connect \BRANCH_D \opcode_in [15:0] + connect \BRANCH_BH \opcode_in [12:11] + connect \BRANCH_BI \opcode_in [20:16] + connect \BRANCH_BO \opcode_in [25:21] + connect \BRANCH_FXM \opcode_in [19:12] + connect \BRANCH_BT \opcode_in [25:21] + connect \BRANCH_BA \opcode_in [20:16] + connect \BRANCH_BB \opcode_in [15:11] + connect \BRANCH_CR \opcode_in [10:1] + connect \BRANCH_BF \opcode_in [25:23] + connect \BRANCH_BD \opcode_in [15:2] + connect \BRANCH_OE \opcode_in [10] + connect \BRANCH_Rc \opcode_in [0] + connect \BRANCH_AA \opcode_in [1] + connect \BRANCH_LK \opcode_in [0] + connect \BRANCH_LI \opcode_in [25:2] + connect \BRANCH_ME32 \opcode_in [5:1] + connect \BRANCH_MB32 \opcode_in [10:6] + connect \BRANCH_sh { \opcode_in [1] \opcode_in [15:11] } + connect \BRANCH_SH32 \opcode_in [15:11] + connect \BRANCH_L \opcode_in [21] + connect \BRANCH_UI \opcode_in [15:0] + connect \BRANCH_SI \opcode_in [15:0] + connect \BRANCH_RB \opcode_in [15:11] + connect \BRANCH_RA \opcode_in [20:16] + connect \BRANCH_RT \opcode_in [25:21] + connect \BRANCH_RS \opcode_in [25:21] + connect \opcode_in \$1 + connect \BRANCH_dec19_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:55889.1-57636.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec" +attribute \generator "nMigen" +module \dec$155 + attribute \src "libresoc.v:57195.3-57222.6" + wire width 3 $0\LOGICAL_cr_in[2:0] + attribute \src "libresoc.v:57223.3-57250.6" + wire width 3 $0\LOGICAL_cr_out[2:0] + attribute \src "libresoc.v:56915.3-56942.6" + wire width 2 $0\LOGICAL_cry_in[1:0] + attribute \src "libresoc.v:56999.3-57026.6" + wire $0\LOGICAL_cry_out[0:0] + attribute \src "libresoc.v:57083.3-57110.6" + wire width 12 $0\LOGICAL_function_unit[11:0] + attribute \src "libresoc.v:57139.3-57166.6" + wire width 3 $0\LOGICAL_in1_sel[2:0] + attribute \src "libresoc.v:57167.3-57194.6" + wire width 4 $0\LOGICAL_in2_sel[3:0] + attribute \src "libresoc.v:57111.3-57138.6" + wire width 7 $0\LOGICAL_internal_op[6:0] + attribute \src "libresoc.v:56943.3-56970.6" + wire $0\LOGICAL_inv_a[0:0] + attribute \src "libresoc.v:56971.3-56998.6" + wire $0\LOGICAL_inv_out[0:0] + attribute \src "libresoc.v:57027.3-57054.6" + wire $0\LOGICAL_is_32b[0:0] + attribute \src "libresoc.v:57251.3-57278.6" + wire width 4 $0\LOGICAL_ldst_len[3:0] + attribute \src "libresoc.v:57279.3-57306.6" + wire width 2 $0\LOGICAL_rc_sel[1:0] + attribute \src "libresoc.v:57055.3-57082.6" + wire $0\LOGICAL_sgn[0:0] + attribute \src "libresoc.v:55890.7-55890.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:57195.3-57222.6" + wire width 3 $1\LOGICAL_cr_in[2:0] + attribute \src "libresoc.v:57223.3-57250.6" + wire width 3 $1\LOGICAL_cr_out[2:0] + attribute \src "libresoc.v:56915.3-56942.6" + wire width 2 $1\LOGICAL_cry_in[1:0] + attribute \src "libresoc.v:56999.3-57026.6" + wire $1\LOGICAL_cry_out[0:0] + attribute \src "libresoc.v:57083.3-57110.6" + wire width 12 $1\LOGICAL_function_unit[11:0] + attribute \src "libresoc.v:57139.3-57166.6" + wire width 3 $1\LOGICAL_in1_sel[2:0] + attribute \src "libresoc.v:57167.3-57194.6" + wire width 4 $1\LOGICAL_in2_sel[3:0] + attribute \src "libresoc.v:57111.3-57138.6" + wire width 7 $1\LOGICAL_internal_op[6:0] + attribute \src "libresoc.v:56943.3-56970.6" + wire $1\LOGICAL_inv_a[0:0] + attribute \src "libresoc.v:56971.3-56998.6" + wire $1\LOGICAL_inv_out[0:0] + attribute \src "libresoc.v:57027.3-57054.6" + wire $1\LOGICAL_is_32b[0:0] + attribute \src "libresoc.v:57251.3-57278.6" + wire width 4 $1\LOGICAL_ldst_len[3:0] + attribute \src "libresoc.v:57279.3-57306.6" + wire width 2 $1\LOGICAL_rc_sel[1:0] + attribute \src "libresoc.v:57055.3-57082.6" + wire $1\LOGICAL_sgn[0:0] + attribute \src "libresoc.v:56897.17-56897.211" + wire width 32 $ternary$libresoc.v:56897$3474_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \LOGICAL_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 27 \LOGICAL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 26 \LOGICAL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 32 \LOGICAL_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 output 25 \LOGICAL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 3 \LOGICAL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 2 \LOGICAL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 30 \LOGICAL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \LOGICAL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 28 \LOGICAL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 10 \LOGICAL_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 \LOGICAL_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 output 31 \LOGICAL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 output 29 \LOGICAL_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \LOGICAL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 24 output 22 \LOGICAL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \LOGICAL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \LOGICAL_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \LOGICAL_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \LOGICAL_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \LOGICAL_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire output 24 \LOGICAL_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 17 \LOGICAL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \LOGICAL_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \LOGICAL_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \LOGICAL_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire output 23 \LOGICAL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \LOGICAL_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 20 \LOGICAL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 output 18 \LOGICAL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 10 \LOGICAL_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \LOGICAL_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 output 19 \LOGICAL_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 4 \LOGICAL_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \LOGICAL_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \LOGICAL_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 14 \LOGICAL_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \LOGICAL_dec31_LOGICAL_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \LOGICAL_dec31_LOGICAL_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \LOGICAL_dec31_LOGICAL_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \LOGICAL_dec31_LOGICAL_dec31_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 \LOGICAL_dec31_LOGICAL_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \LOGICAL_dec31_LOGICAL_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \LOGICAL_dec31_LOGICAL_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \LOGICAL_dec31_LOGICAL_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \LOGICAL_dec31_LOGICAL_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \LOGICAL_dec31_LOGICAL_dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \LOGICAL_dec31_LOGICAL_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \LOGICAL_dec31_LOGICAL_dec31_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \LOGICAL_dec31_LOGICAL_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \LOGICAL_dec31_LOGICAL_dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \LOGICAL_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 7 \LOGICAL_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 8 \LOGICAL_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 9 \LOGICAL_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 6 \LOGICAL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 11 \LOGICAL_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 12 \LOGICAL_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \LOGICAL_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 10 \LOGICAL_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 3 \LOGICAL_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \LOGICAL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 6 output 21 \LOGICAL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XL_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 output 35 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 15 \XL_OC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XO_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XO_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX2_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \XX2_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XX2_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \XX2_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XX2_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_dm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX3_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX3_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX3_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XX3_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX3_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XX3_DM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XX3_SHW + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX3_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX3_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \XX3_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \XX3_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XX3_XO_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX4_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX4_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX4_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX4_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX4_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX4_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX4_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX4_CX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX4_CX_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX4_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX4_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX4_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XX4_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 output 33 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 output 34 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \X_CT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \X_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \X_DRM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_E + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_EO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_EX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \X_E_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \X_IH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \X_IMM8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_L1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_L2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_L3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_MO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_NB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_PRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_RIC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_RM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_RO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_R_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_SP + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + wire input 1 \bigendian + attribute \src "libresoc.v:55890.7-55890.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + wire width 32 input 36 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + cell $mux $ternary$libresoc.v:56897$3474 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:56897$3474_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:56898.17-56914.4" + cell \LOGICAL_dec31 \LOGICAL_dec31 + connect \LOGICAL_dec31_cr_in \LOGICAL_dec31_LOGICAL_dec31_cr_in + connect \LOGICAL_dec31_cr_out \LOGICAL_dec31_LOGICAL_dec31_cr_out + connect \LOGICAL_dec31_cry_in \LOGICAL_dec31_LOGICAL_dec31_cry_in + connect \LOGICAL_dec31_cry_out \LOGICAL_dec31_LOGICAL_dec31_cry_out + connect \LOGICAL_dec31_function_unit \LOGICAL_dec31_LOGICAL_dec31_function_unit + connect \LOGICAL_dec31_in1_sel \LOGICAL_dec31_LOGICAL_dec31_in1_sel + connect \LOGICAL_dec31_in2_sel \LOGICAL_dec31_LOGICAL_dec31_in2_sel + connect \LOGICAL_dec31_internal_op \LOGICAL_dec31_LOGICAL_dec31_internal_op + connect \LOGICAL_dec31_inv_a \LOGICAL_dec31_LOGICAL_dec31_inv_a + connect \LOGICAL_dec31_inv_out \LOGICAL_dec31_LOGICAL_dec31_inv_out + connect \LOGICAL_dec31_is_32b \LOGICAL_dec31_LOGICAL_dec31_is_32b + connect \LOGICAL_dec31_ldst_len \LOGICAL_dec31_LOGICAL_dec31_ldst_len + connect \LOGICAL_dec31_rc_sel \LOGICAL_dec31_LOGICAL_dec31_rc_sel + connect \LOGICAL_dec31_sgn \LOGICAL_dec31_LOGICAL_dec31_sgn + connect \opcode_in \LOGICAL_dec31_opcode_in + end + attribute \src "libresoc.v:55890.7-55890.20" + process $proc$libresoc.v:55890$3489 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:56915.3-56942.6" + process $proc$libresoc.v:56915$3475 + assign { } { } + assign { } { } + assign $0\LOGICAL_cry_in[1:0] $1\LOGICAL_cry_in[1:0] + attribute \src "libresoc.v:56916.5-56916.29" + switch \initial + attribute \src "libresoc.v:56916.9-56916.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_cry_in[1:0] \LOGICAL_dec31_LOGICAL_dec31_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_cry_in[1:0] 2'00 + case + assign $1\LOGICAL_cry_in[1:0] 2'00 + end + sync always + update \LOGICAL_cry_in $0\LOGICAL_cry_in[1:0] + end + attribute \src "libresoc.v:56943.3-56970.6" + process $proc$libresoc.v:56943$3476 + assign { } { } + assign { } { } + assign $0\LOGICAL_inv_a[0:0] $1\LOGICAL_inv_a[0:0] + attribute \src "libresoc.v:56944.5-56944.29" + switch \initial + attribute \src "libresoc.v:56944.9-56944.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_inv_a[0:0] \LOGICAL_dec31_LOGICAL_dec31_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_inv_a[0:0] 1'0 + case + assign $1\LOGICAL_inv_a[0:0] 1'0 + end + sync always + update \LOGICAL_inv_a $0\LOGICAL_inv_a[0:0] + end + attribute \src "libresoc.v:56971.3-56998.6" + process $proc$libresoc.v:56971$3477 + assign { } { } + assign { } { } + assign $0\LOGICAL_inv_out[0:0] $1\LOGICAL_inv_out[0:0] + attribute \src "libresoc.v:56972.5-56972.29" + switch \initial + attribute \src "libresoc.v:56972.9-56972.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_inv_out[0:0] \LOGICAL_dec31_LOGICAL_dec31_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_inv_out[0:0] 1'0 + case + assign $1\LOGICAL_inv_out[0:0] 1'0 + end + sync always + update \LOGICAL_inv_out $0\LOGICAL_inv_out[0:0] + end + attribute \src "libresoc.v:56999.3-57026.6" + process $proc$libresoc.v:56999$3478 + assign { } { } + assign { } { } + assign $0\LOGICAL_cry_out[0:0] $1\LOGICAL_cry_out[0:0] + attribute \src "libresoc.v:57000.5-57000.29" + switch \initial + attribute \src "libresoc.v:57000.9-57000.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_cry_out[0:0] \LOGICAL_dec31_LOGICAL_dec31_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_cry_out[0:0] 1'0 + case + assign $1\LOGICAL_cry_out[0:0] 1'0 + end + sync always + update \LOGICAL_cry_out $0\LOGICAL_cry_out[0:0] + end + attribute \src "libresoc.v:57027.3-57054.6" + process $proc$libresoc.v:57027$3479 + assign { } { } + assign { } { } + assign $0\LOGICAL_is_32b[0:0] $1\LOGICAL_is_32b[0:0] + attribute \src "libresoc.v:57028.5-57028.29" + switch \initial + attribute \src "libresoc.v:57028.9-57028.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_is_32b[0:0] \LOGICAL_dec31_LOGICAL_dec31_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_is_32b[0:0] 1'0 + case + assign $1\LOGICAL_is_32b[0:0] 1'0 + end + sync always + update \LOGICAL_is_32b $0\LOGICAL_is_32b[0:0] + end + attribute \src "libresoc.v:57055.3-57082.6" + process $proc$libresoc.v:57055$3480 + assign { } { } + assign { } { } + assign $0\LOGICAL_sgn[0:0] $1\LOGICAL_sgn[0:0] + attribute \src "libresoc.v:57056.5-57056.29" + switch \initial + attribute \src "libresoc.v:57056.9-57056.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_sgn[0:0] \LOGICAL_dec31_LOGICAL_dec31_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_sgn[0:0] 1'0 + case + assign $1\LOGICAL_sgn[0:0] 1'0 + end + sync always + update \LOGICAL_sgn $0\LOGICAL_sgn[0:0] + end + attribute \src "libresoc.v:57083.3-57110.6" + process $proc$libresoc.v:57083$3481 + assign { } { } + assign { } { } + assign $0\LOGICAL_function_unit[11:0] $1\LOGICAL_function_unit[11:0] + attribute \src "libresoc.v:57084.5-57084.29" + switch \initial + attribute \src "libresoc.v:57084.9-57084.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_function_unit[11:0] \LOGICAL_dec31_LOGICAL_dec31_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_function_unit[11:0] 12'000000010000 + case + assign $1\LOGICAL_function_unit[11:0] 12'000000000000 + end + sync always + update \LOGICAL_function_unit $0\LOGICAL_function_unit[11:0] + end + attribute \src "libresoc.v:57111.3-57138.6" + process $proc$libresoc.v:57111$3482 + assign { } { } + assign { } { } + assign $0\LOGICAL_internal_op[6:0] $1\LOGICAL_internal_op[6:0] + attribute \src "libresoc.v:57112.5-57112.29" + switch \initial + attribute \src "libresoc.v:57112.9-57112.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_internal_op[6:0] \LOGICAL_dec31_LOGICAL_dec31_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_internal_op[6:0] 7'1000011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_internal_op[6:0] 7'1000011 + case + assign $1\LOGICAL_internal_op[6:0] 7'0000000 + end + sync always + update \LOGICAL_internal_op $0\LOGICAL_internal_op[6:0] + end + attribute \src "libresoc.v:57139.3-57166.6" + process $proc$libresoc.v:57139$3483 + assign { } { } + assign { } { } + assign $0\LOGICAL_in1_sel[2:0] $1\LOGICAL_in1_sel[2:0] + attribute \src "libresoc.v:57140.5-57140.29" + switch \initial + attribute \src "libresoc.v:57140.9-57140.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_in1_sel[2:0] \LOGICAL_dec31_LOGICAL_dec31_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_in1_sel[2:0] 3'100 + case + assign $1\LOGICAL_in1_sel[2:0] 3'000 + end + sync always + update \LOGICAL_in1_sel $0\LOGICAL_in1_sel[2:0] + end + attribute \src "libresoc.v:57167.3-57194.6" + process $proc$libresoc.v:57167$3484 + assign { } { } + assign { } { } + assign $0\LOGICAL_in2_sel[3:0] $1\LOGICAL_in2_sel[3:0] + attribute \src "libresoc.v:57168.5-57168.29" + switch \initial + attribute \src "libresoc.v:57168.9-57168.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_in2_sel[3:0] \LOGICAL_dec31_LOGICAL_dec31_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_in2_sel[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_in2_sel[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_in2_sel[3:0] 4'0100 + case + assign $1\LOGICAL_in2_sel[3:0] 4'0000 + end + sync always + update \LOGICAL_in2_sel $0\LOGICAL_in2_sel[3:0] + end + attribute \src "libresoc.v:57195.3-57222.6" + process $proc$libresoc.v:57195$3485 + assign { } { } + assign { } { } + assign $0\LOGICAL_cr_in[2:0] $1\LOGICAL_cr_in[2:0] + attribute \src "libresoc.v:57196.5-57196.29" + switch \initial + attribute \src "libresoc.v:57196.9-57196.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_cr_in[2:0] \LOGICAL_dec31_LOGICAL_dec31_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_cr_in[2:0] 3'000 + case + assign $1\LOGICAL_cr_in[2:0] 3'000 + end + sync always + update \LOGICAL_cr_in $0\LOGICAL_cr_in[2:0] + end + attribute \src "libresoc.v:57223.3-57250.6" + process $proc$libresoc.v:57223$3486 + assign { } { } + assign { } { } + assign $0\LOGICAL_cr_out[2:0] $1\LOGICAL_cr_out[2:0] + attribute \src "libresoc.v:57224.5-57224.29" + switch \initial + attribute \src "libresoc.v:57224.9-57224.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_cr_out[2:0] \LOGICAL_dec31_LOGICAL_dec31_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_cr_out[2:0] 3'000 + case + assign $1\LOGICAL_cr_out[2:0] 3'000 + end + sync always + update \LOGICAL_cr_out $0\LOGICAL_cr_out[2:0] + end + attribute \src "libresoc.v:57251.3-57278.6" + process $proc$libresoc.v:57251$3487 + assign { } { } + assign { } { } + assign $0\LOGICAL_ldst_len[3:0] $1\LOGICAL_ldst_len[3:0] + attribute \src "libresoc.v:57252.5-57252.29" + switch \initial + attribute \src "libresoc.v:57252.9-57252.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_ldst_len[3:0] \LOGICAL_dec31_LOGICAL_dec31_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_ldst_len[3:0] 4'0000 + case + assign $1\LOGICAL_ldst_len[3:0] 4'0000 + end + sync always + update \LOGICAL_ldst_len $0\LOGICAL_ldst_len[3:0] + end + attribute \src "libresoc.v:57279.3-57306.6" + process $proc$libresoc.v:57279$3488 + assign { } { } + assign { } { } + assign $0\LOGICAL_rc_sel[1:0] $1\LOGICAL_rc_sel[1:0] + attribute \src "libresoc.v:57280.5-57280.29" + switch \initial + attribute \src "libresoc.v:57280.9-57280.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_rc_sel[1:0] \LOGICAL_dec31_LOGICAL_dec31_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_rc_sel[1:0] 2'00 + case + assign $1\LOGICAL_rc_sel[1:0] 2'00 + end + sync always + update \LOGICAL_rc_sel $0\LOGICAL_rc_sel[1:0] + end + connect \$1 $ternary$libresoc.v:56897$3474_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \LOGICAL_SPR \opcode_in [20:11] + connect \LOGICAL_MB \opcode_in [10:6] + connect \LOGICAL_ME \opcode_in [5:1] + connect \LOGICAL_SH \opcode_in [15:11] + connect \LOGICAL_BC \opcode_in [10:6] + connect \LOGICAL_TO \opcode_in [25:21] + connect \LOGICAL_DS \opcode_in [15:2] + connect \LOGICAL_D \opcode_in [15:0] + connect \LOGICAL_BH \opcode_in [12:11] + connect \LOGICAL_BI \opcode_in [20:16] + connect \LOGICAL_BO \opcode_in [25:21] + connect \LOGICAL_FXM \opcode_in [19:12] + connect \LOGICAL_BT \opcode_in [25:21] + connect \LOGICAL_BA \opcode_in [20:16] + connect \LOGICAL_BB \opcode_in [15:11] + connect \LOGICAL_CR \opcode_in [10:1] + connect \LOGICAL_BF \opcode_in [25:23] + connect \LOGICAL_BD \opcode_in [15:2] + connect \LOGICAL_OE \opcode_in [10] + connect \LOGICAL_Rc \opcode_in [0] + connect \LOGICAL_AA \opcode_in [1] + connect \LOGICAL_LK \opcode_in [0] + connect \LOGICAL_LI \opcode_in [25:2] + connect \LOGICAL_ME32 \opcode_in [5:1] + connect \LOGICAL_MB32 \opcode_in [10:6] + connect \LOGICAL_sh { \opcode_in [1] \opcode_in [15:11] } + connect \LOGICAL_SH32 \opcode_in [15:11] + connect \LOGICAL_L \opcode_in [21] + connect \LOGICAL_UI \opcode_in [15:0] + connect \LOGICAL_SI \opcode_in [15:0] + connect \LOGICAL_RB \opcode_in [15:11] + connect \LOGICAL_RA \opcode_in [20:16] + connect \LOGICAL_RT \opcode_in [25:21] + connect \LOGICAL_RS \opcode_in [25:21] + connect \opcode_in \$1 + connect \LOGICAL_dec31_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:57640.1-58945.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec" +attribute \generator "nMigen" +module \dec$164 + attribute \src "libresoc.v:58576.3-58585.6" + wire width 3 $0\SPR_cr_in[2:0] + attribute \src "libresoc.v:58586.3-58595.6" + wire width 3 $0\SPR_cr_out[2:0] + attribute \src "libresoc.v:58556.3-58565.6" + wire width 12 $0\SPR_function_unit[11:0] + attribute \src "libresoc.v:58566.3-58575.6" + wire width 7 $0\SPR_internal_op[6:0] + attribute \src "libresoc.v:58606.3-58615.6" + wire $0\SPR_is_32b[0:0] + attribute \src "libresoc.v:58596.3-58605.6" + wire width 2 $0\SPR_rc_sel[1:0] + attribute \src "libresoc.v:57641.7-57641.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:58576.3-58585.6" + wire width 3 $1\SPR_cr_in[2:0] + attribute \src "libresoc.v:58586.3-58595.6" + wire width 3 $1\SPR_cr_out[2:0] + attribute \src "libresoc.v:58556.3-58565.6" + wire width 12 $1\SPR_function_unit[11:0] + attribute \src "libresoc.v:58566.3-58575.6" + wire width 7 $1\SPR_internal_op[6:0] + attribute \src "libresoc.v:58606.3-58615.6" + wire $1\SPR_is_32b[0:0] + attribute \src "libresoc.v:58596.3-58605.6" + wire width 2 $1\SPR_rc_sel[1:0] + attribute \src "libresoc.v:58546.17-58546.211" + wire width 32 $ternary$libresoc.v:58546$3490_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \SPR_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 12 \SPR_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 11 \SPR_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 16 \SPR_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 \SPR_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 3 \SPR_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 2 \SPR_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 15 \SPR_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \SPR_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 13 \SPR_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 10 \SPR_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 \SPR_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 \SPR_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 output 14 \SPR_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \SPR_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 24 \SPR_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \SPR_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \SPR_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \SPR_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \SPR_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \SPR_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire output 10 \SPR_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \SPR_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \SPR_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \SPR_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \SPR_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire output 9 \SPR_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \SPR_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \SPR_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 \SPR_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 10 \SPR_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \SPR_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 \SPR_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 4 \SPR_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \SPR_cr_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \SPR_dec31_SPR_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \SPR_dec31_SPR_dec31_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 \SPR_dec31_SPR_dec31_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \SPR_dec31_SPR_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \SPR_dec31_SPR_dec31_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \SPR_dec31_SPR_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \SPR_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 7 \SPR_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 6 \SPR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 8 \SPR_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 3 \SPR_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 6 \SPR_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XL_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 output 19 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 15 \XL_OC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XO_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XO_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX2_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \XX2_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XX2_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \XX2_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XX2_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_dm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX3_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX3_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX3_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XX3_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX3_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XX3_DM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XX3_SHW + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX3_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX3_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \XX3_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \XX3_XO_1 + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \X_CT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \X_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \X_DRM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_E + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_EO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_EX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \X_E_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + wire input 1 \bigendian + attribute \src "libresoc.v:57641.7-57641.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + wire width 32 input 20 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + cell $mux $ternary$libresoc.v:58546$3490 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:58546$3490_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:58547.13-58555.4" + cell \SPR_dec31 \SPR_dec31 + connect \SPR_dec31_cr_in \SPR_dec31_SPR_dec31_cr_in + connect \SPR_dec31_cr_out \SPR_dec31_SPR_dec31_cr_out + connect \SPR_dec31_function_unit \SPR_dec31_SPR_dec31_function_unit + connect \SPR_dec31_internal_op \SPR_dec31_SPR_dec31_internal_op + connect \SPR_dec31_is_32b \SPR_dec31_SPR_dec31_is_32b + connect \SPR_dec31_rc_sel \SPR_dec31_SPR_dec31_rc_sel + connect \opcode_in \SPR_dec31_opcode_in + end + attribute \src "libresoc.v:57641.7-57641.20" + process $proc$libresoc.v:57641$3497 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:58556.3-58565.6" + process $proc$libresoc.v:58556$3491 + assign { } { } + assign { } { } + assign $0\SPR_function_unit[11:0] $1\SPR_function_unit[11:0] + attribute \src "libresoc.v:58557.5-58557.29" + switch \initial + attribute \src "libresoc.v:58557.9-58557.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SPR_function_unit[11:0] \SPR_dec31_SPR_dec31_function_unit + case + assign $1\SPR_function_unit[11:0] 12'000000000000 + end + sync always + update \SPR_function_unit $0\SPR_function_unit[11:0] + end + attribute \src "libresoc.v:58566.3-58575.6" + process $proc$libresoc.v:58566$3492 + assign { } { } + assign { } { } + assign $0\SPR_internal_op[6:0] $1\SPR_internal_op[6:0] + attribute \src "libresoc.v:58567.5-58567.29" + switch \initial + attribute \src "libresoc.v:58567.9-58567.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SPR_internal_op[6:0] \SPR_dec31_SPR_dec31_internal_op + case + assign $1\SPR_internal_op[6:0] 7'0000000 + end + sync always + update \SPR_internal_op $0\SPR_internal_op[6:0] + end + attribute \src "libresoc.v:58576.3-58585.6" + process $proc$libresoc.v:58576$3493 + assign { } { } + assign { } { } + assign $0\SPR_cr_in[2:0] $1\SPR_cr_in[2:0] + attribute \src "libresoc.v:58577.5-58577.29" + switch \initial + attribute \src "libresoc.v:58577.9-58577.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SPR_cr_in[2:0] \SPR_dec31_SPR_dec31_cr_in + case + assign $1\SPR_cr_in[2:0] 3'000 + end + sync always + update \SPR_cr_in $0\SPR_cr_in[2:0] + end + attribute \src "libresoc.v:58586.3-58595.6" + process $proc$libresoc.v:58586$3494 + assign { } { } + assign { } { } + assign $0\SPR_cr_out[2:0] $1\SPR_cr_out[2:0] + attribute \src "libresoc.v:58587.5-58587.29" + switch \initial + attribute \src "libresoc.v:58587.9-58587.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SPR_cr_out[2:0] \SPR_dec31_SPR_dec31_cr_out + case + assign $1\SPR_cr_out[2:0] 3'000 + end + sync always + update \SPR_cr_out $0\SPR_cr_out[2:0] + end + attribute \src "libresoc.v:58596.3-58605.6" + process $proc$libresoc.v:58596$3495 + assign { } { } + assign { } { } + assign $0\SPR_rc_sel[1:0] $1\SPR_rc_sel[1:0] + attribute \src "libresoc.v:58597.5-58597.29" + switch \initial + attribute \src "libresoc.v:58597.9-58597.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SPR_rc_sel[1:0] \SPR_dec31_SPR_dec31_rc_sel + case + assign $1\SPR_rc_sel[1:0] 2'00 + end + sync always + update \SPR_rc_sel $0\SPR_rc_sel[1:0] + end + attribute \src "libresoc.v:58606.3-58615.6" + process $proc$libresoc.v:58606$3496 + assign { } { } + assign { } { } + assign $0\SPR_is_32b[0:0] $1\SPR_is_32b[0:0] + attribute \src "libresoc.v:58607.5-58607.29" + switch \initial + attribute \src "libresoc.v:58607.9-58607.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SPR_is_32b[0:0] \SPR_dec31_SPR_dec31_is_32b + case + assign $1\SPR_is_32b[0:0] 1'0 + end + sync always + update \SPR_is_32b $0\SPR_is_32b[0:0] + end + connect \$1 $ternary$libresoc.v:58546$3490_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \SPR_SPR \opcode_in [20:11] + connect \SPR_MB \opcode_in [10:6] + connect \SPR_ME \opcode_in [5:1] + connect \SPR_SH \opcode_in [15:11] + connect \SPR_BC \opcode_in [10:6] + connect \SPR_TO \opcode_in [25:21] + connect \SPR_DS \opcode_in [15:2] + connect \SPR_D \opcode_in [15:0] + connect \SPR_BH \opcode_in [12:11] + connect \SPR_BI \opcode_in [20:16] + connect \SPR_BO \opcode_in [25:21] + connect \SPR_FXM \opcode_in [19:12] + connect \SPR_BT \opcode_in [25:21] + connect \SPR_BA \opcode_in [20:16] + connect \SPR_BB \opcode_in [15:11] + connect \SPR_CR \opcode_in [10:1] + connect \SPR_BF \opcode_in [25:23] + connect \SPR_BD \opcode_in [15:2] + connect \SPR_OE \opcode_in [10] + connect \SPR_Rc \opcode_in [0] + connect \SPR_AA \opcode_in [1] + connect \SPR_LK \opcode_in [0] + connect \SPR_LI \opcode_in [25:2] + connect \SPR_ME32 \opcode_in [5:1] + connect \SPR_MB32 \opcode_in [10:6] + connect \SPR_sh { \opcode_in [1] \opcode_in [15:11] } + connect \SPR_SH32 \opcode_in [15:11] + connect \SPR_L \opcode_in [21] + connect \SPR_UI \opcode_in [15:0] + connect \SPR_SI \opcode_in [15:0] + connect \SPR_RB \opcode_in [15:11] + connect \SPR_RA \opcode_in [20:16] + connect \SPR_RT \opcode_in [25:21] + connect \SPR_RS \opcode_in [25:21] + connect \opcode_in \$1 + connect \SPR_dec31_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:58949.1-60444.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec" +attribute \generator "nMigen" +module \dec$171 + attribute \src "libresoc.v:60075.3-60084.6" + wire width 3 $0\DIV_cr_in[2:0] + attribute \src "libresoc.v:60085.3-60094.6" + wire width 3 $0\DIV_cr_out[2:0] + attribute \src "libresoc.v:59975.3-59984.6" + wire width 2 $0\DIV_cry_in[1:0] + attribute \src "libresoc.v:60005.3-60014.6" + wire $0\DIV_cry_out[0:0] + attribute \src "libresoc.v:60035.3-60044.6" + wire width 12 $0\DIV_function_unit[11:0] + attribute \src "libresoc.v:60055.3-60064.6" + wire width 3 $0\DIV_in1_sel[2:0] + attribute \src "libresoc.v:60065.3-60074.6" + wire width 4 $0\DIV_in2_sel[3:0] + attribute \src "libresoc.v:60045.3-60054.6" + wire width 7 $0\DIV_internal_op[6:0] + attribute \src "libresoc.v:59985.3-59994.6" + wire $0\DIV_inv_a[0:0] + attribute \src "libresoc.v:59995.3-60004.6" + wire $0\DIV_inv_out[0:0] + attribute \src "libresoc.v:60015.3-60024.6" + wire $0\DIV_is_32b[0:0] + attribute \src "libresoc.v:60095.3-60104.6" + wire width 4 $0\DIV_ldst_len[3:0] + attribute \src "libresoc.v:60105.3-60114.6" + wire width 2 $0\DIV_rc_sel[1:0] + attribute \src "libresoc.v:60025.3-60034.6" + wire $0\DIV_sgn[0:0] + attribute \src "libresoc.v:58950.7-58950.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:60075.3-60084.6" + wire width 3 $1\DIV_cr_in[2:0] + attribute \src "libresoc.v:60085.3-60094.6" + wire width 3 $1\DIV_cr_out[2:0] + attribute \src "libresoc.v:59975.3-59984.6" + wire width 2 $1\DIV_cry_in[1:0] + attribute \src "libresoc.v:60005.3-60014.6" + wire $1\DIV_cry_out[0:0] + attribute \src "libresoc.v:60035.3-60044.6" + wire width 12 $1\DIV_function_unit[11:0] + attribute \src "libresoc.v:60055.3-60064.6" + wire width 3 $1\DIV_in1_sel[2:0] + attribute \src "libresoc.v:60065.3-60074.6" + wire width 4 $1\DIV_in2_sel[3:0] + attribute \src "libresoc.v:60045.3-60054.6" + wire width 7 $1\DIV_internal_op[6:0] + attribute \src "libresoc.v:59985.3-59994.6" + wire $1\DIV_inv_a[0:0] + attribute \src "libresoc.v:59995.3-60004.6" + wire $1\DIV_inv_out[0:0] + attribute \src "libresoc.v:60015.3-60024.6" + wire $1\DIV_is_32b[0:0] + attribute \src "libresoc.v:60095.3-60104.6" + wire width 4 $1\DIV_ldst_len[3:0] + attribute \src "libresoc.v:60105.3-60114.6" + wire width 2 $1\DIV_rc_sel[1:0] + attribute \src "libresoc.v:60025.3-60034.6" + wire $1\DIV_sgn[0:0] + attribute \src "libresoc.v:59957.17-59957.211" + wire width 32 $ternary$libresoc.v:59957$3498_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \DIV_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 27 \DIV_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 26 \DIV_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 32 \DIV_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 output 25 \DIV_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 3 \DIV_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 2 \DIV_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 30 \DIV_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \DIV_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 28 \DIV_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 10 \DIV_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 \DIV_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 output 31 \DIV_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 output 29 \DIV_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \DIV_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 24 output 22 \DIV_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \DIV_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \DIV_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \DIV_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \DIV_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \DIV_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire output 24 \DIV_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 17 \DIV_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \DIV_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \DIV_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \DIV_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire output 23 \DIV_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \DIV_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 20 \DIV_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 output 18 \DIV_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 10 \DIV_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \DIV_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 output 19 \DIV_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 4 \DIV_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \DIV_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \DIV_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 14 \DIV_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \DIV_dec31_DIV_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \DIV_dec31_DIV_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \DIV_dec31_DIV_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \DIV_dec31_DIV_dec31_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 \DIV_dec31_DIV_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \DIV_dec31_DIV_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \DIV_dec31_DIV_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \DIV_dec31_DIV_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \DIV_dec31_DIV_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \DIV_dec31_DIV_dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \DIV_dec31_DIV_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \DIV_dec31_DIV_dec31_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \DIV_dec31_DIV_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \DIV_dec31_DIV_dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \DIV_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 7 \DIV_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 8 \DIV_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 9 \DIV_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 6 \DIV_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 11 \DIV_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 12 \DIV_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \DIV_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 10 \DIV_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 3 \DIV_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \DIV_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 6 output 21 \DIV_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XL_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 output 35 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 15 \XL_OC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XO_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XO_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX2_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \XX2_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XX2_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \XX2_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XX2_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_dm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX3_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX3_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX3_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XX3_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX3_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XX3_DM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XX3_SHW + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX3_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX3_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \XX3_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \XX3_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XX3_XO_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX4_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX4_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX4_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX4_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX4_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX4_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX4_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX4_CX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX4_CX_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX4_T + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \X_IH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \X_IMM8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_L1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_L2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_L3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_MO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_NB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_PRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_RIC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_RM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_RO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_R_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_SP + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + wire input 1 \bigendian + attribute \src "libresoc.v:58950.7-58950.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + wire width 32 input 36 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + cell $mux $ternary$libresoc.v:59957$3498 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:59957$3498_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:59958.13-59974.4" + cell \DIV_dec31 \DIV_dec31 + connect \DIV_dec31_cr_in \DIV_dec31_DIV_dec31_cr_in + connect \DIV_dec31_cr_out \DIV_dec31_DIV_dec31_cr_out + connect \DIV_dec31_cry_in \DIV_dec31_DIV_dec31_cry_in + connect \DIV_dec31_cry_out \DIV_dec31_DIV_dec31_cry_out + connect \DIV_dec31_function_unit \DIV_dec31_DIV_dec31_function_unit + connect \DIV_dec31_in1_sel \DIV_dec31_DIV_dec31_in1_sel + connect \DIV_dec31_in2_sel \DIV_dec31_DIV_dec31_in2_sel + connect \DIV_dec31_internal_op \DIV_dec31_DIV_dec31_internal_op + connect \DIV_dec31_inv_a \DIV_dec31_DIV_dec31_inv_a + connect \DIV_dec31_inv_out \DIV_dec31_DIV_dec31_inv_out + connect \DIV_dec31_is_32b \DIV_dec31_DIV_dec31_is_32b + connect \DIV_dec31_ldst_len \DIV_dec31_DIV_dec31_ldst_len + connect \DIV_dec31_rc_sel \DIV_dec31_DIV_dec31_rc_sel + connect \DIV_dec31_sgn \DIV_dec31_DIV_dec31_sgn + connect \opcode_in \DIV_dec31_opcode_in + end + attribute \src "libresoc.v:58950.7-58950.20" + process $proc$libresoc.v:58950$3513 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:59975.3-59984.6" + process $proc$libresoc.v:59975$3499 + assign { } { } + assign { } { } + assign $0\DIV_cry_in[1:0] $1\DIV_cry_in[1:0] + attribute \src "libresoc.v:59976.5-59976.29" + switch \initial + attribute \src "libresoc.v:59976.9-59976.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_cry_in[1:0] \DIV_dec31_DIV_dec31_cry_in + case + assign $1\DIV_cry_in[1:0] 2'00 + end + sync always + update \DIV_cry_in $0\DIV_cry_in[1:0] + end + attribute \src "libresoc.v:59985.3-59994.6" + process $proc$libresoc.v:59985$3500 + assign { } { } + assign { } { } + assign $0\DIV_inv_a[0:0] $1\DIV_inv_a[0:0] + attribute \src "libresoc.v:59986.5-59986.29" + switch \initial + attribute \src "libresoc.v:59986.9-59986.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_inv_a[0:0] \DIV_dec31_DIV_dec31_inv_a + case + assign $1\DIV_inv_a[0:0] 1'0 + end + sync always + update \DIV_inv_a $0\DIV_inv_a[0:0] + end + attribute \src "libresoc.v:59995.3-60004.6" + process $proc$libresoc.v:59995$3501 + assign { } { } + assign { } { } + assign $0\DIV_inv_out[0:0] $1\DIV_inv_out[0:0] + attribute \src "libresoc.v:59996.5-59996.29" + switch \initial + attribute \src "libresoc.v:59996.9-59996.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_inv_out[0:0] \DIV_dec31_DIV_dec31_inv_out + case + assign $1\DIV_inv_out[0:0] 1'0 + end + sync always + update \DIV_inv_out $0\DIV_inv_out[0:0] + end + attribute \src "libresoc.v:60005.3-60014.6" + process $proc$libresoc.v:60005$3502 + assign { } { } + assign { } { } + assign $0\DIV_cry_out[0:0] $1\DIV_cry_out[0:0] + attribute \src "libresoc.v:60006.5-60006.29" + switch \initial + attribute \src "libresoc.v:60006.9-60006.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_cry_out[0:0] \DIV_dec31_DIV_dec31_cry_out + case + assign $1\DIV_cry_out[0:0] 1'0 + end + sync always + update \DIV_cry_out $0\DIV_cry_out[0:0] + end + attribute \src "libresoc.v:60015.3-60024.6" + process $proc$libresoc.v:60015$3503 + assign { } { } + assign { } { } + assign $0\DIV_is_32b[0:0] $1\DIV_is_32b[0:0] + attribute \src "libresoc.v:60016.5-60016.29" + switch \initial + attribute \src "libresoc.v:60016.9-60016.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_is_32b[0:0] \DIV_dec31_DIV_dec31_is_32b + case + assign $1\DIV_is_32b[0:0] 1'0 + end + sync always + update \DIV_is_32b $0\DIV_is_32b[0:0] + end + attribute \src "libresoc.v:60025.3-60034.6" + process $proc$libresoc.v:60025$3504 + assign { } { } + assign { } { } + assign $0\DIV_sgn[0:0] $1\DIV_sgn[0:0] + attribute \src "libresoc.v:60026.5-60026.29" + switch \initial + attribute \src "libresoc.v:60026.9-60026.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_sgn[0:0] \DIV_dec31_DIV_dec31_sgn + case + assign $1\DIV_sgn[0:0] 1'0 + end + sync always + update \DIV_sgn $0\DIV_sgn[0:0] + end + attribute \src "libresoc.v:60035.3-60044.6" + process $proc$libresoc.v:60035$3505 + assign { } { } + assign { } { } + assign $0\DIV_function_unit[11:0] $1\DIV_function_unit[11:0] + attribute \src "libresoc.v:60036.5-60036.29" + switch \initial + attribute \src "libresoc.v:60036.9-60036.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_function_unit[11:0] \DIV_dec31_DIV_dec31_function_unit + case + assign $1\DIV_function_unit[11:0] 12'000000000000 + end + sync always + update \DIV_function_unit $0\DIV_function_unit[11:0] + end + attribute \src "libresoc.v:60045.3-60054.6" + process $proc$libresoc.v:60045$3506 + assign { } { } + assign { } { } + assign $0\DIV_internal_op[6:0] $1\DIV_internal_op[6:0] + attribute \src "libresoc.v:60046.5-60046.29" + switch \initial + attribute \src "libresoc.v:60046.9-60046.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_internal_op[6:0] \DIV_dec31_DIV_dec31_internal_op + case + assign $1\DIV_internal_op[6:0] 7'0000000 + end + sync always + update \DIV_internal_op $0\DIV_internal_op[6:0] + end + attribute \src "libresoc.v:60055.3-60064.6" + process $proc$libresoc.v:60055$3507 + assign { } { } + assign { } { } + assign $0\DIV_in1_sel[2:0] $1\DIV_in1_sel[2:0] + attribute \src "libresoc.v:60056.5-60056.29" + switch \initial + attribute \src "libresoc.v:60056.9-60056.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_in1_sel[2:0] \DIV_dec31_DIV_dec31_in1_sel + case + assign $1\DIV_in1_sel[2:0] 3'000 + end + sync always + update \DIV_in1_sel $0\DIV_in1_sel[2:0] + end + attribute \src "libresoc.v:60065.3-60074.6" + process $proc$libresoc.v:60065$3508 + assign { } { } + assign { } { } + assign $0\DIV_in2_sel[3:0] $1\DIV_in2_sel[3:0] + attribute \src "libresoc.v:60066.5-60066.29" + switch \initial + attribute \src "libresoc.v:60066.9-60066.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_in2_sel[3:0] \DIV_dec31_DIV_dec31_in2_sel + case + assign $1\DIV_in2_sel[3:0] 4'0000 + end + sync always + update \DIV_in2_sel $0\DIV_in2_sel[3:0] + end + attribute \src "libresoc.v:60075.3-60084.6" + process $proc$libresoc.v:60075$3509 + assign { } { } + assign { } { } + assign $0\DIV_cr_in[2:0] $1\DIV_cr_in[2:0] + attribute \src "libresoc.v:60076.5-60076.29" + switch \initial + attribute \src "libresoc.v:60076.9-60076.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_cr_in[2:0] \DIV_dec31_DIV_dec31_cr_in + case + assign $1\DIV_cr_in[2:0] 3'000 + end + sync always + update \DIV_cr_in $0\DIV_cr_in[2:0] + end + attribute \src "libresoc.v:60085.3-60094.6" + process $proc$libresoc.v:60085$3510 + assign { } { } + assign { } { } + assign $0\DIV_cr_out[2:0] $1\DIV_cr_out[2:0] + attribute \src "libresoc.v:60086.5-60086.29" + switch \initial + attribute \src "libresoc.v:60086.9-60086.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_cr_out[2:0] \DIV_dec31_DIV_dec31_cr_out + case + assign $1\DIV_cr_out[2:0] 3'000 + end + sync always + update \DIV_cr_out $0\DIV_cr_out[2:0] + end + attribute \src "libresoc.v:60095.3-60104.6" + process $proc$libresoc.v:60095$3511 + assign { } { } + assign { } { } + assign $0\DIV_ldst_len[3:0] $1\DIV_ldst_len[3:0] + attribute \src "libresoc.v:60096.5-60096.29" + switch \initial + attribute \src "libresoc.v:60096.9-60096.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_ldst_len[3:0] \DIV_dec31_DIV_dec31_ldst_len + case + assign $1\DIV_ldst_len[3:0] 4'0000 + end + sync always + update \DIV_ldst_len $0\DIV_ldst_len[3:0] + end + attribute \src "libresoc.v:60105.3-60114.6" + process $proc$libresoc.v:60105$3512 + assign { } { } + assign { } { } + assign $0\DIV_rc_sel[1:0] $1\DIV_rc_sel[1:0] + attribute \src "libresoc.v:60106.5-60106.29" + switch \initial + attribute \src "libresoc.v:60106.9-60106.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_rc_sel[1:0] \DIV_dec31_DIV_dec31_rc_sel + case + assign $1\DIV_rc_sel[1:0] 2'00 + end + sync always + update \DIV_rc_sel $0\DIV_rc_sel[1:0] + end + connect \$1 $ternary$libresoc.v:59957$3498_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \DIV_SPR \opcode_in [20:11] + connect \DIV_MB \opcode_in [10:6] + connect \DIV_ME \opcode_in [5:1] + connect \DIV_SH \opcode_in [15:11] + connect \DIV_BC \opcode_in [10:6] + connect \DIV_TO \opcode_in [25:21] + connect \DIV_DS \opcode_in [15:2] + connect \DIV_D \opcode_in [15:0] + connect \DIV_BH \opcode_in [12:11] + connect \DIV_BI \opcode_in [20:16] + connect \DIV_BO \opcode_in [25:21] + connect \DIV_FXM \opcode_in [19:12] + connect \DIV_BT \opcode_in [25:21] + connect \DIV_BA \opcode_in [20:16] + connect \DIV_BB \opcode_in [15:11] + connect \DIV_CR \opcode_in [10:1] + connect \DIV_BF \opcode_in [25:23] + connect \DIV_BD \opcode_in [15:2] + connect \DIV_OE \opcode_in [10] + connect \DIV_Rc \opcode_in [0] + connect \DIV_AA \opcode_in [1] + connect \DIV_LK \opcode_in [0] + connect \DIV_LI \opcode_in [25:2] + connect \DIV_ME32 \opcode_in [5:1] + connect \DIV_MB32 \opcode_in [10:6] + connect \DIV_sh { \opcode_in [1] \opcode_in [15:11] } + connect \DIV_SH32 \opcode_in [15:11] + connect \DIV_L \opcode_in [21] + connect \DIV_UI \opcode_in [15:0] + connect \DIV_SI \opcode_in [15:0] + connect \DIV_RB \opcode_in [15:11] + connect \DIV_RA \opcode_in [20:16] + connect \DIV_RT \opcode_in [25:21] + connect \DIV_RS \opcode_in [25:21] + connect \opcode_in \$1 + connect \DIV_dec31_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:60448.1-61839.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec" +attribute \generator "nMigen" +module \dec$180 + attribute \src "libresoc.v:61445.3-61457.6" + wire width 3 $0\MUL_cr_in[2:0] + attribute \src "libresoc.v:61458.3-61470.6" + wire width 3 $0\MUL_cr_out[2:0] + attribute \src "libresoc.v:61406.3-61418.6" + wire width 12 $0\MUL_function_unit[11:0] + attribute \src "libresoc.v:61432.3-61444.6" + wire width 4 $0\MUL_in2_sel[3:0] + attribute \src "libresoc.v:61419.3-61431.6" + wire width 7 $0\MUL_internal_op[6:0] + attribute \src "libresoc.v:61484.3-61496.6" + wire $0\MUL_is_32b[0:0] + attribute \src "libresoc.v:61471.3-61483.6" + wire width 2 $0\MUL_rc_sel[1:0] + attribute \src "libresoc.v:61497.3-61509.6" + wire $0\MUL_sgn[0:0] + attribute \src "libresoc.v:60449.7-60449.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:61445.3-61457.6" + wire width 3 $1\MUL_cr_in[2:0] + attribute \src "libresoc.v:61458.3-61470.6" + wire width 3 $1\MUL_cr_out[2:0] + attribute \src "libresoc.v:61406.3-61418.6" + wire width 12 $1\MUL_function_unit[11:0] + attribute \src "libresoc.v:61432.3-61444.6" + wire width 4 $1\MUL_in2_sel[3:0] + attribute \src "libresoc.v:61419.3-61431.6" + wire width 7 $1\MUL_internal_op[6:0] + attribute \src "libresoc.v:61484.3-61496.6" + wire $1\MUL_is_32b[0:0] + attribute \src "libresoc.v:61471.3-61483.6" + wire width 2 $1\MUL_rc_sel[1:0] + attribute \src "libresoc.v:61497.3-61509.6" + wire $1\MUL_sgn[0:0] + attribute \src "libresoc.v:61394.17-61394.211" + wire width 32 $ternary$libresoc.v:61394$3514_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \MUL_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 20 \MUL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 19 \MUL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 25 \MUL_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 output 18 \MUL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 3 \MUL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 2 \MUL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 23 \MUL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \MUL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 21 \MUL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 10 \MUL_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 \MUL_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 output 24 \MUL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 output 22 \MUL_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \MUL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 24 output 15 \MUL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \MUL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \MUL_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \MUL_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \MUL_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \MUL_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire output 17 \MUL_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \MUL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \MUL_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \MUL_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \MUL_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire output 16 \MUL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \MUL_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 13 \MUL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 output 11 \MUL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 10 \MUL_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \MUL_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 output 12 \MUL_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 4 \MUL_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \MUL_cr_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \MUL_dec31_MUL_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \MUL_dec31_MUL_dec31_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 \MUL_dec31_MUL_dec31_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \MUL_dec31_MUL_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \MUL_dec31_MUL_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \MUL_dec31_MUL_dec31_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \MUL_dec31_MUL_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \MUL_dec31_MUL_dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \MUL_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 7 \MUL_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 8 \MUL_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 6 \MUL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 9 \MUL_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 3 \MUL_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 10 \MUL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 6 output 14 \MUL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XL_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 output 28 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 15 \XL_OC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XO_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XO_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX2_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \XX2_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XX2_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \XX2_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XX2_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_dm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX3_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX3_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX3_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XX3_BF + attribute \src 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wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + wire input 1 \bigendian + attribute \src "libresoc.v:60449.7-60449.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + wire width 32 input 29 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + cell $mux $ternary$libresoc.v:61394$3514 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:61394$3514_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:61395.13-61405.4" + cell \MUL_dec31 \MUL_dec31 + connect \MUL_dec31_cr_in \MUL_dec31_MUL_dec31_cr_in + connect \MUL_dec31_cr_out \MUL_dec31_MUL_dec31_cr_out + connect \MUL_dec31_function_unit \MUL_dec31_MUL_dec31_function_unit + connect \MUL_dec31_in2_sel \MUL_dec31_MUL_dec31_in2_sel + connect \MUL_dec31_internal_op \MUL_dec31_MUL_dec31_internal_op + connect \MUL_dec31_is_32b \MUL_dec31_MUL_dec31_is_32b + connect \MUL_dec31_rc_sel \MUL_dec31_MUL_dec31_rc_sel + connect \MUL_dec31_sgn \MUL_dec31_MUL_dec31_sgn + connect \opcode_in \MUL_dec31_opcode_in + end + attribute \src "libresoc.v:60449.7-60449.20" + process $proc$libresoc.v:60449$3523 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:61406.3-61418.6" + process $proc$libresoc.v:61406$3515 + assign { } { } + assign { } { } + assign $0\MUL_function_unit[11:0] $1\MUL_function_unit[11:0] + attribute \src "libresoc.v:61407.5-61407.29" + switch \initial + attribute \src "libresoc.v:61407.9-61407.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_function_unit[11:0] \MUL_dec31_MUL_dec31_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_function_unit[11:0] 12'000100000000 + case + assign $1\MUL_function_unit[11:0] 12'000000000000 + end + sync always + update \MUL_function_unit $0\MUL_function_unit[11:0] + end + attribute \src "libresoc.v:61419.3-61431.6" + process $proc$libresoc.v:61419$3516 + assign { } { } + assign { } { } + assign $0\MUL_internal_op[6:0] $1\MUL_internal_op[6:0] + attribute \src "libresoc.v:61420.5-61420.29" + switch \initial + attribute \src "libresoc.v:61420.9-61420.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_internal_op[6:0] \MUL_dec31_MUL_dec31_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_internal_op[6:0] 7'0110010 + case + assign $1\MUL_internal_op[6:0] 7'0000000 + end + sync always + update \MUL_internal_op $0\MUL_internal_op[6:0] + end + attribute \src "libresoc.v:61432.3-61444.6" + process $proc$libresoc.v:61432$3517 + assign { } { } + assign { } { } + assign $0\MUL_in2_sel[3:0] $1\MUL_in2_sel[3:0] + attribute \src "libresoc.v:61433.5-61433.29" + switch \initial + attribute \src "libresoc.v:61433.9-61433.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_in2_sel[3:0] \MUL_dec31_MUL_dec31_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_in2_sel[3:0] 4'0011 + case + assign $1\MUL_in2_sel[3:0] 4'0000 + end + sync always + update \MUL_in2_sel $0\MUL_in2_sel[3:0] + end + attribute \src "libresoc.v:61445.3-61457.6" + process $proc$libresoc.v:61445$3518 + assign { } { } + assign { } { } + assign $0\MUL_cr_in[2:0] $1\MUL_cr_in[2:0] + attribute \src "libresoc.v:61446.5-61446.29" + switch \initial + attribute \src "libresoc.v:61446.9-61446.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_cr_in[2:0] \MUL_dec31_MUL_dec31_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_cr_in[2:0] 3'000 + case + assign $1\MUL_cr_in[2:0] 3'000 + end + sync always + update \MUL_cr_in $0\MUL_cr_in[2:0] + end + attribute \src "libresoc.v:61458.3-61470.6" + process $proc$libresoc.v:61458$3519 + assign { } { } + assign { } { } + assign $0\MUL_cr_out[2:0] $1\MUL_cr_out[2:0] + attribute \src "libresoc.v:61459.5-61459.29" + switch \initial + attribute \src "libresoc.v:61459.9-61459.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_cr_out[2:0] \MUL_dec31_MUL_dec31_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_cr_out[2:0] 3'001 + case + assign $1\MUL_cr_out[2:0] 3'000 + end + sync always + update \MUL_cr_out $0\MUL_cr_out[2:0] + end + attribute \src "libresoc.v:61471.3-61483.6" + process $proc$libresoc.v:61471$3520 + assign { } { } + assign { } { } + assign $0\MUL_rc_sel[1:0] $1\MUL_rc_sel[1:0] + attribute \src "libresoc.v:61472.5-61472.29" + switch \initial + attribute \src "libresoc.v:61472.9-61472.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_rc_sel[1:0] \MUL_dec31_MUL_dec31_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_rc_sel[1:0] 2'00 + case + assign $1\MUL_rc_sel[1:0] 2'00 + end + sync always + update \MUL_rc_sel $0\MUL_rc_sel[1:0] + end + attribute \src "libresoc.v:61484.3-61496.6" + process $proc$libresoc.v:61484$3521 + assign { } { } + assign { } { } + assign $0\MUL_is_32b[0:0] $1\MUL_is_32b[0:0] + attribute \src "libresoc.v:61485.5-61485.29" + switch \initial + attribute \src "libresoc.v:61485.9-61485.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_is_32b[0:0] \MUL_dec31_MUL_dec31_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_is_32b[0:0] 1'0 + case + assign $1\MUL_is_32b[0:0] 1'0 + end + sync always + update \MUL_is_32b $0\MUL_is_32b[0:0] + end + attribute \src "libresoc.v:61497.3-61509.6" + process $proc$libresoc.v:61497$3522 + assign { } { } + assign { } { } + assign $0\MUL_sgn[0:0] $1\MUL_sgn[0:0] + attribute \src "libresoc.v:61498.5-61498.29" + switch \initial + attribute \src "libresoc.v:61498.9-61498.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_sgn[0:0] \MUL_dec31_MUL_dec31_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_sgn[0:0] 1'1 + case + assign $1\MUL_sgn[0:0] 1'0 + end + sync always + update \MUL_sgn $0\MUL_sgn[0:0] + end + connect \$1 $ternary$libresoc.v:61394$3514_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \MUL_SPR \opcode_in [20:11] + connect \MUL_MB \opcode_in [10:6] + connect \MUL_ME \opcode_in [5:1] + connect \MUL_SH \opcode_in [15:11] + connect \MUL_BC \opcode_in [10:6] + connect \MUL_TO \opcode_in [25:21] + connect \MUL_DS \opcode_in [15:2] + connect \MUL_D \opcode_in [15:0] + connect \MUL_BH \opcode_in [12:11] + connect \MUL_BI \opcode_in [20:16] + connect \MUL_BO \opcode_in [25:21] + connect \MUL_FXM \opcode_in [19:12] + connect \MUL_BT \opcode_in [25:21] + connect \MUL_BA \opcode_in [20:16] + connect \MUL_BB \opcode_in [15:11] + connect \MUL_CR \opcode_in [10:1] + connect \MUL_BF \opcode_in [25:23] + connect \MUL_BD \opcode_in [15:2] + connect \MUL_OE \opcode_in [10] + connect \MUL_Rc \opcode_in [0] + connect \MUL_AA \opcode_in [1] + connect \MUL_LK \opcode_in [0] + connect \MUL_LI \opcode_in [25:2] + connect \MUL_ME32 \opcode_in [5:1] + connect \MUL_MB32 \opcode_in [10:6] + connect \MUL_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MUL_SH32 \opcode_in [15:11] + connect \MUL_L \opcode_in [21] + connect \MUL_UI \opcode_in [15:0] + connect \MUL_SI \opcode_in [15:0] + connect \MUL_RB \opcode_in [15:11] + connect \MUL_RA \opcode_in [20:16] + connect \MUL_RT \opcode_in [25:21] + connect \MUL_RS \opcode_in [25:21] + connect \opcode_in \$1 + connect \MUL_dec31_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:61843.1-63561.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec" +attribute \generator "nMigen" +module \dec$188 + attribute \src "libresoc.v:63143.3-63164.6" + wire width 3 $0\SHIFT_ROT_cr_in[2:0] + attribute \src "libresoc.v:63165.3-63186.6" + wire width 3 $0\SHIFT_ROT_cr_out[2:0] + attribute \src "libresoc.v:63209.3-63230.6" + wire width 2 $0\SHIFT_ROT_cry_in[1:0] + attribute \src "libresoc.v:63011.3-63032.6" + wire $0\SHIFT_ROT_cry_out[0:0] + attribute \src "libresoc.v:63077.3-63098.6" + wire width 12 $0\SHIFT_ROT_function_unit[11:0] + attribute \src "libresoc.v:63121.3-63142.6" + wire width 4 $0\SHIFT_ROT_in2_sel[3:0] + attribute \src "libresoc.v:63099.3-63120.6" + wire width 7 $0\SHIFT_ROT_internal_op[6:0] + attribute \src "libresoc.v:62989.3-63010.6" + wire $0\SHIFT_ROT_inv_a[0:0] + attribute \src "libresoc.v:63033.3-63054.6" + wire $0\SHIFT_ROT_is_32b[0:0] + attribute \src "libresoc.v:63187.3-63208.6" + wire width 2 $0\SHIFT_ROT_rc_sel[1:0] + attribute \src "libresoc.v:63055.3-63076.6" + wire $0\SHIFT_ROT_sgn[0:0] + attribute \src "libresoc.v:61844.7-61844.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:63143.3-63164.6" + wire width 3 $1\SHIFT_ROT_cr_in[2:0] + attribute \src "libresoc.v:63165.3-63186.6" + wire width 3 $1\SHIFT_ROT_cr_out[2:0] + attribute \src "libresoc.v:63209.3-63230.6" + wire width 2 $1\SHIFT_ROT_cry_in[1:0] + attribute \src "libresoc.v:63011.3-63032.6" + wire $1\SHIFT_ROT_cry_out[0:0] + attribute \src "libresoc.v:63077.3-63098.6" + wire width 12 $1\SHIFT_ROT_function_unit[11:0] + attribute \src "libresoc.v:63121.3-63142.6" + wire width 4 $1\SHIFT_ROT_in2_sel[3:0] + attribute \src "libresoc.v:63099.3-63120.6" + wire width 7 $1\SHIFT_ROT_internal_op[6:0] + attribute \src "libresoc.v:62989.3-63010.6" + wire $1\SHIFT_ROT_inv_a[0:0] + attribute \src "libresoc.v:63033.3-63054.6" + wire $1\SHIFT_ROT_is_32b[0:0] + attribute \src "libresoc.v:63187.3-63208.6" + wire width 2 $1\SHIFT_ROT_rc_sel[1:0] + attribute \src "libresoc.v:63055.3-63076.6" + wire $1\SHIFT_ROT_sgn[0:0] + attribute \src "libresoc.v:62960.17-62960.211" + wire width 32 $ternary$libresoc.v:62960$3524_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \SHIFT_ROT_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 23 \SHIFT_ROT_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 22 \SHIFT_ROT_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 28 \SHIFT_ROT_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 output 21 \SHIFT_ROT_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 3 \SHIFT_ROT_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 2 \SHIFT_ROT_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 26 \SHIFT_ROT_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \SHIFT_ROT_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 24 \SHIFT_ROT_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 10 \SHIFT_ROT_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 \SHIFT_ROT_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 output 27 \SHIFT_ROT_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 output 25 \SHIFT_ROT_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \SHIFT_ROT_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 24 output 18 \SHIFT_ROT_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \SHIFT_ROT_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \SHIFT_ROT_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \SHIFT_ROT_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \SHIFT_ROT_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \SHIFT_ROT_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire output 20 \SHIFT_ROT_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \SHIFT_ROT_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \SHIFT_ROT_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \SHIFT_ROT_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \SHIFT_ROT_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire output 19 \SHIFT_ROT_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \SHIFT_ROT_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 16 \SHIFT_ROT_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 output 14 \SHIFT_ROT_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 10 \SHIFT_ROT_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \SHIFT_ROT_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 output 15 \SHIFT_ROT_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 4 \SHIFT_ROT_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \SHIFT_ROT_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 10 \SHIFT_ROT_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 11 \SHIFT_ROT_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \SHIFT_ROT_dec30_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \SHIFT_ROT_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 7 \SHIFT_ROT_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 8 \SHIFT_ROT_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 6 \SHIFT_ROT_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 9 \SHIFT_ROT_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 12 \SHIFT_ROT_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 3 \SHIFT_ROT_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 13 \SHIFT_ROT_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 6 output 17 \SHIFT_ROT_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XFL_Rc + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + wire input 1 \bigendian + attribute \src "libresoc.v:61844.7-61844.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + wire width 32 input 32 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + cell $mux $ternary$libresoc.v:62960$3524 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:62960$3524_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:62961.19-62974.4" + cell \SHIFT_ROT_dec30 \SHIFT_ROT_dec30 + connect \SHIFT_ROT_dec30_cr_in \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in + connect \SHIFT_ROT_dec30_cr_out \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out + connect \SHIFT_ROT_dec30_cry_in \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in + connect \SHIFT_ROT_dec30_cry_out \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out + connect \SHIFT_ROT_dec30_function_unit \SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit + connect \SHIFT_ROT_dec30_in2_sel \SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel + connect \SHIFT_ROT_dec30_internal_op \SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op + connect \SHIFT_ROT_dec30_inv_a \SHIFT_ROT_dec30_SHIFT_ROT_dec30_inv_a + connect \SHIFT_ROT_dec30_is_32b \SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b + connect \SHIFT_ROT_dec30_rc_sel \SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel + connect \SHIFT_ROT_dec30_sgn \SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn + connect \opcode_in \SHIFT_ROT_dec30_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:62975.19-62988.4" + cell \SHIFT_ROT_dec31 \SHIFT_ROT_dec31 + connect \SHIFT_ROT_dec31_cr_in \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in + connect \SHIFT_ROT_dec31_cr_out \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out + connect \SHIFT_ROT_dec31_cry_in \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in + connect \SHIFT_ROT_dec31_cry_out \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out + connect \SHIFT_ROT_dec31_function_unit \SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit + connect \SHIFT_ROT_dec31_in2_sel \SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel + connect \SHIFT_ROT_dec31_internal_op \SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op + connect \SHIFT_ROT_dec31_inv_a \SHIFT_ROT_dec31_SHIFT_ROT_dec31_inv_a + connect \SHIFT_ROT_dec31_is_32b \SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b + connect \SHIFT_ROT_dec31_rc_sel \SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel + connect \SHIFT_ROT_dec31_sgn \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn + connect \opcode_in \SHIFT_ROT_dec31_opcode_in + end + attribute \src "libresoc.v:61844.7-61844.20" + process $proc$libresoc.v:61844$3536 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:62989.3-63010.6" + process $proc$libresoc.v:62989$3525 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_inv_a[0:0] $1\SHIFT_ROT_inv_a[0:0] + attribute \src "libresoc.v:62990.5-62990.29" + switch \initial + attribute \src "libresoc.v:62990.9-62990.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_inv_a[0:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_inv_a[0:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_inv_a[0:0] 1'0 + case + assign $1\SHIFT_ROT_inv_a[0:0] 1'0 + end + sync always + update \SHIFT_ROT_inv_a $0\SHIFT_ROT_inv_a[0:0] + end + attribute \src "libresoc.v:63011.3-63032.6" + process $proc$libresoc.v:63011$3526 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_cry_out[0:0] $1\SHIFT_ROT_cry_out[0:0] + attribute \src "libresoc.v:63012.5-63012.29" + switch \initial + attribute \src "libresoc.v:63012.9-63012.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_cry_out[0:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_cry_out[0:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_cry_out[0:0] 1'0 + case + assign $1\SHIFT_ROT_cry_out[0:0] 1'0 + end + sync always + update \SHIFT_ROT_cry_out $0\SHIFT_ROT_cry_out[0:0] + end + attribute \src "libresoc.v:63033.3-63054.6" + process $proc$libresoc.v:63033$3527 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_is_32b[0:0] $1\SHIFT_ROT_is_32b[0:0] + attribute \src "libresoc.v:63034.5-63034.29" + switch \initial + attribute \src "libresoc.v:63034.9-63034.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_is_32b[0:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_is_32b[0:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_is_32b[0:0] 1'1 + case + assign $1\SHIFT_ROT_is_32b[0:0] 1'0 + end + sync always + update \SHIFT_ROT_is_32b $0\SHIFT_ROT_is_32b[0:0] + end + attribute \src "libresoc.v:63055.3-63076.6" + process $proc$libresoc.v:63055$3528 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_sgn[0:0] $1\SHIFT_ROT_sgn[0:0] + attribute \src "libresoc.v:63056.5-63056.29" + switch \initial + attribute \src "libresoc.v:63056.9-63056.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_sgn[0:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_sgn[0:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_sgn[0:0] 1'0 + case + assign $1\SHIFT_ROT_sgn[0:0] 1'0 + end + sync always + update \SHIFT_ROT_sgn $0\SHIFT_ROT_sgn[0:0] + end + attribute \src "libresoc.v:63077.3-63098.6" + process $proc$libresoc.v:63077$3529 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_function_unit[11:0] $1\SHIFT_ROT_function_unit[11:0] + attribute \src "libresoc.v:63078.5-63078.29" + switch \initial + attribute \src "libresoc.v:63078.9-63078.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_function_unit[11:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_function_unit[11:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_function_unit[11:0] 12'000000001000 + case + assign $1\SHIFT_ROT_function_unit[11:0] 12'000000000000 + end + sync always + update \SHIFT_ROT_function_unit $0\SHIFT_ROT_function_unit[11:0] + end + attribute \src "libresoc.v:63099.3-63120.6" + process $proc$libresoc.v:63099$3530 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_internal_op[6:0] $1\SHIFT_ROT_internal_op[6:0] + attribute \src "libresoc.v:63100.5-63100.29" + switch \initial + attribute \src "libresoc.v:63100.9-63100.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_internal_op[6:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_internal_op[6:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_internal_op[6:0] 7'0111000 + case + assign $1\SHIFT_ROT_internal_op[6:0] 7'0000000 + end + sync always + update \SHIFT_ROT_internal_op $0\SHIFT_ROT_internal_op[6:0] + end + attribute \src "libresoc.v:63121.3-63142.6" + process $proc$libresoc.v:63121$3531 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_in2_sel[3:0] $1\SHIFT_ROT_in2_sel[3:0] + attribute \src "libresoc.v:63122.5-63122.29" + switch \initial + attribute \src "libresoc.v:63122.9-63122.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_in2_sel[3:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_in2_sel[3:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_in2_sel[3:0] 4'1011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_in2_sel[3:0] 4'1011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_in2_sel[3:0] 4'0001 + case + assign $1\SHIFT_ROT_in2_sel[3:0] 4'0000 + end + sync always + update \SHIFT_ROT_in2_sel $0\SHIFT_ROT_in2_sel[3:0] + end + attribute \src "libresoc.v:63143.3-63164.6" + process $proc$libresoc.v:63143$3532 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_cr_in[2:0] $1\SHIFT_ROT_cr_in[2:0] + attribute \src "libresoc.v:63144.5-63144.29" + switch \initial + attribute \src "libresoc.v:63144.9-63144.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_cr_in[2:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_cr_in[2:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_cr_in[2:0] 3'000 + case + assign $1\SHIFT_ROT_cr_in[2:0] 3'000 + end + sync always + update \SHIFT_ROT_cr_in $0\SHIFT_ROT_cr_in[2:0] + end + attribute \src "libresoc.v:63165.3-63186.6" + process $proc$libresoc.v:63165$3533 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_cr_out[2:0] $1\SHIFT_ROT_cr_out[2:0] + attribute \src "libresoc.v:63166.5-63166.29" + switch \initial + attribute \src "libresoc.v:63166.9-63166.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_cr_out[2:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_cr_out[2:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_cr_out[2:0] 3'001 + case + assign $1\SHIFT_ROT_cr_out[2:0] 3'000 + end + sync always + update \SHIFT_ROT_cr_out $0\SHIFT_ROT_cr_out[2:0] + end + attribute \src "libresoc.v:63187.3-63208.6" + process $proc$libresoc.v:63187$3534 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_rc_sel[1:0] $1\SHIFT_ROT_rc_sel[1:0] + attribute \src "libresoc.v:63188.5-63188.29" + switch \initial + attribute \src "libresoc.v:63188.9-63188.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_rc_sel[1:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_rc_sel[1:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_rc_sel[1:0] 2'10 + case + assign $1\SHIFT_ROT_rc_sel[1:0] 2'00 + end + sync always + update \SHIFT_ROT_rc_sel $0\SHIFT_ROT_rc_sel[1:0] + end + attribute \src "libresoc.v:63209.3-63230.6" + process $proc$libresoc.v:63209$3535 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_cry_in[1:0] $1\SHIFT_ROT_cry_in[1:0] + attribute \src "libresoc.v:63210.5-63210.29" + switch \initial + attribute \src "libresoc.v:63210.9-63210.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_cry_in[1:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_cry_in[1:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_cry_in[1:0] 2'00 + case + assign $1\SHIFT_ROT_cry_in[1:0] 2'00 + end + sync always + update \SHIFT_ROT_cry_in $0\SHIFT_ROT_cry_in[1:0] + end + connect \$1 $ternary$libresoc.v:62960$3524_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \SHIFT_ROT_SPR \opcode_in [20:11] + connect \SHIFT_ROT_MB \opcode_in [10:6] + connect \SHIFT_ROT_ME \opcode_in [5:1] + connect \SHIFT_ROT_SH \opcode_in [15:11] + connect \SHIFT_ROT_BC \opcode_in [10:6] + connect \SHIFT_ROT_TO \opcode_in [25:21] + connect \SHIFT_ROT_DS \opcode_in [15:2] + connect \SHIFT_ROT_D \opcode_in [15:0] + connect \SHIFT_ROT_BH \opcode_in [12:11] + connect \SHIFT_ROT_BI \opcode_in [20:16] + connect \SHIFT_ROT_BO \opcode_in [25:21] + connect \SHIFT_ROT_FXM \opcode_in [19:12] + connect \SHIFT_ROT_BT \opcode_in [25:21] + connect \SHIFT_ROT_BA \opcode_in [20:16] + connect \SHIFT_ROT_BB \opcode_in [15:11] + connect \SHIFT_ROT_CR \opcode_in [10:1] + connect \SHIFT_ROT_BF \opcode_in [25:23] + connect \SHIFT_ROT_BD \opcode_in [15:2] + connect \SHIFT_ROT_OE \opcode_in [10] + connect \SHIFT_ROT_Rc \opcode_in [0] + connect \SHIFT_ROT_AA \opcode_in [1] + connect \SHIFT_ROT_LK \opcode_in [0] + connect \SHIFT_ROT_LI \opcode_in [25:2] + connect \SHIFT_ROT_ME32 \opcode_in [5:1] + connect \SHIFT_ROT_MB32 \opcode_in [10:6] + connect \SHIFT_ROT_sh { \opcode_in [1] \opcode_in [15:11] } + connect \SHIFT_ROT_SH32 \opcode_in [15:11] + connect \SHIFT_ROT_L \opcode_in [21] + connect \SHIFT_ROT_UI \opcode_in [15:0] + connect \SHIFT_ROT_SI \opcode_in [15:0] + connect \SHIFT_ROT_RB \opcode_in [15:11] + connect \SHIFT_ROT_RA \opcode_in [20:16] + connect \SHIFT_ROT_RT \opcode_in [25:21] + connect \SHIFT_ROT_RS \opcode_in [25:21] + connect \opcode_in \$1 + connect \SHIFT_ROT_dec31_opcode_in \opcode_in + connect \SHIFT_ROT_dec30_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:63565.1-66034.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec" +attribute \generator "nMigen" +module \dec$196 + attribute \src "libresoc.v:65123.3-65180.6" + wire $0\LDST_br[0:0] + attribute \src "libresoc.v:65587.3-65644.6" + wire width 3 $0\LDST_cr_in[2:0] + attribute \src "libresoc.v:65645.3-65702.6" + wire width 3 $0\LDST_cr_out[2:0] + attribute \src "libresoc.v:65355.3-65412.6" + wire width 12 $0\LDST_function_unit[11:0] + attribute \src "libresoc.v:65471.3-65528.6" + wire width 3 $0\LDST_in1_sel[2:0] + attribute \src "libresoc.v:65529.3-65586.6" + wire width 4 $0\LDST_in2_sel[3:0] + attribute \src "libresoc.v:65413.3-65470.6" + wire width 7 $0\LDST_internal_op[6:0] + attribute \src "libresoc.v:65239.3-65296.6" + wire $0\LDST_is_32b[0:0] + attribute \src "libresoc.v:64949.3-65006.6" + wire width 4 $0\LDST_ldst_len[3:0] + attribute \src "libresoc.v:65065.3-65122.6" + wire width 2 $0\LDST_rc_sel[1:0] + attribute \src "libresoc.v:65297.3-65354.6" + wire $0\LDST_sgn[0:0] + attribute \src "libresoc.v:65181.3-65238.6" + wire $0\LDST_sgn_ext[0:0] + attribute \src "libresoc.v:65007.3-65064.6" + wire width 2 $0\LDST_upd[1:0] + attribute \src "libresoc.v:63566.7-63566.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:65123.3-65180.6" + wire $1\LDST_br[0:0] + attribute \src "libresoc.v:65587.3-65644.6" + wire width 3 $1\LDST_cr_in[2:0] + attribute \src "libresoc.v:65645.3-65702.6" + wire width 3 $1\LDST_cr_out[2:0] + attribute \src "libresoc.v:65355.3-65412.6" + wire width 12 $1\LDST_function_unit[11:0] + attribute \src "libresoc.v:65471.3-65528.6" + wire width 3 $1\LDST_in1_sel[2:0] + attribute \src "libresoc.v:65529.3-65586.6" + wire width 4 $1\LDST_in2_sel[3:0] + attribute \src "libresoc.v:65413.3-65470.6" + wire width 7 $1\LDST_internal_op[6:0] + attribute \src "libresoc.v:65239.3-65296.6" + wire $1\LDST_is_32b[0:0] + attribute \src "libresoc.v:64949.3-65006.6" + wire width 4 $1\LDST_ldst_len[3:0] + attribute \src "libresoc.v:65065.3-65122.6" + wire width 2 $1\LDST_rc_sel[1:0] + attribute \src "libresoc.v:65297.3-65354.6" + wire $1\LDST_sgn[0:0] + attribute \src "libresoc.v:65181.3-65238.6" + wire $1\LDST_sgn_ext[0:0] + attribute \src "libresoc.v:65007.3-65064.6" + wire width 2 $1\LDST_upd[1:0] + attribute \src "libresoc.v:64900.17-64900.211" + wire width 32 $ternary$libresoc.v:64900$3537_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \LDST_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 26 \LDST_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 25 \LDST_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 31 \LDST_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 output 24 \LDST_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 3 \LDST_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 2 \LDST_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 29 \LDST_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \LDST_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 27 \LDST_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 10 \LDST_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 \LDST_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 output 30 \LDST_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 output 28 \LDST_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \LDST_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 24 output 21 \LDST_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \LDST_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \LDST_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \LDST_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \LDST_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \LDST_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire output 23 \LDST_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 16 \LDST_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \LDST_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \LDST_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \LDST_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire output 22 \LDST_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \LDST_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 19 \LDST_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 output 17 \LDST_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 10 \LDST_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \LDST_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 output 18 \LDST_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 13 \LDST_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 4 \LDST_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \LDST_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \LDST_dec31_LDST_dec31_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \LDST_dec31_LDST_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \LDST_dec31_LDST_dec31_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 \LDST_dec31_LDST_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \LDST_dec31_LDST_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \LDST_dec31_LDST_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \LDST_dec31_LDST_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \LDST_dec31_LDST_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + 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attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 6 \LDST_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 11 \LDST_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 10 \LDST_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 3 \LDST_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 12 \LDST_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 14 \LDST_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 6 output 20 \LDST_sh + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 15 \LDST_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XL_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 output 34 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 15 \XL_OC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XO_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XO_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX2_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \XX2_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XX2_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \XX2_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XX2_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_dm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX3_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX3_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX3_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XX3_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX3_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XX3_DM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XX3_SHW + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX3_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX3_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \XX3_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \XX3_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XX3_XO_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX4_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX4_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX4_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX4_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX4_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX4_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX4_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX4_CX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX4_CX_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX4_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX4_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX4_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XX4_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 output 32 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 output 33 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \X_CT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \X_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \X_DRM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_E + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_EO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_EX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \X_E_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \X_IH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \X_IMM8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_L1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_L2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_L3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_MO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_NB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_PRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_RIC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_RM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_RO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_R_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_SP + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + wire input 1 \bigendian + attribute \src "libresoc.v:63566.7-63566.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + wire width 32 input 35 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + cell $mux $ternary$libresoc.v:64900$3537 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:64900$3537_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:64901.14-64916.4" + cell \LDST_dec31 \LDST_dec31 + connect \LDST_dec31_br \LDST_dec31_LDST_dec31_br + connect \LDST_dec31_cr_in \LDST_dec31_LDST_dec31_cr_in + connect \LDST_dec31_cr_out \LDST_dec31_LDST_dec31_cr_out + connect \LDST_dec31_function_unit \LDST_dec31_LDST_dec31_function_unit + connect \LDST_dec31_in1_sel \LDST_dec31_LDST_dec31_in1_sel + connect \LDST_dec31_in2_sel \LDST_dec31_LDST_dec31_in2_sel + connect \LDST_dec31_internal_op \LDST_dec31_LDST_dec31_internal_op + connect \LDST_dec31_is_32b \LDST_dec31_LDST_dec31_is_32b + connect \LDST_dec31_ldst_len \LDST_dec31_LDST_dec31_ldst_len + connect \LDST_dec31_rc_sel \LDST_dec31_LDST_dec31_rc_sel + connect \LDST_dec31_sgn \LDST_dec31_LDST_dec31_sgn + connect \LDST_dec31_sgn_ext \LDST_dec31_LDST_dec31_sgn_ext + connect \LDST_dec31_upd \LDST_dec31_LDST_dec31_upd + connect \opcode_in \LDST_dec31_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:64917.14-64932.4" + cell \LDST_dec58 \LDST_dec58 + connect \LDST_dec58_br \LDST_dec58_LDST_dec58_br + connect \LDST_dec58_cr_in \LDST_dec58_LDST_dec58_cr_in + connect \LDST_dec58_cr_out \LDST_dec58_LDST_dec58_cr_out + connect \LDST_dec58_function_unit \LDST_dec58_LDST_dec58_function_unit + connect \LDST_dec58_in1_sel \LDST_dec58_LDST_dec58_in1_sel + connect \LDST_dec58_in2_sel \LDST_dec58_LDST_dec58_in2_sel + connect \LDST_dec58_internal_op \LDST_dec58_LDST_dec58_internal_op + connect \LDST_dec58_is_32b \LDST_dec58_LDST_dec58_is_32b + connect \LDST_dec58_ldst_len \LDST_dec58_LDST_dec58_ldst_len + connect \LDST_dec58_rc_sel \LDST_dec58_LDST_dec58_rc_sel + connect \LDST_dec58_sgn \LDST_dec58_LDST_dec58_sgn + connect \LDST_dec58_sgn_ext \LDST_dec58_LDST_dec58_sgn_ext + connect \LDST_dec58_upd \LDST_dec58_LDST_dec58_upd + connect \opcode_in \LDST_dec58_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:64933.14-64948.4" + cell \LDST_dec62 \LDST_dec62 + connect \LDST_dec62_br \LDST_dec62_LDST_dec62_br + connect \LDST_dec62_cr_in \LDST_dec62_LDST_dec62_cr_in + connect \LDST_dec62_cr_out \LDST_dec62_LDST_dec62_cr_out + connect \LDST_dec62_function_unit \LDST_dec62_LDST_dec62_function_unit + connect \LDST_dec62_in1_sel \LDST_dec62_LDST_dec62_in1_sel + connect \LDST_dec62_in2_sel \LDST_dec62_LDST_dec62_in2_sel + connect \LDST_dec62_internal_op \LDST_dec62_LDST_dec62_internal_op + connect \LDST_dec62_is_32b \LDST_dec62_LDST_dec62_is_32b + connect \LDST_dec62_ldst_len \LDST_dec62_LDST_dec62_ldst_len + connect \LDST_dec62_rc_sel \LDST_dec62_LDST_dec62_rc_sel + connect \LDST_dec62_sgn \LDST_dec62_LDST_dec62_sgn + connect \LDST_dec62_sgn_ext \LDST_dec62_LDST_dec62_sgn_ext + connect \LDST_dec62_upd \LDST_dec62_LDST_dec62_upd + connect \opcode_in \LDST_dec62_opcode_in + end + attribute \src "libresoc.v:63566.7-63566.20" + process $proc$libresoc.v:63566$3551 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:64949.3-65006.6" + process $proc$libresoc.v:64949$3538 + assign { } { } + assign { } { } + assign $0\LDST_ldst_len[3:0] $1\LDST_ldst_len[3:0] + attribute \src "libresoc.v:64950.5-64950.29" + switch \initial + attribute \src "libresoc.v:64950.9-64950.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_ldst_len[3:0] \LDST_dec31_LDST_dec31_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_ldst_len[3:0] \LDST_dec58_LDST_dec58_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_ldst_len[3:0] \LDST_dec62_LDST_dec62_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0100 + case + assign $1\LDST_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_ldst_len $0\LDST_ldst_len[3:0] + end + attribute \src "libresoc.v:65007.3-65064.6" + process $proc$libresoc.v:65007$3539 + assign { } { } + assign { } { } + assign $0\LDST_upd[1:0] $1\LDST_upd[1:0] + attribute \src "libresoc.v:65008.5-65008.29" + switch \initial + attribute \src "libresoc.v:65008.9-65008.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_upd[1:0] \LDST_dec31_LDST_dec31_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_upd[1:0] \LDST_dec58_LDST_dec58_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_upd[1:0] \LDST_dec62_LDST_dec62_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_upd[1:0] 2'01 + case + assign $1\LDST_upd[1:0] 2'00 + end + sync always + update \LDST_upd $0\LDST_upd[1:0] + end + attribute \src "libresoc.v:65065.3-65122.6" + process $proc$libresoc.v:65065$3540 + assign { } { } + assign { } { } + assign $0\LDST_rc_sel[1:0] $1\LDST_rc_sel[1:0] + attribute \src "libresoc.v:65066.5-65066.29" + switch \initial + attribute \src "libresoc.v:65066.9-65066.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_rc_sel[1:0] \LDST_dec31_LDST_dec31_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_rc_sel[1:0] \LDST_dec58_LDST_dec58_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_rc_sel[1:0] \LDST_dec62_LDST_dec62_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + case + assign $1\LDST_rc_sel[1:0] 2'00 + end + sync always + update \LDST_rc_sel $0\LDST_rc_sel[1:0] + end + attribute \src "libresoc.v:65123.3-65180.6" + process $proc$libresoc.v:65123$3541 + assign { } { } + assign { } { } + assign $0\LDST_br[0:0] $1\LDST_br[0:0] + attribute \src "libresoc.v:65124.5-65124.29" + switch \initial + attribute \src "libresoc.v:65124.9-65124.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_br[0:0] \LDST_dec31_LDST_dec31_br + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_br[0:0] \LDST_dec58_LDST_dec58_br + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_br[0:0] \LDST_dec62_LDST_dec62_br + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + case + assign $1\LDST_br[0:0] 1'0 + end + sync always + update \LDST_br $0\LDST_br[0:0] + end + attribute \src "libresoc.v:65181.3-65238.6" + process $proc$libresoc.v:65181$3542 + assign { } { } + assign { } { } + assign $0\LDST_sgn_ext[0:0] $1\LDST_sgn_ext[0:0] + attribute \src "libresoc.v:65182.5-65182.29" + switch \initial + attribute \src "libresoc.v:65182.9-65182.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_sgn_ext[0:0] \LDST_dec31_LDST_dec31_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_sgn_ext[0:0] \LDST_dec58_LDST_dec58_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_sgn_ext[0:0] \LDST_dec62_LDST_dec62_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + case + assign $1\LDST_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_sgn_ext $0\LDST_sgn_ext[0:0] + end + attribute \src "libresoc.v:65239.3-65296.6" + process $proc$libresoc.v:65239$3543 + assign { } { } + assign { } { } + assign $0\LDST_is_32b[0:0] $1\LDST_is_32b[0:0] + attribute \src "libresoc.v:65240.5-65240.29" + switch \initial + attribute \src "libresoc.v:65240.9-65240.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_is_32b[0:0] \LDST_dec31_LDST_dec31_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_is_32b[0:0] \LDST_dec58_LDST_dec58_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_is_32b[0:0] \LDST_dec62_LDST_dec62_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + case + assign $1\LDST_is_32b[0:0] 1'0 + end + sync always + update \LDST_is_32b $0\LDST_is_32b[0:0] + end + attribute \src "libresoc.v:65297.3-65354.6" + process $proc$libresoc.v:65297$3544 + assign { } { } + assign { } { } + assign $0\LDST_sgn[0:0] $1\LDST_sgn[0:0] + attribute \src "libresoc.v:65298.5-65298.29" + switch \initial + attribute \src "libresoc.v:65298.9-65298.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_sgn[0:0] \LDST_dec31_LDST_dec31_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_sgn[0:0] \LDST_dec58_LDST_dec58_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_sgn[0:0] \LDST_dec62_LDST_dec62_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + case + assign $1\LDST_sgn[0:0] 1'0 + end + sync always + update \LDST_sgn $0\LDST_sgn[0:0] + end + attribute \src "libresoc.v:65355.3-65412.6" + process $proc$libresoc.v:65355$3545 + assign { } { } + assign { } { } + assign $0\LDST_function_unit[11:0] $1\LDST_function_unit[11:0] + attribute \src "libresoc.v:65356.5-65356.29" + switch \initial + attribute \src "libresoc.v:65356.9-65356.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_function_unit[11:0] \LDST_dec31_LDST_dec31_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_function_unit[11:0] \LDST_dec58_LDST_dec58_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_function_unit[11:0] \LDST_dec62_LDST_dec62_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + case + assign $1\LDST_function_unit[11:0] 12'000000000000 + end + sync always + update \LDST_function_unit $0\LDST_function_unit[11:0] + end + attribute \src "libresoc.v:65413.3-65470.6" + process $proc$libresoc.v:65413$3546 + assign { } { } + assign { } { } + assign $0\LDST_internal_op[6:0] $1\LDST_internal_op[6:0] + attribute \src "libresoc.v:65414.5-65414.29" + switch \initial + attribute \src "libresoc.v:65414.9-65414.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_internal_op[6:0] \LDST_dec31_LDST_dec31_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_internal_op[6:0] \LDST_dec58_LDST_dec58_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_internal_op[6:0] \LDST_dec62_LDST_dec62_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100110 + case + assign $1\LDST_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_internal_op $0\LDST_internal_op[6:0] + end + attribute \src "libresoc.v:65471.3-65528.6" + process $proc$libresoc.v:65471$3547 + assign { } { } + assign { } { } + assign $0\LDST_in1_sel[2:0] $1\LDST_in1_sel[2:0] + attribute \src "libresoc.v:65472.5-65472.29" + switch \initial + attribute \src "libresoc.v:65472.9-65472.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_in1_sel[2:0] \LDST_dec31_LDST_dec31_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_in1_sel[2:0] \LDST_dec58_LDST_dec58_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_in1_sel[2:0] \LDST_dec62_LDST_dec62_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + case + assign $1\LDST_in1_sel[2:0] 3'000 + end + sync always + update \LDST_in1_sel $0\LDST_in1_sel[2:0] + end + attribute \src "libresoc.v:65529.3-65586.6" + process $proc$libresoc.v:65529$3548 + assign { } { } + assign { } { } + assign $0\LDST_in2_sel[3:0] $1\LDST_in2_sel[3:0] + attribute \src "libresoc.v:65530.5-65530.29" + switch \initial + attribute \src "libresoc.v:65530.9-65530.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_in2_sel[3:0] \LDST_dec31_LDST_dec31_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_in2_sel[3:0] \LDST_dec58_LDST_dec58_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_in2_sel[3:0] \LDST_dec62_LDST_dec62_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + case + assign $1\LDST_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_in2_sel $0\LDST_in2_sel[3:0] + end + attribute \src "libresoc.v:65587.3-65644.6" + process $proc$libresoc.v:65587$3549 + assign { } { } + assign { } { } + assign $0\LDST_cr_in[2:0] $1\LDST_cr_in[2:0] + attribute \src "libresoc.v:65588.5-65588.29" + switch \initial + attribute \src "libresoc.v:65588.9-65588.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_cr_in[2:0] \LDST_dec31_LDST_dec31_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_cr_in[2:0] \LDST_dec58_LDST_dec58_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_cr_in[2:0] \LDST_dec62_LDST_dec62_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + case + assign $1\LDST_cr_in[2:0] 3'000 + end + sync always + update \LDST_cr_in $0\LDST_cr_in[2:0] + end + attribute \src "libresoc.v:65645.3-65702.6" + process $proc$libresoc.v:65645$3550 + assign { } { } + assign { } { } + assign $0\LDST_cr_out[2:0] $1\LDST_cr_out[2:0] + attribute \src "libresoc.v:65646.5-65646.29" + switch \initial + attribute \src "libresoc.v:65646.9-65646.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_cr_out[2:0] \LDST_dec31_LDST_dec31_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_cr_out[2:0] \LDST_dec58_LDST_dec58_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_cr_out[2:0] \LDST_dec62_LDST_dec62_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + case + assign $1\LDST_cr_out[2:0] 3'000 + end + sync always + update \LDST_cr_out $0\LDST_cr_out[2:0] + end + connect \$1 $ternary$libresoc.v:64900$3537_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \LDST_SPR \opcode_in [20:11] + connect \LDST_MB \opcode_in [10:6] + connect \LDST_ME \opcode_in [5:1] + connect \LDST_SH \opcode_in [15:11] + connect \LDST_BC \opcode_in [10:6] + connect \LDST_TO \opcode_in [25:21] + connect \LDST_DS \opcode_in [15:2] + connect \LDST_D \opcode_in [15:0] + connect \LDST_BH \opcode_in [12:11] + connect \LDST_BI \opcode_in [20:16] + connect \LDST_BO \opcode_in [25:21] + connect \LDST_FXM \opcode_in [19:12] + connect \LDST_BT \opcode_in [25:21] + connect \LDST_BA \opcode_in [20:16] + connect \LDST_BB \opcode_in [15:11] + connect \LDST_CR \opcode_in [10:1] + connect \LDST_BF \opcode_in [25:23] + connect \LDST_BD \opcode_in [15:2] + connect \LDST_OE \opcode_in [10] + connect \LDST_Rc \opcode_in [0] + connect \LDST_AA \opcode_in [1] + connect \LDST_LK \opcode_in [0] + connect \LDST_LI \opcode_in [25:2] + connect \LDST_ME32 \opcode_in [5:1] + connect \LDST_MB32 \opcode_in [10:6] + connect \LDST_sh { \opcode_in [1] \opcode_in [15:11] } + connect \LDST_SH32 \opcode_in [15:11] + connect \LDST_L \opcode_in [21] + connect \LDST_UI \opcode_in [15:0] + connect \LDST_SI \opcode_in [15:0] + connect \LDST_RB \opcode_in [15:11] + connect \LDST_RA \opcode_in [20:16] + connect \LDST_RT \opcode_in [25:21] + connect \LDST_RS \opcode_in [25:21] + connect \opcode_in \$1 + connect \LDST_dec62_opcode_in \opcode_in + connect \LDST_dec58_opcode_in \opcode_in + connect \LDST_dec31_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:66038.1-71971.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec" +attribute \generator "nMigen" +module \dec$205 + attribute \src "libresoc.v:68232.3-68370.6" + wire width 8 $0\asmcode[7:0] + attribute \src "libresoc.v:70217.3-70358.6" + wire $0\br[0:0] + attribute \src "libresoc.v:68939.3-69080.6" + wire width 3 $0\cr_in[2:0] + attribute \src "libresoc.v:69081.3-69222.6" + wire width 3 $0\cr_out[2:0] + attribute \src "libresoc.v:69649.3-69790.6" + wire width 2 $0\cry_in[1:0] + attribute \src "libresoc.v:70075.3-70216.6" + wire $0\cry_out[0:0] + attribute \src "libresoc.v:71495.3-71636.6" + wire width 5 $0\form[4:0] + attribute \src "libresoc.v:71211.3-71352.6" + wire width 12 $0\function_unit[11:0] + attribute \src "libresoc.v:68371.3-68512.6" + wire width 3 $0\in1_sel[2:0] + attribute \src "libresoc.v:68513.3-68654.6" + wire width 4 $0\in2_sel[3:0] + attribute \src "libresoc.v:68655.3-68796.6" + wire width 2 $0\in3_sel[1:0] + attribute \src "libresoc.v:66039.7-66039.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:71353.3-71494.6" + wire width 7 $0\internal_op[6:0] + attribute \src "libresoc.v:69791.3-69932.6" + wire $0\inv_a[0:0] + attribute \src "libresoc.v:69933.3-70074.6" + wire $0\inv_out[0:0] + attribute \src "libresoc.v:70643.3-70784.6" + wire $0\is_32b[0:0] + attribute \src "libresoc.v:69223.3-69364.6" + wire width 4 $0\ldst_len[3:0] + attribute \src "libresoc.v:70927.3-71068.6" + wire $0\lk[0:0] + attribute \src "libresoc.v:68797.3-68938.6" + wire width 2 $0\out_sel[1:0] + attribute \src "libresoc.v:69507.3-69648.6" + wire width 2 $0\rc_sel[1:0] + attribute \src "libresoc.v:70501.3-70642.6" + wire $0\rsrv[0:0] + attribute \src "libresoc.v:71069.3-71210.6" + wire $0\sgl_pipe[0:0] + attribute \src "libresoc.v:70785.3-70926.6" + wire $0\sgn[0:0] + attribute \src "libresoc.v:70359.3-70500.6" + wire $0\sgn_ext[0:0] + attribute \src "libresoc.v:69365.3-69506.6" + wire width 2 $0\upd[1:0] + attribute \src "libresoc.v:68232.3-68370.6" + wire width 8 $1\asmcode[7:0] + attribute \src "libresoc.v:70217.3-70358.6" + wire $1\br[0:0] + attribute \src "libresoc.v:68939.3-69080.6" + wire width 3 $1\cr_in[2:0] + attribute \src "libresoc.v:69081.3-69222.6" + wire width 3 $1\cr_out[2:0] + attribute \src "libresoc.v:69649.3-69790.6" + wire width 2 $1\cry_in[1:0] + attribute \src "libresoc.v:70075.3-70216.6" + wire $1\cry_out[0:0] + attribute \src "libresoc.v:71495.3-71636.6" + wire width 5 $1\form[4:0] + attribute \src "libresoc.v:71211.3-71352.6" + wire width 12 $1\function_unit[11:0] + attribute \src "libresoc.v:68371.3-68512.6" + wire width 3 $1\in1_sel[2:0] + attribute \src "libresoc.v:68513.3-68654.6" + wire width 4 $1\in2_sel[3:0] + attribute \src "libresoc.v:68655.3-68796.6" + wire width 2 $1\in3_sel[1:0] + attribute \src "libresoc.v:71353.3-71494.6" + wire width 7 $1\internal_op[6:0] + attribute \src "libresoc.v:69791.3-69932.6" + wire $1\inv_a[0:0] + attribute \src "libresoc.v:69933.3-70074.6" + wire $1\inv_out[0:0] + attribute \src "libresoc.v:70643.3-70784.6" + wire $1\is_32b[0:0] + attribute \src "libresoc.v:69223.3-69364.6" + wire width 4 $1\ldst_len[3:0] + attribute \src "libresoc.v:70927.3-71068.6" + wire $1\lk[0:0] + attribute \src "libresoc.v:68797.3-68938.6" + wire width 2 $1\out_sel[1:0] + attribute \src "libresoc.v:69507.3-69648.6" + wire width 2 $1\rc_sel[1:0] + attribute \src "libresoc.v:70501.3-70642.6" + wire $1\rsrv[0:0] + attribute \src "libresoc.v:71069.3-71210.6" + wire $1\sgl_pipe[0:0] + attribute \src "libresoc.v:70785.3-70926.6" + wire $1\sgn[0:0] + attribute \src "libresoc.v:70359.3-70500.6" + wire $1\sgn_ext[0:0] + attribute \src "libresoc.v:69365.3-69506.6" + wire width 2 $1\upd[1:0] + attribute \src "libresoc.v:68232.3-68370.6" + wire width 8 $2\asmcode[7:0] + attribute \src "libresoc.v:70217.3-70358.6" + wire $2\br[0:0] + attribute \src "libresoc.v:68939.3-69080.6" + wire width 3 $2\cr_in[2:0] + attribute \src "libresoc.v:69081.3-69222.6" + wire width 3 $2\cr_out[2:0] + attribute \src "libresoc.v:69649.3-69790.6" + wire width 2 $2\cry_in[1:0] + attribute \src "libresoc.v:70075.3-70216.6" + wire $2\cry_out[0:0] + attribute \src "libresoc.v:71495.3-71636.6" + wire width 5 $2\form[4:0] + attribute \src "libresoc.v:71211.3-71352.6" + wire width 12 $2\function_unit[11:0] + attribute \src "libresoc.v:68371.3-68512.6" + wire width 3 $2\in1_sel[2:0] + attribute \src "libresoc.v:68513.3-68654.6" + wire width 4 $2\in2_sel[3:0] + attribute \src "libresoc.v:68655.3-68796.6" + wire width 2 $2\in3_sel[1:0] + attribute \src "libresoc.v:71353.3-71494.6" + wire width 7 $2\internal_op[6:0] + attribute \src "libresoc.v:69791.3-69932.6" + wire $2\inv_a[0:0] + attribute \src "libresoc.v:69933.3-70074.6" + wire $2\inv_out[0:0] + attribute \src "libresoc.v:70643.3-70784.6" + wire $2\is_32b[0:0] + attribute \src "libresoc.v:69223.3-69364.6" + wire width 4 $2\ldst_len[3:0] + attribute \src "libresoc.v:70927.3-71068.6" + wire $2\lk[0:0] + attribute \src "libresoc.v:68797.3-68938.6" + wire width 2 $2\out_sel[1:0] + attribute \src "libresoc.v:69507.3-69648.6" + wire width 2 $2\rc_sel[1:0] + attribute \src "libresoc.v:70501.3-70642.6" + wire $2\rsrv[0:0] + attribute \src "libresoc.v:71069.3-71210.6" + wire $2\sgl_pipe[0:0] + attribute \src "libresoc.v:70785.3-70926.6" + wire $2\sgn[0:0] + attribute \src "libresoc.v:70359.3-70500.6" + wire $2\sgn_ext[0:0] + attribute \src "libresoc.v:69365.3-69506.6" + wire width 2 $2\upd[1:0] + attribute \src "libresoc.v:68096.17-68096.211" + wire width 32 $ternary$libresoc.v:68096$3552_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + wire width 32 \$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 25 \BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 24 \BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 30 \BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 \BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 3 \BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 2 \BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 29 \BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 28 \BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 26 \BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 10 \CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 \D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 \DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 output 27 \FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 24 \LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire output 11 \LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire output 23 \OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 20 \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 21 \RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 18 \RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 19 \RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire output 22 \Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 \SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 10 output 31 \SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 \UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XL_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 output 34 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 15 \XL_OC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 output 35 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XO_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XO_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX2_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \XX2_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XX2_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \XX2_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XX2_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_dm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX3_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX3_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX3_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XX3_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX3_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XX3_DM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XX3_SHW + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX3_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX3_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \XX3_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \XX3_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XX3_XO_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX4_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX4_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX4_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX4_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX4_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX4_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX4_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX4_CX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX4_CX_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX4_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX4_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX4_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XX4_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 output 32 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 output 33 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \X_CT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \X_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \X_DRM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_E + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_EO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_EX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \X_E_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \X_IH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \X_IMM8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_L1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_L2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_L3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_MO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_NB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_PRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_RIC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_RM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_RO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_R_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_SP + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 16 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + wire input 36 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 4 \cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 \dec19_dec19_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec19_dec19_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \dec19_dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \dec19_dec19_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec19_dec19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec19_dec19_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 \dec19_dec19_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 \dec19_dec19_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \dec19_dec19_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \dec19_dec19_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src 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\enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec62_dec62_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \dec62_dec62_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec62_dec62_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec62_dec62_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec62_dec62_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \dec62_dec62_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec62_dec62_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec62_dec62_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec62_dec62_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec62_dec62_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec62_dec62_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec62_dec62_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec62_dec62_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec62_dec62_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \dec62_opcode_in + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 \form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 7 \function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 12 \in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 13 \in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \in3_sel + attribute \src "libresoc.v:66039.7-66039.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 6 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 9 \is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 10 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 32 \opcode_switch$1 + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 15 \out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + wire width 32 input 1 \raw_opcode_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 3 \rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 6 \sh + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 17 \upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + cell $mux $ternary$libresoc.v:68096$3552 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:68096$3552_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:68097.9-68123.4" + cell \dec19 \dec19 + connect \dec19_asmcode \dec19_dec19_asmcode + connect \dec19_br \dec19_dec19_br + connect \dec19_cr_in \dec19_dec19_cr_in + connect \dec19_cr_out \dec19_dec19_cr_out + connect \dec19_cry_in \dec19_dec19_cry_in + connect \dec19_cry_out \dec19_dec19_cry_out + connect \dec19_form \dec19_dec19_form + connect \dec19_function_unit \dec19_dec19_function_unit + connect \dec19_in1_sel \dec19_dec19_in1_sel + connect \dec19_in2_sel \dec19_dec19_in2_sel + connect \dec19_in3_sel \dec19_dec19_in3_sel + connect \dec19_internal_op \dec19_dec19_internal_op + connect \dec19_inv_a \dec19_dec19_inv_a + connect \dec19_inv_out \dec19_dec19_inv_out + connect \dec19_is_32b \dec19_dec19_is_32b + connect \dec19_ldst_len \dec19_dec19_ldst_len + connect \dec19_lk \dec19_dec19_lk + connect \dec19_out_sel \dec19_dec19_out_sel + connect \dec19_rc_sel \dec19_dec19_rc_sel + connect \dec19_rsrv \dec19_dec19_rsrv + connect \dec19_sgl_pipe \dec19_dec19_sgl_pipe + connect \dec19_sgn \dec19_dec19_sgn + connect \dec19_sgn_ext \dec19_dec19_sgn_ext + connect \dec19_upd \dec19_dec19_upd + connect \opcode_in \dec19_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:68124.9-68150.4" + cell \dec30 \dec30 + connect \dec30_asmcode \dec30_dec30_asmcode + connect \dec30_br \dec30_dec30_br + connect \dec30_cr_in \dec30_dec30_cr_in + connect \dec30_cr_out \dec30_dec30_cr_out + connect \dec30_cry_in \dec30_dec30_cry_in + connect \dec30_cry_out \dec30_dec30_cry_out + connect \dec30_form \dec30_dec30_form + connect \dec30_function_unit \dec30_dec30_function_unit + connect \dec30_in1_sel \dec30_dec30_in1_sel + connect \dec30_in2_sel \dec30_dec30_in2_sel + connect \dec30_in3_sel \dec30_dec30_in3_sel + connect \dec30_internal_op \dec30_dec30_internal_op + connect \dec30_inv_a \dec30_dec30_inv_a + connect \dec30_inv_out \dec30_dec30_inv_out + connect \dec30_is_32b \dec30_dec30_is_32b + connect \dec30_ldst_len \dec30_dec30_ldst_len + connect \dec30_lk \dec30_dec30_lk + connect \dec30_out_sel \dec30_dec30_out_sel + connect \dec30_rc_sel \dec30_dec30_rc_sel + connect \dec30_rsrv \dec30_dec30_rsrv + connect \dec30_sgl_pipe \dec30_dec30_sgl_pipe + connect \dec30_sgn \dec30_dec30_sgn + connect \dec30_sgn_ext \dec30_dec30_sgn_ext + connect \dec30_upd \dec30_dec30_upd + connect \opcode_in \dec30_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:68151.9-68177.4" + cell \dec31 \dec31 + connect \dec31_asmcode \dec31_dec31_asmcode + connect \dec31_br \dec31_dec31_br + connect \dec31_cr_in \dec31_dec31_cr_in + connect \dec31_cr_out \dec31_dec31_cr_out + connect \dec31_cry_in \dec31_dec31_cry_in + connect \dec31_cry_out \dec31_dec31_cry_out + connect \dec31_form \dec31_dec31_form + connect \dec31_function_unit \dec31_dec31_function_unit + connect \dec31_in1_sel \dec31_dec31_in1_sel + connect \dec31_in2_sel \dec31_dec31_in2_sel + connect \dec31_in3_sel \dec31_dec31_in3_sel + connect \dec31_internal_op \dec31_dec31_internal_op + connect \dec31_inv_a \dec31_dec31_inv_a + connect \dec31_inv_out \dec31_dec31_inv_out + connect \dec31_is_32b \dec31_dec31_is_32b + connect \dec31_ldst_len \dec31_dec31_ldst_len + connect \dec31_lk \dec31_dec31_lk + connect \dec31_out_sel \dec31_dec31_out_sel + connect \dec31_rc_sel \dec31_dec31_rc_sel + connect \dec31_rsrv \dec31_dec31_rsrv + connect \dec31_sgl_pipe \dec31_dec31_sgl_pipe + connect \dec31_sgn \dec31_dec31_sgn + connect \dec31_sgn_ext \dec31_dec31_sgn_ext + connect \dec31_upd \dec31_dec31_upd + connect \opcode_in \dec31_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:68178.9-68204.4" + cell \dec58 \dec58 + connect \dec58_asmcode \dec58_dec58_asmcode + connect \dec58_br \dec58_dec58_br + connect \dec58_cr_in \dec58_dec58_cr_in + connect \dec58_cr_out \dec58_dec58_cr_out + connect \dec58_cry_in \dec58_dec58_cry_in + connect \dec58_cry_out \dec58_dec58_cry_out + connect \dec58_form \dec58_dec58_form + connect \dec58_function_unit \dec58_dec58_function_unit + connect \dec58_in1_sel \dec58_dec58_in1_sel + connect \dec58_in2_sel \dec58_dec58_in2_sel + connect \dec58_in3_sel \dec58_dec58_in3_sel + connect \dec58_internal_op \dec58_dec58_internal_op + connect \dec58_inv_a \dec58_dec58_inv_a + connect \dec58_inv_out \dec58_dec58_inv_out + connect \dec58_is_32b \dec58_dec58_is_32b + connect \dec58_ldst_len \dec58_dec58_ldst_len + connect \dec58_lk \dec58_dec58_lk + connect \dec58_out_sel \dec58_dec58_out_sel + connect \dec58_rc_sel \dec58_dec58_rc_sel + connect \dec58_rsrv \dec58_dec58_rsrv + connect \dec58_sgl_pipe \dec58_dec58_sgl_pipe + connect \dec58_sgn \dec58_dec58_sgn + connect \dec58_sgn_ext \dec58_dec58_sgn_ext + connect \dec58_upd \dec58_dec58_upd + connect \opcode_in \dec58_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:68205.9-68231.4" + cell \dec62 \dec62 + connect \dec62_asmcode \dec62_dec62_asmcode + connect \dec62_br \dec62_dec62_br + connect \dec62_cr_in \dec62_dec62_cr_in + connect \dec62_cr_out \dec62_dec62_cr_out + connect \dec62_cry_in \dec62_dec62_cry_in + connect \dec62_cry_out \dec62_dec62_cry_out + connect \dec62_form \dec62_dec62_form + connect \dec62_function_unit \dec62_dec62_function_unit + connect \dec62_in1_sel \dec62_dec62_in1_sel + connect \dec62_in2_sel \dec62_dec62_in2_sel + connect \dec62_in3_sel \dec62_dec62_in3_sel + connect \dec62_internal_op \dec62_dec62_internal_op + connect \dec62_inv_a \dec62_dec62_inv_a + connect \dec62_inv_out \dec62_dec62_inv_out + connect \dec62_is_32b \dec62_dec62_is_32b + connect \dec62_ldst_len \dec62_dec62_ldst_len + connect \dec62_lk \dec62_dec62_lk + connect \dec62_out_sel \dec62_dec62_out_sel + connect \dec62_rc_sel \dec62_dec62_rc_sel + connect \dec62_rsrv \dec62_dec62_rsrv + connect \dec62_sgl_pipe \dec62_dec62_sgl_pipe + connect \dec62_sgn \dec62_dec62_sgn + connect \dec62_sgn_ext \dec62_dec62_sgn_ext + connect \dec62_upd \dec62_dec62_upd + connect \opcode_in \dec62_opcode_in + end + attribute \src "libresoc.v:66039.7-66039.20" + process $proc$libresoc.v:66039$3577 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:68232.3-68370.6" + process $proc$libresoc.v:68232$3553 + assign { } { } + assign { } { } + assign { } { } + assign $0\asmcode[7:0] $2\asmcode[7:0] + attribute \src "libresoc.v:68233.5-68233.29" + switch \initial + attribute \src "libresoc.v:68233.9-68233.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\asmcode[7:0] \dec19_dec19_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\asmcode[7:0] \dec30_dec30_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\asmcode[7:0] \dec31_dec31_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\asmcode[7:0] \dec58_dec58_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\asmcode[7:0] \dec62_dec62_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\asmcode[7:0] 8'00000111 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\asmcode[7:0] 8'00001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\asmcode[7:0] 8'00000110 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\asmcode[7:0] 8'00001001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\asmcode[7:0] 8'00010001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\asmcode[7:0] 8'00010010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\asmcode[7:0] 8'00010100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\asmcode[7:0] 8'00010101 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\asmcode[7:0] 8'00011101 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\asmcode[7:0] 8'00011111 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\asmcode[7:0] 8'01001110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\asmcode[7:0] 8'01001111 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\asmcode[7:0] 8'01011000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\asmcode[7:0] 8'01011010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\asmcode[7:0] 8'01011110 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\asmcode[7:0] 8'01011111 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\asmcode[7:0] 8'01100111 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\asmcode[7:0] 8'01101001 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\asmcode[7:0] 8'10000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\asmcode[7:0] 8'10001010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\asmcode[7:0] 8'10001011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\asmcode[7:0] 8'10011000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\asmcode[7:0] 8'10011001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\asmcode[7:0] 8'10011010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\asmcode[7:0] 8'10100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\asmcode[7:0] 8'10101001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\asmcode[7:0] 8'10110010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\asmcode[7:0] 8'10110101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\asmcode[7:0] 8'10111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\asmcode[7:0] 8'10111011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\asmcode[7:0] 8'11000011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\asmcode[7:0] 8'11001011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\asmcode[7:0] 8'11001111 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\asmcode[7:0] 8'11010001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\asmcode[7:0] 8'11010010 + case + assign $1\asmcode[7:0] 8'00000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\asmcode[7:0] 8'00010011 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\asmcode[7:0] 8'10000110 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\asmcode[7:0] 8'10011100 + case + assign $2\asmcode[7:0] $1\asmcode[7:0] + end + sync always + update \asmcode $0\asmcode[7:0] + end + attribute \src "libresoc.v:68371.3-68512.6" + process $proc$libresoc.v:68371$3554 + assign { } { } + assign { } { } + assign { } { } + assign $0\in1_sel[2:0] $2\in1_sel[2:0] + attribute \src "libresoc.v:68372.5-68372.29" + switch \initial + attribute \src "libresoc.v:68372.9-68372.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\in1_sel[2:0] \dec19_dec19_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\in1_sel[2:0] \dec30_dec30_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\in1_sel[2:0] \dec31_dec31_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\in1_sel[2:0] \dec58_dec58_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\in1_sel[2:0] \dec62_dec62_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + case + assign $1\in1_sel[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\in1_sel[2:0] 3'000 + case + assign $2\in1_sel[2:0] $1\in1_sel[2:0] + end + sync always + update \in1_sel $0\in1_sel[2:0] + end + attribute \src "libresoc.v:68513.3-68654.6" + process $proc$libresoc.v:68513$3555 + assign { } { } + assign { } { } + assign { } { } + assign $0\in2_sel[3:0] $2\in2_sel[3:0] + attribute \src "libresoc.v:68514.5-68514.29" + switch \initial + attribute \src "libresoc.v:68514.9-68514.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\in2_sel[3:0] \dec19_dec19_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\in2_sel[3:0] \dec30_dec30_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\in2_sel[3:0] \dec31_dec31_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\in2_sel[3:0] \dec58_dec58_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\in2_sel[3:0] \dec62_dec62_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\in2_sel[3:0] 4'0101 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\in2_sel[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\in2_sel[3:0] 4'0110 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\in2_sel[3:0] 4'0111 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\in2_sel[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\in2_sel[3:0] 4'1011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\in2_sel[3:0] 4'1011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\in2_sel[3:0] 4'0100 + case + assign $1\in2_sel[3:0] 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\in2_sel[3:0] 4'0000 + case + assign $2\in2_sel[3:0] $1\in2_sel[3:0] + end + sync always + update \in2_sel $0\in2_sel[3:0] + end + attribute \src "libresoc.v:68655.3-68796.6" + process $proc$libresoc.v:68655$3556 + assign { } { } + assign { } { } + assign { } { } + assign $0\in3_sel[1:0] $2\in3_sel[1:0] + attribute \src "libresoc.v:68656.5-68656.29" + switch \initial + attribute \src "libresoc.v:68656.9-68656.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\in3_sel[1:0] \dec19_dec19_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\in3_sel[1:0] \dec30_dec30_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\in3_sel[1:0] \dec31_dec31_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\in3_sel[1:0] \dec58_dec58_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\in3_sel[1:0] \dec62_dec62_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + case + assign $1\in3_sel[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\in3_sel[1:0] 2'00 + case + assign $2\in3_sel[1:0] $1\in3_sel[1:0] + end + sync always + update \in3_sel $0\in3_sel[1:0] + end + attribute \src "libresoc.v:68797.3-68938.6" + process $proc$libresoc.v:68797$3557 + assign { } { } + assign { } { } + assign { } { } + assign $0\out_sel[1:0] $2\out_sel[1:0] + attribute \src "libresoc.v:68798.5-68798.29" + switch \initial + attribute \src "libresoc.v:68798.9-68798.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\out_sel[1:0] \dec19_dec19_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\out_sel[1:0] \dec30_dec30_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\out_sel[1:0] \dec31_dec31_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\out_sel[1:0] \dec58_dec58_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\out_sel[1:0] \dec62_dec62_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\out_sel[1:0] 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\out_sel[1:0] 2'10 + case + assign $1\out_sel[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\out_sel[1:0] 2'01 + case + assign $2\out_sel[1:0] $1\out_sel[1:0] + end + sync always + update \out_sel $0\out_sel[1:0] + end + attribute \src "libresoc.v:68939.3-69080.6" + process $proc$libresoc.v:68939$3558 + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_in[2:0] $2\cr_in[2:0] + attribute \src "libresoc.v:68940.5-68940.29" + switch \initial + attribute \src "libresoc.v:68940.9-68940.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\cr_in[2:0] \dec19_dec19_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\cr_in[2:0] \dec30_dec30_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\cr_in[2:0] \dec31_dec31_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\cr_in[2:0] \dec58_dec58_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\cr_in[2:0] \dec62_dec62_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + case + assign $1\cr_in[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\cr_in[2:0] 3'000 + case + assign $2\cr_in[2:0] $1\cr_in[2:0] + end + sync always + update \cr_in $0\cr_in[2:0] + end + attribute \src "libresoc.v:69081.3-69222.6" + process $proc$libresoc.v:69081$3559 + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_out[2:0] $2\cr_out[2:0] + attribute \src "libresoc.v:69082.5-69082.29" + switch \initial + attribute \src "libresoc.v:69082.9-69082.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\cr_out[2:0] \dec19_dec19_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\cr_out[2:0] \dec30_dec30_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\cr_out[2:0] \dec31_dec31_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\cr_out[2:0] \dec58_dec58_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\cr_out[2:0] \dec62_dec62_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\cr_out[2:0] 3'000 + case + assign $1\cr_out[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\cr_out[2:0] 3'000 + case + assign $2\cr_out[2:0] $1\cr_out[2:0] + end + sync always + update \cr_out $0\cr_out[2:0] + end + attribute \src "libresoc.v:69223.3-69364.6" + process $proc$libresoc.v:69223$3560 + assign { } { } + assign { } { } + assign { } { } + assign $0\ldst_len[3:0] $2\ldst_len[3:0] + attribute \src "libresoc.v:69224.5-69224.29" + switch \initial + attribute \src "libresoc.v:69224.9-69224.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ldst_len[3:0] \dec19_dec19_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\ldst_len[3:0] \dec30_dec30_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ldst_len[3:0] \dec31_dec31_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\ldst_len[3:0] \dec58_dec58_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\ldst_len[3:0] \dec62_dec62_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + case + assign $1\ldst_len[3:0] 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\ldst_len[3:0] 4'0000 + case + assign $2\ldst_len[3:0] $1\ldst_len[3:0] + end + sync always + update \ldst_len $0\ldst_len[3:0] + end + attribute \src "libresoc.v:69365.3-69506.6" + process $proc$libresoc.v:69365$3561 + assign { } { } + assign { } { } + assign { } { } + assign $0\upd[1:0] $2\upd[1:0] + attribute \src "libresoc.v:69366.5-69366.29" + switch \initial + attribute \src "libresoc.v:69366.9-69366.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\upd[1:0] \dec19_dec19_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\upd[1:0] \dec30_dec30_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\upd[1:0] \dec31_dec31_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\upd[1:0] \dec58_dec58_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\upd[1:0] \dec62_dec62_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\upd[1:0] 2'00 + case + assign $1\upd[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\upd[1:0] 2'00 + case + assign $2\upd[1:0] $1\upd[1:0] + end + sync always + update \upd $0\upd[1:0] + end + attribute \src "libresoc.v:69507.3-69648.6" + process $proc$libresoc.v:69507$3562 + assign { } { } + assign { } { } + assign { } { } + assign $0\rc_sel[1:0] $2\rc_sel[1:0] + attribute \src "libresoc.v:69508.5-69508.29" + switch \initial + attribute \src "libresoc.v:69508.9-69508.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\rc_sel[1:0] \dec19_dec19_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\rc_sel[1:0] \dec30_dec30_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\rc_sel[1:0] \dec31_dec31_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\rc_sel[1:0] \dec58_dec58_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\rc_sel[1:0] \dec62_dec62_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + case + assign $1\rc_sel[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\rc_sel[1:0] 2'00 + case + assign $2\rc_sel[1:0] $1\rc_sel[1:0] + end + sync always + update \rc_sel $0\rc_sel[1:0] + end + attribute \src "libresoc.v:69649.3-69790.6" + process $proc$libresoc.v:69649$3563 + assign { } { } + assign { } { } + assign { } { } + assign $0\cry_in[1:0] $2\cry_in[1:0] + attribute \src "libresoc.v:69650.5-69650.29" + switch \initial + attribute \src "libresoc.v:69650.9-69650.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\cry_in[1:0] \dec19_dec19_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\cry_in[1:0] \dec30_dec30_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\cry_in[1:0] \dec31_dec31_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\cry_in[1:0] \dec58_dec58_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\cry_in[1:0] \dec62_dec62_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\cry_in[1:0] 2'00 + case + assign $1\cry_in[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\cry_in[1:0] 2'00 + case + assign $2\cry_in[1:0] $1\cry_in[1:0] + end + sync always + update \cry_in $0\cry_in[1:0] + end + attribute \src "libresoc.v:69791.3-69932.6" + process $proc$libresoc.v:69791$3564 + assign { } { } + assign { } { } + assign { } { } + assign $0\inv_a[0:0] $2\inv_a[0:0] + attribute \src "libresoc.v:69792.5-69792.29" + switch \initial + attribute \src "libresoc.v:69792.9-69792.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\inv_a[0:0] \dec19_dec19_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\inv_a[0:0] \dec30_dec30_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\inv_a[0:0] \dec31_dec31_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\inv_a[0:0] \dec58_dec58_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\inv_a[0:0] \dec62_dec62_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\inv_a[0:0] 1'0 + case + assign $1\inv_a[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\inv_a[0:0] 1'0 + case + assign $2\inv_a[0:0] $1\inv_a[0:0] + end + sync always + update \inv_a $0\inv_a[0:0] + end + attribute \src "libresoc.v:69933.3-70074.6" + process $proc$libresoc.v:69933$3565 + assign { } { } + assign { } { } + assign { } { } + assign $0\inv_out[0:0] $2\inv_out[0:0] + attribute \src "libresoc.v:69934.5-69934.29" + switch \initial + attribute \src "libresoc.v:69934.9-69934.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\inv_out[0:0] \dec19_dec19_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\inv_out[0:0] \dec30_dec30_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\inv_out[0:0] \dec31_dec31_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\inv_out[0:0] \dec58_dec58_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\inv_out[0:0] \dec62_dec62_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + case + assign $1\inv_out[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\inv_out[0:0] 1'0 + case + assign $2\inv_out[0:0] $1\inv_out[0:0] + end + sync always + update \inv_out $0\inv_out[0:0] + end + attribute \src "libresoc.v:70075.3-70216.6" + process $proc$libresoc.v:70075$3566 + assign { } { } + assign { } { } + assign { } { } + assign $0\cry_out[0:0] $2\cry_out[0:0] + attribute \src "libresoc.v:70076.5-70076.29" + switch \initial + attribute \src "libresoc.v:70076.9-70076.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\cry_out[0:0] \dec19_dec19_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\cry_out[0:0] \dec30_dec30_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\cry_out[0:0] \dec31_dec31_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\cry_out[0:0] \dec58_dec58_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\cry_out[0:0] \dec62_dec62_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + case + assign $1\cry_out[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\cry_out[0:0] 1'0 + case + assign $2\cry_out[0:0] $1\cry_out[0:0] + end + sync always + update \cry_out $0\cry_out[0:0] + end + attribute \src "libresoc.v:70217.3-70358.6" + process $proc$libresoc.v:70217$3567 + assign { } { } + assign { } { } + assign { } { } + assign $0\br[0:0] $2\br[0:0] + attribute \src "libresoc.v:70218.5-70218.29" + switch \initial + attribute \src "libresoc.v:70218.9-70218.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\br[0:0] \dec19_dec19_br + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\br[0:0] \dec30_dec30_br + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\br[0:0] \dec31_dec31_br + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\br[0:0] \dec58_dec58_br + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\br[0:0] \dec62_dec62_br + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\br[0:0] 1'0 + case + assign $1\br[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\br[0:0] 1'0 + case + assign $2\br[0:0] $1\br[0:0] + end + sync always + update \br $0\br[0:0] + end + attribute \src "libresoc.v:70359.3-70500.6" + process $proc$libresoc.v:70359$3568 + assign { } { } + assign { } { } + assign { } { } + assign $0\sgn_ext[0:0] $2\sgn_ext[0:0] + attribute \src "libresoc.v:70360.5-70360.29" + switch \initial + attribute \src "libresoc.v:70360.9-70360.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sgn_ext[0:0] \dec19_dec19_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sgn_ext[0:0] \dec30_dec30_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sgn_ext[0:0] \dec31_dec31_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sgn_ext[0:0] \dec58_dec58_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sgn_ext[0:0] \dec62_dec62_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + case + assign $1\sgn_ext[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sgn_ext[0:0] 1'0 + case + assign $2\sgn_ext[0:0] $1\sgn_ext[0:0] + end + sync always + update \sgn_ext $0\sgn_ext[0:0] + end + attribute \src "libresoc.v:70501.3-70642.6" + process $proc$libresoc.v:70501$3569 + assign { } { } + assign { } { } + assign { } { } + assign $0\rsrv[0:0] $2\rsrv[0:0] + attribute \src "libresoc.v:70502.5-70502.29" + switch \initial + attribute \src "libresoc.v:70502.9-70502.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\rsrv[0:0] \dec19_dec19_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\rsrv[0:0] \dec30_dec30_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\rsrv[0:0] \dec31_dec31_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\rsrv[0:0] \dec58_dec58_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\rsrv[0:0] \dec62_dec62_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + case + assign $1\rsrv[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\rsrv[0:0] 1'0 + case + assign $2\rsrv[0:0] $1\rsrv[0:0] + end + sync always + update \rsrv $0\rsrv[0:0] + end + attribute \src "libresoc.v:70643.3-70784.6" + process $proc$libresoc.v:70643$3570 + assign { } { } + assign { } { } + assign { } { } + assign $0\is_32b[0:0] $2\is_32b[0:0] + attribute \src "libresoc.v:70644.5-70644.29" + switch \initial + attribute \src "libresoc.v:70644.9-70644.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\is_32b[0:0] \dec19_dec19_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\is_32b[0:0] \dec30_dec30_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\is_32b[0:0] \dec31_dec31_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\is_32b[0:0] \dec58_dec58_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\is_32b[0:0] \dec62_dec62_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\is_32b[0:0] 1'0 + case + assign $1\is_32b[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\is_32b[0:0] 1'0 + case + assign $2\is_32b[0:0] $1\is_32b[0:0] + end + sync always + update \is_32b $0\is_32b[0:0] + end + attribute \src "libresoc.v:70785.3-70926.6" + process $proc$libresoc.v:70785$3571 + assign { } { } + assign { } { } + assign { } { } + assign $0\sgn[0:0] $2\sgn[0:0] + attribute \src "libresoc.v:70786.5-70786.29" + switch \initial + attribute \src "libresoc.v:70786.9-70786.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sgn[0:0] \dec19_dec19_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sgn[0:0] \dec30_dec30_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sgn[0:0] \dec31_dec31_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sgn[0:0] \dec58_dec58_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sgn[0:0] \dec62_dec62_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sgn[0:0] 1'0 + case + assign $1\sgn[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sgn[0:0] 1'0 + case + assign $2\sgn[0:0] $1\sgn[0:0] + end + sync always + update \sgn $0\sgn[0:0] + end + attribute \src "libresoc.v:70927.3-71068.6" + process $proc$libresoc.v:70927$3572 + assign { } { } + assign { } { } + assign { } { } + assign $0\lk[0:0] $2\lk[0:0] + attribute \src "libresoc.v:70928.5-70928.29" + switch \initial + attribute \src "libresoc.v:70928.9-70928.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\lk[0:0] \dec19_dec19_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\lk[0:0] \dec30_dec30_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\lk[0:0] \dec31_dec31_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\lk[0:0] \dec58_dec58_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\lk[0:0] \dec62_dec62_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\lk[0:0] 1'0 + case + assign $1\lk[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\lk[0:0] 1'0 + case + assign $2\lk[0:0] $1\lk[0:0] + end + sync always + update \lk $0\lk[0:0] + end + attribute \src "libresoc.v:71069.3-71210.6" + process $proc$libresoc.v:71069$3573 + assign { } { } + assign { } { } + assign { } { } + assign $0\sgl_pipe[0:0] $2\sgl_pipe[0:0] + attribute \src "libresoc.v:71070.5-71070.29" + switch \initial + attribute \src "libresoc.v:71070.9-71070.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sgl_pipe[0:0] \dec19_dec19_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sgl_pipe[0:0] \dec30_dec30_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sgl_pipe[0:0] \dec31_dec31_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sgl_pipe[0:0] \dec58_dec58_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sgl_pipe[0:0] \dec62_dec62_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + case + assign $1\sgl_pipe[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sgl_pipe[0:0] 1'1 + case + assign $2\sgl_pipe[0:0] $1\sgl_pipe[0:0] + end + sync always + update \sgl_pipe $0\sgl_pipe[0:0] + end + attribute \src "libresoc.v:71211.3-71352.6" + process $proc$libresoc.v:71211$3574 + assign { } { } + assign { } { } + assign { } { } + assign $0\function_unit[11:0] $2\function_unit[11:0] + attribute \src "libresoc.v:71212.5-71212.29" + switch \initial + attribute \src "libresoc.v:71212.9-71212.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\function_unit[11:0] \dec19_dec19_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\function_unit[11:0] \dec30_dec30_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\function_unit[11:0] \dec31_dec31_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\function_unit[11:0] \dec58_dec58_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\function_unit[11:0] \dec62_dec62_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\function_unit[11:0] 12'000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\function_unit[11:0] 12'000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\function_unit[11:0] 12'000000010000 + case + assign $1\function_unit[11:0] 12'000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\function_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\function_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\function_unit[11:0] 12'000000000000 + case + assign $2\function_unit[11:0] $1\function_unit[11:0] + end + sync always + update \function_unit $0\function_unit[11:0] + end + attribute \src "libresoc.v:71353.3-71494.6" + process $proc$libresoc.v:71353$3575 + assign { } { } + assign { } { } + assign { } { } + assign $0\internal_op[6:0] $2\internal_op[6:0] + attribute \src "libresoc.v:71354.5-71354.29" + switch \initial + attribute \src "libresoc.v:71354.9-71354.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\internal_op[6:0] \dec19_dec19_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\internal_op[6:0] \dec30_dec30_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\internal_op[6:0] \dec31_dec31_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\internal_op[6:0] \dec58_dec58_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\internal_op[6:0] \dec62_dec62_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\internal_op[6:0] 7'1001001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\internal_op[6:0] 7'0000110 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\internal_op[6:0] 7'0000111 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\internal_op[6:0] 7'0110010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\internal_op[6:0] 7'0111111 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\internal_op[6:0] 7'0111111 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\internal_op[6:0] 7'1000011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\internal_op[6:0] 7'1000011 + case + assign $1\internal_op[6:0] 7'0000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\internal_op[6:0] 7'0000101 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\internal_op[6:0] 7'1000100 + case + assign $2\internal_op[6:0] $1\internal_op[6:0] + end + sync always + update \internal_op $0\internal_op[6:0] + end + attribute \src "libresoc.v:71495.3-71636.6" + process $proc$libresoc.v:71495$3576 + assign { } { } + assign { } { } + assign { } { } + assign $0\form[4:0] $2\form[4:0] + attribute \src "libresoc.v:71496.5-71496.29" + switch \initial + attribute \src "libresoc.v:71496.9-71496.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\form[4:0] \dec19_dec19_form + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\form[4:0] \dec30_dec30_form + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\form[4:0] \dec31_dec31_form + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\form[4:0] \dec58_dec58_form + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\form[4:0] \dec62_dec62_form + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\form[4:0] 5'00011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\form[4:0] 5'00010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\form[4:0] 5'00010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\form[4:0] 5'00001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\form[4:0] 5'00010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\form[4:0] 5'10011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\form[4:0] 5'10011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\form[4:0] 5'10011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\form[4:0] 5'00100 + case + assign $1\form[4:0] 5'00000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\form[4:0] 5'00000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\form[4:0] 5'00000 + case + assign $2\form[4:0] $1\form[4:0] + end + sync always + update \form $0\form[4:0] + end + connect \$2 $ternary$libresoc.v:68096$3552_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \SPR \opcode_in [20:11] + connect \MB \opcode_in [10:6] + connect \ME \opcode_in [5:1] + connect \SH \opcode_in [15:11] + connect \BC \opcode_in [10:6] + connect \TO \opcode_in [25:21] + connect \DS \opcode_in [15:2] + connect \D \opcode_in [15:0] + connect \BH \opcode_in [12:11] + connect \BI \opcode_in [20:16] + connect \BO \opcode_in [25:21] + connect \FXM \opcode_in [19:12] + connect \BT \opcode_in [25:21] + connect \BA \opcode_in [20:16] + connect \BB \opcode_in [15:11] + connect \CR \opcode_in [10:1] + connect \BF \opcode_in [25:23] + connect \BD \opcode_in [15:2] + connect \OE \opcode_in [10] + connect \Rc \opcode_in [0] + connect \AA \opcode_in [1] + connect \LK \opcode_in [0] + connect \LI \opcode_in [25:2] + connect \ME32 \opcode_in [5:1] + connect \MB32 \opcode_in [10:6] + connect \sh { \opcode_in [1] \opcode_in [15:11] } + connect \SH32 \opcode_in [15:11] + connect \L \opcode_in [21] + connect \UI \opcode_in [15:0] + connect \SI \opcode_in [15:0] + connect \RB \opcode_in [15:11] + connect \RA \opcode_in [20:16] + connect \RT \opcode_in [25:21] + connect \RS \opcode_in [25:21] + connect \opcode_in \$2 + connect \opcode_switch$1 \opcode_in + connect \dec62_opcode_in \opcode_in + connect \dec58_opcode_in \opcode_in + connect \dec31_opcode_in \opcode_in + connect \dec30_opcode_in \opcode_in + connect \dec19_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:71975.1-73482.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec19" +attribute \generator "nMigen" +module \dec19 + attribute \src "libresoc.v:72493.3-72544.6" + wire width 8 $0\dec19_asmcode[7:0] + attribute \src "libresoc.v:72701.3-72752.6" + wire $0\dec19_br[0:0] + attribute \src "libresoc.v:73377.3-73428.6" + wire width 3 $0\dec19_cr_in[2:0] + attribute \src "libresoc.v:73429.3-73480.6" + wire width 3 $0\dec19_cr_out[2:0] + attribute \src "libresoc.v:72441.3-72492.6" + wire width 2 $0\dec19_cry_in[1:0] + attribute \src "libresoc.v:72649.3-72700.6" + wire $0\dec19_cry_out[0:0] + attribute \src "libresoc.v:73117.3-73168.6" + wire width 5 $0\dec19_form[4:0] + attribute \src "libresoc.v:72233.3-72284.6" + wire width 12 $0\dec19_function_unit[11:0] + attribute \src "libresoc.v:73169.3-73220.6" + wire width 3 $0\dec19_in1_sel[2:0] + attribute \src "libresoc.v:73221.3-73272.6" + wire width 4 $0\dec19_in2_sel[3:0] + attribute \src "libresoc.v:73273.3-73324.6" + wire width 2 $0\dec19_in3_sel[1:0] + attribute \src "libresoc.v:72805.3-72856.6" + wire width 7 $0\dec19_internal_op[6:0] + attribute \src "libresoc.v:72545.3-72596.6" + wire $0\dec19_inv_a[0:0] + attribute \src "libresoc.v:72597.3-72648.6" + wire $0\dec19_inv_out[0:0] + attribute \src "libresoc.v:72909.3-72960.6" + wire $0\dec19_is_32b[0:0] + attribute \src "libresoc.v:72285.3-72336.6" + wire width 4 $0\dec19_ldst_len[3:0] + attribute \src "libresoc.v:73013.3-73064.6" + wire $0\dec19_lk[0:0] + attribute \src "libresoc.v:73325.3-73376.6" + wire width 2 $0\dec19_out_sel[1:0] + attribute \src "libresoc.v:72389.3-72440.6" + wire width 2 $0\dec19_rc_sel[1:0] + attribute \src "libresoc.v:72857.3-72908.6" + wire $0\dec19_rsrv[0:0] + attribute \src "libresoc.v:73065.3-73116.6" + wire $0\dec19_sgl_pipe[0:0] + attribute \src "libresoc.v:72961.3-73012.6" + wire $0\dec19_sgn[0:0] + attribute \src "libresoc.v:72753.3-72804.6" + wire $0\dec19_sgn_ext[0:0] + attribute \src "libresoc.v:72337.3-72388.6" + wire width 2 $0\dec19_upd[1:0] + attribute \src "libresoc.v:71976.7-71976.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:72493.3-72544.6" + wire width 8 $1\dec19_asmcode[7:0] + attribute \src "libresoc.v:72701.3-72752.6" + wire $1\dec19_br[0:0] + attribute \src "libresoc.v:73377.3-73428.6" + wire width 3 $1\dec19_cr_in[2:0] + attribute \src "libresoc.v:73429.3-73480.6" + wire width 3 $1\dec19_cr_out[2:0] + attribute \src "libresoc.v:72441.3-72492.6" + wire width 2 $1\dec19_cry_in[1:0] + attribute \src "libresoc.v:72649.3-72700.6" + wire $1\dec19_cry_out[0:0] + attribute \src "libresoc.v:73117.3-73168.6" + wire width 5 $1\dec19_form[4:0] + attribute \src "libresoc.v:72233.3-72284.6" + wire width 12 $1\dec19_function_unit[11:0] + attribute \src "libresoc.v:73169.3-73220.6" + wire width 3 $1\dec19_in1_sel[2:0] + attribute \src "libresoc.v:73221.3-73272.6" + wire width 4 $1\dec19_in2_sel[3:0] + attribute \src "libresoc.v:73273.3-73324.6" + wire width 2 $1\dec19_in3_sel[1:0] + attribute \src "libresoc.v:72805.3-72856.6" + wire width 7 $1\dec19_internal_op[6:0] + attribute \src "libresoc.v:72545.3-72596.6" + wire $1\dec19_inv_a[0:0] + attribute \src "libresoc.v:72597.3-72648.6" + wire $1\dec19_inv_out[0:0] + attribute \src "libresoc.v:72909.3-72960.6" + wire $1\dec19_is_32b[0:0] + attribute \src "libresoc.v:72285.3-72336.6" + wire width 4 $1\dec19_ldst_len[3:0] + attribute \src "libresoc.v:73013.3-73064.6" + wire $1\dec19_lk[0:0] + attribute \src "libresoc.v:73325.3-73376.6" + wire width 2 $1\dec19_out_sel[1:0] + attribute \src "libresoc.v:72389.3-72440.6" + wire width 2 $1\dec19_rc_sel[1:0] + attribute \src "libresoc.v:72857.3-72908.6" + wire $1\dec19_rsrv[0:0] + attribute \src "libresoc.v:73065.3-73116.6" + wire $1\dec19_sgl_pipe[0:0] + attribute \src "libresoc.v:72961.3-73012.6" + wire $1\dec19_sgn[0:0] + attribute \src "libresoc.v:72753.3-72804.6" + wire $1\dec19_sgn_ext[0:0] + attribute \src "libresoc.v:72337.3-72388.6" + wire width 2 $1\dec19_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec19_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec19_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec19_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec19_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec19_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec19_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec19_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec19_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec19_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec19_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec19_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec19_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec19_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec19_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec19_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec19_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec19_upd + attribute \src "libresoc.v:71976.7-71976.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 10 \opcode_switch + attribute \src "libresoc.v:71976.7-71976.20" + process $proc$libresoc.v:71976$3602 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:72233.3-72284.6" + process $proc$libresoc.v:72233$3578 + assign { } { } + assign { } { } + assign $0\dec19_function_unit[11:0] $1\dec19_function_unit[11:0] + attribute \src "libresoc.v:72234.5-72234.29" + switch \initial + attribute \src "libresoc.v:72234.9-72234.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000010000000 + case + assign $1\dec19_function_unit[11:0] 12'000000000000 + end + sync always + update \dec19_function_unit $0\dec19_function_unit[11:0] + end + attribute \src "libresoc.v:72285.3-72336.6" + process $proc$libresoc.v:72285$3579 + assign { } { } + assign { } { } + assign $0\dec19_ldst_len[3:0] $1\dec19_ldst_len[3:0] + attribute \src "libresoc.v:72286.5-72286.29" + switch \initial + attribute \src "libresoc.v:72286.9-72286.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + case + assign $1\dec19_ldst_len[3:0] 4'0000 + end + sync always + update \dec19_ldst_len $0\dec19_ldst_len[3:0] + end + attribute \src "libresoc.v:72337.3-72388.6" + process $proc$libresoc.v:72337$3580 + assign { } { } + assign { } { } + assign $0\dec19_upd[1:0] $1\dec19_upd[1:0] + attribute \src "libresoc.v:72338.5-72338.29" + switch \initial + attribute \src "libresoc.v:72338.9-72338.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + case + assign $1\dec19_upd[1:0] 2'00 + end + sync always + update \dec19_upd $0\dec19_upd[1:0] + end + attribute \src "libresoc.v:72389.3-72440.6" + process $proc$libresoc.v:72389$3581 + assign { } { } + assign { } { } + assign $0\dec19_rc_sel[1:0] $1\dec19_rc_sel[1:0] + attribute \src "libresoc.v:72390.5-72390.29" + switch \initial + attribute \src "libresoc.v:72390.9-72390.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + case + assign $1\dec19_rc_sel[1:0] 2'00 + end + sync always + update \dec19_rc_sel $0\dec19_rc_sel[1:0] + end + attribute \src "libresoc.v:72441.3-72492.6" + process $proc$libresoc.v:72441$3582 + assign { } { } + assign { } { } + assign $0\dec19_cry_in[1:0] $1\dec19_cry_in[1:0] + attribute \src "libresoc.v:72442.5-72442.29" + switch \initial + attribute \src "libresoc.v:72442.9-72442.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + case + assign $1\dec19_cry_in[1:0] 2'00 + end + sync always + update \dec19_cry_in $0\dec19_cry_in[1:0] + end + attribute \src "libresoc.v:72493.3-72544.6" + process $proc$libresoc.v:72493$3583 + assign { } { } + assign { } { } + assign $0\dec19_asmcode[7:0] $1\dec19_asmcode[7:0] + attribute \src "libresoc.v:72494.5-72494.29" + switch \initial + attribute \src "libresoc.v:72494.9-72494.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'01101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00100101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'01001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'10010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'01001000 + case + assign $1\dec19_asmcode[7:0] 8'00000000 + end + sync always + update \dec19_asmcode $0\dec19_asmcode[7:0] + end + attribute \src "libresoc.v:72545.3-72596.6" + process $proc$libresoc.v:72545$3584 + assign { } { } + assign { } { } + assign $0\dec19_inv_a[0:0] $1\dec19_inv_a[0:0] + attribute \src "libresoc.v:72546.5-72546.29" + switch \initial + attribute \src "libresoc.v:72546.9-72546.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + case + assign $1\dec19_inv_a[0:0] 1'0 + end + sync always + update \dec19_inv_a $0\dec19_inv_a[0:0] + end + attribute \src "libresoc.v:72597.3-72648.6" + process $proc$libresoc.v:72597$3585 + assign { } { } + assign { } { } + assign $0\dec19_inv_out[0:0] $1\dec19_inv_out[0:0] + attribute \src "libresoc.v:72598.5-72598.29" + switch \initial + attribute \src "libresoc.v:72598.9-72598.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + case + assign $1\dec19_inv_out[0:0] 1'0 + end + sync always + update \dec19_inv_out $0\dec19_inv_out[0:0] + end + attribute \src "libresoc.v:72649.3-72700.6" + process $proc$libresoc.v:72649$3586 + assign { } { } + assign { } { } + assign $0\dec19_cry_out[0:0] $1\dec19_cry_out[0:0] + attribute \src "libresoc.v:72650.5-72650.29" + switch \initial + attribute \src "libresoc.v:72650.9-72650.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + case + assign $1\dec19_cry_out[0:0] 1'0 + end + sync always + update \dec19_cry_out $0\dec19_cry_out[0:0] + end + attribute \src "libresoc.v:72701.3-72752.6" + process $proc$libresoc.v:72701$3587 + assign { } { } + assign { } { } + assign $0\dec19_br[0:0] $1\dec19_br[0:0] + attribute \src "libresoc.v:72702.5-72702.29" + switch \initial + attribute \src "libresoc.v:72702.9-72702.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + case + assign $1\dec19_br[0:0] 1'0 + end + sync always + update \dec19_br $0\dec19_br[0:0] + end + attribute \src "libresoc.v:72753.3-72804.6" + process $proc$libresoc.v:72753$3588 + assign { } { } + assign { } { } + assign $0\dec19_sgn_ext[0:0] $1\dec19_sgn_ext[0:0] + attribute \src "libresoc.v:72754.5-72754.29" + switch \initial + attribute \src "libresoc.v:72754.9-72754.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + case + assign $1\dec19_sgn_ext[0:0] 1'0 + end + sync always + update \dec19_sgn_ext $0\dec19_sgn_ext[0:0] + end + attribute \src "libresoc.v:72805.3-72856.6" + process $proc$libresoc.v:72805$3589 + assign { } { } + assign { } { } + assign $0\dec19_internal_op[6:0] $1\dec19_internal_op[6:0] + attribute \src "libresoc.v:72806.5-72806.29" + switch \initial + attribute \src "libresoc.v:72806.9-72806.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000110 + case + assign $1\dec19_internal_op[6:0] 7'0000000 + end + sync always + update \dec19_internal_op $0\dec19_internal_op[6:0] + end + attribute \src "libresoc.v:72857.3-72908.6" + process $proc$libresoc.v:72857$3590 + assign { } { } + assign { } { } + assign $0\dec19_rsrv[0:0] $1\dec19_rsrv[0:0] + attribute \src "libresoc.v:72858.5-72858.29" + switch \initial + attribute \src "libresoc.v:72858.9-72858.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + case + assign $1\dec19_rsrv[0:0] 1'0 + end + sync always + update \dec19_rsrv $0\dec19_rsrv[0:0] + end + attribute \src "libresoc.v:72909.3-72960.6" + process $proc$libresoc.v:72909$3591 + assign { } { } + assign { } { } + assign $0\dec19_is_32b[0:0] $1\dec19_is_32b[0:0] + attribute \src "libresoc.v:72910.5-72910.29" + switch \initial + attribute \src "libresoc.v:72910.9-72910.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + case + assign $1\dec19_is_32b[0:0] 1'0 + end + sync always + update \dec19_is_32b $0\dec19_is_32b[0:0] + end + attribute \src "libresoc.v:72961.3-73012.6" + process $proc$libresoc.v:72961$3592 + assign { } { } + assign { } { } + assign $0\dec19_sgn[0:0] $1\dec19_sgn[0:0] + attribute \src "libresoc.v:72962.5-72962.29" + switch \initial + attribute \src "libresoc.v:72962.9-72962.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + case + assign $1\dec19_sgn[0:0] 1'0 + end + sync always + update \dec19_sgn $0\dec19_sgn[0:0] + end + attribute \src "libresoc.v:73013.3-73064.6" + process $proc$libresoc.v:73013$3593 + assign { } { } + assign { } { } + assign $0\dec19_lk[0:0] $1\dec19_lk[0:0] + attribute \src "libresoc.v:73014.5-73014.29" + switch \initial + attribute \src "libresoc.v:73014.9-73014.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + case + assign $1\dec19_lk[0:0] 1'0 + end + sync always + update \dec19_lk $0\dec19_lk[0:0] + end + attribute \src "libresoc.v:73065.3-73116.6" + process $proc$libresoc.v:73065$3594 + assign { } { } + assign { } { } + assign $0\dec19_sgl_pipe[0:0] $1\dec19_sgl_pipe[0:0] + attribute \src "libresoc.v:73066.5-73066.29" + switch \initial + attribute \src "libresoc.v:73066.9-73066.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + case + assign $1\dec19_sgl_pipe[0:0] 1'0 + end + sync always + update \dec19_sgl_pipe $0\dec19_sgl_pipe[0:0] + end + attribute \src "libresoc.v:73117.3-73168.6" + process $proc$libresoc.v:73117$3595 + assign { } { } + assign { } { } + assign $0\dec19_form[4:0] $1\dec19_form[4:0] + attribute \src "libresoc.v:73118.5-73118.29" + switch \initial + attribute \src "libresoc.v:73118.9-73118.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + case + assign $1\dec19_form[4:0] 5'00000 + end + sync always + update \dec19_form $0\dec19_form[4:0] + end + attribute \src "libresoc.v:73169.3-73220.6" + process $proc$libresoc.v:73169$3596 + assign { } { } + assign { } { } + assign $0\dec19_in1_sel[2:0] $1\dec19_in1_sel[2:0] + attribute \src "libresoc.v:73170.5-73170.29" + switch \initial + attribute \src "libresoc.v:73170.9-73170.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + case + assign $1\dec19_in1_sel[2:0] 3'000 + end + sync always + update \dec19_in1_sel $0\dec19_in1_sel[2:0] + end + attribute \src "libresoc.v:73221.3-73272.6" + process $proc$libresoc.v:73221$3597 + assign { } { } + assign { } { } + assign $0\dec19_in2_sel[3:0] $1\dec19_in2_sel[3:0] + attribute \src "libresoc.v:73222.5-73222.29" + switch \initial + attribute \src "libresoc.v:73222.9-73222.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + case + assign $1\dec19_in2_sel[3:0] 4'0000 + end + sync always + update \dec19_in2_sel $0\dec19_in2_sel[3:0] + end + attribute \src "libresoc.v:73273.3-73324.6" + process $proc$libresoc.v:73273$3598 + assign { } { } + assign { } { } + assign $0\dec19_in3_sel[1:0] $1\dec19_in3_sel[1:0] + attribute \src "libresoc.v:73274.5-73274.29" + switch \initial + attribute \src "libresoc.v:73274.9-73274.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + case + assign $1\dec19_in3_sel[1:0] 2'00 + end + sync always + update \dec19_in3_sel $0\dec19_in3_sel[1:0] + end + attribute \src "libresoc.v:73325.3-73376.6" + process $proc$libresoc.v:73325$3599 + assign { } { } + assign { } { } + assign $0\dec19_out_sel[1:0] $1\dec19_out_sel[1:0] + attribute \src "libresoc.v:73326.5-73326.29" + switch \initial + attribute \src "libresoc.v:73326.9-73326.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + case + assign $1\dec19_out_sel[1:0] 2'00 + end + sync always + update \dec19_out_sel $0\dec19_out_sel[1:0] + end + attribute \src "libresoc.v:73377.3-73428.6" + process $proc$libresoc.v:73377$3600 + assign { } { } + assign { } { } + assign $0\dec19_cr_in[2:0] $1\dec19_cr_in[2:0] + attribute \src "libresoc.v:73378.5-73378.29" + switch \initial + attribute \src "libresoc.v:73378.9-73378.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'000 + case + assign $1\dec19_cr_in[2:0] 3'000 + end + sync always + update \dec19_cr_in $0\dec19_cr_in[2:0] + end + attribute \src "libresoc.v:73429.3-73480.6" + process $proc$libresoc.v:73429$3601 + assign { } { } + assign { } { } + assign $0\dec19_cr_out[2:0] $1\dec19_cr_out[2:0] + attribute \src "libresoc.v:73430.5-73430.29" + switch \initial + attribute \src "libresoc.v:73430.9-73430.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + case + assign $1\dec19_cr_out[2:0] 3'000 + end + sync always + update \dec19_cr_out $0\dec19_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:73486.1-75523.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2" +attribute \generator "nMigen" +module \dec2 + attribute \src "libresoc.v:75297.3-75454.6" + wire width 8 $0\asmcode[7:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 64 $0\cia[63:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $0\cr_in1[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $0\cr_in1_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $0\cr_in2$1[2:0]$3621 + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $0\cr_in2[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $0\cr_in2_ok$2[0:0]$3622 + attribute \src "libresoc.v:75297.3-75454.6" + wire $0\cr_in2_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $0\cr_out[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $0\cr_out_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 8 $0\cr_rd[7:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $0\cr_rd_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 8 $0\cr_wr[7:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $0\cr_wr_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 5 $0\ea[4:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $0\ea_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $0\exc_$signal$3[0:0]$3624 + attribute \src "libresoc.v:75297.3-75454.6" + wire $0\exc_$signal$4[0:0]$3625 + attribute \src "libresoc.v:75297.3-75454.6" + wire $0\exc_$signal$5[0:0]$3626 + attribute \src "libresoc.v:75297.3-75454.6" + wire $0\exc_$signal$6[0:0]$3627 + attribute \src "libresoc.v:75297.3-75454.6" + wire $0\exc_$signal$7[0:0]$3628 + attribute \src "libresoc.v:75297.3-75454.6" + wire $0\exc_$signal$8[0:0]$3629 + attribute \src "libresoc.v:75297.3-75454.6" + wire $0\exc_$signal$9[0:0]$3630 + attribute \src "libresoc.v:75297.3-75454.6" + wire $0\exc_$signal[0:0]$3623 + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $0\fast1[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $0\fast1_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $0\fast2[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $0\fast2_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $0\fasto1[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $0\fasto1_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $0\fasto2[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $0\fasto2_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 12 $0\fn_unit[11:0] + attribute \src "libresoc.v:73487.7-73487.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 2 $0\input_carry[1:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 32 $0\insn[31:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 7 $0\insn_type[6:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $0\is_32bit[0:0] + attribute \src "libresoc.v:75277.3-75296.6" + wire $0\is_priv_insn[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $0\lk[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 64 $0\msr[63:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 5 $0\reg1[4:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $0\reg1_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 5 $0\reg2[4:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $0\reg2_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 5 $0\reg3[4:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $0\reg3_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 5 $0\rego[4:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $0\rego_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 10 $0\spr1[9:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $0\spr1_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 10 $0\spro[9:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $0\spro_ok[0:0] + attribute \src "libresoc.v:75231.3-75240.6" + wire $0\tmp_tmp_lk[0:0] + attribute \src "libresoc.v:75267.3-75276.6" + wire width 13 $0\tmp_tmp_trapaddr[12:0] + attribute \src "libresoc.v:75241.3-75256.6" + wire width 3 $0\tmp_xer_in[2:0] + attribute \src "libresoc.v:75257.3-75266.6" + wire $0\tmp_xer_out[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 13 $0\trapaddr[12:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 8 $0\traptype[7:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $0\xer_in[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $0\xer_out[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 8 $1\asmcode[7:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 64 $1\cia[63:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $1\cr_in1[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $1\cr_in1_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $1\cr_in2$1[2:0]$3631 + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $1\cr_in2[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $1\cr_in2_ok$2[0:0]$3632 + attribute \src "libresoc.v:75297.3-75454.6" + wire $1\cr_in2_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $1\cr_out[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $1\cr_out_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 8 $1\cr_rd[7:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $1\cr_rd_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 8 $1\cr_wr[7:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $1\cr_wr_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 5 $1\ea[4:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $1\ea_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $1\exc_$signal$3[0:0]$3634 + attribute \src "libresoc.v:75297.3-75454.6" + wire $1\exc_$signal$4[0:0]$3635 + attribute \src "libresoc.v:75297.3-75454.6" + wire $1\exc_$signal$5[0:0]$3636 + attribute \src "libresoc.v:75297.3-75454.6" + wire $1\exc_$signal$6[0:0]$3637 + attribute \src "libresoc.v:75297.3-75454.6" + wire $1\exc_$signal$7[0:0]$3638 + attribute \src "libresoc.v:75297.3-75454.6" + wire $1\exc_$signal$8[0:0]$3639 + attribute \src "libresoc.v:75297.3-75454.6" + wire $1\exc_$signal$9[0:0]$3640 + attribute \src "libresoc.v:75297.3-75454.6" + wire $1\exc_$signal[0:0]$3633 + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $1\fast1[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $1\fast1_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $1\fast2[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $1\fast2_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $1\fasto1[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $1\fasto1_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $1\fasto2[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $1\fasto2_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 12 $1\fn_unit[11:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 2 $1\input_carry[1:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 32 $1\insn[31:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 7 $1\insn_type[6:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $1\is_32bit[0:0] + attribute \src "libresoc.v:75277.3-75296.6" + wire $1\is_priv_insn[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $1\lk[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 64 $1\msr[63:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $1\rc_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 5 $1\reg1[4:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $1\reg1_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 5 $1\reg2[4:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $1\reg2_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 5 $1\reg3[4:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $1\reg3_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 5 $1\rego[4:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $1\rego_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 10 $1\spr1[9:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $1\spr1_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 10 $1\spro[9:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $1\spro_ok[0:0] + attribute \src "libresoc.v:75231.3-75240.6" + wire $1\tmp_tmp_lk[0:0] + attribute \src "libresoc.v:75267.3-75276.6" + wire width 13 $1\tmp_tmp_trapaddr[12:0] + attribute \src "libresoc.v:75241.3-75256.6" + wire width 3 $1\tmp_xer_in[2:0] + attribute \src "libresoc.v:75257.3-75266.6" + wire $1\tmp_xer_out[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 13 $1\trapaddr[12:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 8 $1\traptype[7:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $1\xer_in[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $1\xer_out[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 8 $2\asmcode[7:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 64 $2\cia[63:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $2\cr_in1[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $2\cr_in1_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $2\cr_in2$1[2:0]$3641 + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $2\cr_in2[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $2\cr_in2_ok$2[0:0]$3642 + attribute \src "libresoc.v:75297.3-75454.6" + wire $2\cr_in2_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $2\cr_out[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $2\cr_out_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 8 $2\cr_rd[7:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $2\cr_rd_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 8 $2\cr_wr[7:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $2\cr_wr_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 5 $2\ea[4:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $2\ea_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $2\exc_$signal$3[0:0]$3644 + attribute \src "libresoc.v:75297.3-75454.6" + wire $2\exc_$signal$4[0:0]$3645 + attribute \src "libresoc.v:75297.3-75454.6" + wire $2\exc_$signal$5[0:0]$3646 + attribute \src "libresoc.v:75297.3-75454.6" + wire $2\exc_$signal$6[0:0]$3647 + attribute \src "libresoc.v:75297.3-75454.6" + wire $2\exc_$signal$7[0:0]$3648 + attribute \src "libresoc.v:75297.3-75454.6" + wire $2\exc_$signal$8[0:0]$3649 + attribute \src "libresoc.v:75297.3-75454.6" + wire $2\exc_$signal$9[0:0]$3650 + attribute \src "libresoc.v:75297.3-75454.6" + wire $2\exc_$signal[0:0]$3643 + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $2\fast1[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $2\fast1_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $2\fast2[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $2\fast2_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $2\fasto1[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $2\fasto1_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $2\fasto2[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $2\fasto2_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 12 $2\fn_unit[11:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 2 $2\input_carry[1:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 32 $2\insn[31:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 7 $2\insn_type[6:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $2\is_32bit[0:0] + attribute \src "libresoc.v:75277.3-75296.6" + wire $2\is_priv_insn[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $2\lk[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 64 $2\msr[63:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $2\oe_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $2\rc[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $2\rc_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 5 $2\reg1[4:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $2\reg1_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 5 $2\reg2[4:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $2\reg2_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 5 $2\reg3[4:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $2\reg3_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 5 $2\rego[4:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $2\rego_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 10 $2\spr1[9:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $2\spr1_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 10 $2\spro[9:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $2\spro_ok[0:0] + attribute \src "libresoc.v:75241.3-75256.6" + wire width 3 $2\tmp_xer_in[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 13 $2\trapaddr[12:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 8 $2\traptype[7:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $2\xer_in[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $2\xer_out[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 8 $3\asmcode[7:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 64 $3\cia[63:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $3\cr_in1[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $3\cr_in1_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $3\cr_in2$1[2:0]$3651 + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $3\cr_in2[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $3\cr_in2_ok$2[0:0]$3652 + attribute \src "libresoc.v:75297.3-75454.6" + wire $3\cr_in2_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $3\cr_out[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $3\cr_out_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 8 $3\cr_rd[7:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $3\cr_rd_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 8 $3\cr_wr[7:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $3\cr_wr_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 5 $3\ea[4:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $3\ea_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $3\exc_$signal$3[0:0]$3654 + attribute \src "libresoc.v:75297.3-75454.6" + wire $3\exc_$signal$4[0:0]$3655 + attribute \src "libresoc.v:75297.3-75454.6" + wire $3\exc_$signal$5[0:0]$3656 + attribute \src "libresoc.v:75297.3-75454.6" + wire $3\exc_$signal$6[0:0]$3657 + attribute \src "libresoc.v:75297.3-75454.6" + wire $3\exc_$signal$7[0:0]$3658 + attribute \src "libresoc.v:75297.3-75454.6" + wire $3\exc_$signal$8[0:0]$3659 + attribute \src "libresoc.v:75297.3-75454.6" + wire $3\exc_$signal$9[0:0]$3660 + attribute \src "libresoc.v:75297.3-75454.6" + wire $3\exc_$signal[0:0]$3653 + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $3\fast1[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $3\fast1_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $3\fast2[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $3\fast2_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $3\fasto1[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $3\fasto1_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $3\fasto2[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $3\fasto2_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 12 $3\fn_unit[11:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 2 $3\input_carry[1:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 32 $3\insn[31:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 7 $3\insn_type[6:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $3\is_32bit[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $3\lk[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 64 $3\msr[63:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $3\oe[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $3\oe_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $3\rc[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $3\rc_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 5 $3\reg1[4:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $3\reg1_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 5 $3\reg2[4:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $3\reg2_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 5 $3\reg3[4:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $3\reg3_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 5 $3\rego[4:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $3\rego_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 10 $3\spr1[9:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $3\spr1_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 10 $3\spro[9:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $3\spro_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 13 $3\trapaddr[12:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 8 $3\traptype[7:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $3\xer_in[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $3\xer_out[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 8 $4\asmcode[7:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 64 $4\cia[63:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $4\cr_in1[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $4\cr_in1_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $4\cr_in2$1[2:0]$3661 + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $4\cr_in2[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $4\cr_in2_ok$2[0:0]$3662 + attribute \src "libresoc.v:75297.3-75454.6" + wire $4\cr_in2_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $4\cr_out[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $4\cr_out_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 8 $4\cr_rd[7:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $4\cr_rd_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 8 $4\cr_wr[7:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $4\cr_wr_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 5 $4\ea[4:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $4\ea_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $4\exc_$signal$3[0:0]$3664 + attribute \src "libresoc.v:75297.3-75454.6" + wire $4\exc_$signal$4[0:0]$3665 + attribute \src "libresoc.v:75297.3-75454.6" + wire $4\exc_$signal$5[0:0]$3666 + attribute \src "libresoc.v:75297.3-75454.6" + wire $4\exc_$signal$6[0:0]$3667 + attribute \src "libresoc.v:75297.3-75454.6" + wire $4\exc_$signal$7[0:0]$3668 + attribute \src "libresoc.v:75297.3-75454.6" + wire $4\exc_$signal$8[0:0]$3669 + attribute \src "libresoc.v:75297.3-75454.6" + wire $4\exc_$signal$9[0:0]$3670 + attribute \src "libresoc.v:75297.3-75454.6" + wire $4\exc_$signal[0:0]$3663 + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $4\fast1[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $4\fast1_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 3 $4\fast2[2:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire $4\fast2_ok[0:0] + attribute \src "libresoc.v:75297.3-75454.6" + wire width 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec_out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec_rc_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + wire width 2 \dec_rc_sel_in + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 output 8 \ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 9 \ea_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 50 \exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 51 \exc_$signal$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 52 \exc_$signal$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 53 \exc_$signal$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 54 \exc_$signal$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 55 \exc_$signal$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 56 \exc_$signal$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 57 \exc_$signal$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:903" + wire \ext_irq_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 22 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 23 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 24 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 25 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 26 \fasto1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 27 \fasto1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 28 \fasto2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 29 \fasto2_ok + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + wire width 12 output 42 \fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:906" + wire \illeg_ok + attribute \src "libresoc.v:73487.7-73487.15" + wire \initial + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + wire width 2 output 48 \input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + wire width 32 output 40 \insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" + wire width 32 \insn_in$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89" + wire width 32 \insn_in$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" + wire width 32 \insn_in$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:283" + wire width 32 \insn_in$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:312" + wire width 32 \insn_in$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:367" + wire width 32 \insn_in$41 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 7 output 41 \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" + wire output 63 \is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:44" + wire \is_priv_insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" + wire output 43 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + wire width 64 output 38 \msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 46 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 47 \oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:905" + wire \priv_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + wire width 32 input 4 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 44 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 45 \rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 output 10 \reg1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 11 \reg1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 output 12 \reg2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 13 \reg2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 output 14 \reg3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 15 \reg3_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 output 6 \rego + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 7 \rego_ok + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + wire width 2 \sel_in + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 output 18 \spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 19 \spr1_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 output 16 \spro + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 17 \spro_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" + wire width 8 \tmp_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \tmp_cr_in1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_cr_in1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \tmp_cr_in2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \tmp_cr_in2$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_cr_in2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_cr_in2_ok$20 + attribute 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"OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 7 \tmp_tmp_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" + wire \tmp_tmp_is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" + wire \tmp_tmp_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + wire width 64 \tmp_tmp_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_tmp_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_tmp_oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_tmp_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_tmp_rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" + wire width 13 \tmp_tmp_trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 8 \tmp_tmp_traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104" + wire width 3 \tmp_xer_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" + wire \tmp_xer_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" + wire width 13 output 58 \trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 8 output 49 \traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104" + wire width 3 output 20 \xer_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" + wire output 21 \xer_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:909" + cell $and $and$libresoc.v:75086$3611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cur_eint + connect \B \cur_msr [15] + connect \Y $and$libresoc.v:75086$3611_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:910" + cell $and $and$libresoc.v:75087$3612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cur_dec [63] + connect \B \cur_msr [15] + connect \Y $and$libresoc.v:75087$3612_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:911" + cell $and $and$libresoc.v:75088$3613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_priv_insn + connect \B \cur_msr [14] + connect \Y $and$libresoc.v:75088$3613_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:960" + cell $eq $eq$libresoc.v:75078$3603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'0111111 + connect \Y $eq$libresoc.v:75078$3603_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:961" + cell $eq $eq$libresoc.v:75079$3604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'1001001 + connect \Y $eq$libresoc.v:75079$3604_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:970" + cell $eq $eq$libresoc.v:75081$3606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'1000110 + connect \Y $eq$libresoc.v:75081$3606_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:878" + cell $eq $eq$libresoc.v:75082$3607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0101110 + connect \Y $eq$libresoc.v:75082$3607_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:880" + cell $eq $eq$libresoc.v:75083$3608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0001010 + connect \Y $eq$libresoc.v:75083$3608_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:882" + cell $eq $eq$libresoc.v:75084$3609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:75084$3609_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:886" + cell $eq $eq$libresoc.v:75085$3610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0111111 + connect \Y $eq$libresoc.v:75085$3610_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:912" + cell $eq $eq$libresoc.v:75089$3614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0000000 + connect \Y $eq$libresoc.v:75089$3614_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:961" + cell $or $or$libresoc.v:75080$3605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \B \$30 + connect \Y $or$libresoc.v:75080$3605_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:75090.13-75127.4" + cell \dec$205 \dec + connect \BA \dec_BA + connect \BB \dec_BB + connect \BC \dec_BC + connect \BI \dec_BI + connect \BO \dec_BO + connect \BT \dec_BT + connect \FXM \dec_FXM + connect \LK \dec_LK + connect \OE \dec_OE + connect \RA \dec_RA + connect \RB \dec_RB + connect \RS \dec_RS + connect \RT \dec_RT + connect \Rc \dec_Rc + connect \SPR \dec_SPR + connect \XL_BT \dec_XL_BT + connect \XL_XO \dec_XL_XO + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \asmcode \dec_asmcode + connect \bigendian \bigendian + connect \cr_in \dec_cr_in + connect \cr_out \dec_cr_out + connect \cry_in \dec_cry_in + connect \function_unit \dec_function_unit + connect \in1_sel \dec_in1_sel + connect \in2_sel \dec_in2_sel + connect \in3_sel \dec_in3_sel + connect \internal_op \dec_internal_op + connect \is_32b \dec_is_32b + connect \lk \dec_lk + connect \opcode_in \dec_opcode_in + connect \out_sel \dec_out_sel + connect \raw_opcode_in \raw_opcode_in + connect \rc_sel \dec_rc_sel + connect \upd \dec_upd + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:75128.9-75142.4" + cell \dec_a \dec_a + connect \BO \dec_BO + connect \RA \dec_RA + connect \RS \dec_RS + connect \SPR \dec_SPR + connect \XL_XO \dec_XL_XO + connect \fast_a \dec_a_fast_a + connect \fast_a_ok \dec_a_fast_a_ok + connect \internal_op \dec_internal_op + connect \reg_a \dec_a_reg_a + connect \reg_a_ok \dec_a_reg_a_ok + connect \sel_in \dec_a_sel_in + connect \spr_a \dec_a_spr_a + connect \spr_a_ok \dec_a_spr_a_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:75143.9-75153.4" + cell \dec_b \dec_b + connect \RB \dec_RB + connect \RS \dec_RS + connect \XL_XO \dec_XL_XO + connect \fast_b \dec_b_fast_b + connect \fast_b_ok \dec_b_fast_b_ok + connect \internal_op \dec_internal_op + connect \reg_b \dec_b_reg_b + connect \reg_b_ok \dec_b_reg_b_ok + connect \sel_in \dec_b_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:75154.9-75160.4" + cell \dec_c \dec_c + connect \RB \dec_RB + connect \RS \dec_RS + connect \reg_c \dec_c_reg_c + connect \reg_c_ok \dec_c_reg_c_ok + connect \sel_in \dec_c_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:75161.19-75180.4" + cell \dec_cr_in$208 \dec_cr_in$10 + connect \BA \dec_BA + connect \BB \dec_BB + connect \BC \dec_BC + connect \BI \dec_BI + connect \BT \dec_BT + connect \FXM \dec_FXM + connect \X_BFA \dec_X_BFA + connect \cr_bitfield \dec_cr_in_cr_bitfield + connect \cr_bitfield_b \dec_cr_in_cr_bitfield_b + connect \cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b_ok + connect \cr_bitfield_o \dec_cr_in_cr_bitfield_o + connect \cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o_ok + connect \cr_bitfield_ok \dec_cr_in_cr_bitfield_ok + connect \cr_fxm \dec_cr_in_cr_fxm + connect \cr_fxm_ok \dec_cr_in_cr_fxm_ok + connect \insn_in \dec_cr_in_insn_in + connect \internal_op \dec_internal_op + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:75181.20-75193.4" + cell \dec_cr_out$210 \dec_cr_out$11 + connect \FXM \dec_FXM + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \cr_bitfield \dec_cr_out_cr_bitfield + connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok + connect \cr_fxm \dec_cr_out_cr_fxm + connect \cr_fxm_ok \dec_cr_out_cr_fxm_ok + connect \insn_in \dec_cr_out_insn_in + connect \internal_op \dec_internal_op + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:75194.9-75207.4" + cell \dec_o \dec_o + connect \BO \dec_BO + connect \RA \dec_RA + connect \RT \dec_RT + connect \SPR \dec_SPR + connect \fast_o \dec_o_fast_o + connect \fast_o_ok \dec_o_fast_o_ok + connect \internal_op \dec_internal_op + connect \reg_o \dec_o_reg_o + connect \reg_o_ok \dec_o_reg_o_ok + connect \sel_in \dec_o_sel_in + connect \spr_o \dec_o_spr_o + connect \spr_o_ok \dec_o_spr_o_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:75208.10-75217.4" + cell \dec_o2 \dec_o2 + connect \RA \dec_RA + connect \fast_o \dec_o2_fast_o + connect \fast_o_ok \dec_o2_fast_o_ok + connect \internal_op \dec_internal_op + connect \lk \dec_o2_lk + connect \reg_o \dec_o2_reg_o + connect \reg_o_ok \dec_o2_reg_o_ok + connect \upd \dec_upd + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:75218.16-75224.4" + cell \dec_oe$207 \dec_oe + connect \OE \dec_OE + connect \internal_op \dec_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:75225.16-75230.4" + cell \dec_rc$206 \dec_rc + connect \Rc \dec_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + attribute \src "libresoc.v:73487.7-73487.20" + process $proc$libresoc.v:73487$3671 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:75231.3-75240.6" + process $proc$libresoc.v:75231$3615 + assign { } { } + assign { } { } + assign $0\tmp_tmp_lk[0:0] $1\tmp_tmp_lk[0:0] + attribute \src "libresoc.v:75232.5-75232.29" + switch \initial + attribute \src "libresoc.v:75232.9-75232.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:762" + switch \dec_lk + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_tmp_lk[0:0] \dec_LK + case + assign $1\tmp_tmp_lk[0:0] 1'0 + end + sync always + update \tmp_tmp_lk $0\tmp_tmp_lk[0:0] + end + attribute \src "libresoc.v:75241.3-75256.6" + process $proc$libresoc.v:75241$3616 + assign { } { } + assign { } { } + assign { } { } + assign $0\tmp_xer_in[2:0] $2\tmp_xer_in[2:0] + attribute \src "libresoc.v:75242.5-75242.29" + switch \initial + attribute \src "libresoc.v:75242.9-75242.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:878" + switch \$42 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_xer_in[2:0] 3'111 + case + assign $1\tmp_xer_in[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:880" + switch \$44 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\tmp_xer_in[2:0] 3'001 + case + assign $2\tmp_xer_in[2:0] $1\tmp_xer_in[2:0] + end + sync always + update \tmp_xer_in $0\tmp_xer_in[2:0] + end + attribute \src "libresoc.v:75257.3-75266.6" + process $proc$libresoc.v:75257$3617 + assign { } { } + assign { } { } + assign $0\tmp_xer_out[0:0] $1\tmp_xer_out[0:0] + attribute \src "libresoc.v:75258.5-75258.29" + switch \initial + attribute \src "libresoc.v:75258.9-75258.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:882" + switch \$46 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_xer_out[0:0] 1'1 + case + assign $1\tmp_xer_out[0:0] 1'0 + end + sync always + update \tmp_xer_out $0\tmp_xer_out[0:0] + end + attribute \src "libresoc.v:75267.3-75276.6" + process $proc$libresoc.v:75267$3618 + assign { } { } + assign { } { } + assign $0\tmp_tmp_trapaddr[12:0] $1\tmp_tmp_trapaddr[12:0] + attribute \src "libresoc.v:75268.5-75268.29" + switch \initial + attribute \src "libresoc.v:75268.9-75268.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:886" + switch \$48 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_tmp_trapaddr[12:0] 13'0000001110000 + case + assign $1\tmp_tmp_trapaddr[12:0] 13'0000000000000 + end + sync always + update \tmp_tmp_trapaddr $0\tmp_tmp_trapaddr[12:0] + end + attribute \src "libresoc.v:75277.3-75296.6" + process $proc$libresoc.v:75277$3619 + assign { } { } + assign { } { } + assign $0\is_priv_insn[0:0] $1\is_priv_insn[0:0] + attribute \src "libresoc.v:75278.5-75278.29" + switch \initial + attribute \src "libresoc.v:75278.9-75278.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:45" + switch \dec_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 , 7'1000111 , 7'1001000 , 7'1001010 , 7'1000110 + assign { } { } + assign $1\is_priv_insn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0101110 , 7'0110001 + assign { } { } + assign $1\is_priv_insn[0:0] $2\is_priv_insn[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:52" + switch \tmp_tmp_insn [20] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\is_priv_insn[0:0] 1'1 + case + assign $2\is_priv_insn[0:0] 1'0 + end + case + assign $1\is_priv_insn[0:0] 1'0 + end + sync always + update \is_priv_insn $0\is_priv_insn[0:0] + end + attribute \src "libresoc.v:75297.3-75454.6" + process $proc$libresoc.v:75297$3620 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + assign $0\spr1[9:0] $1\spr1[9:0] + assign $0\spr1_ok[0:0] $1\spr1_ok[0:0] + assign $0\msr[63:0] $1\msr[63:0] + assign $0\ea_ok[0:0] $1\ea_ok[0:0] + assign $0\ea[4:0] $1\ea[4:0] + assign { } { } + assign $0\cr_out[2:0] $1\cr_out[2:0] + assign $0\lk[0:0] $1\lk[0:0] + assign $0\cia[63:0] $1\cia[63:0] + assign $0\cr_in1[2:0] $1\cr_in1[2:0] + assign $0\cr_in1_ok[0:0] $1\cr_in1_ok[0:0] + assign $0\cr_in2[2:0] $1\cr_in2[2:0] + assign $0\cr_in2$1[2:0]$3621 $1\cr_in2$1[2:0]$3631 + assign $0\cr_in2_ok[0:0] $1\cr_in2_ok[0:0] + assign $0\cr_in2_ok$2[0:0]$3622 $1\cr_in2_ok$2[0:0]$3632 + assign $0\cr_out_ok[0:0] $1\cr_out_ok[0:0] + assign $0\cr_rd[7:0] $1\cr_rd[7:0] + assign $0\cr_rd_ok[0:0] $1\cr_rd_ok[0:0] + assign $0\cr_wr[7:0] $1\cr_wr[7:0] + assign $0\cr_wr_ok[0:0] $1\cr_wr_ok[0:0] + assign $0\exc_$signal[0:0]$3623 $1\exc_$signal[0:0]$3633 + assign $0\exc_$signal$3[0:0]$3624 $1\exc_$signal$3[0:0]$3634 + assign $0\exc_$signal$4[0:0]$3625 $1\exc_$signal$4[0:0]$3635 + assign $0\exc_$signal$5[0:0]$3626 $1\exc_$signal$5[0:0]$3636 + assign $0\exc_$signal$6[0:0]$3627 $1\exc_$signal$6[0:0]$3637 + assign $0\exc_$signal$7[0:0]$3628 $1\exc_$signal$7[0:0]$3638 + assign $0\exc_$signal$8[0:0]$3629 $1\exc_$signal$8[0:0]$3639 + assign $0\exc_$signal$9[0:0]$3630 $1\exc_$signal$9[0:0]$3640 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fn_unit[11:0] $1\fn_unit[11:0] + assign $0\input_carry[1:0] $1\input_carry[1:0] + assign $0\insn[31:0] $1\insn[31:0] + assign $0\insn_type[6:0] $1\insn_type[6:0] + assign $0\is_32bit[0:0] $1\is_32bit[0:0] + assign $0\oe[0:0] $1\oe[0:0] + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + assign $0\reg1[4:0] $1\reg1[4:0] + assign $0\reg1_ok[0:0] $1\reg1_ok[0:0] + assign $0\reg2[4:0] $1\reg2[4:0] + assign $0\reg2_ok[0:0] $1\reg2_ok[0:0] + assign $0\reg3[4:0] $1\reg3[4:0] + assign $0\reg3_ok[0:0] $1\reg3_ok[0:0] + assign $0\rego[4:0] $1\rego[4:0] + assign $0\rego_ok[0:0] $1\rego_ok[0:0] + assign $0\spro[9:0] $1\spro[9:0] + assign $0\spro_ok[0:0] $1\spro_ok[0:0] + assign $0\trapaddr[12:0] $1\trapaddr[12:0] + assign $0\traptype[7:0] $1\traptype[7:0] + assign $0\xer_in[2:0] $1\xer_in[2:0] + assign $0\xer_out[0:0] $1\xer_out[0:0] + assign $0\fasto1[2:0] $5\fasto1[2:0] + assign $0\fasto1_ok[0:0] $5\fasto1_ok[0:0] + assign $0\fasto2[2:0] $5\fasto2[2:0] + assign $0\fasto2_ok[0:0] $5\fasto2_ok[0:0] + assign $0\fast1[2:0] $5\fast1[2:0] + assign $0\fast1_ok[0:0] $5\fast1_ok[0:0] + assign $0\fast2[2:0] $5\fast2[2:0] + assign $0\fast2_ok[0:0] $5\fast2_ok[0:0] + assign $0\asmcode[7:0] \dec_asmcode + attribute \src "libresoc.v:75298.5-75298.29" + switch \initial + attribute \src "libresoc.v:75298.9-75298.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:916" + switch { \illeg_ok \priv_ok \ext_irq_ok \dec_irq_ok \dec2_exc_$signal } + attribute \src "libresoc.v:0.0-0.0" + case 5'----1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\fast1[2:0] $2\fast1[2:0] + assign $1\fast1_ok[0:0] $2\fast1_ok[0:0] + assign $1\fast2[2:0] $2\fast2[2:0] + assign $1\fast2_ok[0:0] $2\fast2_ok[0:0] + assign $1\rc[0:0] $2\rc[0:0] + assign $1\spr1[9:0] $2\spr1[9:0] + assign $1\spr1_ok[0:0] $2\spr1_ok[0:0] + assign $1\msr[63:0] $2\msr[63:0] + assign $1\ea_ok[0:0] $2\ea_ok[0:0] + assign $1\ea[4:0] $2\ea[4:0] + assign $1\asmcode[7:0] $2\asmcode[7:0] + assign $1\cr_out[2:0] $2\cr_out[2:0] + assign $1\lk[0:0] $2\lk[0:0] + assign $1\cia[63:0] $2\cia[63:0] + assign $1\cr_in1[2:0] $2\cr_in1[2:0] + assign $1\cr_in1_ok[0:0] $2\cr_in1_ok[0:0] + assign $1\cr_in2[2:0] $2\cr_in2[2:0] + assign $1\cr_in2$1[2:0]$3631 $2\cr_in2$1[2:0]$3641 + assign $1\cr_in2_ok[0:0] $2\cr_in2_ok[0:0] + assign $1\cr_in2_ok$2[0:0]$3632 $2\cr_in2_ok$2[0:0]$3642 + assign $1\cr_out_ok[0:0] $2\cr_out_ok[0:0] + assign $1\cr_rd[7:0] $2\cr_rd[7:0] + assign $1\cr_rd_ok[0:0] $2\cr_rd_ok[0:0] + assign $1\cr_wr[7:0] $2\cr_wr[7:0] + assign $1\cr_wr_ok[0:0] $2\cr_wr_ok[0:0] + assign $1\exc_$signal[0:0]$3633 $2\exc_$signal[0:0]$3643 + assign $1\exc_$signal$3[0:0]$3634 $2\exc_$signal$3[0:0]$3644 + assign $1\exc_$signal$4[0:0]$3635 $2\exc_$signal$4[0:0]$3645 + assign $1\exc_$signal$5[0:0]$3636 $2\exc_$signal$5[0:0]$3646 + assign $1\exc_$signal$6[0:0]$3637 $2\exc_$signal$6[0:0]$3647 + assign $1\exc_$signal$7[0:0]$3638 $2\exc_$signal$7[0:0]$3648 + assign $1\exc_$signal$8[0:0]$3639 $2\exc_$signal$8[0:0]$3649 + assign $1\exc_$signal$9[0:0]$3640 $2\exc_$signal$9[0:0]$3650 + assign $1\fasto1[2:0] $2\fasto1[2:0] + assign $1\fasto1_ok[0:0] $2\fasto1_ok[0:0] + assign $1\fasto2[2:0] $2\fasto2[2:0] + assign $1\fasto2_ok[0:0] $2\fasto2_ok[0:0] + assign $1\fn_unit[11:0] $2\fn_unit[11:0] + assign $1\input_carry[1:0] $2\input_carry[1:0] + assign $1\insn[31:0] $2\insn[31:0] + assign $1\insn_type[6:0] $2\insn_type[6:0] + assign $1\is_32bit[0:0] $2\is_32bit[0:0] + assign $1\oe[0:0] $2\oe[0:0] + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + assign $1\rc_ok[0:0] $2\rc_ok[0:0] + assign $1\reg1[4:0] $2\reg1[4:0] + assign $1\reg1_ok[0:0] $2\reg1_ok[0:0] + assign $1\reg2[4:0] $2\reg2[4:0] + assign $1\reg2_ok[0:0] $2\reg2_ok[0:0] + assign $1\reg3[4:0] $2\reg3[4:0] + assign $1\reg3_ok[0:0] $2\reg3_ok[0:0] + assign $1\rego[4:0] $2\rego[4:0] + assign $1\rego_ok[0:0] $2\rego_ok[0:0] + assign $1\spro[9:0] $2\spro[9:0] + assign $1\spro_ok[0:0] $2\spro_ok[0:0] + assign $1\trapaddr[12:0] $2\trapaddr[12:0] + assign $1\traptype[7:0] $2\traptype[7:0] + assign $1\xer_in[2:0] $2\xer_in[2:0] + assign $1\xer_out[0:0] $2\xer_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" + switch { \dec2_exc_$signal$13 \dec2_exc_$signal$12 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\is_32bit[0:0] $2\cr_wr_ok[0:0] $2\cr_wr[7:0] $2\cr_rd_ok[0:0] $2\cr_rd[7:0] $2\exc_$signal$9[0:0]$3650 $2\exc_$signal$8[0:0]$3649 $2\exc_$signal$7[0:0]$3648 $2\exc_$signal$6[0:0]$3647 $2\exc_$signal$5[0:0]$3646 $2\exc_$signal$4[0:0]$3645 $2\exc_$signal$3[0:0]$3644 $2\exc_$signal[0:0]$3643 $2\input_carry[1:0] $2\oe_ok[0:0] $2\oe[0:0] $2\rc_ok[0:0] $2\rc[0:0] $2\lk[0:0] $2\cr_out_ok[0:0] $2\cr_out[2:0] $2\cr_in2_ok$2[0:0]$3642 $2\cr_in2$1[2:0]$3641 $2\cr_in2_ok[0:0] $2\cr_in2[2:0] $2\cr_in1_ok[0:0] $2\cr_in1[2:0] $2\fasto2_ok[0:0] $2\fasto2[2:0] $2\fasto1_ok[0:0] $2\fasto1[2:0] $2\fast2_ok[0:0] $2\fast2[2:0] $2\fast1_ok[0:0] $2\fast1[2:0] $2\xer_out[0:0] $2\xer_in[2:0] $2\spr1_ok[0:0] $2\spr1[9:0] $2\spro_ok[0:0] $2\spro[9:0] $2\reg3_ok[0:0] $2\reg3[4:0] $2\reg2_ok[0:0] $2\reg2[4:0] $2\reg1_ok[0:0] $2\reg1[4:0] $2\ea_ok[0:0] $2\ea[4:0] $2\rego_ok[0:0] $2\rego[4:0] $2\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $2\insn[31:0] \dec_opcode_in + assign $2\insn_type[6:0] 7'0111111 + assign $2\fn_unit[11:0] 12'000010000000 + assign $2\trapaddr[12:0] 13'0000001100000 + assign $2\traptype[7:0] 8'00000010 + assign $2\msr[63:0] \cur_msr + assign $2\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\fast1[2:0] $3\fast1[2:0] + assign $2\fast1_ok[0:0] $3\fast1_ok[0:0] + assign $2\fast2[2:0] $3\fast2[2:0] + assign $2\fast2_ok[0:0] $3\fast2_ok[0:0] + assign $2\rc[0:0] $3\rc[0:0] + assign $2\spr1[9:0] $3\spr1[9:0] + assign $2\spr1_ok[0:0] $3\spr1_ok[0:0] + assign $2\msr[63:0] $3\msr[63:0] + assign $2\ea_ok[0:0] $3\ea_ok[0:0] + assign $2\ea[4:0] $3\ea[4:0] + assign $2\asmcode[7:0] $3\asmcode[7:0] + assign $2\cr_out[2:0] $3\cr_out[2:0] + assign $2\lk[0:0] $3\lk[0:0] + assign $2\cia[63:0] $3\cia[63:0] + assign $2\cr_in1[2:0] $3\cr_in1[2:0] + assign $2\cr_in1_ok[0:0] $3\cr_in1_ok[0:0] + assign $2\cr_in2[2:0] $3\cr_in2[2:0] + assign $2\cr_in2$1[2:0]$3641 $3\cr_in2$1[2:0]$3651 + assign $2\cr_in2_ok[0:0] $3\cr_in2_ok[0:0] + assign $2\cr_in2_ok$2[0:0]$3642 $3\cr_in2_ok$2[0:0]$3652 + assign $2\cr_out_ok[0:0] $3\cr_out_ok[0:0] + assign $2\cr_rd[7:0] $3\cr_rd[7:0] + assign $2\cr_rd_ok[0:0] $3\cr_rd_ok[0:0] + assign $2\cr_wr[7:0] $3\cr_wr[7:0] + assign $2\cr_wr_ok[0:0] $3\cr_wr_ok[0:0] + assign $2\exc_$signal[0:0]$3643 $3\exc_$signal[0:0]$3653 + assign $2\exc_$signal$3[0:0]$3644 $3\exc_$signal$3[0:0]$3654 + assign $2\exc_$signal$4[0:0]$3645 $3\exc_$signal$4[0:0]$3655 + assign $2\exc_$signal$5[0:0]$3646 $3\exc_$signal$5[0:0]$3656 + assign $2\exc_$signal$6[0:0]$3647 $3\exc_$signal$6[0:0]$3657 + assign $2\exc_$signal$7[0:0]$3648 $3\exc_$signal$7[0:0]$3658 + assign $2\exc_$signal$8[0:0]$3649 $3\exc_$signal$8[0:0]$3659 + assign $2\exc_$signal$9[0:0]$3650 $3\exc_$signal$9[0:0]$3660 + assign $2\fasto1[2:0] $3\fasto1[2:0] + assign $2\fasto1_ok[0:0] $3\fasto1_ok[0:0] + assign $2\fasto2[2:0] $3\fasto2[2:0] + assign $2\fasto2_ok[0:0] $3\fasto2_ok[0:0] + assign $2\fn_unit[11:0] $3\fn_unit[11:0] + assign $2\input_carry[1:0] $3\input_carry[1:0] + assign $2\insn[31:0] $3\insn[31:0] + assign $2\insn_type[6:0] $3\insn_type[6:0] + assign $2\is_32bit[0:0] $3\is_32bit[0:0] + assign $2\oe[0:0] $3\oe[0:0] + assign $2\oe_ok[0:0] $3\oe_ok[0:0] + assign $2\rc_ok[0:0] $3\rc_ok[0:0] + assign $2\reg1[4:0] $3\reg1[4:0] + assign $2\reg1_ok[0:0] $3\reg1_ok[0:0] + assign $2\reg2[4:0] $3\reg2[4:0] + assign $2\reg2_ok[0:0] $3\reg2_ok[0:0] + assign $2\reg3[4:0] $3\reg3[4:0] + assign $2\reg3_ok[0:0] $3\reg3_ok[0:0] + assign $2\rego[4:0] $3\rego[4:0] + assign $2\rego_ok[0:0] $3\rego_ok[0:0] + assign $2\spro[9:0] $3\spro[9:0] + assign $2\spro_ok[0:0] $3\spro_ok[0:0] + assign $2\trapaddr[12:0] $3\trapaddr[12:0] + assign $2\traptype[7:0] $3\traptype[7:0] + assign $2\xer_in[2:0] $3\xer_in[2:0] + assign $2\xer_out[0:0] $3\xer_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + switch \dec2_exc_$signal$14 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\exc_$signal$9[0:0]$3660 $3\exc_$signal$8[0:0]$3659 $3\exc_$signal$7[0:0]$3658 $3\exc_$signal$6[0:0]$3657 $3\exc_$signal$5[0:0]$3656 $3\exc_$signal$4[0:0]$3655 $3\exc_$signal$3[0:0]$3654 $3\exc_$signal[0:0]$3653 $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[2:0] $3\cr_in2_ok$2[0:0]$3652 $3\cr_in2$1[2:0]$3651 $3\cr_in2_ok[0:0] $3\cr_in2[2:0] $3\cr_in1_ok[0:0] $3\cr_in1[2:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[4:0] $3\reg2_ok[0:0] $3\reg2[4:0] $3\reg1_ok[0:0] $3\reg1[4:0] $3\ea_ok[0:0] $3\ea[4:0] $3\rego_ok[0:0] $3\rego[4:0] $3\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $3\insn[31:0] \dec_opcode_in + assign $3\insn_type[6:0] 7'0111111 + assign $3\fn_unit[11:0] 12'000010000000 + assign $3\trapaddr[12:0] 13'0000001001000 + assign $3\traptype[7:0] 8'00000010 + assign $3\msr[63:0] \cur_msr + assign $3\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[2:0] $3\cr_in2_ok$2[0:0]$3652 $3\cr_in2$1[2:0]$3651 $3\cr_in2_ok[0:0] $3\cr_in2[2:0] $3\cr_in1_ok[0:0] $3\cr_in1[2:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[4:0] $3\reg2_ok[0:0] $3\reg2[4:0] $3\reg1_ok[0:0] $3\reg1[4:0] $3\ea_ok[0:0] $3\ea[4:0] $3\rego_ok[0:0] $3\rego[4:0] $3\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $3\insn[31:0] \dec_opcode_in + assign $3\insn_type[6:0] 7'0111111 + assign $3\fn_unit[11:0] 12'000010000000 + assign $3\trapaddr[12:0] 13'0000001000000 + assign $3\traptype[7:0] 8'01000000 + assign { $3\exc_$signal$9[0:0]$3660 $3\exc_$signal$8[0:0]$3659 $3\exc_$signal$7[0:0]$3658 $3\exc_$signal$6[0:0]$3657 $3\exc_$signal$5[0:0]$3656 $3\exc_$signal$4[0:0]$3655 $3\exc_$signal$3[0:0]$3654 $3\exc_$signal[0:0]$3653 } { \dec2_exc_$signal$14 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal$15 \dec2_exc_$signal$13 \dec2_exc_$signal$12 \dec2_exc_$signal } + assign $3\msr[63:0] \cur_msr + assign $3\cia[63:0] \cur_pc + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\fast1[2:0] $4\fast1[2:0] + assign $2\fast1_ok[0:0] $4\fast1_ok[0:0] + assign $2\fast2[2:0] $4\fast2[2:0] + assign $2\fast2_ok[0:0] $4\fast2_ok[0:0] + assign $2\rc[0:0] $4\rc[0:0] + assign $2\spr1[9:0] $4\spr1[9:0] + assign $2\spr1_ok[0:0] $4\spr1_ok[0:0] + assign $2\msr[63:0] $4\msr[63:0] + assign $2\ea_ok[0:0] $4\ea_ok[0:0] + assign $2\ea[4:0] $4\ea[4:0] + assign $2\asmcode[7:0] $4\asmcode[7:0] + assign $2\cr_out[2:0] $4\cr_out[2:0] + assign $2\lk[0:0] $4\lk[0:0] + assign $2\cia[63:0] $4\cia[63:0] + assign $2\cr_in1[2:0] $4\cr_in1[2:0] + assign $2\cr_in1_ok[0:0] $4\cr_in1_ok[0:0] + assign $2\cr_in2[2:0] $4\cr_in2[2:0] + assign $2\cr_in2$1[2:0]$3641 $4\cr_in2$1[2:0]$3661 + assign $2\cr_in2_ok[0:0] $4\cr_in2_ok[0:0] + assign $2\cr_in2_ok$2[0:0]$3642 $4\cr_in2_ok$2[0:0]$3662 + assign $2\cr_out_ok[0:0] $4\cr_out_ok[0:0] + assign $2\cr_rd[7:0] $4\cr_rd[7:0] + assign $2\cr_rd_ok[0:0] $4\cr_rd_ok[0:0] + assign $2\cr_wr[7:0] $4\cr_wr[7:0] + assign $2\cr_wr_ok[0:0] $4\cr_wr_ok[0:0] + assign $2\exc_$signal[0:0]$3643 $4\exc_$signal[0:0]$3663 + assign $2\exc_$signal$3[0:0]$3644 $4\exc_$signal$3[0:0]$3664 + assign $2\exc_$signal$4[0:0]$3645 $4\exc_$signal$4[0:0]$3665 + assign $2\exc_$signal$5[0:0]$3646 $4\exc_$signal$5[0:0]$3666 + assign $2\exc_$signal$6[0:0]$3647 $4\exc_$signal$6[0:0]$3667 + assign $2\exc_$signal$7[0:0]$3648 $4\exc_$signal$7[0:0]$3668 + assign $2\exc_$signal$8[0:0]$3649 $4\exc_$signal$8[0:0]$3669 + assign $2\exc_$signal$9[0:0]$3650 $4\exc_$signal$9[0:0]$3670 + assign $2\fasto1[2:0] $4\fasto1[2:0] + assign $2\fasto1_ok[0:0] $4\fasto1_ok[0:0] + assign $2\fasto2[2:0] $4\fasto2[2:0] + assign $2\fasto2_ok[0:0] $4\fasto2_ok[0:0] + assign $2\fn_unit[11:0] $4\fn_unit[11:0] + assign $2\input_carry[1:0] $4\input_carry[1:0] + assign $2\insn[31:0] $4\insn[31:0] + assign $2\insn_type[6:0] $4\insn_type[6:0] + assign $2\is_32bit[0:0] $4\is_32bit[0:0] + assign $2\oe[0:0] $4\oe[0:0] + assign $2\oe_ok[0:0] $4\oe_ok[0:0] + assign $2\rc_ok[0:0] $4\rc_ok[0:0] + assign $2\reg1[4:0] $4\reg1[4:0] + assign $2\reg1_ok[0:0] $4\reg1_ok[0:0] + assign $2\reg2[4:0] $4\reg2[4:0] + assign $2\reg2_ok[0:0] $4\reg2_ok[0:0] + assign $2\reg3[4:0] $4\reg3[4:0] + assign $2\reg3_ok[0:0] $4\reg3_ok[0:0] + assign $2\rego[4:0] $4\rego[4:0] + assign $2\rego_ok[0:0] $4\rego_ok[0:0] + assign $2\spro[9:0] $4\spro[9:0] + assign $2\spro_ok[0:0] $4\spro_ok[0:0] + assign $2\trapaddr[12:0] $4\trapaddr[12:0] + assign $2\traptype[7:0] $4\traptype[7:0] + assign $2\xer_in[2:0] $4\xer_in[2:0] + assign $2\xer_out[0:0] $4\xer_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:926" + switch \dec2_exc_$signal$14 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3670 $4\exc_$signal$8[0:0]$3669 $4\exc_$signal$7[0:0]$3668 $4\exc_$signal$6[0:0]$3667 $4\exc_$signal$5[0:0]$3666 $4\exc_$signal$4[0:0]$3665 $4\exc_$signal$3[0:0]$3664 $4\exc_$signal[0:0]$3663 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[2:0] $4\cr_in2_ok$2[0:0]$3662 $4\cr_in2$1[2:0]$3661 $4\cr_in2_ok[0:0] $4\cr_in2[2:0] $4\cr_in1_ok[0:0] $4\cr_in1[2:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[4:0] $4\reg2_ok[0:0] $4\reg2[4:0] $4\reg1_ok[0:0] $4\reg1[4:0] $4\ea_ok[0:0] $4\ea[4:0] $4\rego_ok[0:0] $4\rego[4:0] $4\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $4\insn[31:0] \dec_opcode_in + assign $4\insn_type[6:0] 7'0111111 + assign $4\fn_unit[11:0] 12'000010000000 + assign $4\trapaddr[12:0] 13'0000000111000 + assign $4\traptype[7:0] 8'00000010 + assign $4\msr[63:0] \cur_msr + assign $4\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3670 $4\exc_$signal$8[0:0]$3669 $4\exc_$signal$7[0:0]$3668 $4\exc_$signal$6[0:0]$3667 $4\exc_$signal$5[0:0]$3666 $4\exc_$signal$4[0:0]$3665 $4\exc_$signal$3[0:0]$3664 $4\exc_$signal[0:0]$3663 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[2:0] $4\cr_in2_ok$2[0:0]$3662 $4\cr_in2$1[2:0]$3661 $4\cr_in2_ok[0:0] $4\cr_in2[2:0] $4\cr_in1_ok[0:0] $4\cr_in1[2:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[4:0] $4\reg2_ok[0:0] $4\reg2[4:0] $4\reg1_ok[0:0] $4\reg1[4:0] $4\ea_ok[0:0] $4\ea[4:0] $4\rego_ok[0:0] $4\rego[4:0] $4\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $4\insn[31:0] \dec_opcode_in + assign $4\insn_type[6:0] 7'0111111 + assign $4\fn_unit[11:0] 12'000010000000 + assign $4\trapaddr[12:0] 13'0000000110000 + assign $4\traptype[7:0] 8'00000010 + assign $4\msr[63:0] \cur_msr + assign $4\cia[63:0] \cur_pc + end + end + attribute \src "libresoc.v:0.0-0.0" + case 5'---1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3640 $1\exc_$signal$8[0:0]$3639 $1\exc_$signal$7[0:0]$3638 $1\exc_$signal$6[0:0]$3637 $1\exc_$signal$5[0:0]$3636 $1\exc_$signal$4[0:0]$3635 $1\exc_$signal$3[0:0]$3634 $1\exc_$signal[0:0]$3633 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3632 $1\cr_in2$1[2:0]$3631 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\insn[31:0] \dec_opcode_in + assign $1\insn_type[6:0] 7'0111111 + assign $1\fn_unit[11:0] 12'000010000000 + assign $1\trapaddr[12:0] 13'0000010010000 + assign $1\traptype[7:0] 8'00100000 + assign $1\msr[63:0] \cur_msr + assign $1\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case 5'--1-- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3640 $1\exc_$signal$8[0:0]$3639 $1\exc_$signal$7[0:0]$3638 $1\exc_$signal$6[0:0]$3637 $1\exc_$signal$5[0:0]$3636 $1\exc_$signal$4[0:0]$3635 $1\exc_$signal$3[0:0]$3634 $1\exc_$signal[0:0]$3633 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3632 $1\cr_in2$1[2:0]$3631 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\insn[31:0] \dec_opcode_in + assign $1\insn_type[6:0] 7'0111111 + assign $1\fn_unit[11:0] 12'000010000000 + assign $1\trapaddr[12:0] 13'0000001010000 + assign $1\traptype[7:0] 8'00010000 + assign $1\msr[63:0] \cur_msr + assign $1\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case 5'-1--- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3640 $1\exc_$signal$8[0:0]$3639 $1\exc_$signal$7[0:0]$3638 $1\exc_$signal$6[0:0]$3637 $1\exc_$signal$5[0:0]$3636 $1\exc_$signal$4[0:0]$3635 $1\exc_$signal$3[0:0]$3634 $1\exc_$signal[0:0]$3633 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3632 $1\cr_in2$1[2:0]$3631 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\insn[31:0] \dec_opcode_in + assign $1\insn_type[6:0] 7'0111111 + assign $1\fn_unit[11:0] 12'000010000000 + assign $1\trapaddr[12:0] 13'0000001110000 + assign $1\traptype[7:0] 8'00000010 + assign $1\msr[63:0] \cur_msr + assign $1\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case 5'1---- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3640 $1\exc_$signal$8[0:0]$3639 $1\exc_$signal$7[0:0]$3638 $1\exc_$signal$6[0:0]$3637 $1\exc_$signal$5[0:0]$3636 $1\exc_$signal$4[0:0]$3635 $1\exc_$signal$3[0:0]$3634 $1\exc_$signal[0:0]$3633 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3632 $1\cr_in2$1[2:0]$3631 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\insn[31:0] \dec_opcode_in + assign $1\insn_type[6:0] 7'0111111 + assign $1\fn_unit[11:0] 12'000010000000 + assign $1\trapaddr[12:0] 13'0000001110000 + assign $1\traptype[7:0] 8'10000000 + assign $1\msr[63:0] \cur_msr + assign $1\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\trapaddr[12:0] $1\exc_$signal$9[0:0]$3640 $1\exc_$signal$8[0:0]$3639 $1\exc_$signal$7[0:0]$3638 $1\exc_$signal$6[0:0]$3637 $1\exc_$signal$5[0:0]$3636 $1\exc_$signal$4[0:0]$3635 $1\exc_$signal$3[0:0]$3634 $1\exc_$signal[0:0]$3633 $1\traptype[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\fn_unit[11:0] $1\insn_type[6:0] $1\insn[31:0] $1\cia[63:0] $1\msr[63:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3632 $1\cr_in2$1[2:0]$3631 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } { \tmp_tmp_is_32bit \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd \tmp_tmp_trapaddr \tmp_tmp_exc_$signal$27 \tmp_tmp_exc_$signal$26 \tmp_tmp_exc_$signal$25 \tmp_tmp_exc_$signal$24 \tmp_tmp_exc_$signal$23 \tmp_tmp_exc_$signal$22 \tmp_tmp_exc_$signal$21 \tmp_tmp_exc_$signal \tmp_tmp_traptype \tmp_tmp_input_carry \tmp_tmp_oe_ok \tmp_tmp_oe \tmp_tmp_rc_ok \tmp_tmp_rc \tmp_tmp_lk \tmp_tmp_fn_unit \tmp_tmp_insn_type \tmp_tmp_insn \tmp_tmp_cia \tmp_tmp_msr \tmp_cr_out_ok \tmp_cr_out \tmp_cr_in2_ok$20 \tmp_cr_in2$19 \tmp_cr_in2_ok \tmp_cr_in2 \tmp_cr_in1_ok \tmp_cr_in1 \tmp_fasto2_ok \tmp_fasto2 \tmp_fasto1_ok \tmp_fasto1 \tmp_fast2_ok \tmp_fast2 \tmp_fast1_ok \tmp_fast1 \tmp_xer_out \tmp_xer_in \tmp_spr1_ok \tmp_spr1 \tmp_spro_ok \tmp_spro \tmp_reg3_ok \tmp_reg3 \tmp_reg2_ok \tmp_reg2 \tmp_reg1_ok \tmp_reg1 \tmp_ea_ok \tmp_ea \tmp_rego_ok \tmp_rego \tmp_asmcode } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:961" + switch \$32 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $5\fasto1[2:0] 3'011 + assign $5\fasto1_ok[0:0] 1'1 + assign $5\fasto2[2:0] 3'100 + assign $5\fasto2_ok[0:0] 1'1 + case + assign $5\fasto1[2:0] $1\fasto1[2:0] + assign $5\fasto1_ok[0:0] $1\fasto1_ok[0:0] + assign $5\fasto2[2:0] $1\fasto2[2:0] + assign $5\fasto2_ok[0:0] $1\fasto2_ok[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:970" + switch \$34 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $5\fast1[2:0] 3'011 + assign $5\fast1_ok[0:0] 1'1 + assign $5\fast2[2:0] 3'100 + assign $5\fast2_ok[0:0] 1'1 + case + assign $5\fast1[2:0] $1\fast1[2:0] + assign $5\fast1_ok[0:0] $1\fast1_ok[0:0] + assign $5\fast2[2:0] $1\fast2[2:0] + assign $5\fast2_ok[0:0] $1\fast2_ok[0:0] + end + sync always + update \fast1 $0\fast1[2:0] + update \fast1_ok $0\fast1_ok[0:0] + update \fast2 $0\fast2[2:0] + update \fast2_ok $0\fast2_ok[0:0] + update \rc $0\rc[0:0] + update \spr1 $0\spr1[9:0] + update \spr1_ok $0\spr1_ok[0:0] + update \msr $0\msr[63:0] + update \ea_ok $0\ea_ok[0:0] + update \ea $0\ea[4:0] + update \asmcode $0\asmcode[7:0] + update \cr_out $0\cr_out[2:0] + update \lk $0\lk[0:0] + update \cia $0\cia[63:0] + update \cr_in1 $0\cr_in1[2:0] + update \cr_in1_ok $0\cr_in1_ok[0:0] + update \cr_in2 $0\cr_in2[2:0] + update \cr_in2$1 $0\cr_in2$1[2:0]$3621 + update \cr_in2_ok $0\cr_in2_ok[0:0] + update \cr_in2_ok$2 $0\cr_in2_ok$2[0:0]$3622 + update \cr_out_ok $0\cr_out_ok[0:0] + update \cr_rd $0\cr_rd[7:0] + update \cr_rd_ok $0\cr_rd_ok[0:0] + update \cr_wr $0\cr_wr[7:0] + update \cr_wr_ok $0\cr_wr_ok[0:0] + update \exc_$signal $0\exc_$signal[0:0]$3623 + update \exc_$signal$3 $0\exc_$signal$3[0:0]$3624 + update \exc_$signal$4 $0\exc_$signal$4[0:0]$3625 + update \exc_$signal$5 $0\exc_$signal$5[0:0]$3626 + update \exc_$signal$6 $0\exc_$signal$6[0:0]$3627 + update \exc_$signal$7 $0\exc_$signal$7[0:0]$3628 + update \exc_$signal$8 $0\exc_$signal$8[0:0]$3629 + update \exc_$signal$9 $0\exc_$signal$9[0:0]$3630 + update \fasto1 $0\fasto1[2:0] + update \fasto1_ok $0\fasto1_ok[0:0] + update \fasto2 $0\fasto2[2:0] + update \fasto2_ok $0\fasto2_ok[0:0] + update \fn_unit $0\fn_unit[11:0] + update \input_carry $0\input_carry[1:0] + update \insn $0\insn[31:0] + update \insn_type $0\insn_type[6:0] + update \is_32bit $0\is_32bit[0:0] + update \oe $0\oe[0:0] + update \oe_ok $0\oe_ok[0:0] + update \rc_ok $0\rc_ok[0:0] + update \reg1 $0\reg1[4:0] + update \reg1_ok $0\reg1_ok[0:0] + update \reg2 $0\reg2[4:0] + update \reg2_ok $0\reg2_ok[0:0] + update \reg3 $0\reg3[4:0] + update \reg3_ok $0\reg3_ok[0:0] + update \rego $0\rego[4:0] + update \rego_ok $0\rego_ok[0:0] + update \spro $0\spro[9:0] + update \spro_ok $0\spro_ok[0:0] + update \trapaddr $0\trapaddr[12:0] + update \traptype $0\traptype[7:0] + update \xer_in $0\xer_in[2:0] + update \xer_out $0\xer_out[0:0] + end + connect \$28 $eq$libresoc.v:75078$3603_Y + connect \$30 $eq$libresoc.v:75079$3604_Y + connect \$32 $or$libresoc.v:75080$3605_Y + connect \$34 $eq$libresoc.v:75081$3606_Y + connect \$42 $eq$libresoc.v:75082$3607_Y + connect \$44 $eq$libresoc.v:75083$3608_Y + connect \$46 $eq$libresoc.v:75084$3609_Y + connect \$48 $eq$libresoc.v:75085$3610_Y + connect \$50 $and$libresoc.v:75086$3611_Y + connect \$52 $and$libresoc.v:75087$3612_Y + connect \$54 $and$libresoc.v:75088$3613_Y + connect \$56 $eq$libresoc.v:75089$3614_Y + connect \dec2_exc_$signal 1'0 + connect \dec2_exc_$signal$12 1'0 + connect \dec2_exc_$signal$13 1'0 + connect \dec2_exc_$signal$14 1'0 + connect \dec2_exc_$signal$15 1'0 + connect \dec2_exc_$signal$16 1'0 + connect \dec2_exc_$signal$17 1'0 + connect \dec2_exc_$signal$18 1'0 + connect \tmp_asmcode 8'00000000 + connect \tmp_tmp_traptype 8'00000000 + connect \tmp_tmp_exc_$signal 1'0 + connect \tmp_tmp_exc_$signal$21 1'0 + connect \tmp_tmp_exc_$signal$22 1'0 + connect \tmp_tmp_exc_$signal$23 1'0 + connect \tmp_tmp_exc_$signal$24 1'0 + connect \tmp_tmp_exc_$signal$25 1'0 + connect \tmp_tmp_exc_$signal$26 1'0 + connect \tmp_tmp_exc_$signal$27 1'0 + connect \illeg_ok \$56 + connect \priv_ok \$54 + connect \dec_irq_ok \$52 + connect \ext_irq_ok \$50 + connect { \tmp_cr_out_ok \tmp_cr_out } { \dec_cr_out_cr_bitfield_ok \dec_cr_out_cr_bitfield } + connect { \tmp_cr_in2_ok$20 \tmp_cr_in2$19 } { \dec_cr_in_cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o } + connect { \tmp_cr_in2_ok \tmp_cr_in2 } { \dec_cr_in_cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b } + connect { \tmp_cr_in1_ok \tmp_cr_in1 } { \dec_cr_in_cr_bitfield_ok \dec_cr_in_cr_bitfield } + connect { \tmp_fasto2_ok \tmp_fasto2 } { \dec_o2_fast_o_ok \dec_o2_fast_o } + connect { \tmp_fasto1_ok \tmp_fasto1 } { \dec_o_fast_o_ok \dec_o_fast_o } + connect { \tmp_fast2_ok \tmp_fast2 } { \dec_b_fast_b_ok \dec_b_fast_b } + connect { \tmp_fast1_ok \tmp_fast1 } { \dec_a_fast_a_ok \dec_a_fast_a } + connect { \tmp_spro_ok \tmp_spro } { \dec_o_spr_o_ok \dec_o_spr_o } + connect { \tmp_spr1_ok \tmp_spr1 } { \dec_a_spr_a_ok \dec_a_spr_a } + connect { \tmp_ea_ok \tmp_ea } { \dec_o2_reg_o_ok \dec_o2_reg_o } + connect { \tmp_rego_ok \tmp_rego } { \dec_o_reg_o_ok \dec_o_reg_o } + connect { \tmp_reg3_ok \tmp_reg3 } { \dec_c_reg_c_ok \dec_c_reg_c } + connect { \tmp_reg2_ok \tmp_reg2 } { \dec_b_reg_b_ok \dec_b_reg_b } + connect { \tmp_reg1_ok \tmp_reg1 } { \dec_a_reg_a_ok \dec_a_reg_a } + connect \dec_o2_lk \tmp_tmp_lk + connect \sel_in \dec_out_sel + connect \dec_o_sel_in \dec_out_sel + connect \dec_c_sel_in \dec_in3_sel + connect \dec_b_sel_in \dec_in2_sel + connect \dec_a_sel_in \dec_in1_sel + connect \insn_in$41 \dec_opcode_in + connect \insn_in$40 \dec_opcode_in + connect \insn_in$39 \dec_opcode_in + connect \insn_in$38 \dec_opcode_in + connect \insn_in$37 \dec_opcode_in + connect \tmp_tmp_insn \dec_opcode_in + connect \tmp_tmp_is_32bit \dec_is_32b + connect \tmp_tmp_input_carry \dec_cry_in + connect { \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr } { \dec_cr_out_cr_fxm_ok \dec_cr_out_cr_fxm } + connect { \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd } { \dec_cr_in_cr_fxm_ok \dec_cr_in_cr_fxm } + connect { \tmp_tmp_oe_ok \tmp_tmp_oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \tmp_tmp_rc_ok \tmp_tmp_rc } { \dec_rc_rc_ok \dec_rc_rc } + connect \tmp_tmp_fn_unit \dec_function_unit + connect \tmp_tmp_insn_type \dec_internal_op + connect \tmp_tmp_cia \cur_pc + connect \tmp_tmp_msr \cur_msr + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_cr_out + connect \dec_cr_in_sel_in \dec_cr_in + connect \dec_oe_sel_in \dec_rc_sel + connect \dec_rc_sel_in \dec_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$36 \dec_opcode_in + connect \insn_in \dec_opcode_in +end +attribute \src "libresoc.v:75527.1-76674.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec30" +attribute \generator "nMigen" +module \dec30 + attribute \src "libresoc.v:75970.3-76006.6" + wire width 8 $0\dec30_asmcode[7:0] + attribute \src "libresoc.v:76118.3-76154.6" + wire $0\dec30_br[0:0] + attribute \src "libresoc.v:76599.3-76635.6" + wire width 3 $0\dec30_cr_in[2:0] + attribute \src "libresoc.v:76636.3-76672.6" + wire width 3 $0\dec30_cr_out[2:0] + attribute \src "libresoc.v:75933.3-75969.6" + wire width 2 $0\dec30_cry_in[1:0] + attribute \src "libresoc.v:76081.3-76117.6" + wire $0\dec30_cry_out[0:0] + attribute \src "libresoc.v:76414.3-76450.6" + wire width 5 $0\dec30_form[4:0] + attribute \src "libresoc.v:75785.3-75821.6" + wire width 12 $0\dec30_function_unit[11:0] + attribute \src "libresoc.v:76451.3-76487.6" + wire width 3 $0\dec30_in1_sel[2:0] + attribute \src "libresoc.v:76488.3-76524.6" + wire width 4 $0\dec30_in2_sel[3:0] + attribute \src "libresoc.v:76525.3-76561.6" + wire width 2 $0\dec30_in3_sel[1:0] + attribute \src "libresoc.v:76192.3-76228.6" + wire width 7 $0\dec30_internal_op[6:0] + attribute \src "libresoc.v:76007.3-76043.6" + wire $0\dec30_inv_a[0:0] + attribute \src "libresoc.v:76044.3-76080.6" + wire $0\dec30_inv_out[0:0] + attribute \src "libresoc.v:76266.3-76302.6" + wire $0\dec30_is_32b[0:0] + attribute \src "libresoc.v:75822.3-75858.6" + wire width 4 $0\dec30_ldst_len[3:0] + attribute \src "libresoc.v:76340.3-76376.6" + wire $0\dec30_lk[0:0] + attribute \src "libresoc.v:76562.3-76598.6" + wire width 2 $0\dec30_out_sel[1:0] + attribute \src "libresoc.v:75896.3-75932.6" + wire width 2 $0\dec30_rc_sel[1:0] + attribute \src "libresoc.v:76229.3-76265.6" + wire $0\dec30_rsrv[0:0] + attribute \src "libresoc.v:76377.3-76413.6" + wire $0\dec30_sgl_pipe[0:0] + attribute \src "libresoc.v:76303.3-76339.6" + wire $0\dec30_sgn[0:0] + attribute \src "libresoc.v:76155.3-76191.6" + wire $0\dec30_sgn_ext[0:0] + attribute \src "libresoc.v:75859.3-75895.6" + wire width 2 $0\dec30_upd[1:0] + attribute \src "libresoc.v:75528.7-75528.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:75970.3-76006.6" + wire width 8 $1\dec30_asmcode[7:0] + attribute \src "libresoc.v:76118.3-76154.6" + wire $1\dec30_br[0:0] + attribute \src "libresoc.v:76599.3-76635.6" + wire width 3 $1\dec30_cr_in[2:0] + attribute \src "libresoc.v:76636.3-76672.6" + wire width 3 $1\dec30_cr_out[2:0] + attribute \src "libresoc.v:75933.3-75969.6" + wire width 2 $1\dec30_cry_in[1:0] + attribute \src "libresoc.v:76081.3-76117.6" + wire $1\dec30_cry_out[0:0] + attribute \src "libresoc.v:76414.3-76450.6" + wire width 5 $1\dec30_form[4:0] + attribute \src "libresoc.v:75785.3-75821.6" + wire width 12 $1\dec30_function_unit[11:0] + attribute \src "libresoc.v:76451.3-76487.6" + wire width 3 $1\dec30_in1_sel[2:0] + attribute \src "libresoc.v:76488.3-76524.6" + wire width 4 $1\dec30_in2_sel[3:0] + attribute \src "libresoc.v:76525.3-76561.6" + wire width 2 $1\dec30_in3_sel[1:0] + attribute \src "libresoc.v:76192.3-76228.6" + wire width 7 $1\dec30_internal_op[6:0] + attribute \src "libresoc.v:76007.3-76043.6" + wire $1\dec30_inv_a[0:0] + attribute \src "libresoc.v:76044.3-76080.6" + wire $1\dec30_inv_out[0:0] + attribute \src "libresoc.v:76266.3-76302.6" + wire $1\dec30_is_32b[0:0] + attribute \src "libresoc.v:75822.3-75858.6" + wire width 4 $1\dec30_ldst_len[3:0] + attribute \src "libresoc.v:76340.3-76376.6" + wire $1\dec30_lk[0:0] + attribute \src "libresoc.v:76562.3-76598.6" + wire width 2 $1\dec30_out_sel[1:0] + attribute \src "libresoc.v:75896.3-75932.6" + wire width 2 $1\dec30_rc_sel[1:0] + attribute \src "libresoc.v:76229.3-76265.6" + wire $1\dec30_rsrv[0:0] + attribute \src "libresoc.v:76377.3-76413.6" + wire $1\dec30_sgl_pipe[0:0] + attribute \src "libresoc.v:76303.3-76339.6" + wire $1\dec30_sgn[0:0] + attribute \src "libresoc.v:76155.3-76191.6" + wire $1\dec30_sgn_ext[0:0] + attribute \src "libresoc.v:75859.3-75895.6" + wire width 2 $1\dec30_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec30_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec30_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec30_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec30_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec30_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec30_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec30_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec30_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec30_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec30_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec30_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec30_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec30_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec30_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec30_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec30_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec30_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec30_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec30_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec30_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec30_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec30_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec30_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec30_upd + attribute \src "libresoc.v:75528.7-75528.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 4 \opcode_switch + attribute \src "libresoc.v:75528.7-75528.20" + process $proc$libresoc.v:75528$3696 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:75785.3-75821.6" + process $proc$libresoc.v:75785$3672 + assign { } { } + assign { } { } + assign $0\dec30_function_unit[11:0] $1\dec30_function_unit[11:0] + attribute \src "libresoc.v:75786.5-75786.29" + switch \initial + attribute \src "libresoc.v:75786.9-75786.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + case + assign $1\dec30_function_unit[11:0] 12'000000000000 + end + sync always + update \dec30_function_unit $0\dec30_function_unit[11:0] + end + attribute \src "libresoc.v:75822.3-75858.6" + process $proc$libresoc.v:75822$3673 + assign { } { } + assign { } { } + assign $0\dec30_ldst_len[3:0] $1\dec30_ldst_len[3:0] + attribute \src "libresoc.v:75823.5-75823.29" + switch \initial + attribute \src "libresoc.v:75823.9-75823.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + case + assign $1\dec30_ldst_len[3:0] 4'0000 + end + sync always + update \dec30_ldst_len $0\dec30_ldst_len[3:0] + end + attribute \src "libresoc.v:75859.3-75895.6" + process $proc$libresoc.v:75859$3674 + assign { } { } + assign { } { } + assign $0\dec30_upd[1:0] $1\dec30_upd[1:0] + attribute \src "libresoc.v:75860.5-75860.29" + switch \initial + attribute \src "libresoc.v:75860.9-75860.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + case + assign $1\dec30_upd[1:0] 2'00 + end + sync always + update \dec30_upd $0\dec30_upd[1:0] + end + attribute \src "libresoc.v:75896.3-75932.6" + process $proc$libresoc.v:75896$3675 + assign { } { } + assign { } { } + assign $0\dec30_rc_sel[1:0] $1\dec30_rc_sel[1:0] + attribute \src "libresoc.v:75897.5-75897.29" + switch \initial + attribute \src "libresoc.v:75897.9-75897.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + case + assign $1\dec30_rc_sel[1:0] 2'00 + end + sync always + update \dec30_rc_sel $0\dec30_rc_sel[1:0] + end + attribute \src "libresoc.v:75933.3-75969.6" + process $proc$libresoc.v:75933$3676 + assign { } { } + assign { } { } + assign $0\dec30_cry_in[1:0] $1\dec30_cry_in[1:0] + attribute \src "libresoc.v:75934.5-75934.29" + switch \initial + attribute \src "libresoc.v:75934.9-75934.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + case + assign $1\dec30_cry_in[1:0] 2'00 + end + sync always + update \dec30_cry_in $0\dec30_cry_in[1:0] + end + attribute \src "libresoc.v:75970.3-76006.6" + process $proc$libresoc.v:75970$3677 + assign { } { } + assign { } { } + assign $0\dec30_asmcode[7:0] $1\dec30_asmcode[7:0] + attribute \src "libresoc.v:75971.5-75971.29" + switch \initial + attribute \src "libresoc.v:75971.9-75971.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010101 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010101 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010110 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010110 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010111 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010111 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010010 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010011 + case + assign $1\dec30_asmcode[7:0] 8'00000000 + end + sync always + update \dec30_asmcode $0\dec30_asmcode[7:0] + end + attribute \src "libresoc.v:76007.3-76043.6" + process $proc$libresoc.v:76007$3678 + assign { } { } + assign { } { } + assign $0\dec30_inv_a[0:0] $1\dec30_inv_a[0:0] + attribute \src "libresoc.v:76008.5-76008.29" + switch \initial + attribute \src "libresoc.v:76008.9-76008.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + case + assign $1\dec30_inv_a[0:0] 1'0 + end + sync always + update \dec30_inv_a $0\dec30_inv_a[0:0] + end + attribute \src "libresoc.v:76044.3-76080.6" + process $proc$libresoc.v:76044$3679 + assign { } { } + assign { } { } + assign $0\dec30_inv_out[0:0] $1\dec30_inv_out[0:0] + attribute \src "libresoc.v:76045.5-76045.29" + switch \initial + attribute \src "libresoc.v:76045.9-76045.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + case + assign $1\dec30_inv_out[0:0] 1'0 + end + sync always + update \dec30_inv_out $0\dec30_inv_out[0:0] + end + attribute \src "libresoc.v:76081.3-76117.6" + process $proc$libresoc.v:76081$3680 + assign { } { } + assign { } { } + assign $0\dec30_cry_out[0:0] $1\dec30_cry_out[0:0] + attribute \src "libresoc.v:76082.5-76082.29" + switch \initial + attribute \src "libresoc.v:76082.9-76082.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + case + assign $1\dec30_cry_out[0:0] 1'0 + end + sync always + update \dec30_cry_out $0\dec30_cry_out[0:0] + end + attribute \src "libresoc.v:76118.3-76154.6" + process $proc$libresoc.v:76118$3681 + assign { } { } + assign { } { } + assign $0\dec30_br[0:0] $1\dec30_br[0:0] + attribute \src "libresoc.v:76119.5-76119.29" + switch \initial + attribute \src "libresoc.v:76119.9-76119.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + case + assign $1\dec30_br[0:0] 1'0 + end + sync always + update \dec30_br $0\dec30_br[0:0] + end + attribute \src "libresoc.v:76155.3-76191.6" + process $proc$libresoc.v:76155$3682 + assign { } { } + assign { } { } + assign $0\dec30_sgn_ext[0:0] $1\dec30_sgn_ext[0:0] + attribute \src "libresoc.v:76156.5-76156.29" + switch \initial + attribute \src "libresoc.v:76156.9-76156.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + case + assign $1\dec30_sgn_ext[0:0] 1'0 + end + sync always + update \dec30_sgn_ext $0\dec30_sgn_ext[0:0] + end + attribute \src "libresoc.v:76192.3-76228.6" + process $proc$libresoc.v:76192$3683 + assign { } { } + assign { } { } + assign $0\dec30_internal_op[6:0] $1\dec30_internal_op[6:0] + attribute \src "libresoc.v:76193.5-76193.29" + switch \initial + attribute \src "libresoc.v:76193.9-76193.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111010 + case + assign $1\dec30_internal_op[6:0] 7'0000000 + end + sync always + update \dec30_internal_op $0\dec30_internal_op[6:0] + end + attribute \src "libresoc.v:76229.3-76265.6" + process $proc$libresoc.v:76229$3684 + assign { } { } + assign { } { } + assign $0\dec30_rsrv[0:0] $1\dec30_rsrv[0:0] + attribute \src "libresoc.v:76230.5-76230.29" + switch \initial + attribute \src "libresoc.v:76230.9-76230.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + case + assign $1\dec30_rsrv[0:0] 1'0 + end + sync always + update \dec30_rsrv $0\dec30_rsrv[0:0] + end + attribute \src "libresoc.v:76266.3-76302.6" + process $proc$libresoc.v:76266$3685 + assign { } { } + assign { } { } + assign $0\dec30_is_32b[0:0] $1\dec30_is_32b[0:0] + attribute \src "libresoc.v:76267.5-76267.29" + switch \initial + attribute \src "libresoc.v:76267.9-76267.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + case + assign $1\dec30_is_32b[0:0] 1'0 + end + sync always + update \dec30_is_32b $0\dec30_is_32b[0:0] + end + attribute \src "libresoc.v:76303.3-76339.6" + process $proc$libresoc.v:76303$3686 + assign { } { } + assign { } { } + assign $0\dec30_sgn[0:0] $1\dec30_sgn[0:0] + attribute \src "libresoc.v:76304.5-76304.29" + switch \initial + attribute \src "libresoc.v:76304.9-76304.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + case + assign $1\dec30_sgn[0:0] 1'0 + end + sync always + update \dec30_sgn $0\dec30_sgn[0:0] + end + attribute \src "libresoc.v:76340.3-76376.6" + process $proc$libresoc.v:76340$3687 + assign { } { } + assign { } { } + assign $0\dec30_lk[0:0] $1\dec30_lk[0:0] + attribute \src "libresoc.v:76341.5-76341.29" + switch \initial + attribute \src "libresoc.v:76341.9-76341.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + case + assign $1\dec30_lk[0:0] 1'0 + end + sync always + update \dec30_lk $0\dec30_lk[0:0] + end + attribute \src "libresoc.v:76377.3-76413.6" + process $proc$libresoc.v:76377$3688 + assign { } { } + assign { } { } + assign $0\dec30_sgl_pipe[0:0] $1\dec30_sgl_pipe[0:0] + attribute \src "libresoc.v:76378.5-76378.29" + switch \initial + attribute \src "libresoc.v:76378.9-76378.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + case + assign $1\dec30_sgl_pipe[0:0] 1'0 + end + sync always + update \dec30_sgl_pipe $0\dec30_sgl_pipe[0:0] + end + attribute \src "libresoc.v:76414.3-76450.6" + process $proc$libresoc.v:76414$3689 + assign { } { } + assign { } { } + assign $0\dec30_form[4:0] $1\dec30_form[4:0] + attribute \src "libresoc.v:76415.5-76415.29" + switch \initial + attribute \src "libresoc.v:76415.9-76415.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_form[4:0] 5'10101 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_form[4:0] 5'10101 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + case + assign $1\dec30_form[4:0] 5'00000 + end + sync always + update \dec30_form $0\dec30_form[4:0] + end + attribute \src "libresoc.v:76451.3-76487.6" + process $proc$libresoc.v:76451$3690 + assign { } { } + assign { } { } + assign $0\dec30_in1_sel[2:0] $1\dec30_in1_sel[2:0] + attribute \src "libresoc.v:76452.5-76452.29" + switch \initial + attribute \src "libresoc.v:76452.9-76452.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + case + assign $1\dec30_in1_sel[2:0] 3'000 + end + sync always + update \dec30_in1_sel $0\dec30_in1_sel[2:0] + end + attribute \src "libresoc.v:76488.3-76524.6" + process $proc$libresoc.v:76488$3691 + assign { } { } + assign { } { } + assign $0\dec30_in2_sel[3:0] $1\dec30_in2_sel[3:0] + attribute \src "libresoc.v:76489.5-76489.29" + switch \initial + attribute \src "libresoc.v:76489.9-76489.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'0001 + case + assign $1\dec30_in2_sel[3:0] 4'0000 + end + sync always + update \dec30_in2_sel $0\dec30_in2_sel[3:0] + end + attribute \src "libresoc.v:76525.3-76561.6" + process $proc$libresoc.v:76525$3692 + assign { } { } + assign { } { } + assign $0\dec30_in3_sel[1:0] $1\dec30_in3_sel[1:0] + attribute \src "libresoc.v:76526.5-76526.29" + switch \initial + attribute \src "libresoc.v:76526.9-76526.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + case + assign $1\dec30_in3_sel[1:0] 2'00 + end + sync always + update \dec30_in3_sel $0\dec30_in3_sel[1:0] + end + attribute \src "libresoc.v:76562.3-76598.6" + process $proc$libresoc.v:76562$3693 + assign { } { } + assign { } { } + assign $0\dec30_out_sel[1:0] $1\dec30_out_sel[1:0] + attribute \src "libresoc.v:76563.5-76563.29" + switch \initial + attribute \src "libresoc.v:76563.9-76563.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + case + assign $1\dec30_out_sel[1:0] 2'00 + end + sync always + update \dec30_out_sel $0\dec30_out_sel[1:0] + end + attribute \src "libresoc.v:76599.3-76635.6" + process $proc$libresoc.v:76599$3694 + assign { } { } + assign { } { } + assign $0\dec30_cr_in[2:0] $1\dec30_cr_in[2:0] + attribute \src "libresoc.v:76600.5-76600.29" + switch \initial + attribute \src "libresoc.v:76600.9-76600.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + case + assign $1\dec30_cr_in[2:0] 3'000 + end + sync always + update \dec30_cr_in $0\dec30_cr_in[2:0] + end + attribute \src "libresoc.v:76636.3-76672.6" + process $proc$libresoc.v:76636$3695 + assign { } { } + assign { } { } + assign $0\dec30_cr_out[2:0] $1\dec30_cr_out[2:0] + attribute \src "libresoc.v:76637.5-76637.29" + switch \initial + attribute \src "libresoc.v:76637.9-76637.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + case + assign $1\dec30_cr_out[2:0] 3'000 + end + sync always + update \dec30_cr_out $0\dec30_cr_out[2:0] + end + connect \opcode_switch \opcode_in [4:1] +end +attribute \src "libresoc.v:76678.1-83048.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31" +attribute \generator "nMigen" +module \dec31 + attribute \src "libresoc.v:81747.3-81807.6" + wire width 8 $0\dec31_asmcode[7:0] + attribute \src "libresoc.v:82601.3-82661.6" + wire $0\dec31_br[0:0] + attribute \src "libresoc.v:82052.3-82112.6" + wire width 3 $0\dec31_cr_in[2:0] + attribute \src "libresoc.v:82113.3-82173.6" + wire width 3 $0\dec31_cr_out[2:0] + attribute \src "libresoc.v:82357.3-82417.6" + wire width 2 $0\dec31_cry_in[1:0] + attribute \src "libresoc.v:82540.3-82600.6" + wire $0\dec31_cry_out[0:0] + attribute \src "libresoc.v:81686.3-81746.6" + wire width 5 $0\dec31_form[4:0] + attribute \src "libresoc.v:81564.3-81624.6" + wire width 12 $0\dec31_function_unit[11:0] + attribute \src "libresoc.v:81808.3-81868.6" + wire width 3 $0\dec31_in1_sel[2:0] + attribute \src "libresoc.v:81869.3-81929.6" + wire width 4 $0\dec31_in2_sel[3:0] + attribute \src "libresoc.v:81930.3-81990.6" + wire width 2 $0\dec31_in3_sel[1:0] + attribute \src "libresoc.v:81625.3-81685.6" + wire width 7 $0\dec31_internal_op[6:0] + attribute \src "libresoc.v:82418.3-82478.6" + wire $0\dec31_inv_a[0:0] + attribute \src "libresoc.v:82479.3-82539.6" + wire $0\dec31_inv_out[0:0] + attribute \src "libresoc.v:82784.3-82844.6" + wire $0\dec31_is_32b[0:0] + attribute \src "libresoc.v:82174.3-82234.6" + wire width 4 $0\dec31_ldst_len[3:0] + attribute \src "libresoc.v:82906.3-82966.6" + wire $0\dec31_lk[0:0] + attribute \src "libresoc.v:81991.3-82051.6" + wire width 2 $0\dec31_out_sel[1:0] + attribute \src "libresoc.v:82296.3-82356.6" + wire width 2 $0\dec31_rc_sel[1:0] + attribute \src "libresoc.v:82723.3-82783.6" + wire $0\dec31_rsrv[0:0] + attribute \src "libresoc.v:82967.3-83027.6" + wire $0\dec31_sgl_pipe[0:0] + attribute \src "libresoc.v:82845.3-82905.6" + wire $0\dec31_sgn[0:0] + attribute \src "libresoc.v:82662.3-82722.6" + wire $0\dec31_sgn_ext[0:0] + attribute \src "libresoc.v:82235.3-82295.6" + wire width 2 $0\dec31_upd[1:0] + attribute \src "libresoc.v:76679.7-76679.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:81747.3-81807.6" + wire width 8 $1\dec31_asmcode[7:0] + attribute \src "libresoc.v:82601.3-82661.6" + wire $1\dec31_br[0:0] + attribute \src "libresoc.v:82052.3-82112.6" + wire width 3 $1\dec31_cr_in[2:0] + attribute \src "libresoc.v:82113.3-82173.6" + wire width 3 $1\dec31_cr_out[2:0] + attribute \src "libresoc.v:82357.3-82417.6" + wire width 2 $1\dec31_cry_in[1:0] + attribute \src "libresoc.v:82540.3-82600.6" + wire $1\dec31_cry_out[0:0] + attribute \src "libresoc.v:81686.3-81746.6" + wire width 5 $1\dec31_form[4:0] + attribute \src "libresoc.v:81564.3-81624.6" + wire width 12 $1\dec31_function_unit[11:0] + attribute \src "libresoc.v:81808.3-81868.6" + wire width 3 $1\dec31_in1_sel[2:0] + attribute \src "libresoc.v:81869.3-81929.6" + wire width 4 $1\dec31_in2_sel[3:0] + attribute \src "libresoc.v:81930.3-81990.6" + wire width 2 $1\dec31_in3_sel[1:0] + attribute \src "libresoc.v:81625.3-81685.6" + wire width 7 $1\dec31_internal_op[6:0] + attribute \src "libresoc.v:82418.3-82478.6" + wire $1\dec31_inv_a[0:0] + attribute \src "libresoc.v:82479.3-82539.6" + wire $1\dec31_inv_out[0:0] + attribute \src "libresoc.v:82784.3-82844.6" + wire $1\dec31_is_32b[0:0] + attribute \src "libresoc.v:82174.3-82234.6" + wire width 4 $1\dec31_ldst_len[3:0] + attribute \src "libresoc.v:82906.3-82966.6" + wire $1\dec31_lk[0:0] + attribute \src "libresoc.v:81991.3-82051.6" + wire width 2 $1\dec31_out_sel[1:0] + attribute \src "libresoc.v:82296.3-82356.6" + wire width 2 $1\dec31_rc_sel[1:0] + attribute \src "libresoc.v:82723.3-82783.6" + wire $1\dec31_rsrv[0:0] + attribute \src "libresoc.v:82967.3-83027.6" + wire $1\dec31_sgl_pipe[0:0] + attribute \src "libresoc.v:82845.3-82905.6" + wire $1\dec31_sgn[0:0] + attribute \src "libresoc.v:82662.3-82722.6" + wire $1\dec31_sgn_ext[0:0] + attribute \src "libresoc.v:82235.3-82295.6" + wire width 2 $1\dec31_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 \dec31_dec_sub0_dec31_dec_sub0_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec_sub0_dec31_dec_sub0_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec31_dec_sub0_dec31_dec_sub0_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec_sub0_dec31_dec_sub0_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 \dec31_dec_sub0_dec31_dec_sub0_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 \dec31_dec_sub0_dec31_dec_sub0_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \dec31_dec_sub0_dec31_dec_sub0_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec31_dec_sub0_dec31_dec_sub0_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute 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\enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \dec31_dec_sub9_dec31_dec_sub9_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec_sub9_dec31_dec_sub9_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec_sub9_dec31_dec_sub9_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec_sub9_dec31_dec_sub9_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \dec31_dec_sub9_dec31_dec_sub9_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec_sub9_dec31_dec_sub9_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec31_dec_sub9_dec31_dec_sub9_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec31_dec_sub9_dec31_dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec_sub9_dec31_dec_sub9_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec_sub9_dec31_dec_sub9_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec_sub9_dec31_dec_sub9_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec31_dec_sub9_dec31_dec_sub9_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \dec31_dec_sub9_opcode_in + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_upd + attribute \src "libresoc.v:76679.7-76679.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:81078.18-81104.4" + cell \dec31_dec_sub0 \dec31_dec_sub0 + connect \dec31_dec_sub0_asmcode \dec31_dec_sub0_dec31_dec_sub0_asmcode + connect \dec31_dec_sub0_br \dec31_dec_sub0_dec31_dec_sub0_br + connect \dec31_dec_sub0_cr_in \dec31_dec_sub0_dec31_dec_sub0_cr_in + connect \dec31_dec_sub0_cr_out \dec31_dec_sub0_dec31_dec_sub0_cr_out + connect \dec31_dec_sub0_cry_in \dec31_dec_sub0_dec31_dec_sub0_cry_in + connect \dec31_dec_sub0_cry_out \dec31_dec_sub0_dec31_dec_sub0_cry_out + connect \dec31_dec_sub0_form \dec31_dec_sub0_dec31_dec_sub0_form + connect \dec31_dec_sub0_function_unit \dec31_dec_sub0_dec31_dec_sub0_function_unit + connect \dec31_dec_sub0_in1_sel \dec31_dec_sub0_dec31_dec_sub0_in1_sel + connect \dec31_dec_sub0_in2_sel \dec31_dec_sub0_dec31_dec_sub0_in2_sel + connect \dec31_dec_sub0_in3_sel \dec31_dec_sub0_dec31_dec_sub0_in3_sel + connect \dec31_dec_sub0_internal_op \dec31_dec_sub0_dec31_dec_sub0_internal_op + connect \dec31_dec_sub0_inv_a \dec31_dec_sub0_dec31_dec_sub0_inv_a + connect \dec31_dec_sub0_inv_out \dec31_dec_sub0_dec31_dec_sub0_inv_out + connect \dec31_dec_sub0_is_32b \dec31_dec_sub0_dec31_dec_sub0_is_32b + connect \dec31_dec_sub0_ldst_len \dec31_dec_sub0_dec31_dec_sub0_ldst_len + connect \dec31_dec_sub0_lk \dec31_dec_sub0_dec31_dec_sub0_lk + connect \dec31_dec_sub0_out_sel \dec31_dec_sub0_dec31_dec_sub0_out_sel + connect \dec31_dec_sub0_rc_sel \dec31_dec_sub0_dec31_dec_sub0_rc_sel + connect \dec31_dec_sub0_rsrv \dec31_dec_sub0_dec31_dec_sub0_rsrv + connect \dec31_dec_sub0_sgl_pipe \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe + connect \dec31_dec_sub0_sgn \dec31_dec_sub0_dec31_dec_sub0_sgn + connect \dec31_dec_sub0_sgn_ext \dec31_dec_sub0_dec31_dec_sub0_sgn_ext + connect \dec31_dec_sub0_upd \dec31_dec_sub0_dec31_dec_sub0_upd + connect \opcode_in \dec31_dec_sub0_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:81105.19-81131.4" + cell \dec31_dec_sub10 \dec31_dec_sub10 + connect \dec31_dec_sub10_asmcode \dec31_dec_sub10_dec31_dec_sub10_asmcode + connect \dec31_dec_sub10_br \dec31_dec_sub10_dec31_dec_sub10_br + connect \dec31_dec_sub10_cr_in \dec31_dec_sub10_dec31_dec_sub10_cr_in + connect \dec31_dec_sub10_cr_out \dec31_dec_sub10_dec31_dec_sub10_cr_out + connect \dec31_dec_sub10_cry_in \dec31_dec_sub10_dec31_dec_sub10_cry_in + connect \dec31_dec_sub10_cry_out \dec31_dec_sub10_dec31_dec_sub10_cry_out + connect \dec31_dec_sub10_form \dec31_dec_sub10_dec31_dec_sub10_form + connect \dec31_dec_sub10_function_unit \dec31_dec_sub10_dec31_dec_sub10_function_unit + connect \dec31_dec_sub10_in1_sel \dec31_dec_sub10_dec31_dec_sub10_in1_sel + connect \dec31_dec_sub10_in2_sel \dec31_dec_sub10_dec31_dec_sub10_in2_sel + connect \dec31_dec_sub10_in3_sel \dec31_dec_sub10_dec31_dec_sub10_in3_sel + connect \dec31_dec_sub10_internal_op \dec31_dec_sub10_dec31_dec_sub10_internal_op + connect \dec31_dec_sub10_inv_a \dec31_dec_sub10_dec31_dec_sub10_inv_a + connect \dec31_dec_sub10_inv_out \dec31_dec_sub10_dec31_dec_sub10_inv_out + connect \dec31_dec_sub10_is_32b \dec31_dec_sub10_dec31_dec_sub10_is_32b + connect \dec31_dec_sub10_ldst_len \dec31_dec_sub10_dec31_dec_sub10_ldst_len + connect \dec31_dec_sub10_lk \dec31_dec_sub10_dec31_dec_sub10_lk + connect \dec31_dec_sub10_out_sel \dec31_dec_sub10_dec31_dec_sub10_out_sel + connect \dec31_dec_sub10_rc_sel \dec31_dec_sub10_dec31_dec_sub10_rc_sel + connect \dec31_dec_sub10_rsrv \dec31_dec_sub10_dec31_dec_sub10_rsrv + connect \dec31_dec_sub10_sgl_pipe \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe + connect \dec31_dec_sub10_sgn \dec31_dec_sub10_dec31_dec_sub10_sgn + connect \dec31_dec_sub10_sgn_ext \dec31_dec_sub10_dec31_dec_sub10_sgn_ext + connect \dec31_dec_sub10_upd \dec31_dec_sub10_dec31_dec_sub10_upd + connect \opcode_in \dec31_dec_sub10_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:81132.19-81158.4" + cell \dec31_dec_sub11 \dec31_dec_sub11 + connect \dec31_dec_sub11_asmcode \dec31_dec_sub11_dec31_dec_sub11_asmcode + connect \dec31_dec_sub11_br \dec31_dec_sub11_dec31_dec_sub11_br + connect \dec31_dec_sub11_cr_in \dec31_dec_sub11_dec31_dec_sub11_cr_in + connect \dec31_dec_sub11_cr_out \dec31_dec_sub11_dec31_dec_sub11_cr_out + connect \dec31_dec_sub11_cry_in \dec31_dec_sub11_dec31_dec_sub11_cry_in + connect \dec31_dec_sub11_cry_out \dec31_dec_sub11_dec31_dec_sub11_cry_out + connect \dec31_dec_sub11_form \dec31_dec_sub11_dec31_dec_sub11_form + connect \dec31_dec_sub11_function_unit \dec31_dec_sub11_dec31_dec_sub11_function_unit + connect \dec31_dec_sub11_in1_sel \dec31_dec_sub11_dec31_dec_sub11_in1_sel + connect \dec31_dec_sub11_in2_sel \dec31_dec_sub11_dec31_dec_sub11_in2_sel + connect \dec31_dec_sub11_in3_sel \dec31_dec_sub11_dec31_dec_sub11_in3_sel + connect \dec31_dec_sub11_internal_op \dec31_dec_sub11_dec31_dec_sub11_internal_op + connect \dec31_dec_sub11_inv_a \dec31_dec_sub11_dec31_dec_sub11_inv_a + connect \dec31_dec_sub11_inv_out \dec31_dec_sub11_dec31_dec_sub11_inv_out + connect \dec31_dec_sub11_is_32b \dec31_dec_sub11_dec31_dec_sub11_is_32b + connect \dec31_dec_sub11_ldst_len \dec31_dec_sub11_dec31_dec_sub11_ldst_len + connect \dec31_dec_sub11_lk \dec31_dec_sub11_dec31_dec_sub11_lk + connect \dec31_dec_sub11_out_sel \dec31_dec_sub11_dec31_dec_sub11_out_sel + connect \dec31_dec_sub11_rc_sel \dec31_dec_sub11_dec31_dec_sub11_rc_sel + connect \dec31_dec_sub11_rsrv \dec31_dec_sub11_dec31_dec_sub11_rsrv + connect \dec31_dec_sub11_sgl_pipe \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe + connect \dec31_dec_sub11_sgn \dec31_dec_sub11_dec31_dec_sub11_sgn + connect \dec31_dec_sub11_sgn_ext \dec31_dec_sub11_dec31_dec_sub11_sgn_ext + connect \dec31_dec_sub11_upd \dec31_dec_sub11_dec31_dec_sub11_upd + connect \opcode_in \dec31_dec_sub11_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:81159.19-81185.4" + cell \dec31_dec_sub15 \dec31_dec_sub15 + connect \dec31_dec_sub15_asmcode \dec31_dec_sub15_dec31_dec_sub15_asmcode + connect \dec31_dec_sub15_br \dec31_dec_sub15_dec31_dec_sub15_br + connect \dec31_dec_sub15_cr_in \dec31_dec_sub15_dec31_dec_sub15_cr_in + connect \dec31_dec_sub15_cr_out \dec31_dec_sub15_dec31_dec_sub15_cr_out + connect \dec31_dec_sub15_cry_in \dec31_dec_sub15_dec31_dec_sub15_cry_in + connect \dec31_dec_sub15_cry_out \dec31_dec_sub15_dec31_dec_sub15_cry_out + connect \dec31_dec_sub15_form \dec31_dec_sub15_dec31_dec_sub15_form + connect \dec31_dec_sub15_function_unit \dec31_dec_sub15_dec31_dec_sub15_function_unit + connect \dec31_dec_sub15_in1_sel \dec31_dec_sub15_dec31_dec_sub15_in1_sel + connect \dec31_dec_sub15_in2_sel \dec31_dec_sub15_dec31_dec_sub15_in2_sel + connect \dec31_dec_sub15_in3_sel \dec31_dec_sub15_dec31_dec_sub15_in3_sel + connect \dec31_dec_sub15_internal_op \dec31_dec_sub15_dec31_dec_sub15_internal_op + connect \dec31_dec_sub15_inv_a \dec31_dec_sub15_dec31_dec_sub15_inv_a + connect \dec31_dec_sub15_inv_out \dec31_dec_sub15_dec31_dec_sub15_inv_out + connect \dec31_dec_sub15_is_32b \dec31_dec_sub15_dec31_dec_sub15_is_32b + connect \dec31_dec_sub15_ldst_len \dec31_dec_sub15_dec31_dec_sub15_ldst_len + connect \dec31_dec_sub15_lk \dec31_dec_sub15_dec31_dec_sub15_lk + connect \dec31_dec_sub15_out_sel \dec31_dec_sub15_dec31_dec_sub15_out_sel + connect \dec31_dec_sub15_rc_sel \dec31_dec_sub15_dec31_dec_sub15_rc_sel + connect \dec31_dec_sub15_rsrv \dec31_dec_sub15_dec31_dec_sub15_rsrv + connect \dec31_dec_sub15_sgl_pipe \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe + connect \dec31_dec_sub15_sgn \dec31_dec_sub15_dec31_dec_sub15_sgn + connect \dec31_dec_sub15_sgn_ext \dec31_dec_sub15_dec31_dec_sub15_sgn_ext + connect \dec31_dec_sub15_upd \dec31_dec_sub15_dec31_dec_sub15_upd + connect \opcode_in \dec31_dec_sub15_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:81186.19-81212.4" + cell \dec31_dec_sub16 \dec31_dec_sub16 + connect \dec31_dec_sub16_asmcode \dec31_dec_sub16_dec31_dec_sub16_asmcode + connect \dec31_dec_sub16_br \dec31_dec_sub16_dec31_dec_sub16_br + connect \dec31_dec_sub16_cr_in \dec31_dec_sub16_dec31_dec_sub16_cr_in + connect \dec31_dec_sub16_cr_out \dec31_dec_sub16_dec31_dec_sub16_cr_out + connect \dec31_dec_sub16_cry_in \dec31_dec_sub16_dec31_dec_sub16_cry_in + connect \dec31_dec_sub16_cry_out \dec31_dec_sub16_dec31_dec_sub16_cry_out + connect \dec31_dec_sub16_form \dec31_dec_sub16_dec31_dec_sub16_form + connect \dec31_dec_sub16_function_unit \dec31_dec_sub16_dec31_dec_sub16_function_unit + connect \dec31_dec_sub16_in1_sel \dec31_dec_sub16_dec31_dec_sub16_in1_sel + connect \dec31_dec_sub16_in2_sel \dec31_dec_sub16_dec31_dec_sub16_in2_sel + connect \dec31_dec_sub16_in3_sel \dec31_dec_sub16_dec31_dec_sub16_in3_sel + connect \dec31_dec_sub16_internal_op \dec31_dec_sub16_dec31_dec_sub16_internal_op + connect \dec31_dec_sub16_inv_a \dec31_dec_sub16_dec31_dec_sub16_inv_a + connect \dec31_dec_sub16_inv_out \dec31_dec_sub16_dec31_dec_sub16_inv_out + connect \dec31_dec_sub16_is_32b \dec31_dec_sub16_dec31_dec_sub16_is_32b + connect \dec31_dec_sub16_ldst_len \dec31_dec_sub16_dec31_dec_sub16_ldst_len + connect \dec31_dec_sub16_lk \dec31_dec_sub16_dec31_dec_sub16_lk + connect \dec31_dec_sub16_out_sel \dec31_dec_sub16_dec31_dec_sub16_out_sel + connect \dec31_dec_sub16_rc_sel \dec31_dec_sub16_dec31_dec_sub16_rc_sel + connect \dec31_dec_sub16_rsrv \dec31_dec_sub16_dec31_dec_sub16_rsrv + connect \dec31_dec_sub16_sgl_pipe \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe + connect \dec31_dec_sub16_sgn \dec31_dec_sub16_dec31_dec_sub16_sgn + connect \dec31_dec_sub16_sgn_ext \dec31_dec_sub16_dec31_dec_sub16_sgn_ext + connect \dec31_dec_sub16_upd \dec31_dec_sub16_dec31_dec_sub16_upd + connect \opcode_in \dec31_dec_sub16_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:81213.19-81239.4" + cell \dec31_dec_sub18 \dec31_dec_sub18 + connect \dec31_dec_sub18_asmcode \dec31_dec_sub18_dec31_dec_sub18_asmcode + connect \dec31_dec_sub18_br \dec31_dec_sub18_dec31_dec_sub18_br + connect \dec31_dec_sub18_cr_in \dec31_dec_sub18_dec31_dec_sub18_cr_in + connect \dec31_dec_sub18_cr_out \dec31_dec_sub18_dec31_dec_sub18_cr_out + connect \dec31_dec_sub18_cry_in \dec31_dec_sub18_dec31_dec_sub18_cry_in + connect \dec31_dec_sub18_cry_out \dec31_dec_sub18_dec31_dec_sub18_cry_out + connect \dec31_dec_sub18_form \dec31_dec_sub18_dec31_dec_sub18_form + connect \dec31_dec_sub18_function_unit \dec31_dec_sub18_dec31_dec_sub18_function_unit + connect \dec31_dec_sub18_in1_sel \dec31_dec_sub18_dec31_dec_sub18_in1_sel + connect \dec31_dec_sub18_in2_sel \dec31_dec_sub18_dec31_dec_sub18_in2_sel + connect \dec31_dec_sub18_in3_sel \dec31_dec_sub18_dec31_dec_sub18_in3_sel + connect \dec31_dec_sub18_internal_op \dec31_dec_sub18_dec31_dec_sub18_internal_op + connect \dec31_dec_sub18_inv_a \dec31_dec_sub18_dec31_dec_sub18_inv_a + connect \dec31_dec_sub18_inv_out \dec31_dec_sub18_dec31_dec_sub18_inv_out + connect \dec31_dec_sub18_is_32b \dec31_dec_sub18_dec31_dec_sub18_is_32b + connect \dec31_dec_sub18_ldst_len \dec31_dec_sub18_dec31_dec_sub18_ldst_len + connect \dec31_dec_sub18_lk \dec31_dec_sub18_dec31_dec_sub18_lk + connect \dec31_dec_sub18_out_sel \dec31_dec_sub18_dec31_dec_sub18_out_sel + connect \dec31_dec_sub18_rc_sel \dec31_dec_sub18_dec31_dec_sub18_rc_sel + connect \dec31_dec_sub18_rsrv \dec31_dec_sub18_dec31_dec_sub18_rsrv + connect \dec31_dec_sub18_sgl_pipe \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe + connect \dec31_dec_sub18_sgn \dec31_dec_sub18_dec31_dec_sub18_sgn + connect \dec31_dec_sub18_sgn_ext \dec31_dec_sub18_dec31_dec_sub18_sgn_ext + connect \dec31_dec_sub18_upd \dec31_dec_sub18_dec31_dec_sub18_upd + connect \opcode_in \dec31_dec_sub18_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:81240.19-81266.4" + cell \dec31_dec_sub19 \dec31_dec_sub19 + connect \dec31_dec_sub19_asmcode \dec31_dec_sub19_dec31_dec_sub19_asmcode + connect \dec31_dec_sub19_br \dec31_dec_sub19_dec31_dec_sub19_br + connect \dec31_dec_sub19_cr_in \dec31_dec_sub19_dec31_dec_sub19_cr_in + connect \dec31_dec_sub19_cr_out \dec31_dec_sub19_dec31_dec_sub19_cr_out + connect \dec31_dec_sub19_cry_in \dec31_dec_sub19_dec31_dec_sub19_cry_in + connect \dec31_dec_sub19_cry_out \dec31_dec_sub19_dec31_dec_sub19_cry_out + connect \dec31_dec_sub19_form \dec31_dec_sub19_dec31_dec_sub19_form + connect \dec31_dec_sub19_function_unit \dec31_dec_sub19_dec31_dec_sub19_function_unit + connect \dec31_dec_sub19_in1_sel \dec31_dec_sub19_dec31_dec_sub19_in1_sel + connect \dec31_dec_sub19_in2_sel \dec31_dec_sub19_dec31_dec_sub19_in2_sel + connect \dec31_dec_sub19_in3_sel \dec31_dec_sub19_dec31_dec_sub19_in3_sel + connect \dec31_dec_sub19_internal_op \dec31_dec_sub19_dec31_dec_sub19_internal_op + connect \dec31_dec_sub19_inv_a \dec31_dec_sub19_dec31_dec_sub19_inv_a + connect \dec31_dec_sub19_inv_out \dec31_dec_sub19_dec31_dec_sub19_inv_out + connect \dec31_dec_sub19_is_32b \dec31_dec_sub19_dec31_dec_sub19_is_32b + connect \dec31_dec_sub19_ldst_len \dec31_dec_sub19_dec31_dec_sub19_ldst_len + connect \dec31_dec_sub19_lk \dec31_dec_sub19_dec31_dec_sub19_lk + connect \dec31_dec_sub19_out_sel \dec31_dec_sub19_dec31_dec_sub19_out_sel + connect \dec31_dec_sub19_rc_sel \dec31_dec_sub19_dec31_dec_sub19_rc_sel + connect \dec31_dec_sub19_rsrv \dec31_dec_sub19_dec31_dec_sub19_rsrv + connect \dec31_dec_sub19_sgl_pipe \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe + connect \dec31_dec_sub19_sgn \dec31_dec_sub19_dec31_dec_sub19_sgn + connect \dec31_dec_sub19_sgn_ext \dec31_dec_sub19_dec31_dec_sub19_sgn_ext + connect \dec31_dec_sub19_upd \dec31_dec_sub19_dec31_dec_sub19_upd + connect \opcode_in \dec31_dec_sub19_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:81267.19-81293.4" + cell \dec31_dec_sub20 \dec31_dec_sub20 + connect \dec31_dec_sub20_asmcode \dec31_dec_sub20_dec31_dec_sub20_asmcode + connect \dec31_dec_sub20_br \dec31_dec_sub20_dec31_dec_sub20_br + connect \dec31_dec_sub20_cr_in \dec31_dec_sub20_dec31_dec_sub20_cr_in + connect \dec31_dec_sub20_cr_out \dec31_dec_sub20_dec31_dec_sub20_cr_out + connect \dec31_dec_sub20_cry_in \dec31_dec_sub20_dec31_dec_sub20_cry_in + connect \dec31_dec_sub20_cry_out \dec31_dec_sub20_dec31_dec_sub20_cry_out + connect \dec31_dec_sub20_form \dec31_dec_sub20_dec31_dec_sub20_form + connect \dec31_dec_sub20_function_unit \dec31_dec_sub20_dec31_dec_sub20_function_unit + connect \dec31_dec_sub20_in1_sel \dec31_dec_sub20_dec31_dec_sub20_in1_sel + connect \dec31_dec_sub20_in2_sel \dec31_dec_sub20_dec31_dec_sub20_in2_sel + connect \dec31_dec_sub20_in3_sel \dec31_dec_sub20_dec31_dec_sub20_in3_sel + connect \dec31_dec_sub20_internal_op \dec31_dec_sub20_dec31_dec_sub20_internal_op + connect \dec31_dec_sub20_inv_a \dec31_dec_sub20_dec31_dec_sub20_inv_a + connect \dec31_dec_sub20_inv_out \dec31_dec_sub20_dec31_dec_sub20_inv_out + connect \dec31_dec_sub20_is_32b \dec31_dec_sub20_dec31_dec_sub20_is_32b + connect \dec31_dec_sub20_ldst_len \dec31_dec_sub20_dec31_dec_sub20_ldst_len + connect \dec31_dec_sub20_lk \dec31_dec_sub20_dec31_dec_sub20_lk + connect \dec31_dec_sub20_out_sel \dec31_dec_sub20_dec31_dec_sub20_out_sel + connect \dec31_dec_sub20_rc_sel \dec31_dec_sub20_dec31_dec_sub20_rc_sel + connect \dec31_dec_sub20_rsrv \dec31_dec_sub20_dec31_dec_sub20_rsrv + connect \dec31_dec_sub20_sgl_pipe \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe + connect \dec31_dec_sub20_sgn \dec31_dec_sub20_dec31_dec_sub20_sgn + connect \dec31_dec_sub20_sgn_ext \dec31_dec_sub20_dec31_dec_sub20_sgn_ext + connect \dec31_dec_sub20_upd \dec31_dec_sub20_dec31_dec_sub20_upd + connect \opcode_in \dec31_dec_sub20_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:81294.19-81320.4" + cell \dec31_dec_sub21 \dec31_dec_sub21 + connect \dec31_dec_sub21_asmcode \dec31_dec_sub21_dec31_dec_sub21_asmcode + connect \dec31_dec_sub21_br \dec31_dec_sub21_dec31_dec_sub21_br + connect \dec31_dec_sub21_cr_in \dec31_dec_sub21_dec31_dec_sub21_cr_in + connect \dec31_dec_sub21_cr_out \dec31_dec_sub21_dec31_dec_sub21_cr_out + connect \dec31_dec_sub21_cry_in \dec31_dec_sub21_dec31_dec_sub21_cry_in + connect \dec31_dec_sub21_cry_out \dec31_dec_sub21_dec31_dec_sub21_cry_out + connect \dec31_dec_sub21_form \dec31_dec_sub21_dec31_dec_sub21_form + connect \dec31_dec_sub21_function_unit \dec31_dec_sub21_dec31_dec_sub21_function_unit + connect \dec31_dec_sub21_in1_sel \dec31_dec_sub21_dec31_dec_sub21_in1_sel + connect \dec31_dec_sub21_in2_sel \dec31_dec_sub21_dec31_dec_sub21_in2_sel + connect \dec31_dec_sub21_in3_sel \dec31_dec_sub21_dec31_dec_sub21_in3_sel + connect \dec31_dec_sub21_internal_op \dec31_dec_sub21_dec31_dec_sub21_internal_op + connect \dec31_dec_sub21_inv_a \dec31_dec_sub21_dec31_dec_sub21_inv_a + connect \dec31_dec_sub21_inv_out \dec31_dec_sub21_dec31_dec_sub21_inv_out + connect \dec31_dec_sub21_is_32b \dec31_dec_sub21_dec31_dec_sub21_is_32b + connect \dec31_dec_sub21_ldst_len \dec31_dec_sub21_dec31_dec_sub21_ldst_len + connect \dec31_dec_sub21_lk \dec31_dec_sub21_dec31_dec_sub21_lk + connect \dec31_dec_sub21_out_sel \dec31_dec_sub21_dec31_dec_sub21_out_sel + connect \dec31_dec_sub21_rc_sel \dec31_dec_sub21_dec31_dec_sub21_rc_sel + connect \dec31_dec_sub21_rsrv \dec31_dec_sub21_dec31_dec_sub21_rsrv + connect \dec31_dec_sub21_sgl_pipe \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe + connect \dec31_dec_sub21_sgn \dec31_dec_sub21_dec31_dec_sub21_sgn + connect \dec31_dec_sub21_sgn_ext \dec31_dec_sub21_dec31_dec_sub21_sgn_ext + connect \dec31_dec_sub21_upd \dec31_dec_sub21_dec31_dec_sub21_upd + connect \opcode_in \dec31_dec_sub21_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:81321.19-81347.4" + cell \dec31_dec_sub22 \dec31_dec_sub22 + connect \dec31_dec_sub22_asmcode \dec31_dec_sub22_dec31_dec_sub22_asmcode + connect \dec31_dec_sub22_br \dec31_dec_sub22_dec31_dec_sub22_br + connect \dec31_dec_sub22_cr_in \dec31_dec_sub22_dec31_dec_sub22_cr_in + connect \dec31_dec_sub22_cr_out \dec31_dec_sub22_dec31_dec_sub22_cr_out + connect \dec31_dec_sub22_cry_in \dec31_dec_sub22_dec31_dec_sub22_cry_in + connect \dec31_dec_sub22_cry_out \dec31_dec_sub22_dec31_dec_sub22_cry_out + connect \dec31_dec_sub22_form \dec31_dec_sub22_dec31_dec_sub22_form + connect \dec31_dec_sub22_function_unit \dec31_dec_sub22_dec31_dec_sub22_function_unit + connect \dec31_dec_sub22_in1_sel \dec31_dec_sub22_dec31_dec_sub22_in1_sel + connect \dec31_dec_sub22_in2_sel \dec31_dec_sub22_dec31_dec_sub22_in2_sel + connect \dec31_dec_sub22_in3_sel \dec31_dec_sub22_dec31_dec_sub22_in3_sel + connect \dec31_dec_sub22_internal_op \dec31_dec_sub22_dec31_dec_sub22_internal_op + connect \dec31_dec_sub22_inv_a \dec31_dec_sub22_dec31_dec_sub22_inv_a + connect \dec31_dec_sub22_inv_out \dec31_dec_sub22_dec31_dec_sub22_inv_out + connect \dec31_dec_sub22_is_32b \dec31_dec_sub22_dec31_dec_sub22_is_32b + connect \dec31_dec_sub22_ldst_len \dec31_dec_sub22_dec31_dec_sub22_ldst_len + connect \dec31_dec_sub22_lk \dec31_dec_sub22_dec31_dec_sub22_lk + connect \dec31_dec_sub22_out_sel \dec31_dec_sub22_dec31_dec_sub22_out_sel + connect \dec31_dec_sub22_rc_sel \dec31_dec_sub22_dec31_dec_sub22_rc_sel + connect \dec31_dec_sub22_rsrv \dec31_dec_sub22_dec31_dec_sub22_rsrv + connect \dec31_dec_sub22_sgl_pipe \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe + connect \dec31_dec_sub22_sgn \dec31_dec_sub22_dec31_dec_sub22_sgn + connect \dec31_dec_sub22_sgn_ext \dec31_dec_sub22_dec31_dec_sub22_sgn_ext + connect \dec31_dec_sub22_upd \dec31_dec_sub22_dec31_dec_sub22_upd + connect \opcode_in \dec31_dec_sub22_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:81348.19-81374.4" + cell \dec31_dec_sub23 \dec31_dec_sub23 + connect \dec31_dec_sub23_asmcode \dec31_dec_sub23_dec31_dec_sub23_asmcode + connect \dec31_dec_sub23_br \dec31_dec_sub23_dec31_dec_sub23_br + connect \dec31_dec_sub23_cr_in \dec31_dec_sub23_dec31_dec_sub23_cr_in + connect \dec31_dec_sub23_cr_out \dec31_dec_sub23_dec31_dec_sub23_cr_out + connect \dec31_dec_sub23_cry_in \dec31_dec_sub23_dec31_dec_sub23_cry_in + connect \dec31_dec_sub23_cry_out \dec31_dec_sub23_dec31_dec_sub23_cry_out + connect \dec31_dec_sub23_form \dec31_dec_sub23_dec31_dec_sub23_form + connect \dec31_dec_sub23_function_unit \dec31_dec_sub23_dec31_dec_sub23_function_unit + connect \dec31_dec_sub23_in1_sel \dec31_dec_sub23_dec31_dec_sub23_in1_sel + connect \dec31_dec_sub23_in2_sel \dec31_dec_sub23_dec31_dec_sub23_in2_sel + connect \dec31_dec_sub23_in3_sel \dec31_dec_sub23_dec31_dec_sub23_in3_sel + connect \dec31_dec_sub23_internal_op \dec31_dec_sub23_dec31_dec_sub23_internal_op + connect \dec31_dec_sub23_inv_a \dec31_dec_sub23_dec31_dec_sub23_inv_a + connect \dec31_dec_sub23_inv_out \dec31_dec_sub23_dec31_dec_sub23_inv_out + connect \dec31_dec_sub23_is_32b \dec31_dec_sub23_dec31_dec_sub23_is_32b + connect \dec31_dec_sub23_ldst_len \dec31_dec_sub23_dec31_dec_sub23_ldst_len + connect \dec31_dec_sub23_lk \dec31_dec_sub23_dec31_dec_sub23_lk + connect \dec31_dec_sub23_out_sel \dec31_dec_sub23_dec31_dec_sub23_out_sel + connect \dec31_dec_sub23_rc_sel \dec31_dec_sub23_dec31_dec_sub23_rc_sel + connect \dec31_dec_sub23_rsrv \dec31_dec_sub23_dec31_dec_sub23_rsrv + connect \dec31_dec_sub23_sgl_pipe \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe + connect \dec31_dec_sub23_sgn \dec31_dec_sub23_dec31_dec_sub23_sgn + connect \dec31_dec_sub23_sgn_ext \dec31_dec_sub23_dec31_dec_sub23_sgn_ext + connect \dec31_dec_sub23_upd \dec31_dec_sub23_dec31_dec_sub23_upd + connect \opcode_in \dec31_dec_sub23_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:81375.19-81401.4" + cell \dec31_dec_sub24 \dec31_dec_sub24 + connect \dec31_dec_sub24_asmcode \dec31_dec_sub24_dec31_dec_sub24_asmcode + connect \dec31_dec_sub24_br \dec31_dec_sub24_dec31_dec_sub24_br + connect \dec31_dec_sub24_cr_in \dec31_dec_sub24_dec31_dec_sub24_cr_in + connect \dec31_dec_sub24_cr_out \dec31_dec_sub24_dec31_dec_sub24_cr_out + connect \dec31_dec_sub24_cry_in \dec31_dec_sub24_dec31_dec_sub24_cry_in + connect \dec31_dec_sub24_cry_out \dec31_dec_sub24_dec31_dec_sub24_cry_out + connect \dec31_dec_sub24_form \dec31_dec_sub24_dec31_dec_sub24_form + connect \dec31_dec_sub24_function_unit \dec31_dec_sub24_dec31_dec_sub24_function_unit + connect \dec31_dec_sub24_in1_sel \dec31_dec_sub24_dec31_dec_sub24_in1_sel + connect \dec31_dec_sub24_in2_sel \dec31_dec_sub24_dec31_dec_sub24_in2_sel + connect \dec31_dec_sub24_in3_sel \dec31_dec_sub24_dec31_dec_sub24_in3_sel + connect \dec31_dec_sub24_internal_op \dec31_dec_sub24_dec31_dec_sub24_internal_op + connect \dec31_dec_sub24_inv_a \dec31_dec_sub24_dec31_dec_sub24_inv_a + connect \dec31_dec_sub24_inv_out \dec31_dec_sub24_dec31_dec_sub24_inv_out + connect \dec31_dec_sub24_is_32b \dec31_dec_sub24_dec31_dec_sub24_is_32b + connect \dec31_dec_sub24_ldst_len \dec31_dec_sub24_dec31_dec_sub24_ldst_len + connect \dec31_dec_sub24_lk \dec31_dec_sub24_dec31_dec_sub24_lk + connect \dec31_dec_sub24_out_sel \dec31_dec_sub24_dec31_dec_sub24_out_sel + connect \dec31_dec_sub24_rc_sel \dec31_dec_sub24_dec31_dec_sub24_rc_sel + connect \dec31_dec_sub24_rsrv \dec31_dec_sub24_dec31_dec_sub24_rsrv + connect \dec31_dec_sub24_sgl_pipe \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe + connect \dec31_dec_sub24_sgn \dec31_dec_sub24_dec31_dec_sub24_sgn + connect \dec31_dec_sub24_sgn_ext \dec31_dec_sub24_dec31_dec_sub24_sgn_ext + connect \dec31_dec_sub24_upd \dec31_dec_sub24_dec31_dec_sub24_upd + connect \opcode_in \dec31_dec_sub24_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:81402.19-81428.4" + cell \dec31_dec_sub26 \dec31_dec_sub26 + connect \dec31_dec_sub26_asmcode \dec31_dec_sub26_dec31_dec_sub26_asmcode + connect \dec31_dec_sub26_br \dec31_dec_sub26_dec31_dec_sub26_br + connect \dec31_dec_sub26_cr_in \dec31_dec_sub26_dec31_dec_sub26_cr_in + connect \dec31_dec_sub26_cr_out \dec31_dec_sub26_dec31_dec_sub26_cr_out + connect \dec31_dec_sub26_cry_in \dec31_dec_sub26_dec31_dec_sub26_cry_in + connect \dec31_dec_sub26_cry_out \dec31_dec_sub26_dec31_dec_sub26_cry_out + connect \dec31_dec_sub26_form \dec31_dec_sub26_dec31_dec_sub26_form + connect \dec31_dec_sub26_function_unit \dec31_dec_sub26_dec31_dec_sub26_function_unit + connect \dec31_dec_sub26_in1_sel \dec31_dec_sub26_dec31_dec_sub26_in1_sel + connect \dec31_dec_sub26_in2_sel \dec31_dec_sub26_dec31_dec_sub26_in2_sel + connect \dec31_dec_sub26_in3_sel \dec31_dec_sub26_dec31_dec_sub26_in3_sel + connect \dec31_dec_sub26_internal_op \dec31_dec_sub26_dec31_dec_sub26_internal_op + connect \dec31_dec_sub26_inv_a \dec31_dec_sub26_dec31_dec_sub26_inv_a + connect \dec31_dec_sub26_inv_out \dec31_dec_sub26_dec31_dec_sub26_inv_out + connect \dec31_dec_sub26_is_32b \dec31_dec_sub26_dec31_dec_sub26_is_32b + connect \dec31_dec_sub26_ldst_len \dec31_dec_sub26_dec31_dec_sub26_ldst_len + connect \dec31_dec_sub26_lk \dec31_dec_sub26_dec31_dec_sub26_lk + connect \dec31_dec_sub26_out_sel \dec31_dec_sub26_dec31_dec_sub26_out_sel + connect \dec31_dec_sub26_rc_sel \dec31_dec_sub26_dec31_dec_sub26_rc_sel + connect \dec31_dec_sub26_rsrv \dec31_dec_sub26_dec31_dec_sub26_rsrv + connect \dec31_dec_sub26_sgl_pipe \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe + connect \dec31_dec_sub26_sgn \dec31_dec_sub26_dec31_dec_sub26_sgn + connect \dec31_dec_sub26_sgn_ext \dec31_dec_sub26_dec31_dec_sub26_sgn_ext + connect \dec31_dec_sub26_upd \dec31_dec_sub26_dec31_dec_sub26_upd + connect \opcode_in \dec31_dec_sub26_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:81429.19-81455.4" + cell \dec31_dec_sub27 \dec31_dec_sub27 + connect \dec31_dec_sub27_asmcode \dec31_dec_sub27_dec31_dec_sub27_asmcode + connect \dec31_dec_sub27_br \dec31_dec_sub27_dec31_dec_sub27_br + connect \dec31_dec_sub27_cr_in \dec31_dec_sub27_dec31_dec_sub27_cr_in + connect \dec31_dec_sub27_cr_out \dec31_dec_sub27_dec31_dec_sub27_cr_out + connect \dec31_dec_sub27_cry_in \dec31_dec_sub27_dec31_dec_sub27_cry_in + connect \dec31_dec_sub27_cry_out \dec31_dec_sub27_dec31_dec_sub27_cry_out + connect \dec31_dec_sub27_form \dec31_dec_sub27_dec31_dec_sub27_form + connect \dec31_dec_sub27_function_unit \dec31_dec_sub27_dec31_dec_sub27_function_unit + connect \dec31_dec_sub27_in1_sel \dec31_dec_sub27_dec31_dec_sub27_in1_sel + connect \dec31_dec_sub27_in2_sel \dec31_dec_sub27_dec31_dec_sub27_in2_sel + connect \dec31_dec_sub27_in3_sel \dec31_dec_sub27_dec31_dec_sub27_in3_sel + connect \dec31_dec_sub27_internal_op \dec31_dec_sub27_dec31_dec_sub27_internal_op + connect \dec31_dec_sub27_inv_a \dec31_dec_sub27_dec31_dec_sub27_inv_a + connect \dec31_dec_sub27_inv_out \dec31_dec_sub27_dec31_dec_sub27_inv_out + connect \dec31_dec_sub27_is_32b \dec31_dec_sub27_dec31_dec_sub27_is_32b + connect \dec31_dec_sub27_ldst_len \dec31_dec_sub27_dec31_dec_sub27_ldst_len + connect \dec31_dec_sub27_lk \dec31_dec_sub27_dec31_dec_sub27_lk + connect \dec31_dec_sub27_out_sel \dec31_dec_sub27_dec31_dec_sub27_out_sel + connect \dec31_dec_sub27_rc_sel \dec31_dec_sub27_dec31_dec_sub27_rc_sel + connect \dec31_dec_sub27_rsrv \dec31_dec_sub27_dec31_dec_sub27_rsrv + connect \dec31_dec_sub27_sgl_pipe \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe + connect \dec31_dec_sub27_sgn \dec31_dec_sub27_dec31_dec_sub27_sgn + connect \dec31_dec_sub27_sgn_ext \dec31_dec_sub27_dec31_dec_sub27_sgn_ext + connect \dec31_dec_sub27_upd \dec31_dec_sub27_dec31_dec_sub27_upd + connect \opcode_in \dec31_dec_sub27_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:81456.19-81482.4" + cell \dec31_dec_sub28 \dec31_dec_sub28 + connect \dec31_dec_sub28_asmcode \dec31_dec_sub28_dec31_dec_sub28_asmcode + connect \dec31_dec_sub28_br \dec31_dec_sub28_dec31_dec_sub28_br + connect \dec31_dec_sub28_cr_in \dec31_dec_sub28_dec31_dec_sub28_cr_in + connect \dec31_dec_sub28_cr_out \dec31_dec_sub28_dec31_dec_sub28_cr_out + connect \dec31_dec_sub28_cry_in \dec31_dec_sub28_dec31_dec_sub28_cry_in + connect \dec31_dec_sub28_cry_out \dec31_dec_sub28_dec31_dec_sub28_cry_out + connect \dec31_dec_sub28_form \dec31_dec_sub28_dec31_dec_sub28_form + connect \dec31_dec_sub28_function_unit \dec31_dec_sub28_dec31_dec_sub28_function_unit + connect \dec31_dec_sub28_in1_sel \dec31_dec_sub28_dec31_dec_sub28_in1_sel + connect \dec31_dec_sub28_in2_sel \dec31_dec_sub28_dec31_dec_sub28_in2_sel + connect \dec31_dec_sub28_in3_sel \dec31_dec_sub28_dec31_dec_sub28_in3_sel + connect \dec31_dec_sub28_internal_op \dec31_dec_sub28_dec31_dec_sub28_internal_op + connect \dec31_dec_sub28_inv_a \dec31_dec_sub28_dec31_dec_sub28_inv_a + connect \dec31_dec_sub28_inv_out \dec31_dec_sub28_dec31_dec_sub28_inv_out + connect \dec31_dec_sub28_is_32b \dec31_dec_sub28_dec31_dec_sub28_is_32b + connect \dec31_dec_sub28_ldst_len \dec31_dec_sub28_dec31_dec_sub28_ldst_len + connect \dec31_dec_sub28_lk \dec31_dec_sub28_dec31_dec_sub28_lk + connect \dec31_dec_sub28_out_sel \dec31_dec_sub28_dec31_dec_sub28_out_sel + connect \dec31_dec_sub28_rc_sel \dec31_dec_sub28_dec31_dec_sub28_rc_sel + connect \dec31_dec_sub28_rsrv \dec31_dec_sub28_dec31_dec_sub28_rsrv + connect \dec31_dec_sub28_sgl_pipe \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe + connect \dec31_dec_sub28_sgn \dec31_dec_sub28_dec31_dec_sub28_sgn + connect \dec31_dec_sub28_sgn_ext \dec31_dec_sub28_dec31_dec_sub28_sgn_ext + connect \dec31_dec_sub28_upd \dec31_dec_sub28_dec31_dec_sub28_upd + connect \opcode_in \dec31_dec_sub28_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:81483.18-81509.4" + cell \dec31_dec_sub4 \dec31_dec_sub4 + connect \dec31_dec_sub4_asmcode \dec31_dec_sub4_dec31_dec_sub4_asmcode + connect \dec31_dec_sub4_br \dec31_dec_sub4_dec31_dec_sub4_br + connect \dec31_dec_sub4_cr_in \dec31_dec_sub4_dec31_dec_sub4_cr_in + connect \dec31_dec_sub4_cr_out \dec31_dec_sub4_dec31_dec_sub4_cr_out + connect \dec31_dec_sub4_cry_in \dec31_dec_sub4_dec31_dec_sub4_cry_in + connect \dec31_dec_sub4_cry_out \dec31_dec_sub4_dec31_dec_sub4_cry_out + connect \dec31_dec_sub4_form \dec31_dec_sub4_dec31_dec_sub4_form + connect \dec31_dec_sub4_function_unit \dec31_dec_sub4_dec31_dec_sub4_function_unit + connect \dec31_dec_sub4_in1_sel \dec31_dec_sub4_dec31_dec_sub4_in1_sel + connect \dec31_dec_sub4_in2_sel \dec31_dec_sub4_dec31_dec_sub4_in2_sel + connect \dec31_dec_sub4_in3_sel \dec31_dec_sub4_dec31_dec_sub4_in3_sel + connect \dec31_dec_sub4_internal_op \dec31_dec_sub4_dec31_dec_sub4_internal_op + connect \dec31_dec_sub4_inv_a \dec31_dec_sub4_dec31_dec_sub4_inv_a + connect \dec31_dec_sub4_inv_out \dec31_dec_sub4_dec31_dec_sub4_inv_out + connect \dec31_dec_sub4_is_32b \dec31_dec_sub4_dec31_dec_sub4_is_32b + connect \dec31_dec_sub4_ldst_len \dec31_dec_sub4_dec31_dec_sub4_ldst_len + connect \dec31_dec_sub4_lk \dec31_dec_sub4_dec31_dec_sub4_lk + connect \dec31_dec_sub4_out_sel \dec31_dec_sub4_dec31_dec_sub4_out_sel + connect \dec31_dec_sub4_rc_sel \dec31_dec_sub4_dec31_dec_sub4_rc_sel + connect \dec31_dec_sub4_rsrv \dec31_dec_sub4_dec31_dec_sub4_rsrv + connect \dec31_dec_sub4_sgl_pipe \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe + connect \dec31_dec_sub4_sgn \dec31_dec_sub4_dec31_dec_sub4_sgn + connect \dec31_dec_sub4_sgn_ext \dec31_dec_sub4_dec31_dec_sub4_sgn_ext + connect \dec31_dec_sub4_upd \dec31_dec_sub4_dec31_dec_sub4_upd + connect \opcode_in \dec31_dec_sub4_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:81510.18-81536.4" + cell \dec31_dec_sub8 \dec31_dec_sub8 + connect \dec31_dec_sub8_asmcode \dec31_dec_sub8_dec31_dec_sub8_asmcode + connect \dec31_dec_sub8_br \dec31_dec_sub8_dec31_dec_sub8_br + connect \dec31_dec_sub8_cr_in \dec31_dec_sub8_dec31_dec_sub8_cr_in + connect \dec31_dec_sub8_cr_out \dec31_dec_sub8_dec31_dec_sub8_cr_out + connect \dec31_dec_sub8_cry_in \dec31_dec_sub8_dec31_dec_sub8_cry_in + connect \dec31_dec_sub8_cry_out \dec31_dec_sub8_dec31_dec_sub8_cry_out + connect \dec31_dec_sub8_form \dec31_dec_sub8_dec31_dec_sub8_form + connect \dec31_dec_sub8_function_unit \dec31_dec_sub8_dec31_dec_sub8_function_unit + connect \dec31_dec_sub8_in1_sel \dec31_dec_sub8_dec31_dec_sub8_in1_sel + connect \dec31_dec_sub8_in2_sel \dec31_dec_sub8_dec31_dec_sub8_in2_sel + connect \dec31_dec_sub8_in3_sel \dec31_dec_sub8_dec31_dec_sub8_in3_sel + connect \dec31_dec_sub8_internal_op \dec31_dec_sub8_dec31_dec_sub8_internal_op + connect \dec31_dec_sub8_inv_a \dec31_dec_sub8_dec31_dec_sub8_inv_a + connect \dec31_dec_sub8_inv_out \dec31_dec_sub8_dec31_dec_sub8_inv_out + connect \dec31_dec_sub8_is_32b \dec31_dec_sub8_dec31_dec_sub8_is_32b + connect \dec31_dec_sub8_ldst_len \dec31_dec_sub8_dec31_dec_sub8_ldst_len + connect \dec31_dec_sub8_lk \dec31_dec_sub8_dec31_dec_sub8_lk + connect \dec31_dec_sub8_out_sel \dec31_dec_sub8_dec31_dec_sub8_out_sel + connect \dec31_dec_sub8_rc_sel \dec31_dec_sub8_dec31_dec_sub8_rc_sel + connect \dec31_dec_sub8_rsrv \dec31_dec_sub8_dec31_dec_sub8_rsrv + connect \dec31_dec_sub8_sgl_pipe \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe + connect \dec31_dec_sub8_sgn \dec31_dec_sub8_dec31_dec_sub8_sgn + connect \dec31_dec_sub8_sgn_ext \dec31_dec_sub8_dec31_dec_sub8_sgn_ext + connect \dec31_dec_sub8_upd \dec31_dec_sub8_dec31_dec_sub8_upd + connect \opcode_in \dec31_dec_sub8_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:81537.18-81563.4" + cell \dec31_dec_sub9 \dec31_dec_sub9 + connect \dec31_dec_sub9_asmcode \dec31_dec_sub9_dec31_dec_sub9_asmcode + connect \dec31_dec_sub9_br \dec31_dec_sub9_dec31_dec_sub9_br + connect \dec31_dec_sub9_cr_in \dec31_dec_sub9_dec31_dec_sub9_cr_in + connect \dec31_dec_sub9_cr_out \dec31_dec_sub9_dec31_dec_sub9_cr_out + connect \dec31_dec_sub9_cry_in \dec31_dec_sub9_dec31_dec_sub9_cry_in + connect \dec31_dec_sub9_cry_out \dec31_dec_sub9_dec31_dec_sub9_cry_out + connect \dec31_dec_sub9_form \dec31_dec_sub9_dec31_dec_sub9_form + connect \dec31_dec_sub9_function_unit \dec31_dec_sub9_dec31_dec_sub9_function_unit + connect \dec31_dec_sub9_in1_sel \dec31_dec_sub9_dec31_dec_sub9_in1_sel + connect \dec31_dec_sub9_in2_sel \dec31_dec_sub9_dec31_dec_sub9_in2_sel + connect \dec31_dec_sub9_in3_sel \dec31_dec_sub9_dec31_dec_sub9_in3_sel + connect \dec31_dec_sub9_internal_op \dec31_dec_sub9_dec31_dec_sub9_internal_op + connect \dec31_dec_sub9_inv_a \dec31_dec_sub9_dec31_dec_sub9_inv_a + connect \dec31_dec_sub9_inv_out \dec31_dec_sub9_dec31_dec_sub9_inv_out + connect \dec31_dec_sub9_is_32b \dec31_dec_sub9_dec31_dec_sub9_is_32b + connect \dec31_dec_sub9_ldst_len \dec31_dec_sub9_dec31_dec_sub9_ldst_len + connect \dec31_dec_sub9_lk \dec31_dec_sub9_dec31_dec_sub9_lk + connect \dec31_dec_sub9_out_sel \dec31_dec_sub9_dec31_dec_sub9_out_sel + connect \dec31_dec_sub9_rc_sel \dec31_dec_sub9_dec31_dec_sub9_rc_sel + connect \dec31_dec_sub9_rsrv \dec31_dec_sub9_dec31_dec_sub9_rsrv + connect \dec31_dec_sub9_sgl_pipe \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe + connect \dec31_dec_sub9_sgn \dec31_dec_sub9_dec31_dec_sub9_sgn + connect \dec31_dec_sub9_sgn_ext \dec31_dec_sub9_dec31_dec_sub9_sgn_ext + connect \dec31_dec_sub9_upd \dec31_dec_sub9_dec31_dec_sub9_upd + connect \opcode_in \dec31_dec_sub9_opcode_in + end + attribute \src "libresoc.v:76679.7-76679.20" + process $proc$libresoc.v:76679$3721 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:81564.3-81624.6" + process $proc$libresoc.v:81564$3697 + assign { } { } + assign { } { } + assign $0\dec31_function_unit[11:0] $1\dec31_function_unit[11:0] + attribute \src "libresoc.v:81565.5-81565.29" + switch \initial + attribute \src "libresoc.v:81565.9-81565.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub10_dec31_dec_sub10_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub28_dec31_dec_sub28_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub0_dec31_dec_sub0_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub26_dec31_dec_sub26_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub19_dec31_dec_sub19_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub22_dec31_dec_sub22_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub9_dec31_dec_sub9_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub11_dec31_dec_sub11_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub27_dec31_dec_sub27_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub15_dec31_dec_sub15_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub20_dec31_dec_sub20_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub21_dec31_dec_sub21_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub23_dec31_dec_sub23_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub16_dec31_dec_sub16_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub18_dec31_dec_sub18_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub8_dec31_dec_sub8_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub24_dec31_dec_sub24_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub4_dec31_dec_sub4_function_unit + case + assign $1\dec31_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_function_unit $0\dec31_function_unit[11:0] + end + attribute \src "libresoc.v:81625.3-81685.6" + process $proc$libresoc.v:81625$3698 + assign { } { } + assign { } { } + assign $0\dec31_internal_op[6:0] $1\dec31_internal_op[6:0] + attribute \src "libresoc.v:81626.5-81626.29" + switch \initial + attribute \src "libresoc.v:81626.9-81626.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub10_dec31_dec_sub10_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub28_dec31_dec_sub28_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub0_dec31_dec_sub0_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub26_dec31_dec_sub26_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub19_dec31_dec_sub19_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub22_dec31_dec_sub22_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub9_dec31_dec_sub9_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub11_dec31_dec_sub11_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub27_dec31_dec_sub27_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub15_dec31_dec_sub15_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub20_dec31_dec_sub20_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub21_dec31_dec_sub21_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub23_dec31_dec_sub23_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub16_dec31_dec_sub16_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub18_dec31_dec_sub18_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub8_dec31_dec_sub8_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub24_dec31_dec_sub24_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub4_dec31_dec_sub4_internal_op + case + assign $1\dec31_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_internal_op $0\dec31_internal_op[6:0] + end + attribute \src "libresoc.v:81686.3-81746.6" + process $proc$libresoc.v:81686$3699 + assign { } { } + assign { } { } + assign $0\dec31_form[4:0] $1\dec31_form[4:0] + attribute \src "libresoc.v:81687.5-81687.29" + switch \initial + attribute \src "libresoc.v:81687.9-81687.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub10_dec31_dec_sub10_form + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub28_dec31_dec_sub28_form + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub0_dec31_dec_sub0_form + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub26_dec31_dec_sub26_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub19_dec31_dec_sub19_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub22_dec31_dec_sub22_form + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub9_dec31_dec_sub9_form + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub11_dec31_dec_sub11_form + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub27_dec31_dec_sub27_form + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub15_dec31_dec_sub15_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub20_dec31_dec_sub20_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub21_dec31_dec_sub21_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub23_dec31_dec_sub23_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub16_dec31_dec_sub16_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub18_dec31_dec_sub18_form + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub8_dec31_dec_sub8_form + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub24_dec31_dec_sub24_form + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub4_dec31_dec_sub4_form + case + assign $1\dec31_form[4:0] 5'00000 + end + sync always + update \dec31_form $0\dec31_form[4:0] + end + attribute \src "libresoc.v:81747.3-81807.6" + process $proc$libresoc.v:81747$3700 + assign { } { } + assign { } { } + assign $0\dec31_asmcode[7:0] $1\dec31_asmcode[7:0] + attribute \src "libresoc.v:81748.5-81748.29" + switch \initial + attribute \src "libresoc.v:81748.9-81748.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub10_dec31_dec_sub10_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub28_dec31_dec_sub28_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub0_dec31_dec_sub0_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub26_dec31_dec_sub26_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub19_dec31_dec_sub19_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub22_dec31_dec_sub22_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub9_dec31_dec_sub9_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub11_dec31_dec_sub11_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub27_dec31_dec_sub27_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub15_dec31_dec_sub15_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub20_dec31_dec_sub20_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub21_dec31_dec_sub21_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub23_dec31_dec_sub23_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub16_dec31_dec_sub16_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub18_dec31_dec_sub18_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub8_dec31_dec_sub8_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub24_dec31_dec_sub24_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub4_dec31_dec_sub4_asmcode + case + assign $1\dec31_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_asmcode $0\dec31_asmcode[7:0] + end + attribute \src "libresoc.v:81808.3-81868.6" + process $proc$libresoc.v:81808$3701 + assign { } { } + assign { } { } + assign $0\dec31_in1_sel[2:0] $1\dec31_in1_sel[2:0] + attribute \src "libresoc.v:81809.5-81809.29" + switch \initial + attribute \src "libresoc.v:81809.9-81809.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub10_dec31_dec_sub10_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub28_dec31_dec_sub28_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub0_dec31_dec_sub0_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub26_dec31_dec_sub26_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub19_dec31_dec_sub19_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub22_dec31_dec_sub22_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub9_dec31_dec_sub9_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub11_dec31_dec_sub11_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub27_dec31_dec_sub27_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub15_dec31_dec_sub15_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub20_dec31_dec_sub20_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub21_dec31_dec_sub21_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub23_dec31_dec_sub23_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub16_dec31_dec_sub16_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub18_dec31_dec_sub18_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub8_dec31_dec_sub8_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub24_dec31_dec_sub24_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub4_dec31_dec_sub4_in1_sel + case + assign $1\dec31_in1_sel[2:0] 3'000 + end + sync always + update \dec31_in1_sel $0\dec31_in1_sel[2:0] + end + attribute \src "libresoc.v:81869.3-81929.6" + process $proc$libresoc.v:81869$3702 + assign { } { } + assign { } { } + assign $0\dec31_in2_sel[3:0] $1\dec31_in2_sel[3:0] + attribute \src "libresoc.v:81870.5-81870.29" + switch \initial + attribute \src "libresoc.v:81870.9-81870.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub10_dec31_dec_sub10_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub28_dec31_dec_sub28_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub0_dec31_dec_sub0_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub26_dec31_dec_sub26_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub19_dec31_dec_sub19_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub22_dec31_dec_sub22_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub9_dec31_dec_sub9_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub11_dec31_dec_sub11_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub27_dec31_dec_sub27_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub15_dec31_dec_sub15_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub20_dec31_dec_sub20_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub21_dec31_dec_sub21_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub23_dec31_dec_sub23_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub16_dec31_dec_sub16_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub18_dec31_dec_sub18_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub8_dec31_dec_sub8_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub24_dec31_dec_sub24_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub4_dec31_dec_sub4_in2_sel + case + assign $1\dec31_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_in2_sel $0\dec31_in2_sel[3:0] + end + attribute \src "libresoc.v:81930.3-81990.6" + process $proc$libresoc.v:81930$3703 + assign { } { } + assign { } { } + assign $0\dec31_in3_sel[1:0] $1\dec31_in3_sel[1:0] + attribute \src "libresoc.v:81931.5-81931.29" + switch \initial + attribute \src "libresoc.v:81931.9-81931.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_in3_sel + case + assign $1\dec31_in3_sel[1:0] 2'00 + end + sync always + update \dec31_in3_sel $0\dec31_in3_sel[1:0] + end + attribute \src "libresoc.v:81991.3-82051.6" + process $proc$libresoc.v:81991$3704 + assign { } { } + assign { } { } + assign $0\dec31_out_sel[1:0] $1\dec31_out_sel[1:0] + attribute \src "libresoc.v:81992.5-81992.29" + switch \initial + attribute \src "libresoc.v:81992.9-81992.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_out_sel + case + assign $1\dec31_out_sel[1:0] 2'00 + end + sync always + update \dec31_out_sel $0\dec31_out_sel[1:0] + end + attribute \src "libresoc.v:82052.3-82112.6" + process $proc$libresoc.v:82052$3705 + assign { } { } + assign { } { } + assign $0\dec31_cr_in[2:0] $1\dec31_cr_in[2:0] + attribute \src "libresoc.v:82053.5-82053.29" + switch \initial + attribute \src "libresoc.v:82053.9-82053.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub10_dec31_dec_sub10_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub28_dec31_dec_sub28_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub0_dec31_dec_sub0_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub26_dec31_dec_sub26_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub19_dec31_dec_sub19_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub22_dec31_dec_sub22_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub9_dec31_dec_sub9_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub11_dec31_dec_sub11_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub27_dec31_dec_sub27_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub15_dec31_dec_sub15_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub20_dec31_dec_sub20_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub21_dec31_dec_sub21_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub23_dec31_dec_sub23_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub16_dec31_dec_sub16_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub18_dec31_dec_sub18_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub8_dec31_dec_sub8_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub24_dec31_dec_sub24_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub4_dec31_dec_sub4_cr_in + case + assign $1\dec31_cr_in[2:0] 3'000 + end + sync always + update \dec31_cr_in $0\dec31_cr_in[2:0] + end + attribute \src "libresoc.v:82113.3-82173.6" + process $proc$libresoc.v:82113$3706 + assign { } { } + assign { } { } + assign $0\dec31_cr_out[2:0] $1\dec31_cr_out[2:0] + attribute \src "libresoc.v:82114.5-82114.29" + switch \initial + attribute \src "libresoc.v:82114.9-82114.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub10_dec31_dec_sub10_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub28_dec31_dec_sub28_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub0_dec31_dec_sub0_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub26_dec31_dec_sub26_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub19_dec31_dec_sub19_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub22_dec31_dec_sub22_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub9_dec31_dec_sub9_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub11_dec31_dec_sub11_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub27_dec31_dec_sub27_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub15_dec31_dec_sub15_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub20_dec31_dec_sub20_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub21_dec31_dec_sub21_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub23_dec31_dec_sub23_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub16_dec31_dec_sub16_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub18_dec31_dec_sub18_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub8_dec31_dec_sub8_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub24_dec31_dec_sub24_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub4_dec31_dec_sub4_cr_out + case + assign $1\dec31_cr_out[2:0] 3'000 + end + sync always + update \dec31_cr_out $0\dec31_cr_out[2:0] + end + attribute \src "libresoc.v:82174.3-82234.6" + process $proc$libresoc.v:82174$3707 + assign { } { } + assign { } { } + assign $0\dec31_ldst_len[3:0] $1\dec31_ldst_len[3:0] + attribute \src "libresoc.v:82175.5-82175.29" + switch \initial + attribute \src "libresoc.v:82175.9-82175.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub10_dec31_dec_sub10_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub28_dec31_dec_sub28_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub0_dec31_dec_sub0_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub26_dec31_dec_sub26_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub19_dec31_dec_sub19_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub22_dec31_dec_sub22_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub9_dec31_dec_sub9_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub11_dec31_dec_sub11_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub27_dec31_dec_sub27_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub15_dec31_dec_sub15_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub20_dec31_dec_sub20_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub21_dec31_dec_sub21_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub23_dec31_dec_sub23_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub16_dec31_dec_sub16_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub18_dec31_dec_sub18_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub8_dec31_dec_sub8_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub24_dec31_dec_sub24_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub4_dec31_dec_sub4_ldst_len + case + assign $1\dec31_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_ldst_len $0\dec31_ldst_len[3:0] + end + attribute \src "libresoc.v:82235.3-82295.6" + process $proc$libresoc.v:82235$3708 + assign { } { } + assign { } { } + assign $0\dec31_upd[1:0] $1\dec31_upd[1:0] + attribute \src "libresoc.v:82236.5-82236.29" + switch \initial + attribute \src "libresoc.v:82236.9-82236.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub10_dec31_dec_sub10_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub28_dec31_dec_sub28_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub0_dec31_dec_sub0_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub26_dec31_dec_sub26_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub19_dec31_dec_sub19_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub22_dec31_dec_sub22_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub9_dec31_dec_sub9_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub11_dec31_dec_sub11_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub27_dec31_dec_sub27_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub15_dec31_dec_sub15_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub20_dec31_dec_sub20_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub21_dec31_dec_sub21_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub23_dec31_dec_sub23_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub16_dec31_dec_sub16_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub18_dec31_dec_sub18_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub8_dec31_dec_sub8_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub24_dec31_dec_sub24_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub4_dec31_dec_sub4_upd + case + assign $1\dec31_upd[1:0] 2'00 + end + sync always + update \dec31_upd $0\dec31_upd[1:0] + end + attribute \src "libresoc.v:82296.3-82356.6" + process $proc$libresoc.v:82296$3709 + assign { } { } + assign { } { } + assign $0\dec31_rc_sel[1:0] $1\dec31_rc_sel[1:0] + attribute \src "libresoc.v:82297.5-82297.29" + switch \initial + attribute \src "libresoc.v:82297.9-82297.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_rc_sel + case + assign $1\dec31_rc_sel[1:0] 2'00 + end + sync always + update \dec31_rc_sel $0\dec31_rc_sel[1:0] + end + attribute \src "libresoc.v:82357.3-82417.6" + process $proc$libresoc.v:82357$3710 + assign { } { } + assign { } { } + assign $0\dec31_cry_in[1:0] $1\dec31_cry_in[1:0] + attribute \src "libresoc.v:82358.5-82358.29" + switch \initial + attribute \src "libresoc.v:82358.9-82358.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub10_dec31_dec_sub10_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub28_dec31_dec_sub28_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub0_dec31_dec_sub0_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub26_dec31_dec_sub26_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub19_dec31_dec_sub19_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub22_dec31_dec_sub22_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub9_dec31_dec_sub9_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub11_dec31_dec_sub11_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub27_dec31_dec_sub27_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub15_dec31_dec_sub15_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub20_dec31_dec_sub20_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub21_dec31_dec_sub21_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub23_dec31_dec_sub23_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub16_dec31_dec_sub16_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub18_dec31_dec_sub18_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub8_dec31_dec_sub8_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub24_dec31_dec_sub24_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub4_dec31_dec_sub4_cry_in + case + assign $1\dec31_cry_in[1:0] 2'00 + end + sync always + update \dec31_cry_in $0\dec31_cry_in[1:0] + end + attribute \src "libresoc.v:82418.3-82478.6" + process $proc$libresoc.v:82418$3711 + assign { } { } + assign { } { } + assign $0\dec31_inv_a[0:0] $1\dec31_inv_a[0:0] + attribute \src "libresoc.v:82419.5-82419.29" + switch \initial + attribute \src "libresoc.v:82419.9-82419.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub10_dec31_dec_sub10_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub28_dec31_dec_sub28_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub0_dec31_dec_sub0_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub26_dec31_dec_sub26_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub19_dec31_dec_sub19_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub22_dec31_dec_sub22_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub9_dec31_dec_sub9_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub11_dec31_dec_sub11_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub27_dec31_dec_sub27_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub15_dec31_dec_sub15_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub20_dec31_dec_sub20_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub21_dec31_dec_sub21_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub23_dec31_dec_sub23_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub16_dec31_dec_sub16_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub18_dec31_dec_sub18_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub8_dec31_dec_sub8_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub24_dec31_dec_sub24_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub4_dec31_dec_sub4_inv_a + case + assign $1\dec31_inv_a[0:0] 1'0 + end + sync always + update \dec31_inv_a $0\dec31_inv_a[0:0] + end + attribute \src "libresoc.v:82479.3-82539.6" + process $proc$libresoc.v:82479$3712 + assign { } { } + assign { } { } + assign $0\dec31_inv_out[0:0] $1\dec31_inv_out[0:0] + attribute \src "libresoc.v:82480.5-82480.29" + switch \initial + attribute \src "libresoc.v:82480.9-82480.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub10_dec31_dec_sub10_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub28_dec31_dec_sub28_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub0_dec31_dec_sub0_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub26_dec31_dec_sub26_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub19_dec31_dec_sub19_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub22_dec31_dec_sub22_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub9_dec31_dec_sub9_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub11_dec31_dec_sub11_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub27_dec31_dec_sub27_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub15_dec31_dec_sub15_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub20_dec31_dec_sub20_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub21_dec31_dec_sub21_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub23_dec31_dec_sub23_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub16_dec31_dec_sub16_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub18_dec31_dec_sub18_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub8_dec31_dec_sub8_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub24_dec31_dec_sub24_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub4_dec31_dec_sub4_inv_out + case + assign $1\dec31_inv_out[0:0] 1'0 + end + sync always + update \dec31_inv_out $0\dec31_inv_out[0:0] + end + attribute \src "libresoc.v:82540.3-82600.6" + process $proc$libresoc.v:82540$3713 + assign { } { } + assign { } { } + assign $0\dec31_cry_out[0:0] $1\dec31_cry_out[0:0] + attribute \src "libresoc.v:82541.5-82541.29" + switch \initial + attribute \src "libresoc.v:82541.9-82541.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub10_dec31_dec_sub10_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub28_dec31_dec_sub28_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub0_dec31_dec_sub0_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub26_dec31_dec_sub26_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub19_dec31_dec_sub19_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub22_dec31_dec_sub22_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub9_dec31_dec_sub9_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub11_dec31_dec_sub11_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub27_dec31_dec_sub27_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub15_dec31_dec_sub15_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub20_dec31_dec_sub20_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub21_dec31_dec_sub21_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub23_dec31_dec_sub23_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub16_dec31_dec_sub16_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub18_dec31_dec_sub18_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub8_dec31_dec_sub8_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub24_dec31_dec_sub24_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub4_dec31_dec_sub4_cry_out + case + assign $1\dec31_cry_out[0:0] 1'0 + end + sync always + update \dec31_cry_out $0\dec31_cry_out[0:0] + end + attribute \src "libresoc.v:82601.3-82661.6" + process $proc$libresoc.v:82601$3714 + assign { } { } + assign { } { } + assign $0\dec31_br[0:0] $1\dec31_br[0:0] + attribute \src "libresoc.v:82602.5-82602.29" + switch \initial + attribute \src "libresoc.v:82602.9-82602.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub10_dec31_dec_sub10_br + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub28_dec31_dec_sub28_br + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub0_dec31_dec_sub0_br + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub26_dec31_dec_sub26_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub19_dec31_dec_sub19_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub22_dec31_dec_sub22_br + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub9_dec31_dec_sub9_br + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub11_dec31_dec_sub11_br + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub27_dec31_dec_sub27_br + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub15_dec31_dec_sub15_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub20_dec31_dec_sub20_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub21_dec31_dec_sub21_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub23_dec31_dec_sub23_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub16_dec31_dec_sub16_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub18_dec31_dec_sub18_br + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub8_dec31_dec_sub8_br + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub24_dec31_dec_sub24_br + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub4_dec31_dec_sub4_br + case + assign $1\dec31_br[0:0] 1'0 + end + sync always + update \dec31_br $0\dec31_br[0:0] + end + attribute \src "libresoc.v:82662.3-82722.6" + process $proc$libresoc.v:82662$3715 + assign { } { } + assign { } { } + assign $0\dec31_sgn_ext[0:0] $1\dec31_sgn_ext[0:0] + attribute \src "libresoc.v:82663.5-82663.29" + switch \initial + attribute \src "libresoc.v:82663.9-82663.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgn_ext + case + assign $1\dec31_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_sgn_ext $0\dec31_sgn_ext[0:0] + end + attribute \src "libresoc.v:82723.3-82783.6" + process $proc$libresoc.v:82723$3716 + assign { } { } + assign { } { } + assign $0\dec31_rsrv[0:0] $1\dec31_rsrv[0:0] + attribute \src "libresoc.v:82724.5-82724.29" + switch \initial + attribute \src "libresoc.v:82724.9-82724.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub10_dec31_dec_sub10_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub28_dec31_dec_sub28_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub0_dec31_dec_sub0_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub26_dec31_dec_sub26_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub19_dec31_dec_sub19_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub22_dec31_dec_sub22_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub9_dec31_dec_sub9_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub11_dec31_dec_sub11_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub27_dec31_dec_sub27_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub15_dec31_dec_sub15_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub20_dec31_dec_sub20_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub21_dec31_dec_sub21_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub23_dec31_dec_sub23_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub16_dec31_dec_sub16_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub18_dec31_dec_sub18_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub8_dec31_dec_sub8_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub24_dec31_dec_sub24_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub4_dec31_dec_sub4_rsrv + case + assign $1\dec31_rsrv[0:0] 1'0 + end + sync always + update \dec31_rsrv $0\dec31_rsrv[0:0] + end + attribute \src "libresoc.v:82784.3-82844.6" + process $proc$libresoc.v:82784$3717 + assign { } { } + assign { } { } + assign $0\dec31_is_32b[0:0] $1\dec31_is_32b[0:0] + attribute \src "libresoc.v:82785.5-82785.29" + switch \initial + attribute \src "libresoc.v:82785.9-82785.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub10_dec31_dec_sub10_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub28_dec31_dec_sub28_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub0_dec31_dec_sub0_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub26_dec31_dec_sub26_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub19_dec31_dec_sub19_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub22_dec31_dec_sub22_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub9_dec31_dec_sub9_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub11_dec31_dec_sub11_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub27_dec31_dec_sub27_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub15_dec31_dec_sub15_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub20_dec31_dec_sub20_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub21_dec31_dec_sub21_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub23_dec31_dec_sub23_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub16_dec31_dec_sub16_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub18_dec31_dec_sub18_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub8_dec31_dec_sub8_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub24_dec31_dec_sub24_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub4_dec31_dec_sub4_is_32b + case + assign $1\dec31_is_32b[0:0] 1'0 + end + sync always + update \dec31_is_32b $0\dec31_is_32b[0:0] + end + attribute \src "libresoc.v:82845.3-82905.6" + process $proc$libresoc.v:82845$3718 + assign { } { } + assign { } { } + assign $0\dec31_sgn[0:0] $1\dec31_sgn[0:0] + attribute \src "libresoc.v:82846.5-82846.29" + switch \initial + attribute \src "libresoc.v:82846.9-82846.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgn + case + assign $1\dec31_sgn[0:0] 1'0 + end + sync always + update \dec31_sgn $0\dec31_sgn[0:0] + end + attribute \src "libresoc.v:82906.3-82966.6" + process $proc$libresoc.v:82906$3719 + assign { } { } + assign { } { } + assign $0\dec31_lk[0:0] $1\dec31_lk[0:0] + attribute \src "libresoc.v:82907.5-82907.29" + switch \initial + attribute \src "libresoc.v:82907.9-82907.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub10_dec31_dec_sub10_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub28_dec31_dec_sub28_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub0_dec31_dec_sub0_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub26_dec31_dec_sub26_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub19_dec31_dec_sub19_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub22_dec31_dec_sub22_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub9_dec31_dec_sub9_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub11_dec31_dec_sub11_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub27_dec31_dec_sub27_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub15_dec31_dec_sub15_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub20_dec31_dec_sub20_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub21_dec31_dec_sub21_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub23_dec31_dec_sub23_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub16_dec31_dec_sub16_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub18_dec31_dec_sub18_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub8_dec31_dec_sub8_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub24_dec31_dec_sub24_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub4_dec31_dec_sub4_lk + case + assign $1\dec31_lk[0:0] 1'0 + end + sync always + update \dec31_lk $0\dec31_lk[0:0] + end + attribute \src "libresoc.v:82967.3-83027.6" + process $proc$libresoc.v:82967$3720 + assign { } { } + assign { } { } + assign $0\dec31_sgl_pipe[0:0] $1\dec31_sgl_pipe[0:0] + attribute \src "libresoc.v:82968.5-82968.29" + switch \initial + attribute \src "libresoc.v:82968.9-82968.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe + case + assign $1\dec31_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_sgl_pipe $0\dec31_sgl_pipe[0:0] + end + connect \dec31_dec_sub4_opcode_in \opcode_in + connect \dec31_dec_sub24_opcode_in \opcode_in + connect \dec31_dec_sub8_opcode_in \opcode_in + connect \dec31_dec_sub18_opcode_in \opcode_in + connect \dec31_dec_sub16_opcode_in \opcode_in + connect \dec31_dec_sub23_opcode_in \opcode_in + connect \dec31_dec_sub21_opcode_in \opcode_in + connect \dec31_dec_sub20_opcode_in \opcode_in + connect \dec31_dec_sub15_opcode_in \opcode_in + connect \dec31_dec_sub27_opcode_in \opcode_in + connect \dec31_dec_sub11_opcode_in \opcode_in + connect \dec31_dec_sub9_opcode_in \opcode_in + connect \dec31_dec_sub22_opcode_in \opcode_in + connect \dec31_dec_sub19_opcode_in \opcode_in + connect \dec31_dec_sub26_opcode_in \opcode_in + connect \dec31_dec_sub0_opcode_in \opcode_in + connect \dec31_dec_sub28_opcode_in \opcode_in + connect \dec31_dec_sub10_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:83052.1-83767.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub0" +attribute \generator "nMigen" +module \dec31_dec_sub0 + attribute \src "libresoc.v:83405.3-83423.6" + wire width 8 $0\dec31_dec_sub0_asmcode[7:0] + attribute \src "libresoc.v:83481.3-83499.6" + wire $0\dec31_dec_sub0_br[0:0] + attribute \src "libresoc.v:83728.3-83746.6" + wire width 3 $0\dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:83747.3-83765.6" + wire width 3 $0\dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:83386.3-83404.6" + wire width 2 $0\dec31_dec_sub0_cry_in[1:0] + attribute \src "libresoc.v:83462.3-83480.6" + wire $0\dec31_dec_sub0_cry_out[0:0] + attribute \src "libresoc.v:83633.3-83651.6" + wire width 5 $0\dec31_dec_sub0_form[4:0] + attribute \src "libresoc.v:83310.3-83328.6" + wire width 12 $0\dec31_dec_sub0_function_unit[11:0] + attribute \src "libresoc.v:83652.3-83670.6" + wire width 3 $0\dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:83671.3-83689.6" + wire width 4 $0\dec31_dec_sub0_in2_sel[3:0] + attribute \src "libresoc.v:83690.3-83708.6" + wire width 2 $0\dec31_dec_sub0_in3_sel[1:0] + attribute \src "libresoc.v:83519.3-83537.6" + wire width 7 $0\dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:83424.3-83442.6" + wire $0\dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:83443.3-83461.6" + wire $0\dec31_dec_sub0_inv_out[0:0] + attribute \src "libresoc.v:83557.3-83575.6" + wire $0\dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:83329.3-83347.6" + wire width 4 $0\dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:83595.3-83613.6" + wire $0\dec31_dec_sub0_lk[0:0] + attribute \src "libresoc.v:83709.3-83727.6" + wire width 2 $0\dec31_dec_sub0_out_sel[1:0] + attribute \src "libresoc.v:83367.3-83385.6" + wire width 2 $0\dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:83538.3-83556.6" + wire $0\dec31_dec_sub0_rsrv[0:0] + attribute \src "libresoc.v:83614.3-83632.6" + wire $0\dec31_dec_sub0_sgl_pipe[0:0] + attribute \src "libresoc.v:83576.3-83594.6" + wire $0\dec31_dec_sub0_sgn[0:0] + attribute \src "libresoc.v:83500.3-83518.6" + wire $0\dec31_dec_sub0_sgn_ext[0:0] + attribute \src "libresoc.v:83348.3-83366.6" + wire width 2 $0\dec31_dec_sub0_upd[1:0] + attribute \src "libresoc.v:83053.7-83053.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:83405.3-83423.6" + wire width 8 $1\dec31_dec_sub0_asmcode[7:0] + attribute \src "libresoc.v:83481.3-83499.6" + wire $1\dec31_dec_sub0_br[0:0] + attribute \src "libresoc.v:83728.3-83746.6" + wire width 3 $1\dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:83747.3-83765.6" + wire width 3 $1\dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:83386.3-83404.6" + wire width 2 $1\dec31_dec_sub0_cry_in[1:0] + attribute \src "libresoc.v:83462.3-83480.6" + wire $1\dec31_dec_sub0_cry_out[0:0] + attribute \src "libresoc.v:83633.3-83651.6" + wire width 5 $1\dec31_dec_sub0_form[4:0] + attribute \src "libresoc.v:83310.3-83328.6" + wire width 12 $1\dec31_dec_sub0_function_unit[11:0] + attribute \src "libresoc.v:83652.3-83670.6" + wire width 3 $1\dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:83671.3-83689.6" + wire width 4 $1\dec31_dec_sub0_in2_sel[3:0] + attribute \src "libresoc.v:83690.3-83708.6" + wire width 2 $1\dec31_dec_sub0_in3_sel[1:0] + attribute \src "libresoc.v:83519.3-83537.6" + wire width 7 $1\dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:83424.3-83442.6" + wire $1\dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:83443.3-83461.6" + wire $1\dec31_dec_sub0_inv_out[0:0] + attribute \src "libresoc.v:83557.3-83575.6" + wire $1\dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:83329.3-83347.6" + wire width 4 $1\dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:83595.3-83613.6" + wire $1\dec31_dec_sub0_lk[0:0] + attribute \src "libresoc.v:83709.3-83727.6" + wire width 2 $1\dec31_dec_sub0_out_sel[1:0] + attribute \src "libresoc.v:83367.3-83385.6" + wire width 2 $1\dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:83538.3-83556.6" + wire $1\dec31_dec_sub0_rsrv[0:0] + attribute \src "libresoc.v:83614.3-83632.6" + wire $1\dec31_dec_sub0_sgl_pipe[0:0] + attribute \src "libresoc.v:83576.3-83594.6" + wire $1\dec31_dec_sub0_sgn[0:0] + attribute \src "libresoc.v:83500.3-83518.6" + wire $1\dec31_dec_sub0_sgn_ext[0:0] + attribute \src "libresoc.v:83348.3-83366.6" + wire width 2 $1\dec31_dec_sub0_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub0_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub0_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub0_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub0_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub0_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub0_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub0_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub0_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub0_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub0_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub0_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub0_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub0_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub0_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub0_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub0_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub0_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub0_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub0_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub0_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub0_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub0_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub0_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub0_upd + attribute \src "libresoc.v:83053.7-83053.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:83053.7-83053.20" + process $proc$libresoc.v:83053$3746 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:83310.3-83328.6" + process $proc$libresoc.v:83310$3722 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_function_unit[11:0] $1\dec31_dec_sub0_function_unit[11:0] + attribute \src "libresoc.v:83311.5-83311.29" + switch \initial + attribute \src "libresoc.v:83311.9-83311.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[11:0] 12'000001000000 + case + assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub0_function_unit $0\dec31_dec_sub0_function_unit[11:0] + end + attribute \src "libresoc.v:83329.3-83347.6" + process $proc$libresoc.v:83329$3723 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_ldst_len[3:0] $1\dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:83330.5-83330.29" + switch \initial + attribute \src "libresoc.v:83330.9-83330.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub0_ldst_len $0\dec31_dec_sub0_ldst_len[3:0] + end + attribute \src "libresoc.v:83348.3-83366.6" + process $proc$libresoc.v:83348$3724 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_upd[1:0] $1\dec31_dec_sub0_upd[1:0] + attribute \src "libresoc.v:83349.5-83349.29" + switch \initial + attribute \src "libresoc.v:83349.9-83349.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_upd $0\dec31_dec_sub0_upd[1:0] + end + attribute \src "libresoc.v:83367.3-83385.6" + process $proc$libresoc.v:83367$3725 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_rc_sel[1:0] $1\dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:83368.5-83368.29" + switch \initial + attribute \src "libresoc.v:83368.9-83368.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_rc_sel $0\dec31_dec_sub0_rc_sel[1:0] + end + attribute \src "libresoc.v:83386.3-83404.6" + process $proc$libresoc.v:83386$3726 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cry_in[1:0] $1\dec31_dec_sub0_cry_in[1:0] + attribute \src "libresoc.v:83387.5-83387.29" + switch \initial + attribute \src "libresoc.v:83387.9-83387.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_cry_in $0\dec31_dec_sub0_cry_in[1:0] + end + attribute \src "libresoc.v:83405.3-83423.6" + process $proc$libresoc.v:83405$3727 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_asmcode[7:0] $1\dec31_dec_sub0_asmcode[7:0] + attribute \src "libresoc.v:83406.5-83406.29" + switch \initial + attribute \src "libresoc.v:83406.9-83406.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_asmcode[7:0] 8'10011011 + case + assign $1\dec31_dec_sub0_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub0_asmcode $0\dec31_dec_sub0_asmcode[7:0] + end + attribute \src "libresoc.v:83424.3-83442.6" + process $proc$libresoc.v:83424$3728 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_inv_a[0:0] $1\dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:83425.5-83425.29" + switch \initial + attribute \src "libresoc.v:83425.9-83425.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_inv_a $0\dec31_dec_sub0_inv_a[0:0] + end + attribute \src "libresoc.v:83443.3-83461.6" + process $proc$libresoc.v:83443$3729 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_inv_out[0:0] $1\dec31_dec_sub0_inv_out[0:0] + attribute \src "libresoc.v:83444.5-83444.29" + switch \initial + attribute \src "libresoc.v:83444.9-83444.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_inv_out $0\dec31_dec_sub0_inv_out[0:0] + end + attribute \src "libresoc.v:83462.3-83480.6" + process $proc$libresoc.v:83462$3730 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cry_out[0:0] $1\dec31_dec_sub0_cry_out[0:0] + attribute \src "libresoc.v:83463.5-83463.29" + switch \initial + attribute \src "libresoc.v:83463.9-83463.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_cry_out $0\dec31_dec_sub0_cry_out[0:0] + end + attribute \src "libresoc.v:83481.3-83499.6" + process $proc$libresoc.v:83481$3731 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_br[0:0] $1\dec31_dec_sub0_br[0:0] + attribute \src "libresoc.v:83482.5-83482.29" + switch \initial + attribute \src "libresoc.v:83482.9-83482.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_br[0:0] 1'0 + case + assign $1\dec31_dec_sub0_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_br $0\dec31_dec_sub0_br[0:0] + end + attribute \src "libresoc.v:83500.3-83518.6" + process $proc$libresoc.v:83500$3732 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sgn_ext[0:0] $1\dec31_dec_sub0_sgn_ext[0:0] + attribute \src "libresoc.v:83501.5-83501.29" + switch \initial + attribute \src "libresoc.v:83501.9-83501.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_sgn_ext $0\dec31_dec_sub0_sgn_ext[0:0] + end + attribute \src "libresoc.v:83519.3-83537.6" + process $proc$libresoc.v:83519$3733 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_internal_op[6:0] $1\dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:83520.5-83520.29" + switch \initial + attribute \src "libresoc.v:83520.9-83520.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0111011 + case + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub0_internal_op $0\dec31_dec_sub0_internal_op[6:0] + end + attribute \src "libresoc.v:83538.3-83556.6" + process $proc$libresoc.v:83538$3734 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_rsrv[0:0] $1\dec31_dec_sub0_rsrv[0:0] + attribute \src "libresoc.v:83539.5-83539.29" + switch \initial + attribute \src "libresoc.v:83539.9-83539.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_rsrv $0\dec31_dec_sub0_rsrv[0:0] + end + attribute \src "libresoc.v:83557.3-83575.6" + process $proc$libresoc.v:83557$3735 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_is_32b[0:0] $1\dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:83558.5-83558.29" + switch \initial + attribute \src "libresoc.v:83558.9-83558.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_is_32b $0\dec31_dec_sub0_is_32b[0:0] + end + attribute \src "libresoc.v:83576.3-83594.6" + process $proc$libresoc.v:83576$3736 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sgn[0:0] $1\dec31_dec_sub0_sgn[0:0] + attribute \src "libresoc.v:83577.5-83577.29" + switch \initial + attribute \src "libresoc.v:83577.9-83577.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_sgn $0\dec31_dec_sub0_sgn[0:0] + end + attribute \src "libresoc.v:83595.3-83613.6" + process $proc$libresoc.v:83595$3737 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_lk[0:0] $1\dec31_dec_sub0_lk[0:0] + attribute \src "libresoc.v:83596.5-83596.29" + switch \initial + attribute \src "libresoc.v:83596.9-83596.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_lk $0\dec31_dec_sub0_lk[0:0] + end + attribute \src "libresoc.v:83614.3-83632.6" + process $proc$libresoc.v:83614$3738 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sgl_pipe[0:0] $1\dec31_dec_sub0_sgl_pipe[0:0] + attribute \src "libresoc.v:83615.5-83615.29" + switch \initial + attribute \src "libresoc.v:83615.9-83615.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_sgl_pipe $0\dec31_dec_sub0_sgl_pipe[0:0] + end + attribute \src "libresoc.v:83633.3-83651.6" + process $proc$libresoc.v:83633$3739 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_form[4:0] $1\dec31_dec_sub0_form[4:0] + attribute \src "libresoc.v:83634.5-83634.29" + switch \initial + attribute \src "libresoc.v:83634.9-83634.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_form[4:0] 5'11000 + case + assign $1\dec31_dec_sub0_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub0_form $0\dec31_dec_sub0_form[4:0] + end + attribute \src "libresoc.v:83652.3-83670.6" + process $proc$libresoc.v:83652$3740 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_in1_sel[2:0] $1\dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:83653.5-83653.29" + switch \initial + attribute \src "libresoc.v:83653.9-83653.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_in1_sel $0\dec31_dec_sub0_in1_sel[2:0] + end + attribute \src "libresoc.v:83671.3-83689.6" + process $proc$libresoc.v:83671$3741 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_in2_sel[3:0] $1\dec31_dec_sub0_in2_sel[3:0] + attribute \src "libresoc.v:83672.5-83672.29" + switch \initial + attribute \src "libresoc.v:83672.9-83672.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub0_in2_sel $0\dec31_dec_sub0_in2_sel[3:0] + end + attribute \src "libresoc.v:83690.3-83708.6" + process $proc$libresoc.v:83690$3742 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_in3_sel[1:0] $1\dec31_dec_sub0_in3_sel[1:0] + attribute \src "libresoc.v:83691.5-83691.29" + switch \initial + attribute \src "libresoc.v:83691.9-83691.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_in3_sel $0\dec31_dec_sub0_in3_sel[1:0] + end + attribute \src "libresoc.v:83709.3-83727.6" + process $proc$libresoc.v:83709$3743 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_out_sel[1:0] $1\dec31_dec_sub0_out_sel[1:0] + attribute \src "libresoc.v:83710.5-83710.29" + switch \initial + attribute \src "libresoc.v:83710.9-83710.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_out_sel $0\dec31_dec_sub0_out_sel[1:0] + end + attribute \src "libresoc.v:83728.3-83746.6" + process $proc$libresoc.v:83728$3744 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cr_in[2:0] $1\dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:83729.5-83729.29" + switch \initial + attribute \src "libresoc.v:83729.9-83729.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'011 + case + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_cr_in $0\dec31_dec_sub0_cr_in[2:0] + end + attribute \src "libresoc.v:83747.3-83765.6" + process $proc$libresoc.v:83747$3745 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cr_out[2:0] $1\dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:83748.5-83748.29" + switch \initial + attribute \src "libresoc.v:83748.9-83748.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub0_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_cr_out $0\dec31_dec_sub0_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:83771.1-84918.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub10" +attribute \generator "nMigen" +module \dec31_dec_sub10 + attribute \src "libresoc.v:84214.3-84250.6" + wire width 8 $0\dec31_dec_sub10_asmcode[7:0] + attribute \src "libresoc.v:84362.3-84398.6" + wire $0\dec31_dec_sub10_br[0:0] + attribute \src "libresoc.v:84843.3-84879.6" + wire width 3 $0\dec31_dec_sub10_cr_in[2:0] + attribute \src "libresoc.v:84880.3-84916.6" + wire width 3 $0\dec31_dec_sub10_cr_out[2:0] + attribute \src "libresoc.v:84177.3-84213.6" + wire width 2 $0\dec31_dec_sub10_cry_in[1:0] + attribute \src "libresoc.v:84325.3-84361.6" + wire $0\dec31_dec_sub10_cry_out[0:0] + attribute \src "libresoc.v:84658.3-84694.6" + wire width 5 $0\dec31_dec_sub10_form[4:0] + attribute \src "libresoc.v:84029.3-84065.6" + wire width 12 $0\dec31_dec_sub10_function_unit[11:0] + attribute \src "libresoc.v:84695.3-84731.6" + wire width 3 $0\dec31_dec_sub10_in1_sel[2:0] + attribute \src "libresoc.v:84732.3-84768.6" + wire width 4 $0\dec31_dec_sub10_in2_sel[3:0] + attribute \src "libresoc.v:84769.3-84805.6" + wire width 2 $0\dec31_dec_sub10_in3_sel[1:0] + attribute \src "libresoc.v:84436.3-84472.6" + wire width 7 $0\dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:84251.3-84287.6" + wire $0\dec31_dec_sub10_inv_a[0:0] + attribute \src "libresoc.v:84288.3-84324.6" + wire $0\dec31_dec_sub10_inv_out[0:0] + attribute \src "libresoc.v:84510.3-84546.6" + wire $0\dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:84066.3-84102.6" + wire width 4 $0\dec31_dec_sub10_ldst_len[3:0] + attribute \src "libresoc.v:84584.3-84620.6" + wire $0\dec31_dec_sub10_lk[0:0] + attribute \src "libresoc.v:84806.3-84842.6" + wire width 2 $0\dec31_dec_sub10_out_sel[1:0] + attribute \src "libresoc.v:84140.3-84176.6" + wire width 2 $0\dec31_dec_sub10_rc_sel[1:0] + attribute \src "libresoc.v:84473.3-84509.6" + wire $0\dec31_dec_sub10_rsrv[0:0] + attribute \src "libresoc.v:84621.3-84657.6" + wire $0\dec31_dec_sub10_sgl_pipe[0:0] + attribute \src "libresoc.v:84547.3-84583.6" + wire $0\dec31_dec_sub10_sgn[0:0] + attribute \src "libresoc.v:84399.3-84435.6" + wire $0\dec31_dec_sub10_sgn_ext[0:0] + attribute \src "libresoc.v:84103.3-84139.6" + wire width 2 $0\dec31_dec_sub10_upd[1:0] + attribute \src "libresoc.v:83772.7-83772.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:84214.3-84250.6" + wire width 8 $1\dec31_dec_sub10_asmcode[7:0] + attribute \src "libresoc.v:84362.3-84398.6" + wire $1\dec31_dec_sub10_br[0:0] + attribute \src "libresoc.v:84843.3-84879.6" + wire width 3 $1\dec31_dec_sub10_cr_in[2:0] + attribute \src "libresoc.v:84880.3-84916.6" + wire width 3 $1\dec31_dec_sub10_cr_out[2:0] + attribute \src "libresoc.v:84177.3-84213.6" + wire width 2 $1\dec31_dec_sub10_cry_in[1:0] + attribute \src "libresoc.v:84325.3-84361.6" + wire $1\dec31_dec_sub10_cry_out[0:0] + attribute \src "libresoc.v:84658.3-84694.6" + wire width 5 $1\dec31_dec_sub10_form[4:0] + attribute \src "libresoc.v:84029.3-84065.6" + wire width 12 $1\dec31_dec_sub10_function_unit[11:0] + attribute \src "libresoc.v:84695.3-84731.6" + wire width 3 $1\dec31_dec_sub10_in1_sel[2:0] + attribute \src "libresoc.v:84732.3-84768.6" + wire width 4 $1\dec31_dec_sub10_in2_sel[3:0] + attribute \src "libresoc.v:84769.3-84805.6" + wire width 2 $1\dec31_dec_sub10_in3_sel[1:0] + attribute \src "libresoc.v:84436.3-84472.6" + wire width 7 $1\dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:84251.3-84287.6" + wire $1\dec31_dec_sub10_inv_a[0:0] + attribute \src "libresoc.v:84288.3-84324.6" + wire $1\dec31_dec_sub10_inv_out[0:0] + attribute \src "libresoc.v:84510.3-84546.6" + wire $1\dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:84066.3-84102.6" + wire width 4 $1\dec31_dec_sub10_ldst_len[3:0] + attribute \src "libresoc.v:84584.3-84620.6" + wire $1\dec31_dec_sub10_lk[0:0] + attribute \src "libresoc.v:84806.3-84842.6" + wire width 2 $1\dec31_dec_sub10_out_sel[1:0] + attribute \src "libresoc.v:84140.3-84176.6" + wire width 2 $1\dec31_dec_sub10_rc_sel[1:0] + attribute \src "libresoc.v:84473.3-84509.6" + wire $1\dec31_dec_sub10_rsrv[0:0] + attribute \src "libresoc.v:84621.3-84657.6" + wire $1\dec31_dec_sub10_sgl_pipe[0:0] + attribute \src "libresoc.v:84547.3-84583.6" + wire $1\dec31_dec_sub10_sgn[0:0] + attribute \src "libresoc.v:84399.3-84435.6" + wire $1\dec31_dec_sub10_sgn_ext[0:0] + attribute \src "libresoc.v:84103.3-84139.6" + wire width 2 $1\dec31_dec_sub10_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub10_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub10_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub10_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub10_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub10_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub10_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub10_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub10_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub10_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub10_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub10_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub10_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub10_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub10_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub10_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub10_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub10_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub10_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub10_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub10_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub10_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub10_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub10_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub10_upd + attribute \src "libresoc.v:83772.7-83772.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:145" - wire width 32 \log_dmi_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:145" - wire width 32 \log_dmi_addr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" - wire width 64 \log_dmi_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:119" - wire width 32 \log_write_addr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:134" - wire width 64 \stat_reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137" - wire \stopping - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137" - wire \stopping$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:102" - wire input 9 \terminate_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141" - wire \terminated - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141" - wire \terminated$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:122" - wire \terminated_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $add $add$libresoc.v:717$89 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \log_dmi_addr [1:0] - connect \B 1'1 - connect \Y $add$libresoc.v:717$89_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:83772.7-83772.20" + process $proc$libresoc.v:83772$3771 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:708$80 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B \$7 - connect \Y $and$libresoc.v:708$80_Y + attribute \src "libresoc.v:84029.3-84065.6" + process $proc$libresoc.v:84029$3747 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_function_unit[11:0] $1\dec31_dec_sub10_function_unit[11:0] + attribute \src "libresoc.v:84030.5-84030.29" + switch \initial + attribute \src "libresoc.v:84030.9-84030.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + case + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub10_function_unit $0\dec31_dec_sub10_function_unit[11:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:711$83 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B \$101 - connect \Y $and$libresoc.v:711$83_Y + attribute \src "libresoc.v:84066.3-84102.6" + process $proc$libresoc.v:84066$3748 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_ldst_len[3:0] $1\dec31_dec_sub10_ldst_len[3:0] + attribute \src "libresoc.v:84067.5-84067.29" + switch \initial + attribute \src "libresoc.v:84067.9-84067.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub10_ldst_len $0\dec31_dec_sub10_ldst_len[3:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:713$85 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B \$105 - connect \Y $and$libresoc.v:713$85_Y + attribute \src "libresoc.v:84103.3-84139.6" + process $proc$libresoc.v:84103$3749 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_upd[1:0] $1\dec31_dec_sub10_upd[1:0] + attribute \src "libresoc.v:84104.5-84104.29" + switch \initial + attribute \src "libresoc.v:84104.9-84104.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_upd $0\dec31_dec_sub10_upd[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242" - cell $and $and$libresoc.v:720$92 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B \$118 - connect \Y $and$libresoc.v:720$92_Y + attribute \src "libresoc.v:84140.3-84176.6" + process $proc$libresoc.v:84140$3750 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_rc_sel[1:0] $1\dec31_dec_sub10_rc_sel[1:0] + attribute \src "libresoc.v:84141.5-84141.29" + switch \initial + attribute \src "libresoc.v:84141.9-84141.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_rc_sel $0\dec31_dec_sub10_rc_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254" - cell $and $and$libresoc.v:722$94 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \stopping - connect \B \$122 - connect \Y $and$libresoc.v:722$94_Y + attribute \src "libresoc.v:84177.3-84213.6" + process $proc$libresoc.v:84177$3751 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_cry_in[1:0] $1\dec31_dec_sub10_cry_in[1:0] + attribute \src "libresoc.v:84178.5-84178.29" + switch \initial + attribute \src "libresoc.v:84178.9-84178.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + case + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_cry_in $0\dec31_dec_sub10_cry_in[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:727$99 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B \$17 - connect \Y $and$libresoc.v:727$99_Y + attribute \src "libresoc.v:84214.3-84250.6" + process $proc$libresoc.v:84214$3752 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_asmcode[7:0] $1\dec31_dec_sub10_asmcode[7:0] + attribute \src "libresoc.v:84215.5-84215.29" + switch \initial + attribute \src "libresoc.v:84215.9-84215.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001110 + case + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub10_asmcode $0\dec31_dec_sub10_asmcode[7:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:729$101 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B \$21 - connect \Y $and$libresoc.v:729$101_Y + attribute \src "libresoc.v:84251.3-84287.6" + process $proc$libresoc.v:84251$3753 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_inv_a[0:0] $1\dec31_dec_sub10_inv_a[0:0] + attribute \src "libresoc.v:84252.5-84252.29" + switch \initial + attribute \src "libresoc.v:84252.9-84252.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_inv_a $0\dec31_dec_sub10_inv_a[0:0] + end + attribute \src "libresoc.v:84288.3-84324.6" + process $proc$libresoc.v:84288$3754 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_inv_out[0:0] $1\dec31_dec_sub10_inv_out[0:0] + attribute \src "libresoc.v:84289.5-84289.29" + switch \initial + attribute \src "libresoc.v:84289.9-84289.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_inv_out $0\dec31_dec_sub10_inv_out[0:0] + end + attribute \src "libresoc.v:84325.3-84361.6" + process $proc$libresoc.v:84325$3755 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_cry_out[0:0] $1\dec31_dec_sub10_cry_out[0:0] + attribute \src "libresoc.v:84326.5-84326.29" + switch \initial + attribute \src "libresoc.v:84326.9-84326.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + case + assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_cry_out $0\dec31_dec_sub10_cry_out[0:0] + end + attribute \src "libresoc.v:84362.3-84398.6" + process $proc$libresoc.v:84362$3756 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_br[0:0] $1\dec31_dec_sub10_br[0:0] + attribute \src "libresoc.v:84363.5-84363.29" + switch \initial + attribute \src "libresoc.v:84363.9-84363.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + case + assign $1\dec31_dec_sub10_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_br $0\dec31_dec_sub10_br[0:0] + end + attribute \src "libresoc.v:84399.3-84435.6" + process $proc$libresoc.v:84399$3757 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sgn_ext[0:0] $1\dec31_dec_sub10_sgn_ext[0:0] + attribute \src "libresoc.v:84400.5-84400.29" + switch \initial + attribute \src "libresoc.v:84400.9-84400.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_sgn_ext $0\dec31_dec_sub10_sgn_ext[0:0] + end + attribute \src "libresoc.v:84436.3-84472.6" + process $proc$libresoc.v:84436$3758 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_internal_op[6:0] $1\dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:84437.5-84437.29" + switch \initial + attribute \src "libresoc.v:84437.9-84437.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + case + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub10_internal_op $0\dec31_dec_sub10_internal_op[6:0] + end + attribute \src "libresoc.v:84473.3-84509.6" + process $proc$libresoc.v:84473$3759 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_rsrv[0:0] $1\dec31_dec_sub10_rsrv[0:0] + attribute \src "libresoc.v:84474.5-84474.29" + switch \initial + attribute \src "libresoc.v:84474.9-84474.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_rsrv $0\dec31_dec_sub10_rsrv[0:0] + end + attribute \src "libresoc.v:84510.3-84546.6" + process $proc$libresoc.v:84510$3760 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_is_32b[0:0] $1\dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:84511.5-84511.29" + switch \initial + attribute \src "libresoc.v:84511.9-84511.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_is_32b $0\dec31_dec_sub10_is_32b[0:0] + end + attribute \src "libresoc.v:84547.3-84583.6" + process $proc$libresoc.v:84547$3761 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sgn[0:0] $1\dec31_dec_sub10_sgn[0:0] + attribute \src "libresoc.v:84548.5-84548.29" + switch \initial + attribute \src "libresoc.v:84548.9-84548.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_sgn $0\dec31_dec_sub10_sgn[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:734$106 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B \$31 - connect \Y $and$libresoc.v:734$106_Y + attribute \src "libresoc.v:84584.3-84620.6" + process $proc$libresoc.v:84584$3762 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_lk[0:0] $1\dec31_dec_sub10_lk[0:0] + attribute \src "libresoc.v:84585.5-84585.29" + switch \initial + attribute \src "libresoc.v:84585.9-84585.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_lk $0\dec31_dec_sub10_lk[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:736$108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B \$35 - connect \Y $and$libresoc.v:736$108_Y + attribute \src "libresoc.v:84621.3-84657.6" + process $proc$libresoc.v:84621$3763 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sgl_pipe[0:0] $1\dec31_dec_sub10_sgl_pipe[0:0] + attribute \src "libresoc.v:84622.5-84622.29" + switch \initial + attribute \src "libresoc.v:84622.9-84622.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_sgl_pipe $0\dec31_dec_sub10_sgl_pipe[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:742$114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B \$45 - connect \Y $and$libresoc.v:742$114_Y + attribute \src "libresoc.v:84658.3-84694.6" + process $proc$libresoc.v:84658$3764 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_form[4:0] $1\dec31_dec_sub10_form[4:0] + attribute \src "libresoc.v:84659.5-84659.29" + switch \initial + attribute \src "libresoc.v:84659.9-84659.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + case + assign $1\dec31_dec_sub10_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub10_form $0\dec31_dec_sub10_form[4:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:744$116 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B \$49 - connect \Y $and$libresoc.v:744$116_Y + attribute \src "libresoc.v:84695.3-84731.6" + process $proc$libresoc.v:84695$3765 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_in1_sel[2:0] $1\dec31_dec_sub10_in1_sel[2:0] + attribute \src "libresoc.v:84696.5-84696.29" + switch \initial + attribute \src "libresoc.v:84696.9-84696.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_in1_sel $0\dec31_dec_sub10_in1_sel[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:748$120 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B \$3 - connect \Y $and$libresoc.v:748$120_Y + attribute \src "libresoc.v:84732.3-84768.6" + process $proc$libresoc.v:84732$3766 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_in2_sel[3:0] $1\dec31_dec_sub10_in2_sel[3:0] + attribute \src "libresoc.v:84733.5-84733.29" + switch \initial + attribute \src "libresoc.v:84733.9-84733.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub10_in2_sel $0\dec31_dec_sub10_in2_sel[3:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:750$122 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B \$59 - connect \Y $and$libresoc.v:750$122_Y + attribute \src "libresoc.v:84769.3-84805.6" + process $proc$libresoc.v:84769$3767 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_in3_sel[1:0] $1\dec31_dec_sub10_in3_sel[1:0] + attribute \src "libresoc.v:84770.5-84770.29" + switch \initial + attribute \src "libresoc.v:84770.9-84770.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_in3_sel $0\dec31_dec_sub10_in3_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:752$124 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B \$63 - connect \Y $and$libresoc.v:752$124_Y + attribute \src "libresoc.v:84806.3-84842.6" + process $proc$libresoc.v:84806$3768 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_out_sel[1:0] $1\dec31_dec_sub10_out_sel[1:0] + attribute \src "libresoc.v:84807.5-84807.29" + switch \initial + attribute \src "libresoc.v:84807.9-84807.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub10_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_out_sel $0\dec31_dec_sub10_out_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:757$129 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B \$73 - connect \Y $and$libresoc.v:757$129_Y + attribute \src "libresoc.v:84843.3-84879.6" + process $proc$libresoc.v:84843$3769 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_cr_in[2:0] $1\dec31_dec_sub10_cr_in[2:0] + attribute \src "libresoc.v:84844.5-84844.29" + switch \initial + attribute \src "libresoc.v:84844.9-84844.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_cr_in $0\dec31_dec_sub10_cr_in[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:760$132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B \$77 - connect \Y $and$libresoc.v:760$132_Y + attribute \src "libresoc.v:84880.3-84916.6" + process $proc$libresoc.v:84880$3770 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_cr_out[2:0] $1\dec31_dec_sub10_cr_out[2:0] + attribute \src "libresoc.v:84881.5-84881.29" + switch \initial + attribute \src "libresoc.v:84881.9-84881.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub10_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_cr_out $0\dec31_dec_sub10_cr_out[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:765$137 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B \$87 - connect \Y $and$libresoc.v:765$137_Y + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:84922.1-86501.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub11" +attribute \generator "nMigen" +module \dec31_dec_sub11 + attribute \src "libresoc.v:85455.3-85509.6" + wire width 8 $0\dec31_dec_sub11_asmcode[7:0] + attribute \src "libresoc.v:85675.3-85729.6" + wire $0\dec31_dec_sub11_br[0:0] + attribute \src "libresoc.v:86390.3-86444.6" + wire width 3 $0\dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:86445.3-86499.6" + wire width 3 $0\dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:85400.3-85454.6" + wire width 2 $0\dec31_dec_sub11_cry_in[1:0] + attribute \src "libresoc.v:85620.3-85674.6" + wire $0\dec31_dec_sub11_cry_out[0:0] + attribute \src "libresoc.v:86115.3-86169.6" + wire width 5 $0\dec31_dec_sub11_form[4:0] + attribute \src "libresoc.v:85180.3-85234.6" + wire width 12 $0\dec31_dec_sub11_function_unit[11:0] + attribute \src "libresoc.v:86170.3-86224.6" + wire width 3 $0\dec31_dec_sub11_in1_sel[2:0] + attribute \src "libresoc.v:86225.3-86279.6" + wire width 4 $0\dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:86280.3-86334.6" + wire width 2 $0\dec31_dec_sub11_in3_sel[1:0] + attribute \src "libresoc.v:85785.3-85839.6" + wire width 7 $0\dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:85510.3-85564.6" + wire $0\dec31_dec_sub11_inv_a[0:0] + attribute \src "libresoc.v:85565.3-85619.6" + wire $0\dec31_dec_sub11_inv_out[0:0] + attribute \src "libresoc.v:85895.3-85949.6" + wire $0\dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:85235.3-85289.6" + wire width 4 $0\dec31_dec_sub11_ldst_len[3:0] + attribute \src "libresoc.v:86005.3-86059.6" + wire $0\dec31_dec_sub11_lk[0:0] + attribute \src "libresoc.v:86335.3-86389.6" + wire width 2 $0\dec31_dec_sub11_out_sel[1:0] + attribute \src "libresoc.v:85345.3-85399.6" + wire width 2 $0\dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:85840.3-85894.6" + wire $0\dec31_dec_sub11_rsrv[0:0] + attribute \src "libresoc.v:86060.3-86114.6" + wire $0\dec31_dec_sub11_sgl_pipe[0:0] + attribute \src "libresoc.v:85950.3-86004.6" + wire $0\dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:85730.3-85784.6" + wire $0\dec31_dec_sub11_sgn_ext[0:0] + attribute \src "libresoc.v:85290.3-85344.6" + wire width 2 $0\dec31_dec_sub11_upd[1:0] + attribute \src "libresoc.v:84923.7-84923.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:85455.3-85509.6" + wire width 8 $1\dec31_dec_sub11_asmcode[7:0] + attribute \src "libresoc.v:85675.3-85729.6" + wire $1\dec31_dec_sub11_br[0:0] + attribute \src "libresoc.v:86390.3-86444.6" + wire width 3 $1\dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:86445.3-86499.6" + wire width 3 $1\dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:85400.3-85454.6" + wire width 2 $1\dec31_dec_sub11_cry_in[1:0] + attribute \src "libresoc.v:85620.3-85674.6" + wire $1\dec31_dec_sub11_cry_out[0:0] + attribute \src "libresoc.v:86115.3-86169.6" + wire width 5 $1\dec31_dec_sub11_form[4:0] + attribute \src "libresoc.v:85180.3-85234.6" + wire width 12 $1\dec31_dec_sub11_function_unit[11:0] + attribute \src "libresoc.v:86170.3-86224.6" + wire width 3 $1\dec31_dec_sub11_in1_sel[2:0] + attribute \src "libresoc.v:86225.3-86279.6" + wire width 4 $1\dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:86280.3-86334.6" + wire width 2 $1\dec31_dec_sub11_in3_sel[1:0] + attribute \src "libresoc.v:85785.3-85839.6" + wire width 7 $1\dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:85510.3-85564.6" + wire $1\dec31_dec_sub11_inv_a[0:0] + attribute \src "libresoc.v:85565.3-85619.6" + wire $1\dec31_dec_sub11_inv_out[0:0] + attribute \src "libresoc.v:85895.3-85949.6" + wire $1\dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:85235.3-85289.6" + wire width 4 $1\dec31_dec_sub11_ldst_len[3:0] + attribute \src "libresoc.v:86005.3-86059.6" + wire $1\dec31_dec_sub11_lk[0:0] + attribute \src "libresoc.v:86335.3-86389.6" + wire width 2 $1\dec31_dec_sub11_out_sel[1:0] + attribute \src "libresoc.v:85345.3-85399.6" + wire width 2 $1\dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:85840.3-85894.6" + wire $1\dec31_dec_sub11_rsrv[0:0] + attribute \src "libresoc.v:86060.3-86114.6" + wire $1\dec31_dec_sub11_sgl_pipe[0:0] + attribute \src "libresoc.v:85950.3-86004.6" + wire $1\dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:85730.3-85784.6" + wire $1\dec31_dec_sub11_sgn_ext[0:0] + attribute \src "libresoc.v:85290.3-85344.6" + wire width 2 $1\dec31_dec_sub11_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub11_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub11_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub11_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub11_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub11_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub11_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub11_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub11_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub11_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub11_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub11_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub11_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub11_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub11_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub11_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub11_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub11_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub11_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub11_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub11_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub11_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub11_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub11_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub11_upd + attribute \src "libresoc.v:84923.7-84923.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:84923.7-84923.20" + process $proc$libresoc.v:84923$3796 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:767$139 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B \$91 - connect \Y $and$libresoc.v:767$139_Y + attribute \src "libresoc.v:85180.3-85234.6" + process $proc$libresoc.v:85180$3772 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_function_unit[11:0] $1\dec31_dec_sub11_function_unit[11:0] + attribute \src "libresoc.v:85181.5-85181.29" + switch \initial + attribute \src "libresoc.v:85181.9-85181.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + case + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub11_function_unit $0\dec31_dec_sub11_function_unit[11:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:709$81 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $eq$libresoc.v:709$81_Y + attribute \src "libresoc.v:85235.3-85289.6" + process $proc$libresoc.v:85235$3773 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_ldst_len[3:0] $1\dec31_dec_sub11_ldst_len[3:0] + attribute \src "libresoc.v:85236.5-85236.29" + switch \initial + attribute \src "libresoc.v:85236.9-85236.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub11_ldst_len $0\dec31_dec_sub11_ldst_len[3:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:714$86 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $eq$libresoc.v:714$86_Y + attribute \src "libresoc.v:85290.3-85344.6" + process $proc$libresoc.v:85290$3774 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_upd[1:0] $1\dec31_dec_sub11_upd[1:0] + attribute \src "libresoc.v:85291.5-85291.29" + switch \initial + attribute \src "libresoc.v:85291.9-85291.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_upd $0\dec31_dec_sub11_upd[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:715$87 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $eq$libresoc.v:715$87_Y + attribute \src "libresoc.v:85345.3-85399.6" + process $proc$libresoc.v:85345$3775 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_rc_sel[1:0] $1\dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:85346.5-85346.29" + switch \initial + attribute \src "libresoc.v:85346.9-85346.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_rc_sel $0\dec31_dec_sub11_rc_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:716$88 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $eq$libresoc.v:716$88_Y + attribute \src "libresoc.v:85400.3-85454.6" + process $proc$libresoc.v:85400$3776 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_cry_in[1:0] $1\dec31_dec_sub11_cry_in[1:0] + attribute \src "libresoc.v:85401.5-85401.29" + switch \initial + attribute \src "libresoc.v:85401.9-85401.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_cry_in $0\dec31_dec_sub11_cry_in[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242" - cell $eq $eq$libresoc.v:718$90 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'111 - connect \Y $eq$libresoc.v:718$90_Y + attribute \src "libresoc.v:85455.3-85509.6" + process $proc$libresoc.v:85455$3777 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_asmcode[7:0] $1\dec31_dec_sub11_asmcode[7:0] + attribute \src "libresoc.v:85456.5-85456.29" + switch \initial + attribute \src "libresoc.v:85456.9-85456.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'10000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'10000010 + case + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub11_asmcode $0\dec31_dec_sub11_asmcode[7:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:719$91 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $eq$libresoc.v:719$91_Y + attribute \src "libresoc.v:85510.3-85564.6" + process $proc$libresoc.v:85510$3778 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_inv_a[0:0] $1\dec31_dec_sub11_inv_a[0:0] + attribute \src "libresoc.v:85511.5-85511.29" + switch \initial + attribute \src "libresoc.v:85511.9-85511.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_inv_a $0\dec31_dec_sub11_inv_a[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:723$95 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $eq$libresoc.v:723$95_Y + attribute \src "libresoc.v:85565.3-85619.6" + process $proc$libresoc.v:85565$3779 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_inv_out[0:0] $1\dec31_dec_sub11_inv_out[0:0] + attribute \src "libresoc.v:85566.5-85566.29" + switch \initial + attribute \src "libresoc.v:85566.9-85566.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_inv_out $0\dec31_dec_sub11_inv_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:724$96 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $eq$libresoc.v:724$96_Y + attribute \src "libresoc.v:85620.3-85674.6" + process $proc$libresoc.v:85620$3780 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_cry_out[0:0] $1\dec31_dec_sub11_cry_out[0:0] + attribute \src "libresoc.v:85621.5-85621.29" + switch \initial + attribute \src "libresoc.v:85621.9-85621.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_cry_out $0\dec31_dec_sub11_cry_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:730$102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $eq$libresoc.v:730$102_Y + attribute \src "libresoc.v:85675.3-85729.6" + process $proc$libresoc.v:85675$3781 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_br[0:0] $1\dec31_dec_sub11_br[0:0] + attribute \src "libresoc.v:85676.5-85676.29" + switch \initial + attribute \src "libresoc.v:85676.9-85676.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + case + assign $1\dec31_dec_sub11_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_br $0\dec31_dec_sub11_br[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:731$103 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $eq$libresoc.v:731$103_Y + attribute \src "libresoc.v:85730.3-85784.6" + process $proc$libresoc.v:85730$3782 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sgn_ext[0:0] $1\dec31_dec_sub11_sgn_ext[0:0] + attribute \src "libresoc.v:85731.5-85731.29" + switch \initial + attribute \src "libresoc.v:85731.9-85731.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_sgn_ext $0\dec31_dec_sub11_sgn_ext[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:732$104 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $eq$libresoc.v:732$104_Y + attribute \src "libresoc.v:85785.3-85839.6" + process $proc$libresoc.v:85785$3783 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_internal_op[6:0] $1\dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:85786.5-85786.29" + switch \initial + attribute \src "libresoc.v:85786.9-85786.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010 + case + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub11_internal_op $0\dec31_dec_sub11_internal_op[6:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:738$110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $eq$libresoc.v:738$110_Y + attribute \src "libresoc.v:85840.3-85894.6" + process $proc$libresoc.v:85840$3784 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_rsrv[0:0] $1\dec31_dec_sub11_rsrv[0:0] + attribute \src "libresoc.v:85841.5-85841.29" + switch \initial + attribute \src "libresoc.v:85841.9-85841.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_rsrv $0\dec31_dec_sub11_rsrv[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:739$111 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $eq$libresoc.v:739$111_Y + attribute \src "libresoc.v:85895.3-85949.6" + process $proc$libresoc.v:85895$3785 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_is_32b[0:0] $1\dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:85896.5-85896.29" + switch \initial + attribute \src "libresoc.v:85896.9-85896.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + case + assign $1\dec31_dec_sub11_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_is_32b $0\dec31_dec_sub11_is_32b[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:740$112 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $eq$libresoc.v:740$112_Y + attribute \src "libresoc.v:85950.3-86004.6" + process $proc$libresoc.v:85950$3786 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sgn[0:0] $1\dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:85951.5-85951.29" + switch \initial + attribute \src "libresoc.v:85951.9-85951.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + case + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_sgn $0\dec31_dec_sub11_sgn[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:745$117 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $eq$libresoc.v:745$117_Y + attribute \src "libresoc.v:86005.3-86059.6" + process $proc$libresoc.v:86005$3787 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_lk[0:0] $1\dec31_dec_sub11_lk[0:0] + attribute \src "libresoc.v:86006.5-86006.29" + switch \initial + attribute \src "libresoc.v:86006.9-86006.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_lk $0\dec31_dec_sub11_lk[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:746$118 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $eq$libresoc.v:746$118_Y + attribute \src "libresoc.v:86060.3-86114.6" + process $proc$libresoc.v:86060$3788 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sgl_pipe[0:0] $1\dec31_dec_sub11_sgl_pipe[0:0] + attribute \src "libresoc.v:86061.5-86061.29" + switch \initial + attribute \src "libresoc.v:86061.9-86061.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_sgl_pipe $0\dec31_dec_sub11_sgl_pipe[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:747$119 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $eq$libresoc.v:747$119_Y + attribute \src "libresoc.v:86115.3-86169.6" + process $proc$libresoc.v:86115$3789 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_form[4:0] $1\dec31_dec_sub11_form[4:0] + attribute \src "libresoc.v:86116.5-86116.29" + switch \initial + attribute \src "libresoc.v:86116.9-86116.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + case + assign $1\dec31_dec_sub11_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub11_form $0\dec31_dec_sub11_form[4:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:753$125 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $eq$libresoc.v:753$125_Y + attribute \src "libresoc.v:86170.3-86224.6" + process $proc$libresoc.v:86170$3790 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_in1_sel[2:0] $1\dec31_dec_sub11_in1_sel[2:0] + attribute \src "libresoc.v:86171.5-86171.29" + switch \initial + attribute \src "libresoc.v:86171.9-86171.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_in1_sel $0\dec31_dec_sub11_in1_sel[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:754$126 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $eq$libresoc.v:754$126_Y + attribute \src "libresoc.v:86225.3-86279.6" + process $proc$libresoc.v:86225$3791 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_in2_sel[3:0] $1\dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:86226.5-86226.29" + switch \initial + attribute \src "libresoc.v:86226.9-86226.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub11_in2_sel $0\dec31_dec_sub11_in2_sel[3:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:755$127 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $eq$libresoc.v:755$127_Y + attribute \src "libresoc.v:86280.3-86334.6" + process $proc$libresoc.v:86280$3792 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_in3_sel[1:0] $1\dec31_dec_sub11_in3_sel[1:0] + attribute \src "libresoc.v:86281.5-86281.29" + switch \initial + attribute \src "libresoc.v:86281.9-86281.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_in3_sel $0\dec31_dec_sub11_in3_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:761$133 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $eq$libresoc.v:761$133_Y + attribute \src "libresoc.v:86335.3-86389.6" + process $proc$libresoc.v:86335$3793 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_out_sel[1:0] $1\dec31_dec_sub11_out_sel[1:0] + attribute \src "libresoc.v:86336.5-86336.29" + switch \initial + attribute \src "libresoc.v:86336.9-86336.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub11_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_out_sel $0\dec31_dec_sub11_out_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:762$134 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $eq$libresoc.v:762$134_Y + attribute \src "libresoc.v:86390.3-86444.6" + process $proc$libresoc.v:86390$3794 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_cr_in[2:0] $1\dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:86391.5-86391.29" + switch \initial + attribute \src "libresoc.v:86391.9-86391.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_cr_in $0\dec31_dec_sub11_cr_in[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:763$135 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $eq$libresoc.v:763$135_Y + attribute \src "libresoc.v:86445.3-86499.6" + process $proc$libresoc.v:86445$3795 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_cr_out[2:0] $1\dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:86446.5-86446.29" + switch \initial + attribute \src "libresoc.v:86446.9-86446.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_cr_out $0\dec31_dec_sub11_cr_out[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:768$140 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $eq$libresoc.v:768$140_Y + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:86505.1-89236.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub15" +attribute \generator "nMigen" +module \dec31_dec_sub15 + attribute \src "libresoc.v:87278.3-87380.6" + wire width 8 $0\dec31_dec_sub15_asmcode[7:0] + attribute \src "libresoc.v:87690.3-87792.6" + wire $0\dec31_dec_sub15_br[0:0] + attribute \src "libresoc.v:89029.3-89131.6" + wire width 3 $0\dec31_dec_sub15_cr_in[2:0] + attribute \src "libresoc.v:89132.3-89234.6" + wire width 3 $0\dec31_dec_sub15_cr_out[2:0] + attribute \src "libresoc.v:87175.3-87277.6" + wire width 2 $0\dec31_dec_sub15_cry_in[1:0] + attribute \src "libresoc.v:87587.3-87689.6" + wire $0\dec31_dec_sub15_cry_out[0:0] + attribute \src "libresoc.v:88514.3-88616.6" + wire width 5 $0\dec31_dec_sub15_form[4:0] + attribute \src "libresoc.v:86763.3-86865.6" + wire width 12 $0\dec31_dec_sub15_function_unit[11:0] + attribute \src "libresoc.v:88617.3-88719.6" + wire width 3 $0\dec31_dec_sub15_in1_sel[2:0] + attribute \src "libresoc.v:88720.3-88822.6" + wire width 4 $0\dec31_dec_sub15_in2_sel[3:0] + attribute \src "libresoc.v:88823.3-88925.6" + wire width 2 $0\dec31_dec_sub15_in3_sel[1:0] + attribute \src "libresoc.v:87896.3-87998.6" + wire width 7 $0\dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:87381.3-87483.6" + wire $0\dec31_dec_sub15_inv_a[0:0] + attribute \src "libresoc.v:87484.3-87586.6" + wire $0\dec31_dec_sub15_inv_out[0:0] + attribute \src "libresoc.v:88102.3-88204.6" + wire $0\dec31_dec_sub15_is_32b[0:0] + attribute \src "libresoc.v:86866.3-86968.6" + wire width 4 $0\dec31_dec_sub15_ldst_len[3:0] + attribute \src "libresoc.v:88308.3-88410.6" + wire $0\dec31_dec_sub15_lk[0:0] + attribute \src "libresoc.v:88926.3-89028.6" + wire width 2 $0\dec31_dec_sub15_out_sel[1:0] + attribute \src "libresoc.v:87072.3-87174.6" + wire width 2 $0\dec31_dec_sub15_rc_sel[1:0] + attribute \src "libresoc.v:87999.3-88101.6" + wire $0\dec31_dec_sub15_rsrv[0:0] + attribute \src "libresoc.v:88411.3-88513.6" + wire $0\dec31_dec_sub15_sgl_pipe[0:0] + attribute \src "libresoc.v:88205.3-88307.6" + wire $0\dec31_dec_sub15_sgn[0:0] + attribute \src "libresoc.v:87793.3-87895.6" + wire $0\dec31_dec_sub15_sgn_ext[0:0] + attribute \src "libresoc.v:86969.3-87071.6" + wire width 2 $0\dec31_dec_sub15_upd[1:0] + attribute \src "libresoc.v:86506.7-86506.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:87278.3-87380.6" + wire width 8 $1\dec31_dec_sub15_asmcode[7:0] + attribute \src "libresoc.v:87690.3-87792.6" + wire $1\dec31_dec_sub15_br[0:0] + attribute \src "libresoc.v:89029.3-89131.6" + wire width 3 $1\dec31_dec_sub15_cr_in[2:0] + attribute \src "libresoc.v:89132.3-89234.6" + wire width 3 $1\dec31_dec_sub15_cr_out[2:0] + attribute \src "libresoc.v:87175.3-87277.6" + wire width 2 $1\dec31_dec_sub15_cry_in[1:0] + attribute \src "libresoc.v:87587.3-87689.6" + wire $1\dec31_dec_sub15_cry_out[0:0] + attribute \src "libresoc.v:88514.3-88616.6" + wire width 5 $1\dec31_dec_sub15_form[4:0] + attribute \src "libresoc.v:86763.3-86865.6" + wire width 12 $1\dec31_dec_sub15_function_unit[11:0] + attribute \src "libresoc.v:88617.3-88719.6" + wire width 3 $1\dec31_dec_sub15_in1_sel[2:0] + attribute \src "libresoc.v:88720.3-88822.6" + wire width 4 $1\dec31_dec_sub15_in2_sel[3:0] + attribute \src "libresoc.v:88823.3-88925.6" + wire width 2 $1\dec31_dec_sub15_in3_sel[1:0] + attribute \src "libresoc.v:87896.3-87998.6" + wire width 7 $1\dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:87381.3-87483.6" + wire $1\dec31_dec_sub15_inv_a[0:0] + attribute \src "libresoc.v:87484.3-87586.6" + wire $1\dec31_dec_sub15_inv_out[0:0] + attribute \src "libresoc.v:88102.3-88204.6" + wire $1\dec31_dec_sub15_is_32b[0:0] + attribute \src "libresoc.v:86866.3-86968.6" + wire width 4 $1\dec31_dec_sub15_ldst_len[3:0] + attribute \src "libresoc.v:88308.3-88410.6" + wire $1\dec31_dec_sub15_lk[0:0] + attribute \src "libresoc.v:88926.3-89028.6" + wire width 2 $1\dec31_dec_sub15_out_sel[1:0] + attribute \src "libresoc.v:87072.3-87174.6" + wire width 2 $1\dec31_dec_sub15_rc_sel[1:0] + attribute \src "libresoc.v:87999.3-88101.6" + wire $1\dec31_dec_sub15_rsrv[0:0] + attribute \src "libresoc.v:88411.3-88513.6" + wire $1\dec31_dec_sub15_sgl_pipe[0:0] + attribute \src "libresoc.v:88205.3-88307.6" + wire $1\dec31_dec_sub15_sgn[0:0] + attribute \src "libresoc.v:87793.3-87895.6" + wire $1\dec31_dec_sub15_sgn_ext[0:0] + attribute \src "libresoc.v:86969.3-87071.6" + wire width 2 $1\dec31_dec_sub15_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub15_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub15_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub15_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub15_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub15_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub15_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub15_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub15_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub15_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub15_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub15_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub15_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub15_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub15_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub15_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub15_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub15_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub15_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub15_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub15_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub15_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub15_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub15_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub15_upd + attribute \src "libresoc.v:86506.7-86506.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:86506.7-86506.20" + process $proc$libresoc.v:86506$3821 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:769$141 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $eq$libresoc.v:769$141_Y + attribute \src "libresoc.v:86763.3-86865.6" + process $proc$libresoc.v:86763$3797 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_function_unit[11:0] $1\dec31_dec_sub15_function_unit[11:0] + attribute \src "libresoc.v:86764.5-86764.29" + switch \initial + attribute \src "libresoc.v:86764.9-86764.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + case + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub15_function_unit $0\dec31_dec_sub15_function_unit[11:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:710$82 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:710$82_Y + attribute \src "libresoc.v:86866.3-86968.6" + process $proc$libresoc.v:86866$3798 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_ldst_len[3:0] $1\dec31_dec_sub15_ldst_len[3:0] + attribute \src "libresoc.v:86867.5-86867.29" + switch \initial + attribute \src "libresoc.v:86867.9-86867.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub15_ldst_len $0\dec31_dec_sub15_ldst_len[3:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:712$84 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:712$84_Y + attribute \src "libresoc.v:86969.3-87071.6" + process $proc$libresoc.v:86969$3799 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_upd[1:0] $1\dec31_dec_sub15_upd[1:0] + attribute \src "libresoc.v:86970.5-86970.29" + switch \initial + attribute \src "libresoc.v:86970.9-86970.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_upd $0\dec31_dec_sub15_upd[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254" - cell $not $not$libresoc.v:721$93 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \do_step - connect \Y $not$libresoc.v:721$93_Y + attribute \src "libresoc.v:87072.3-87174.6" + process $proc$libresoc.v:87072$3800 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_rc_sel[1:0] $1\dec31_dec_sub15_rc_sel[1:0] + attribute \src "libresoc.v:87073.5-87073.29" + switch \initial + attribute \src "libresoc.v:87073.9-87073.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_rc_sel $0\dec31_dec_sub15_rc_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:725$97 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:725$97_Y + attribute \src "libresoc.v:87175.3-87277.6" + process $proc$libresoc.v:87175$3801 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_cry_in[1:0] $1\dec31_dec_sub15_cry_in[1:0] + attribute \src "libresoc.v:87176.5-87176.29" + switch \initial + attribute \src "libresoc.v:87176.9-87176.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_cry_in $0\dec31_dec_sub15_cry_in[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:728$100 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:728$100_Y + attribute \src "libresoc.v:87278.3-87380.6" + process $proc$libresoc.v:87278$3802 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_asmcode[7:0] $1\dec31_dec_sub15_asmcode[7:0] + attribute \src "libresoc.v:87279.5-87279.29" + switch \initial + attribute \src "libresoc.v:87279.9-87279.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + case + assign $1\dec31_dec_sub15_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub15_asmcode $0\dec31_dec_sub15_asmcode[7:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:733$105 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:733$105_Y + attribute \src "libresoc.v:87381.3-87483.6" + process $proc$libresoc.v:87381$3803 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_inv_a[0:0] $1\dec31_dec_sub15_inv_a[0:0] + attribute \src "libresoc.v:87382.5-87382.29" + switch \initial + attribute \src "libresoc.v:87382.9-87382.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_inv_a $0\dec31_dec_sub15_inv_a[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:735$107 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:735$107_Y + attribute \src "libresoc.v:87484.3-87586.6" + process $proc$libresoc.v:87484$3804 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_inv_out[0:0] $1\dec31_dec_sub15_inv_out[0:0] + attribute \src "libresoc.v:87485.5-87485.29" + switch \initial + attribute \src "libresoc.v:87485.9-87485.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_inv_out $0\dec31_dec_sub15_inv_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:737$109 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:737$109_Y + attribute \src "libresoc.v:87587.3-87689.6" + process $proc$libresoc.v:87587$3805 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_cry_out[0:0] $1\dec31_dec_sub15_cry_out[0:0] + attribute \src "libresoc.v:87588.5-87588.29" + switch \initial + attribute \src "libresoc.v:87588.9-87588.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_cry_out $0\dec31_dec_sub15_cry_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:741$113 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:741$113_Y + attribute \src "libresoc.v:87690.3-87792.6" + process $proc$libresoc.v:87690$3806 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_br[0:0] $1\dec31_dec_sub15_br[0:0] + attribute \src "libresoc.v:87691.5-87691.29" + switch \initial + attribute \src "libresoc.v:87691.9-87691.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + case + assign $1\dec31_dec_sub15_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_br $0\dec31_dec_sub15_br[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:743$115 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:743$115_Y + attribute \src "libresoc.v:87793.3-87895.6" + process $proc$libresoc.v:87793$3807 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sgn_ext[0:0] $1\dec31_dec_sub15_sgn_ext[0:0] + attribute \src "libresoc.v:87794.5-87794.29" + switch \initial + attribute \src "libresoc.v:87794.9-87794.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_sgn_ext $0\dec31_dec_sub15_sgn_ext[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:749$121 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:749$121_Y + attribute \src "libresoc.v:87896.3-87998.6" + process $proc$libresoc.v:87896$3808 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_internal_op[6:0] $1\dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:87897.5-87897.29" + switch \initial + attribute \src "libresoc.v:87897.9-87897.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + case + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub15_internal_op $0\dec31_dec_sub15_internal_op[6:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:751$123 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:751$123_Y + attribute \src "libresoc.v:87999.3-88101.6" + process $proc$libresoc.v:87999$3809 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_rsrv[0:0] $1\dec31_dec_sub15_rsrv[0:0] + attribute \src "libresoc.v:88000.5-88000.29" + switch \initial + attribute \src "libresoc.v:88000.9-88000.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_rsrv $0\dec31_dec_sub15_rsrv[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:756$128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:756$128_Y + attribute \src "libresoc.v:88102.3-88204.6" + process $proc$libresoc.v:88102$3810 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_is_32b[0:0] $1\dec31_dec_sub15_is_32b[0:0] + attribute \src "libresoc.v:88103.5-88103.29" + switch \initial + attribute \src "libresoc.v:88103.9-88103.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_is_32b $0\dec31_dec_sub15_is_32b[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:758$130 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:758$130_Y + attribute \src "libresoc.v:88205.3-88307.6" + process $proc$libresoc.v:88205$3811 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sgn[0:0] $1\dec31_dec_sub15_sgn[0:0] + attribute \src "libresoc.v:88206.5-88206.29" + switch \initial + attribute \src "libresoc.v:88206.9-88206.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_sgn $0\dec31_dec_sub15_sgn[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:759$131 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:759$131_Y + attribute \src "libresoc.v:88308.3-88410.6" + process $proc$libresoc.v:88308$3812 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_lk[0:0] $1\dec31_dec_sub15_lk[0:0] + attribute \src "libresoc.v:88309.5-88309.29" + switch \initial + attribute \src "libresoc.v:88309.9-88309.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_lk $0\dec31_dec_sub15_lk[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:764$136 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:764$136_Y + attribute \src "libresoc.v:88411.3-88513.6" + process $proc$libresoc.v:88411$3813 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sgl_pipe[0:0] $1\dec31_dec_sub15_sgl_pipe[0:0] + attribute \src "libresoc.v:88412.5-88412.29" + switch \initial + attribute \src "libresoc.v:88412.9-88412.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_sgl_pipe $0\dec31_dec_sub15_sgl_pipe[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:766$138 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:766$138_Y + attribute \src "libresoc.v:88514.3-88616.6" + process $proc$libresoc.v:88514$3814 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_form[4:0] $1\dec31_dec_sub15_form[4:0] + attribute \src "libresoc.v:88515.5-88515.29" + switch \initial + attribute \src "libresoc.v:88515.9-88515.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + case + assign $1\dec31_dec_sub15_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub15_form $0\dec31_dec_sub15_form[4:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:170" - cell $pos $pos$libresoc.v:726$98 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 61'0000000000000000000000000000000000000000000000000000000000000 \terminated \core_stopped_i \stopping } - connect \Y $pos$libresoc.v:726$98_Y + attribute \src "libresoc.v:88617.3-88719.6" + process $proc$libresoc.v:88617$3815 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_in1_sel[2:0] $1\dec31_dec_sub15_in1_sel[2:0] + attribute \src "libresoc.v:88618.5-88618.29" + switch \initial + attribute \src "libresoc.v:88618.9-88618.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_in1_sel $0\dec31_dec_sub15_in1_sel[2:0] end - attribute \src "libresoc.v:1003.3-1012.6" - process $proc$libresoc.v:1003$195 + attribute \src "libresoc.v:88720.3-88822.6" + process $proc$libresoc.v:88720$3816 assign { } { } assign { } { } - assign $0\d_cr_req[0:0] $1\d_cr_req[0:0] - attribute \src "libresoc.v:1004.5-1004.29" + assign $0\dec31_dec_sub15_in2_sel[3:0] $1\dec31_dec_sub15_in2_sel[3:0] + attribute \src "libresoc.v:88721.5-88721.29" switch \initial - attribute \src "libresoc.v:1004.9-1004.17" + attribute \src "libresoc.v:88721.9-88721.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" - switch \dmi_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 4'1000 + case 5'10100 assign { } { } - assign $1\d_cr_req[0:0] \dmi_req_i - case - assign $1\d_cr_req[0:0] 1'0 - end - sync always - update \d_cr_req $0\d_cr_req[0:0] - end - attribute \src "libresoc.v:1013.3-1022.6" - process $proc$libresoc.v:1013$196 - assign { } { } - assign { } { } - assign $0\d_xer_req[0:0] $1\d_xer_req[0:0] - attribute \src "libresoc.v:1014.5-1014.29" - switch \initial - attribute \src "libresoc.v:1014.9-1014.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" - switch \dmi_addr_i + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 4'1001 + case 5'10101 assign { } { } - assign $1\d_xer_req[0:0] \dmi_req_i - case - assign $1\d_xer_req[0:0] 1'0 - end - sync always - update \d_xer_req $0\d_xer_req[0:0] - end - attribute \src "libresoc.v:1023.3-1053.6" - process $proc$libresoc.v:1023$197 - assign { } { } - assign { } { } - assign $0\dmi_dout[63:0] $1\dmi_dout[63:0] - attribute \src "libresoc.v:1024.5-1024.29" - switch \initial - attribute \src "libresoc.v:1024.9-1024.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:173" - switch \dmi_addr_i + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 4'0001 + case 5'10110 assign { } { } - assign $1\dmi_dout[63:0] \stat_reg + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 4'0010 + case 5'10111 assign { } { } - assign $1\dmi_dout[63:0] \core_dbg_pc + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 4'0011 + case 5'11000 assign { } { } - assign $1\dmi_dout[63:0] \core_dbg_msr + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 4'0101 + case 5'11001 assign { } { } - assign $1\dmi_dout[63:0] \d_gpr_data + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 4'0110 + case 5'11010 assign { } { } - assign $1\dmi_dout[63:0] { \log_write_addr_o \log_dmi_addr } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 4'0111 + case 5'11011 assign { } { } - assign $1\dmi_dout[63:0] \log_dmi_data + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 4'1000 + case 5'11100 assign { } { } - assign $1\dmi_dout[63:0] \d_cr_data + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 4'1001 + case 5'11101 assign { } { } - assign $1\dmi_dout[63:0] \d_xer_data - case - assign $1\dmi_dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dmi_dout $0\dmi_dout[63:0] - end - attribute \src "libresoc.v:1054.3-1083.6" - process $proc$libresoc.v:1054$198 - assign { } { } - assign { } { } - assign { } { } - assign $0\do_step$next[0:0]$199 $5\do_step$next[0:0]$204 - attribute \src "libresoc.v:1055.5-1055.29" - switch \initial - attribute \src "libresoc.v:1055.9-1055.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - switch { \$9 \$5 } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 5'11110 assign { } { } - assign $1\do_step$next[0:0]$200 $2\do_step$next[0:0]$201 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" - switch \dmi_we_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\do_step$next[0:0]$201 $3\do_step$next[0:0]$202 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - switch { \$15 \$13 \$11 } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $3\do_step$next[0:0]$202 $4\do_step$next[0:0]$203 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:213" - switch \dmi_din [3] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\do_step$next[0:0]$203 1'1 - case - assign $4\do_step$next[0:0]$203 1'0 - end - case - assign $3\do_step$next[0:0]$202 1'0 - end - case - assign $2\do_step$next[0:0]$201 1'0 - end - case - assign $1\do_step$next[0:0]$200 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11111 assign { } { } - assign $5\do_step$next[0:0]$204 1'0 + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 case - assign $5\do_step$next[0:0]$204 $1\do_step$next[0:0]$200 + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0000 end sync always - update \do_step$next $0\do_step$next[0:0]$199 + update \dec31_dec_sub15_in2_sel $0\dec31_dec_sub15_in2_sel[3:0] end - attribute \src "libresoc.v:1084.3-1113.6" - process $proc$libresoc.v:1084$205 - assign { } { } + attribute \src "libresoc.v:88823.3-88925.6" + process $proc$libresoc.v:88823$3817 assign { } { } assign { } { } - assign $0\do_reset$next[0:0]$206 $5\do_reset$next[0:0]$211 - attribute \src "libresoc.v:1085.5-1085.29" + assign $0\dec31_dec_sub15_in3_sel[1:0] $1\dec31_dec_sub15_in3_sel[1:0] + attribute \src "libresoc.v:88824.5-88824.29" switch \initial - attribute \src "libresoc.v:1085.9-1085.17" + attribute \src "libresoc.v:88824.9-88824.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - switch { \$23 \$19 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 5'00000 assign { } { } - assign $1\do_reset$next[0:0]$207 $2\do_reset$next[0:0]$208 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" - switch \dmi_we_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\do_reset$next[0:0]$208 $3\do_reset$next[0:0]$209 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - switch { \$29 \$27 \$25 } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $3\do_reset$next[0:0]$209 $4\do_reset$next[0:0]$210 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208" - switch \dmi_din [1] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\do_reset$next[0:0]$210 1'1 - case - assign $4\do_reset$next[0:0]$210 1'0 - end - case - assign $3\do_reset$next[0:0]$209 1'0 - end - case - assign $2\do_reset$next[0:0]$208 1'0 - end - case - assign $1\do_reset$next[0:0]$207 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 assign { } { } - assign $5\do_reset$next[0:0]$211 1'0 - case - assign $5\do_reset$next[0:0]$211 $1\do_reset$next[0:0]$207 - end - sync always - update \do_reset$next $0\do_reset$next[0:0]$206 - end - attribute \src "libresoc.v:1114.3-1143.6" - process $proc$libresoc.v:1114$212 - assign { } { } - assign { } { } - assign { } { } - assign $0\do_icreset$next[0:0]$213 $5\do_icreset$next[0:0]$218 - attribute \src "libresoc.v:1115.5-1115.29" - switch \initial - attribute \src "libresoc.v:1115.9-1115.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - switch { \$37 \$33 } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 5'00010 assign { } { } - assign $1\do_icreset$next[0:0]$214 $2\do_icreset$next[0:0]$215 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" - switch \dmi_we_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\do_icreset$next[0:0]$215 $3\do_icreset$next[0:0]$216 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - switch { \$43 \$41 \$39 } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $3\do_icreset$next[0:0]$216 $4\do_icreset$next[0:0]$217 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216" - switch \dmi_din [2] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\do_icreset$next[0:0]$217 1'1 - case - assign $4\do_icreset$next[0:0]$217 1'0 - end - case - assign $3\do_icreset$next[0:0]$216 1'0 - end - case - assign $2\do_icreset$next[0:0]$215 1'0 - end - case - assign $1\do_icreset$next[0:0]$214 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 assign { } { } - assign $5\do_icreset$next[0:0]$218 1'0 - case - assign $5\do_icreset$next[0:0]$218 $1\do_icreset$next[0:0]$214 - end - sync always - update \do_icreset$next $0\do_icreset$next[0:0]$213 - end - attribute \src "libresoc.v:1144.3-1177.6" - process $proc$libresoc.v:1144$219 - assign { } { } - assign { } { } - assign { } { } - assign $0\do_dmi_log_rd$next[0:0]$220 $4\do_dmi_log_rd$next[0:0]$224 - attribute \src "libresoc.v:1145.5-1145.29" - switch \initial - attribute \src "libresoc.v:1145.9-1145.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - switch { \$51 \$47 } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 5'00100 assign { } { } - assign $1\do_dmi_log_rd$next[0:0]$221 $2\do_dmi_log_rd$next[0:0]$222 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" - switch \dmi_we_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\do_dmi_log_rd$next[0:0]$222 $3\do_dmi_log_rd$next[0:0]$223 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - switch { \$57 \$55 \$53 } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign $3\do_dmi_log_rd$next[0:0]$223 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign $3\do_dmi_log_rd$next[0:0]$223 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $3\do_dmi_log_rd$next[0:0]$223 1'1 - case - assign $3\do_dmi_log_rd$next[0:0]$223 1'0 - end - case - assign $2\do_dmi_log_rd$next[0:0]$222 1'0 - end + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 5'00101 assign { } { } - assign $1\do_dmi_log_rd$next[0:0]$221 1'1 - case - assign $1\do_dmi_log_rd$next[0:0]$221 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00110 assign { } { } - assign $4\do_dmi_log_rd$next[0:0]$224 1'0 - case - assign $4\do_dmi_log_rd$next[0:0]$224 $1\do_dmi_log_rd$next[0:0]$221 - end - sync always - update \do_dmi_log_rd$next $0\do_dmi_log_rd$next[0:0]$220 - end - attribute \src "libresoc.v:474.7-474.20" - process $proc$libresoc.v:474$225 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:647.7-647.31" - process $proc$libresoc.v:647$226 - assign { } { } - assign $1\dmi_read_log_data[0:0] 1'0 - sync always - sync init - update \dmi_read_log_data $1\dmi_read_log_data[0:0] - end - attribute \src "libresoc.v:651.7-651.33" - process $proc$libresoc.v:651$227 - assign { } { } - assign $1\dmi_read_log_data_1[0:0] 1'0 - sync always - sync init - update \dmi_read_log_data_1 $1\dmi_read_log_data_1[0:0] - end - attribute \src "libresoc.v:657.7-657.25" - process $proc$libresoc.v:657$228 - assign { } { } - assign $1\dmi_req_i_1[0:0] 1'0 - sync always - sync init - update \dmi_req_i_1 $1\dmi_req_i_1[0:0] - end - attribute \src "libresoc.v:663.7-663.27" - process $proc$libresoc.v:663$229 - assign { } { } - assign $1\do_dmi_log_rd[0:0] 1'0 - sync always - sync init - update \do_dmi_log_rd $1\do_dmi_log_rd[0:0] - end - attribute \src "libresoc.v:667.7-667.24" - process $proc$libresoc.v:667$230 - assign { } { } - assign $1\do_icreset[0:0] 1'0 - sync always - sync init - update \do_icreset $1\do_icreset[0:0] - end - attribute \src "libresoc.v:671.7-671.22" - process $proc$libresoc.v:671$231 - assign { } { } - assign $1\do_reset[0:0] 1'0 - sync always - sync init - update \do_reset $1\do_reset[0:0] - end - attribute \src "libresoc.v:675.7-675.21" - process $proc$libresoc.v:675$232 - assign { } { } - assign $1\do_step[0:0] 1'0 - sync always - sync init - update \do_step $1\do_step[0:0] - end - attribute \src "libresoc.v:679.13-679.31" - process $proc$libresoc.v:679$233 - assign { } { } - assign $1\gspr_index[6:0] 7'0000000 - sync always - sync init - update \gspr_index $1\gspr_index[6:0] - end - attribute \src "libresoc.v:685.14-685.34" - process $proc$libresoc.v:685$234 - assign { } { } - assign $1\log_dmi_addr[31:0] 0 - sync always - sync init - update \log_dmi_addr $1\log_dmi_addr[31:0] - end - attribute \src "libresoc.v:697.7-697.22" - process $proc$libresoc.v:697$235 - assign { } { } - assign $1\stopping[0:0] 1'0 - sync always - sync init - update \stopping $1\stopping[0:0] - end - attribute \src "libresoc.v:703.7-703.24" - process $proc$libresoc.v:703$236 - assign { } { } - assign $1\terminated[0:0] 1'0 - sync always - sync init - update \terminated $1\terminated[0:0] - end - attribute \src "libresoc.v:770.3-771.51" - process $proc$libresoc.v:770$142 - assign { } { } - assign $0\dmi_read_log_data[0:0] \dmi_read_log_data$next - sync posedge \clk - update \dmi_read_log_data $0\dmi_read_log_data[0:0] - end - attribute \src "libresoc.v:772.3-773.55" - process $proc$libresoc.v:772$143 - assign { } { } - assign $0\dmi_read_log_data_1[0:0] \dmi_read_log_data_1$next - sync posedge \clk - update \dmi_read_log_data_1 $0\dmi_read_log_data_1[0:0] - end - attribute \src "libresoc.v:774.3-775.41" - process $proc$libresoc.v:774$144 - assign { } { } - assign $0\log_dmi_addr[31:0] \log_dmi_addr$next - sync posedge \clk - update \log_dmi_addr $0\log_dmi_addr[31:0] - end - attribute \src "libresoc.v:776.3-777.37" - process $proc$libresoc.v:776$145 - assign { } { } - assign $0\gspr_index[6:0] \gspr_index$next - sync posedge \clk - update \gspr_index $0\gspr_index[6:0] - end - attribute \src "libresoc.v:778.3-779.33" - process $proc$libresoc.v:778$146 - assign { } { } - assign $0\stopping[0:0] \stopping$next - sync posedge \clk - update \stopping $0\stopping[0:0] - end - attribute \src "libresoc.v:780.3-781.37" - process $proc$libresoc.v:780$147 - assign { } { } - assign $0\terminated[0:0] \terminated$next - sync posedge \clk - update \terminated $0\terminated[0:0] - end - attribute \src "libresoc.v:782.3-783.39" - process $proc$libresoc.v:782$148 - assign { } { } - assign $0\dmi_req_i_1[0:0] \dmi_req_i_1$next - sync posedge \clk - update \dmi_req_i_1 $0\dmi_req_i_1[0:0] - end - attribute \src "libresoc.v:784.3-785.43" - process $proc$libresoc.v:784$149 - assign { } { } - assign $0\do_dmi_log_rd[0:0] \do_dmi_log_rd$next - sync posedge \clk - update \do_dmi_log_rd $0\do_dmi_log_rd[0:0] - end - attribute \src "libresoc.v:786.3-787.37" - process $proc$libresoc.v:786$150 - assign { } { } - assign $0\do_icreset[0:0] \do_icreset$next - sync posedge \clk - update \do_icreset $0\do_icreset[0:0] - end - attribute \src "libresoc.v:788.3-789.33" - process $proc$libresoc.v:788$151 - assign { } { } - assign $0\do_reset[0:0] \do_reset$next - sync posedge \clk - update \do_reset $0\do_reset[0:0] - end - attribute \src "libresoc.v:790.3-791.31" - process $proc$libresoc.v:790$152 - assign { } { } - assign $0\do_step[0:0] \do_step$next - sync posedge \clk - update \do_step $0\do_step[0:0] - end - attribute \src "libresoc.v:792.3-809.6" - process $proc$libresoc.v:792$153 - assign { } { } - assign $0\dmi_ack_o[0:0] $1\dmi_ack_o[0:0] - attribute \src "libresoc.v:793.5-793.29" - switch \initial - attribute \src "libresoc.v:793.9-793.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" - switch \dmi_addr_i + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 4'0101 + case 5'00111 assign { } { } - assign $1\dmi_ack_o[0:0] \d_gpr_ack + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 4'1000 + case 5'01000 assign { } { } - assign $1\dmi_ack_o[0:0] \d_cr_ack + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 4'1001 + case 5'01001 assign { } { } - assign $1\dmi_ack_o[0:0] \d_xer_ack + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case + case 5'01010 assign { } { } - assign $1\dmi_ack_o[0:0] \dmi_req_i - end - sync always - update \dmi_ack_o $0\dmi_ack_o[0:0] - end - attribute \src "libresoc.v:810.3-819.6" - process $proc$libresoc.v:810$154 - assign { } { } - assign { } { } - assign $0\d_gpr_req[0:0] $1\d_gpr_req[0:0] - attribute \src "libresoc.v:811.5-811.29" - switch \initial - attribute \src "libresoc.v:811.9-811.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" - switch \dmi_addr_i + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 4'0101 + case 5'01011 assign { } { } - assign $1\d_gpr_req[0:0] \dmi_req_i - case - assign $1\d_gpr_req[0:0] 1'0 - end - sync always - update \d_gpr_req $0\d_gpr_req[0:0] - end - attribute \src "libresoc.v:820.3-828.6" - process $proc$libresoc.v:820$155 - assign { } { } - assign { } { } - assign $0\dmi_req_i_1$next[0:0]$156 $1\dmi_req_i_1$next[0:0]$157 - attribute \src "libresoc.v:821.5-821.29" - switch \initial - attribute \src "libresoc.v:821.9-821.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01100 assign { } { } - assign $1\dmi_req_i_1$next[0:0]$157 1'0 - case - assign $1\dmi_req_i_1$next[0:0]$157 \dmi_req_i - end - sync always - update \dmi_req_i_1$next $0\dmi_req_i_1$next[0:0]$156 - end - attribute \src "libresoc.v:829.3-878.6" - process $proc$libresoc.v:829$158 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\terminated$next[0:0]$159 $8\terminated$next[0:0]$167 - attribute \src "libresoc.v:830.5-830.29" - switch \initial - attribute \src "libresoc.v:830.9-830.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - switch { \$65 \$61 } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 5'01101 assign { } { } - assign $1\terminated$next[0:0]$160 $2\terminated$next[0:0]$161 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" - switch \dmi_we_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\terminated$next[0:0]$161 $3\terminated$next[0:0]$162 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - switch { \$71 \$69 \$67 } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign { } { } - assign { } { } - assign $3\terminated$next[0:0]$162 $6\terminated$next[0:0]$165 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208" - switch \dmi_din [1] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\terminated$next[0:0]$163 1'0 - case - assign $4\terminated$next[0:0]$163 \terminated - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:213" - switch \dmi_din [3] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\terminated$next[0:0]$164 1'0 - case - assign $5\terminated$next[0:0]$164 $4\terminated$next[0:0]$163 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" - switch \dmi_din [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\terminated$next[0:0]$165 1'0 - case - assign $6\terminated$next[0:0]$165 $5\terminated$next[0:0]$164 - end - case - assign $3\terminated$next[0:0]$162 \terminated - end - case - assign $2\terminated$next[0:0]$161 \terminated - end - case - assign $1\terminated$next[0:0]$160 \terminated - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:247" - switch \terminate_i + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01110 assign { } { } - assign $7\terminated$next[0:0]$166 1'1 - case - assign $7\terminated$next[0:0]$166 $1\terminated$next[0:0]$160 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 assign { } { } - assign $8\terminated$next[0:0]$167 1'0 + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 case - assign $8\terminated$next[0:0]$167 $7\terminated$next[0:0]$166 + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 end sync always - update \terminated$next $0\terminated$next[0:0]$159 + update \dec31_dec_sub15_in3_sel $0\dec31_dec_sub15_in3_sel[1:0] end - attribute \src "libresoc.v:879.3-922.6" - process $proc$libresoc.v:879$168 - assign { } { } + attribute \src "libresoc.v:88926.3-89028.6" + process $proc$libresoc.v:88926$3818 assign { } { } assign { } { } - assign { } { } - assign $0\stopping$next[0:0]$169 $7\stopping$next[0:0]$176 - attribute \src "libresoc.v:880.5-880.29" + assign $0\dec31_dec_sub15_out_sel[1:0] $1\dec31_dec_sub15_out_sel[1:0] + attribute \src "libresoc.v:88927.5-88927.29" switch \initial - attribute \src "libresoc.v:880.9-880.17" + attribute \src "libresoc.v:88927.9-88927.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - switch { \$79 \$75 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 5'00000 assign { } { } - assign $1\stopping$next[0:0]$170 $2\stopping$next[0:0]$171 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" - switch \dmi_we_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\stopping$next[0:0]$171 $3\stopping$next[0:0]$172 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - switch { \$85 \$83 \$81 } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign { } { } - assign $3\stopping$next[0:0]$172 $5\stopping$next[0:0]$174 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" - switch \dmi_din [0] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\stopping$next[0:0]$173 1'1 - case - assign $4\stopping$next[0:0]$173 \stopping - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" - switch \dmi_din [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\stopping$next[0:0]$174 1'0 - case - assign $5\stopping$next[0:0]$174 $4\stopping$next[0:0]$173 - end - case - assign $3\stopping$next[0:0]$172 \stopping - end - case - assign $2\stopping$next[0:0]$171 \stopping - end - case - assign $1\stopping$next[0:0]$170 \stopping - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:247" - switch \terminate_i + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 assign { } { } - assign $6\stopping$next[0:0]$175 1'1 - case - assign $6\stopping$next[0:0]$175 $1\stopping$next[0:0]$170 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 assign { } { } - assign $7\stopping$next[0:0]$176 1'0 + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 case - assign $7\stopping$next[0:0]$176 $6\stopping$next[0:0]$175 + assign $1\dec31_dec_sub15_out_sel[1:0] 2'00 end sync always - update \stopping$next $0\stopping$next[0:0]$169 + update \dec31_dec_sub15_out_sel $0\dec31_dec_sub15_out_sel[1:0] end - attribute \src "libresoc.v:923.3-950.6" - process $proc$libresoc.v:923$177 + attribute \src "libresoc.v:89029.3-89131.6" + process $proc$libresoc.v:89029$3819 assign { } { } assign { } { } - assign { } { } - assign $0\gspr_index$next[6:0]$178 $4\gspr_index$next[6:0]$182 - attribute \src "libresoc.v:924.5-924.29" + assign $0\dec31_dec_sub15_cr_in[2:0] $1\dec31_dec_sub15_cr_in[2:0] + attribute \src "libresoc.v:89030.5-89030.29" switch \initial - attribute \src "libresoc.v:924.9-924.17" + attribute \src "libresoc.v:89030.9-89030.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - switch { \$93 \$89 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 5'00000 assign { } { } - assign $1\gspr_index$next[6:0]$179 $2\gspr_index$next[6:0]$180 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" - switch \dmi_we_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\gspr_index$next[6:0]$180 $3\gspr_index$next[6:0]$181 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - switch { \$99 \$97 \$95 } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign $3\gspr_index$next[6:0]$181 \gspr_index - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign $3\gspr_index$next[6:0]$181 \dmi_din [6:0] - case - assign $3\gspr_index$next[6:0]$181 \gspr_index - end - case - assign $2\gspr_index$next[6:0]$180 \gspr_index - end - case - assign $1\gspr_index$next[6:0]$179 \gspr_index - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 assign { } { } - assign $4\gspr_index$next[6:0]$182 7'0000000 + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 case - assign $4\gspr_index$next[6:0]$182 $1\gspr_index$next[6:0]$179 + assign $1\dec31_dec_sub15_cr_in[2:0] 3'000 end sync always - update \gspr_index$next $0\gspr_index$next[6:0]$178 + update \dec31_dec_sub15_cr_in $0\dec31_dec_sub15_cr_in[2:0] end - attribute \src "libresoc.v:951.3-984.6" - process $proc$libresoc.v:951$183 + attribute \src "libresoc.v:89132.3-89234.6" + process $proc$libresoc.v:89132$3820 assign { } { } assign { } { } - assign { } { } - assign $0\log_dmi_addr$next[31:0]$184 $4\log_dmi_addr$next[31:0]$188 - attribute \src "libresoc.v:952.5-952.29" + assign $0\dec31_dec_sub15_cr_out[2:0] $1\dec31_dec_sub15_cr_out[2:0] + attribute \src "libresoc.v:89133.5-89133.29" switch \initial - attribute \src "libresoc.v:952.9-952.17" + attribute \src "libresoc.v:89133.9-89133.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - switch { \$107 \$103 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 5'00000 assign { } { } - assign $1\log_dmi_addr$next[31:0]$185 $2\log_dmi_addr$next[31:0]$186 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" - switch \dmi_we_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\log_dmi_addr$next[31:0]$186 $3\log_dmi_addr$next[31:0]$187 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - switch { \$113 \$111 \$109 } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign $3\log_dmi_addr$next[31:0]$187 \log_dmi_addr - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign $3\log_dmi_addr$next[31:0]$187 \log_dmi_addr - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $3\log_dmi_addr$next[31:0]$187 \dmi_din [31:0] - case - assign $3\log_dmi_addr$next[31:0]$187 \log_dmi_addr - end - case - assign $2\log_dmi_addr$next[31:0]$186 \log_dmi_addr - end + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign $1\log_dmi_addr$next[31:0]$185 [31:2] \log_dmi_addr [31:2] - assign $1\log_dmi_addr$next[31:0]$185 [1:0] \$115 [1:0] - case - assign $1\log_dmi_addr$next[31:0]$185 \log_dmi_addr - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11100 assign { } { } - assign $4\log_dmi_addr$next[31:0]$188 0 - case - assign $4\log_dmi_addr$next[31:0]$188 $1\log_dmi_addr$next[31:0]$185 - end - sync always - update \log_dmi_addr$next $0\log_dmi_addr$next[31:0]$184 - end - attribute \src "libresoc.v:985.3-993.6" - process $proc$libresoc.v:985$189 - assign { } { } - assign { } { } - assign $0\dmi_read_log_data_1$next[0:0]$190 $1\dmi_read_log_data_1$next[0:0]$191 - attribute \src "libresoc.v:986.5-986.29" - switch \initial - attribute \src "libresoc.v:986.9-986.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 assign { } { } - assign $1\dmi_read_log_data_1$next[0:0]$191 1'0 + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 case - assign $1\dmi_read_log_data_1$next[0:0]$191 \dmi_read_log_data + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 end sync always - update \dmi_read_log_data_1$next $0\dmi_read_log_data_1$next[0:0]$190 + update \dec31_dec_sub15_cr_out $0\dec31_dec_sub15_cr_out[2:0] end - attribute \src "libresoc.v:994.3-1002.6" - process $proc$libresoc.v:994$192 - assign { } { } - assign { } { } - assign $0\dmi_read_log_data$next[0:0]$193 $1\dmi_read_log_data$next[0:0]$194 - attribute \src "libresoc.v:995.5-995.29" - switch \initial - attribute \src "libresoc.v:995.9-995.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi_read_log_data$next[0:0]$194 1'0 - case - assign $1\dmi_read_log_data$next[0:0]$194 \$120 - end - sync always - update \dmi_read_log_data$next $0\dmi_read_log_data$next[0:0]$193 - end - connect \$9 $and$libresoc.v:708$80_Y - connect \$99 $eq$libresoc.v:709$81_Y - connect \$101 $not$libresoc.v:710$82_Y - connect \$103 $and$libresoc.v:711$83_Y - connect \$105 $not$libresoc.v:712$84_Y - connect \$107 $and$libresoc.v:713$85_Y - connect \$109 $eq$libresoc.v:714$86_Y - connect \$111 $eq$libresoc.v:715$87_Y - connect \$113 $eq$libresoc.v:716$88_Y - connect \$116 $add$libresoc.v:717$89_Y - connect \$118 $eq$libresoc.v:718$90_Y - connect \$11 $eq$libresoc.v:719$91_Y - connect \$120 $and$libresoc.v:720$92_Y - connect \$122 $not$libresoc.v:721$93_Y - connect \$124 $and$libresoc.v:722$94_Y - connect \$13 $eq$libresoc.v:723$95_Y - connect \$15 $eq$libresoc.v:724$96_Y - connect \$17 $not$libresoc.v:725$97_Y - connect \$1 $pos$libresoc.v:726$98_Y - connect \$19 $and$libresoc.v:727$99_Y - connect \$21 $not$libresoc.v:728$100_Y - connect \$23 $and$libresoc.v:729$101_Y - connect \$25 $eq$libresoc.v:730$102_Y - connect \$27 $eq$libresoc.v:731$103_Y - connect \$29 $eq$libresoc.v:732$104_Y - connect \$31 $not$libresoc.v:733$105_Y - connect \$33 $and$libresoc.v:734$106_Y - connect \$35 $not$libresoc.v:735$107_Y - connect \$37 $and$libresoc.v:736$108_Y - connect \$3 $not$libresoc.v:737$109_Y - connect \$39 $eq$libresoc.v:738$110_Y - connect \$41 $eq$libresoc.v:739$111_Y - connect \$43 $eq$libresoc.v:740$112_Y - connect \$45 $not$libresoc.v:741$113_Y - connect \$47 $and$libresoc.v:742$114_Y - connect \$49 $not$libresoc.v:743$115_Y - connect \$51 $and$libresoc.v:744$116_Y - connect \$53 $eq$libresoc.v:745$117_Y - connect \$55 $eq$libresoc.v:746$118_Y - connect \$57 $eq$libresoc.v:747$119_Y - connect \$5 $and$libresoc.v:748$120_Y - connect \$59 $not$libresoc.v:749$121_Y - connect \$61 $and$libresoc.v:750$122_Y - connect \$63 $not$libresoc.v:751$123_Y - connect \$65 $and$libresoc.v:752$124_Y - connect \$67 $eq$libresoc.v:753$125_Y - connect \$69 $eq$libresoc.v:754$126_Y - connect \$71 $eq$libresoc.v:755$127_Y - connect \$73 $not$libresoc.v:756$128_Y - connect \$75 $and$libresoc.v:757$129_Y - connect \$77 $not$libresoc.v:758$130_Y - connect \$7 $not$libresoc.v:759$131_Y - connect \$79 $and$libresoc.v:760$132_Y - connect \$81 $eq$libresoc.v:761$133_Y - connect \$83 $eq$libresoc.v:762$134_Y - connect \$85 $eq$libresoc.v:763$135_Y - connect \$87 $not$libresoc.v:764$136_Y - connect \$89 $and$libresoc.v:765$137_Y - connect \$91 $not$libresoc.v:766$138_Y - connect \$93 $and$libresoc.v:767$139_Y - connect \$95 $eq$libresoc.v:768$140_Y - connect \$97 $eq$libresoc.v:769$141_Y - connect \$115 \$116 - connect \log_write_addr_o 0 - connect \log_dmi_data 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \terminated_o \terminated - connect \icache_rst_o \do_icreset - connect \core_rst_o \do_reset - connect \core_stop_o \$124 - connect \d_gpr_addr \gspr_index - connect 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 output 27 \FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 24 \LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire output 11 \LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire output 23 \OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 20 \RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 21 \RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 18 \RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 19 \RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire output 22 \Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 \SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 10 output 31 \SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 \UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 output 34 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 output 35 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 output 32 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 output 33 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_RB 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \all_PO + attribute \src "libresoc.v:89548.3-89557.6" + wire width 8 $1\dec31_dec_sub16_asmcode[7:0] + attribute \src "libresoc.v:89588.3-89597.6" + wire $1\dec31_dec_sub16_br[0:0] + attribute \src "libresoc.v:89718.3-89727.6" + wire width 3 $1\dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:89728.3-89737.6" + wire width 3 $1\dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:89538.3-89547.6" + wire width 2 $1\dec31_dec_sub16_cry_in[1:0] + attribute \src "libresoc.v:89578.3-89587.6" + wire $1\dec31_dec_sub16_cry_out[0:0] + attribute \src "libresoc.v:89668.3-89677.6" + wire width 5 $1\dec31_dec_sub16_form[4:0] + attribute \src "libresoc.v:89498.3-89507.6" + wire width 12 $1\dec31_dec_sub16_function_unit[11:0] + attribute \src "libresoc.v:89678.3-89687.6" + wire width 3 $1\dec31_dec_sub16_in1_sel[2:0] + attribute \src "libresoc.v:89688.3-89697.6" + wire width 4 $1\dec31_dec_sub16_in2_sel[3:0] + attribute \src "libresoc.v:89698.3-89707.6" + wire width 2 $1\dec31_dec_sub16_in3_sel[1:0] + attribute \src "libresoc.v:89608.3-89617.6" + wire width 7 $1\dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:89558.3-89567.6" + wire $1\dec31_dec_sub16_inv_a[0:0] + attribute \src "libresoc.v:89568.3-89577.6" + wire $1\dec31_dec_sub16_inv_out[0:0] + attribute \src "libresoc.v:89628.3-89637.6" + wire $1\dec31_dec_sub16_is_32b[0:0] + attribute \src "libresoc.v:89508.3-89517.6" + wire width 4 $1\dec31_dec_sub16_ldst_len[3:0] + attribute \src "libresoc.v:89648.3-89657.6" + wire $1\dec31_dec_sub16_lk[0:0] + attribute \src "libresoc.v:89708.3-89717.6" + wire width 2 $1\dec31_dec_sub16_out_sel[1:0] + attribute \src "libresoc.v:89528.3-89537.6" + wire width 2 $1\dec31_dec_sub16_rc_sel[1:0] + attribute \src "libresoc.v:89618.3-89627.6" + wire $1\dec31_dec_sub16_rsrv[0:0] + attribute \src "libresoc.v:89658.3-89667.6" + wire $1\dec31_dec_sub16_sgl_pipe[0:0] + attribute \src "libresoc.v:89638.3-89647.6" + wire $1\dec31_dec_sub16_sgn[0:0] + attribute \src "libresoc.v:89598.3-89607.6" + wire $1\dec31_dec_sub16_sgn_ext[0:0] + attribute \src "libresoc.v:89518.3-89527.6" + wire width 2 $1\dec31_dec_sub16_upd[1:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 16 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" - wire input 36 \bigendian + wire width 8 output 4 \dec31_dec_sub16_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \br + wire output 18 \dec31_dec_sub16_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -4141,27 +140710,896 @@ module \dec attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 4 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" + wire width 3 output 9 \dec31_dec_sub16_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub16_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub16_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub16_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub16_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub16_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub16_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub16_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub16_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub16_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub16_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub16_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub16_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub16_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub16_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" + wire width 2 output 8 \dec31_dec_sub16_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" + attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \cry_in + wire width 2 output 13 \dec31_dec_sub16_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \cry_out + wire output 20 \dec31_dec_sub16_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub16_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub16_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub16_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 \dec19_dec19_asmcode + wire width 2 output 12 \dec31_dec_sub16_upd + attribute \src "libresoc.v:89241.7-89241.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:89241.7-89241.20" + process $proc$libresoc.v:89241$3846 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:89498.3-89507.6" + process $proc$libresoc.v:89498$3822 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_function_unit[11:0] $1\dec31_dec_sub16_function_unit[11:0] + attribute \src "libresoc.v:89499.5-89499.29" + switch \initial + attribute \src "libresoc.v:89499.9-89499.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_function_unit[11:0] 12'000001000000 + case + assign $1\dec31_dec_sub16_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub16_function_unit $0\dec31_dec_sub16_function_unit[11:0] + end + attribute \src "libresoc.v:89508.3-89517.6" + process $proc$libresoc.v:89508$3823 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_ldst_len[3:0] $1\dec31_dec_sub16_ldst_len[3:0] + attribute \src "libresoc.v:89509.5-89509.29" + switch \initial + attribute \src "libresoc.v:89509.9-89509.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub16_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub16_ldst_len $0\dec31_dec_sub16_ldst_len[3:0] + end + attribute \src "libresoc.v:89518.3-89527.6" + process $proc$libresoc.v:89518$3824 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_upd[1:0] $1\dec31_dec_sub16_upd[1:0] + attribute \src "libresoc.v:89519.5-89519.29" + switch \initial + attribute \src "libresoc.v:89519.9-89519.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub16_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_upd $0\dec31_dec_sub16_upd[1:0] + end + attribute \src "libresoc.v:89528.3-89537.6" + process $proc$libresoc.v:89528$3825 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_rc_sel[1:0] $1\dec31_dec_sub16_rc_sel[1:0] + attribute \src "libresoc.v:89529.5-89529.29" + switch \initial + attribute \src "libresoc.v:89529.9-89529.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub16_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_rc_sel $0\dec31_dec_sub16_rc_sel[1:0] + end + attribute \src "libresoc.v:89538.3-89547.6" + process $proc$libresoc.v:89538$3826 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_cry_in[1:0] $1\dec31_dec_sub16_cry_in[1:0] + attribute \src "libresoc.v:89539.5-89539.29" + switch \initial + attribute \src "libresoc.v:89539.9-89539.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub16_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_cry_in $0\dec31_dec_sub16_cry_in[1:0] + end + attribute \src "libresoc.v:89548.3-89557.6" + process $proc$libresoc.v:89548$3827 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_asmcode[7:0] $1\dec31_dec_sub16_asmcode[7:0] + attribute \src "libresoc.v:89549.5-89549.29" + switch \initial + attribute \src "libresoc.v:89549.9-89549.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_asmcode[7:0] 8'01110110 + case + assign $1\dec31_dec_sub16_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub16_asmcode $0\dec31_dec_sub16_asmcode[7:0] + end + attribute \src "libresoc.v:89558.3-89567.6" + process $proc$libresoc.v:89558$3828 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_inv_a[0:0] $1\dec31_dec_sub16_inv_a[0:0] + attribute \src "libresoc.v:89559.5-89559.29" + switch \initial + attribute \src "libresoc.v:89559.9-89559.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub16_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_inv_a $0\dec31_dec_sub16_inv_a[0:0] + end + attribute \src "libresoc.v:89568.3-89577.6" + process $proc$libresoc.v:89568$3829 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_inv_out[0:0] $1\dec31_dec_sub16_inv_out[0:0] + attribute \src "libresoc.v:89569.5-89569.29" + switch \initial + attribute \src "libresoc.v:89569.9-89569.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub16_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_inv_out $0\dec31_dec_sub16_inv_out[0:0] + end + attribute \src "libresoc.v:89578.3-89587.6" + process $proc$libresoc.v:89578$3830 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_cry_out[0:0] $1\dec31_dec_sub16_cry_out[0:0] + attribute \src "libresoc.v:89579.5-89579.29" + switch \initial + attribute \src "libresoc.v:89579.9-89579.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub16_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_cry_out $0\dec31_dec_sub16_cry_out[0:0] + end + attribute \src "libresoc.v:89588.3-89597.6" + process $proc$libresoc.v:89588$3831 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_br[0:0] $1\dec31_dec_sub16_br[0:0] + attribute \src "libresoc.v:89589.5-89589.29" + switch \initial + attribute \src "libresoc.v:89589.9-89589.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_br[0:0] 1'0 + case + assign $1\dec31_dec_sub16_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_br $0\dec31_dec_sub16_br[0:0] + end + attribute \src "libresoc.v:89598.3-89607.6" + process $proc$libresoc.v:89598$3832 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sgn_ext[0:0] $1\dec31_dec_sub16_sgn_ext[0:0] + attribute \src "libresoc.v:89599.5-89599.29" + switch \initial + attribute \src "libresoc.v:89599.9-89599.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub16_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_sgn_ext $0\dec31_dec_sub16_sgn_ext[0:0] + end + attribute \src "libresoc.v:89608.3-89617.6" + process $proc$libresoc.v:89608$3833 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_internal_op[6:0] $1\dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:89609.5-89609.29" + switch \initial + attribute \src "libresoc.v:89609.9-89609.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_internal_op[6:0] 7'0110000 + case + assign $1\dec31_dec_sub16_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub16_internal_op $0\dec31_dec_sub16_internal_op[6:0] + end + attribute \src "libresoc.v:89618.3-89627.6" + process $proc$libresoc.v:89618$3834 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_rsrv[0:0] $1\dec31_dec_sub16_rsrv[0:0] + attribute \src "libresoc.v:89619.5-89619.29" + switch \initial + attribute \src "libresoc.v:89619.9-89619.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub16_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_rsrv $0\dec31_dec_sub16_rsrv[0:0] + end + attribute \src "libresoc.v:89628.3-89637.6" + process $proc$libresoc.v:89628$3835 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_is_32b[0:0] $1\dec31_dec_sub16_is_32b[0:0] + attribute \src "libresoc.v:89629.5-89629.29" + switch \initial + attribute \src "libresoc.v:89629.9-89629.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_is_32b $0\dec31_dec_sub16_is_32b[0:0] + end + attribute \src "libresoc.v:89638.3-89647.6" + process $proc$libresoc.v:89638$3836 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sgn[0:0] $1\dec31_dec_sub16_sgn[0:0] + attribute \src "libresoc.v:89639.5-89639.29" + switch \initial + attribute \src "libresoc.v:89639.9-89639.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub16_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_sgn $0\dec31_dec_sub16_sgn[0:0] + end + attribute \src "libresoc.v:89648.3-89657.6" + process $proc$libresoc.v:89648$3837 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_lk[0:0] $1\dec31_dec_sub16_lk[0:0] + attribute \src "libresoc.v:89649.5-89649.29" + switch \initial + attribute \src "libresoc.v:89649.9-89649.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub16_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_lk $0\dec31_dec_sub16_lk[0:0] + end + attribute \src "libresoc.v:89658.3-89667.6" + process $proc$libresoc.v:89658$3838 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sgl_pipe[0:0] $1\dec31_dec_sub16_sgl_pipe[0:0] + attribute \src "libresoc.v:89659.5-89659.29" + switch \initial + attribute \src "libresoc.v:89659.9-89659.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub16_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_sgl_pipe $0\dec31_dec_sub16_sgl_pipe[0:0] + end + attribute \src "libresoc.v:89668.3-89677.6" + process $proc$libresoc.v:89668$3839 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_form[4:0] $1\dec31_dec_sub16_form[4:0] + attribute \src "libresoc.v:89669.5-89669.29" + switch \initial + attribute \src "libresoc.v:89669.9-89669.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_form[4:0] 5'01010 + case + assign $1\dec31_dec_sub16_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub16_form $0\dec31_dec_sub16_form[4:0] + end + attribute \src "libresoc.v:89678.3-89687.6" + process $proc$libresoc.v:89678$3840 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_in1_sel[2:0] $1\dec31_dec_sub16_in1_sel[2:0] + attribute \src "libresoc.v:89679.5-89679.29" + switch \initial + attribute \src "libresoc.v:89679.9-89679.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_in1_sel[2:0] 3'100 + case + assign $1\dec31_dec_sub16_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_in1_sel $0\dec31_dec_sub16_in1_sel[2:0] + end + attribute \src "libresoc.v:89688.3-89697.6" + process $proc$libresoc.v:89688$3841 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_in2_sel[3:0] $1\dec31_dec_sub16_in2_sel[3:0] + attribute \src "libresoc.v:89689.5-89689.29" + switch \initial + attribute \src "libresoc.v:89689.9-89689.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub16_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub16_in2_sel $0\dec31_dec_sub16_in2_sel[3:0] + end + attribute \src "libresoc.v:89698.3-89707.6" + process $proc$libresoc.v:89698$3842 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_in3_sel[1:0] $1\dec31_dec_sub16_in3_sel[1:0] + attribute \src "libresoc.v:89699.5-89699.29" + switch \initial + attribute \src "libresoc.v:89699.9-89699.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub16_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_in3_sel $0\dec31_dec_sub16_in3_sel[1:0] + end + attribute \src "libresoc.v:89708.3-89717.6" + process $proc$libresoc.v:89708$3843 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_out_sel[1:0] $1\dec31_dec_sub16_out_sel[1:0] + attribute \src "libresoc.v:89709.5-89709.29" + switch \initial + attribute \src "libresoc.v:89709.9-89709.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub16_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_out_sel $0\dec31_dec_sub16_out_sel[1:0] + end + attribute \src "libresoc.v:89718.3-89727.6" + process $proc$libresoc.v:89718$3844 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_cr_in[2:0] $1\dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:89719.5-89719.29" + switch \initial + attribute \src "libresoc.v:89719.9-89719.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_cr_in[2:0] 3'110 + case + assign $1\dec31_dec_sub16_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_cr_in $0\dec31_dec_sub16_cr_in[2:0] + end + attribute \src "libresoc.v:89728.3-89737.6" + process $proc$libresoc.v:89728$3845 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_cr_out[2:0] $1\dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:89729.5-89729.29" + switch \initial + attribute \src "libresoc.v:89729.9-89729.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_cr_out[2:0] 3'100 + case + assign $1\dec31_dec_sub16_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_cr_out $0\dec31_dec_sub16_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:89743.1-90530.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub18" +attribute \generator "nMigen" +module \dec31_dec_sub18 + attribute \src "libresoc.v:90111.3-90132.6" + wire width 8 $0\dec31_dec_sub18_asmcode[7:0] + attribute \src "libresoc.v:90199.3-90220.6" + wire $0\dec31_dec_sub18_br[0:0] + attribute \src "libresoc.v:90485.3-90506.6" + wire width 3 $0\dec31_dec_sub18_cr_in[2:0] + attribute \src "libresoc.v:90507.3-90528.6" + wire width 3 $0\dec31_dec_sub18_cr_out[2:0] + attribute \src "libresoc.v:90089.3-90110.6" + wire width 2 $0\dec31_dec_sub18_cry_in[1:0] + attribute \src "libresoc.v:90177.3-90198.6" + wire $0\dec31_dec_sub18_cry_out[0:0] + attribute \src "libresoc.v:90375.3-90396.6" + wire width 5 $0\dec31_dec_sub18_form[4:0] + attribute \src "libresoc.v:90001.3-90022.6" + wire width 12 $0\dec31_dec_sub18_function_unit[11:0] + attribute \src "libresoc.v:90397.3-90418.6" + wire width 3 $0\dec31_dec_sub18_in1_sel[2:0] + attribute \src "libresoc.v:90419.3-90440.6" + wire width 4 $0\dec31_dec_sub18_in2_sel[3:0] + attribute \src "libresoc.v:90441.3-90462.6" + wire width 2 $0\dec31_dec_sub18_in3_sel[1:0] + attribute \src "libresoc.v:90243.3-90264.6" + wire width 7 $0\dec31_dec_sub18_internal_op[6:0] + attribute \src "libresoc.v:90133.3-90154.6" + wire $0\dec31_dec_sub18_inv_a[0:0] + attribute \src "libresoc.v:90155.3-90176.6" + wire $0\dec31_dec_sub18_inv_out[0:0] + attribute \src "libresoc.v:90287.3-90308.6" + wire $0\dec31_dec_sub18_is_32b[0:0] + attribute \src "libresoc.v:90023.3-90044.6" + wire width 4 $0\dec31_dec_sub18_ldst_len[3:0] + attribute \src "libresoc.v:90331.3-90352.6" + wire $0\dec31_dec_sub18_lk[0:0] + attribute \src "libresoc.v:90463.3-90484.6" + wire width 2 $0\dec31_dec_sub18_out_sel[1:0] + attribute \src "libresoc.v:90067.3-90088.6" + wire width 2 $0\dec31_dec_sub18_rc_sel[1:0] + attribute \src "libresoc.v:90265.3-90286.6" + wire $0\dec31_dec_sub18_rsrv[0:0] + attribute \src "libresoc.v:90353.3-90374.6" + wire $0\dec31_dec_sub18_sgl_pipe[0:0] + attribute \src "libresoc.v:90309.3-90330.6" + wire $0\dec31_dec_sub18_sgn[0:0] + attribute \src "libresoc.v:90221.3-90242.6" + wire $0\dec31_dec_sub18_sgn_ext[0:0] + attribute \src "libresoc.v:90045.3-90066.6" + wire width 2 $0\dec31_dec_sub18_upd[1:0] + attribute \src "libresoc.v:89744.7-89744.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:90111.3-90132.6" + wire width 8 $1\dec31_dec_sub18_asmcode[7:0] + attribute \src "libresoc.v:90199.3-90220.6" + wire $1\dec31_dec_sub18_br[0:0] + attribute \src "libresoc.v:90485.3-90506.6" + wire width 3 $1\dec31_dec_sub18_cr_in[2:0] + attribute \src "libresoc.v:90507.3-90528.6" + wire width 3 $1\dec31_dec_sub18_cr_out[2:0] + attribute \src "libresoc.v:90089.3-90110.6" + wire width 2 $1\dec31_dec_sub18_cry_in[1:0] + attribute \src "libresoc.v:90177.3-90198.6" + wire $1\dec31_dec_sub18_cry_out[0:0] + attribute \src "libresoc.v:90375.3-90396.6" + wire width 5 $1\dec31_dec_sub18_form[4:0] + attribute \src "libresoc.v:90001.3-90022.6" + wire width 12 $1\dec31_dec_sub18_function_unit[11:0] + attribute \src "libresoc.v:90397.3-90418.6" + wire width 3 $1\dec31_dec_sub18_in1_sel[2:0] + attribute \src "libresoc.v:90419.3-90440.6" + wire width 4 $1\dec31_dec_sub18_in2_sel[3:0] + attribute \src "libresoc.v:90441.3-90462.6" + wire width 2 $1\dec31_dec_sub18_in3_sel[1:0] + attribute \src "libresoc.v:90243.3-90264.6" + wire width 7 $1\dec31_dec_sub18_internal_op[6:0] + attribute \src "libresoc.v:90133.3-90154.6" + wire $1\dec31_dec_sub18_inv_a[0:0] + attribute \src "libresoc.v:90155.3-90176.6" + wire $1\dec31_dec_sub18_inv_out[0:0] + attribute \src "libresoc.v:90287.3-90308.6" + wire $1\dec31_dec_sub18_is_32b[0:0] + attribute \src "libresoc.v:90023.3-90044.6" + wire width 4 $1\dec31_dec_sub18_ldst_len[3:0] + attribute \src "libresoc.v:90331.3-90352.6" + wire $1\dec31_dec_sub18_lk[0:0] + attribute \src "libresoc.v:90463.3-90484.6" + wire width 2 $1\dec31_dec_sub18_out_sel[1:0] + attribute \src "libresoc.v:90067.3-90088.6" + wire width 2 $1\dec31_dec_sub18_rc_sel[1:0] + attribute \src "libresoc.v:90265.3-90286.6" + wire $1\dec31_dec_sub18_rsrv[0:0] + attribute \src "libresoc.v:90353.3-90374.6" + wire $1\dec31_dec_sub18_sgl_pipe[0:0] + attribute \src "libresoc.v:90309.3-90330.6" + wire $1\dec31_dec_sub18_sgn[0:0] + attribute \src "libresoc.v:90221.3-90242.6" + wire $1\dec31_dec_sub18_sgn_ext[0:0] + attribute \src "libresoc.v:90045.3-90066.6" + wire width 2 $1\dec31_dec_sub18_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub18_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec19_dec19_br + wire output 18 \dec31_dec_sub18_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -4171,7 +141609,7 @@ module \dec attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec19_dec19_cr_in + wire width 3 output 9 \dec31_dec_sub18_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -4179,15 +141617,15 @@ module \dec attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec19_dec19_cr_out + wire width 3 output 10 \dec31_dec_sub18_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec19_dec19_cry_in + wire width 2 output 14 \dec31_dec_sub18_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec19_dec19_cry_out + wire output 17 \dec31_dec_sub18_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -4219,7 +141657,7 @@ module \dec attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 \dec19_dec19_form + wire width 5 output 3 \dec31_dec_sub18_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -4234,7 +141672,7 @@ module \dec attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec19_dec19_function_unit + wire width 12 output 1 \dec31_dec_sub18_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -4242,7 +141680,7 @@ module \dec attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec19_dec19_in1_sel + wire width 3 output 5 \dec31_dec_sub18_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -4259,13 +141697,13 @@ module \dec attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec19_dec19_in2_sel + wire width 4 output 6 \dec31_dec_sub18_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec19_dec19_in3_sel + wire width 2 output 7 \dec31_dec_sub18_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -4341,13 +141779,13 @@ module \dec attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec19_dec19_internal_op + wire width 7 output 2 \dec31_dec_sub18_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec19_dec19_inv_a + wire output 15 \dec31_dec_sub18_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec19_dec19_inv_out + wire output 16 \dec31_dec_sub18_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec19_dec19_is_32b + wire output 21 \dec31_dec_sub18_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" @@ -4355,43 +141793,1096 @@ module \dec attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec19_dec19_ldst_len + wire width 4 output 11 \dec31_dec_sub18_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec19_dec19_lk + wire output 23 \dec31_dec_sub18_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec19_dec19_out_sel + wire width 2 output 8 \dec31_dec_sub18_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec19_dec19_rc_sel + wire width 2 output 13 \dec31_dec_sub18_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec19_dec19_rsrv + wire output 20 \dec31_dec_sub18_rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec19_dec19_sgl_pipe + wire output 24 \dec31_dec_sub18_sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec19_dec19_sgn + wire output 22 \dec31_dec_sub18_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec19_dec19_sgn_ext + wire output 19 \dec31_dec_sub18_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec19_dec19_upd + wire width 2 output 12 \dec31_dec_sub18_upd + attribute \src "libresoc.v:89744.7-89744.15" + wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec19_opcode_in + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:89744.7-89744.20" + process $proc$libresoc.v:89744$3871 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:90001.3-90022.6" + process $proc$libresoc.v:90001$3847 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_function_unit[11:0] $1\dec31_dec_sub18_function_unit[11:0] + attribute \src "libresoc.v:90002.5-90002.29" + switch \initial + attribute \src "libresoc.v:90002.9-90002.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[11:0] 12'100000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[11:0] 12'100000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[11:0] 12'100000000000 + case + assign $1\dec31_dec_sub18_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub18_function_unit $0\dec31_dec_sub18_function_unit[11:0] + end + attribute \src "libresoc.v:90023.3-90044.6" + process $proc$libresoc.v:90023$3848 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_ldst_len[3:0] $1\dec31_dec_sub18_ldst_len[3:0] + attribute \src "libresoc.v:90024.5-90024.29" + switch \initial + attribute \src "libresoc.v:90024.9-90024.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub18_ldst_len $0\dec31_dec_sub18_ldst_len[3:0] + end + attribute \src "libresoc.v:90045.3-90066.6" + process $proc$libresoc.v:90045$3849 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_upd[1:0] $1\dec31_dec_sub18_upd[1:0] + attribute \src "libresoc.v:90046.5-90046.29" + switch \initial + attribute \src "libresoc.v:90046.9-90046.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_upd $0\dec31_dec_sub18_upd[1:0] + end + attribute \src "libresoc.v:90067.3-90088.6" + process $proc$libresoc.v:90067$3850 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_rc_sel[1:0] $1\dec31_dec_sub18_rc_sel[1:0] + attribute \src "libresoc.v:90068.5-90068.29" + switch \initial + attribute \src "libresoc.v:90068.9-90068.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_rc_sel $0\dec31_dec_sub18_rc_sel[1:0] + end + attribute \src "libresoc.v:90089.3-90110.6" + process $proc$libresoc.v:90089$3851 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cry_in[1:0] $1\dec31_dec_sub18_cry_in[1:0] + attribute \src "libresoc.v:90090.5-90090.29" + switch \initial + attribute \src "libresoc.v:90090.9-90090.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_cry_in $0\dec31_dec_sub18_cry_in[1:0] + end + attribute \src "libresoc.v:90111.3-90132.6" + process $proc$libresoc.v:90111$3852 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_asmcode[7:0] $1\dec31_dec_sub18_asmcode[7:0] + attribute \src "libresoc.v:90112.5-90112.29" + switch \initial + attribute \src "libresoc.v:90112.9-90112.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'01111000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'01110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'10011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'11001100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'11001101 + case + assign $1\dec31_dec_sub18_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub18_asmcode $0\dec31_dec_sub18_asmcode[7:0] + end + attribute \src "libresoc.v:90133.3-90154.6" + process $proc$libresoc.v:90133$3853 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_inv_a[0:0] $1\dec31_dec_sub18_inv_a[0:0] + attribute \src "libresoc.v:90134.5-90134.29" + switch \initial + attribute \src "libresoc.v:90134.9-90134.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_inv_a $0\dec31_dec_sub18_inv_a[0:0] + end + attribute \src "libresoc.v:90155.3-90176.6" + process $proc$libresoc.v:90155$3854 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_inv_out[0:0] $1\dec31_dec_sub18_inv_out[0:0] + attribute \src "libresoc.v:90156.5-90156.29" + switch \initial + attribute \src "libresoc.v:90156.9-90156.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_inv_out $0\dec31_dec_sub18_inv_out[0:0] + end + attribute \src "libresoc.v:90177.3-90198.6" + process $proc$libresoc.v:90177$3855 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cry_out[0:0] $1\dec31_dec_sub18_cry_out[0:0] + attribute \src "libresoc.v:90178.5-90178.29" + switch \initial + attribute \src "libresoc.v:90178.9-90178.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_cry_out $0\dec31_dec_sub18_cry_out[0:0] + end + attribute \src "libresoc.v:90199.3-90220.6" + process $proc$libresoc.v:90199$3856 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_br[0:0] $1\dec31_dec_sub18_br[0:0] + attribute \src "libresoc.v:90200.5-90200.29" + switch \initial + attribute \src "libresoc.v:90200.9-90200.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + case + assign $1\dec31_dec_sub18_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_br $0\dec31_dec_sub18_br[0:0] + end + attribute \src "libresoc.v:90221.3-90242.6" + process $proc$libresoc.v:90221$3857 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sgn_ext[0:0] $1\dec31_dec_sub18_sgn_ext[0:0] + attribute \src "libresoc.v:90222.5-90222.29" + switch \initial + attribute \src "libresoc.v:90222.9-90222.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_sgn_ext $0\dec31_dec_sub18_sgn_ext[0:0] + end + attribute \src "libresoc.v:90243.3-90264.6" + process $proc$libresoc.v:90243$3858 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_internal_op[6:0] $1\dec31_dec_sub18_internal_op[6:0] + attribute \src "libresoc.v:90244.5-90244.29" + switch \initial + attribute \src "libresoc.v:90244.9-90244.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + case + assign $1\dec31_dec_sub18_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub18_internal_op $0\dec31_dec_sub18_internal_op[6:0] + end + attribute \src "libresoc.v:90265.3-90286.6" + process $proc$libresoc.v:90265$3859 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_rsrv[0:0] $1\dec31_dec_sub18_rsrv[0:0] + attribute \src "libresoc.v:90266.5-90266.29" + switch \initial + attribute \src "libresoc.v:90266.9-90266.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_rsrv $0\dec31_dec_sub18_rsrv[0:0] + end + attribute \src "libresoc.v:90287.3-90308.6" + process $proc$libresoc.v:90287$3860 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_is_32b[0:0] $1\dec31_dec_sub18_is_32b[0:0] + attribute \src "libresoc.v:90288.5-90288.29" + switch \initial + attribute \src "libresoc.v:90288.9-90288.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_is_32b $0\dec31_dec_sub18_is_32b[0:0] + end + attribute \src "libresoc.v:90309.3-90330.6" + process $proc$libresoc.v:90309$3861 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sgn[0:0] $1\dec31_dec_sub18_sgn[0:0] + attribute \src "libresoc.v:90310.5-90310.29" + switch \initial + attribute \src "libresoc.v:90310.9-90310.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_sgn $0\dec31_dec_sub18_sgn[0:0] + end + attribute \src "libresoc.v:90331.3-90352.6" + process $proc$libresoc.v:90331$3862 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_lk[0:0] $1\dec31_dec_sub18_lk[0:0] + attribute \src "libresoc.v:90332.5-90332.29" + switch \initial + attribute \src "libresoc.v:90332.9-90332.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_lk $0\dec31_dec_sub18_lk[0:0] + end + attribute \src "libresoc.v:90353.3-90374.6" + process $proc$libresoc.v:90353$3863 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sgl_pipe[0:0] $1\dec31_dec_sub18_sgl_pipe[0:0] + attribute \src "libresoc.v:90354.5-90354.29" + switch \initial + attribute \src "libresoc.v:90354.9-90354.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_sgl_pipe $0\dec31_dec_sub18_sgl_pipe[0:0] + end + attribute \src "libresoc.v:90375.3-90396.6" + process $proc$libresoc.v:90375$3864 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_form[4:0] $1\dec31_dec_sub18_form[4:0] + attribute \src "libresoc.v:90376.5-90376.29" + switch \initial + attribute \src "libresoc.v:90376.9-90376.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub18_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub18_form $0\dec31_dec_sub18_form[4:0] + end + attribute \src "libresoc.v:90397.3-90418.6" + process $proc$libresoc.v:90397$3865 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_in1_sel[2:0] $1\dec31_dec_sub18_in1_sel[2:0] + attribute \src "libresoc.v:90398.5-90398.29" + switch \initial + attribute \src "libresoc.v:90398.9-90398.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_in1_sel $0\dec31_dec_sub18_in1_sel[2:0] + end + attribute \src "libresoc.v:90419.3-90440.6" + process $proc$libresoc.v:90419$3866 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_in2_sel[3:0] $1\dec31_dec_sub18_in2_sel[3:0] + attribute \src "libresoc.v:90420.5-90420.29" + switch \initial + attribute \src "libresoc.v:90420.9-90420.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub18_in2_sel $0\dec31_dec_sub18_in2_sel[3:0] + end + attribute \src "libresoc.v:90441.3-90462.6" + process $proc$libresoc.v:90441$3867 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_in3_sel[1:0] $1\dec31_dec_sub18_in3_sel[1:0] + attribute \src "libresoc.v:90442.5-90442.29" + switch \initial + attribute \src "libresoc.v:90442.9-90442.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_in3_sel $0\dec31_dec_sub18_in3_sel[1:0] + end + attribute \src "libresoc.v:90463.3-90484.6" + process $proc$libresoc.v:90463$3868 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_out_sel[1:0] $1\dec31_dec_sub18_out_sel[1:0] + attribute \src "libresoc.v:90464.5-90464.29" + switch \initial + attribute \src "libresoc.v:90464.9-90464.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_out_sel $0\dec31_dec_sub18_out_sel[1:0] + end + attribute \src "libresoc.v:90485.3-90506.6" + process $proc$libresoc.v:90485$3869 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cr_in[2:0] $1\dec31_dec_sub18_cr_in[2:0] + attribute \src "libresoc.v:90486.5-90486.29" + switch \initial + attribute \src "libresoc.v:90486.9-90486.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_cr_in $0\dec31_dec_sub18_cr_in[2:0] + end + attribute \src "libresoc.v:90507.3-90528.6" + process $proc$libresoc.v:90507$3870 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cr_out[2:0] $1\dec31_dec_sub18_cr_out[2:0] + attribute \src "libresoc.v:90508.5-90508.29" + switch \initial + attribute \src "libresoc.v:90508.9-90508.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_cr_out $0\dec31_dec_sub18_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:90534.1-91249.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub19" +attribute \generator "nMigen" +module \dec31_dec_sub19 + attribute \src "libresoc.v:90887.3-90905.6" + wire width 8 $0\dec31_dec_sub19_asmcode[7:0] + attribute \src "libresoc.v:90963.3-90981.6" + wire $0\dec31_dec_sub19_br[0:0] + attribute \src "libresoc.v:91210.3-91228.6" + wire width 3 $0\dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:91229.3-91247.6" + wire width 3 $0\dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:90868.3-90886.6" + wire width 2 $0\dec31_dec_sub19_cry_in[1:0] + attribute \src "libresoc.v:90944.3-90962.6" + wire $0\dec31_dec_sub19_cry_out[0:0] + attribute \src "libresoc.v:91115.3-91133.6" + wire width 5 $0\dec31_dec_sub19_form[4:0] + attribute \src "libresoc.v:90792.3-90810.6" + wire width 12 $0\dec31_dec_sub19_function_unit[11:0] + attribute \src "libresoc.v:91134.3-91152.6" + wire width 3 $0\dec31_dec_sub19_in1_sel[2:0] + attribute \src "libresoc.v:91153.3-91171.6" + wire width 4 $0\dec31_dec_sub19_in2_sel[3:0] + attribute \src "libresoc.v:91172.3-91190.6" + wire width 2 $0\dec31_dec_sub19_in3_sel[1:0] + attribute \src "libresoc.v:91001.3-91019.6" + wire width 7 $0\dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:90906.3-90924.6" + wire $0\dec31_dec_sub19_inv_a[0:0] + attribute \src "libresoc.v:90925.3-90943.6" + wire $0\dec31_dec_sub19_inv_out[0:0] + attribute \src "libresoc.v:91039.3-91057.6" + wire $0\dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:90811.3-90829.6" + wire width 4 $0\dec31_dec_sub19_ldst_len[3:0] + attribute \src "libresoc.v:91077.3-91095.6" + wire $0\dec31_dec_sub19_lk[0:0] + attribute \src "libresoc.v:91191.3-91209.6" + wire width 2 $0\dec31_dec_sub19_out_sel[1:0] + attribute \src "libresoc.v:90849.3-90867.6" + wire width 2 $0\dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:91020.3-91038.6" + wire $0\dec31_dec_sub19_rsrv[0:0] + attribute \src "libresoc.v:91096.3-91114.6" + wire $0\dec31_dec_sub19_sgl_pipe[0:0] + attribute \src "libresoc.v:91058.3-91076.6" + wire $0\dec31_dec_sub19_sgn[0:0] + attribute \src "libresoc.v:90982.3-91000.6" + wire $0\dec31_dec_sub19_sgn_ext[0:0] + attribute \src "libresoc.v:90830.3-90848.6" + wire width 2 $0\dec31_dec_sub19_upd[1:0] + attribute \src "libresoc.v:90535.7-90535.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:90887.3-90905.6" + wire width 8 $1\dec31_dec_sub19_asmcode[7:0] + attribute \src "libresoc.v:90963.3-90981.6" + wire $1\dec31_dec_sub19_br[0:0] + attribute \src "libresoc.v:91210.3-91228.6" + wire width 3 $1\dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:91229.3-91247.6" + wire width 3 $1\dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:90868.3-90886.6" + wire width 2 $1\dec31_dec_sub19_cry_in[1:0] + attribute \src "libresoc.v:90944.3-90962.6" + wire $1\dec31_dec_sub19_cry_out[0:0] + attribute \src "libresoc.v:91115.3-91133.6" + wire width 5 $1\dec31_dec_sub19_form[4:0] + attribute \src "libresoc.v:90792.3-90810.6" + wire width 12 $1\dec31_dec_sub19_function_unit[11:0] + attribute \src "libresoc.v:91134.3-91152.6" + wire width 3 $1\dec31_dec_sub19_in1_sel[2:0] + attribute \src "libresoc.v:91153.3-91171.6" + wire width 4 $1\dec31_dec_sub19_in2_sel[3:0] + attribute \src "libresoc.v:91172.3-91190.6" + wire width 2 $1\dec31_dec_sub19_in3_sel[1:0] + attribute \src "libresoc.v:91001.3-91019.6" + wire width 7 $1\dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:90906.3-90924.6" + wire $1\dec31_dec_sub19_inv_a[0:0] + attribute \src "libresoc.v:90925.3-90943.6" + wire $1\dec31_dec_sub19_inv_out[0:0] + attribute \src "libresoc.v:91039.3-91057.6" + wire $1\dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:90811.3-90829.6" + wire width 4 $1\dec31_dec_sub19_ldst_len[3:0] + attribute \src "libresoc.v:91077.3-91095.6" + wire $1\dec31_dec_sub19_lk[0:0] + attribute \src "libresoc.v:91191.3-91209.6" + wire width 2 $1\dec31_dec_sub19_out_sel[1:0] + attribute \src "libresoc.v:90849.3-90867.6" + wire width 2 $1\dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:91020.3-91038.6" + wire $1\dec31_dec_sub19_rsrv[0:0] + attribute \src "libresoc.v:91096.3-91114.6" + wire $1\dec31_dec_sub19_sgl_pipe[0:0] + attribute \src "libresoc.v:91058.3-91076.6" + wire $1\dec31_dec_sub19_sgn[0:0] + attribute \src "libresoc.v:90982.3-91000.6" + wire $1\dec31_dec_sub19_sgn_ext[0:0] + attribute \src "libresoc.v:90830.3-90848.6" + wire width 2 $1\dec31_dec_sub19_upd[1:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 \dec30_dec30_asmcode + wire width 8 output 4 \dec31_dec_sub19_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec30_dec30_br + wire output 18 \dec31_dec_sub19_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -4401,7 +142892,7 @@ module \dec attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec30_dec30_cr_in + wire width 3 output 9 \dec31_dec_sub19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -4409,15 +142900,15 @@ module \dec attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec30_dec30_cr_out + wire width 3 output 10 \dec31_dec_sub19_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec30_dec30_cry_in + wire width 2 output 14 \dec31_dec_sub19_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec30_dec30_cry_out + wire output 17 \dec31_dec_sub19_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -4449,7 +142940,7 @@ module \dec attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 \dec30_dec30_form + wire width 5 output 3 \dec31_dec_sub19_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -4464,7 +142955,7 @@ module \dec attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec30_dec30_function_unit + wire width 12 output 1 \dec31_dec_sub19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -4472,7 +142963,7 @@ module \dec attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec30_dec30_in1_sel + wire width 3 output 5 \dec31_dec_sub19_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -4489,13 +142980,13 @@ module \dec attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec30_dec30_in2_sel + wire width 4 output 6 \dec31_dec_sub19_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec30_dec30_in3_sel + wire width 2 output 7 \dec31_dec_sub19_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -4571,13 +143062,13 @@ module \dec attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec30_dec30_internal_op + wire width 7 output 2 \dec31_dec_sub19_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec30_dec30_inv_a + wire output 15 \dec31_dec_sub19_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec30_dec30_inv_out + wire output 16 \dec31_dec_sub19_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec30_dec30_is_32b + wire output 21 \dec31_dec_sub19_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" @@ -4585,43 +143076,1000 @@ module \dec attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec30_dec30_ldst_len + wire width 4 output 11 \dec31_dec_sub19_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec30_dec30_lk + wire output 23 \dec31_dec_sub19_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec30_dec30_out_sel + wire width 2 output 8 \dec31_dec_sub19_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec30_dec30_rc_sel + wire width 2 output 13 \dec31_dec_sub19_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec30_dec30_rsrv + wire output 20 \dec31_dec_sub19_rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec30_dec30_sgl_pipe + wire output 24 \dec31_dec_sub19_sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec30_dec30_sgn + wire output 22 \dec31_dec_sub19_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec30_dec30_sgn_ext + wire output 19 \dec31_dec_sub19_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec30_dec30_upd + wire width 2 output 12 \dec31_dec_sub19_upd + attribute \src "libresoc.v:90535.7-90535.15" + wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec30_opcode_in + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:90535.7-90535.20" + process $proc$libresoc.v:90535$3896 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:90792.3-90810.6" + process $proc$libresoc.v:90792$3872 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_function_unit[11:0] $1\dec31_dec_sub19_function_unit[11:0] + attribute \src "libresoc.v:90793.5-90793.29" + switch \initial + attribute \src "libresoc.v:90793.9-90793.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[11:0] 12'010000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[11:0] 12'010000000000 + case + assign $1\dec31_dec_sub19_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub19_function_unit $0\dec31_dec_sub19_function_unit[11:0] + end + attribute \src "libresoc.v:90811.3-90829.6" + process $proc$libresoc.v:90811$3873 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_ldst_len[3:0] $1\dec31_dec_sub19_ldst_len[3:0] + attribute \src "libresoc.v:90812.5-90812.29" + switch \initial + attribute \src "libresoc.v:90812.9-90812.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub19_ldst_len $0\dec31_dec_sub19_ldst_len[3:0] + end + attribute \src "libresoc.v:90830.3-90848.6" + process $proc$libresoc.v:90830$3874 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_upd[1:0] $1\dec31_dec_sub19_upd[1:0] + attribute \src "libresoc.v:90831.5-90831.29" + switch \initial + attribute \src "libresoc.v:90831.9-90831.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_upd $0\dec31_dec_sub19_upd[1:0] + end + attribute \src "libresoc.v:90849.3-90867.6" + process $proc$libresoc.v:90849$3875 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_rc_sel[1:0] $1\dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:90850.5-90850.29" + switch \initial + attribute \src "libresoc.v:90850.9-90850.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_rc_sel $0\dec31_dec_sub19_rc_sel[1:0] + end + attribute \src "libresoc.v:90868.3-90886.6" + process $proc$libresoc.v:90868$3876 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cry_in[1:0] $1\dec31_dec_sub19_cry_in[1:0] + attribute \src "libresoc.v:90869.5-90869.29" + switch \initial + attribute \src "libresoc.v:90869.9-90869.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_cry_in $0\dec31_dec_sub19_cry_in[1:0] + end + attribute \src "libresoc.v:90887.3-90905.6" + process $proc$libresoc.v:90887$3877 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_asmcode[7:0] $1\dec31_dec_sub19_asmcode[7:0] + attribute \src "libresoc.v:90888.5-90888.29" + switch \initial + attribute \src "libresoc.v:90888.9-90888.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01111001 + case + assign $1\dec31_dec_sub19_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub19_asmcode $0\dec31_dec_sub19_asmcode[7:0] + end + attribute \src "libresoc.v:90906.3-90924.6" + process $proc$libresoc.v:90906$3878 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_inv_a[0:0] $1\dec31_dec_sub19_inv_a[0:0] + attribute \src "libresoc.v:90907.5-90907.29" + switch \initial + attribute \src "libresoc.v:90907.9-90907.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_inv_a $0\dec31_dec_sub19_inv_a[0:0] + end + attribute \src "libresoc.v:90925.3-90943.6" + process $proc$libresoc.v:90925$3879 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_inv_out[0:0] $1\dec31_dec_sub19_inv_out[0:0] + attribute \src "libresoc.v:90926.5-90926.29" + switch \initial + attribute \src "libresoc.v:90926.9-90926.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_inv_out $0\dec31_dec_sub19_inv_out[0:0] + end + attribute \src "libresoc.v:90944.3-90962.6" + process $proc$libresoc.v:90944$3880 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cry_out[0:0] $1\dec31_dec_sub19_cry_out[0:0] + attribute \src "libresoc.v:90945.5-90945.29" + switch \initial + attribute \src "libresoc.v:90945.9-90945.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_cry_out $0\dec31_dec_sub19_cry_out[0:0] + end + attribute \src "libresoc.v:90963.3-90981.6" + process $proc$libresoc.v:90963$3881 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_br[0:0] $1\dec31_dec_sub19_br[0:0] + attribute \src "libresoc.v:90964.5-90964.29" + switch \initial + attribute \src "libresoc.v:90964.9-90964.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_br[0:0] 1'0 + case + assign $1\dec31_dec_sub19_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_br $0\dec31_dec_sub19_br[0:0] + end + attribute \src "libresoc.v:90982.3-91000.6" + process $proc$libresoc.v:90982$3882 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sgn_ext[0:0] $1\dec31_dec_sub19_sgn_ext[0:0] + attribute \src "libresoc.v:90983.5-90983.29" + switch \initial + attribute \src "libresoc.v:90983.9-90983.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_sgn_ext $0\dec31_dec_sub19_sgn_ext[0:0] + end + attribute \src "libresoc.v:91001.3-91019.6" + process $proc$libresoc.v:91001$3883 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_internal_op[6:0] $1\dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:91002.5-91002.29" + switch \initial + attribute \src "libresoc.v:91002.9-91002.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_internal_op[6:0] 7'1000111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0110001 + case + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub19_internal_op $0\dec31_dec_sub19_internal_op[6:0] + end + attribute \src "libresoc.v:91020.3-91038.6" + process $proc$libresoc.v:91020$3884 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_rsrv[0:0] $1\dec31_dec_sub19_rsrv[0:0] + attribute \src "libresoc.v:91021.5-91021.29" + switch \initial + attribute \src "libresoc.v:91021.9-91021.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_rsrv $0\dec31_dec_sub19_rsrv[0:0] + end + attribute \src "libresoc.v:91039.3-91057.6" + process $proc$libresoc.v:91039$3885 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_is_32b[0:0] $1\dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:91040.5-91040.29" + switch \initial + attribute \src "libresoc.v:91040.9-91040.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_is_32b $0\dec31_dec_sub19_is_32b[0:0] + end + attribute \src "libresoc.v:91058.3-91076.6" + process $proc$libresoc.v:91058$3886 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sgn[0:0] $1\dec31_dec_sub19_sgn[0:0] + attribute \src "libresoc.v:91059.5-91059.29" + switch \initial + attribute \src "libresoc.v:91059.9-91059.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_sgn $0\dec31_dec_sub19_sgn[0:0] + end + attribute \src "libresoc.v:91077.3-91095.6" + process $proc$libresoc.v:91077$3887 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_lk[0:0] $1\dec31_dec_sub19_lk[0:0] + attribute \src "libresoc.v:91078.5-91078.29" + switch \initial + attribute \src "libresoc.v:91078.9-91078.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_lk $0\dec31_dec_sub19_lk[0:0] + end + attribute \src "libresoc.v:91096.3-91114.6" + process $proc$libresoc.v:91096$3888 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sgl_pipe[0:0] $1\dec31_dec_sub19_sgl_pipe[0:0] + attribute \src "libresoc.v:91097.5-91097.29" + switch \initial + attribute \src "libresoc.v:91097.9-91097.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_sgl_pipe $0\dec31_dec_sub19_sgl_pipe[0:0] + end + attribute \src "libresoc.v:91115.3-91133.6" + process $proc$libresoc.v:91115$3889 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_form[4:0] $1\dec31_dec_sub19_form[4:0] + attribute \src "libresoc.v:91116.5-91116.29" + switch \initial + attribute \src "libresoc.v:91116.9-91116.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_form[4:0] 5'01010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_form[4:0] 5'01010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_form[4:0] 5'01010 + case + assign $1\dec31_dec_sub19_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub19_form $0\dec31_dec_sub19_form[4:0] + end + attribute \src "libresoc.v:91134.3-91152.6" + process $proc$libresoc.v:91134$3890 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_in1_sel[2:0] $1\dec31_dec_sub19_in1_sel[2:0] + attribute \src "libresoc.v:91135.5-91135.29" + switch \initial + attribute \src "libresoc.v:91135.9-91135.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'100 + case + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_in1_sel $0\dec31_dec_sub19_in1_sel[2:0] + end + attribute \src "libresoc.v:91153.3-91171.6" + process $proc$libresoc.v:91153$3891 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_in2_sel[3:0] $1\dec31_dec_sub19_in2_sel[3:0] + attribute \src "libresoc.v:91154.5-91154.29" + switch \initial + attribute \src "libresoc.v:91154.9-91154.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub19_in2_sel $0\dec31_dec_sub19_in2_sel[3:0] + end + attribute \src "libresoc.v:91172.3-91190.6" + process $proc$libresoc.v:91172$3892 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_in3_sel[1:0] $1\dec31_dec_sub19_in3_sel[1:0] + attribute \src "libresoc.v:91173.5-91173.29" + switch \initial + attribute \src "libresoc.v:91173.9-91173.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_in3_sel $0\dec31_dec_sub19_in3_sel[1:0] + end + attribute \src "libresoc.v:91191.3-91209.6" + process $proc$libresoc.v:91191$3893 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_out_sel[1:0] $1\dec31_dec_sub19_out_sel[1:0] + attribute \src "libresoc.v:91192.5-91192.29" + switch \initial + attribute \src "libresoc.v:91192.9-91192.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_out_sel[1:0] 2'11 + case + assign $1\dec31_dec_sub19_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_out_sel $0\dec31_dec_sub19_out_sel[1:0] + end + attribute \src "libresoc.v:91210.3-91228.6" + process $proc$libresoc.v:91210$3894 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cr_in[2:0] $1\dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:91211.5-91211.29" + switch \initial + attribute \src "libresoc.v:91211.9-91211.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_cr_in $0\dec31_dec_sub19_cr_in[2:0] + end + attribute \src "libresoc.v:91229.3-91247.6" + process $proc$libresoc.v:91229$3895 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cr_out[2:0] $1\dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:91230.5-91230.29" + switch \initial + attribute \src "libresoc.v:91230.9-91230.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_cr_out $0\dec31_dec_sub19_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:91253.1-92112.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub20" +attribute \generator "nMigen" +module \dec31_dec_sub20 + attribute \src "libresoc.v:91636.3-91660.6" + wire width 8 $0\dec31_dec_sub20_asmcode[7:0] + attribute \src "libresoc.v:91736.3-91760.6" + wire $0\dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:92061.3-92085.6" + wire width 3 $0\dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:92086.3-92110.6" + wire width 3 $0\dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:91611.3-91635.6" + wire width 2 $0\dec31_dec_sub20_cry_in[1:0] + attribute \src "libresoc.v:91711.3-91735.6" + wire $0\dec31_dec_sub20_cry_out[0:0] + attribute \src "libresoc.v:91936.3-91960.6" + wire width 5 $0\dec31_dec_sub20_form[4:0] + attribute \src "libresoc.v:91511.3-91535.6" + wire width 12 $0\dec31_dec_sub20_function_unit[11:0] + attribute \src "libresoc.v:91961.3-91985.6" + wire width 3 $0\dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:91986.3-92010.6" + wire width 4 $0\dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:92011.3-92035.6" + wire width 2 $0\dec31_dec_sub20_in3_sel[1:0] + attribute \src "libresoc.v:91786.3-91810.6" + wire width 7 $0\dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:91661.3-91685.6" + wire $0\dec31_dec_sub20_inv_a[0:0] + attribute \src "libresoc.v:91686.3-91710.6" + wire $0\dec31_dec_sub20_inv_out[0:0] + attribute \src "libresoc.v:91836.3-91860.6" + wire $0\dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:91536.3-91560.6" + wire width 4 $0\dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:91886.3-91910.6" + wire $0\dec31_dec_sub20_lk[0:0] + attribute \src "libresoc.v:92036.3-92060.6" + wire width 2 $0\dec31_dec_sub20_out_sel[1:0] + attribute \src "libresoc.v:91586.3-91610.6" + wire width 2 $0\dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:91811.3-91835.6" + wire $0\dec31_dec_sub20_rsrv[0:0] + attribute \src "libresoc.v:91911.3-91935.6" + wire $0\dec31_dec_sub20_sgl_pipe[0:0] + attribute \src "libresoc.v:91861.3-91885.6" + wire $0\dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:91761.3-91785.6" + wire $0\dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:91561.3-91585.6" + wire width 2 $0\dec31_dec_sub20_upd[1:0] + attribute \src "libresoc.v:91254.7-91254.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:91636.3-91660.6" + wire width 8 $1\dec31_dec_sub20_asmcode[7:0] + attribute \src "libresoc.v:91736.3-91760.6" + wire $1\dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:92061.3-92085.6" + wire width 3 $1\dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:92086.3-92110.6" + wire width 3 $1\dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:91611.3-91635.6" + wire width 2 $1\dec31_dec_sub20_cry_in[1:0] + attribute \src "libresoc.v:91711.3-91735.6" + wire $1\dec31_dec_sub20_cry_out[0:0] + attribute \src "libresoc.v:91936.3-91960.6" + wire width 5 $1\dec31_dec_sub20_form[4:0] + attribute \src "libresoc.v:91511.3-91535.6" + wire width 12 $1\dec31_dec_sub20_function_unit[11:0] + attribute \src "libresoc.v:91961.3-91985.6" + wire width 3 $1\dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:91986.3-92010.6" + wire width 4 $1\dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:92011.3-92035.6" + wire width 2 $1\dec31_dec_sub20_in3_sel[1:0] + attribute \src "libresoc.v:91786.3-91810.6" + wire width 7 $1\dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:91661.3-91685.6" + wire $1\dec31_dec_sub20_inv_a[0:0] + attribute \src "libresoc.v:91686.3-91710.6" + wire $1\dec31_dec_sub20_inv_out[0:0] + attribute \src "libresoc.v:91836.3-91860.6" + wire $1\dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:91536.3-91560.6" + wire width 4 $1\dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:91886.3-91910.6" + wire $1\dec31_dec_sub20_lk[0:0] + attribute \src "libresoc.v:92036.3-92060.6" + wire width 2 $1\dec31_dec_sub20_out_sel[1:0] + attribute \src "libresoc.v:91586.3-91610.6" + wire width 2 $1\dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:91811.3-91835.6" + wire $1\dec31_dec_sub20_rsrv[0:0] + attribute \src "libresoc.v:91911.3-91935.6" + wire $1\dec31_dec_sub20_sgl_pipe[0:0] + attribute \src "libresoc.v:91861.3-91885.6" + wire $1\dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:91761.3-91785.6" + wire $1\dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:91561.3-91585.6" + wire width 2 $1\dec31_dec_sub20_upd[1:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 \dec31_dec31_asmcode + wire width 8 output 4 \dec31_dec_sub20_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec31_br + wire output 18 \dec31_dec_sub20_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -4631,7 +144079,7 @@ module \dec attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec31_cr_in + wire width 3 output 9 \dec31_dec_sub20_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -4639,15 +144087,15 @@ module \dec attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec31_cr_out + wire width 3 output 10 \dec31_dec_sub20_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec31_cry_in + wire width 2 output 14 \dec31_dec_sub20_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec31_cry_out + wire output 17 \dec31_dec_sub20_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -4679,7 +144127,7 @@ module \dec attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 \dec31_dec31_form + wire width 5 output 3 \dec31_dec_sub20_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -4694,7 +144142,7 @@ module \dec attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec31_function_unit + wire width 12 output 1 \dec31_dec_sub20_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -4702,7 +144150,7 @@ module \dec attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec31_in1_sel + wire width 3 output 5 \dec31_dec_sub20_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -4719,13 +144167,13 @@ module \dec attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec31_in2_sel + wire width 4 output 6 \dec31_dec_sub20_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec31_in3_sel + wire width 2 output 7 \dec31_dec_sub20_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -4801,13 +144249,13 @@ module \dec attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec31_dec31_internal_op + wire width 7 output 2 \dec31_dec_sub20_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec31_inv_a + wire output 15 \dec31_dec_sub20_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec31_inv_out + wire output 16 \dec31_dec_sub20_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec31_is_32b + wire output 21 \dec31_dec_sub20_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" @@ -4815,43 +144263,1192 @@ module \dec attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec31_ldst_len + wire width 4 output 11 \dec31_dec_sub20_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec31_lk + wire output 23 \dec31_dec_sub20_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec31_out_sel + wire width 2 output 8 \dec31_dec_sub20_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec31_rc_sel + wire width 2 output 13 \dec31_dec_sub20_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec31_rsrv + wire output 20 \dec31_dec_sub20_rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec31_sgl_pipe + wire output 24 \dec31_dec_sub20_sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec31_sgn + wire output 22 \dec31_dec_sub20_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec31_sgn_ext + wire output 19 \dec31_dec_sub20_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec31_upd + wire width 2 output 12 \dec31_dec_sub20_upd + attribute \src "libresoc.v:91254.7-91254.15" + wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec31_opcode_in + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:91254.7-91254.20" + process $proc$libresoc.v:91254$3921 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:91511.3-91535.6" + process $proc$libresoc.v:91511$3897 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_function_unit[11:0] $1\dec31_dec_sub20_function_unit[11:0] + attribute \src "libresoc.v:91512.5-91512.29" + switch \initial + attribute \src "libresoc.v:91512.9-91512.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + case + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub20_function_unit $0\dec31_dec_sub20_function_unit[11:0] + end + attribute \src "libresoc.v:91536.3-91560.6" + process $proc$libresoc.v:91536$3898 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_ldst_len[3:0] $1\dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:91537.5-91537.29" + switch \initial + attribute \src "libresoc.v:91537.9-91537.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 + case + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub20_ldst_len $0\dec31_dec_sub20_ldst_len[3:0] + end + attribute \src "libresoc.v:91561.3-91585.6" + process $proc$libresoc.v:91561$3899 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_upd[1:0] $1\dec31_dec_sub20_upd[1:0] + attribute \src "libresoc.v:91562.5-91562.29" + switch \initial + attribute \src "libresoc.v:91562.9-91562.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_upd $0\dec31_dec_sub20_upd[1:0] + end + attribute \src "libresoc.v:91586.3-91610.6" + process $proc$libresoc.v:91586$3900 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_rc_sel[1:0] $1\dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:91587.5-91587.29" + switch \initial + attribute \src "libresoc.v:91587.9-91587.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_rc_sel $0\dec31_dec_sub20_rc_sel[1:0] + end + attribute \src "libresoc.v:91611.3-91635.6" + process $proc$libresoc.v:91611$3901 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cry_in[1:0] $1\dec31_dec_sub20_cry_in[1:0] + attribute \src "libresoc.v:91612.5-91612.29" + switch \initial + attribute \src "libresoc.v:91612.9-91612.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_cry_in $0\dec31_dec_sub20_cry_in[1:0] + end + attribute \src "libresoc.v:91636.3-91660.6" + process $proc$libresoc.v:91636$3902 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_asmcode[7:0] $1\dec31_dec_sub20_asmcode[7:0] + attribute \src "libresoc.v:91637.5-91637.29" + switch \initial + attribute \src "libresoc.v:91637.9-91637.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01001101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01010011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01010100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01011001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'10101101 + case + assign $1\dec31_dec_sub20_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub20_asmcode $0\dec31_dec_sub20_asmcode[7:0] + end + attribute \src "libresoc.v:91661.3-91685.6" + process $proc$libresoc.v:91661$3903 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_inv_a[0:0] $1\dec31_dec_sub20_inv_a[0:0] + attribute \src "libresoc.v:91662.5-91662.29" + switch \initial + attribute \src "libresoc.v:91662.9-91662.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_inv_a $0\dec31_dec_sub20_inv_a[0:0] + end + attribute \src "libresoc.v:91686.3-91710.6" + process $proc$libresoc.v:91686$3904 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_inv_out[0:0] $1\dec31_dec_sub20_inv_out[0:0] + attribute \src "libresoc.v:91687.5-91687.29" + switch \initial + attribute \src "libresoc.v:91687.9-91687.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_inv_out $0\dec31_dec_sub20_inv_out[0:0] + end + attribute \src "libresoc.v:91711.3-91735.6" + process $proc$libresoc.v:91711$3905 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cry_out[0:0] $1\dec31_dec_sub20_cry_out[0:0] + attribute \src "libresoc.v:91712.5-91712.29" + switch \initial + attribute \src "libresoc.v:91712.9-91712.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_cry_out $0\dec31_dec_sub20_cry_out[0:0] + end + attribute \src "libresoc.v:91736.3-91760.6" + process $proc$libresoc.v:91736$3906 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_br[0:0] $1\dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:91737.5-91737.29" + switch \initial + attribute \src "libresoc.v:91737.9-91737.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'1 + case + assign $1\dec31_dec_sub20_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_br $0\dec31_dec_sub20_br[0:0] + end + attribute \src "libresoc.v:91761.3-91785.6" + process $proc$libresoc.v:91761$3907 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sgn_ext[0:0] $1\dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:91762.5-91762.29" + switch \initial + attribute \src "libresoc.v:91762.9-91762.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_sgn_ext $0\dec31_dec_sub20_sgn_ext[0:0] + end + attribute \src "libresoc.v:91786.3-91810.6" + process $proc$libresoc.v:91786$3908 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_internal_op[6:0] $1\dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:91787.5-91787.29" + switch \initial + attribute \src "libresoc.v:91787.9-91787.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100110 + case + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub20_internal_op $0\dec31_dec_sub20_internal_op[6:0] + end + attribute \src "libresoc.v:91811.3-91835.6" + process $proc$libresoc.v:91811$3909 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_rsrv[0:0] $1\dec31_dec_sub20_rsrv[0:0] + attribute \src "libresoc.v:91812.5-91812.29" + switch \initial + attribute \src "libresoc.v:91812.9-91812.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_rsrv $0\dec31_dec_sub20_rsrv[0:0] + end + attribute \src "libresoc.v:91836.3-91860.6" + process $proc$libresoc.v:91836$3910 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_is_32b[0:0] $1\dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:91837.5-91837.29" + switch \initial + attribute \src "libresoc.v:91837.9-91837.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_is_32b $0\dec31_dec_sub20_is_32b[0:0] + end + attribute \src "libresoc.v:91861.3-91885.6" + process $proc$libresoc.v:91861$3911 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sgn[0:0] $1\dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:91862.5-91862.29" + switch \initial + attribute \src "libresoc.v:91862.9-91862.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_sgn $0\dec31_dec_sub20_sgn[0:0] + end + attribute \src "libresoc.v:91886.3-91910.6" + process $proc$libresoc.v:91886$3912 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_lk[0:0] $1\dec31_dec_sub20_lk[0:0] + attribute \src "libresoc.v:91887.5-91887.29" + switch \initial + attribute \src "libresoc.v:91887.9-91887.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_lk $0\dec31_dec_sub20_lk[0:0] + end + attribute \src "libresoc.v:91911.3-91935.6" + process $proc$libresoc.v:91911$3913 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sgl_pipe[0:0] $1\dec31_dec_sub20_sgl_pipe[0:0] + attribute \src "libresoc.v:91912.5-91912.29" + switch \initial + attribute \src "libresoc.v:91912.9-91912.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_sgl_pipe $0\dec31_dec_sub20_sgl_pipe[0:0] + end + attribute \src "libresoc.v:91936.3-91960.6" + process $proc$libresoc.v:91936$3914 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_form[4:0] $1\dec31_dec_sub20_form[4:0] + attribute \src "libresoc.v:91937.5-91937.29" + switch \initial + attribute \src "libresoc.v:91937.9-91937.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub20_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub20_form $0\dec31_dec_sub20_form[4:0] + end + attribute \src "libresoc.v:91961.3-91985.6" + process $proc$libresoc.v:91961$3915 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_in1_sel[2:0] $1\dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:91962.5-91962.29" + switch \initial + attribute \src "libresoc.v:91962.9-91962.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_in1_sel $0\dec31_dec_sub20_in1_sel[2:0] + end + attribute \src "libresoc.v:91986.3-92010.6" + process $proc$libresoc.v:91986$3916 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_in2_sel[3:0] $1\dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:91987.5-91987.29" + switch \initial + attribute \src "libresoc.v:91987.9-91987.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub20_in2_sel $0\dec31_dec_sub20_in2_sel[3:0] + end + attribute \src "libresoc.v:92011.3-92035.6" + process $proc$libresoc.v:92011$3917 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_in3_sel[1:0] $1\dec31_dec_sub20_in3_sel[1:0] + attribute \src "libresoc.v:92012.5-92012.29" + switch \initial + attribute \src "libresoc.v:92012.9-92012.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_in3_sel $0\dec31_dec_sub20_in3_sel[1:0] + end + attribute \src "libresoc.v:92036.3-92060.6" + process $proc$libresoc.v:92036$3918 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_out_sel[1:0] $1\dec31_dec_sub20_out_sel[1:0] + attribute \src "libresoc.v:92037.5-92037.29" + switch \initial + attribute \src "libresoc.v:92037.9-92037.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub20_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_out_sel $0\dec31_dec_sub20_out_sel[1:0] + end + attribute \src "libresoc.v:92061.3-92085.6" + process $proc$libresoc.v:92061$3919 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cr_in[2:0] $1\dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:92062.5-92062.29" + switch \initial + attribute \src "libresoc.v:92062.9-92062.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_cr_in $0\dec31_dec_sub20_cr_in[2:0] + end + attribute \src "libresoc.v:92086.3-92110.6" + process $proc$libresoc.v:92086$3920 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cr_out[2:0] $1\dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:92087.5-92087.29" + switch \initial + attribute \src "libresoc.v:92087.9-92087.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_cr_out $0\dec31_dec_sub20_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:92116.1-93533.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub21" +attribute \generator "nMigen" +module \dec31_dec_sub21 + attribute \src "libresoc.v:93158.3-93188.6" + wire width 8 $0\dec31_dec_sub21_asmcode[7:0] + attribute \src "libresoc.v:92766.3-92814.6" + wire $0\dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:93434.3-93482.6" + wire width 3 $0\dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:93483.3-93531.6" + wire width 3 $0\dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:92570.3-92618.6" + wire width 2 $0\dec31_dec_sub21_cry_in[1:0] + attribute \src "libresoc.v:92717.3-92765.6" + wire $0\dec31_dec_sub21_cry_out[0:0] + attribute \src "libresoc.v:93189.3-93237.6" + wire width 5 $0\dec31_dec_sub21_form[4:0] + attribute \src "libresoc.v:92374.3-92422.6" + wire width 12 $0\dec31_dec_sub21_function_unit[11:0] + attribute \src "libresoc.v:93238.3-93286.6" + wire width 3 $0\dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:93287.3-93335.6" + wire width 4 $0\dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:93336.3-93384.6" + wire width 2 $0\dec31_dec_sub21_in3_sel[1:0] + attribute \src "libresoc.v:92913.3-92961.6" + wire width 7 $0\dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:92619.3-92667.6" + wire $0\dec31_dec_sub21_inv_a[0:0] + attribute \src "libresoc.v:92668.3-92716.6" + wire $0\dec31_dec_sub21_inv_out[0:0] + attribute \src "libresoc.v:92962.3-93010.6" + wire $0\dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:92423.3-92471.6" + wire width 4 $0\dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:93060.3-93108.6" + wire $0\dec31_dec_sub21_lk[0:0] + attribute \src "libresoc.v:93385.3-93433.6" + wire width 2 $0\dec31_dec_sub21_out_sel[1:0] + attribute \src "libresoc.v:92521.3-92569.6" + wire width 2 $0\dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:92864.3-92912.6" + wire $0\dec31_dec_sub21_rsrv[0:0] + attribute \src "libresoc.v:93109.3-93157.6" + wire $0\dec31_dec_sub21_sgl_pipe[0:0] + attribute \src "libresoc.v:93011.3-93059.6" + wire $0\dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:92815.3-92863.6" + wire $0\dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:92472.3-92520.6" + wire width 2 $0\dec31_dec_sub21_upd[1:0] + attribute \src "libresoc.v:92117.7-92117.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:93158.3-93188.6" + wire width 8 $1\dec31_dec_sub21_asmcode[7:0] + attribute \src "libresoc.v:92766.3-92814.6" + wire $1\dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:93434.3-93482.6" + wire width 3 $1\dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:93483.3-93531.6" + wire width 3 $1\dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:92570.3-92618.6" + wire width 2 $1\dec31_dec_sub21_cry_in[1:0] + attribute \src "libresoc.v:92717.3-92765.6" + wire $1\dec31_dec_sub21_cry_out[0:0] + attribute \src "libresoc.v:93189.3-93237.6" + wire width 5 $1\dec31_dec_sub21_form[4:0] + attribute \src "libresoc.v:92374.3-92422.6" + wire width 12 $1\dec31_dec_sub21_function_unit[11:0] + attribute \src "libresoc.v:93238.3-93286.6" + wire width 3 $1\dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:93287.3-93335.6" + wire width 4 $1\dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:93336.3-93384.6" + wire width 2 $1\dec31_dec_sub21_in3_sel[1:0] + attribute \src "libresoc.v:92913.3-92961.6" + wire width 7 $1\dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:92619.3-92667.6" + wire $1\dec31_dec_sub21_inv_a[0:0] + attribute \src "libresoc.v:92668.3-92716.6" + wire $1\dec31_dec_sub21_inv_out[0:0] + attribute \src "libresoc.v:92962.3-93010.6" + wire $1\dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:92423.3-92471.6" + wire width 4 $1\dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:93060.3-93108.6" + wire $1\dec31_dec_sub21_lk[0:0] + attribute \src "libresoc.v:93385.3-93433.6" + wire width 2 $1\dec31_dec_sub21_out_sel[1:0] + attribute \src "libresoc.v:92521.3-92569.6" + wire width 2 $1\dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:92864.3-92912.6" + wire $1\dec31_dec_sub21_rsrv[0:0] + attribute \src "libresoc.v:93109.3-93157.6" + wire $1\dec31_dec_sub21_sgl_pipe[0:0] + attribute \src "libresoc.v:93011.3-93059.6" + wire $1\dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:92815.3-92863.6" + wire $1\dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:92472.3-92520.6" + wire width 2 $1\dec31_dec_sub21_upd[1:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 \dec58_dec58_asmcode + wire width 8 output 4 \dec31_dec_sub21_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec58_dec58_br + wire output 18 \dec31_dec_sub21_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -4861,7 +145458,7 @@ module \dec attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec58_dec58_cr_in + wire width 3 output 9 \dec31_dec_sub21_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -4869,15 +145466,15 @@ module \dec attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec58_dec58_cr_out + wire width 3 output 10 \dec31_dec_sub21_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec58_dec58_cry_in + wire width 2 output 14 \dec31_dec_sub21_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec58_dec58_cry_out + wire output 17 \dec31_dec_sub21_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -4909,7 +145506,7 @@ module \dec attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 \dec58_dec58_form + wire width 5 output 3 \dec31_dec_sub21_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -4924,7 +145521,7 @@ module \dec attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec58_dec58_function_unit + wire width 12 output 1 \dec31_dec_sub21_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -4932,7 +145529,7 @@ module \dec attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec58_dec58_in1_sel + wire width 3 output 5 \dec31_dec_sub21_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -4949,13 +145546,13 @@ module \dec attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec58_dec58_in2_sel + wire width 4 output 6 \dec31_dec_sub21_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec58_dec58_in3_sel + wire width 2 output 7 \dec31_dec_sub21_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -5031,13 +145628,13 @@ module \dec attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec58_dec58_internal_op + wire width 7 output 2 \dec31_dec_sub21_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec58_dec58_inv_a + wire output 15 \dec31_dec_sub21_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec58_dec58_inv_out + wire output 16 \dec31_dec_sub21_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec58_dec58_is_32b + wire output 21 \dec31_dec_sub21_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" @@ -5045,43 +145642,1936 @@ module \dec attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec58_dec58_ldst_len + wire width 4 output 11 \dec31_dec_sub21_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec58_dec58_lk + wire output 23 \dec31_dec_sub21_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec58_dec58_out_sel + wire width 2 output 8 \dec31_dec_sub21_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec58_dec58_rc_sel + wire width 2 output 13 \dec31_dec_sub21_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec58_dec58_rsrv + wire output 20 \dec31_dec_sub21_rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec58_dec58_sgl_pipe + wire output 24 \dec31_dec_sub21_sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec58_dec58_sgn + wire output 22 \dec31_dec_sub21_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec58_dec58_sgn_ext + wire output 19 \dec31_dec_sub21_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec58_dec58_upd + wire width 2 output 12 \dec31_dec_sub21_upd + attribute \src "libresoc.v:92117.7-92117.15" + wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec58_opcode_in + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:92117.7-92117.20" + process $proc$libresoc.v:92117$3946 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:92374.3-92422.6" + process $proc$libresoc.v:92374$3922 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_function_unit[11:0] $1\dec31_dec_sub21_function_unit[11:0] + attribute \src "libresoc.v:92375.5-92375.29" + switch \initial + attribute \src "libresoc.v:92375.9-92375.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + case + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub21_function_unit $0\dec31_dec_sub21_function_unit[11:0] + end + attribute \src "libresoc.v:92423.3-92471.6" + process $proc$libresoc.v:92423$3923 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_ldst_len[3:0] $1\dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:92424.5-92424.29" + switch \initial + attribute \src "libresoc.v:92424.9-92424.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + case + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub21_ldst_len $0\dec31_dec_sub21_ldst_len[3:0] + end + attribute \src "libresoc.v:92472.3-92520.6" + process $proc$libresoc.v:92472$3924 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_upd[1:0] $1\dec31_dec_sub21_upd[1:0] + attribute \src "libresoc.v:92473.5-92473.29" + switch \initial + attribute \src "libresoc.v:92473.9-92473.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + case + assign $1\dec31_dec_sub21_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_upd $0\dec31_dec_sub21_upd[1:0] + end + attribute \src "libresoc.v:92521.3-92569.6" + process $proc$libresoc.v:92521$3925 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_rc_sel[1:0] $1\dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:92522.5-92522.29" + switch \initial + attribute \src "libresoc.v:92522.9-92522.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_rc_sel $0\dec31_dec_sub21_rc_sel[1:0] + end + attribute \src "libresoc.v:92570.3-92618.6" + process $proc$libresoc.v:92570$3926 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_cry_in[1:0] $1\dec31_dec_sub21_cry_in[1:0] + attribute \src "libresoc.v:92571.5-92571.29" + switch \initial + attribute \src "libresoc.v:92571.9-92571.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_cry_in $0\dec31_dec_sub21_cry_in[1:0] + end + attribute \src "libresoc.v:92619.3-92667.6" + process $proc$libresoc.v:92619$3927 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_inv_a[0:0] $1\dec31_dec_sub21_inv_a[0:0] + attribute \src "libresoc.v:92620.5-92620.29" + switch \initial + attribute \src "libresoc.v:92620.9-92620.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_inv_a $0\dec31_dec_sub21_inv_a[0:0] + end + attribute \src "libresoc.v:92668.3-92716.6" + process $proc$libresoc.v:92668$3928 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_inv_out[0:0] $1\dec31_dec_sub21_inv_out[0:0] + attribute \src "libresoc.v:92669.5-92669.29" + switch \initial + attribute \src "libresoc.v:92669.9-92669.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_inv_out $0\dec31_dec_sub21_inv_out[0:0] + end + attribute \src "libresoc.v:92717.3-92765.6" + process $proc$libresoc.v:92717$3929 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_cry_out[0:0] $1\dec31_dec_sub21_cry_out[0:0] + attribute \src "libresoc.v:92718.5-92718.29" + switch \initial + attribute \src "libresoc.v:92718.9-92718.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_cry_out $0\dec31_dec_sub21_cry_out[0:0] + end + attribute \src "libresoc.v:92766.3-92814.6" + process $proc$libresoc.v:92766$3930 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_br[0:0] $1\dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:92767.5-92767.29" + switch \initial + attribute \src "libresoc.v:92767.9-92767.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + case + assign $1\dec31_dec_sub21_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_br $0\dec31_dec_sub21_br[0:0] + end + attribute \src "libresoc.v:92815.3-92863.6" + process $proc$libresoc.v:92815$3931 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sgn_ext[0:0] $1\dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:92816.5-92816.29" + switch \initial + attribute \src "libresoc.v:92816.9-92816.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_sgn_ext $0\dec31_dec_sub21_sgn_ext[0:0] + end + attribute \src "libresoc.v:92864.3-92912.6" + process $proc$libresoc.v:92864$3932 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_rsrv[0:0] $1\dec31_dec_sub21_rsrv[0:0] + attribute \src "libresoc.v:92865.5-92865.29" + switch \initial + attribute \src "libresoc.v:92865.9-92865.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_rsrv $0\dec31_dec_sub21_rsrv[0:0] + end + attribute \src "libresoc.v:92913.3-92961.6" + process $proc$libresoc.v:92913$3933 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_internal_op[6:0] $1\dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:92914.5-92914.29" + switch \initial + attribute \src "libresoc.v:92914.9-92914.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + case + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub21_internal_op $0\dec31_dec_sub21_internal_op[6:0] + end + attribute \src "libresoc.v:92962.3-93010.6" + process $proc$libresoc.v:92962$3934 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_is_32b[0:0] $1\dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:92963.5-92963.29" + switch \initial + attribute \src "libresoc.v:92963.9-92963.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_is_32b $0\dec31_dec_sub21_is_32b[0:0] + end + attribute \src "libresoc.v:93011.3-93059.6" + process $proc$libresoc.v:93011$3935 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sgn[0:0] $1\dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:93012.5-93012.29" + switch \initial + attribute \src "libresoc.v:93012.9-93012.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_sgn $0\dec31_dec_sub21_sgn[0:0] + end + attribute \src "libresoc.v:93060.3-93108.6" + process $proc$libresoc.v:93060$3936 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_lk[0:0] $1\dec31_dec_sub21_lk[0:0] + attribute \src "libresoc.v:93061.5-93061.29" + switch \initial + attribute \src "libresoc.v:93061.9-93061.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_lk $0\dec31_dec_sub21_lk[0:0] + end + attribute \src "libresoc.v:93109.3-93157.6" + process $proc$libresoc.v:93109$3937 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sgl_pipe[0:0] $1\dec31_dec_sub21_sgl_pipe[0:0] + attribute \src "libresoc.v:93110.5-93110.29" + switch \initial + attribute \src "libresoc.v:93110.9-93110.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_sgl_pipe $0\dec31_dec_sub21_sgl_pipe[0:0] + end + attribute \src "libresoc.v:93158.3-93188.6" + process $proc$libresoc.v:93158$3938 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_asmcode[7:0] $1\dec31_dec_sub21_asmcode[7:0] + attribute \src "libresoc.v:93159.5-93159.29" + switch \initial + attribute \src "libresoc.v:93159.9-93159.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01100100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01101000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'10100111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'10110000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'10110001 + case + assign $1\dec31_dec_sub21_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub21_asmcode $0\dec31_dec_sub21_asmcode[7:0] + end + attribute \src "libresoc.v:93189.3-93237.6" + process $proc$libresoc.v:93189$3939 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_form[4:0] $1\dec31_dec_sub21_form[4:0] + attribute \src "libresoc.v:93190.5-93190.29" + switch \initial + attribute \src "libresoc.v:93190.9-93190.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub21_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub21_form $0\dec31_dec_sub21_form[4:0] + end + attribute \src "libresoc.v:93238.3-93286.6" + process $proc$libresoc.v:93238$3940 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_in1_sel[2:0] $1\dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:93239.5-93239.29" + switch \initial + attribute \src "libresoc.v:93239.9-93239.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_in1_sel $0\dec31_dec_sub21_in1_sel[2:0] + end + attribute \src "libresoc.v:93287.3-93335.6" + process $proc$libresoc.v:93287$3941 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_in2_sel[3:0] $1\dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:93288.5-93288.29" + switch \initial + attribute \src "libresoc.v:93288.9-93288.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub21_in2_sel $0\dec31_dec_sub21_in2_sel[3:0] + end + attribute \src "libresoc.v:93336.3-93384.6" + process $proc$libresoc.v:93336$3942 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_in3_sel[1:0] $1\dec31_dec_sub21_in3_sel[1:0] + attribute \src "libresoc.v:93337.5-93337.29" + switch \initial + attribute \src "libresoc.v:93337.9-93337.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_in3_sel $0\dec31_dec_sub21_in3_sel[1:0] + end + attribute \src "libresoc.v:93385.3-93433.6" + process $proc$libresoc.v:93385$3943 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_out_sel[1:0] $1\dec31_dec_sub21_out_sel[1:0] + attribute \src "libresoc.v:93386.5-93386.29" + switch \initial + attribute \src "libresoc.v:93386.9-93386.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_out_sel $0\dec31_dec_sub21_out_sel[1:0] + end + attribute \src "libresoc.v:93434.3-93482.6" + process $proc$libresoc.v:93434$3944 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_cr_in[2:0] $1\dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:93435.5-93435.29" + switch \initial + attribute \src "libresoc.v:93435.9-93435.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_cr_in $0\dec31_dec_sub21_cr_in[2:0] + end + attribute \src "libresoc.v:93483.3-93531.6" + process $proc$libresoc.v:93483$3945 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_cr_out[2:0] $1\dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:93484.5-93484.29" + switch \initial + attribute \src "libresoc.v:93484.9-93484.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_cr_out $0\dec31_dec_sub21_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:93537.1-95116.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub22" +attribute \generator "nMigen" +module \dec31_dec_sub22 + attribute \src "libresoc.v:94070.3-94124.6" + wire width 8 $0\dec31_dec_sub22_asmcode[7:0] + attribute \src "libresoc.v:94290.3-94344.6" + wire $0\dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:95005.3-95059.6" + wire width 3 $0\dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:95060.3-95114.6" + wire width 3 $0\dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:94015.3-94069.6" + wire width 2 $0\dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:94235.3-94289.6" + wire $0\dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:94730.3-94784.6" + wire width 5 $0\dec31_dec_sub22_form[4:0] + attribute \src "libresoc.v:93795.3-93849.6" + wire width 12 $0\dec31_dec_sub22_function_unit[11:0] + attribute \src "libresoc.v:94785.3-94839.6" + wire width 3 $0\dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:94840.3-94894.6" + wire width 4 $0\dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:94895.3-94949.6" + wire width 2 $0\dec31_dec_sub22_in3_sel[1:0] + attribute \src "libresoc.v:94400.3-94454.6" + wire width 7 $0\dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:94125.3-94179.6" + wire $0\dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:94180.3-94234.6" + wire $0\dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:94510.3-94564.6" + wire $0\dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:93850.3-93904.6" + wire width 4 $0\dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:94620.3-94674.6" + wire $0\dec31_dec_sub22_lk[0:0] + attribute \src "libresoc.v:94950.3-95004.6" + wire width 2 $0\dec31_dec_sub22_out_sel[1:0] + attribute \src "libresoc.v:93960.3-94014.6" + wire width 2 $0\dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:94455.3-94509.6" + wire $0\dec31_dec_sub22_rsrv[0:0] + attribute \src "libresoc.v:94675.3-94729.6" + wire $0\dec31_dec_sub22_sgl_pipe[0:0] + attribute \src "libresoc.v:94565.3-94619.6" + wire $0\dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:94345.3-94399.6" + wire $0\dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:93905.3-93959.6" + wire width 2 $0\dec31_dec_sub22_upd[1:0] + attribute \src "libresoc.v:93538.7-93538.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:94070.3-94124.6" + wire width 8 $1\dec31_dec_sub22_asmcode[7:0] + attribute \src "libresoc.v:94290.3-94344.6" + wire $1\dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:95005.3-95059.6" + wire width 3 $1\dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:95060.3-95114.6" + wire width 3 $1\dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:94015.3-94069.6" + wire width 2 $1\dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:94235.3-94289.6" + wire $1\dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:94730.3-94784.6" + wire width 5 $1\dec31_dec_sub22_form[4:0] + attribute \src "libresoc.v:93795.3-93849.6" + wire width 12 $1\dec31_dec_sub22_function_unit[11:0] + attribute \src "libresoc.v:94785.3-94839.6" + wire width 3 $1\dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:94840.3-94894.6" + wire width 4 $1\dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:94895.3-94949.6" + wire width 2 $1\dec31_dec_sub22_in3_sel[1:0] + attribute \src "libresoc.v:94400.3-94454.6" + wire width 7 $1\dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:94125.3-94179.6" + wire $1\dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:94180.3-94234.6" + wire $1\dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:94510.3-94564.6" + wire $1\dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:93850.3-93904.6" + wire width 4 $1\dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:94620.3-94674.6" + wire $1\dec31_dec_sub22_lk[0:0] + attribute \src "libresoc.v:94950.3-95004.6" + wire width 2 $1\dec31_dec_sub22_out_sel[1:0] + attribute \src "libresoc.v:93960.3-94014.6" + wire width 2 $1\dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:94455.3-94509.6" + wire $1\dec31_dec_sub22_rsrv[0:0] + attribute \src "libresoc.v:94675.3-94729.6" + wire $1\dec31_dec_sub22_sgl_pipe[0:0] + attribute \src "libresoc.v:94565.3-94619.6" + wire $1\dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:94345.3-94399.6" + wire $1\dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:93905.3-93959.6" + wire width 2 $1\dec31_dec_sub22_upd[1:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 \dec62_dec62_asmcode + wire width 8 output 4 \dec31_dec_sub22_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec62_dec62_br + wire output 18 \dec31_dec_sub22_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -5091,7 +147581,7 @@ module \dec attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec62_dec62_cr_in + wire width 3 output 9 \dec31_dec_sub22_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -5099,15 +147589,15 @@ module \dec attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec62_dec62_cr_out + wire width 3 output 10 \dec31_dec_sub22_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec62_dec62_cry_in + wire width 2 output 14 \dec31_dec_sub22_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec62_dec62_cry_out + wire output 17 \dec31_dec_sub22_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -5139,7 +147629,7 @@ module \dec attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 \dec62_dec62_form + wire width 5 output 3 \dec31_dec_sub22_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -5154,7 +147644,7 @@ module \dec attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec62_dec62_function_unit + wire width 12 output 1 \dec31_dec_sub22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -5162,7 +147652,7 @@ module \dec attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec62_dec62_in1_sel + wire width 3 output 5 \dec31_dec_sub22_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -5179,13 +147669,13 @@ module \dec attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec62_dec62_in2_sel + wire width 4 output 6 \dec31_dec_sub22_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec62_dec62_in3_sel + wire width 2 output 7 \dec31_dec_sub22_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -5261,13 +147751,13 @@ module \dec attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec62_dec62_internal_op + wire width 7 output 2 \dec31_dec_sub22_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec62_dec62_inv_a + wire output 15 \dec31_dec_sub22_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec62_dec62_inv_out + wire output 16 \dec31_dec_sub22_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec62_dec62_is_32b + wire output 21 \dec31_dec_sub22_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" @@ -5275,5673 +147765,8916 @@ module \dec attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec62_dec62_ldst_len + wire width 4 output 11 \dec31_dec_sub22_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec62_dec62_lk + wire output 23 \dec31_dec_sub22_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec62_dec62_out_sel + wire width 2 output 8 \dec31_dec_sub22_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec62_dec62_rc_sel + wire width 2 output 13 \dec31_dec_sub22_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec62_dec62_rsrv + wire output 20 \dec31_dec_sub22_rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec62_dec62_sgl_pipe + wire output 24 \dec31_dec_sub22_sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec62_dec62_sgn + wire output 22 \dec31_dec_sub22_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec62_dec62_sgn_ext + wire output 19 \dec31_dec_sub22_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec62_dec62_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec62_opcode_in - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 \form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 7 \function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 12 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 13 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \in3_sel - attribute \src "libresoc.v:1192.7-1192.15" + wire width 2 output 12 \dec31_dec_sub22_upd + attribute \src "libresoc.v:93538.7-93538.15" wire \initial - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 6 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 9 \is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 10 \lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 6 \opcode_switch + wire width 32 input 25 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 32 \opcode_switch$1 - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 15 \out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 input 1 \raw_opcode_in - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 3 \rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 6 \sh - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 17 \upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" - cell $mux $ternary$libresoc.v:3249$237 - parameter \WIDTH 32 - connect \A \raw_opcode_in - connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } - connect \S \bigendian - connect \Y $ternary$libresoc.v:3249$237_Y + wire width 5 \opcode_switch + attribute \src "libresoc.v:93538.7-93538.20" + process $proc$libresoc.v:93538$3971 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \module_not_derived 1 - attribute \src "libresoc.v:3250.9-3276.4" - cell \dec19 \dec19 - connect \dec19_asmcode \dec19_dec19_asmcode - connect \dec19_br \dec19_dec19_br - connect \dec19_cr_in \dec19_dec19_cr_in - connect \dec19_cr_out \dec19_dec19_cr_out - connect \dec19_cry_in \dec19_dec19_cry_in - connect \dec19_cry_out \dec19_dec19_cry_out - connect \dec19_form \dec19_dec19_form - connect \dec19_function_unit \dec19_dec19_function_unit - connect \dec19_in1_sel \dec19_dec19_in1_sel - connect \dec19_in2_sel \dec19_dec19_in2_sel - connect \dec19_in3_sel \dec19_dec19_in3_sel - connect \dec19_internal_op \dec19_dec19_internal_op - connect \dec19_inv_a \dec19_dec19_inv_a - connect \dec19_inv_out \dec19_dec19_inv_out - connect \dec19_is_32b \dec19_dec19_is_32b - connect \dec19_ldst_len \dec19_dec19_ldst_len - connect \dec19_lk \dec19_dec19_lk - connect \dec19_out_sel \dec19_dec19_out_sel - connect \dec19_rc_sel \dec19_dec19_rc_sel - connect \dec19_rsrv \dec19_dec19_rsrv - connect \dec19_sgl_pipe \dec19_dec19_sgl_pipe - connect \dec19_sgn \dec19_dec19_sgn - connect \dec19_sgn_ext \dec19_dec19_sgn_ext - connect \dec19_upd \dec19_dec19_upd - connect \opcode_in \dec19_opcode_in + attribute \src "libresoc.v:93795.3-93849.6" + process $proc$libresoc.v:93795$3947 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_function_unit[11:0] $1\dec31_dec_sub22_function_unit[11:0] + attribute \src "libresoc.v:93796.5-93796.29" + switch \initial + attribute \src "libresoc.v:93796.9-93796.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'100000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + case + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub22_function_unit $0\dec31_dec_sub22_function_unit[11:0] end - attribute \module_not_derived 1 - attribute \src "libresoc.v:3277.9-3303.4" - cell \dec30 \dec30 - connect \dec30_asmcode \dec30_dec30_asmcode - connect \dec30_br \dec30_dec30_br - connect \dec30_cr_in \dec30_dec30_cr_in - connect \dec30_cr_out \dec30_dec30_cr_out - connect \dec30_cry_in \dec30_dec30_cry_in - connect \dec30_cry_out \dec30_dec30_cry_out - connect \dec30_form \dec30_dec30_form - connect \dec30_function_unit \dec30_dec30_function_unit - connect \dec30_in1_sel \dec30_dec30_in1_sel - connect \dec30_in2_sel \dec30_dec30_in2_sel - connect \dec30_in3_sel \dec30_dec30_in3_sel - connect \dec30_internal_op \dec30_dec30_internal_op - connect \dec30_inv_a \dec30_dec30_inv_a - connect \dec30_inv_out \dec30_dec30_inv_out - connect \dec30_is_32b \dec30_dec30_is_32b - connect \dec30_ldst_len \dec30_dec30_ldst_len - connect \dec30_lk \dec30_dec30_lk - connect \dec30_out_sel \dec30_dec30_out_sel - connect \dec30_rc_sel \dec30_dec30_rc_sel - connect \dec30_rsrv \dec30_dec30_rsrv - connect \dec30_sgl_pipe \dec30_dec30_sgl_pipe - connect \dec30_sgn \dec30_dec30_sgn - connect \dec30_sgn_ext \dec30_dec30_sgn_ext - connect \dec30_upd \dec30_dec30_upd - connect \opcode_in \dec30_opcode_in + attribute \src "libresoc.v:93850.3-93904.6" + process $proc$libresoc.v:93850$3948 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_ldst_len[3:0] $1\dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:93851.5-93851.29" + switch \initial + attribute \src "libresoc.v:93851.9-93851.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub22_ldst_len $0\dec31_dec_sub22_ldst_len[3:0] end - attribute \module_not_derived 1 - attribute \src "libresoc.v:3304.9-3330.4" - cell \dec31 \dec31 - connect \dec31_asmcode \dec31_dec31_asmcode - connect \dec31_br \dec31_dec31_br - connect \dec31_cr_in \dec31_dec31_cr_in - connect \dec31_cr_out \dec31_dec31_cr_out - connect \dec31_cry_in \dec31_dec31_cry_in - connect \dec31_cry_out \dec31_dec31_cry_out - connect \dec31_form \dec31_dec31_form - connect \dec31_function_unit \dec31_dec31_function_unit - connect \dec31_in1_sel \dec31_dec31_in1_sel - connect \dec31_in2_sel \dec31_dec31_in2_sel - connect \dec31_in3_sel \dec31_dec31_in3_sel - connect \dec31_internal_op \dec31_dec31_internal_op - connect \dec31_inv_a \dec31_dec31_inv_a - connect \dec31_inv_out \dec31_dec31_inv_out - connect \dec31_is_32b \dec31_dec31_is_32b - connect \dec31_ldst_len \dec31_dec31_ldst_len - connect \dec31_lk \dec31_dec31_lk - connect \dec31_out_sel \dec31_dec31_out_sel - connect \dec31_rc_sel \dec31_dec31_rc_sel - connect \dec31_rsrv \dec31_dec31_rsrv - connect \dec31_sgl_pipe \dec31_dec31_sgl_pipe - connect \dec31_sgn \dec31_dec31_sgn - connect \dec31_sgn_ext \dec31_dec31_sgn_ext - connect \dec31_upd \dec31_dec31_upd - connect \opcode_in \dec31_opcode_in + attribute \src "libresoc.v:93905.3-93959.6" + process $proc$libresoc.v:93905$3949 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_upd[1:0] $1\dec31_dec_sub22_upd[1:0] + attribute \src "libresoc.v:93906.5-93906.29" + switch \initial + attribute \src "libresoc.v:93906.9-93906.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_upd $0\dec31_dec_sub22_upd[1:0] end - attribute \module_not_derived 1 - attribute \src "libresoc.v:3331.9-3357.4" - cell \dec58 \dec58 - connect \dec58_asmcode \dec58_dec58_asmcode - connect \dec58_br \dec58_dec58_br - connect \dec58_cr_in \dec58_dec58_cr_in - connect \dec58_cr_out \dec58_dec58_cr_out - connect \dec58_cry_in \dec58_dec58_cry_in - connect \dec58_cry_out \dec58_dec58_cry_out - connect \dec58_form \dec58_dec58_form - connect \dec58_function_unit \dec58_dec58_function_unit - connect \dec58_in1_sel \dec58_dec58_in1_sel - connect \dec58_in2_sel \dec58_dec58_in2_sel - connect \dec58_in3_sel \dec58_dec58_in3_sel - connect \dec58_internal_op \dec58_dec58_internal_op - connect \dec58_inv_a \dec58_dec58_inv_a - connect \dec58_inv_out \dec58_dec58_inv_out - connect \dec58_is_32b \dec58_dec58_is_32b - connect \dec58_ldst_len \dec58_dec58_ldst_len - connect \dec58_lk \dec58_dec58_lk - connect \dec58_out_sel \dec58_dec58_out_sel - connect \dec58_rc_sel \dec58_dec58_rc_sel - connect \dec58_rsrv \dec58_dec58_rsrv - connect \dec58_sgl_pipe \dec58_dec58_sgl_pipe - connect \dec58_sgn \dec58_dec58_sgn - connect \dec58_sgn_ext \dec58_dec58_sgn_ext - connect \dec58_upd \dec58_dec58_upd - connect \opcode_in \dec58_opcode_in + attribute \src "libresoc.v:93960.3-94014.6" + process $proc$libresoc.v:93960$3950 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_rc_sel[1:0] $1\dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:93961.5-93961.29" + switch \initial + attribute \src "libresoc.v:93961.9-93961.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_rc_sel $0\dec31_dec_sub22_rc_sel[1:0] + end + attribute \src "libresoc.v:94015.3-94069.6" + process $proc$libresoc.v:94015$3951 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_cry_in[1:0] $1\dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:94016.5-94016.29" + switch \initial + attribute \src "libresoc.v:94016.9-94016.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_cry_in $0\dec31_dec_sub22_cry_in[1:0] + end + attribute \src "libresoc.v:94070.3-94124.6" + process $proc$libresoc.v:94070$3952 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_asmcode[7:0] $1\dec31_dec_sub22_asmcode[7:0] + attribute \src "libresoc.v:94071.5-94071.29" + switch \initial + attribute \src "libresoc.v:94071.9-94071.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00101110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01001001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10101000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10101110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10111001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10111010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'11001001 + case + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub22_asmcode $0\dec31_dec_sub22_asmcode[7:0] + end + attribute \src "libresoc.v:94125.3-94179.6" + process $proc$libresoc.v:94125$3953 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_inv_a[0:0] $1\dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:94126.5-94126.29" + switch \initial + attribute \src "libresoc.v:94126.9-94126.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_inv_a $0\dec31_dec_sub22_inv_a[0:0] + end + attribute \src "libresoc.v:94180.3-94234.6" + process $proc$libresoc.v:94180$3954 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_inv_out[0:0] $1\dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:94181.5-94181.29" + switch \initial + attribute \src "libresoc.v:94181.9-94181.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_inv_out $0\dec31_dec_sub22_inv_out[0:0] end - attribute \module_not_derived 1 - attribute \src "libresoc.v:3358.9-3384.4" - cell \dec62 \dec62 - connect \dec62_asmcode \dec62_dec62_asmcode - connect \dec62_br \dec62_dec62_br - connect \dec62_cr_in \dec62_dec62_cr_in - connect \dec62_cr_out \dec62_dec62_cr_out - connect \dec62_cry_in \dec62_dec62_cry_in - connect \dec62_cry_out \dec62_dec62_cry_out - connect \dec62_form \dec62_dec62_form - connect \dec62_function_unit \dec62_dec62_function_unit - connect \dec62_in1_sel \dec62_dec62_in1_sel - connect \dec62_in2_sel \dec62_dec62_in2_sel - connect \dec62_in3_sel \dec62_dec62_in3_sel - connect \dec62_internal_op \dec62_dec62_internal_op - connect \dec62_inv_a \dec62_dec62_inv_a - connect \dec62_inv_out \dec62_dec62_inv_out - connect \dec62_is_32b \dec62_dec62_is_32b - connect \dec62_ldst_len \dec62_dec62_ldst_len - connect \dec62_lk \dec62_dec62_lk - connect \dec62_out_sel \dec62_dec62_out_sel - connect \dec62_rc_sel \dec62_dec62_rc_sel - connect \dec62_rsrv \dec62_dec62_rsrv - connect \dec62_sgl_pipe \dec62_dec62_sgl_pipe - connect \dec62_sgn \dec62_dec62_sgn - connect \dec62_sgn_ext \dec62_dec62_sgn_ext - connect \dec62_upd \dec62_dec62_upd - connect \opcode_in \dec62_opcode_in + attribute \src "libresoc.v:94235.3-94289.6" + process $proc$libresoc.v:94235$3955 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_cry_out[0:0] $1\dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:94236.5-94236.29" + switch \initial + attribute \src "libresoc.v:94236.9-94236.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_cry_out $0\dec31_dec_sub22_cry_out[0:0] end - attribute \src "libresoc.v:1192.7-1192.20" - process $proc$libresoc.v:1192$262 + attribute \src "libresoc.v:94290.3-94344.6" + process $proc$libresoc.v:94290$3956 assign { } { } - assign $0\initial[0:0] 1'0 + assign { } { } + assign $0\dec31_dec_sub22_br[0:0] $1\dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:94291.5-94291.29" + switch \initial + attribute \src "libresoc.v:94291.9-94291.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + case + assign $1\dec31_dec_sub22_br[0:0] 1'0 + end sync always - update \initial $0\initial[0:0] - sync init + update \dec31_dec_sub22_br $0\dec31_dec_sub22_br[0:0] end - attribute \src "libresoc.v:3385.3-3523.6" - process $proc$libresoc.v:3385$238 + attribute \src "libresoc.v:94345.3-94399.6" + process $proc$libresoc.v:94345$3957 assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sgn_ext[0:0] $1\dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:94346.5-94346.29" + switch \initial + attribute \src "libresoc.v:94346.9-94346.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_sgn_ext $0\dec31_dec_sub22_sgn_ext[0:0] + end + attribute \src "libresoc.v:94400.3-94454.6" + process $proc$libresoc.v:94400$3958 assign { } { } assign { } { } - assign $0\asmcode[7:0] $2\asmcode[7:0] - attribute \src "libresoc.v:3386.5-3386.29" + assign $0\dec31_dec_sub22_internal_op[6:0] $1\dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:94401.5-94401.29" switch \initial - attribute \src "libresoc.v:3386.9-3386.17" + attribute \src "libresoc.v:94401.9-94401.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010011 + case 5'00010 assign { } { } - assign $1\asmcode[7:0] \dec19_dec19_asmcode + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 attribute \src "libresoc.v:0.0-0.0" - case 6'011110 + case 5'00001 assign { } { } - assign $1\asmcode[7:0] \dec30_dec30_asmcode + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 attribute \src "libresoc.v:0.0-0.0" - case 6'011111 + case 5'01000 assign { } { } - assign $1\asmcode[7:0] \dec31_dec31_asmcode + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 attribute \src "libresoc.v:0.0-0.0" - case 6'111010 + case 5'00111 assign { } { } - assign $1\asmcode[7:0] \dec58_dec58_asmcode + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 attribute \src "libresoc.v:0.0-0.0" - case 6'111110 + case 5'11111 assign { } { } - assign $1\asmcode[7:0] \dec62_dec62_asmcode + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0011100 attribute \src "libresoc.v:0.0-0.0" - case 6'001100 + case 5'11110 assign { } { } - assign $1\asmcode[7:0] 8'00000111 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100001 attribute \src "libresoc.v:0.0-0.0" - case 6'001101 + case 5'00000 assign { } { } - assign $1\asmcode[7:0] 8'00001000 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 attribute \src "libresoc.v:0.0-0.0" - case 6'001110 + case 5'11000 assign { } { } - assign $1\asmcode[7:0] 8'00000110 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" - case 6'001111 + case 5'10000 assign { } { } - assign $1\asmcode[7:0] 8'00001001 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" - case 6'011100 + case 5'10101 assign { } { } - assign $1\asmcode[7:0] 8'00010001 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" - case 6'011101 + case 5'00110 assign { } { } - assign $1\asmcode[7:0] 8'00010010 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" - case 6'010010 + case 5'11100 assign { } { } - assign $1\asmcode[7:0] 8'00010100 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" - case 6'010000 + case 5'10110 assign { } { } - assign $1\asmcode[7:0] 8'00010101 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" - case 6'001011 + case 5'10100 assign { } { } - assign $1\asmcode[7:0] 8'00011101 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" - case 6'001010 + case 5'00100 assign { } { } - assign $1\asmcode[7:0] 8'00011111 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" - case 6'100010 + case 5'10010 assign { } { } - assign $1\asmcode[7:0] 8'01001110 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + case + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub22_internal_op $0\dec31_dec_sub22_internal_op[6:0] + end + attribute \src "libresoc.v:94455.3-94509.6" + process $proc$libresoc.v:94455$3959 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_rsrv[0:0] $1\dec31_dec_sub22_rsrv[0:0] + attribute \src "libresoc.v:94456.5-94456.29" + switch \initial + attribute \src "libresoc.v:94456.9-94456.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'100011 + case 5'00010 assign { } { } - assign $1\asmcode[7:0] 8'01001111 + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101010 + case 5'00001 assign { } { } - assign $1\asmcode[7:0] 8'01011000 + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101011 + case 5'01000 assign { } { } - assign $1\asmcode[7:0] 8'01011010 + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101000 + case 5'00111 assign { } { } - assign $1\asmcode[7:0] 8'01011110 + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101001 + case 5'11111 assign { } { } - assign $1\asmcode[7:0] 8'01011111 + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100000 + case 5'11110 assign { } { } - assign $1\asmcode[7:0] 8'01100111 + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100001 + case 5'00000 assign { } { } - assign $1\asmcode[7:0] 8'01101001 + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'000111 + case 5'11000 assign { } { } - assign $1\asmcode[7:0] 8'10000000 + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011000 + case 5'10000 assign { } { } - assign $1\asmcode[7:0] 8'10001010 + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011001 + case 5'10101 assign { } { } - assign $1\asmcode[7:0] 8'10001011 + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'010100 + case 5'00110 assign { } { } - assign $1\asmcode[7:0] 8'10011000 + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'010101 + case 5'11100 assign { } { } - assign $1\asmcode[7:0] 8'10011001 + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010111 + case 5'10110 assign { } { } - assign $1\asmcode[7:0] 8'10011010 + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'100110 + case 5'10100 assign { } { } - assign $1\asmcode[7:0] 8'10100110 + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100111 + case 5'00100 assign { } { } - assign $1\asmcode[7:0] 8'10101001 + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'101100 + case 5'10010 assign { } { } - assign $1\asmcode[7:0] 8'10110010 + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_rsrv $0\dec31_dec_sub22_rsrv[0:0] + end + attribute \src "libresoc.v:94510.3-94564.6" + process $proc$libresoc.v:94510$3960 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_is_32b[0:0] $1\dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:94511.5-94511.29" + switch \initial + attribute \src "libresoc.v:94511.9-94511.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'101101 + case 5'00010 assign { } { } - assign $1\asmcode[7:0] 8'10110101 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100100 + case 5'00001 assign { } { } - assign $1\asmcode[7:0] 8'10111000 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100101 + case 5'01000 assign { } { } - assign $1\asmcode[7:0] 8'10111011 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001000 + case 5'00111 assign { } { } - assign $1\asmcode[7:0] 8'11000011 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'000010 + case 5'11111 assign { } { } - assign $1\asmcode[7:0] 8'11001011 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'000011 + case 5'11110 assign { } { } - assign $1\asmcode[7:0] 8'11001111 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011010 + case 5'00000 assign { } { } - assign $1\asmcode[7:0] 8'11010001 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011011 + case 5'11000 assign { } { } - assign $1\asmcode[7:0] 8'11010010 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_is_32b $0\dec31_dec_sub22_is_32b[0:0] + end + attribute \src "libresoc.v:94565.3-94619.6" + process $proc$libresoc.v:94565$3961 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sgn[0:0] $1\dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:94566.5-94566.29" + switch \initial + attribute \src "libresoc.v:94566.9-94566.17" + case 1'1 case - assign $1\asmcode[7:0] 8'00000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- + case 5'00010 assign { } { } - assign $2\asmcode[7:0] 8'00010011 + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1610612736 + case 5'00001 assign { } { } - assign $2\asmcode[7:0] 8'10000110 + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- + case 5'01000 assign { } { } - assign $2\asmcode[7:0] 8'10011100 + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 case - assign $2\asmcode[7:0] $1\asmcode[7:0] + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 end sync always - update \asmcode $0\asmcode[7:0] + update \dec31_dec_sub22_sgn $0\dec31_dec_sub22_sgn[0:0] end - attribute \src "libresoc.v:3524.3-3665.6" - process $proc$libresoc.v:3524$239 + attribute \src "libresoc.v:94620.3-94674.6" + process $proc$libresoc.v:94620$3962 assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_lk[0:0] $1\dec31_dec_sub22_lk[0:0] + attribute \src "libresoc.v:94621.5-94621.29" + switch \initial + attribute \src "libresoc.v:94621.9-94621.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_lk $0\dec31_dec_sub22_lk[0:0] + end + attribute \src "libresoc.v:94675.3-94729.6" + process $proc$libresoc.v:94675$3963 assign { } { } assign { } { } - assign $0\in1_sel[2:0] $2\in1_sel[2:0] - attribute \src "libresoc.v:3525.5-3525.29" + assign $0\dec31_dec_sub22_sgl_pipe[0:0] $1\dec31_dec_sub22_sgl_pipe[0:0] + attribute \src "libresoc.v:94676.5-94676.29" switch \initial - attribute \src "libresoc.v:3525.9-3525.17" + attribute \src "libresoc.v:94676.9-94676.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010011 + case 5'00010 assign { } { } - assign $1\in1_sel[2:0] \dec19_dec19_in1_sel + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'011110 + case 5'00001 assign { } { } - assign $1\in1_sel[2:0] \dec30_dec30_in1_sel + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'011111 + case 5'01000 assign { } { } - assign $1\in1_sel[2:0] \dec31_dec31_in1_sel + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'111010 + case 5'00111 assign { } { } - assign $1\in1_sel[2:0] \dec58_dec58_in1_sel + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'111110 + case 5'11111 assign { } { } - assign $1\in1_sel[2:0] \dec62_dec62_in1_sel + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001100 + case 5'11110 assign { } { } - assign $1\in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'001101 + case 5'00000 assign { } { } - assign $1\in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'001110 + case 5'11000 assign { } { } - assign $1\in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'001111 + case 5'10000 assign { } { } - assign $1\in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'010001 + case 5'10101 assign { } { } - assign $1\in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'011100 + case 5'00110 assign { } { } - assign $1\in1_sel[2:0] 3'100 + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'011101 + case 5'11100 assign { } { } - assign $1\in1_sel[2:0] 3'100 + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'010010 + case 5'10110 assign { } { } - assign $1\in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'010000 + case 5'10100 assign { } { } - assign $1\in1_sel[2:0] 3'011 + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'001011 + case 5'00100 assign { } { } - assign $1\in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'001010 + case 5'10010 assign { } { } - assign $1\in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_sgl_pipe $0\dec31_dec_sub22_sgl_pipe[0:0] + end + attribute \src "libresoc.v:94730.3-94784.6" + process $proc$libresoc.v:94730$3964 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_form[4:0] $1\dec31_dec_sub22_form[4:0] + attribute \src "libresoc.v:94731.5-94731.29" + switch \initial + attribute \src "libresoc.v:94731.9-94731.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'100010 + case 5'00010 assign { } { } - assign $1\in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'100011 + case 5'00001 assign { } { } - assign $1\in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'101010 + case 5'01000 assign { } { } - assign $1\in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'101011 + case 5'00111 assign { } { } - assign $1\in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'101000 + case 5'11111 assign { } { } - assign $1\in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'101001 + case 5'11110 assign { } { } - assign $1\in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'100000 + case 5'00000 assign { } { } - assign $1\in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'100001 + case 5'11000 assign { } { } - assign $1\in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'000111 + case 5'10000 assign { } { } - assign $1\in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'011000 + case 5'10101 assign { } { } - assign $1\in1_sel[2:0] 3'100 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'011001 + case 5'00110 assign { } { } - assign $1\in1_sel[2:0] 3'100 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'010100 + case 5'11100 assign { } { } - assign $1\in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'010101 + case 5'10110 assign { } { } - assign $1\in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'010111 + case 5'10100 assign { } { } - assign $1\in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'100110 + case 5'00100 assign { } { } - assign $1\in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'100111 + case 5'10010 assign { } { } - assign $1\in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub22_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub22_form $0\dec31_dec_sub22_form[4:0] + end + attribute \src "libresoc.v:94785.3-94839.6" + process $proc$libresoc.v:94785$3965 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_in1_sel[2:0] $1\dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:94786.5-94786.29" + switch \initial + attribute \src "libresoc.v:94786.9-94786.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'101100 + case 5'00010 assign { } { } - assign $1\in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'101101 + case 5'00001 assign { } { } - assign $1\in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'100100 + case 5'01000 assign { } { } - assign $1\in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'100101 + case 5'00111 assign { } { } - assign $1\in1_sel[2:0] 3'010 + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'001000 + case 5'11111 assign { } { } - assign $1\in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 6'000010 + case 5'11110 assign { } { } - assign $1\in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'000011 + case 5'00000 assign { } { } - assign $1\in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'011010 + case 5'11000 assign { } { } - assign $1\in1_sel[2:0] 3'100 + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 6'011011 + case 5'10000 assign { } { } - assign $1\in1_sel[2:0] 3'100 + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_in1_sel $0\dec31_dec_sub22_in1_sel[2:0] + end + attribute \src "libresoc.v:94840.3-94894.6" + process $proc$libresoc.v:94840$3966 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_in2_sel[3:0] $1\dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:94841.5-94841.29" + switch \initial + attribute \src "libresoc.v:94841.9-94841.17" + case 1'1 case - assign $1\in1_sel[2:0] 3'000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- + case 5'00010 assign { } { } - assign $2\in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 1610612736 + case 5'00001 assign { } { } - assign $2\in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 assign { } { } - assign $2\in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 case - assign $2\in1_sel[2:0] $1\in1_sel[2:0] + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 end sync always - update \in1_sel $0\in1_sel[2:0] + update \dec31_dec_sub22_in2_sel $0\dec31_dec_sub22_in2_sel[3:0] end - attribute \src "libresoc.v:3666.3-3807.6" - process $proc$libresoc.v:3666$240 + attribute \src "libresoc.v:94895.3-94949.6" + process $proc$libresoc.v:94895$3967 assign { } { } assign { } { } - assign { } { } - assign $0\in2_sel[3:0] $2\in2_sel[3:0] - attribute \src "libresoc.v:3667.5-3667.29" + assign $0\dec31_dec_sub22_in3_sel[1:0] $1\dec31_dec_sub22_in3_sel[1:0] + attribute \src "libresoc.v:94896.5-94896.29" switch \initial - attribute \src "libresoc.v:3667.9-3667.17" + attribute \src "libresoc.v:94896.9-94896.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010011 + case 5'00010 assign { } { } - assign $1\in2_sel[3:0] \dec19_dec19_in2_sel + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'011110 + case 5'00001 assign { } { } - assign $1\in2_sel[3:0] \dec30_dec30_in2_sel + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'011111 + case 5'01000 assign { } { } - assign $1\in2_sel[3:0] \dec31_dec31_in2_sel + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'111010 + case 5'00111 assign { } { } - assign $1\in2_sel[3:0] \dec58_dec58_in2_sel + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'111110 + case 5'11111 assign { } { } - assign $1\in2_sel[3:0] \dec62_dec62_in2_sel + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'001100 + case 5'11110 assign { } { } - assign $1\in2_sel[3:0] 4'0011 + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'001101 + case 5'00000 assign { } { } - assign $1\in2_sel[3:0] 4'0011 + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'001110 + case 5'11000 assign { } { } - assign $1\in2_sel[3:0] 4'0011 + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'001111 + case 5'10000 assign { } { } - assign $1\in2_sel[3:0] 4'0101 + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'010001 + case 5'10101 assign { } { } - assign $1\in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 6'011100 + case 5'00110 assign { } { } - assign $1\in2_sel[3:0] 4'0010 + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 6'011101 + case 5'11100 assign { } { } - assign $1\in2_sel[3:0] 4'0100 + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 6'010010 + case 5'10110 assign { } { } - assign $1\in2_sel[3:0] 4'0110 + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 6'010000 + case 5'10100 assign { } { } - assign $1\in2_sel[3:0] 4'0111 + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 6'001011 + case 5'00100 assign { } { } - assign $1\in2_sel[3:0] 4'0011 + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 6'001010 + case 5'10010 assign { } { } - assign $1\in2_sel[3:0] 4'0010 + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_in3_sel $0\dec31_dec_sub22_in3_sel[1:0] + end + attribute \src "libresoc.v:94950.3-95004.6" + process $proc$libresoc.v:94950$3968 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_out_sel[1:0] $1\dec31_dec_sub22_out_sel[1:0] + attribute \src "libresoc.v:94951.5-94951.29" + switch \initial + attribute \src "libresoc.v:94951.9-94951.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'100010 + case 5'00010 assign { } { } - assign $1\in2_sel[3:0] 4'0011 + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'100011 + case 5'00001 assign { } { } - assign $1\in2_sel[3:0] 4'0011 + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'101010 + case 5'01000 assign { } { } - assign $1\in2_sel[3:0] 4'0011 + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'101011 + case 5'00111 assign { } { } - assign $1\in2_sel[3:0] 4'0011 + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'101000 + case 5'11111 assign { } { } - assign $1\in2_sel[3:0] 4'0011 + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'101001 + case 5'11110 assign { } { } - assign $1\in2_sel[3:0] 4'0011 + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'100000 + case 5'00000 assign { } { } - assign $1\in2_sel[3:0] 4'0011 + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'100001 + case 5'11000 assign { } { } - assign $1\in2_sel[3:0] 4'0011 + assign $1\dec31_dec_sub22_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 6'000111 + case 5'10000 assign { } { } - assign $1\in2_sel[3:0] 4'0011 + assign $1\dec31_dec_sub22_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 6'011000 + case 5'10101 assign { } { } - assign $1\in2_sel[3:0] 4'0010 + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'011001 + case 5'00110 assign { } { } - assign $1\in2_sel[3:0] 4'0100 + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'010100 + case 5'11100 assign { } { } - assign $1\in2_sel[3:0] 4'1011 + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'010101 + case 5'10110 assign { } { } - assign $1\in2_sel[3:0] 4'1011 + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'010111 + case 5'10100 assign { } { } - assign $1\in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'100110 + case 5'00100 assign { } { } - assign $1\in2_sel[3:0] 4'0011 + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'100111 + case 5'10010 assign { } { } - assign $1\in2_sel[3:0] 4'0011 + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_out_sel $0\dec31_dec_sub22_out_sel[1:0] + end + attribute \src "libresoc.v:95005.3-95059.6" + process $proc$libresoc.v:95005$3969 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_cr_in[2:0] $1\dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:95006.5-95006.29" + switch \initial + attribute \src "libresoc.v:95006.9-95006.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'101100 + case 5'00010 assign { } { } - assign $1\in2_sel[3:0] 4'0011 + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'101101 + case 5'00001 assign { } { } - assign $1\in2_sel[3:0] 4'0011 + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'100100 + case 5'01000 assign { } { } - assign $1\in2_sel[3:0] 4'0011 + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'100101 + case 5'00111 assign { } { } - assign $1\in2_sel[3:0] 4'0011 + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'001000 + case 5'11111 assign { } { } - assign $1\in2_sel[3:0] 4'0011 + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'000010 + case 5'11110 assign { } { } - assign $1\in2_sel[3:0] 4'0011 + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'000011 + case 5'00000 assign { } { } - assign $1\in2_sel[3:0] 4'0011 + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'011010 + case 5'11000 assign { } { } - assign $1\in2_sel[3:0] 4'0010 + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'011011 + case 5'10000 assign { } { } - assign $1\in2_sel[3:0] 4'0100 - case - assign $1\in2_sel[3:0] 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- + case 5'10101 assign { } { } - assign $2\in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 1610612736 + case 5'00110 assign { } { } - assign $2\in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- + case 5'11100 assign { } { } - assign $2\in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 case - assign $2\in2_sel[3:0] $1\in2_sel[3:0] + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 end sync always - update \in2_sel $0\in2_sel[3:0] + update \dec31_dec_sub22_cr_in $0\dec31_dec_sub22_cr_in[2:0] end - attribute \src "libresoc.v:3808.3-3949.6" - process $proc$libresoc.v:3808$241 + attribute \src "libresoc.v:95060.3-95114.6" + process $proc$libresoc.v:95060$3970 assign { } { } assign { } { } - assign { } { } - assign $0\in3_sel[1:0] $2\in3_sel[1:0] - attribute \src "libresoc.v:3809.5-3809.29" + assign $0\dec31_dec_sub22_cr_out[2:0] $1\dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:95061.5-95061.29" switch \initial - attribute \src "libresoc.v:3809.9-3809.17" + attribute \src "libresoc.v:95061.9-95061.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010011 + case 5'00010 assign { } { } - assign $1\in3_sel[1:0] \dec19_dec19_in3_sel + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'011110 + case 5'00001 assign { } { } - assign $1\in3_sel[1:0] \dec30_dec30_in3_sel + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'011111 + case 5'01000 assign { } { } - assign $1\in3_sel[1:0] \dec31_dec31_in3_sel + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'111010 + case 5'00111 assign { } { } - assign $1\in3_sel[1:0] \dec58_dec58_in3_sel + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'111110 + case 5'11111 assign { } { } - assign $1\in3_sel[1:0] \dec62_dec62_in3_sel + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'001100 + case 5'11110 assign { } { } - assign $1\in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'001101 + case 5'00000 assign { } { } - assign $1\in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'001110 + case 5'11000 assign { } { } - assign $1\in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'001111 + case 5'10000 assign { } { } - assign $1\in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'010001 + case 5'10101 assign { } { } - assign $1\in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 6'011100 + case 5'00110 assign { } { } - assign $1\in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'011101 + case 5'11100 assign { } { } - assign $1\in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'010010 + case 5'10110 assign { } { } - assign $1\in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'010000 + case 5'10100 assign { } { } - assign $1\in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'001011 + case 5'00100 assign { } { } - assign $1\in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'001010 + case 5'10010 assign { } { } - assign $1\in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_cr_out $0\dec31_dec_sub22_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:95120.1-96555.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub23" +attribute \generator "nMigen" +module \dec31_dec_sub23 + attribute \src "libresoc.v:95623.3-95671.6" + wire width 8 $0\dec31_dec_sub23_asmcode[7:0] + attribute \src "libresoc.v:95819.3-95867.6" + wire $0\dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:96456.3-96504.6" + wire width 3 $0\dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:96505.3-96553.6" + wire width 3 $0\dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:95574.3-95622.6" + wire width 2 $0\dec31_dec_sub23_cry_in[1:0] + attribute \src "libresoc.v:95770.3-95818.6" + wire $0\dec31_dec_sub23_cry_out[0:0] + attribute \src "libresoc.v:96211.3-96259.6" + wire width 5 $0\dec31_dec_sub23_form[4:0] + attribute \src "libresoc.v:95378.3-95426.6" + wire width 12 $0\dec31_dec_sub23_function_unit[11:0] + attribute \src "libresoc.v:96260.3-96308.6" + wire width 3 $0\dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:96309.3-96357.6" + wire width 4 $0\dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:96358.3-96406.6" + wire width 2 $0\dec31_dec_sub23_in3_sel[1:0] + attribute \src "libresoc.v:95917.3-95965.6" + wire width 7 $0\dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:95672.3-95720.6" + wire $0\dec31_dec_sub23_inv_a[0:0] + attribute \src "libresoc.v:95721.3-95769.6" + wire $0\dec31_dec_sub23_inv_out[0:0] + attribute \src "libresoc.v:96015.3-96063.6" + wire $0\dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:95427.3-95475.6" + wire width 4 $0\dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:96113.3-96161.6" + wire $0\dec31_dec_sub23_lk[0:0] + attribute \src "libresoc.v:96407.3-96455.6" + wire width 2 $0\dec31_dec_sub23_out_sel[1:0] + attribute \src "libresoc.v:95525.3-95573.6" + wire width 2 $0\dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:95966.3-96014.6" + wire $0\dec31_dec_sub23_rsrv[0:0] + attribute \src "libresoc.v:96162.3-96210.6" + wire $0\dec31_dec_sub23_sgl_pipe[0:0] + attribute \src "libresoc.v:96064.3-96112.6" + wire $0\dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:95868.3-95916.6" + wire $0\dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:95476.3-95524.6" + wire width 2 $0\dec31_dec_sub23_upd[1:0] + attribute \src "libresoc.v:95121.7-95121.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:95623.3-95671.6" + wire width 8 $1\dec31_dec_sub23_asmcode[7:0] + attribute \src "libresoc.v:95819.3-95867.6" + wire $1\dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:96456.3-96504.6" + wire width 3 $1\dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:96505.3-96553.6" + wire width 3 $1\dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:95574.3-95622.6" + wire width 2 $1\dec31_dec_sub23_cry_in[1:0] + attribute \src "libresoc.v:95770.3-95818.6" + wire $1\dec31_dec_sub23_cry_out[0:0] + attribute \src "libresoc.v:96211.3-96259.6" + wire width 5 $1\dec31_dec_sub23_form[4:0] + attribute \src "libresoc.v:95378.3-95426.6" + wire width 12 $1\dec31_dec_sub23_function_unit[11:0] + attribute \src "libresoc.v:96260.3-96308.6" + wire width 3 $1\dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:96309.3-96357.6" + wire width 4 $1\dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:96358.3-96406.6" + wire width 2 $1\dec31_dec_sub23_in3_sel[1:0] + attribute \src "libresoc.v:95917.3-95965.6" + wire width 7 $1\dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:95672.3-95720.6" + wire $1\dec31_dec_sub23_inv_a[0:0] + attribute \src "libresoc.v:95721.3-95769.6" + wire $1\dec31_dec_sub23_inv_out[0:0] + attribute \src "libresoc.v:96015.3-96063.6" + wire $1\dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:95427.3-95475.6" + wire width 4 $1\dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:96113.3-96161.6" + wire $1\dec31_dec_sub23_lk[0:0] + attribute \src "libresoc.v:96407.3-96455.6" + wire width 2 $1\dec31_dec_sub23_out_sel[1:0] + attribute \src "libresoc.v:95525.3-95573.6" + wire width 2 $1\dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:95966.3-96014.6" + wire $1\dec31_dec_sub23_rsrv[0:0] + attribute \src "libresoc.v:96162.3-96210.6" + wire $1\dec31_dec_sub23_sgl_pipe[0:0] + attribute \src "libresoc.v:96064.3-96112.6" + wire $1\dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:95868.3-95916.6" + wire $1\dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:95476.3-95524.6" + wire width 2 $1\dec31_dec_sub23_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub23_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub23_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub23_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub23_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub23_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub23_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub23_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub23_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub23_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub23_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub23_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub23_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub23_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub23_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub23_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub23_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub23_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub23_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub23_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub23_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub23_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub23_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub23_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub23_upd + attribute \src "libresoc.v:95121.7-95121.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:95121.7-95121.20" + process $proc$libresoc.v:95121$3996 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:95378.3-95426.6" + process $proc$libresoc.v:95378$3972 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_function_unit[11:0] $1\dec31_dec_sub23_function_unit[11:0] + attribute \src "libresoc.v:95379.5-95379.29" + switch \initial + attribute \src "libresoc.v:95379.9-95379.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'100010 + case 5'00011 assign { } { } - assign $1\in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 attribute \src "libresoc.v:0.0-0.0" - case 6'100011 + case 5'00010 assign { } { } - assign $1\in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 attribute \src "libresoc.v:0.0-0.0" - case 6'101010 + case 5'01011 assign { } { } - assign $1\in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 attribute \src "libresoc.v:0.0-0.0" - case 6'101011 + case 5'01010 assign { } { } - assign $1\in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 attribute \src "libresoc.v:0.0-0.0" - case 6'101000 + case 5'01001 assign { } { } - assign $1\in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 attribute \src "libresoc.v:0.0-0.0" - case 6'101001 + case 5'01000 assign { } { } - assign $1\in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 attribute \src "libresoc.v:0.0-0.0" - case 6'100000 + case 5'00001 assign { } { } - assign $1\in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 attribute \src "libresoc.v:0.0-0.0" - case 6'100001 + case 5'00000 assign { } { } - assign $1\in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 attribute \src "libresoc.v:0.0-0.0" - case 6'000111 + case 5'00111 assign { } { } - assign $1\in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 attribute \src "libresoc.v:0.0-0.0" - case 6'011000 + case 5'00110 assign { } { } - assign $1\in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 attribute \src "libresoc.v:0.0-0.0" - case 6'011001 + case 5'01101 assign { } { } - assign $1\in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 attribute \src "libresoc.v:0.0-0.0" - case 6'010100 + case 5'01100 assign { } { } - assign $1\in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 attribute \src "libresoc.v:0.0-0.0" - case 6'010101 + case 5'00101 assign { } { } - assign $1\in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 attribute \src "libresoc.v:0.0-0.0" - case 6'010111 + case 5'00100 assign { } { } - assign $1\in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + case + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub23_function_unit $0\dec31_dec_sub23_function_unit[11:0] + end + attribute \src "libresoc.v:95427.3-95475.6" + process $proc$libresoc.v:95427$3973 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_ldst_len[3:0] $1\dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:95428.5-95428.29" + switch \initial + attribute \src "libresoc.v:95428.9-95428.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'100110 + case 5'00011 assign { } { } - assign $1\in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 6'100111 + case 5'00010 assign { } { } - assign $1\in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 6'101100 + case 5'01011 assign { } { } - assign $1\in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" - case 6'101101 + case 5'01010 assign { } { } - assign $1\in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" - case 6'100100 + case 5'01001 assign { } { } - assign $1\in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" - case 6'100101 + case 5'01000 assign { } { } - assign $1\in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" - case 6'001000 + case 5'00001 assign { } { } - assign $1\in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" - case 6'000010 + case 5'00000 assign { } { } - assign $1\in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" - case 6'000011 + case 5'00111 assign { } { } - assign $1\in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 6'011010 + case 5'00110 assign { } { } - assign $1\in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 6'011011 + case 5'01101 assign { } { } - assign $1\in3_sel[1:0] 2'00 - case - assign $1\in3_sel[1:0] 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- + case 5'01100 assign { } { } - assign $2\in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" - case 1610612736 + case 5'00101 assign { } { } - assign $2\in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- + case 5'00100 assign { } { } - assign $2\in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 case - assign $2\in3_sel[1:0] $1\in3_sel[1:0] + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0000 end sync always - update \in3_sel $0\in3_sel[1:0] + update \dec31_dec_sub23_ldst_len $0\dec31_dec_sub23_ldst_len[3:0] end - attribute \src "libresoc.v:3950.3-4091.6" - process $proc$libresoc.v:3950$242 + attribute \src "libresoc.v:95476.3-95524.6" + process $proc$libresoc.v:95476$3974 assign { } { } assign { } { } - assign { } { } - assign $0\out_sel[1:0] $2\out_sel[1:0] - attribute \src "libresoc.v:3951.5-3951.29" + assign $0\dec31_dec_sub23_upd[1:0] $1\dec31_dec_sub23_upd[1:0] + attribute \src "libresoc.v:95477.5-95477.29" switch \initial - attribute \src "libresoc.v:3951.9-3951.17" + attribute \src "libresoc.v:95477.9-95477.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\out_sel[1:0] \dec19_dec19_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\out_sel[1:0] \dec30_dec30_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 + case 5'00011 assign { } { } - assign $1\out_sel[1:0] \dec31_dec31_out_sel + assign $1\dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 6'111010 + case 5'00010 assign { } { } - assign $1\out_sel[1:0] \dec58_dec58_out_sel + assign $1\dec31_dec_sub23_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'111110 + case 5'01011 assign { } { } - assign $1\out_sel[1:0] \dec62_dec62_out_sel + assign $1\dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 6'001100 + case 5'01010 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'001101 + case 5'01001 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 6'001110 + case 5'01000 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'001111 + case 5'00001 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 6'010001 + case 5'00000 assign { } { } - assign $1\out_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'011100 + case 5'00111 assign { } { } - assign $1\out_sel[1:0] 2'10 + assign $1\dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 6'011101 + case 5'00110 assign { } { } - assign $1\out_sel[1:0] 2'10 + assign $1\dec31_dec_sub23_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'010010 + case 5'01101 assign { } { } - assign $1\out_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 6'010000 + case 5'01100 assign { } { } - assign $1\out_sel[1:0] 2'11 + assign $1\dec31_dec_sub23_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'001011 + case 5'00101 assign { } { } - assign $1\out_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 6'001010 + case 5'00100 assign { } { } - assign $1\out_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_upd $0\dec31_dec_sub23_upd[1:0] + end + attribute \src "libresoc.v:95525.3-95573.6" + process $proc$libresoc.v:95525$3975 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_rc_sel[1:0] $1\dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:95526.5-95526.29" + switch \initial + attribute \src "libresoc.v:95526.9-95526.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'100010 + case 5'00011 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'100011 + case 5'00010 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'101010 + case 5'01011 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'101011 + case 5'01010 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'101000 + case 5'01001 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'101001 + case 5'01000 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'100000 + case 5'00001 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'100001 + case 5'00000 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'000111 + case 5'00111 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 6'011000 + case 5'00110 assign { } { } - assign $1\out_sel[1:0] 2'10 + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 6'011001 + case 5'01101 assign { } { } - assign $1\out_sel[1:0] 2'10 + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'010100 + case 5'01100 assign { } { } - assign $1\out_sel[1:0] 2'10 + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'010101 + case 5'00101 assign { } { } - assign $1\out_sel[1:0] 2'10 + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'010111 + case 5'00100 assign { } { } - assign $1\out_sel[1:0] 2'10 + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_rc_sel $0\dec31_dec_sub23_rc_sel[1:0] + end + attribute \src "libresoc.v:95574.3-95622.6" + process $proc$libresoc.v:95574$3976 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_cry_in[1:0] $1\dec31_dec_sub23_cry_in[1:0] + attribute \src "libresoc.v:95575.5-95575.29" + switch \initial + attribute \src "libresoc.v:95575.9-95575.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'100110 + case 5'00011 assign { } { } - assign $1\out_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'100111 + case 5'00010 assign { } { } - assign $1\out_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'101100 + case 5'01011 assign { } { } - assign $1\out_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'101101 + case 5'01010 assign { } { } - assign $1\out_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'100100 + case 5'01001 assign { } { } - assign $1\out_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'100101 + case 5'01000 assign { } { } - assign $1\out_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'001000 + case 5'00001 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'000010 + case 5'00000 assign { } { } - assign $1\out_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'000011 + case 5'00111 assign { } { } - assign $1\out_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'011010 + case 5'00110 assign { } { } - assign $1\out_sel[1:0] 2'10 + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'011011 + case 5'01101 assign { } { } - assign $1\out_sel[1:0] 2'10 - case - assign $1\out_sel[1:0] 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- + case 5'01100 assign { } { } - assign $2\out_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1610612736 + case 5'00101 assign { } { } - assign $2\out_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- + case 5'00100 assign { } { } - assign $2\out_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 case - assign $2\out_sel[1:0] $1\out_sel[1:0] + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 end sync always - update \out_sel $0\out_sel[1:0] + update \dec31_dec_sub23_cry_in $0\dec31_dec_sub23_cry_in[1:0] end - attribute \src "libresoc.v:4092.3-4233.6" - process $proc$libresoc.v:4092$243 + attribute \src "libresoc.v:95623.3-95671.6" + process $proc$libresoc.v:95623$3977 assign { } { } assign { } { } - assign { } { } - assign $0\cr_in[2:0] $2\cr_in[2:0] - attribute \src "libresoc.v:4093.5-4093.29" + assign $0\dec31_dec_sub23_asmcode[7:0] $1\dec31_dec_sub23_asmcode[7:0] + attribute \src "libresoc.v:95624.5-95624.29" switch \initial - attribute \src "libresoc.v:4093.9-4093.17" + attribute \src "libresoc.v:95624.9-95624.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\cr_in[2:0] \dec19_dec19_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\cr_in[2:0] \dec30_dec30_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 + case 5'00011 assign { } { } - assign $1\cr_in[2:0] \dec31_dec31_cr_in + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01010000 attribute \src "libresoc.v:0.0-0.0" - case 6'111010 + case 5'00010 assign { } { } - assign $1\cr_in[2:0] \dec58_dec58_cr_in + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01010001 attribute \src "libresoc.v:0.0-0.0" - case 6'111110 + case 5'01011 assign { } { } - assign $1\cr_in[2:0] \dec62_dec62_cr_in + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01011011 attribute \src "libresoc.v:0.0-0.0" - case 6'001100 + case 5'01010 assign { } { } - assign $1\cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01011100 attribute \src "libresoc.v:0.0-0.0" - case 6'001101 + case 5'01001 assign { } { } - assign $1\cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01100000 attribute \src "libresoc.v:0.0-0.0" - case 6'001110 + case 5'01000 assign { } { } - assign $1\cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01100001 attribute \src "libresoc.v:0.0-0.0" - case 6'001111 + case 5'00001 assign { } { } - assign $1\cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01101010 attribute \src "libresoc.v:0.0-0.0" - case 6'010001 + case 5'00000 assign { } { } - assign $1\cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01101011 attribute \src "libresoc.v:0.0-0.0" - case 6'011100 + case 5'00111 assign { } { } - assign $1\cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10101010 attribute \src "libresoc.v:0.0-0.0" - case 6'011101 + case 5'00110 assign { } { } - assign $1\cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10101011 attribute \src "libresoc.v:0.0-0.0" - case 6'010010 + case 5'01101 assign { } { } - assign $1\cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10110110 attribute \src "libresoc.v:0.0-0.0" - case 6'010000 + case 5'01100 assign { } { } - assign $1\cr_in[2:0] 3'010 + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10110111 attribute \src "libresoc.v:0.0-0.0" - case 6'001011 + case 5'00101 assign { } { } - assign $1\cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111100 attribute \src "libresoc.v:0.0-0.0" - case 6'001010 + case 5'00100 assign { } { } - assign $1\cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111101 + case + assign $1\dec31_dec_sub23_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub23_asmcode $0\dec31_dec_sub23_asmcode[7:0] + end + attribute \src "libresoc.v:95672.3-95720.6" + process $proc$libresoc.v:95672$3978 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_inv_a[0:0] $1\dec31_dec_sub23_inv_a[0:0] + attribute \src "libresoc.v:95673.5-95673.29" + switch \initial + attribute \src "libresoc.v:95673.9-95673.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'100010 + case 5'00011 assign { } { } - assign $1\cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100011 + case 5'00010 assign { } { } - assign $1\cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101010 + case 5'01011 assign { } { } - assign $1\cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101011 + case 5'01010 assign { } { } - assign $1\cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101000 + case 5'01001 assign { } { } - assign $1\cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101001 + case 5'01000 assign { } { } - assign $1\cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100000 + case 5'00001 assign { } { } - assign $1\cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100001 + case 5'00000 assign { } { } - assign $1\cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'000111 + case 5'00111 assign { } { } - assign $1\cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011000 + case 5'00110 assign { } { } - assign $1\cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011001 + case 5'01101 assign { } { } - assign $1\cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010100 + case 5'01100 assign { } { } - assign $1\cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010101 + case 5'00101 assign { } { } - assign $1\cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010111 + case 5'00100 assign { } { } - assign $1\cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_inv_a $0\dec31_dec_sub23_inv_a[0:0] + end + attribute \src "libresoc.v:95721.3-95769.6" + process $proc$libresoc.v:95721$3979 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_inv_out[0:0] $1\dec31_dec_sub23_inv_out[0:0] + attribute \src "libresoc.v:95722.5-95722.29" + switch \initial + attribute \src "libresoc.v:95722.9-95722.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'100110 + case 5'00011 assign { } { } - assign $1\cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100111 + case 5'00010 assign { } { } - assign $1\cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101100 + case 5'01011 assign { } { } - assign $1\cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101101 + case 5'01010 assign { } { } - assign $1\cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100100 + case 5'01001 assign { } { } - assign $1\cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100101 + case 5'01000 assign { } { } - assign $1\cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001000 + case 5'00001 assign { } { } - assign $1\cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'000010 + case 5'00000 assign { } { } - assign $1\cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'000011 + case 5'00111 assign { } { } - assign $1\cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011010 + case 5'00110 assign { } { } - assign $1\cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011011 + case 5'01101 assign { } { } - assign $1\cr_in[2:0] 3'000 - case - assign $1\cr_in[2:0] 3'000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- + case 5'01100 assign { } { } - assign $2\cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1610612736 + case 5'00101 assign { } { } - assign $2\cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- + case 5'00100 assign { } { } - assign $2\cr_in[2:0] 3'000 + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 case - assign $2\cr_in[2:0] $1\cr_in[2:0] + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 end sync always - update \cr_in $0\cr_in[2:0] + update \dec31_dec_sub23_inv_out $0\dec31_dec_sub23_inv_out[0:0] end - attribute \src "libresoc.v:4234.3-4375.6" - process $proc$libresoc.v:4234$244 + attribute \src "libresoc.v:95770.3-95818.6" + process $proc$libresoc.v:95770$3980 assign { } { } assign { } { } - assign { } { } - assign $0\cr_out[2:0] $2\cr_out[2:0] - attribute \src "libresoc.v:4235.5-4235.29" + assign $0\dec31_dec_sub23_cry_out[0:0] $1\dec31_dec_sub23_cry_out[0:0] + attribute \src "libresoc.v:95771.5-95771.29" switch \initial - attribute \src "libresoc.v:4235.9-4235.17" + attribute \src "libresoc.v:95771.9-95771.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\cr_out[2:0] \dec19_dec19_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\cr_out[2:0] \dec30_dec30_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 + case 5'00011 assign { } { } - assign $1\cr_out[2:0] \dec31_dec31_cr_out + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'111010 + case 5'00010 assign { } { } - assign $1\cr_out[2:0] \dec58_dec58_cr_out + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'111110 + case 5'01011 assign { } { } - assign $1\cr_out[2:0] \dec62_dec62_cr_out + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001100 + case 5'01010 assign { } { } - assign $1\cr_out[2:0] 3'000 + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001101 + case 5'01001 assign { } { } - assign $1\cr_out[2:0] 3'001 + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001110 + case 5'01000 assign { } { } - assign $1\cr_out[2:0] 3'000 + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001111 + case 5'00001 assign { } { } - assign $1\cr_out[2:0] 3'000 + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010001 + case 5'00000 assign { } { } - assign $1\cr_out[2:0] 3'000 + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011100 + case 5'00111 assign { } { } - assign $1\cr_out[2:0] 3'001 + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011101 + case 5'00110 assign { } { } - assign $1\cr_out[2:0] 3'001 + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010010 + case 5'01101 assign { } { } - assign $1\cr_out[2:0] 3'000 + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010000 + case 5'01100 assign { } { } - assign $1\cr_out[2:0] 3'000 + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001011 + case 5'00101 assign { } { } - assign $1\cr_out[2:0] 3'010 + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001010 + case 5'00100 assign { } { } - assign $1\cr_out[2:0] 3'010 + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_cry_out $0\dec31_dec_sub23_cry_out[0:0] + end + attribute \src "libresoc.v:95819.3-95867.6" + process $proc$libresoc.v:95819$3981 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_br[0:0] $1\dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:95820.5-95820.29" + switch \initial + attribute \src "libresoc.v:95820.9-95820.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'100010 + case 5'00011 assign { } { } - assign $1\cr_out[2:0] 3'000 + assign $1\dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100011 + case 5'00010 assign { } { } - assign $1\cr_out[2:0] 3'000 + assign $1\dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101010 + case 5'01011 assign { } { } - assign $1\cr_out[2:0] 3'000 + assign $1\dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101011 + case 5'01010 assign { } { } - assign $1\cr_out[2:0] 3'000 + assign $1\dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101000 + case 5'01001 assign { } { } - assign $1\cr_out[2:0] 3'000 + assign $1\dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101001 + case 5'01000 assign { } { } - assign $1\cr_out[2:0] 3'000 + assign $1\dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100000 + case 5'00001 assign { } { } - assign $1\cr_out[2:0] 3'000 + assign $1\dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100001 + case 5'00000 assign { } { } - assign $1\cr_out[2:0] 3'000 + assign $1\dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'000111 + case 5'00111 assign { } { } - assign $1\cr_out[2:0] 3'001 + assign $1\dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011000 + case 5'00110 assign { } { } - assign $1\cr_out[2:0] 3'000 + assign $1\dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011001 + case 5'01101 assign { } { } - assign $1\cr_out[2:0] 3'000 + assign $1\dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010100 + case 5'01100 assign { } { } - assign $1\cr_out[2:0] 3'001 + assign $1\dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010101 + case 5'00101 assign { } { } - assign $1\cr_out[2:0] 3'001 + assign $1\dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010111 + case 5'00100 assign { } { } - assign $1\cr_out[2:0] 3'001 + assign $1\dec31_dec_sub23_br[0:0] 1'0 + case + assign $1\dec31_dec_sub23_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_br $0\dec31_dec_sub23_br[0:0] + end + attribute \src "libresoc.v:95868.3-95916.6" + process $proc$libresoc.v:95868$3982 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sgn_ext[0:0] $1\dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:95869.5-95869.29" + switch \initial + attribute \src "libresoc.v:95869.9-95869.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'100110 + case 5'00011 assign { } { } - assign $1\cr_out[2:0] 3'000 + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100111 + case 5'00010 assign { } { } - assign $1\cr_out[2:0] 3'000 + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101100 + case 5'01011 assign { } { } - assign $1\cr_out[2:0] 3'000 + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'101101 + case 5'01010 assign { } { } - assign $1\cr_out[2:0] 3'000 + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'100100 + case 5'01001 assign { } { } - assign $1\cr_out[2:0] 3'000 + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100101 + case 5'01000 assign { } { } - assign $1\cr_out[2:0] 3'000 + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001000 + case 5'00001 assign { } { } - assign $1\cr_out[2:0] 3'000 + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'000010 + case 5'00000 assign { } { } - assign $1\cr_out[2:0] 3'000 + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'000011 + case 5'00111 assign { } { } - assign $1\cr_out[2:0] 3'000 + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011010 + case 5'00110 assign { } { } - assign $1\cr_out[2:0] 3'000 + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011011 + case 5'01101 assign { } { } - assign $1\cr_out[2:0] 3'000 - case - assign $1\cr_out[2:0] 3'000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- + case 5'01100 assign { } { } - assign $2\cr_out[2:0] 3'000 + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1610612736 + case 5'00101 assign { } { } - assign $2\cr_out[2:0] 3'000 + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- + case 5'00100 assign { } { } - assign $2\cr_out[2:0] 3'000 + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 case - assign $2\cr_out[2:0] $1\cr_out[2:0] + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 end sync always - update \cr_out $0\cr_out[2:0] + update \dec31_dec_sub23_sgn_ext $0\dec31_dec_sub23_sgn_ext[0:0] end - attribute \src "libresoc.v:4376.3-4517.6" - process $proc$libresoc.v:4376$245 + attribute \src "libresoc.v:95917.3-95965.6" + process $proc$libresoc.v:95917$3983 assign { } { } assign { } { } - assign { } { } - assign $0\ldst_len[3:0] $2\ldst_len[3:0] - attribute \src "libresoc.v:4377.5-4377.29" + assign $0\dec31_dec_sub23_internal_op[6:0] $1\dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:95918.5-95918.29" switch \initial - attribute \src "libresoc.v:4377.9-4377.17" + attribute \src "libresoc.v:95918.9-95918.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\ldst_len[3:0] \dec19_dec19_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\ldst_len[3:0] \dec30_dec30_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 + case 5'00011 assign { } { } - assign $1\ldst_len[3:0] \dec31_dec31_ldst_len + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" - case 6'111010 + case 5'00010 assign { } { } - assign $1\ldst_len[3:0] \dec58_dec58_ldst_len + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" - case 6'111110 + case 5'01011 assign { } { } - assign $1\ldst_len[3:0] \dec62_dec62_ldst_len + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" - case 6'001100 + case 5'01010 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" - case 6'001101 + case 5'01001 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" - case 6'001110 + case 5'01000 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" - case 6'001111 + case 5'00001 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" - case 6'010001 + case 5'00000 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" - case 6'011100 + case 5'00111 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" - case 6'011101 + case 5'00110 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" - case 6'010010 + case 5'01101 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" - case 6'010000 + case 5'01100 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" - case 6'001011 + case 5'00101 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" - case 6'001010 + case 5'00100 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + case + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub23_internal_op $0\dec31_dec_sub23_internal_op[6:0] + end + attribute \src "libresoc.v:95966.3-96014.6" + process $proc$libresoc.v:95966$3984 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_rsrv[0:0] $1\dec31_dec_sub23_rsrv[0:0] + attribute \src "libresoc.v:95967.5-95967.29" + switch \initial + attribute \src "libresoc.v:95967.9-95967.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'100010 + case 5'00011 assign { } { } - assign $1\ldst_len[3:0] 4'0001 + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100011 + case 5'00010 assign { } { } - assign $1\ldst_len[3:0] 4'0001 + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101010 + case 5'01011 assign { } { } - assign $1\ldst_len[3:0] 4'0010 + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101011 + case 5'01010 assign { } { } - assign $1\ldst_len[3:0] 4'0010 + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101000 + case 5'01001 assign { } { } - assign $1\ldst_len[3:0] 4'0010 + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101001 + case 5'01000 assign { } { } - assign $1\ldst_len[3:0] 4'0010 + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100000 + case 5'00001 assign { } { } - assign $1\ldst_len[3:0] 4'0100 + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100001 + case 5'00000 assign { } { } - assign $1\ldst_len[3:0] 4'0100 + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'000111 + case 5'00111 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011000 + case 5'00110 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011001 + case 5'01101 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010100 + case 5'01100 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010101 + case 5'00101 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010111 + case 5'00100 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_rsrv $0\dec31_dec_sub23_rsrv[0:0] + end + attribute \src "libresoc.v:96015.3-96063.6" + process $proc$libresoc.v:96015$3985 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_is_32b[0:0] $1\dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:96016.5-96016.29" + switch \initial + attribute \src "libresoc.v:96016.9-96016.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'100110 + case 5'00011 assign { } { } - assign $1\ldst_len[3:0] 4'0001 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100111 + case 5'00010 assign { } { } - assign $1\ldst_len[3:0] 4'0001 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101100 + case 5'01011 assign { } { } - assign $1\ldst_len[3:0] 4'0010 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101101 + case 5'01010 assign { } { } - assign $1\ldst_len[3:0] 4'0010 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100100 + case 5'01001 assign { } { } - assign $1\ldst_len[3:0] 4'0100 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100101 + case 5'01000 assign { } { } - assign $1\ldst_len[3:0] 4'0100 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001000 + case 5'00001 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'000010 + case 5'00000 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'000011 + case 5'00111 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011010 + case 5'00110 assign { } { } - assign $1\ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011011 + case 5'01101 assign { } { } - assign $1\ldst_len[3:0] 4'0000 - case - assign $1\ldst_len[3:0] 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- + case 5'01100 assign { } { } - assign $2\ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1610612736 + case 5'00101 assign { } { } - assign $2\ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- + case 5'00100 assign { } { } - assign $2\ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 case - assign $2\ldst_len[3:0] $1\ldst_len[3:0] + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 end sync always - update \ldst_len $0\ldst_len[3:0] + update \dec31_dec_sub23_is_32b $0\dec31_dec_sub23_is_32b[0:0] end - attribute \src "libresoc.v:4518.3-4659.6" - process $proc$libresoc.v:4518$246 + attribute \src "libresoc.v:96064.3-96112.6" + process $proc$libresoc.v:96064$3986 assign { } { } assign { } { } - assign { } { } - assign $0\upd[1:0] $2\upd[1:0] - attribute \src "libresoc.v:4519.5-4519.29" + assign $0\dec31_dec_sub23_sgn[0:0] $1\dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:96065.5-96065.29" switch \initial - attribute \src "libresoc.v:4519.9-4519.17" + attribute \src "libresoc.v:96065.9-96065.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\upd[1:0] \dec19_dec19_upd - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\upd[1:0] \dec30_dec30_upd - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 + case 5'00011 assign { } { } - assign $1\upd[1:0] \dec31_dec31_upd + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'111010 + case 5'00010 assign { } { } - assign $1\upd[1:0] \dec58_dec58_upd + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'111110 + case 5'01011 assign { } { } - assign $1\upd[1:0] \dec62_dec62_upd + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001100 + case 5'01010 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001101 + case 5'01001 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001110 + case 5'01000 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001111 + case 5'00001 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010001 + case 5'00000 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011100 + case 5'00111 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011101 + case 5'00110 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010010 + case 5'01101 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010000 + case 5'01100 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001011 + case 5'00101 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001010 + case 5'00100 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_sgn $0\dec31_dec_sub23_sgn[0:0] + end + attribute \src "libresoc.v:96113.3-96161.6" + process $proc$libresoc.v:96113$3987 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_lk[0:0] $1\dec31_dec_sub23_lk[0:0] + attribute \src "libresoc.v:96114.5-96114.29" + switch \initial + attribute \src "libresoc.v:96114.9-96114.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'100010 + case 5'00011 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\dec31_dec_sub23_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100011 + case 5'00010 assign { } { } - assign $1\upd[1:0] 2'01 + assign $1\dec31_dec_sub23_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101010 + case 5'01011 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\dec31_dec_sub23_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101011 + case 5'01010 assign { } { } - assign $1\upd[1:0] 2'01 + assign $1\dec31_dec_sub23_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101000 + case 5'01001 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\dec31_dec_sub23_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101001 + case 5'01000 assign { } { } - assign $1\upd[1:0] 2'01 + assign $1\dec31_dec_sub23_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100000 + case 5'00001 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\dec31_dec_sub23_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100001 + case 5'00000 assign { } { } - assign $1\upd[1:0] 2'01 + assign $1\dec31_dec_sub23_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'000111 + case 5'00111 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\dec31_dec_sub23_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011000 + case 5'00110 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\dec31_dec_sub23_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011001 + case 5'01101 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\dec31_dec_sub23_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010100 + case 5'01100 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\dec31_dec_sub23_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010101 + case 5'00101 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\dec31_dec_sub23_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010111 + case 5'00100 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_lk $0\dec31_dec_sub23_lk[0:0] + end + attribute \src "libresoc.v:96162.3-96210.6" + process $proc$libresoc.v:96162$3988 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sgl_pipe[0:0] $1\dec31_dec_sub23_sgl_pipe[0:0] + attribute \src "libresoc.v:96163.5-96163.29" + switch \initial + attribute \src "libresoc.v:96163.9-96163.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'100110 + case 5'00011 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'100111 + case 5'00010 assign { } { } - assign $1\upd[1:0] 2'01 + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'101100 + case 5'01011 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'101101 + case 5'01010 assign { } { } - assign $1\upd[1:0] 2'01 + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'100100 + case 5'01001 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'100101 + case 5'01000 assign { } { } - assign $1\upd[1:0] 2'01 + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'001000 + case 5'00001 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'000010 + case 5'00000 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'000011 + case 5'00111 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'011010 + case 5'00110 assign { } { } - assign $1\upd[1:0] 2'00 + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'011011 + case 5'01101 assign { } { } - assign $1\upd[1:0] 2'00 - case - assign $1\upd[1:0] 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- + case 5'01100 assign { } { } - assign $2\upd[1:0] 2'00 + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 1610612736 + case 5'00101 assign { } { } - assign $2\upd[1:0] 2'00 + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- + case 5'00100 assign { } { } - assign $2\upd[1:0] 2'00 + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 case - assign $2\upd[1:0] $1\upd[1:0] + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'0 end sync always - update \upd $0\upd[1:0] + update \dec31_dec_sub23_sgl_pipe $0\dec31_dec_sub23_sgl_pipe[0:0] end - attribute \src "libresoc.v:4660.3-4801.6" - process $proc$libresoc.v:4660$247 + attribute \src "libresoc.v:96211.3-96259.6" + process $proc$libresoc.v:96211$3989 assign { } { } assign { } { } - assign { } { } - assign $0\rc_sel[1:0] $2\rc_sel[1:0] - attribute \src "libresoc.v:4661.5-4661.29" + assign $0\dec31_dec_sub23_form[4:0] $1\dec31_dec_sub23_form[4:0] + attribute \src "libresoc.v:96212.5-96212.29" switch \initial - attribute \src "libresoc.v:4661.9-4661.17" + attribute \src "libresoc.v:96212.9-96212.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\rc_sel[1:0] \dec19_dec19_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\rc_sel[1:0] \dec30_dec30_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 + case 5'00011 assign { } { } - assign $1\rc_sel[1:0] \dec31_dec31_rc_sel + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'111010 + case 5'00010 assign { } { } - assign $1\rc_sel[1:0] \dec58_dec58_rc_sel + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'111110 + case 5'01011 assign { } { } - assign $1\rc_sel[1:0] \dec62_dec62_rc_sel + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'001100 + case 5'01010 assign { } { } - assign $1\rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'001101 + case 5'01001 assign { } { } - assign $1\rc_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'001110 + case 5'01000 assign { } { } - assign $1\rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'001111 + case 5'00001 assign { } { } - assign $1\rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'010001 + case 5'00000 assign { } { } - assign $1\rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'011100 + case 5'00111 assign { } { } - assign $1\rc_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'011101 + case 5'00110 assign { } { } - assign $1\rc_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'010010 + case 5'01101 assign { } { } - assign $1\rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'010000 + case 5'01100 assign { } { } - assign $1\rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'001011 + case 5'00101 assign { } { } - assign $1\rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'001010 + case 5'00100 assign { } { } - assign $1\rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub23_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub23_form $0\dec31_dec_sub23_form[4:0] + end + attribute \src "libresoc.v:96260.3-96308.6" + process $proc$libresoc.v:96260$3990 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_in1_sel[2:0] $1\dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:96261.5-96261.29" + switch \initial + attribute \src "libresoc.v:96261.9-96261.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'100010 + case 5'00011 assign { } { } - assign $1\rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 6'100011 + case 5'00010 assign { } { } - assign $1\rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 6'101010 + case 5'01011 assign { } { } - assign $1\rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 6'101011 + case 5'01010 assign { } { } - assign $1\rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 6'101000 + case 5'01001 assign { } { } - assign $1\rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 6'101001 + case 5'01000 assign { } { } - assign $1\rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 6'100000 + case 5'00001 assign { } { } - assign $1\rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 6'100001 + case 5'00000 assign { } { } - assign $1\rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 6'000111 + case 5'00111 assign { } { } - assign $1\rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 6'011000 + case 5'00110 assign { } { } - assign $1\rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 6'011001 + case 5'01101 assign { } { } - assign $1\rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 6'010100 + case 5'01100 assign { } { } - assign $1\rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 6'010101 + case 5'00101 assign { } { } - assign $1\rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 6'010111 + case 5'00100 assign { } { } - assign $1\rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_in1_sel $0\dec31_dec_sub23_in1_sel[2:0] + end + attribute \src "libresoc.v:96309.3-96357.6" + process $proc$libresoc.v:96309$3991 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_in2_sel[3:0] $1\dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:96310.5-96310.29" + switch \initial + attribute \src "libresoc.v:96310.9-96310.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'100110 + case 5'00011 assign { } { } - assign $1\rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 6'100111 + case 5'00010 assign { } { } - assign $1\rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 6'101100 + case 5'01011 assign { } { } - assign $1\rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 6'101101 + case 5'01010 assign { } { } - assign $1\rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 6'100100 + case 5'01001 assign { } { } - assign $1\rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 6'100101 + case 5'01000 assign { } { } - assign $1\rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 6'001000 + case 5'00001 assign { } { } - assign $1\rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 6'000010 + case 5'00000 assign { } { } - assign $1\rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 6'000011 + case 5'00111 assign { } { } - assign $1\rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 6'011010 + case 5'00110 assign { } { } - assign $1\rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 6'011011 + case 5'01101 assign { } { } - assign $1\rc_sel[1:0] 2'00 - case - assign $1\rc_sel[1:0] 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- + case 5'01100 assign { } { } - assign $2\rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 1610612736 + case 5'00101 assign { } { } - assign $2\rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- + case 5'00100 assign { } { } - assign $2\rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 case - assign $2\rc_sel[1:0] $1\rc_sel[1:0] + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0000 end sync always - update \rc_sel $0\rc_sel[1:0] + update \dec31_dec_sub23_in2_sel $0\dec31_dec_sub23_in2_sel[3:0] end - attribute \src "libresoc.v:4802.3-4943.6" - process $proc$libresoc.v:4802$248 + attribute \src "libresoc.v:96358.3-96406.6" + process $proc$libresoc.v:96358$3992 assign { } { } assign { } { } - assign { } { } - assign $0\cry_in[1:0] $2\cry_in[1:0] - attribute \src "libresoc.v:4803.5-4803.29" + assign $0\dec31_dec_sub23_in3_sel[1:0] $1\dec31_dec_sub23_in3_sel[1:0] + attribute \src "libresoc.v:96359.5-96359.29" switch \initial - attribute \src "libresoc.v:4803.9-4803.17" + attribute \src "libresoc.v:96359.9-96359.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\cry_in[1:0] \dec19_dec19_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\cry_in[1:0] \dec30_dec30_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 + case 5'00011 assign { } { } - assign $1\cry_in[1:0] \dec31_dec31_cry_in + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'111010 + case 5'00010 assign { } { } - assign $1\cry_in[1:0] \dec58_dec58_cry_in + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'111110 + case 5'01011 assign { } { } - assign $1\cry_in[1:0] \dec62_dec62_cry_in + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'001100 + case 5'01010 assign { } { } - assign $1\cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'001101 + case 5'01001 assign { } { } - assign $1\cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'001110 + case 5'01000 assign { } { } - assign $1\cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'001111 + case 5'00001 assign { } { } - assign $1\cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'010001 + case 5'00000 assign { } { } - assign $1\cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'011100 + case 5'00111 assign { } { } - assign $1\cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 6'011101 + case 5'00110 assign { } { } - assign $1\cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 6'010010 + case 5'01101 assign { } { } - assign $1\cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 6'010000 + case 5'01100 assign { } { } - assign $1\cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 6'001011 + case 5'00101 assign { } { } - assign $1\cry_in[1:0] 2'01 + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 6'001010 + case 5'00100 assign { } { } - assign $1\cry_in[1:0] 2'01 + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_in3_sel $0\dec31_dec_sub23_in3_sel[1:0] + end + attribute \src "libresoc.v:96407.3-96455.6" + process $proc$libresoc.v:96407$3993 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_out_sel[1:0] $1\dec31_dec_sub23_out_sel[1:0] + attribute \src "libresoc.v:96408.5-96408.29" + switch \initial + attribute \src "libresoc.v:96408.9-96408.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'100010 + case 5'00011 assign { } { } - assign $1\cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 6'100011 + case 5'00010 assign { } { } - assign $1\cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 6'101010 + case 5'01011 assign { } { } - assign $1\cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 6'101011 + case 5'01010 assign { } { } - assign $1\cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 6'101000 + case 5'01001 assign { } { } - assign $1\cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 6'101001 + case 5'01000 assign { } { } - assign $1\cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 6'100000 + case 5'00001 assign { } { } - assign $1\cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 6'100001 + case 5'00000 assign { } { } - assign $1\cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 6'000111 + case 5'00111 assign { } { } - assign $1\cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'011000 + case 5'00110 assign { } { } - assign $1\cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'011001 + case 5'01101 assign { } { } - assign $1\cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'010100 + case 5'01100 assign { } { } - assign $1\cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'010101 + case 5'00101 assign { } { } - assign $1\cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'010111 + case 5'00100 assign { } { } - assign $1\cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_out_sel $0\dec31_dec_sub23_out_sel[1:0] + end + attribute \src "libresoc.v:96456.3-96504.6" + process $proc$libresoc.v:96456$3994 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_cr_in[2:0] $1\dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:96457.5-96457.29" + switch \initial + attribute \src "libresoc.v:96457.9-96457.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'100110 + case 5'00011 assign { } { } - assign $1\cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'100111 + case 5'00010 assign { } { } - assign $1\cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'101100 + case 5'01011 assign { } { } - assign $1\cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'101101 + case 5'01010 assign { } { } - assign $1\cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'100100 + case 5'01001 assign { } { } - assign $1\cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'100101 + case 5'01000 assign { } { } - assign $1\cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'001000 + case 5'00001 assign { } { } - assign $1\cry_in[1:0] 2'01 + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'000010 + case 5'00000 assign { } { } - assign $1\cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'000011 + case 5'00111 assign { } { } - assign $1\cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'011010 + case 5'00110 assign { } { } - assign $1\cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'011011 + case 5'01101 assign { } { } - assign $1\cry_in[1:0] 2'00 - case - assign $1\cry_in[1:0] 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- + case 5'01100 assign { } { } - assign $2\cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 1610612736 + case 5'00101 assign { } { } - assign $2\cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- + case 5'00100 assign { } { } - assign $2\cry_in[1:0] 2'00 + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 case - assign $2\cry_in[1:0] $1\cry_in[1:0] + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 end sync always - update \cry_in $0\cry_in[1:0] + update \dec31_dec_sub23_cr_in $0\dec31_dec_sub23_cr_in[2:0] end - attribute \src "libresoc.v:4944.3-5085.6" - process $proc$libresoc.v:4944$249 + attribute \src "libresoc.v:96505.3-96553.6" + process $proc$libresoc.v:96505$3995 assign { } { } assign { } { } - assign { } { } - assign $0\inv_a[0:0] $2\inv_a[0:0] - attribute \src "libresoc.v:4945.5-4945.29" + assign $0\dec31_dec_sub23_cr_out[2:0] $1\dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:96506.5-96506.29" switch \initial - attribute \src "libresoc.v:4945.9-4945.17" + attribute \src "libresoc.v:96506.9-96506.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\inv_a[0:0] \dec19_dec19_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\inv_a[0:0] \dec30_dec30_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\inv_a[0:0] \dec31_dec31_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\inv_a[0:0] \dec58_dec58_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\inv_a[0:0] \dec62_dec62_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 + case 5'00011 assign { } { } - assign $1\inv_a[0:0] 1'0 + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'001111 + case 5'00010 assign { } { } - assign $1\inv_a[0:0] 1'0 + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'010001 + case 5'01011 assign { } { } - assign $1\inv_a[0:0] 1'0 + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'011100 + case 5'01010 assign { } { } - assign $1\inv_a[0:0] 1'0 + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'011101 + case 5'01001 assign { } { } - assign $1\inv_a[0:0] 1'0 + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'010010 + case 5'01000 assign { } { } - assign $1\inv_a[0:0] 1'0 + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'010000 + case 5'00001 assign { } { } - assign $1\inv_a[0:0] 1'0 + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'001011 + case 5'00000 assign { } { } - assign $1\inv_a[0:0] 1'1 + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'001010 + case 5'00111 assign { } { } - assign $1\inv_a[0:0] 1'1 + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'100010 + case 5'00110 assign { } { } - assign $1\inv_a[0:0] 1'0 + assign $1\dec31_dec_sub23_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 6'100011 + case 5'01101 assign { } { } - assign $1\inv_a[0:0] 1'0 + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'101010 + case 5'01100 assign { } { } - assign $1\inv_a[0:0] 1'0 + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'101011 + case 5'00101 assign { } { } - assign $1\inv_a[0:0] 1'0 + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'101000 + case 5'00100 assign { } { } - assign $1\inv_a[0:0] 1'0 + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_cr_out $0\dec31_dec_sub23_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:96559.1-97274.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub24" +attribute \generator "nMigen" +module \dec31_dec_sub24 + attribute \src "libresoc.v:96912.3-96930.6" + wire width 8 $0\dec31_dec_sub24_asmcode[7:0] + attribute \src "libresoc.v:96988.3-97006.6" + wire $0\dec31_dec_sub24_br[0:0] + attribute \src "libresoc.v:97235.3-97253.6" + wire width 3 $0\dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:97254.3-97272.6" + wire width 3 $0\dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:96893.3-96911.6" + wire width 2 $0\dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:96969.3-96987.6" + wire $0\dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:97140.3-97158.6" + wire width 5 $0\dec31_dec_sub24_form[4:0] + attribute \src "libresoc.v:96817.3-96835.6" + wire width 12 $0\dec31_dec_sub24_function_unit[11:0] + attribute \src "libresoc.v:97159.3-97177.6" + wire width 3 $0\dec31_dec_sub24_in1_sel[2:0] + attribute \src "libresoc.v:97178.3-97196.6" + wire width 4 $0\dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:97197.3-97215.6" + wire width 2 $0\dec31_dec_sub24_in3_sel[1:0] + attribute \src "libresoc.v:97026.3-97044.6" + wire width 7 $0\dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:96931.3-96949.6" + wire $0\dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:96950.3-96968.6" + wire $0\dec31_dec_sub24_inv_out[0:0] + attribute \src "libresoc.v:97064.3-97082.6" + wire $0\dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:96836.3-96854.6" + wire width 4 $0\dec31_dec_sub24_ldst_len[3:0] + attribute \src "libresoc.v:97102.3-97120.6" + wire $0\dec31_dec_sub24_lk[0:0] + attribute \src "libresoc.v:97216.3-97234.6" + wire width 2 $0\dec31_dec_sub24_out_sel[1:0] + attribute \src "libresoc.v:96874.3-96892.6" + wire width 2 $0\dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:97045.3-97063.6" + wire $0\dec31_dec_sub24_rsrv[0:0] + attribute \src "libresoc.v:97121.3-97139.6" + wire $0\dec31_dec_sub24_sgl_pipe[0:0] + attribute \src "libresoc.v:97083.3-97101.6" + wire $0\dec31_dec_sub24_sgn[0:0] + attribute \src "libresoc.v:97007.3-97025.6" + wire $0\dec31_dec_sub24_sgn_ext[0:0] + attribute \src "libresoc.v:96855.3-96873.6" + wire width 2 $0\dec31_dec_sub24_upd[1:0] + attribute \src "libresoc.v:96560.7-96560.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:96912.3-96930.6" + wire width 8 $1\dec31_dec_sub24_asmcode[7:0] + attribute \src "libresoc.v:96988.3-97006.6" + wire $1\dec31_dec_sub24_br[0:0] + attribute \src "libresoc.v:97235.3-97253.6" + wire width 3 $1\dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:97254.3-97272.6" + wire width 3 $1\dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:96893.3-96911.6" + wire width 2 $1\dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:96969.3-96987.6" + wire $1\dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:97140.3-97158.6" + wire width 5 $1\dec31_dec_sub24_form[4:0] + attribute \src "libresoc.v:96817.3-96835.6" + wire width 12 $1\dec31_dec_sub24_function_unit[11:0] + attribute \src "libresoc.v:97159.3-97177.6" + wire width 3 $1\dec31_dec_sub24_in1_sel[2:0] + attribute \src "libresoc.v:97178.3-97196.6" + wire width 4 $1\dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:97197.3-97215.6" + wire width 2 $1\dec31_dec_sub24_in3_sel[1:0] + attribute \src "libresoc.v:97026.3-97044.6" + wire width 7 $1\dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:96931.3-96949.6" + wire $1\dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:96950.3-96968.6" + wire $1\dec31_dec_sub24_inv_out[0:0] + attribute \src "libresoc.v:97064.3-97082.6" + wire $1\dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:96836.3-96854.6" + wire width 4 $1\dec31_dec_sub24_ldst_len[3:0] + attribute \src "libresoc.v:97102.3-97120.6" + wire $1\dec31_dec_sub24_lk[0:0] + attribute \src "libresoc.v:97216.3-97234.6" + wire width 2 $1\dec31_dec_sub24_out_sel[1:0] + attribute \src "libresoc.v:96874.3-96892.6" + wire width 2 $1\dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:97045.3-97063.6" + wire $1\dec31_dec_sub24_rsrv[0:0] + attribute \src "libresoc.v:97121.3-97139.6" + wire $1\dec31_dec_sub24_sgl_pipe[0:0] + attribute \src "libresoc.v:97083.3-97101.6" + wire $1\dec31_dec_sub24_sgn[0:0] + attribute \src "libresoc.v:97007.3-97025.6" + wire $1\dec31_dec_sub24_sgn_ext[0:0] + attribute \src "libresoc.v:96855.3-96873.6" + wire width 2 $1\dec31_dec_sub24_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub24_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub24_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub24_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub24_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub24_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub24_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub24_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub24_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub24_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub24_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub24_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub24_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub24_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub24_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub24_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub24_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub24_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub24_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub24_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub24_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub24_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub24_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub24_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub24_upd + attribute \src "libresoc.v:96560.7-96560.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:96560.7-96560.20" + process $proc$libresoc.v:96560$4021 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:96817.3-96835.6" + process $proc$libresoc.v:96817$3997 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_function_unit[11:0] $1\dec31_dec_sub24_function_unit[11:0] + attribute \src "libresoc.v:96818.5-96818.29" + switch \initial + attribute \src "libresoc.v:96818.9-96818.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'101001 + case 5'00000 assign { } { } - assign $1\inv_a[0:0] 1'0 + assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 attribute \src "libresoc.v:0.0-0.0" - case 6'100000 + case 5'11000 assign { } { } - assign $1\inv_a[0:0] 1'0 + assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 attribute \src "libresoc.v:0.0-0.0" - case 6'100001 + case 5'11001 assign { } { } - assign $1\inv_a[0:0] 1'0 + assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 attribute \src "libresoc.v:0.0-0.0" - case 6'000111 + case 5'10000 assign { } { } - assign $1\inv_a[0:0] 1'0 + assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 + case + assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub24_function_unit $0\dec31_dec_sub24_function_unit[11:0] + end + attribute \src "libresoc.v:96836.3-96854.6" + process $proc$libresoc.v:96836$3998 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_ldst_len[3:0] $1\dec31_dec_sub24_ldst_len[3:0] + attribute \src "libresoc.v:96837.5-96837.29" + switch \initial + attribute \src "libresoc.v:96837.9-96837.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'011000 + case 5'00000 assign { } { } - assign $1\inv_a[0:0] 1'0 + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 6'011001 + case 5'11000 assign { } { } - assign $1\inv_a[0:0] 1'0 + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 6'010100 + case 5'11001 assign { } { } - assign $1\inv_a[0:0] 1'0 + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 6'010101 + case 5'10000 assign { } { } - assign $1\inv_a[0:0] 1'0 + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub24_ldst_len $0\dec31_dec_sub24_ldst_len[3:0] + end + attribute \src "libresoc.v:96855.3-96873.6" + process $proc$libresoc.v:96855$3999 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_upd[1:0] $1\dec31_dec_sub24_upd[1:0] + attribute \src "libresoc.v:96856.5-96856.29" + switch \initial + attribute \src "libresoc.v:96856.9-96856.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010111 + case 5'00000 assign { } { } - assign $1\inv_a[0:0] 1'0 + assign $1\dec31_dec_sub24_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'100110 + case 5'11000 assign { } { } - assign $1\inv_a[0:0] 1'0 + assign $1\dec31_dec_sub24_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'100111 + case 5'11001 assign { } { } - assign $1\inv_a[0:0] 1'0 + assign $1\dec31_dec_sub24_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'101100 + case 5'10000 assign { } { } - assign $1\inv_a[0:0] 1'0 + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_upd $0\dec31_dec_sub24_upd[1:0] + end + attribute \src "libresoc.v:96874.3-96892.6" + process $proc$libresoc.v:96874$4000 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_rc_sel[1:0] $1\dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:96875.5-96875.29" + switch \initial + attribute \src "libresoc.v:96875.9-96875.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'101101 + case 5'00000 assign { } { } - assign $1\inv_a[0:0] 1'0 + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 6'100100 + case 5'11000 assign { } { } - assign $1\inv_a[0:0] 1'0 + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 6'100101 + case 5'11001 assign { } { } - assign $1\inv_a[0:0] 1'0 + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 6'001000 + case 5'10000 assign { } { } - assign $1\inv_a[0:0] 1'1 + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_rc_sel $0\dec31_dec_sub24_rc_sel[1:0] + end + attribute \src "libresoc.v:96893.3-96911.6" + process $proc$libresoc.v:96893$4001 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_cry_in[1:0] $1\dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:96894.5-96894.29" + switch \initial + attribute \src "libresoc.v:96894.9-96894.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'000010 + case 5'00000 assign { } { } - assign $1\inv_a[0:0] 1'0 + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'000011 + case 5'11000 assign { } { } - assign $1\inv_a[0:0] 1'0 + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'011010 + case 5'11001 assign { } { } - assign $1\inv_a[0:0] 1'0 + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'011011 + case 5'10000 assign { } { } - assign $1\inv_a[0:0] 1'0 + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_cry_in $0\dec31_dec_sub24_cry_in[1:0] + end + attribute \src "libresoc.v:96912.3-96930.6" + process $proc$libresoc.v:96912$4002 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_asmcode[7:0] $1\dec31_dec_sub24_asmcode[7:0] + attribute \src "libresoc.v:96913.5-96913.29" + switch \initial + attribute \src "libresoc.v:96913.9-96913.17" + case 1'1 case - assign $1\inv_a[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- + case 5'00000 assign { } { } - assign $2\inv_a[0:0] 1'0 + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10011111 attribute \src "libresoc.v:0.0-0.0" - case 1610612736 + case 5'11000 assign { } { } - assign $2\inv_a[0:0] 1'0 + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100010 attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- + case 5'11001 assign { } { } - assign $2\inv_a[0:0] 1'0 + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100101 case - assign $2\inv_a[0:0] $1\inv_a[0:0] + assign $1\dec31_dec_sub24_asmcode[7:0] 8'00000000 end sync always - update \inv_a $0\inv_a[0:0] + update \dec31_dec_sub24_asmcode $0\dec31_dec_sub24_asmcode[7:0] end - attribute \src "libresoc.v:5086.3-5227.6" - process $proc$libresoc.v:5086$250 + attribute \src "libresoc.v:96931.3-96949.6" + process $proc$libresoc.v:96931$4003 assign { } { } assign { } { } - assign { } { } - assign $0\inv_out[0:0] $2\inv_out[0:0] - attribute \src "libresoc.v:5087.5-5087.29" + assign $0\dec31_dec_sub24_inv_a[0:0] $1\dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:96932.5-96932.29" switch \initial - attribute \src "libresoc.v:5087.9-5087.17" + attribute \src "libresoc.v:96932.9-96932.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\inv_out[0:0] \dec19_dec19_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 + case 5'00000 assign { } { } - assign $1\inv_out[0:0] \dec30_dec30_inv_out + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011111 + case 5'11000 assign { } { } - assign $1\inv_out[0:0] \dec31_dec31_inv_out + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'111010 + case 5'11001 assign { } { } - assign $1\inv_out[0:0] \dec58_dec58_inv_out + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'111110 + case 5'10000 assign { } { } - assign $1\inv_out[0:0] \dec62_dec62_inv_out + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_inv_a $0\dec31_dec_sub24_inv_a[0:0] + end + attribute \src "libresoc.v:96950.3-96968.6" + process $proc$libresoc.v:96950$4004 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_inv_out[0:0] $1\dec31_dec_sub24_inv_out[0:0] + attribute \src "libresoc.v:96951.5-96951.29" + switch \initial + attribute \src "libresoc.v:96951.9-96951.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'001100 + case 5'00000 assign { } { } - assign $1\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001101 + case 5'11000 assign { } { } - assign $1\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001110 + case 5'11001 assign { } { } - assign $1\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001111 + case 5'10000 assign { } { } - assign $1\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_inv_out $0\dec31_dec_sub24_inv_out[0:0] + end + attribute \src "libresoc.v:96969.3-96987.6" + process $proc$libresoc.v:96969$4005 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_cry_out[0:0] $1\dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:96970.5-96970.29" + switch \initial + attribute \src "libresoc.v:96970.9-96970.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010001 + case 5'00000 assign { } { } - assign $1\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011100 + case 5'11000 assign { } { } - assign $1\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'011101 + case 5'11001 assign { } { } - assign $1\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'010010 + case 5'10000 assign { } { } - assign $1\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_cry_out $0\dec31_dec_sub24_cry_out[0:0] + end + attribute \src "libresoc.v:96988.3-97006.6" + process $proc$libresoc.v:96988$4006 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_br[0:0] $1\dec31_dec_sub24_br[0:0] + attribute \src "libresoc.v:96989.5-96989.29" + switch \initial + attribute \src "libresoc.v:96989.9-96989.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010000 + case 5'00000 assign { } { } - assign $1\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001011 + case 5'11000 assign { } { } - assign $1\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001010 + case 5'11001 assign { } { } - assign $1\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100010 + case 5'10000 assign { } { } - assign $1\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_br[0:0] 1'0 + case + assign $1\dec31_dec_sub24_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_br $0\dec31_dec_sub24_br[0:0] + end + attribute \src "libresoc.v:97007.3-97025.6" + process $proc$libresoc.v:97007$4007 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sgn_ext[0:0] $1\dec31_dec_sub24_sgn_ext[0:0] + attribute \src "libresoc.v:97008.5-97008.29" + switch \initial + attribute \src "libresoc.v:97008.9-97008.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'100011 + case 5'00000 assign { } { } - assign $1\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101010 + case 5'11000 assign { } { } - assign $1\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101011 + case 5'11001 assign { } { } - assign $1\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101000 + case 5'10000 assign { } { } - assign $1\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_sgn_ext $0\dec31_dec_sub24_sgn_ext[0:0] + end + attribute \src "libresoc.v:97026.3-97044.6" + process $proc$libresoc.v:97026$4008 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_internal_op[6:0] $1\dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:97027.5-97027.29" + switch \initial + attribute \src "libresoc.v:97027.9-97027.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'101001 + case 5'00000 assign { } { } - assign $1\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111100 attribute \src "libresoc.v:0.0-0.0" - case 6'100000 + case 5'11000 assign { } { } - assign $1\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 attribute \src "libresoc.v:0.0-0.0" - case 6'100001 + case 5'11001 assign { } { } - assign $1\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 attribute \src "libresoc.v:0.0-0.0" - case 6'000111 + case 5'10000 assign { } { } - assign $1\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 + case + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub24_internal_op $0\dec31_dec_sub24_internal_op[6:0] + end + attribute \src "libresoc.v:97045.3-97063.6" + process $proc$libresoc.v:97045$4009 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_rsrv[0:0] $1\dec31_dec_sub24_rsrv[0:0] + attribute \src "libresoc.v:97046.5-97046.29" + switch \initial + attribute \src "libresoc.v:97046.9-97046.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'011000 + case 5'00000 assign { } { } - assign $1\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011001 + case 5'11000 assign { } { } - assign $1\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010100 + case 5'11001 assign { } { } - assign $1\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010101 + case 5'10000 assign { } { } - assign $1\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_rsrv $0\dec31_dec_sub24_rsrv[0:0] + end + attribute \src "libresoc.v:97064.3-97082.6" + process $proc$libresoc.v:97064$4010 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_is_32b[0:0] $1\dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:97065.5-97065.29" + switch \initial + attribute \src "libresoc.v:97065.9-97065.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010111 + case 5'00000 assign { } { } - assign $1\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'100110 + case 5'11000 assign { } { } - assign $1\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'100111 + case 5'11001 assign { } { } - assign $1\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'101100 + case 5'10000 assign { } { } - assign $1\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + case + assign $1\dec31_dec_sub24_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_is_32b $0\dec31_dec_sub24_is_32b[0:0] + end + attribute \src "libresoc.v:97083.3-97101.6" + process $proc$libresoc.v:97083$4011 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sgn[0:0] $1\dec31_dec_sub24_sgn[0:0] + attribute \src "libresoc.v:97084.5-97084.29" + switch \initial + attribute \src "libresoc.v:97084.9-97084.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'101101 + case 5'00000 assign { } { } - assign $1\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100100 + case 5'11000 assign { } { } - assign $1\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'100101 + case 5'11001 assign { } { } - assign $1\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'001000 + case 5'10000 assign { } { } - assign $1\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub24_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_sgn $0\dec31_dec_sub24_sgn[0:0] + end + attribute \src "libresoc.v:97102.3-97120.6" + process $proc$libresoc.v:97102$4012 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_lk[0:0] $1\dec31_dec_sub24_lk[0:0] + attribute \src "libresoc.v:97103.5-97103.29" + switch \initial + attribute \src "libresoc.v:97103.9-97103.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'000010 + case 5'00000 assign { } { } - assign $1\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'000011 + case 5'11000 assign { } { } - assign $1\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011010 + case 5'11001 assign { } { } - assign $1\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011011 + case 5'10000 assign { } { } - assign $1\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_lk $0\dec31_dec_sub24_lk[0:0] + end + attribute \src "libresoc.v:97121.3-97139.6" + process $proc$libresoc.v:97121$4013 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sgl_pipe[0:0] $1\dec31_dec_sub24_sgl_pipe[0:0] + attribute \src "libresoc.v:97122.5-97122.29" + switch \initial + attribute \src "libresoc.v:97122.9-97122.17" + case 1'1 case - assign $1\inv_out[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- + case 5'00000 assign { } { } - assign $2\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1610612736 + case 5'11000 assign { } { } - assign $2\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- + case 5'11001 assign { } { } - assign $2\inv_out[0:0] 1'0 + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 case - assign $2\inv_out[0:0] $1\inv_out[0:0] + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 end sync always - update \inv_out $0\inv_out[0:0] + update \dec31_dec_sub24_sgl_pipe $0\dec31_dec_sub24_sgl_pipe[0:0] end - attribute \src "libresoc.v:5228.3-5369.6" - process $proc$libresoc.v:5228$251 + attribute \src "libresoc.v:97140.3-97158.6" + process $proc$libresoc.v:97140$4014 assign { } { } assign { } { } - assign { } { } - assign $0\cry_out[0:0] $2\cry_out[0:0] - attribute \src "libresoc.v:5229.5-5229.29" + assign $0\dec31_dec_sub24_form[4:0] $1\dec31_dec_sub24_form[4:0] + attribute \src "libresoc.v:97141.5-97141.29" switch \initial - attribute \src "libresoc.v:5229.9-5229.17" + attribute \src "libresoc.v:97141.9-97141.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\cry_out[0:0] \dec19_dec19_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 + case 5'00000 assign { } { } - assign $1\cry_out[0:0] \dec30_dec30_cry_out + assign $1\dec31_dec_sub24_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'011111 + case 5'11000 assign { } { } - assign $1\cry_out[0:0] \dec31_dec31_cry_out + assign $1\dec31_dec_sub24_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'111010 + case 5'11001 assign { } { } - assign $1\cry_out[0:0] \dec58_dec58_cry_out + assign $1\dec31_dec_sub24_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'111110 + case 5'10000 assign { } { } - assign $1\cry_out[0:0] \dec62_dec62_cry_out + assign $1\dec31_dec_sub24_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub24_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub24_form $0\dec31_dec_sub24_form[4:0] + end + attribute \src "libresoc.v:97159.3-97177.6" + process $proc$libresoc.v:97159$4015 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_in1_sel[2:0] $1\dec31_dec_sub24_in1_sel[2:0] + attribute \src "libresoc.v:97160.5-97160.29" + switch \initial + attribute \src "libresoc.v:97160.9-97160.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'001100 + case 5'00000 assign { } { } - assign $1\cry_out[0:0] 1'1 + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'001101 + case 5'11000 assign { } { } - assign $1\cry_out[0:0] 1'1 + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'001110 + case 5'11001 assign { } { } - assign $1\cry_out[0:0] 1'0 + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'001111 + case 5'10000 assign { } { } - assign $1\cry_out[0:0] 1'0 + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_in1_sel $0\dec31_dec_sub24_in1_sel[2:0] + end + attribute \src "libresoc.v:97178.3-97196.6" + process $proc$libresoc.v:97178$4016 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_in2_sel[3:0] $1\dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:97179.5-97179.29" + switch \initial + attribute \src "libresoc.v:97179.9-97179.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010001 + case 5'00000 assign { } { } - assign $1\cry_out[0:0] 1'0 + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 6'011100 + case 5'11000 assign { } { } - assign $1\cry_out[0:0] 1'0 + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 6'011101 + case 5'11001 assign { } { } - assign $1\cry_out[0:0] 1'0 + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'1011 attribute \src "libresoc.v:0.0-0.0" - case 6'010010 + case 5'10000 assign { } { } - assign $1\cry_out[0:0] 1'0 + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub24_in2_sel $0\dec31_dec_sub24_in2_sel[3:0] + end + attribute \src "libresoc.v:97197.3-97215.6" + process $proc$libresoc.v:97197$4017 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_in3_sel[1:0] $1\dec31_dec_sub24_in3_sel[1:0] + attribute \src "libresoc.v:97198.5-97198.29" + switch \initial + attribute \src "libresoc.v:97198.9-97198.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010000 + case 5'00000 assign { } { } - assign $1\cry_out[0:0] 1'0 + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 6'001011 + case 5'11000 assign { } { } - assign $1\cry_out[0:0] 1'0 + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 6'001010 + case 5'11001 assign { } { } - assign $1\cry_out[0:0] 1'0 + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 6'100010 + case 5'10000 assign { } { } - assign $1\cry_out[0:0] 1'0 + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_in3_sel $0\dec31_dec_sub24_in3_sel[1:0] + end + attribute \src "libresoc.v:97216.3-97234.6" + process $proc$libresoc.v:97216$4018 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_out_sel[1:0] $1\dec31_dec_sub24_out_sel[1:0] + attribute \src "libresoc.v:97217.5-97217.29" + switch \initial + attribute \src "libresoc.v:97217.9-97217.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'100011 + case 5'00000 assign { } { } - assign $1\cry_out[0:0] 1'0 + assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 6'101010 + case 5'11000 assign { } { } - assign $1\cry_out[0:0] 1'0 + assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 6'101011 + case 5'11001 assign { } { } - assign $1\cry_out[0:0] 1'0 + assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 6'101000 + case 5'10000 assign { } { } - assign $1\cry_out[0:0] 1'0 + assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub24_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_out_sel $0\dec31_dec_sub24_out_sel[1:0] + end + attribute \src "libresoc.v:97235.3-97253.6" + process $proc$libresoc.v:97235$4019 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_cr_in[2:0] $1\dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:97236.5-97236.29" + switch \initial + attribute \src "libresoc.v:97236.9-97236.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'101001 + case 5'00000 assign { } { } - assign $1\cry_out[0:0] 1'0 + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'100000 + case 5'11000 assign { } { } - assign $1\cry_out[0:0] 1'0 + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'100001 + case 5'11001 assign { } { } - assign $1\cry_out[0:0] 1'0 + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'000111 + case 5'10000 assign { } { } - assign $1\cry_out[0:0] 1'0 + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_cr_in $0\dec31_dec_sub24_cr_in[2:0] + end + attribute \src "libresoc.v:97254.3-97272.6" + process $proc$libresoc.v:97254$4020 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_cr_out[2:0] $1\dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:97255.5-97255.29" + switch \initial + attribute \src "libresoc.v:97255.9-97255.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'011000 + case 5'00000 assign { } { } - assign $1\cry_out[0:0] 1'0 + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 6'011001 + case 5'11000 assign { } { } - assign $1\cry_out[0:0] 1'0 + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 6'010100 + case 5'11001 assign { } { } - assign $1\cry_out[0:0] 1'0 + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 6'010101 + case 5'10000 assign { } { } - assign $1\cry_out[0:0] 1'0 + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub24_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_cr_out $0\dec31_dec_sub24_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:97278.1-98785.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub26" +attribute \generator "nMigen" +module \dec31_dec_sub26 + attribute \src "libresoc.v:97796.3-97847.6" + wire width 8 $0\dec31_dec_sub26_asmcode[7:0] + attribute \src "libresoc.v:98004.3-98055.6" + wire $0\dec31_dec_sub26_br[0:0] + attribute \src "libresoc.v:98680.3-98731.6" + wire width 3 $0\dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:98732.3-98783.6" + wire width 3 $0\dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:97744.3-97795.6" + wire width 2 $0\dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:97952.3-98003.6" + wire $0\dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:98420.3-98471.6" + wire width 5 $0\dec31_dec_sub26_form[4:0] + attribute \src "libresoc.v:97536.3-97587.6" + wire width 12 $0\dec31_dec_sub26_function_unit[11:0] + attribute \src "libresoc.v:98472.3-98523.6" + wire width 3 $0\dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:98524.3-98575.6" + wire width 4 $0\dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:98576.3-98627.6" + wire width 2 $0\dec31_dec_sub26_in3_sel[1:0] + attribute \src "libresoc.v:98108.3-98159.6" + wire width 7 $0\dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:97848.3-97899.6" + wire $0\dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:97900.3-97951.6" + wire $0\dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:98212.3-98263.6" + wire $0\dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:97588.3-97639.6" + wire width 4 $0\dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:98316.3-98367.6" + wire $0\dec31_dec_sub26_lk[0:0] + attribute \src "libresoc.v:98628.3-98679.6" + wire width 2 $0\dec31_dec_sub26_out_sel[1:0] + attribute \src "libresoc.v:97692.3-97743.6" + wire width 2 $0\dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:98160.3-98211.6" + wire $0\dec31_dec_sub26_rsrv[0:0] + attribute \src "libresoc.v:98368.3-98419.6" + wire $0\dec31_dec_sub26_sgl_pipe[0:0] + attribute \src "libresoc.v:98264.3-98315.6" + wire $0\dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:98056.3-98107.6" + wire $0\dec31_dec_sub26_sgn_ext[0:0] + attribute \src "libresoc.v:97640.3-97691.6" + wire width 2 $0\dec31_dec_sub26_upd[1:0] + attribute \src "libresoc.v:97279.7-97279.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:97796.3-97847.6" + wire width 8 $1\dec31_dec_sub26_asmcode[7:0] + attribute \src "libresoc.v:98004.3-98055.6" + wire $1\dec31_dec_sub26_br[0:0] + attribute \src "libresoc.v:98680.3-98731.6" + wire width 3 $1\dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:98732.3-98783.6" + wire width 3 $1\dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:97744.3-97795.6" + wire width 2 $1\dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:97952.3-98003.6" + wire $1\dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:98420.3-98471.6" + wire width 5 $1\dec31_dec_sub26_form[4:0] + attribute \src "libresoc.v:97536.3-97587.6" + wire width 12 $1\dec31_dec_sub26_function_unit[11:0] + attribute \src "libresoc.v:98472.3-98523.6" + wire width 3 $1\dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:98524.3-98575.6" + wire width 4 $1\dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:98576.3-98627.6" + wire width 2 $1\dec31_dec_sub26_in3_sel[1:0] + attribute \src "libresoc.v:98108.3-98159.6" + wire width 7 $1\dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:97848.3-97899.6" + wire $1\dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:97900.3-97951.6" + wire $1\dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:98212.3-98263.6" + wire $1\dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:97588.3-97639.6" + wire width 4 $1\dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:98316.3-98367.6" + wire $1\dec31_dec_sub26_lk[0:0] + attribute \src "libresoc.v:98628.3-98679.6" + wire width 2 $1\dec31_dec_sub26_out_sel[1:0] + attribute \src "libresoc.v:97692.3-97743.6" + wire width 2 $1\dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:98160.3-98211.6" + wire $1\dec31_dec_sub26_rsrv[0:0] + attribute \src "libresoc.v:98368.3-98419.6" + wire $1\dec31_dec_sub26_sgl_pipe[0:0] + attribute \src "libresoc.v:98264.3-98315.6" + wire $1\dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:98056.3-98107.6" + wire $1\dec31_dec_sub26_sgn_ext[0:0] + attribute \src "libresoc.v:97640.3-97691.6" + wire width 2 $1\dec31_dec_sub26_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub26_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub26_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub26_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub26_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub26_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub26_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub26_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub26_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub26_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub26_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub26_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub26_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub26_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub26_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub26_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub26_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub26_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub26_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub26_upd + attribute \src "libresoc.v:97279.7-97279.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:97279.7-97279.20" + process $proc$libresoc.v:97279$4046 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:97536.3-97587.6" + process $proc$libresoc.v:97536$4022 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_function_unit[11:0] $1\dec31_dec_sub26_function_unit[11:0] + attribute \src "libresoc.v:97537.5-97537.29" + switch \initial + attribute \src "libresoc.v:97537.9-97537.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010111 + case 5'00001 assign { } { } - assign $1\cry_out[0:0] 1'0 + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 attribute \src "libresoc.v:0.0-0.0" - case 6'100110 + case 5'00000 assign { } { } - assign $1\cry_out[0:0] 1'0 + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 attribute \src "libresoc.v:0.0-0.0" - case 6'100111 + case 5'10001 assign { } { } - assign $1\cry_out[0:0] 1'0 + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 attribute \src "libresoc.v:0.0-0.0" - case 6'101100 + case 5'10000 assign { } { } - assign $1\cry_out[0:0] 1'0 + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 attribute \src "libresoc.v:0.0-0.0" - case 6'101101 + case 5'11101 assign { } { } - assign $1\cry_out[0:0] 1'0 + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010 attribute \src "libresoc.v:0.0-0.0" - case 6'100100 + case 5'11100 assign { } { } - assign $1\cry_out[0:0] 1'0 + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010 attribute \src "libresoc.v:0.0-0.0" - case 6'100101 + case 5'11110 assign { } { } - assign $1\cry_out[0:0] 1'0 + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010 attribute \src "libresoc.v:0.0-0.0" - case 6'001000 + case 5'11011 assign { } { } - assign $1\cry_out[0:0] 1'1 + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000 attribute \src "libresoc.v:0.0-0.0" - case 6'000010 + case 5'00011 assign { } { } - assign $1\cry_out[0:0] 1'0 + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 attribute \src "libresoc.v:0.0-0.0" - case 6'000011 + case 5'01111 assign { } { } - assign $1\cry_out[0:0] 1'0 + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 attribute \src "libresoc.v:0.0-0.0" - case 6'011010 + case 5'01011 assign { } { } - assign $1\cry_out[0:0] 1'0 + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 attribute \src "libresoc.v:0.0-0.0" - case 6'011011 + case 5'00101 assign { } { } - assign $1\cry_out[0:0] 1'0 - case - assign $1\cry_out[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- + case 5'00100 assign { } { } - assign $2\cry_out[0:0] 1'0 + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 attribute \src "libresoc.v:0.0-0.0" - case 1610612736 + case 5'11000 assign { } { } - assign $2\cry_out[0:0] 1'0 + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000 attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- + case 5'11001 assign { } { } - assign $2\cry_out[0:0] 1'0 + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000 case - assign $2\cry_out[0:0] $1\cry_out[0:0] + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000000 end sync always - update \cry_out $0\cry_out[0:0] + update \dec31_dec_sub26_function_unit $0\dec31_dec_sub26_function_unit[11:0] end - attribute \src "libresoc.v:5370.3-5511.6" - process $proc$libresoc.v:5370$252 - assign { } { } + attribute \src "libresoc.v:97588.3-97639.6" + process $proc$libresoc.v:97588$4023 assign { } { } assign { } { } - assign $0\br[0:0] $2\br[0:0] - attribute \src "libresoc.v:5371.5-5371.29" + assign $0\dec31_dec_sub26_ldst_len[3:0] $1\dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:97589.5-97589.29" switch \initial - attribute \src "libresoc.v:5371.9-5371.17" + attribute \src "libresoc.v:97589.9-97589.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010011 + case 5'00001 assign { } { } - assign $1\br[0:0] \dec19_dec19_br + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 6'011110 + case 5'00000 assign { } { } - assign $1\br[0:0] \dec30_dec30_br + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 6'011111 + case 5'10001 assign { } { } - assign $1\br[0:0] \dec31_dec31_br + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 6'111010 + case 5'10000 assign { } { } - assign $1\br[0:0] \dec58_dec58_br + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 6'111110 + case 5'11101 assign { } { } - assign $1\br[0:0] \dec62_dec62_br + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 6'001100 + case 5'11100 assign { } { } - assign $1\br[0:0] 1'0 + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" - case 6'001101 + case 5'11110 assign { } { } - assign $1\br[0:0] 1'0 + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" - case 6'001110 + case 5'11011 assign { } { } - assign $1\br[0:0] 1'0 + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 6'001111 + case 5'00011 assign { } { } - assign $1\br[0:0] 1'0 + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 6'010001 + case 5'01111 assign { } { } - assign $1\br[0:0] 1'0 + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" - case 6'011100 + case 5'01011 assign { } { } - assign $1\br[0:0] 1'0 + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" - case 6'011101 + case 5'00101 assign { } { } - assign $1\br[0:0] 1'0 + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" - case 6'010010 + case 5'00100 assign { } { } - assign $1\br[0:0] 1'0 + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" - case 6'010000 + case 5'11000 assign { } { } - assign $1\br[0:0] 1'0 + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 6'001011 + case 5'11001 assign { } { } - assign $1\br[0:0] 1'0 + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub26_ldst_len $0\dec31_dec_sub26_ldst_len[3:0] + end + attribute \src "libresoc.v:97640.3-97691.6" + process $proc$libresoc.v:97640$4024 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_upd[1:0] $1\dec31_dec_sub26_upd[1:0] + attribute \src "libresoc.v:97641.5-97641.29" + switch \initial + attribute \src "libresoc.v:97641.9-97641.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'001010 + case 5'00001 assign { } { } - assign $1\br[0:0] 1'0 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'100010 + case 5'00000 assign { } { } - assign $1\br[0:0] 1'0 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'100011 + case 5'10001 assign { } { } - assign $1\br[0:0] 1'0 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'101010 + case 5'10000 assign { } { } - assign $1\br[0:0] 1'0 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'101011 + case 5'11101 assign { } { } - assign $1\br[0:0] 1'0 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'101000 + case 5'11100 assign { } { } - assign $1\br[0:0] 1'0 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'101001 + case 5'11110 assign { } { } - assign $1\br[0:0] 1'0 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'100000 + case 5'11011 assign { } { } - assign $1\br[0:0] 1'0 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'100001 + case 5'00011 assign { } { } - assign $1\br[0:0] 1'0 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'000111 + case 5'01111 assign { } { } - assign $1\br[0:0] 1'0 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'011000 + case 5'01011 assign { } { } - assign $1\br[0:0] 1'0 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'011001 + case 5'00101 assign { } { } - assign $1\br[0:0] 1'0 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'010100 + case 5'00100 assign { } { } - assign $1\br[0:0] 1'0 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'010101 + case 5'11000 assign { } { } - assign $1\br[0:0] 1'0 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'010111 + case 5'11001 assign { } { } - assign $1\br[0:0] 1'0 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_upd $0\dec31_dec_sub26_upd[1:0] + end + attribute \src "libresoc.v:97692.3-97743.6" + process $proc$libresoc.v:97692$4025 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_rc_sel[1:0] $1\dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:97693.5-97693.29" + switch \initial + attribute \src "libresoc.v:97693.9-97693.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'100110 + case 5'00001 assign { } { } - assign $1\br[0:0] 1'0 + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 6'100111 + case 5'00000 assign { } { } - assign $1\br[0:0] 1'0 + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 6'101100 + case 5'10001 assign { } { } - assign $1\br[0:0] 1'0 + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 6'101101 + case 5'10000 assign { } { } - assign $1\br[0:0] 1'0 + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 6'100100 + case 5'11101 assign { } { } - assign $1\br[0:0] 1'0 + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 6'100101 + case 5'11100 assign { } { } - assign $1\br[0:0] 1'0 + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 6'001000 + case 5'11110 assign { } { } - assign $1\br[0:0] 1'0 + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 6'000010 + case 5'11011 assign { } { } - assign $1\br[0:0] 1'0 + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 6'000011 + case 5'00011 assign { } { } - assign $1\br[0:0] 1'0 + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'011010 + case 5'01111 assign { } { } - assign $1\br[0:0] 1'0 + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'011011 + case 5'01011 assign { } { } - assign $1\br[0:0] 1'0 - case - assign $1\br[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- + case 5'00101 assign { } { } - assign $2\br[0:0] 1'0 + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1610612736 + case 5'00100 assign { } { } - assign $2\br[0:0] 1'0 + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- + case 5'11000 assign { } { } - assign $2\br[0:0] 1'0 + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 case - assign $2\br[0:0] $1\br[0:0] + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 end sync always - update \br $0\br[0:0] + update \dec31_dec_sub26_rc_sel $0\dec31_dec_sub26_rc_sel[1:0] end - attribute \src "libresoc.v:5512.3-5653.6" - process $proc$libresoc.v:5512$253 - assign { } { } + attribute \src "libresoc.v:97744.3-97795.6" + process $proc$libresoc.v:97744$4026 assign { } { } assign { } { } - assign $0\sgn_ext[0:0] $2\sgn_ext[0:0] - attribute \src "libresoc.v:5513.5-5513.29" + assign $0\dec31_dec_sub26_cry_in[1:0] $1\dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:97745.5-97745.29" switch \initial - attribute \src "libresoc.v:5513.9-5513.17" + attribute \src "libresoc.v:97745.9-97745.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010011 + case 5'00001 assign { } { } - assign $1\sgn_ext[0:0] \dec19_dec19_sgn_ext + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'011110 + case 5'00000 assign { } { } - assign $1\sgn_ext[0:0] \dec30_dec30_sgn_ext + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'011111 + case 5'10001 assign { } { } - assign $1\sgn_ext[0:0] \dec31_dec31_sgn_ext + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'111010 + case 5'10000 assign { } { } - assign $1\sgn_ext[0:0] \dec58_dec58_sgn_ext + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'111110 + case 5'11101 assign { } { } - assign $1\sgn_ext[0:0] \dec62_dec62_sgn_ext + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'001100 + case 5'11100 assign { } { } - assign $1\sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'001101 + case 5'11110 assign { } { } - assign $1\sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'001110 + case 5'11011 assign { } { } - assign $1\sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'001111 + case 5'00011 assign { } { } - assign $1\sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'010001 + case 5'01111 assign { } { } - assign $1\sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'011100 + case 5'01011 assign { } { } - assign $1\sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'011101 + case 5'00101 assign { } { } - assign $1\sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'010010 + case 5'00100 assign { } { } - assign $1\sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'010000 + case 5'11000 assign { } { } - assign $1\sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'001011 + case 5'11001 assign { } { } - assign $1\sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_cry_in $0\dec31_dec_sub26_cry_in[1:0] + end + attribute \src "libresoc.v:97796.3-97847.6" + process $proc$libresoc.v:97796$4027 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_asmcode[7:0] $1\dec31_dec_sub26_asmcode[7:0] + attribute \src "libresoc.v:97797.5-97797.29" + switch \initial + attribute \src "libresoc.v:97797.9-97797.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'001010 + case 5'00001 assign { } { } - assign $1\sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100001 attribute \src "libresoc.v:0.0-0.0" - case 6'100010 + case 5'00000 assign { } { } - assign $1\sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100010 attribute \src "libresoc.v:0.0-0.0" - case 6'100011 + case 5'10001 assign { } { } - assign $1\sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100011 attribute \src "libresoc.v:0.0-0.0" - case 6'101010 + case 5'10000 assign { } { } - assign $1\sgn_ext[0:0] 1'1 + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100100 attribute \src "libresoc.v:0.0-0.0" - case 6'101011 + case 5'11101 assign { } { } - assign $1\sgn_ext[0:0] 1'1 + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000100 attribute \src "libresoc.v:0.0-0.0" - case 6'101000 + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 assign { } { } - assign $1\sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000110 attribute \src "libresoc.v:0.0-0.0" - case 6'101001 + case 5'11011 assign { } { } - assign $1\sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000111 attribute \src "libresoc.v:0.0-0.0" - case 6'100000 + case 5'00011 assign { } { } - assign $1\sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001100 attribute \src "libresoc.v:0.0-0.0" - case 6'100001 + case 5'01111 assign { } { } - assign $1\sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001101 attribute \src "libresoc.v:0.0-0.0" - case 6'000111 + case 5'01011 assign { } { } - assign $1\sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001110 attribute \src "libresoc.v:0.0-0.0" - case 6'011000 + case 5'00101 assign { } { } - assign $1\sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001111 attribute \src "libresoc.v:0.0-0.0" - case 6'011001 + case 5'00100 assign { } { } - assign $1\sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10010000 attribute \src "libresoc.v:0.0-0.0" - case 6'010100 + case 5'11000 assign { } { } - assign $1\sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10100000 attribute \src "libresoc.v:0.0-0.0" - case 6'010101 + case 5'11001 assign { } { } - assign $1\sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10100001 + case + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub26_asmcode $0\dec31_dec_sub26_asmcode[7:0] + end + attribute \src "libresoc.v:97848.3-97899.6" + process $proc$libresoc.v:97848$4028 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_inv_a[0:0] $1\dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:97849.5-97849.29" + switch \initial + attribute \src "libresoc.v:97849.9-97849.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010111 + case 5'00001 assign { } { } - assign $1\sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100110 + case 5'00000 assign { } { } - assign $1\sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100111 + case 5'10001 assign { } { } - assign $1\sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101100 + case 5'10000 assign { } { } - assign $1\sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101101 + case 5'11101 assign { } { } - assign $1\sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100100 + case 5'11100 assign { } { } - assign $1\sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100101 + case 5'11110 assign { } { } - assign $1\sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001000 + case 5'11011 assign { } { } - assign $1\sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'000010 + case 5'00011 assign { } { } - assign $1\sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'000011 + case 5'01111 assign { } { } - assign $1\sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011010 + case 5'01011 assign { } { } - assign $1\sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011011 + case 5'00101 assign { } { } - assign $1\sgn_ext[0:0] 1'0 - case - assign $1\sgn_ext[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- + case 5'00100 assign { } { } - assign $2\sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1610612736 + case 5'11000 assign { } { } - assign $2\sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- + case 5'11001 assign { } { } - assign $2\sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 case - assign $2\sgn_ext[0:0] $1\sgn_ext[0:0] + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 end sync always - update \sgn_ext $0\sgn_ext[0:0] + update \dec31_dec_sub26_inv_a $0\dec31_dec_sub26_inv_a[0:0] end - attribute \src "libresoc.v:5654.3-5795.6" - process $proc$libresoc.v:5654$254 - assign { } { } + attribute \src "libresoc.v:97900.3-97951.6" + process $proc$libresoc.v:97900$4029 assign { } { } assign { } { } - assign $0\rsrv[0:0] $2\rsrv[0:0] - attribute \src "libresoc.v:5655.5-5655.29" + assign $0\dec31_dec_sub26_inv_out[0:0] $1\dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:97901.5-97901.29" switch \initial - attribute \src "libresoc.v:5655.9-5655.17" + attribute \src "libresoc.v:97901.9-97901.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010011 + case 5'00001 assign { } { } - assign $1\rsrv[0:0] \dec19_dec19_rsrv + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011110 + case 5'00000 assign { } { } - assign $1\rsrv[0:0] \dec30_dec30_rsrv + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011111 + case 5'10001 assign { } { } - assign $1\rsrv[0:0] \dec31_dec31_rsrv + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'111010 + case 5'10000 assign { } { } - assign $1\rsrv[0:0] \dec58_dec58_rsrv + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'111110 + case 5'11101 assign { } { } - assign $1\rsrv[0:0] \dec62_dec62_rsrv + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001100 + case 5'11100 assign { } { } - assign $1\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001101 + case 5'11110 assign { } { } - assign $1\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001110 + case 5'11011 assign { } { } - assign $1\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001111 + case 5'00011 assign { } { } - assign $1\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010001 + case 5'01111 assign { } { } - assign $1\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011100 + case 5'01011 assign { } { } - assign $1\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011101 + case 5'00101 assign { } { } - assign $1\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010010 + case 5'00100 assign { } { } - assign $1\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010000 + case 5'11000 assign { } { } - assign $1\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001011 + case 5'11001 assign { } { } - assign $1\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_inv_out $0\dec31_dec_sub26_inv_out[0:0] + end + attribute \src "libresoc.v:97952.3-98003.6" + process $proc$libresoc.v:97952$4030 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_cry_out[0:0] $1\dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:97953.5-97953.29" + switch \initial + attribute \src "libresoc.v:97953.9-97953.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'001010 + case 5'00001 assign { } { } - assign $1\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100010 + case 5'00000 assign { } { } - assign $1\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100011 + case 5'10001 assign { } { } - assign $1\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101010 + case 5'10000 assign { } { } - assign $1\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101011 + case 5'11101 assign { } { } - assign $1\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101000 + case 5'11100 assign { } { } - assign $1\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101001 + case 5'11110 assign { } { } - assign $1\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100000 + case 5'11011 assign { } { } - assign $1\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100001 + case 5'00011 assign { } { } - assign $1\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'000111 + case 5'01111 assign { } { } - assign $1\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011000 + case 5'01011 assign { } { } - assign $1\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011001 + case 5'00101 assign { } { } - assign $1\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010100 + case 5'00100 assign { } { } - assign $1\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010101 + case 5'11000 assign { } { } - assign $1\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'010111 + case 5'11001 assign { } { } - assign $1\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_cry_out[0:0] 1'1 + case + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_cry_out $0\dec31_dec_sub26_cry_out[0:0] + end + attribute \src "libresoc.v:98004.3-98055.6" + process $proc$libresoc.v:98004$4031 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_br[0:0] $1\dec31_dec_sub26_br[0:0] + attribute \src "libresoc.v:98005.5-98005.29" + switch \initial + attribute \src "libresoc.v:98005.9-98005.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'100110 + case 5'00001 assign { } { } - assign $1\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100111 + case 5'00000 assign { } { } - assign $1\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101100 + case 5'10001 assign { } { } - assign $1\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101101 + case 5'10000 assign { } { } - assign $1\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100100 + case 5'11101 assign { } { } - assign $1\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100101 + case 5'11100 assign { } { } - assign $1\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001000 + case 5'11110 assign { } { } - assign $1\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'000010 + case 5'11011 assign { } { } - assign $1\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'000011 + case 5'00011 assign { } { } - assign $1\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011010 + case 5'01111 assign { } { } - assign $1\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011011 + case 5'01011 assign { } { } - assign $1\rsrv[0:0] 1'0 - case - assign $1\rsrv[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 + assign $1\dec31_dec_sub26_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- + case 5'00101 assign { } { } - assign $2\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1610612736 + case 5'00100 assign { } { } - assign $2\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- + case 5'11000 assign { } { } - assign $2\rsrv[0:0] 1'0 + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 case - assign $2\rsrv[0:0] $1\rsrv[0:0] + assign $1\dec31_dec_sub26_br[0:0] 1'0 end sync always - update \rsrv $0\rsrv[0:0] + update \dec31_dec_sub26_br $0\dec31_dec_sub26_br[0:0] end - attribute \src "libresoc.v:5796.3-5937.6" - process $proc$libresoc.v:5796$255 - assign { } { } + attribute \src "libresoc.v:98056.3-98107.6" + process $proc$libresoc.v:98056$4032 assign { } { } assign { } { } - assign $0\is_32b[0:0] $2\is_32b[0:0] - attribute \src "libresoc.v:5797.5-5797.29" + assign $0\dec31_dec_sub26_sgn_ext[0:0] $1\dec31_dec_sub26_sgn_ext[0:0] + attribute \src "libresoc.v:98057.5-98057.29" switch \initial - attribute \src "libresoc.v:5797.9-5797.17" + attribute \src "libresoc.v:98057.9-98057.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010011 + case 5'00001 assign { } { } - assign $1\is_32b[0:0] \dec19_dec19_is_32b + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011110 + case 5'00000 assign { } { } - assign $1\is_32b[0:0] \dec30_dec30_is_32b + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011111 + case 5'10001 assign { } { } - assign $1\is_32b[0:0] \dec31_dec31_is_32b + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'111010 + case 5'10000 assign { } { } - assign $1\is_32b[0:0] \dec58_dec58_is_32b + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'111110 + case 5'11101 assign { } { } - assign $1\is_32b[0:0] \dec62_dec62_is_32b + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001100 + case 5'11100 assign { } { } - assign $1\is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001101 + case 5'11110 assign { } { } - assign $1\is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001110 + case 5'11011 assign { } { } - assign $1\is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001111 + case 5'00011 assign { } { } - assign $1\is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010001 + case 5'01111 assign { } { } - assign $1\is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011100 + case 5'01011 assign { } { } - assign $1\is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011101 + case 5'00101 assign { } { } - assign $1\is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010010 + case 5'00100 assign { } { } - assign $1\is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010000 + case 5'11000 assign { } { } - assign $1\is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001011 + case 5'11001 assign { } { } - assign $1\is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_sgn_ext $0\dec31_dec_sub26_sgn_ext[0:0] + end + attribute \src "libresoc.v:98108.3-98159.6" + process $proc$libresoc.v:98108$4033 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_internal_op[6:0] $1\dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:98109.5-98109.29" + switch \initial + attribute \src "libresoc.v:98109.9-98109.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'001010 + case 5'00001 assign { } { } - assign $1\is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 attribute \src "libresoc.v:0.0-0.0" - case 6'100010 + case 5'00000 assign { } { } - assign $1\is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 attribute \src "libresoc.v:0.0-0.0" - case 6'100011 + case 5'10001 assign { } { } - assign $1\is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 attribute \src "libresoc.v:0.0-0.0" - case 6'101010 + case 5'10000 assign { } { } - assign $1\is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 attribute \src "libresoc.v:0.0-0.0" - case 6'101011 + case 5'11101 assign { } { } - assign $1\is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 attribute \src "libresoc.v:0.0-0.0" - case 6'101000 + case 5'11100 assign { } { } - assign $1\is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 attribute \src "libresoc.v:0.0-0.0" - case 6'101001 + case 5'11110 assign { } { } - assign $1\is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 attribute \src "libresoc.v:0.0-0.0" - case 6'100000 + case 5'11011 assign { } { } - assign $1\is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0100000 attribute \src "libresoc.v:0.0-0.0" - case 6'100001 + case 5'00011 assign { } { } - assign $1\is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 attribute \src "libresoc.v:0.0-0.0" - case 6'000111 + case 5'01111 assign { } { } - assign $1\is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 attribute \src "libresoc.v:0.0-0.0" - case 6'011000 + case 5'01011 assign { } { } - assign $1\is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 attribute \src "libresoc.v:0.0-0.0" - case 6'011001 + case 5'00101 assign { } { } - assign $1\is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 attribute \src "libresoc.v:0.0-0.0" - case 6'010100 + case 5'00100 assign { } { } - assign $1\is_32b[0:0] 1'1 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 attribute \src "libresoc.v:0.0-0.0" - case 6'010101 + case 5'11000 assign { } { } - assign $1\is_32b[0:0] 1'1 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 attribute \src "libresoc.v:0.0-0.0" - case 6'010111 + case 5'11001 assign { } { } - assign $1\is_32b[0:0] 1'1 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 + case + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub26_internal_op $0\dec31_dec_sub26_internal_op[6:0] + end + attribute \src "libresoc.v:98160.3-98211.6" + process $proc$libresoc.v:98160$4034 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_rsrv[0:0] $1\dec31_dec_sub26_rsrv[0:0] + attribute \src "libresoc.v:98161.5-98161.29" + switch \initial + attribute \src "libresoc.v:98161.9-98161.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'100110 + case 5'00001 assign { } { } - assign $1\is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100111 + case 5'00000 assign { } { } - assign $1\is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101100 + case 5'10001 assign { } { } - assign $1\is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101101 + case 5'10000 assign { } { } - assign $1\is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100100 + case 5'11101 assign { } { } - assign $1\is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100101 + case 5'11100 assign { } { } - assign $1\is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001000 + case 5'11110 assign { } { } - assign $1\is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'000010 + case 5'11011 assign { } { } - assign $1\is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'000011 + case 5'00011 assign { } { } - assign $1\is_32b[0:0] 1'1 + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011010 + case 5'01111 assign { } { } - assign $1\is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011011 + case 5'01011 assign { } { } - assign $1\is_32b[0:0] 1'0 - case - assign $1\is_32b[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- + case 5'00101 assign { } { } - assign $2\is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1610612736 + case 5'00100 assign { } { } - assign $2\is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- + case 5'11000 assign { } { } - assign $2\is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 case - assign $2\is_32b[0:0] $1\is_32b[0:0] + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 end sync always - update \is_32b $0\is_32b[0:0] + update \dec31_dec_sub26_rsrv $0\dec31_dec_sub26_rsrv[0:0] end - attribute \src "libresoc.v:5938.3-6079.6" - process $proc$libresoc.v:5938$256 - assign { } { } + attribute \src "libresoc.v:98212.3-98263.6" + process $proc$libresoc.v:98212$4035 assign { } { } assign { } { } - assign $0\sgn[0:0] $2\sgn[0:0] - attribute \src "libresoc.v:5939.5-5939.29" + assign $0\dec31_dec_sub26_is_32b[0:0] $1\dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:98213.5-98213.29" switch \initial - attribute \src "libresoc.v:5939.9-5939.17" + attribute \src "libresoc.v:98213.9-98213.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010011 + case 5'00001 assign { } { } - assign $1\sgn[0:0] \dec19_dec19_sgn + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011110 + case 5'00000 assign { } { } - assign $1\sgn[0:0] \dec30_dec30_sgn + assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'011111 + case 5'10001 assign { } { } - assign $1\sgn[0:0] \dec31_dec31_sgn + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'111010 + case 5'10000 assign { } { } - assign $1\sgn[0:0] \dec58_dec58_sgn + assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'111110 + case 5'11101 assign { } { } - assign $1\sgn[0:0] \dec62_dec62_sgn + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001100 + case 5'11100 assign { } { } - assign $1\sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001101 + case 5'11110 assign { } { } - assign $1\sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001110 + case 5'11011 assign { } { } - assign $1\sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001111 + case 5'00011 assign { } { } - assign $1\sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010001 + case 5'01111 assign { } { } - assign $1\sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011100 + case 5'01011 assign { } { } - assign $1\sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011101 + case 5'00101 assign { } { } - assign $1\sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010010 + case 5'00100 assign { } { } - assign $1\sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010000 + case 5'11000 assign { } { } - assign $1\sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001011 + case 5'11001 assign { } { } - assign $1\sgn[0:0] 1'1 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_is_32b $0\dec31_dec_sub26_is_32b[0:0] + end + attribute \src "libresoc.v:98264.3-98315.6" + process $proc$libresoc.v:98264$4036 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sgn[0:0] $1\dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:98265.5-98265.29" + switch \initial + attribute \src "libresoc.v:98265.9-98265.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'001010 + case 5'00001 assign { } { } - assign $1\sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100010 + case 5'00000 assign { } { } - assign $1\sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100011 + case 5'10001 assign { } { } - assign $1\sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101010 + case 5'10000 assign { } { } - assign $1\sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101011 + case 5'11101 assign { } { } - assign $1\sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101000 + case 5'11100 assign { } { } - assign $1\sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101001 + case 5'11110 assign { } { } - assign $1\sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100000 + case 5'11011 assign { } { } - assign $1\sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100001 + case 5'00011 assign { } { } - assign $1\sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'000111 + case 5'01111 assign { } { } - assign $1\sgn[0:0] 1'1 + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011000 + case 5'01011 assign { } { } - assign $1\sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011001 + case 5'00101 assign { } { } - assign $1\sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010100 + case 5'00100 assign { } { } - assign $1\sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010101 + case 5'11000 assign { } { } - assign $1\sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'010111 + case 5'11001 assign { } { } - assign $1\sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_sgn[0:0] 1'1 + case + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_sgn $0\dec31_dec_sub26_sgn[0:0] + end + attribute \src "libresoc.v:98316.3-98367.6" + process $proc$libresoc.v:98316$4037 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_lk[0:0] $1\dec31_dec_sub26_lk[0:0] + attribute \src "libresoc.v:98317.5-98317.29" + switch \initial + attribute \src "libresoc.v:98317.9-98317.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'100110 + case 5'00001 assign { } { } - assign $1\sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100111 + case 5'00000 assign { } { } - assign $1\sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101100 + case 5'10001 assign { } { } - assign $1\sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101101 + case 5'10000 assign { } { } - assign $1\sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100100 + case 5'11101 assign { } { } - assign $1\sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100101 + case 5'11100 assign { } { } - assign $1\sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001000 + case 5'11110 assign { } { } - assign $1\sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'000010 + case 5'11011 assign { } { } - assign $1\sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'000011 + case 5'00011 assign { } { } - assign $1\sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011010 + case 5'01111 assign { } { } - assign $1\sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011011 + case 5'01011 assign { } { } - assign $1\sgn[0:0] 1'0 - case - assign $1\sgn[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 + assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- + case 5'00101 assign { } { } - assign $2\sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1610612736 + case 5'00100 assign { } { } - assign $2\sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- + case 5'11000 assign { } { } - assign $2\sgn[0:0] 1'0 + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 case - assign $2\sgn[0:0] $1\sgn[0:0] + assign $1\dec31_dec_sub26_lk[0:0] 1'0 end sync always - update \sgn $0\sgn[0:0] + update \dec31_dec_sub26_lk $0\dec31_dec_sub26_lk[0:0] end - attribute \src "libresoc.v:6080.3-6221.6" - process $proc$libresoc.v:6080$257 - assign { } { } + attribute \src "libresoc.v:98368.3-98419.6" + process $proc$libresoc.v:98368$4038 assign { } { } assign { } { } - assign $0\lk[0:0] $2\lk[0:0] - attribute \src "libresoc.v:6081.5-6081.29" + assign $0\dec31_dec_sub26_sgl_pipe[0:0] $1\dec31_dec_sub26_sgl_pipe[0:0] + attribute \src "libresoc.v:98369.5-98369.29" switch \initial - attribute \src "libresoc.v:6081.9-6081.17" + attribute \src "libresoc.v:98369.9-98369.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010011 + case 5'00001 assign { } { } - assign $1\lk[0:0] \dec19_dec19_lk + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011110 + case 5'00000 assign { } { } - assign $1\lk[0:0] \dec30_dec30_lk + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011111 + case 5'10001 assign { } { } - assign $1\lk[0:0] \dec31_dec31_lk + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'111010 + case 5'10000 assign { } { } - assign $1\lk[0:0] \dec58_dec58_lk + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'111110 + case 5'11101 assign { } { } - assign $1\lk[0:0] \dec62_dec62_lk + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001100 + case 5'11100 assign { } { } - assign $1\lk[0:0] 1'0 + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001101 + case 5'11110 assign { } { } - assign $1\lk[0:0] 1'0 + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001110 + case 5'11011 assign { } { } - assign $1\lk[0:0] 1'0 + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001111 + case 5'00011 assign { } { } - assign $1\lk[0:0] 1'0 + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010001 + case 5'01111 assign { } { } - assign $1\lk[0:0] 1'0 + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011100 + case 5'01011 assign { } { } - assign $1\lk[0:0] 1'0 + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011101 + case 5'00101 assign { } { } - assign $1\lk[0:0] 1'0 + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010010 + case 5'00100 assign { } { } - assign $1\lk[0:0] 1'1 + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010000 + case 5'11000 assign { } { } - assign $1\lk[0:0] 1'1 + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001011 + case 5'11001 assign { } { } - assign $1\lk[0:0] 1'0 + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_sgl_pipe $0\dec31_dec_sub26_sgl_pipe[0:0] + end + attribute \src "libresoc.v:98420.3-98471.6" + process $proc$libresoc.v:98420$4039 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_form[4:0] $1\dec31_dec_sub26_form[4:0] + attribute \src "libresoc.v:98421.5-98421.29" + switch \initial + attribute \src "libresoc.v:98421.9-98421.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'001010 + case 5'00001 assign { } { } - assign $1\lk[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'100010 + case 5'00000 assign { } { } - assign $1\lk[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'100011 + case 5'10001 assign { } { } - assign $1\lk[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'101010 + case 5'10000 assign { } { } - assign $1\lk[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'101011 + case 5'11101 assign { } { } - assign $1\lk[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'101000 + case 5'11100 assign { } { } - assign $1\lk[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'101001 + case 5'11110 assign { } { } - assign $1\lk[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'100000 + case 5'11011 assign { } { } - assign $1\lk[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'10000 attribute \src "libresoc.v:0.0-0.0" - case 6'100001 + case 5'00011 assign { } { } - assign $1\lk[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'000111 + case 5'01111 assign { } { } - assign $1\lk[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'011000 + case 5'01011 assign { } { } - assign $1\lk[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'011001 + case 5'00101 assign { } { } - assign $1\lk[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'010100 + case 5'00100 assign { } { } - assign $1\lk[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'010101 + case 5'11000 assign { } { } - assign $1\lk[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'010111 + case 5'11001 assign { } { } - assign $1\lk[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'10000 + case + assign $1\dec31_dec_sub26_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub26_form $0\dec31_dec_sub26_form[4:0] + end + attribute \src "libresoc.v:98472.3-98523.6" + process $proc$libresoc.v:98472$4040 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_in1_sel[2:0] $1\dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:98473.5-98473.29" + switch \initial + attribute \src "libresoc.v:98473.9-98473.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'100110 + case 5'00001 assign { } { } - assign $1\lk[0:0] 1'0 + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" - case 6'100111 + case 5'00000 assign { } { } - assign $1\lk[0:0] 1'0 + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" - case 6'101100 + case 5'10001 assign { } { } - assign $1\lk[0:0] 1'0 + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" - case 6'101101 + case 5'10000 assign { } { } - assign $1\lk[0:0] 1'0 + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" - case 6'100100 + case 5'11101 assign { } { } - assign $1\lk[0:0] 1'0 + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" - case 6'100101 + case 5'11100 assign { } { } - assign $1\lk[0:0] 1'0 + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" - case 6'001000 + case 5'11110 assign { } { } - assign $1\lk[0:0] 1'0 + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" - case 6'000010 + case 5'11011 assign { } { } - assign $1\lk[0:0] 1'0 + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'000011 + case 5'00011 assign { } { } - assign $1\lk[0:0] 1'0 + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" - case 6'011010 + case 5'01111 assign { } { } - assign $1\lk[0:0] 1'0 + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" - case 6'011011 + case 5'01011 assign { } { } - assign $1\lk[0:0] 1'0 - case - assign $1\lk[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- + case 5'00101 assign { } { } - assign $2\lk[0:0] 1'0 + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" - case 1610612736 + case 5'00100 assign { } { } - assign $2\lk[0:0] 1'0 + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- + case 5'11000 assign { } { } - assign $2\lk[0:0] 1'0 + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 case - assign $2\lk[0:0] $1\lk[0:0] + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 end sync always - update \lk $0\lk[0:0] + update \dec31_dec_sub26_in1_sel $0\dec31_dec_sub26_in1_sel[2:0] end - attribute \src "libresoc.v:6222.3-6363.6" - process $proc$libresoc.v:6222$258 - assign { } { } + attribute \src "libresoc.v:98524.3-98575.6" + process $proc$libresoc.v:98524$4041 assign { } { } assign { } { } - assign $0\sgl_pipe[0:0] $2\sgl_pipe[0:0] - attribute \src "libresoc.v:6223.5-6223.29" + assign $0\dec31_dec_sub26_in2_sel[3:0] $1\dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:98525.5-98525.29" switch \initial - attribute \src "libresoc.v:6223.9-6223.17" + attribute \src "libresoc.v:98525.9-98525.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010011 + case 5'00001 assign { } { } - assign $1\sgl_pipe[0:0] \dec19_dec19_sgl_pipe + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 6'011110 + case 5'00000 assign { } { } - assign $1\sgl_pipe[0:0] \dec30_dec30_sgl_pipe + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 6'011111 + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\sgl_pipe[0:0] \dec31_dec31_sgl_pipe + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 6'111010 + case 5'11101 assign { } { } - assign $1\sgl_pipe[0:0] \dec58_dec58_sgl_pipe + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 6'111110 + case 5'11100 assign { } { } - assign $1\sgl_pipe[0:0] \dec62_dec62_sgl_pipe + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 6'001100 + case 5'11110 assign { } { } - assign $1\sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 6'001101 + case 5'11011 assign { } { } - assign $1\sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'1010 attribute \src "libresoc.v:0.0-0.0" - case 6'001110 + case 5'00011 assign { } { } - assign $1\sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 6'001111 + case 5'01111 assign { } { } - assign $1\sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 6'010001 + case 5'01011 assign { } { } - assign $1\sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 6'011100 + case 5'00101 assign { } { } - assign $1\sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 6'011101 + case 5'00100 assign { } { } - assign $1\sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 6'010010 + case 5'11000 assign { } { } - assign $1\sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 6'010000 + case 5'11001 assign { } { } - assign $1\sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'1010 + case + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub26_in2_sel $0\dec31_dec_sub26_in2_sel[3:0] + end + attribute \src "libresoc.v:98576.3-98627.6" + process $proc$libresoc.v:98576$4042 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_in3_sel[1:0] $1\dec31_dec_sub26_in3_sel[1:0] + attribute \src "libresoc.v:98577.5-98577.29" + switch \initial + attribute \src "libresoc.v:98577.9-98577.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'001011 + case 5'00001 assign { } { } - assign $1\sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'001010 + case 5'00000 assign { } { } - assign $1\sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'100010 + case 5'10001 assign { } { } - assign $1\sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'100011 + case 5'10000 assign { } { } - assign $1\sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'101010 + case 5'11101 assign { } { } - assign $1\sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'101011 + case 5'11100 assign { } { } - assign $1\sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'101000 + case 5'11110 assign { } { } - assign $1\sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'101001 + case 5'11011 assign { } { } - assign $1\sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 6'100000 + case 5'00011 assign { } { } - assign $1\sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'100001 + case 5'01111 assign { } { } - assign $1\sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'000111 + case 5'01011 assign { } { } - assign $1\sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'011000 + case 5'00101 assign { } { } - assign $1\sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'011001 + case 5'00100 assign { } { } - assign $1\sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'010100 + case 5'11000 assign { } { } - assign $1\sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 6'010101 + case 5'11001 assign { } { } - assign $1\sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_in3_sel $0\dec31_dec_sub26_in3_sel[1:0] + end + attribute \src "libresoc.v:98628.3-98679.6" + process $proc$libresoc.v:98628$4043 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_out_sel[1:0] $1\dec31_dec_sub26_out_sel[1:0] + attribute \src "libresoc.v:98629.5-98629.29" + switch \initial + attribute \src "libresoc.v:98629.9-98629.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010111 + case 5'00001 assign { } { } - assign $1\sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 6'100110 + case 5'00000 assign { } { } - assign $1\sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 6'100111 + case 5'10001 assign { } { } - assign $1\sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 6'101100 + case 5'10000 assign { } { } - assign $1\sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 6'101101 + case 5'11101 assign { } { } - assign $1\sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 6'100100 + case 5'11100 assign { } { } - assign $1\sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 6'100101 + case 5'11110 assign { } { } - assign $1\sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 6'001000 + case 5'11011 assign { } { } - assign $1\sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 6'000010 + case 5'00011 assign { } { } - assign $1\sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 6'000011 + case 5'01111 assign { } { } - assign $1\sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 6'011010 + case 5'01011 assign { } { } - assign $1\sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 6'011011 + case 5'00101 assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - case - assign $1\sgl_pipe[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- + case 5'00100 assign { } { } - assign $2\sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 1610612736 + case 5'11000 assign { } { } - assign $2\sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- + case 5'11001 assign { } { } - assign $2\sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 case - assign $2\sgl_pipe[0:0] $1\sgl_pipe[0:0] + assign $1\dec31_dec_sub26_out_sel[1:0] 2'00 end sync always - update \sgl_pipe $0\sgl_pipe[0:0] + update \dec31_dec_sub26_out_sel $0\dec31_dec_sub26_out_sel[1:0] end - attribute \src "libresoc.v:6364.3-6505.6" - process $proc$libresoc.v:6364$259 - assign { } { } + attribute \src "libresoc.v:98680.3-98731.6" + process $proc$libresoc.v:98680$4044 assign { } { } assign { } { } - assign $0\function_unit[11:0] $2\function_unit[11:0] - attribute \src "libresoc.v:6365.5-6365.29" + assign $0\dec31_dec_sub26_cr_in[2:0] $1\dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:98681.5-98681.29" switch \initial - attribute \src "libresoc.v:6365.9-6365.17" + attribute \src "libresoc.v:98681.9-98681.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\function_unit[11:0] \dec19_dec19_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\function_unit[11:0] \dec30_dec30_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\function_unit[11:0] \dec31_dec31_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\function_unit[11:0] \dec58_dec58_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\function_unit[11:0] \dec62_dec62_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 + case 5'00001 assign { } { } - assign $1\function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'001111 + case 5'00000 assign { } { } - assign $1\function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'010001 + case 5'10001 assign { } { } - assign $1\function_unit[11:0] 12'000010000000 + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'011100 + case 5'10000 assign { } { } - assign $1\function_unit[11:0] 12'000000010000 + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'011101 + case 5'11101 assign { } { } - assign $1\function_unit[11:0] 12'000000010000 + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'010010 + case 5'11100 assign { } { } - assign $1\function_unit[11:0] 12'000000100000 + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'010000 + case 5'11110 assign { } { } - assign $1\function_unit[11:0] 12'000000100000 + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'001011 + case 5'11011 assign { } { } - assign $1\function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'001010 + case 5'00011 assign { } { } - assign $1\function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'100010 + case 5'01111 assign { } { } - assign $1\function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'100011 + case 5'01011 assign { } { } - assign $1\function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'101010 + case 5'00101 assign { } { } - assign $1\function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'101011 + case 5'00100 assign { } { } - assign $1\function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'101000 + case 5'11000 assign { } { } - assign $1\function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'101001 + case 5'11001 assign { } { } - assign $1\function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_cr_in $0\dec31_dec_sub26_cr_in[2:0] + end + attribute \src "libresoc.v:98732.3-98783.6" + process $proc$libresoc.v:98732$4045 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_cr_out[2:0] $1\dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:98733.5-98733.29" + switch \initial + attribute \src "libresoc.v:98733.9-98733.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'100000 + case 5'00001 assign { } { } - assign $1\function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 6'100001 + case 5'00000 assign { } { } - assign $1\function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 6'000111 + case 5'10001 assign { } { } - assign $1\function_unit[11:0] 12'000100000000 + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 6'011000 + case 5'10000 assign { } { } - assign $1\function_unit[11:0] 12'000000010000 + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 6'011001 + case 5'11101 assign { } { } - assign $1\function_unit[11:0] 12'000000010000 + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 6'010100 + case 5'11100 assign { } { } - assign $1\function_unit[11:0] 12'000000001000 + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 6'010101 + case 5'11110 assign { } { } - assign $1\function_unit[11:0] 12'000000001000 + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 6'010111 + case 5'11011 assign { } { } - assign $1\function_unit[11:0] 12'000000001000 + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 6'100110 + case 5'00011 assign { } { } - assign $1\function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'100111 + case 5'01111 assign { } { } - assign $1\function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'101100 + case 5'01011 assign { } { } - assign $1\function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'101101 + case 5'00101 assign { } { } - assign $1\function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'100100 + case 5'00100 assign { } { } - assign $1\function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'100101 + case 5'11000 assign { } { } - assign $1\function_unit[11:0] 12'000000000100 + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 6'001000 + case 5'11001 assign { } { } - assign $1\function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_cr_out $0\dec31_dec_sub26_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:98789.1-99504.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub27" +attribute \generator "nMigen" +module \dec31_dec_sub27 + attribute \src "libresoc.v:99142.3-99160.6" + wire width 8 $0\dec31_dec_sub27_asmcode[7:0] + attribute \src "libresoc.v:99218.3-99236.6" + wire $0\dec31_dec_sub27_br[0:0] + attribute \src "libresoc.v:99465.3-99483.6" + wire width 3 $0\dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:99484.3-99502.6" + wire width 3 $0\dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:99123.3-99141.6" + wire width 2 $0\dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:99199.3-99217.6" + wire $0\dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:99370.3-99388.6" + wire width 5 $0\dec31_dec_sub27_form[4:0] + attribute \src "libresoc.v:99047.3-99065.6" + wire width 12 $0\dec31_dec_sub27_function_unit[11:0] + attribute \src "libresoc.v:99389.3-99407.6" + wire width 3 $0\dec31_dec_sub27_in1_sel[2:0] + attribute \src "libresoc.v:99408.3-99426.6" + wire width 4 $0\dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:99427.3-99445.6" + wire width 2 $0\dec31_dec_sub27_in3_sel[1:0] + attribute \src "libresoc.v:99256.3-99274.6" + wire width 7 $0\dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:99161.3-99179.6" + wire $0\dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:99180.3-99198.6" + wire $0\dec31_dec_sub27_inv_out[0:0] + attribute \src "libresoc.v:99294.3-99312.6" + wire $0\dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:99066.3-99084.6" + wire width 4 $0\dec31_dec_sub27_ldst_len[3:0] + attribute \src "libresoc.v:99332.3-99350.6" + wire $0\dec31_dec_sub27_lk[0:0] + attribute \src "libresoc.v:99446.3-99464.6" + wire width 2 $0\dec31_dec_sub27_out_sel[1:0] + attribute \src "libresoc.v:99104.3-99122.6" + wire width 2 $0\dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:99275.3-99293.6" + wire $0\dec31_dec_sub27_rsrv[0:0] + attribute \src "libresoc.v:99351.3-99369.6" + wire $0\dec31_dec_sub27_sgl_pipe[0:0] + attribute \src "libresoc.v:99313.3-99331.6" + wire $0\dec31_dec_sub27_sgn[0:0] + attribute \src "libresoc.v:99237.3-99255.6" + wire $0\dec31_dec_sub27_sgn_ext[0:0] + attribute \src "libresoc.v:99085.3-99103.6" + wire width 2 $0\dec31_dec_sub27_upd[1:0] + attribute \src "libresoc.v:98790.7-98790.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:99142.3-99160.6" + wire width 8 $1\dec31_dec_sub27_asmcode[7:0] + attribute \src "libresoc.v:99218.3-99236.6" + wire $1\dec31_dec_sub27_br[0:0] + attribute \src "libresoc.v:99465.3-99483.6" + wire width 3 $1\dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:99484.3-99502.6" + wire width 3 $1\dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:99123.3-99141.6" + wire width 2 $1\dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:99199.3-99217.6" + wire $1\dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:99370.3-99388.6" + wire width 5 $1\dec31_dec_sub27_form[4:0] + attribute \src "libresoc.v:99047.3-99065.6" + wire width 12 $1\dec31_dec_sub27_function_unit[11:0] + attribute \src "libresoc.v:99389.3-99407.6" + wire width 3 $1\dec31_dec_sub27_in1_sel[2:0] + attribute \src "libresoc.v:99408.3-99426.6" + wire width 4 $1\dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:99427.3-99445.6" + wire width 2 $1\dec31_dec_sub27_in3_sel[1:0] + attribute \src "libresoc.v:99256.3-99274.6" + wire width 7 $1\dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:99161.3-99179.6" + wire $1\dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:99180.3-99198.6" + wire $1\dec31_dec_sub27_inv_out[0:0] + attribute \src "libresoc.v:99294.3-99312.6" + wire $1\dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:99066.3-99084.6" + wire width 4 $1\dec31_dec_sub27_ldst_len[3:0] + attribute \src "libresoc.v:99332.3-99350.6" + wire $1\dec31_dec_sub27_lk[0:0] + attribute \src "libresoc.v:99446.3-99464.6" + wire width 2 $1\dec31_dec_sub27_out_sel[1:0] + attribute \src "libresoc.v:99104.3-99122.6" + wire width 2 $1\dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:99275.3-99293.6" + wire $1\dec31_dec_sub27_rsrv[0:0] + attribute \src "libresoc.v:99351.3-99369.6" + wire $1\dec31_dec_sub27_sgl_pipe[0:0] + attribute \src "libresoc.v:99313.3-99331.6" + wire $1\dec31_dec_sub27_sgn[0:0] + attribute \src "libresoc.v:99237.3-99255.6" + wire $1\dec31_dec_sub27_sgn_ext[0:0] + attribute \src "libresoc.v:99085.3-99103.6" + wire width 2 $1\dec31_dec_sub27_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub27_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub27_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub27_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub27_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub27_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub27_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub27_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub27_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub27_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub27_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub27_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub27_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub27_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub27_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub27_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub27_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub27_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub27_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub27_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub27_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub27_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub27_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub27_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub27_upd + attribute \src "libresoc.v:98790.7-98790.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:98790.7-98790.20" + process $proc$libresoc.v:98790$4071 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:99047.3-99065.6" + process $proc$libresoc.v:99047$4047 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_function_unit[11:0] $1\dec31_dec_sub27_function_unit[11:0] + attribute \src "libresoc.v:99048.5-99048.29" + switch \initial + attribute \src "libresoc.v:99048.9-99048.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'000010 + case 5'11011 assign { } { } - assign $1\function_unit[11:0] 12'000010000000 + assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 attribute \src "libresoc.v:0.0-0.0" - case 6'000011 + case 5'00000 assign { } { } - assign $1\function_unit[11:0] 12'000010000000 + assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 attribute \src "libresoc.v:0.0-0.0" - case 6'011010 + case 5'11001 assign { } { } - assign $1\function_unit[11:0] 12'000000010000 + assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 attribute \src "libresoc.v:0.0-0.0" - case 6'011011 + case 5'10000 assign { } { } - assign $1\function_unit[11:0] 12'000000010000 + assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 + case + assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub27_function_unit $0\dec31_dec_sub27_function_unit[11:0] + end + attribute \src "libresoc.v:99066.3-99084.6" + process $proc$libresoc.v:99066$4048 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_ldst_len[3:0] $1\dec31_dec_sub27_ldst_len[3:0] + attribute \src "libresoc.v:99067.5-99067.29" + switch \initial + attribute \src "libresoc.v:99067.9-99067.17" + case 1'1 case - assign $1\function_unit[11:0] 12'000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- + case 5'11011 assign { } { } - assign $2\function_unit[11:0] 12'000000000000 + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 1610612736 + case 5'00000 assign { } { } - assign $2\function_unit[11:0] 12'000000000000 + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- + case 5'11001 assign { } { } - assign $2\function_unit[11:0] 12'000000000000 + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 case - assign $2\function_unit[11:0] $1\function_unit[11:0] + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 end sync always - update \function_unit $0\function_unit[11:0] + update \dec31_dec_sub27_ldst_len $0\dec31_dec_sub27_ldst_len[3:0] end - attribute \src "libresoc.v:6506.3-6647.6" - process $proc$libresoc.v:6506$260 + attribute \src "libresoc.v:99085.3-99103.6" + process $proc$libresoc.v:99085$4049 assign { } { } assign { } { } - assign { } { } - assign $0\internal_op[6:0] $2\internal_op[6:0] - attribute \src "libresoc.v:6507.5-6507.29" + assign $0\dec31_dec_sub27_upd[1:0] $1\dec31_dec_sub27_upd[1:0] + attribute \src "libresoc.v:99086.5-99086.29" switch \initial - attribute \src "libresoc.v:6507.9-6507.17" + attribute \src "libresoc.v:99086.9-99086.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\internal_op[6:0] \dec19_dec19_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 + case 5'11011 assign { } { } - assign $1\internal_op[6:0] \dec30_dec30_internal_op + assign $1\dec31_dec_sub27_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'011111 + case 5'00000 assign { } { } - assign $1\internal_op[6:0] \dec31_dec31_internal_op + assign $1\dec31_dec_sub27_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'111010 + case 5'11001 assign { } { } - assign $1\internal_op[6:0] \dec58_dec58_internal_op + assign $1\dec31_dec_sub27_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'111110 + case 5'10000 assign { } { } - assign $1\internal_op[6:0] \dec62_dec62_internal_op + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_upd $0\dec31_dec_sub27_upd[1:0] + end + attribute \src "libresoc.v:99104.3-99122.6" + process $proc$libresoc.v:99104$4050 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_rc_sel[1:0] $1\dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:99105.5-99105.29" + switch \initial + attribute \src "libresoc.v:99105.9-99105.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'001100 + case 5'11011 assign { } { } - assign $1\internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 6'001101 + case 5'00000 assign { } { } - assign $1\internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 6'001110 + case 5'11001 assign { } { } - assign $1\internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 6'001111 + case 5'10000 assign { } { } - assign $1\internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_rc_sel $0\dec31_dec_sub27_rc_sel[1:0] + end + attribute \src "libresoc.v:99123.3-99141.6" + process $proc$libresoc.v:99123$4051 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_cry_in[1:0] $1\dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:99124.5-99124.29" + switch \initial + attribute \src "libresoc.v:99124.9-99124.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010001 + case 5'11011 assign { } { } - assign $1\internal_op[6:0] 7'1001001 + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'011100 + case 5'00000 assign { } { } - assign $1\internal_op[6:0] 7'0000100 + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'011101 + case 5'11001 assign { } { } - assign $1\internal_op[6:0] 7'0000100 + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 6'010010 + case 5'10000 assign { } { } - assign $1\internal_op[6:0] 7'0000110 + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_cry_in $0\dec31_dec_sub27_cry_in[1:0] + end + attribute \src "libresoc.v:99142.3-99160.6" + process $proc$libresoc.v:99142$4052 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_asmcode[7:0] $1\dec31_dec_sub27_asmcode[7:0] + attribute \src "libresoc.v:99143.5-99143.29" + switch \initial + attribute \src "libresoc.v:99143.9-99143.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010000 + case 5'11011 assign { } { } - assign $1\internal_op[6:0] 7'0000111 + assign $1\dec31_dec_sub27_asmcode[7:0] 8'01000111 attribute \src "libresoc.v:0.0-0.0" - case 6'001011 + case 5'00000 assign { } { } - assign $1\internal_op[6:0] 7'0001010 + assign $1\dec31_dec_sub27_asmcode[7:0] 8'10011110 attribute \src "libresoc.v:0.0-0.0" - case 6'001010 + case 5'11001 assign { } { } - assign $1\internal_op[6:0] 7'0001010 + assign $1\dec31_dec_sub27_asmcode[7:0] 8'10100001 attribute \src "libresoc.v:0.0-0.0" - case 6'100010 + case 5'10000 assign { } { } - assign $1\internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub27_asmcode[7:0] 8'10100100 + case + assign $1\dec31_dec_sub27_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub27_asmcode $0\dec31_dec_sub27_asmcode[7:0] + end + attribute \src "libresoc.v:99161.3-99179.6" + process $proc$libresoc.v:99161$4053 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_inv_a[0:0] $1\dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:99162.5-99162.29" + switch \initial + attribute \src "libresoc.v:99162.9-99162.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'100011 + case 5'11011 assign { } { } - assign $1\internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101010 + case 5'00000 assign { } { } - assign $1\internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101011 + case 5'11001 assign { } { } - assign $1\internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101000 + case 5'10000 assign { } { } - assign $1\internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_inv_a $0\dec31_dec_sub27_inv_a[0:0] + end + attribute \src "libresoc.v:99180.3-99198.6" + process $proc$libresoc.v:99180$4054 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_inv_out[0:0] $1\dec31_dec_sub27_inv_out[0:0] + attribute \src "libresoc.v:99181.5-99181.29" + switch \initial + attribute \src "libresoc.v:99181.9-99181.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'101001 + case 5'11011 assign { } { } - assign $1\internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100000 + case 5'00000 assign { } { } - assign $1\internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100001 + case 5'11001 assign { } { } - assign $1\internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'000111 + case 5'10000 assign { } { } - assign $1\internal_op[6:0] 7'0110010 + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_inv_out $0\dec31_dec_sub27_inv_out[0:0] + end + attribute \src "libresoc.v:99199.3-99217.6" + process $proc$libresoc.v:99199$4055 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_cry_out[0:0] $1\dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:99200.5-99200.29" + switch \initial + attribute \src "libresoc.v:99200.9-99200.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'011000 + case 5'11011 assign { } { } - assign $1\internal_op[6:0] 7'0110101 + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011001 + case 5'00000 assign { } { } - assign $1\internal_op[6:0] 7'0110101 + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010100 + case 5'11001 assign { } { } - assign $1\internal_op[6:0] 7'0111000 + assign $1\dec31_dec_sub27_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'010101 + case 5'10000 assign { } { } - assign $1\internal_op[6:0] 7'0111000 + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_cry_out $0\dec31_dec_sub27_cry_out[0:0] + end + attribute \src "libresoc.v:99218.3-99236.6" + process $proc$libresoc.v:99218$4056 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_br[0:0] $1\dec31_dec_sub27_br[0:0] + attribute \src "libresoc.v:99219.5-99219.29" + switch \initial + attribute \src "libresoc.v:99219.9-99219.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010111 + case 5'11011 assign { } { } - assign $1\internal_op[6:0] 7'0111000 + assign $1\dec31_dec_sub27_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100110 + case 5'00000 assign { } { } - assign $1\internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub27_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100111 + case 5'11001 assign { } { } - assign $1\internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub27_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'101100 + case 5'10000 assign { } { } - assign $1\internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub27_br[0:0] 1'0 + case + assign $1\dec31_dec_sub27_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_br $0\dec31_dec_sub27_br[0:0] + end + attribute \src "libresoc.v:99237.3-99255.6" + process $proc$libresoc.v:99237$4057 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sgn_ext[0:0] $1\dec31_dec_sub27_sgn_ext[0:0] + attribute \src "libresoc.v:99238.5-99238.29" + switch \initial + attribute \src "libresoc.v:99238.9-99238.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'101101 + case 5'11011 assign { } { } - assign $1\internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100100 + case 5'00000 assign { } { } - assign $1\internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100101 + case 5'11001 assign { } { } - assign $1\internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001000 + case 5'10000 assign { } { } - assign $1\internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_sgn_ext $0\dec31_dec_sub27_sgn_ext[0:0] + end + attribute \src "libresoc.v:99256.3-99274.6" + process $proc$libresoc.v:99256$4058 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_internal_op[6:0] $1\dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:99257.5-99257.29" + switch \initial + attribute \src "libresoc.v:99257.9-99257.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'000010 + case 5'11011 assign { } { } - assign $1\internal_op[6:0] 7'0111111 + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0100000 attribute \src "libresoc.v:0.0-0.0" - case 6'000011 + case 5'00000 assign { } { } - assign $1\internal_op[6:0] 7'0111111 + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111100 attribute \src "libresoc.v:0.0-0.0" - case 6'011010 + case 5'11001 assign { } { } - assign $1\internal_op[6:0] 7'1000011 + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 attribute \src "libresoc.v:0.0-0.0" - case 6'011011 + case 5'10000 assign { } { } - assign $1\internal_op[6:0] 7'1000011 + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 + case + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub27_internal_op $0\dec31_dec_sub27_internal_op[6:0] + end + attribute \src "libresoc.v:99275.3-99293.6" + process $proc$libresoc.v:99275$4059 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_rsrv[0:0] $1\dec31_dec_sub27_rsrv[0:0] + attribute \src "libresoc.v:99276.5-99276.29" + switch \initial + attribute \src "libresoc.v:99276.9-99276.17" + case 1'1 case - assign $1\internal_op[6:0] 7'0000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- + case 5'11011 assign { } { } - assign $2\internal_op[6:0] 7'0000101 + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1610612736 + case 5'00000 assign { } { } - assign $2\internal_op[6:0] 7'0000001 + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- + case 5'11001 assign { } { } - assign $2\internal_op[6:0] 7'1000100 + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 case - assign $2\internal_op[6:0] $1\internal_op[6:0] + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 end sync always - update \internal_op $0\internal_op[6:0] + update \dec31_dec_sub27_rsrv $0\dec31_dec_sub27_rsrv[0:0] end - attribute \src "libresoc.v:6648.3-6789.6" - process $proc$libresoc.v:6648$261 + attribute \src "libresoc.v:99294.3-99312.6" + process $proc$libresoc.v:99294$4060 assign { } { } assign { } { } - assign { } { } - assign $0\form[4:0] $2\form[4:0] - attribute \src "libresoc.v:6649.5-6649.29" + assign $0\dec31_dec_sub27_is_32b[0:0] $1\dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:99295.5-99295.29" switch \initial - attribute \src "libresoc.v:6649.9-6649.17" + attribute \src "libresoc.v:99295.9-99295.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\form[4:0] \dec19_dec19_form - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 + case 5'11011 assign { } { } - assign $1\form[4:0] \dec30_dec30_form + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011111 + case 5'00000 assign { } { } - assign $1\form[4:0] \dec31_dec31_form + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'111010 + case 5'11001 assign { } { } - assign $1\form[4:0] \dec58_dec58_form + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'111110 + case 5'10000 assign { } { } - assign $1\form[4:0] \dec62_dec62_form + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_is_32b $0\dec31_dec_sub27_is_32b[0:0] + end + attribute \src "libresoc.v:99313.3-99331.6" + process $proc$libresoc.v:99313$4061 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sgn[0:0] $1\dec31_dec_sub27_sgn[0:0] + attribute \src "libresoc.v:99314.5-99314.29" + switch \initial + attribute \src "libresoc.v:99314.9-99314.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'001100 + case 5'11011 assign { } { } - assign $1\form[4:0] 5'00100 + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001101 + case 5'00000 assign { } { } - assign $1\form[4:0] 5'00100 + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001110 + case 5'11001 assign { } { } - assign $1\form[4:0] 5'00100 + assign $1\dec31_dec_sub27_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 6'001111 + case 5'10000 assign { } { } - assign $1\form[4:0] 5'00100 + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_sgn $0\dec31_dec_sub27_sgn[0:0] + end + attribute \src "libresoc.v:99332.3-99350.6" + process $proc$libresoc.v:99332$4062 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_lk[0:0] $1\dec31_dec_sub27_lk[0:0] + attribute \src "libresoc.v:99333.5-99333.29" + switch \initial + attribute \src "libresoc.v:99333.9-99333.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010001 + case 5'11011 assign { } { } - assign $1\form[4:0] 5'00011 + assign $1\dec31_dec_sub27_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011100 + case 5'00000 assign { } { } - assign $1\form[4:0] 5'00010 + assign $1\dec31_dec_sub27_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'011101 + case 5'11001 assign { } { } - assign $1\form[4:0] 5'00010 + assign $1\dec31_dec_sub27_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'010010 + case 5'10000 assign { } { } - assign $1\form[4:0] 5'00001 + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_lk $0\dec31_dec_sub27_lk[0:0] + end + attribute \src "libresoc.v:99351.3-99369.6" + process $proc$libresoc.v:99351$4063 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sgl_pipe[0:0] $1\dec31_dec_sub27_sgl_pipe[0:0] + attribute \src "libresoc.v:99352.5-99352.29" + switch \initial + attribute \src "libresoc.v:99352.9-99352.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010000 + case 5'11011 assign { } { } - assign $1\form[4:0] 5'00010 + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001011 + case 5'00000 assign { } { } - assign $1\form[4:0] 5'00100 + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'001010 + case 5'11001 assign { } { } - assign $1\form[4:0] 5'00100 + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 6'100010 + case 5'10000 assign { } { } - assign $1\form[4:0] 5'00100 + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_sgl_pipe $0\dec31_dec_sub27_sgl_pipe[0:0] + end + attribute \src "libresoc.v:99370.3-99388.6" + process $proc$libresoc.v:99370$4064 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_form[4:0] $1\dec31_dec_sub27_form[4:0] + attribute \src "libresoc.v:99371.5-99371.29" + switch \initial + attribute \src "libresoc.v:99371.9-99371.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'100011 + case 5'11011 assign { } { } - assign $1\form[4:0] 5'00100 + assign $1\dec31_dec_sub27_form[4:0] 5'10000 attribute \src "libresoc.v:0.0-0.0" - case 6'101010 + case 5'00000 assign { } { } - assign $1\form[4:0] 5'00100 + assign $1\dec31_dec_sub27_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 6'101011 + case 5'11001 assign { } { } - assign $1\form[4:0] 5'00100 + assign $1\dec31_dec_sub27_form[4:0] 5'10000 attribute \src "libresoc.v:0.0-0.0" - case 6'101000 + case 5'10000 assign { } { } - assign $1\form[4:0] 5'00100 + assign $1\dec31_dec_sub27_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub27_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub27_form $0\dec31_dec_sub27_form[4:0] + end + attribute \src "libresoc.v:99389.3-99407.6" + process $proc$libresoc.v:99389$4065 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_in1_sel[2:0] $1\dec31_dec_sub27_in1_sel[2:0] + attribute \src "libresoc.v:99390.5-99390.29" + switch \initial + attribute \src "libresoc.v:99390.9-99390.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'101001 + case 5'11011 assign { } { } - assign $1\form[4:0] 5'00100 + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'100000 + case 5'00000 assign { } { } - assign $1\form[4:0] 5'00100 + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'100001 + case 5'11001 assign { } { } - assign $1\form[4:0] 5'00100 + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'000111 + case 5'10000 assign { } { } - assign $1\form[4:0] 5'00100 + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_in1_sel $0\dec31_dec_sub27_in1_sel[2:0] + end + attribute \src "libresoc.v:99408.3-99426.6" + process $proc$libresoc.v:99408$4066 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_in2_sel[3:0] $1\dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:99409.5-99409.29" + switch \initial + attribute \src "libresoc.v:99409.9-99409.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'011000 + case 5'11011 assign { } { } - assign $1\form[4:0] 5'00100 + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'1010 attribute \src "libresoc.v:0.0-0.0" - case 6'011001 + case 5'00000 assign { } { } - assign $1\form[4:0] 5'00100 + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 6'010100 + case 5'11001 assign { } { } - assign $1\form[4:0] 5'10011 + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'1010 attribute \src "libresoc.v:0.0-0.0" - case 6'010101 + case 5'10000 assign { } { } - assign $1\form[4:0] 5'10011 + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub27_in2_sel $0\dec31_dec_sub27_in2_sel[3:0] + end + attribute \src "libresoc.v:99427.3-99445.6" + process $proc$libresoc.v:99427$4067 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_in3_sel[1:0] $1\dec31_dec_sub27_in3_sel[1:0] + attribute \src "libresoc.v:99428.5-99428.29" + switch \initial + attribute \src "libresoc.v:99428.9-99428.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'010111 + case 5'11011 assign { } { } - assign $1\form[4:0] 5'10011 + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 6'100110 + case 5'00000 assign { } { } - assign $1\form[4:0] 5'00100 + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 6'100111 + case 5'11001 assign { } { } - assign $1\form[4:0] 5'00100 + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 6'101100 + case 5'10000 assign { } { } - assign $1\form[4:0] 5'00100 + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_in3_sel $0\dec31_dec_sub27_in3_sel[1:0] + end + attribute \src "libresoc.v:99446.3-99464.6" + process $proc$libresoc.v:99446$4068 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_out_sel[1:0] $1\dec31_dec_sub27_out_sel[1:0] + attribute \src "libresoc.v:99447.5-99447.29" + switch \initial + attribute \src "libresoc.v:99447.9-99447.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'101101 + case 5'11011 assign { } { } - assign $1\form[4:0] 5'00100 + assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 6'100100 + case 5'00000 assign { } { } - assign $1\form[4:0] 5'00100 + assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 6'100101 + case 5'11001 assign { } { } - assign $1\form[4:0] 5'00100 + assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 6'001000 + case 5'10000 assign { } { } - assign $1\form[4:0] 5'00100 + assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub27_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_out_sel $0\dec31_dec_sub27_out_sel[1:0] + end + attribute \src "libresoc.v:99465.3-99483.6" + process $proc$libresoc.v:99465$4069 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_cr_in[2:0] $1\dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:99466.5-99466.29" + switch \initial + attribute \src "libresoc.v:99466.9-99466.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 6'000010 + case 5'11011 assign { } { } - assign $1\form[4:0] 5'00100 + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'000011 + case 5'00000 assign { } { } - assign $1\form[4:0] 5'00100 + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'011010 + case 5'11001 assign { } { } - assign $1\form[4:0] 5'00100 + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 6'011011 + case 5'10000 assign { } { } - assign $1\form[4:0] 5'00100 + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_cr_in $0\dec31_dec_sub27_cr_in[2:0] + end + attribute \src "libresoc.v:99484.3-99502.6" + process $proc$libresoc.v:99484$4070 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_cr_out[2:0] $1\dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:99485.5-99485.29" + switch \initial + attribute \src "libresoc.v:99485.9-99485.17" + case 1'1 case - assign $1\form[4:0] 5'00000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- + case 5'11011 assign { } { } - assign $2\form[4:0] 5'00000 + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 1610612736 + case 5'00000 assign { } { } - assign $2\form[4:0] 5'00100 + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- + case 5'11001 assign { } { } - assign $2\form[4:0] 5'00000 + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 case - assign $2\form[4:0] $1\form[4:0] + assign $1\dec31_dec_sub27_cr_out[2:0] 3'000 end sync always - update \form $0\form[4:0] + update \dec31_dec_sub27_cr_out $0\dec31_dec_sub27_cr_out[2:0] end - connect \$2 $ternary$libresoc.v:3249$237_Y - connect \VC_XO \opcode_in [9:0] - connect \VC_VRT \opcode_in [25:21] - connect \VC_VRB \opcode_in [15:11] - connect \VC_VRA \opcode_in [20:16] - connect \VC_Rc \opcode_in [10] - connect \XS_XO \opcode_in [10:2] - connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } - connect \XS_RS \opcode_in [25:21] - connect \XS_Rc \opcode_in [0] - connect \XS_RA \opcode_in [20:16] - connect \VA_XO \opcode_in [5:0] - connect \VA_VRT \opcode_in [25:21] - connect \VA_VRC \opcode_in [10:6] - connect \VA_VRB \opcode_in [15:11] - connect \VA_VRA \opcode_in [20:16] - connect \VA_SHB \opcode_in [9:6] - connect \VA_RT \opcode_in [25:21] - connect \VA_RC \opcode_in [10:6] - connect \VA_RB \opcode_in [15:11] - connect \VA_RA \opcode_in [20:16] - connect \TX_XO \opcode_in [6:1] - connect \TX_XBI \opcode_in [10:7] - connect \TX_UI \opcode_in [15:11] - connect \TX_RA \opcode_in [20:16] - connect \DQE_XO \opcode_in [1:0] - connect \DQE_RT \opcode_in [25:21] - connect \DQE_RA \opcode_in [20:16] - connect \XO_XO \opcode_in [9:1] - connect \XO_RT \opcode_in [25:21] - connect \XO_Rc \opcode_in [0] - connect \XO_RB \opcode_in [15:11] - connect \XO_RA \opcode_in [20:16] - connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] - connect \MD_XO \opcode_in [4:2] - connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } - connect \MD_RS \opcode_in [25:21] - connect \MD_Rc \opcode_in [0] - connect \MD_RA \opcode_in [20:16] - connect \MD_me \opcode_in [10:5] - connect \MD_mb \opcode_in [10:5] - connect \M_SH \opcode_in [15:11] - connect \M_RS \opcode_in [25:21] - connect \M_Rc \opcode_in [0] - connect \M_RB \opcode_in [15:11] - connect \M_RA \opcode_in [20:16] - connect \M_ME \opcode_in [5:1] - connect \M_MB \opcode_in [10:6] - connect \SC_XO_1 \opcode_in [1:0] - connect \SC_XO \opcode_in [1] - connect \SC_LEV \opcode_in [11:5] - connect \MDS_XO \opcode_in [4:1] - connect \MDS_XBI_1 \opcode_in [10:7] - connect \MDS_XBI \opcode_in [10:7] - connect \MDS_RS \opcode_in [25:21] - connect \MDS_Rc \opcode_in [0] - connect \MDS_RB \opcode_in [15:11] - connect \MDS_RA \opcode_in [20:16] - connect \MDS_me \opcode_in [10:5] - connect \MDS_mb \opcode_in [10:5] - connect \MDS_IS \opcode_in [25:21] - connect \MDS_IB \opcode_in [15:11] - connect \Z23_XO \opcode_in [8:1] - connect \Z23_TE \opcode_in [20:16] - connect \Z23_RMC \opcode_in [10:9] - connect \Z23_Rc \opcode_in [0] - connect \Z23_R \opcode_in [16] - connect \Z23_FRTp \opcode_in [25:21] - connect \Z23_FRT \opcode_in [25:21] - connect \Z23_FRBp \opcode_in [15:11] - connect \Z23_FRB \opcode_in [15:11] - connect \Z23_FRAp \opcode_in [20:16] - connect \Z23_FRA \opcode_in [20:16] - connect \XFL_XO \opcode_in [10:1] - connect \XFL_W \opcode_in [16] - connect \XFL_Rc \opcode_in [0] - connect \XFL_L \opcode_in [25] - connect \XFL_FRB \opcode_in [15:11] - connect \XFL_FLM \opcode_in [24:17] - connect \VX_XO_1 \opcode_in [10:0] - connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } - connect \VX_VRT \opcode_in [25:21] - connect \VX_VRB \opcode_in [15:11] - connect \VX_VRA \opcode_in [20:16] - connect \VX_UIM_3 \opcode_in [17:16] - connect \VX_UIM_2 \opcode_in [18:16] - connect \VX_UIM_1 \opcode_in [19:16] - connect \VX_UIM \opcode_in [20:16] - connect \VX_SIM \opcode_in [20:16] - connect \VX_RT \opcode_in [25:21] - connect \VX_RA \opcode_in [20:16] - connect \VX_PS \opcode_in [9] - connect \VX_EO \opcode_in [20:16] - connect \DS_XO \opcode_in [1:0] - connect \DS_VRT \opcode_in [25:21] - connect \DS_VRS \opcode_in [25:21] - connect \DS_RT \opcode_in [25:21] - connect \DS_RSp \opcode_in [25:21] - connect \DS_RS \opcode_in [25:21] - connect \DS_RA \opcode_in [20:16] - connect \DS_FRTp \opcode_in [25:21] - connect \DS_FRSp \opcode_in [25:21] - connect \DS_DS \opcode_in [15:2] - connect \DQ_XO \opcode_in [2:0] - connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_T \opcode_in [25:21] - connect \DQ_TX \opcode_in [3] - connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_S \opcode_in [25:21] - connect \DQ_SX \opcode_in [3] - connect \DQ_RTp \opcode_in [25:21] - connect \DQ_RA \opcode_in [20:16] - connect \DQ_PT \opcode_in [3:0] - connect \DQ_DQ \opcode_in [15:4] - connect \DX_XO \opcode_in [5:1] - connect \DX_RT \opcode_in [25:21] - connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } - connect \DX_d2 \opcode_in [0] - connect \DX_d1 \opcode_in [20:16] - connect \DX_d0 \opcode_in [15:6] - connect \XFX_XO \opcode_in [10:1] - connect \XFX_SPR \opcode_in [20:11] - connect \XFX_RT \opcode_in [25:21] - connect \XFX_RS \opcode_in [25:21] - connect \XFX_FXM \opcode_in [19:12] - connect \XFX_DUIS \opcode_in [20:11] - connect \XFX_DUI \opcode_in [25:21] - connect \XFX_BHRBE \opcode_in [20:11] - connect \EVS_BFA \opcode_in [2:0] - connect \Z22_XO \opcode_in [9:1] - connect \Z22_SH \opcode_in [15:10] - connect \Z22_Rc \opcode_in [0] - connect \Z22_FRTp \opcode_in [25:21] - connect \Z22_FRT \opcode_in [25:21] - connect \Z22_FRAp \opcode_in [20:16] - connect \Z22_FRA \opcode_in [20:16] - connect \Z22_DGM \opcode_in [15:10] - connect \Z22_DCM \opcode_in [15:10] - connect \Z22_BF \opcode_in [25:23] - connect \XX2_XO_1 \opcode_in [10:2] - connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } - connect \XX2_UIM_1 \opcode_in [17:16] - connect \XX2_UIM \opcode_in [19:16] - connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX2_T \opcode_in [25:21] - connect \XX2_TX \opcode_in [0] - connect \XX2_RT \opcode_in [25:21] - connect \XX2_EO \opcode_in [20:16] - connect \XX2_DCMX \opcode_in [22:16] - connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } - connect \XX2_dx \opcode_in [20:16] - connect \XX2_dm \opcode_in [2] - connect \XX2_dc \opcode_in [6] - connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX2_B \opcode_in [15:11] - connect \XX2_BX \opcode_in [1] - connect \XX2_BF \opcode_in [25:23] - connect \D_UI \opcode_in [15:0] - connect \D_TO \opcode_in [25:21] - connect \D_SI \opcode_in [15:0] - connect \D_RT \opcode_in [25:21] - connect \D_RS \opcode_in [25:21] - connect \D_RA \opcode_in [20:16] - connect \D_L \opcode_in [21] - connect \D_FRT \opcode_in [25:21] - connect \D_FRS \opcode_in [25:21] - connect \D_D \opcode_in [15:0] - connect \D_BF \opcode_in [25:23] - connect \A_XO \opcode_in [5:1] - connect \A_RT \opcode_in [25:21] - connect \A_Rc \opcode_in [0] - connect \A_RB \opcode_in [15:11] - connect \A_RA \opcode_in [20:16] - connect \A_FRT \opcode_in [25:21] - connect \A_FRC \opcode_in [10:6] - connect \A_FRB \opcode_in [15:11] - connect \A_FRA \opcode_in [20:16] - connect \A_BC \opcode_in [10:6] - connect \XL_XO \opcode_in [10:1] - connect \XL_S \opcode_in [11] - connect \XL_OC \opcode_in [25:11] - connect \XL_LK \opcode_in [0] - connect \XL_BT \opcode_in [25:21] - connect \XL_BO_1 \opcode_in [25:21] - connect \XL_BO \opcode_in [25:21] - connect \XL_BI \opcode_in [20:16] - connect \XL_BH \opcode_in [12:11] - connect \XL_BFA \opcode_in [20:18] - connect \XL_BF \opcode_in [25:23] - connect \XL_BB \opcode_in [15:11] - connect \XL_BA \opcode_in [20:16] - connect \XX4_XO \opcode_in [5:4] - connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX4_T \opcode_in [25:21] - connect \XX4_TX \opcode_in [0] - connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } - connect \XX4_C \opcode_in [10:6] - connect \XX4_CX \opcode_in [3] - connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX4_B \opcode_in [15:11] - connect \XX4_BX \opcode_in [1] - connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } - connect \XX4_A \opcode_in [20:16] - connect \XX4_AX \opcode_in [2] - connect \XX3_XO_2 \opcode_in [9:1] - connect \XX3_XO_1 \opcode_in [10:3] - connect \XX3_XO \opcode_in [10:7] - connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX3_T \opcode_in [25:21] - connect \XX3_TX \opcode_in [0] - connect \XX3_SHW \opcode_in [9:8] - connect \XX3_Rc \opcode_in [10] - connect \XX3_DM \opcode_in [9:8] - connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX3_B \opcode_in [15:11] - connect \XX3_BX \opcode_in [1] - connect \XX3_BF \opcode_in [25:23] - connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } - connect \XX3_A \opcode_in [20:16] - connect \XX3_AX \opcode_in [2] - connect \I_LK \opcode_in [0] - connect \I_LI \opcode_in [25:2] - connect \I_AA \opcode_in [1] - connect \B_LK \opcode_in [0] - connect \B_BO \opcode_in [25:21] - connect \B_BI \opcode_in [20:16] - connect \B_BD \opcode_in [15:2] - connect \B_AA \opcode_in [1] - connect \X_XO_1 \opcode_in [8:1] - connect \X_XO \opcode_in [10:1] - connect \X_WC \opcode_in [22:21] - connect \X_W \opcode_in [16] - connect \X_VRT \opcode_in [25:21] - connect \X_VRS \opcode_in [25:21] - connect \X_UIM \opcode_in [20:16] - connect \X_U \opcode_in [15:12] - connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \X_TX \opcode_in [0] - connect \X_TO \opcode_in [25:21] - connect \X_TH \opcode_in [25:21] - connect \X_TBR \opcode_in [20:11] - connect \X_T \opcode_in [25:21] - connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } - connect \X_SX \opcode_in [0] - connect \X_SR \opcode_in [19:16] - connect \X_SP \opcode_in [20:19] - connect \X_SI \opcode_in [15:11] - connect \X_SH \opcode_in [15:11] - connect \X_S \opcode_in [25:21] - connect \X_RTp \opcode_in [25:21] - connect \X_RT \opcode_in [25:21] - connect \X_RSp \opcode_in [25:21] - connect \X_RS \opcode_in [25:21] - connect \X_RO \opcode_in [0] - connect \X_RM \opcode_in [12:11] - connect \X_RIC \opcode_in [19:18] - connect \X_Rc \opcode_in [0] - connect \X_RB \opcode_in [15:11] - connect \X_RA \opcode_in [20:16] - connect \X_R_1 \opcode_in [16] - connect \X_R \opcode_in [21] - connect \X_PRS \opcode_in [17] - connect \X_NB \opcode_in [15:11] - connect \X_MO \opcode_in [25:21] - connect \X_L3 \opcode_in [17:16] - connect \X_L1 \opcode_in [16] - connect \X_L \opcode_in [21] - connect \X_L2 \opcode_in [22:21] - connect \X_IMM8 \opcode_in [18:11] - connect \X_IH \opcode_in [23:21] - connect \X_FRTp \opcode_in [25:21] - connect \X_FRT \opcode_in [25:21] - connect \X_FRSp \opcode_in [25:21] - connect \X_FRS \opcode_in [25:21] - connect \X_FRBp \opcode_in [15:11] - connect \X_FRB \opcode_in [15:11] - connect \X_FRAp \opcode_in [20:16] - connect \X_FRA \opcode_in [20:16] - connect \X_FC \opcode_in [15:11] - connect \X_EX \opcode_in [0] - connect \X_EO_1 \opcode_in [20:16] - connect \X_EO \opcode_in [20:19] - connect \X_E_1 \opcode_in [19:16] - connect \X_E \opcode_in [15] - connect \X_DRM \opcode_in [13:11] - connect \X_DCMX \opcode_in [22:16] - connect \X_CT \opcode_in [24:21] - connect \X_BO \opcode_in [25:21] - connect \X_BFA \opcode_in [20:18] - connect \X_BF \opcode_in [25:23] - connect \X_A \opcode_in [25] - connect \SPR \opcode_in [20:11] - connect \MB \opcode_in [10:6] - connect \ME \opcode_in [5:1] - connect \SH \opcode_in [15:11] - connect \BC \opcode_in [10:6] - connect \TO \opcode_in [25:21] - connect \DS \opcode_in [15:2] - connect \D \opcode_in [15:0] - connect \BH \opcode_in [12:11] - connect \BI \opcode_in [20:16] - connect \BO \opcode_in [25:21] - connect \FXM \opcode_in [19:12] - connect \BT \opcode_in [25:21] - connect \BA \opcode_in [20:16] - connect \BB \opcode_in [15:11] - connect \CR \opcode_in [10:1] - connect \BF \opcode_in [25:23] - connect \BD \opcode_in [15:2] - connect \OE \opcode_in [10] - connect \Rc \opcode_in [0] - connect \AA \opcode_in [1] - connect \LK \opcode_in [0] - connect \LI \opcode_in [25:2] - connect \ME32 \opcode_in [5:1] - connect \MB32 \opcode_in [10:6] - connect \sh { \opcode_in [1] \opcode_in [15:11] } - connect \SH32 \opcode_in [15:11] - connect \L \opcode_in [21] - connect \UI \opcode_in [15:0] - connect \SI \opcode_in [15:0] - connect \RB \opcode_in [15:11] - connect \RA \opcode_in [20:16] - connect \RT \opcode_in [25:21] - connect \RS \opcode_in [25:21] - connect \opcode_in \$2 - connect \opcode_switch$1 \opcode_in - connect \dec62_opcode_in \opcode_in - connect \dec58_opcode_in \opcode_in - connect \dec31_opcode_in \opcode_in - connect \dec30_opcode_in \opcode_in - connect \dec19_opcode_in \opcode_in - connect \opcode_switch \opcode_in [31:26] + connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:7128.1-8635.10" +attribute \src "libresoc.v:99508.1-100655.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec19" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub28" attribute \generator "nMigen" -module \dec19 - attribute \src "libresoc.v:7646.3-7697.6" - wire width 8 $0\dec19_asmcode[7:0] - attribute \src "libresoc.v:7854.3-7905.6" - wire $0\dec19_br[0:0] - attribute \src "libresoc.v:8530.3-8581.6" - wire width 3 $0\dec19_cr_in[2:0] - attribute \src "libresoc.v:8582.3-8633.6" - wire width 3 $0\dec19_cr_out[2:0] - attribute \src "libresoc.v:7594.3-7645.6" - wire width 2 $0\dec19_cry_in[1:0] - attribute \src "libresoc.v:7802.3-7853.6" - wire $0\dec19_cry_out[0:0] - attribute \src "libresoc.v:8270.3-8321.6" - wire width 5 $0\dec19_form[4:0] - attribute \src "libresoc.v:7386.3-7437.6" - wire width 12 $0\dec19_function_unit[11:0] - attribute \src "libresoc.v:8322.3-8373.6" - wire width 3 $0\dec19_in1_sel[2:0] - attribute \src "libresoc.v:8374.3-8425.6" - wire width 4 $0\dec19_in2_sel[3:0] - attribute \src "libresoc.v:8426.3-8477.6" - wire width 2 $0\dec19_in3_sel[1:0] - attribute \src "libresoc.v:7958.3-8009.6" - wire width 7 $0\dec19_internal_op[6:0] - attribute \src "libresoc.v:7698.3-7749.6" - wire $0\dec19_inv_a[0:0] - attribute \src "libresoc.v:7750.3-7801.6" - wire $0\dec19_inv_out[0:0] - attribute \src "libresoc.v:8062.3-8113.6" - wire $0\dec19_is_32b[0:0] - attribute \src "libresoc.v:7438.3-7489.6" - wire width 4 $0\dec19_ldst_len[3:0] - attribute \src "libresoc.v:8166.3-8217.6" - wire $0\dec19_lk[0:0] - attribute \src "libresoc.v:8478.3-8529.6" - wire width 2 $0\dec19_out_sel[1:0] - attribute \src "libresoc.v:7542.3-7593.6" - wire width 2 $0\dec19_rc_sel[1:0] - attribute \src "libresoc.v:8010.3-8061.6" - wire $0\dec19_rsrv[0:0] - attribute \src "libresoc.v:8218.3-8269.6" - wire $0\dec19_sgl_pipe[0:0] - attribute \src "libresoc.v:8114.3-8165.6" - wire $0\dec19_sgn[0:0] - attribute \src "libresoc.v:7906.3-7957.6" - wire $0\dec19_sgn_ext[0:0] - attribute \src "libresoc.v:7490.3-7541.6" - wire width 2 $0\dec19_upd[1:0] - attribute \src "libresoc.v:7129.7-7129.20" +module \dec31_dec_sub28 + attribute \src "libresoc.v:99951.3-99987.6" + wire width 8 $0\dec31_dec_sub28_asmcode[7:0] + attribute \src "libresoc.v:100099.3-100135.6" + wire $0\dec31_dec_sub28_br[0:0] + attribute \src "libresoc.v:100580.3-100616.6" + wire width 3 $0\dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:100617.3-100653.6" + wire width 3 $0\dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:99914.3-99950.6" + wire width 2 $0\dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:100062.3-100098.6" + wire $0\dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:100395.3-100431.6" + wire width 5 $0\dec31_dec_sub28_form[4:0] + attribute \src "libresoc.v:99766.3-99802.6" + wire width 12 $0\dec31_dec_sub28_function_unit[11:0] + attribute \src "libresoc.v:100432.3-100468.6" + wire width 3 $0\dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:100469.3-100505.6" + wire width 4 $0\dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:100506.3-100542.6" + wire width 2 $0\dec31_dec_sub28_in3_sel[1:0] + attribute \src "libresoc.v:100173.3-100209.6" + wire width 7 $0\dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:99988.3-100024.6" + wire $0\dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:100025.3-100061.6" + wire $0\dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:100247.3-100283.6" + wire $0\dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:99803.3-99839.6" + wire width 4 $0\dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:100321.3-100357.6" + wire $0\dec31_dec_sub28_lk[0:0] + attribute \src "libresoc.v:100543.3-100579.6" + wire width 2 $0\dec31_dec_sub28_out_sel[1:0] + attribute \src "libresoc.v:99877.3-99913.6" + wire width 2 $0\dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:100210.3-100246.6" + wire $0\dec31_dec_sub28_rsrv[0:0] + attribute \src "libresoc.v:100358.3-100394.6" + wire $0\dec31_dec_sub28_sgl_pipe[0:0] + attribute \src "libresoc.v:100284.3-100320.6" + wire $0\dec31_dec_sub28_sgn[0:0] + attribute \src "libresoc.v:100136.3-100172.6" + wire $0\dec31_dec_sub28_sgn_ext[0:0] + attribute \src "libresoc.v:99840.3-99876.6" + wire width 2 $0\dec31_dec_sub28_upd[1:0] + attribute \src "libresoc.v:99509.7-99509.20" wire $0\initial[0:0] - attribute \src "libresoc.v:7646.3-7697.6" - wire width 8 $1\dec19_asmcode[7:0] - attribute \src "libresoc.v:7854.3-7905.6" - wire $1\dec19_br[0:0] - attribute \src "libresoc.v:8530.3-8581.6" - wire width 3 $1\dec19_cr_in[2:0] - attribute \src "libresoc.v:8582.3-8633.6" - wire width 3 $1\dec19_cr_out[2:0] - attribute \src "libresoc.v:7594.3-7645.6" - wire width 2 $1\dec19_cry_in[1:0] - attribute \src "libresoc.v:7802.3-7853.6" - wire $1\dec19_cry_out[0:0] - attribute \src "libresoc.v:8270.3-8321.6" - wire width 5 $1\dec19_form[4:0] - attribute \src "libresoc.v:7386.3-7437.6" - wire width 12 $1\dec19_function_unit[11:0] - attribute \src "libresoc.v:8322.3-8373.6" - wire width 3 $1\dec19_in1_sel[2:0] - attribute \src "libresoc.v:8374.3-8425.6" - wire width 4 $1\dec19_in2_sel[3:0] - attribute \src "libresoc.v:8426.3-8477.6" - wire width 2 $1\dec19_in3_sel[1:0] - attribute \src "libresoc.v:7958.3-8009.6" - wire width 7 $1\dec19_internal_op[6:0] - attribute \src "libresoc.v:7698.3-7749.6" - wire $1\dec19_inv_a[0:0] - attribute \src "libresoc.v:7750.3-7801.6" - wire $1\dec19_inv_out[0:0] - attribute \src "libresoc.v:8062.3-8113.6" - wire $1\dec19_is_32b[0:0] - attribute \src "libresoc.v:7438.3-7489.6" - wire width 4 $1\dec19_ldst_len[3:0] - attribute \src "libresoc.v:8166.3-8217.6" - wire $1\dec19_lk[0:0] - attribute \src "libresoc.v:8478.3-8529.6" - wire width 2 $1\dec19_out_sel[1:0] - attribute \src "libresoc.v:7542.3-7593.6" - wire width 2 $1\dec19_rc_sel[1:0] - attribute \src "libresoc.v:8010.3-8061.6" - wire $1\dec19_rsrv[0:0] - attribute \src "libresoc.v:8218.3-8269.6" - wire $1\dec19_sgl_pipe[0:0] - attribute \src "libresoc.v:8114.3-8165.6" - wire $1\dec19_sgn[0:0] - attribute \src "libresoc.v:7906.3-7957.6" - wire $1\dec19_sgn_ext[0:0] - attribute \src "libresoc.v:7490.3-7541.6" - wire width 2 $1\dec19_upd[1:0] + attribute \src "libresoc.v:99951.3-99987.6" + wire width 8 $1\dec31_dec_sub28_asmcode[7:0] + attribute \src "libresoc.v:100099.3-100135.6" + wire $1\dec31_dec_sub28_br[0:0] + attribute \src "libresoc.v:100580.3-100616.6" + wire width 3 $1\dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:100617.3-100653.6" + wire width 3 $1\dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:99914.3-99950.6" + wire width 2 $1\dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:100062.3-100098.6" + wire $1\dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:100395.3-100431.6" + wire width 5 $1\dec31_dec_sub28_form[4:0] + attribute \src "libresoc.v:99766.3-99802.6" + wire width 12 $1\dec31_dec_sub28_function_unit[11:0] + attribute \src "libresoc.v:100432.3-100468.6" + wire width 3 $1\dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:100469.3-100505.6" + wire width 4 $1\dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:100506.3-100542.6" + wire width 2 $1\dec31_dec_sub28_in3_sel[1:0] + attribute \src "libresoc.v:100173.3-100209.6" + wire width 7 $1\dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:99988.3-100024.6" + wire $1\dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:100025.3-100061.6" + wire $1\dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:100247.3-100283.6" + wire $1\dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:99803.3-99839.6" + wire width 4 $1\dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:100321.3-100357.6" + wire $1\dec31_dec_sub28_lk[0:0] + attribute \src "libresoc.v:100543.3-100579.6" + wire width 2 $1\dec31_dec_sub28_out_sel[1:0] + attribute \src "libresoc.v:99877.3-99913.6" + wire width 2 $1\dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:100210.3-100246.6" + wire $1\dec31_dec_sub28_rsrv[0:0] + attribute \src "libresoc.v:100358.3-100394.6" + wire $1\dec31_dec_sub28_sgl_pipe[0:0] + attribute \src "libresoc.v:100284.3-100320.6" + wire $1\dec31_dec_sub28_sgn[0:0] + attribute \src "libresoc.v:100136.3-100172.6" + wire $1\dec31_dec_sub28_sgn_ext[0:0] + attribute \src "libresoc.v:99840.3-99876.6" + wire width 2 $1\dec31_dec_sub28_upd[1:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec19_asmcode + wire width 8 output 4 \dec31_dec_sub28_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec19_br + wire output 18 \dec31_dec_sub28_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -10951,7 +156684,7 @@ module \dec19 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec19_cr_in + wire width 3 output 9 \dec31_dec_sub28_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -10959,15 +156692,15 @@ module \dec19 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec19_cr_out + wire width 3 output 10 \dec31_dec_sub28_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec19_cry_in + wire width 2 output 14 \dec31_dec_sub28_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec19_cry_out + wire output 17 \dec31_dec_sub28_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -10999,7 +156732,7 @@ module \dec19 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec19_form + wire width 5 output 3 \dec31_dec_sub28_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -11014,7 +156747,7 @@ module \dec19 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec19_function_unit + wire width 12 output 1 \dec31_dec_sub28_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -11022,7 +156755,7 @@ module \dec19 attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec19_in1_sel + wire width 3 output 5 \dec31_dec_sub28_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -11039,13 +156772,13 @@ module \dec19 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec19_in2_sel + wire width 4 output 6 \dec31_dec_sub28_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec19_in3_sel + wire width 2 output 7 \dec31_dec_sub28_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -11121,13 +156854,13 @@ module \dec19 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec19_internal_op + wire width 7 output 2 \dec31_dec_sub28_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec19_inv_a + wire output 15 \dec31_dec_sub28_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec19_inv_out + wire output 16 \dec31_dec_sub28_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec19_is_32b + wire output 21 \dec31_dec_sub28_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" @@ -11135,2922 +156868,1576 @@ module \dec19 attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec19_ldst_len + wire width 4 output 11 \dec31_dec_sub28_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec19_lk + wire output 23 \dec31_dec_sub28_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec19_out_sel + wire width 2 output 8 \dec31_dec_sub28_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec19_rc_sel + wire width 2 output 13 \dec31_dec_sub28_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec19_rsrv + wire output 20 \dec31_dec_sub28_rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec19_sgl_pipe + wire output 24 \dec31_dec_sub28_sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec19_sgn + wire output 22 \dec31_dec_sub28_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec19_sgn_ext + wire output 19 \dec31_dec_sub28_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec19_upd - attribute \src "libresoc.v:7129.7-7129.15" + wire width 2 output 12 \dec31_dec_sub28_upd + attribute \src "libresoc.v:99509.7-99509.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 25 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 10 \opcode_switch - attribute \src "libresoc.v:7129.7-7129.20" - process $proc$libresoc.v:7129$287 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:7386.3-7437.6" - process $proc$libresoc.v:7386$263 + wire width 5 \opcode_switch + attribute \src "libresoc.v:100025.3-100061.6" + process $proc$libresoc.v:100025$4079 assign { } { } assign { } { } - assign $0\dec19_function_unit[11:0] $1\dec19_function_unit[11:0] - attribute \src "libresoc.v:7387.5-7387.29" + assign $0\dec31_dec_sub28_inv_out[0:0] $1\dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:100026.5-100026.29" switch \initial - attribute \src "libresoc.v:7387.9-7387.17" + attribute \src "libresoc.v:100026.9-100026.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 + case 5'00000 assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 + case 5'00001 assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 + case 5'00111 assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 + case 5'01111 assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 + case 5'01000 assign { } { } - assign $1\dec19_function_unit[11:0] 12'000000100000 + assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 + case 5'01110 assign { } { } - assign $1\dec19_function_unit[11:0] 12'000000100000 + assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 + case 5'00011 assign { } { } - assign $1\dec19_function_unit[11:0] 12'000000100000 + assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 + case 5'01101 assign { } { } - assign $1\dec19_function_unit[11:0] 12'000000000010 + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 + case 5'01100 assign { } { } - assign $1\dec19_function_unit[11:0] 12'000010000000 + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 + case 5'01001 assign { } { } - assign $1\dec19_function_unit[11:0] 12'000010000000 + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 case - assign $1\dec19_function_unit[11:0] 12'000000000000 + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 end sync always - update \dec19_function_unit $0\dec19_function_unit[11:0] + update \dec31_dec_sub28_inv_out $0\dec31_dec_sub28_inv_out[0:0] end - attribute \src "libresoc.v:7438.3-7489.6" - process $proc$libresoc.v:7438$264 + attribute \src "libresoc.v:100062.3-100098.6" + process $proc$libresoc.v:100062$4080 assign { } { } assign { } { } - assign $0\dec19_ldst_len[3:0] $1\dec19_ldst_len[3:0] - attribute \src "libresoc.v:7439.5-7439.29" + assign $0\dec31_dec_sub28_cry_out[0:0] $1\dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:100063.5-100063.29" switch \initial - attribute \src "libresoc.v:7439.9-7439.17" + attribute \src "libresoc.v:100063.9-100063.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 + case 5'00000 assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 + case 5'00001 assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 + case 5'00111 assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 + case 5'01111 assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 + case 5'01000 assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 + case 5'01110 assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 + case 5'00011 assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 + case 5'01101 assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 + case 5'01100 assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 + case 5'01001 assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 case - assign $1\dec19_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 end sync always - update \dec19_ldst_len $0\dec19_ldst_len[3:0] + update \dec31_dec_sub28_cry_out $0\dec31_dec_sub28_cry_out[0:0] end - attribute \src "libresoc.v:7490.3-7541.6" - process $proc$libresoc.v:7490$265 + attribute \src "libresoc.v:100099.3-100135.6" + process $proc$libresoc.v:100099$4081 assign { } { } assign { } { } - assign $0\dec19_upd[1:0] $1\dec19_upd[1:0] - attribute \src "libresoc.v:7491.5-7491.29" + assign $0\dec31_dec_sub28_br[0:0] $1\dec31_dec_sub28_br[0:0] + attribute \src "libresoc.v:100100.5-100100.29" switch \initial - attribute \src "libresoc.v:7491.9-7491.17" + attribute \src "libresoc.v:100100.9-100100.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 + case 5'00000 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 + case 5'00001 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 + case 5'00111 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 + case 5'01111 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 + case 5'01000 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 + case 5'01110 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 + case 5'00011 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 + case 5'01101 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 + case 5'01100 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 + case 5'01001 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_br[0:0] 1'0 case - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_br[0:0] 1'0 end sync always - update \dec19_upd $0\dec19_upd[1:0] + update \dec31_dec_sub28_br $0\dec31_dec_sub28_br[0:0] end - attribute \src "libresoc.v:7542.3-7593.6" - process $proc$libresoc.v:7542$266 + attribute \src "libresoc.v:100136.3-100172.6" + process $proc$libresoc.v:100136$4082 assign { } { } assign { } { } - assign $0\dec19_rc_sel[1:0] $1\dec19_rc_sel[1:0] - attribute \src "libresoc.v:7543.5-7543.29" + assign $0\dec31_dec_sub28_sgn_ext[0:0] $1\dec31_dec_sub28_sgn_ext[0:0] + attribute \src "libresoc.v:100137.5-100137.29" switch \initial - attribute \src "libresoc.v:7543.9-7543.17" + attribute \src "libresoc.v:100137.9-100137.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 + case 5'00000 assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 + case 5'00001 assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 + case 5'00111 assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 + case 5'01111 assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 + case 5'01000 assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 + case 5'01110 assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 + case 5'00011 assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 + case 5'01101 assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 + case 5'01100 assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 + case 5'01001 assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 case - assign $1\dec19_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 end sync always - update \dec19_rc_sel $0\dec19_rc_sel[1:0] + update \dec31_dec_sub28_sgn_ext $0\dec31_dec_sub28_sgn_ext[0:0] end - attribute \src "libresoc.v:7594.3-7645.6" - process $proc$libresoc.v:7594$267 + attribute \src "libresoc.v:100173.3-100209.6" + process $proc$libresoc.v:100173$4083 assign { } { } assign { } { } - assign $0\dec19_cry_in[1:0] $1\dec19_cry_in[1:0] - attribute \src "libresoc.v:7595.5-7595.29" + assign $0\dec31_dec_sub28_internal_op[6:0] $1\dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:100174.5-100174.29" switch \initial - attribute \src "libresoc.v:7595.9-7595.17" + attribute \src "libresoc.v:100174.9-100174.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 + case 5'00000 assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 + case 5'00001 assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 + case 5'00111 assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001001 attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 + case 5'01111 assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001011 attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 + case 5'01000 assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 + case 5'01110 assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 + case 5'00011 assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 + case 5'01101 assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 + case 5'01100 assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 + case 5'01001 assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 case - assign $1\dec19_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000000 end sync always - update \dec19_cry_in $0\dec19_cry_in[1:0] + update \dec31_dec_sub28_internal_op $0\dec31_dec_sub28_internal_op[6:0] end - attribute \src "libresoc.v:7646.3-7697.6" - process $proc$libresoc.v:7646$268 + attribute \src "libresoc.v:100210.3-100246.6" + process $proc$libresoc.v:100210$4084 assign { } { } assign { } { } - assign $0\dec19_asmcode[7:0] $1\dec19_asmcode[7:0] - attribute \src "libresoc.v:7647.5-7647.29" + assign $0\dec31_dec_sub28_rsrv[0:0] $1\dec31_dec_sub28_rsrv[0:0] + attribute \src "libresoc.v:100211.5-100211.29" switch \initial - attribute \src "libresoc.v:7647.9-7647.17" + attribute \src "libresoc.v:100211.9-100211.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'01101100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'00100101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'00100110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'00100111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'00101000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 + case 5'00000 assign { } { } - assign $1\dec19_asmcode[7:0] 8'00101001 + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 + case 5'00001 assign { } { } - assign $1\dec19_asmcode[7:0] 8'00101010 + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 + case 5'00111 assign { } { } - assign $1\dec19_asmcode[7:0] 8'00101011 + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 + case 5'01111 assign { } { } - assign $1\dec19_asmcode[7:0] 8'00101100 + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 + case 5'01000 assign { } { } - assign $1\dec19_asmcode[7:0] 8'00010110 + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 + case 5'01110 assign { } { } - assign $1\dec19_asmcode[7:0] 8'00010111 + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 + case 5'00011 assign { } { } - assign $1\dec19_asmcode[7:0] 8'00011000 + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 + case 5'01101 assign { } { } - assign $1\dec19_asmcode[7:0] 8'01001100 + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 + case 5'01100 assign { } { } - assign $1\dec19_asmcode[7:0] 8'10010001 + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 + case 5'01001 assign { } { } - assign $1\dec19_asmcode[7:0] 8'01001000 + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 case - assign $1\dec19_asmcode[7:0] 8'00000000 + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 end sync always - update \dec19_asmcode $0\dec19_asmcode[7:0] + update \dec31_dec_sub28_rsrv $0\dec31_dec_sub28_rsrv[0:0] end - attribute \src "libresoc.v:7698.3-7749.6" - process $proc$libresoc.v:7698$269 + attribute \src "libresoc.v:100247.3-100283.6" + process $proc$libresoc.v:100247$4085 assign { } { } assign { } { } - assign $0\dec19_inv_a[0:0] $1\dec19_inv_a[0:0] - attribute \src "libresoc.v:7699.5-7699.29" + assign $0\dec31_dec_sub28_is_32b[0:0] $1\dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:100248.5-100248.29" switch \initial - attribute \src "libresoc.v:7699.9-7699.17" + attribute \src "libresoc.v:100248.9-100248.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 + case 5'00000 assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 + case 5'00001 assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 + case 5'00111 assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 + case 5'01111 assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 + case 5'01000 assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 + case 5'01110 assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 + case 5'00011 assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 + case 5'01101 assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 + case 5'01100 assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 + case 5'01001 assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 case - assign $1\dec19_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 end sync always - update \dec19_inv_a $0\dec19_inv_a[0:0] + update \dec31_dec_sub28_is_32b $0\dec31_dec_sub28_is_32b[0:0] end - attribute \src "libresoc.v:7750.3-7801.6" - process $proc$libresoc.v:7750$270 + attribute \src "libresoc.v:100284.3-100320.6" + process $proc$libresoc.v:100284$4086 assign { } { } assign { } { } - assign $0\dec19_inv_out[0:0] $1\dec19_inv_out[0:0] - attribute \src "libresoc.v:7751.5-7751.29" + assign $0\dec31_dec_sub28_sgn[0:0] $1\dec31_dec_sub28_sgn[0:0] + attribute \src "libresoc.v:100285.5-100285.29" switch \initial - attribute \src "libresoc.v:7751.9-7751.17" + attribute \src "libresoc.v:100285.9-100285.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 + case 5'00000 assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 + case 5'00001 assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 + case 5'00111 assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 + case 5'01111 assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 + case 5'01000 assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 + case 5'01110 assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 + case 5'00011 assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 + case 5'01101 assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 + case 5'01100 assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 + case 5'01001 assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 case - assign $1\dec19_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 end sync always - update \dec19_inv_out $0\dec19_inv_out[0:0] + update \dec31_dec_sub28_sgn $0\dec31_dec_sub28_sgn[0:0] end - attribute \src "libresoc.v:7802.3-7853.6" - process $proc$libresoc.v:7802$271 + attribute \src "libresoc.v:100321.3-100357.6" + process $proc$libresoc.v:100321$4087 assign { } { } assign { } { } - assign $0\dec19_cry_out[0:0] $1\dec19_cry_out[0:0] - attribute \src "libresoc.v:7803.5-7803.29" + assign $0\dec31_dec_sub28_lk[0:0] $1\dec31_dec_sub28_lk[0:0] + attribute \src "libresoc.v:100322.5-100322.29" switch \initial - attribute \src "libresoc.v:7803.9-7803.17" + attribute \src "libresoc.v:100322.9-100322.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 + case 5'00000 assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub28_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 + case 5'00001 assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub28_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 + case 5'00111 assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub28_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 + case 5'01111 assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub28_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 + case 5'01000 assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub28_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 + case 5'01110 assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub28_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 + case 5'00011 assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub28_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 + case 5'01101 assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub28_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 + case 5'01100 assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub28_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 + case 5'01001 assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub28_lk[0:0] 1'0 case - assign $1\dec19_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub28_lk[0:0] 1'0 end sync always - update \dec19_cry_out $0\dec19_cry_out[0:0] + update \dec31_dec_sub28_lk $0\dec31_dec_sub28_lk[0:0] end - attribute \src "libresoc.v:7854.3-7905.6" - process $proc$libresoc.v:7854$272 + attribute \src "libresoc.v:100358.3-100394.6" + process $proc$libresoc.v:100358$4088 assign { } { } assign { } { } - assign $0\dec19_br[0:0] $1\dec19_br[0:0] - attribute \src "libresoc.v:7855.5-7855.29" + assign $0\dec31_dec_sub28_sgl_pipe[0:0] $1\dec31_dec_sub28_sgl_pipe[0:0] + attribute \src "libresoc.v:100359.5-100359.29" switch \initial - attribute \src "libresoc.v:7855.9-7855.17" + attribute \src "libresoc.v:100359.9-100359.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 + case 5'00000 assign { } { } - assign $1\dec19_br[0:0] 1'0 + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 + case 5'00001 assign { } { } - assign $1\dec19_br[0:0] 1'0 + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 + case 5'00111 assign { } { } - assign $1\dec19_br[0:0] 1'0 + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 + case 5'01111 assign { } { } - assign $1\dec19_br[0:0] 1'0 + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 + case 5'01000 assign { } { } - assign $1\dec19_br[0:0] 1'0 + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 + case 5'01110 assign { } { } - assign $1\dec19_br[0:0] 1'0 + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 + case 5'00011 assign { } { } - assign $1\dec19_br[0:0] 1'0 + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 + case 5'01101 assign { } { } - assign $1\dec19_br[0:0] 1'0 + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 + case 5'01100 assign { } { } - assign $1\dec19_br[0:0] 1'0 + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 + case 5'01001 assign { } { } - assign $1\dec19_br[0:0] 1'0 + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 case - assign $1\dec19_br[0:0] 1'0 + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 end sync always - update \dec19_br $0\dec19_br[0:0] + update \dec31_dec_sub28_sgl_pipe $0\dec31_dec_sub28_sgl_pipe[0:0] end - attribute \src "libresoc.v:7906.3-7957.6" - process $proc$libresoc.v:7906$273 + attribute \src "libresoc.v:100395.3-100431.6" + process $proc$libresoc.v:100395$4089 assign { } { } assign { } { } - assign $0\dec19_sgn_ext[0:0] $1\dec19_sgn_ext[0:0] - attribute \src "libresoc.v:7907.5-7907.29" + assign $0\dec31_dec_sub28_form[4:0] $1\dec31_dec_sub28_form[4:0] + attribute \src "libresoc.v:100396.5-100396.29" switch \initial - attribute \src "libresoc.v:7907.9-7907.17" + attribute \src "libresoc.v:100396.9-100396.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 + case 5'00000 assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 + case 5'00001 assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 + case 5'00111 assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 + case 5'01111 assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 + case 5'01000 assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 + case 5'01110 assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 + case 5'00011 assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 + case 5'01101 assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 + case 5'01100 assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 + case 5'01001 assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub28_form[4:0] 5'01000 case - assign $1\dec19_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub28_form[4:0] 5'00000 end sync always - update \dec19_sgn_ext $0\dec19_sgn_ext[0:0] + update \dec31_dec_sub28_form $0\dec31_dec_sub28_form[4:0] end - attribute \src "libresoc.v:7958.3-8009.6" - process $proc$libresoc.v:7958$274 + attribute \src "libresoc.v:100432.3-100468.6" + process $proc$libresoc.v:100432$4090 assign { } { } assign { } { } - assign $0\dec19_internal_op[6:0] $1\dec19_internal_op[6:0] - attribute \src "libresoc.v:7959.5-7959.29" + assign $0\dec31_dec_sub28_in1_sel[2:0] $1\dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:100433.5-100433.29" switch \initial - attribute \src "libresoc.v:7959.9-7959.17" + attribute \src "libresoc.v:100433.9-100433.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'0101010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 + case 5'00000 assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 + case 5'00001 assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 + case 5'00111 assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 + case 5'01111 assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 + case 5'01000 assign { } { } - assign $1\dec19_internal_op[6:0] 7'0001000 + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 + case 5'01110 assign { } { } - assign $1\dec19_internal_op[6:0] 7'0001000 + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 + case 5'00011 assign { } { } - assign $1\dec19_internal_op[6:0] 7'0001000 + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 + case 5'01101 assign { } { } - assign $1\dec19_internal_op[6:0] 7'0100100 + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 + case 5'01100 assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000110 + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 + case 5'01001 assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000110 + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 case - assign $1\dec19_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'000 end sync always - update \dec19_internal_op $0\dec19_internal_op[6:0] + update \dec31_dec_sub28_in1_sel $0\dec31_dec_sub28_in1_sel[2:0] end - attribute \src "libresoc.v:8010.3-8061.6" - process $proc$libresoc.v:8010$275 + attribute \src "libresoc.v:100469.3-100505.6" + process $proc$libresoc.v:100469$4091 assign { } { } assign { } { } - assign $0\dec19_rsrv[0:0] $1\dec19_rsrv[0:0] - attribute \src "libresoc.v:8011.5-8011.29" + assign $0\dec31_dec_sub28_in2_sel[3:0] $1\dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:100470.5-100470.29" switch \initial - attribute \src "libresoc.v:8011.9-8011.17" + attribute \src "libresoc.v:100470.9-100470.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 + case 5'00000 assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 + case 5'00001 assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 + case 5'00111 assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 + case 5'01111 assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 + case 5'01000 assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 + case 5'01110 assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 + case 5'00011 assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 + case 5'01101 assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 + case 5'01100 assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 + case 5'01001 assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 case - assign $1\dec19_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0000 end sync always - update \dec19_rsrv $0\dec19_rsrv[0:0] + update \dec31_dec_sub28_in2_sel $0\dec31_dec_sub28_in2_sel[3:0] end - attribute \src "libresoc.v:8062.3-8113.6" - process $proc$libresoc.v:8062$276 + attribute \src "libresoc.v:100506.3-100542.6" + process $proc$libresoc.v:100506$4092 assign { } { } assign { } { } - assign $0\dec19_is_32b[0:0] $1\dec19_is_32b[0:0] - attribute \src "libresoc.v:8063.5-8063.29" + assign $0\dec31_dec_sub28_in3_sel[1:0] $1\dec31_dec_sub28_in3_sel[1:0] + attribute \src "libresoc.v:100507.5-100507.29" switch \initial - attribute \src "libresoc.v:8063.9-8063.17" + attribute \src "libresoc.v:100507.9-100507.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 + case 5'00000 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 + case 5'00001 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 + case 5'00111 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 + case 5'01111 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 + case 5'01000 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 + case 5'01110 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 + case 5'00011 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 + case 5'01101 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 + case 5'01100 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 + case 5'01001 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 case - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 end sync always - update \dec19_is_32b $0\dec19_is_32b[0:0] + update \dec31_dec_sub28_in3_sel $0\dec31_dec_sub28_in3_sel[1:0] end - attribute \src "libresoc.v:8114.3-8165.6" - process $proc$libresoc.v:8114$277 + attribute \src "libresoc.v:100543.3-100579.6" + process $proc$libresoc.v:100543$4093 assign { } { } assign { } { } - assign $0\dec19_sgn[0:0] $1\dec19_sgn[0:0] - attribute \src "libresoc.v:8115.5-8115.29" + assign $0\dec31_dec_sub28_out_sel[1:0] $1\dec31_dec_sub28_out_sel[1:0] + attribute \src "libresoc.v:100544.5-100544.29" switch \initial - attribute \src "libresoc.v:8115.9-8115.17" + attribute \src "libresoc.v:100544.9-100544.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 + case 5'00000 assign { } { } - assign $1\dec19_sgn[0:0] 1'0 + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 + case 5'00001 assign { } { } - assign $1\dec19_sgn[0:0] 1'0 + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 + case 5'00111 assign { } { } - assign $1\dec19_sgn[0:0] 1'0 + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 + case 5'01111 assign { } { } - assign $1\dec19_sgn[0:0] 1'0 + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 + case 5'01000 assign { } { } - assign $1\dec19_sgn[0:0] 1'0 + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 + case 5'01110 assign { } { } - assign $1\dec19_sgn[0:0] 1'0 + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 + case 5'00011 assign { } { } - assign $1\dec19_sgn[0:0] 1'0 + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 + case 5'01101 assign { } { } - assign $1\dec19_sgn[0:0] 1'0 + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 + case 5'01100 assign { } { } - assign $1\dec19_sgn[0:0] 1'0 + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 + case 5'01001 assign { } { } - assign $1\dec19_sgn[0:0] 1'0 + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 case - assign $1\dec19_sgn[0:0] 1'0 + assign $1\dec31_dec_sub28_out_sel[1:0] 2'00 end sync always - update \dec19_sgn $0\dec19_sgn[0:0] + update \dec31_dec_sub28_out_sel $0\dec31_dec_sub28_out_sel[1:0] end - attribute \src "libresoc.v:8166.3-8217.6" - process $proc$libresoc.v:8166$278 + attribute \src "libresoc.v:100580.3-100616.6" + process $proc$libresoc.v:100580$4094 assign { } { } assign { } { } - assign $0\dec19_lk[0:0] $1\dec19_lk[0:0] - attribute \src "libresoc.v:8167.5-8167.29" + assign $0\dec31_dec_sub28_cr_in[2:0] $1\dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:100581.5-100581.29" switch \initial - attribute \src "libresoc.v:8167.9-8167.17" + attribute \src "libresoc.v:100581.9-100581.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 + case 5'00000 assign { } { } - assign $1\dec19_lk[0:0] 1'0 + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 + case 5'00001 assign { } { } - assign $1\dec19_lk[0:0] 1'0 + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 + case 5'00111 assign { } { } - assign $1\dec19_lk[0:0] 1'0 + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 + case 5'01111 assign { } { } - assign $1\dec19_lk[0:0] 1'0 + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 + case 5'01000 assign { } { } - assign $1\dec19_lk[0:0] 1'1 + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 + case 5'01110 assign { } { } - assign $1\dec19_lk[0:0] 1'1 + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 + case 5'00011 assign { } { } - assign $1\dec19_lk[0:0] 1'1 + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 + case 5'01101 assign { } { } - assign $1\dec19_lk[0:0] 1'0 + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 + case 5'01100 assign { } { } - assign $1\dec19_lk[0:0] 1'0 + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 + case 5'01001 assign { } { } - assign $1\dec19_lk[0:0] 1'0 + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 case - assign $1\dec19_lk[0:0] 1'0 + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 end sync always - update \dec19_lk $0\dec19_lk[0:0] + update \dec31_dec_sub28_cr_in $0\dec31_dec_sub28_cr_in[2:0] end - attribute \src "libresoc.v:8218.3-8269.6" - process $proc$libresoc.v:8218$279 + attribute \src "libresoc.v:100617.3-100653.6" + process $proc$libresoc.v:100617$4095 assign { } { } assign { } { } - assign $0\dec19_sgl_pipe[0:0] $1\dec19_sgl_pipe[0:0] - attribute \src "libresoc.v:8219.5-8219.29" + assign $0\dec31_dec_sub28_cr_out[2:0] $1\dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:100618.5-100618.29" switch \initial - attribute \src "libresoc.v:8219.9-8219.17" + attribute \src "libresoc.v:100618.9-100618.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 + case 5'00000 assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 + case 5'00001 assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 + case 5'00111 assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 + case 5'01111 assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 + case 5'01000 assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 + case 5'01110 assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 + case 5'00011 assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 + case 5'01101 assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'1 + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 + case 5'01100 assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 + case 5'01001 assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 case - assign $1\dec19_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 end sync always - update \dec19_sgl_pipe $0\dec19_sgl_pipe[0:0] + update \dec31_dec_sub28_cr_out $0\dec31_dec_sub28_cr_out[2:0] + end + attribute \src "libresoc.v:99509.7-99509.20" + process $proc$libresoc.v:99509$4096 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:8270.3-8321.6" - process $proc$libresoc.v:8270$280 + attribute \src "libresoc.v:99766.3-99802.6" + process $proc$libresoc.v:99766$4072 assign { } { } assign { } { } - assign $0\dec19_form[4:0] $1\dec19_form[4:0] - attribute \src "libresoc.v:8271.5-8271.29" + assign $0\dec31_dec_sub28_function_unit[11:0] $1\dec31_dec_sub28_function_unit[11:0] + attribute \src "libresoc.v:99767.5-99767.29" switch \initial - attribute \src "libresoc.v:8271.9-8271.17" + attribute \src "libresoc.v:99767.9-99767.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 + case 5'00000 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 + case 5'00001 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 + case 5'00111 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 + case 5'01111 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 + case 5'01000 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 + case 5'01110 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 + case 5'00011 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 + case 5'01101 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 + case 5'01100 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 + case 5'01001 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 case - assign $1\dec19_form[4:0] 5'00000 + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000000000 end sync always - update \dec19_form $0\dec19_form[4:0] + update \dec31_dec_sub28_function_unit $0\dec31_dec_sub28_function_unit[11:0] end - attribute \src "libresoc.v:8322.3-8373.6" - process $proc$libresoc.v:8322$281 + attribute \src "libresoc.v:99803.3-99839.6" + process $proc$libresoc.v:99803$4073 assign { } { } assign { } { } - assign $0\dec19_in1_sel[2:0] $1\dec19_in1_sel[2:0] - attribute \src "libresoc.v:8323.5-8323.29" + assign $0\dec31_dec_sub28_ldst_len[3:0] $1\dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:99804.5-99804.29" switch \initial - attribute \src "libresoc.v:8323.9-8323.17" + attribute \src "libresoc.v:99804.9-99804.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 + case 5'00000 assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 + case 5'00001 assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 + case 5'00111 assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 + case 5'01111 assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 + case 5'01000 assign { } { } - assign $1\dec19_in1_sel[2:0] 3'011 + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 + case 5'01110 assign { } { } - assign $1\dec19_in1_sel[2:0] 3'011 + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 + case 5'00011 assign { } { } - assign $1\dec19_in1_sel[2:0] 3'011 + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 + case 5'01101 assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 + case 5'01100 assign { } { } - assign $1\dec19_in1_sel[2:0] 3'011 + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 + case 5'01001 assign { } { } - assign $1\dec19_in1_sel[2:0] 3'011 + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 case - assign $1\dec19_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 end sync always - update \dec19_in1_sel $0\dec19_in1_sel[2:0] + update \dec31_dec_sub28_ldst_len $0\dec31_dec_sub28_ldst_len[3:0] end - attribute \src "libresoc.v:8374.3-8425.6" - process $proc$libresoc.v:8374$282 + attribute \src "libresoc.v:99840.3-99876.6" + process $proc$libresoc.v:99840$4074 assign { } { } assign { } { } - assign $0\dec19_in2_sel[3:0] $1\dec19_in2_sel[3:0] - attribute \src "libresoc.v:8375.5-8375.29" + assign $0\dec31_dec_sub28_upd[1:0] $1\dec31_dec_sub28_upd[1:0] + attribute \src "libresoc.v:99841.5-99841.29" switch \initial - attribute \src "libresoc.v:8375.9-8375.17" + attribute \src "libresoc.v:99841.9-99841.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 + case 5'00000 assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 + case 5'00001 assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 + case 5'00111 assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 + case 5'01111 assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 + case 5'01000 assign { } { } - assign $1\dec19_in2_sel[3:0] 4'1100 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 + case 5'01110 assign { } { } - assign $1\dec19_in2_sel[3:0] 4'1100 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 + case 5'00011 assign { } { } - assign $1\dec19_in2_sel[3:0] 4'1100 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 + case 5'01101 assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 + case 5'01100 assign { } { } - assign $1\dec19_in2_sel[3:0] 4'1100 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 + case 5'01001 assign { } { } - assign $1\dec19_in2_sel[3:0] 4'1100 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 case - assign $1\dec19_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 end sync always - update \dec19_in2_sel $0\dec19_in2_sel[3:0] + update \dec31_dec_sub28_upd $0\dec31_dec_sub28_upd[1:0] end - attribute \src "libresoc.v:8426.3-8477.6" - process $proc$libresoc.v:8426$283 + attribute \src "libresoc.v:99877.3-99913.6" + process $proc$libresoc.v:99877$4075 assign { } { } assign { } { } - assign $0\dec19_in3_sel[1:0] $1\dec19_in3_sel[1:0] - attribute \src "libresoc.v:8427.5-8427.29" + assign $0\dec31_dec_sub28_rc_sel[1:0] $1\dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:99878.5-99878.29" switch \initial - attribute \src "libresoc.v:8427.9-8427.17" + attribute \src "libresoc.v:99878.9-99878.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 + case 5'00000 assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 + case 5'00001 assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 + case 5'00111 assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 + case 5'01111 assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 + case 5'01000 assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 + case 5'01110 assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 + case 5'00011 assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 + case 5'01101 assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 + case 5'01100 assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 + case 5'01001 assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 case - assign $1\dec19_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 end sync always - update \dec19_in3_sel $0\dec19_in3_sel[1:0] + update \dec31_dec_sub28_rc_sel $0\dec31_dec_sub28_rc_sel[1:0] end - attribute \src "libresoc.v:8478.3-8529.6" - process $proc$libresoc.v:8478$284 + attribute \src "libresoc.v:99914.3-99950.6" + process $proc$libresoc.v:99914$4076 assign { } { } assign { } { } - assign $0\dec19_out_sel[1:0] $1\dec19_out_sel[1:0] - attribute \src "libresoc.v:8479.5-8479.29" + assign $0\dec31_dec_sub28_cry_in[1:0] $1\dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:99915.5-99915.29" switch \initial - attribute \src "libresoc.v:8479.9-8479.17" + attribute \src "libresoc.v:99915.9-99915.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 + case 5'00000 assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 + case 5'00001 assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 + case 5'00111 assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 + case 5'01111 assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 + case 5'01000 assign { } { } - assign $1\dec19_out_sel[1:0] 2'11 + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 + case 5'01110 assign { } { } - assign $1\dec19_out_sel[1:0] 2'11 + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 + case 5'00011 assign { } { } - assign $1\dec19_out_sel[1:0] 2'11 + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 + case 5'01101 assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 + case 5'01100 assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 + case 5'01001 assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 case - assign $1\dec19_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 end sync always - update \dec19_out_sel $0\dec19_out_sel[1:0] + update \dec31_dec_sub28_cry_in $0\dec31_dec_sub28_cry_in[1:0] end - attribute \src "libresoc.v:8530.3-8581.6" - process $proc$libresoc.v:8530$285 + attribute \src "libresoc.v:99951.3-99987.6" + process $proc$libresoc.v:99951$4077 assign { } { } assign { } { } - assign $0\dec19_cr_in[2:0] $1\dec19_cr_in[2:0] - attribute \src "libresoc.v:8531.5-8531.29" + assign $0\dec31_dec_sub28_asmcode[7:0] $1\dec31_dec_sub28_asmcode[7:0] + attribute \src "libresoc.v:99952.5-99952.29" switch \initial - attribute \src "libresoc.v:8531.9-8531.17" + attribute \src "libresoc.v:99952.9-99952.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 + case 5'00000 assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00001111 attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 + case 5'00001 assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00010000 attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 + case 5'00111 assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00011001 attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 + case 5'01111 assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00011011 attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 + case 5'01000 assign { } { } - assign $1\dec19_cr_in[2:0] 3'010 + assign $1\dec31_dec_sub28_asmcode[7:0] 8'01000011 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 + case 5'01110 assign { } { } - assign $1\dec19_cr_in[2:0] 3'010 + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10000011 attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 + case 5'00011 assign { } { } - assign $1\dec19_cr_in[2:0] 3'010 + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10000111 attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 + case 5'01101 assign { } { } - assign $1\dec19_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10001000 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 + case 5'01100 assign { } { } - assign $1\dec19_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10001001 attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 + case 5'01001 assign { } { } - assign $1\dec19_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub28_asmcode[7:0] 8'11010000 case - assign $1\dec19_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00000000 end sync always - update \dec19_cr_in $0\dec19_cr_in[2:0] + update \dec31_dec_sub28_asmcode $0\dec31_dec_sub28_asmcode[7:0] end - attribute \src "libresoc.v:8582.3-8633.6" - process $proc$libresoc.v:8582$286 + attribute \src "libresoc.v:99988.3-100024.6" + process $proc$libresoc.v:99988$4078 assign { } { } assign { } { } - assign $0\dec19_cr_out[2:0] $1\dec19_cr_out[2:0] - attribute \src "libresoc.v:8583.5-8583.29" + assign $0\dec31_dec_sub28_inv_a[0:0] $1\dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:99989.5-99989.29" switch \initial - attribute \src "libresoc.v:8583.9-8583.17" + attribute \src "libresoc.v:99989.9-99989.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 + case 5'00000 assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 + case 5'00001 assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 + assign $1\dec31_dec_sub28_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 + case 5'00111 assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 + case 5'01111 assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 + case 5'01000 assign { } { } - assign $1\dec19_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 + case 5'01110 assign { } { } - assign $1\dec19_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 + case 5'00011 assign { } { } - assign $1\dec19_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 + case 5'01101 assign { } { } - assign $1\dec19_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 + case 5'01100 assign { } { } - assign $1\dec19_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub28_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 + case 5'01001 assign { } { } - assign $1\dec19_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 case - assign $1\dec19_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 end sync always - update \dec19_cr_out $0\dec19_cr_out[2:0] + update \dec31_dec_sub28_inv_a $0\dec31_dec_sub28_inv_a[0:0] end - connect \opcode_switch \opcode_in [10:1] + connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:8639.1-10676.10" +attribute \src "libresoc.v:100659.1-101230.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub4" attribute \generator "nMigen" -module \dec2 - attribute \src "libresoc.v:10450.3-10607.6" - wire width 8 $0\asmcode[7:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 64 $0\cia[63:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 3 $0\cr_in1[2:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $0\cr_in1_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 3 $0\cr_in2$1[2:0]$306 - attribute \src "libresoc.v:10450.3-10607.6" - wire width 3 $0\cr_in2[2:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $0\cr_in2_ok$2[0:0]$307 - attribute \src "libresoc.v:10450.3-10607.6" - wire $0\cr_in2_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 3 $0\cr_out[2:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $0\cr_out_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 8 $0\cr_rd[7:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $0\cr_rd_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 8 $0\cr_wr[7:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $0\cr_wr_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 5 $0\ea[4:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $0\ea_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $0\exc_$signal$3[0:0]$309 - attribute \src "libresoc.v:10450.3-10607.6" - wire $0\exc_$signal$4[0:0]$310 - attribute \src "libresoc.v:10450.3-10607.6" - wire $0\exc_$signal$5[0:0]$311 - attribute \src "libresoc.v:10450.3-10607.6" - wire $0\exc_$signal$6[0:0]$312 - attribute \src "libresoc.v:10450.3-10607.6" - wire $0\exc_$signal$7[0:0]$313 - attribute \src "libresoc.v:10450.3-10607.6" - wire $0\exc_$signal$8[0:0]$314 - attribute \src "libresoc.v:10450.3-10607.6" - wire $0\exc_$signal$9[0:0]$315 - attribute \src "libresoc.v:10450.3-10607.6" - wire $0\exc_$signal[0:0]$308 - attribute \src "libresoc.v:10450.3-10607.6" - wire width 3 $0\fast1[2:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 3 $0\fast2[2:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 3 $0\fasto1[2:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $0\fasto1_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 3 $0\fasto2[2:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $0\fasto2_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 12 $0\fn_unit[11:0] - attribute \src "libresoc.v:8640.7-8640.20" +module \dec31_dec_sub4 + attribute \src "libresoc.v:100982.3-100994.6" + wire width 8 $0\dec31_dec_sub4_asmcode[7:0] + attribute \src "libresoc.v:101034.3-101046.6" + wire $0\dec31_dec_sub4_br[0:0] + attribute \src "libresoc.v:101203.3-101215.6" + wire width 3 $0\dec31_dec_sub4_cr_in[2:0] + attribute \src "libresoc.v:101216.3-101228.6" + wire width 3 $0\dec31_dec_sub4_cr_out[2:0] + attribute \src "libresoc.v:100969.3-100981.6" + wire width 2 $0\dec31_dec_sub4_cry_in[1:0] + attribute \src "libresoc.v:101021.3-101033.6" + wire $0\dec31_dec_sub4_cry_out[0:0] + attribute \src "libresoc.v:101138.3-101150.6" + wire width 5 $0\dec31_dec_sub4_form[4:0] + attribute \src "libresoc.v:100917.3-100929.6" + wire width 12 $0\dec31_dec_sub4_function_unit[11:0] + attribute \src "libresoc.v:101151.3-101163.6" + wire width 3 $0\dec31_dec_sub4_in1_sel[2:0] + attribute \src "libresoc.v:101164.3-101176.6" + wire width 4 $0\dec31_dec_sub4_in2_sel[3:0] + attribute \src "libresoc.v:101177.3-101189.6" + wire width 2 $0\dec31_dec_sub4_in3_sel[1:0] + attribute \src "libresoc.v:101060.3-101072.6" + wire width 7 $0\dec31_dec_sub4_internal_op[6:0] + attribute \src "libresoc.v:100995.3-101007.6" + wire $0\dec31_dec_sub4_inv_a[0:0] + attribute \src "libresoc.v:101008.3-101020.6" + wire $0\dec31_dec_sub4_inv_out[0:0] + attribute \src "libresoc.v:101086.3-101098.6" + wire $0\dec31_dec_sub4_is_32b[0:0] + attribute \src "libresoc.v:100930.3-100942.6" + wire width 4 $0\dec31_dec_sub4_ldst_len[3:0] + attribute \src "libresoc.v:101112.3-101124.6" + wire $0\dec31_dec_sub4_lk[0:0] + attribute \src "libresoc.v:101190.3-101202.6" + wire width 2 $0\dec31_dec_sub4_out_sel[1:0] + attribute \src "libresoc.v:100956.3-100968.6" + wire width 2 $0\dec31_dec_sub4_rc_sel[1:0] + attribute \src "libresoc.v:101073.3-101085.6" + wire $0\dec31_dec_sub4_rsrv[0:0] + attribute \src "libresoc.v:101125.3-101137.6" + wire $0\dec31_dec_sub4_sgl_pipe[0:0] + attribute \src "libresoc.v:101099.3-101111.6" + wire $0\dec31_dec_sub4_sgn[0:0] + attribute \src "libresoc.v:101047.3-101059.6" + wire $0\dec31_dec_sub4_sgn_ext[0:0] + attribute \src "libresoc.v:100943.3-100955.6" + wire width 2 $0\dec31_dec_sub4_upd[1:0] + attribute \src "libresoc.v:100660.7-100660.20" wire $0\initial[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 2 $0\input_carry[1:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 32 $0\insn[31:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 7 $0\insn_type[6:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $0\is_32bit[0:0] - attribute \src "libresoc.v:10430.3-10449.6" - wire $0\is_priv_insn[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $0\lk[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 64 $0\msr[63:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $0\oe[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $0\oe_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $0\rc[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $0\rc_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 5 $0\reg1[4:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $0\reg1_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 5 $0\reg2[4:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $0\reg2_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 5 $0\reg3[4:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $0\reg3_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 5 $0\rego[4:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $0\rego_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 10 $0\spr1[9:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $0\spr1_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 10 $0\spro[9:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $0\spro_ok[0:0] - attribute \src "libresoc.v:10384.3-10393.6" - wire $0\tmp_tmp_lk[0:0] - attribute \src "libresoc.v:10420.3-10429.6" - wire width 13 $0\tmp_tmp_trapaddr[12:0] - attribute \src "libresoc.v:10394.3-10409.6" - wire width 3 $0\tmp_xer_in[2:0] - attribute \src "libresoc.v:10410.3-10419.6" - wire $0\tmp_xer_out[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 13 $0\trapaddr[12:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 8 $0\traptype[7:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 3 $0\xer_in[2:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $0\xer_out[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 8 $1\asmcode[7:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 64 $1\cia[63:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 3 $1\cr_in1[2:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $1\cr_in1_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 3 $1\cr_in2$1[2:0]$316 - attribute \src "libresoc.v:10450.3-10607.6" - wire width 3 $1\cr_in2[2:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $1\cr_in2_ok$2[0:0]$317 - attribute \src "libresoc.v:10450.3-10607.6" - wire $1\cr_in2_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 3 $1\cr_out[2:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $1\cr_out_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 8 $1\cr_rd[7:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $1\cr_rd_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 8 $1\cr_wr[7:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $1\cr_wr_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 5 $1\ea[4:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $1\ea_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $1\exc_$signal$3[0:0]$319 - attribute \src "libresoc.v:10450.3-10607.6" - wire $1\exc_$signal$4[0:0]$320 - attribute \src "libresoc.v:10450.3-10607.6" - wire $1\exc_$signal$5[0:0]$321 - attribute \src "libresoc.v:10450.3-10607.6" - wire $1\exc_$signal$6[0:0]$322 - attribute \src "libresoc.v:10450.3-10607.6" - wire $1\exc_$signal$7[0:0]$323 - attribute \src "libresoc.v:10450.3-10607.6" - wire $1\exc_$signal$8[0:0]$324 - attribute \src "libresoc.v:10450.3-10607.6" - wire $1\exc_$signal$9[0:0]$325 - attribute \src "libresoc.v:10450.3-10607.6" - wire $1\exc_$signal[0:0]$318 - attribute \src "libresoc.v:10450.3-10607.6" - wire width 3 $1\fast1[2:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 3 $1\fast2[2:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 3 $1\fasto1[2:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $1\fasto1_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 3 $1\fasto2[2:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $1\fasto2_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 12 $1\fn_unit[11:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 2 $1\input_carry[1:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 32 $1\insn[31:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 7 $1\insn_type[6:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $1\is_32bit[0:0] - attribute \src "libresoc.v:10430.3-10449.6" - wire $1\is_priv_insn[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $1\lk[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 64 $1\msr[63:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $1\oe[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $1\oe_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $1\rc[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $1\rc_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 5 $1\reg1[4:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $1\reg1_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 5 $1\reg2[4:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $1\reg2_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 5 $1\reg3[4:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $1\reg3_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 5 $1\rego[4:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $1\rego_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 10 $1\spr1[9:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $1\spr1_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 10 $1\spro[9:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $1\spro_ok[0:0] - attribute \src "libresoc.v:10384.3-10393.6" - wire $1\tmp_tmp_lk[0:0] - attribute \src "libresoc.v:10420.3-10429.6" - wire width 13 $1\tmp_tmp_trapaddr[12:0] - attribute \src "libresoc.v:10394.3-10409.6" - wire width 3 $1\tmp_xer_in[2:0] - attribute \src "libresoc.v:10410.3-10419.6" - wire $1\tmp_xer_out[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 13 $1\trapaddr[12:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 8 $1\traptype[7:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 3 $1\xer_in[2:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $1\xer_out[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 8 $2\asmcode[7:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 64 $2\cia[63:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 3 $2\cr_in1[2:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $2\cr_in1_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 3 $2\cr_in2$1[2:0]$326 - attribute \src "libresoc.v:10450.3-10607.6" - wire width 3 $2\cr_in2[2:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $2\cr_in2_ok$2[0:0]$327 - attribute \src "libresoc.v:10450.3-10607.6" - wire $2\cr_in2_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 3 $2\cr_out[2:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $2\cr_out_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 8 $2\cr_rd[7:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $2\cr_rd_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 8 $2\cr_wr[7:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $2\cr_wr_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 5 $2\ea[4:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $2\ea_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $2\exc_$signal$3[0:0]$329 - attribute \src "libresoc.v:10450.3-10607.6" - wire $2\exc_$signal$4[0:0]$330 - attribute \src "libresoc.v:10450.3-10607.6" - wire $2\exc_$signal$5[0:0]$331 - attribute \src "libresoc.v:10450.3-10607.6" - wire $2\exc_$signal$6[0:0]$332 - attribute \src "libresoc.v:10450.3-10607.6" - wire $2\exc_$signal$7[0:0]$333 - attribute \src "libresoc.v:10450.3-10607.6" - wire $2\exc_$signal$8[0:0]$334 - attribute \src "libresoc.v:10450.3-10607.6" - wire $2\exc_$signal$9[0:0]$335 - attribute \src "libresoc.v:10450.3-10607.6" - wire $2\exc_$signal[0:0]$328 - attribute \src "libresoc.v:10450.3-10607.6" - wire width 3 $2\fast1[2:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $2\fast1_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 3 $2\fast2[2:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $2\fast2_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 3 $2\fasto1[2:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $2\fasto1_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 3 $2\fasto2[2:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $2\fasto2_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 12 $2\fn_unit[11:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 2 $2\input_carry[1:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 32 $2\insn[31:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 7 $2\insn_type[6:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $2\is_32bit[0:0] - attribute \src "libresoc.v:10430.3-10449.6" - wire $2\is_priv_insn[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $2\lk[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 64 $2\msr[63:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $2\oe[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $2\oe_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $2\rc[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $2\rc_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 5 $2\reg1[4:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $2\reg1_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 5 $2\reg2[4:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $2\reg2_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 5 $2\reg3[4:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $2\reg3_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 5 $2\rego[4:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $2\rego_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 10 $2\spr1[9:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $2\spr1_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 10 $2\spro[9:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $2\spro_ok[0:0] - attribute \src "libresoc.v:10394.3-10409.6" - wire width 3 $2\tmp_xer_in[2:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 13 $2\trapaddr[12:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 8 $2\traptype[7:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 3 $2\xer_in[2:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $2\xer_out[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 8 $3\asmcode[7:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 64 $3\cia[63:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 3 $3\cr_in1[2:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $3\cr_in1_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 3 $3\cr_in2$1[2:0]$336 - attribute \src "libresoc.v:10450.3-10607.6" - wire width 3 $3\cr_in2[2:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $3\cr_in2_ok$2[0:0]$337 - attribute \src "libresoc.v:10450.3-10607.6" - wire $3\cr_in2_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 3 $3\cr_out[2:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $3\cr_out_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 8 $3\cr_rd[7:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $3\cr_rd_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 8 $3\cr_wr[7:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $3\cr_wr_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 5 $3\ea[4:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $3\ea_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $3\exc_$signal$3[0:0]$339 - attribute \src "libresoc.v:10450.3-10607.6" - wire $3\exc_$signal$4[0:0]$340 - attribute \src "libresoc.v:10450.3-10607.6" - wire $3\exc_$signal$5[0:0]$341 - attribute \src "libresoc.v:10450.3-10607.6" - wire $3\exc_$signal$6[0:0]$342 - attribute \src "libresoc.v:10450.3-10607.6" - wire $3\exc_$signal$7[0:0]$343 - attribute \src "libresoc.v:10450.3-10607.6" - wire $3\exc_$signal$8[0:0]$344 - attribute \src "libresoc.v:10450.3-10607.6" - wire $3\exc_$signal$9[0:0]$345 - attribute \src "libresoc.v:10450.3-10607.6" - wire $3\exc_$signal[0:0]$338 - attribute \src "libresoc.v:10450.3-10607.6" - wire width 3 $3\fast1[2:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $3\fast1_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 3 $3\fast2[2:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $3\fast2_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 3 $3\fasto1[2:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $3\fasto1_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 3 $3\fasto2[2:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $3\fasto2_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 12 $3\fn_unit[11:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 2 $3\input_carry[1:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 32 $3\insn[31:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 7 $3\insn_type[6:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $3\is_32bit[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $3\lk[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 64 $3\msr[63:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $3\oe[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $3\oe_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $3\rc[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $3\rc_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 5 $3\reg1[4:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $3\reg1_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 5 $3\reg2[4:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $3\reg2_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 5 $3\reg3[4:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $3\reg3_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 5 $3\rego[4:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $3\rego_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 10 $3\spr1[9:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $3\spr1_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 10 $3\spro[9:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $3\spro_ok[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 13 $3\trapaddr[12:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 8 $3\traptype[7:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 3 $3\xer_in[2:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire $3\xer_out[0:0] - attribute \src "libresoc.v:10450.3-10607.6" - wire width 8 $4\asmcode[7:0] - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_a_spr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 \dec_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \dec_b_fast_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_b_fast_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 \dec_b_reg_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_b_reg_b_ok - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:178" - wire width 4 \dec_b_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 \dec_c_reg_c - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_c_reg_c_ok - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:282" - wire width 2 \dec_c_sel_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" + attribute \src "libresoc.v:100982.3-100994.6" + wire width 8 $1\dec31_dec_sub4_asmcode[7:0] + attribute \src "libresoc.v:101034.3-101046.6" + wire $1\dec31_dec_sub4_br[0:0] + attribute \src "libresoc.v:101203.3-101215.6" + wire width 3 $1\dec31_dec_sub4_cr_in[2:0] + attribute \src "libresoc.v:101216.3-101228.6" + wire width 3 $1\dec31_dec_sub4_cr_out[2:0] + attribute \src "libresoc.v:100969.3-100981.6" + wire width 2 $1\dec31_dec_sub4_cry_in[1:0] + attribute \src "libresoc.v:101021.3-101033.6" + wire $1\dec31_dec_sub4_cry_out[0:0] + attribute \src "libresoc.v:101138.3-101150.6" + wire width 5 $1\dec31_dec_sub4_form[4:0] + attribute \src "libresoc.v:100917.3-100929.6" + wire width 12 $1\dec31_dec_sub4_function_unit[11:0] + attribute \src "libresoc.v:101151.3-101163.6" + wire width 3 $1\dec31_dec_sub4_in1_sel[2:0] + attribute \src "libresoc.v:101164.3-101176.6" + wire width 4 $1\dec31_dec_sub4_in2_sel[3:0] + attribute \src "libresoc.v:101177.3-101189.6" + wire width 2 $1\dec31_dec_sub4_in3_sel[1:0] + attribute \src "libresoc.v:101060.3-101072.6" + wire width 7 $1\dec31_dec_sub4_internal_op[6:0] + attribute \src "libresoc.v:100995.3-101007.6" + wire $1\dec31_dec_sub4_inv_a[0:0] + attribute \src "libresoc.v:101008.3-101020.6" + wire $1\dec31_dec_sub4_inv_out[0:0] + attribute \src "libresoc.v:101086.3-101098.6" + wire $1\dec31_dec_sub4_is_32b[0:0] + attribute \src "libresoc.v:100930.3-100942.6" + wire width 4 $1\dec31_dec_sub4_ldst_len[3:0] + attribute \src "libresoc.v:101112.3-101124.6" + wire $1\dec31_dec_sub4_lk[0:0] + attribute \src "libresoc.v:101190.3-101202.6" + wire width 2 $1\dec31_dec_sub4_out_sel[1:0] + attribute \src "libresoc.v:100956.3-100968.6" + wire width 2 $1\dec31_dec_sub4_rc_sel[1:0] + attribute \src "libresoc.v:101073.3-101085.6" + wire $1\dec31_dec_sub4_rsrv[0:0] + attribute \src "libresoc.v:101125.3-101137.6" + wire $1\dec31_dec_sub4_sgl_pipe[0:0] + attribute \src "libresoc.v:101099.3-101111.6" + wire $1\dec31_dec_sub4_sgn[0:0] + attribute \src "libresoc.v:101047.3-101059.6" + wire $1\dec31_dec_sub4_sgn_ext[0:0] + attribute \src "libresoc.v:100943.3-100955.6" + wire width 2 $1\dec31_dec_sub4_upd[1:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \dec_cr_in_cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \dec_cr_in_cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_cr_in_cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \dec_cr_in_cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_cr_in_cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_cr_in_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \dec_cr_in_cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_cr_in_cr_fxm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" - wire width 32 \dec_cr_in_insn_in + wire width 8 output 4 \dec31_dec_sub4_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub4_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -14059,42 +158446,56 @@ module \dec2 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" - wire width 3 \dec_cr_in_sel_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \dec_cr_out_cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_cr_out_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \dec_cr_out_cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_cr_out_cr_fxm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" - wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" - wire \dec_cr_out_rc_in + wire width 3 output 9 \dec31_dec_sub4_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" - wire width 3 \dec_cr_out_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub4_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec_cry_in + wire width 2 output 14 \dec31_dec_sub4_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub4_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub4_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -14109,7 +158510,7 @@ module \dec2 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec_function_unit + wire width 12 output 1 \dec31_dec_sub4_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -14117,7 +158518,7 @@ module \dec2 attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_in1_sel + wire width 3 output 5 \dec31_dec_sub4_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -14134,13 +158535,13 @@ module \dec2 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec_in2_sel + wire width 4 output 6 \dec31_dec_sub4_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec_in3_sel + wire width 2 output 7 \dec31_dec_sub4_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -14216,933 +158617,880 @@ module \dec2 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:904" - wire \dec_irq_ok + wire width 7 output 2 \dec31_dec_sub4_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_is_32b + wire output 15 \dec31_dec_sub4_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \dec_o2_fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_o2_fast_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:366" - wire \dec_o2_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 \dec_o2_reg_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_o2_reg_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \dec_o_fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_o_fast_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 \dec_o_reg_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_o_reg_o_ok - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311" - wire width 2 \dec_o_sel_in - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" - attribute \enum_value_0000010010 "DSISR" - attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" - attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" - attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" - attribute \enum_value_0100010000 "SPRG0_priv" - attribute \enum_value_0100010001 "SPRG1_priv" - attribute \enum_value_0100010010 "SPRG2_priv" - attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 10 \dec_o_spr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_o_spr_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_oe_oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" - wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec_opcode_in + wire output 16 \dec31_dec_sub4_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub4_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub4_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub4_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_rc_rc_ok + wire width 2 output 8 \dec31_dec_sub4_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec_rc_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" - wire width 2 \dec_rc_sel_in + wire width 2 output 13 \dec31_dec_sub4_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub4_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub4_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub4_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub4_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 output 8 \ea - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 9 \ea_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 50 \exc_$signal - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 51 \exc_$signal$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 52 \exc_$signal$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 53 \exc_$signal$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 54 \exc_$signal$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 55 \exc_$signal$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 56 \exc_$signal$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 57 \exc_$signal$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:903" - wire \ext_irq_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 output 22 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 23 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 output 24 \fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 25 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 output 26 \fasto1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 27 \fasto1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 output 28 \fasto2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 29 \fasto2_ok - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" - wire width 12 output 42 \fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:906" - wire \illeg_ok - attribute \src "libresoc.v:8640.7-8640.15" - wire \initial - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" - wire width 2 output 48 \input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" - wire width 32 output 40 \insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" - wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" - wire width 32 \insn_in$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89" - wire width 32 \insn_in$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" - wire width 32 \insn_in$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:283" - wire width 32 \insn_in$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:312" - wire width 32 \insn_in$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:367" - wire width 32 \insn_in$41 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" - wire width 7 output 41 \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" - wire output 63 \is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:44" - wire \is_priv_insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" - wire output 43 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" - wire width 64 output 38 \msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 46 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 47 \oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:905" - wire \priv_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 input 4 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 44 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 45 \rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 output 10 \reg1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 11 \reg1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 output 12 \reg2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 13 \reg2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 output 14 \reg3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 15 \reg3_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 output 6 \rego - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 7 \rego_ok - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" - wire width 2 \sel_in - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" - attribute \enum_value_0000010010 "DSISR" - attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" - attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" - attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" - attribute \enum_value_0100010000 "SPRG0_priv" - attribute \enum_value_0100010001 "SPRG1_priv" - attribute \enum_value_0100010010 "SPRG2_priv" - attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute 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attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 10 output 18 \spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 19 \spr1_ok - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" 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attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \tmp_tmp_exc_$signal$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \tmp_tmp_exc_$signal$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \tmp_tmp_exc_$signal$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \tmp_tmp_exc_$signal$27 + wire width 2 output 12 \dec31_dec_sub4_upd + attribute \src "libresoc.v:100660.7-100660.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:100660.7-100660.20" + process $proc$libresoc.v:100660$4121 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:100917.3-100929.6" + process $proc$libresoc.v:100917$4097 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_function_unit[11:0] $1\dec31_dec_sub4_function_unit[11:0] + attribute \src "libresoc.v:100918.5-100918.29" + switch \initial + attribute \src "libresoc.v:100918.9-100918.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_function_unit[11:0] 12'000010000000 + case + assign $1\dec31_dec_sub4_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub4_function_unit $0\dec31_dec_sub4_function_unit[11:0] + end + attribute \src "libresoc.v:100930.3-100942.6" + process $proc$libresoc.v:100930$4098 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_ldst_len[3:0] $1\dec31_dec_sub4_ldst_len[3:0] + attribute \src "libresoc.v:100931.5-100931.29" + switch \initial + attribute \src "libresoc.v:100931.9-100931.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub4_ldst_len $0\dec31_dec_sub4_ldst_len[3:0] + end + attribute \src "libresoc.v:100943.3-100955.6" + process $proc$libresoc.v:100943$4099 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_upd[1:0] $1\dec31_dec_sub4_upd[1:0] + attribute \src "libresoc.v:100944.5-100944.29" + switch \initial + attribute \src "libresoc.v:100944.9-100944.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub4_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_upd $0\dec31_dec_sub4_upd[1:0] + end + attribute \src "libresoc.v:100956.3-100968.6" + process $proc$libresoc.v:100956$4100 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_rc_sel[1:0] $1\dec31_dec_sub4_rc_sel[1:0] + attribute \src "libresoc.v:100957.5-100957.29" + switch \initial + attribute \src "libresoc.v:100957.9-100957.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_rc_sel $0\dec31_dec_sub4_rc_sel[1:0] + end + attribute \src "libresoc.v:100969.3-100981.6" + process $proc$libresoc.v:100969$4101 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_cry_in[1:0] $1\dec31_dec_sub4_cry_in[1:0] + attribute \src "libresoc.v:100970.5-100970.29" + switch \initial + attribute \src "libresoc.v:100970.9-100970.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_cry_in $0\dec31_dec_sub4_cry_in[1:0] + end + attribute \src "libresoc.v:100982.3-100994.6" + process $proc$libresoc.v:100982$4102 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_asmcode[7:0] $1\dec31_dec_sub4_asmcode[7:0] + attribute \src "libresoc.v:100983.5-100983.29" + switch \initial + attribute \src "libresoc.v:100983.9-100983.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_asmcode[7:0] 8'11001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_asmcode[7:0] 8'11001110 + case + assign $1\dec31_dec_sub4_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub4_asmcode $0\dec31_dec_sub4_asmcode[7:0] + end + attribute \src "libresoc.v:100995.3-101007.6" + process $proc$libresoc.v:100995$4103 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_inv_a[0:0] $1\dec31_dec_sub4_inv_a[0:0] + attribute \src "libresoc.v:100996.5-100996.29" + switch \initial + attribute \src "libresoc.v:100996.9-100996.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_inv_a $0\dec31_dec_sub4_inv_a[0:0] + end + attribute \src "libresoc.v:101008.3-101020.6" + process $proc$libresoc.v:101008$4104 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_inv_out[0:0] $1\dec31_dec_sub4_inv_out[0:0] + attribute \src "libresoc.v:101009.5-101009.29" + switch \initial + attribute \src "libresoc.v:101009.9-101009.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_inv_out $0\dec31_dec_sub4_inv_out[0:0] + end + attribute \src "libresoc.v:101021.3-101033.6" + process $proc$libresoc.v:101021$4105 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_cry_out[0:0] $1\dec31_dec_sub4_cry_out[0:0] + attribute \src "libresoc.v:101022.5-101022.29" + switch \initial + attribute \src "libresoc.v:101022.9-101022.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_cry_out $0\dec31_dec_sub4_cry_out[0:0] + end + attribute \src "libresoc.v:101034.3-101046.6" + process $proc$libresoc.v:101034$4106 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_br[0:0] $1\dec31_dec_sub4_br[0:0] + attribute \src "libresoc.v:101035.5-101035.29" + switch \initial + attribute \src "libresoc.v:101035.9-101035.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_br[0:0] 1'0 + case + assign $1\dec31_dec_sub4_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_br $0\dec31_dec_sub4_br[0:0] + end + attribute \src "libresoc.v:101047.3-101059.6" + process $proc$libresoc.v:101047$4107 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sgn_ext[0:0] $1\dec31_dec_sub4_sgn_ext[0:0] + attribute \src "libresoc.v:101048.5-101048.29" + switch \initial + attribute \src "libresoc.v:101048.9-101048.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_sgn_ext $0\dec31_dec_sub4_sgn_ext[0:0] + end + attribute \src "libresoc.v:101060.3-101072.6" + process $proc$libresoc.v:101060$4108 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_internal_op[6:0] $1\dec31_dec_sub4_internal_op[6:0] + attribute \src "libresoc.v:101061.5-101061.29" + switch \initial + attribute \src "libresoc.v:101061.9-101061.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 + case + assign $1\dec31_dec_sub4_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub4_internal_op $0\dec31_dec_sub4_internal_op[6:0] + end + attribute \src "libresoc.v:101073.3-101085.6" + process $proc$libresoc.v:101073$4109 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_rsrv[0:0] $1\dec31_dec_sub4_rsrv[0:0] + attribute \src "libresoc.v:101074.5-101074.29" + switch \initial + attribute \src "libresoc.v:101074.9-101074.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_rsrv $0\dec31_dec_sub4_rsrv[0:0] + end + attribute \src "libresoc.v:101086.3-101098.6" + process $proc$libresoc.v:101086$4110 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_is_32b[0:0] $1\dec31_dec_sub4_is_32b[0:0] + attribute \src "libresoc.v:101087.5-101087.29" + switch \initial + attribute \src "libresoc.v:101087.9-101087.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_is_32b[0:0] 1'1 + case + assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_is_32b $0\dec31_dec_sub4_is_32b[0:0] + end + attribute \src "libresoc.v:101099.3-101111.6" + process $proc$libresoc.v:101099$4111 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sgn[0:0] $1\dec31_dec_sub4_sgn[0:0] + attribute \src "libresoc.v:101100.5-101100.29" + switch \initial + attribute \src "libresoc.v:101100.9-101100.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub4_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_sgn $0\dec31_dec_sub4_sgn[0:0] + end + attribute \src "libresoc.v:101112.3-101124.6" + process $proc$libresoc.v:101112$4112 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_lk[0:0] $1\dec31_dec_sub4_lk[0:0] + attribute \src "libresoc.v:101113.5-101113.29" + switch \initial + attribute \src "libresoc.v:101113.9-101113.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub4_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_lk $0\dec31_dec_sub4_lk[0:0] + end + attribute \src "libresoc.v:101125.3-101137.6" + process $proc$libresoc.v:101125$4113 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sgl_pipe[0:0] $1\dec31_dec_sub4_sgl_pipe[0:0] + attribute \src "libresoc.v:101126.5-101126.29" + switch \initial + attribute \src "libresoc.v:101126.9-101126.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_sgl_pipe $0\dec31_dec_sub4_sgl_pipe[0:0] + end + attribute \src "libresoc.v:101138.3-101150.6" + process $proc$libresoc.v:101138$4114 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_form[4:0] $1\dec31_dec_sub4_form[4:0] + attribute \src "libresoc.v:101139.5-101139.29" + switch \initial + attribute \src "libresoc.v:101139.9-101139.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub4_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub4_form $0\dec31_dec_sub4_form[4:0] + end + attribute \src "libresoc.v:101151.3-101163.6" + process $proc$libresoc.v:101151$4115 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_in1_sel[2:0] $1\dec31_dec_sub4_in1_sel[2:0] + attribute \src "libresoc.v:101152.5-101152.29" + switch \initial + attribute \src "libresoc.v:101152.9-101152.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub4_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_in1_sel $0\dec31_dec_sub4_in1_sel[2:0] + end + attribute \src "libresoc.v:101164.3-101176.6" + process $proc$libresoc.v:101164$4116 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_in2_sel[3:0] $1\dec31_dec_sub4_in2_sel[3:0] + attribute \src "libresoc.v:101165.5-101165.29" + switch \initial + attribute \src "libresoc.v:101165.9-101165.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub4_in2_sel $0\dec31_dec_sub4_in2_sel[3:0] + end + attribute \src "libresoc.v:101177.3-101189.6" + process $proc$libresoc.v:101177$4117 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_in3_sel[1:0] $1\dec31_dec_sub4_in3_sel[1:0] + attribute \src "libresoc.v:101178.5-101178.29" + switch \initial + attribute \src "libresoc.v:101178.9-101178.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_in3_sel $0\dec31_dec_sub4_in3_sel[1:0] + end + attribute \src "libresoc.v:101190.3-101202.6" + process $proc$libresoc.v:101190$4118 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_out_sel[1:0] $1\dec31_dec_sub4_out_sel[1:0] + attribute \src "libresoc.v:101191.5-101191.29" + switch \initial + attribute \src "libresoc.v:101191.9-101191.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_out_sel $0\dec31_dec_sub4_out_sel[1:0] + end + attribute \src "libresoc.v:101203.3-101215.6" + process $proc$libresoc.v:101203$4119 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_cr_in[2:0] $1\dec31_dec_sub4_cr_in[2:0] + attribute \src "libresoc.v:101204.5-101204.29" + switch \initial + attribute \src "libresoc.v:101204.9-101204.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_cr_in $0\dec31_dec_sub4_cr_in[2:0] + end + attribute \src "libresoc.v:101216.3-101228.6" + process $proc$libresoc.v:101216$4120 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_cr_out[2:0] $1\dec31_dec_sub4_cr_out[2:0] + attribute \src "libresoc.v:101217.5-101217.29" + switch \initial + attribute \src "libresoc.v:101217.9-101217.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_cr_out $0\dec31_dec_sub4_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:101234.1-102525.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub8" +attribute \generator "nMigen" +module \dec31_dec_sub8 + attribute \src "libresoc.v:101707.3-101749.6" + wire width 8 $0\dec31_dec_sub8_asmcode[7:0] + attribute \src "libresoc.v:101879.3-101921.6" + wire $0\dec31_dec_sub8_br[0:0] + attribute \src "libresoc.v:102438.3-102480.6" + wire width 3 $0\dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:102481.3-102523.6" + wire width 3 $0\dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:101664.3-101706.6" + wire width 2 $0\dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:101836.3-101878.6" + wire $0\dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:102223.3-102265.6" + wire width 5 $0\dec31_dec_sub8_form[4:0] + attribute \src "libresoc.v:101492.3-101534.6" + wire width 12 $0\dec31_dec_sub8_function_unit[11:0] + attribute \src "libresoc.v:102266.3-102308.6" + wire width 3 $0\dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:102309.3-102351.6" + wire width 4 $0\dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:102352.3-102394.6" + wire width 2 $0\dec31_dec_sub8_in3_sel[1:0] + attribute \src "libresoc.v:101965.3-102007.6" + wire width 7 $0\dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:101750.3-101792.6" + wire $0\dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:101793.3-101835.6" + wire $0\dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:102051.3-102093.6" + wire $0\dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:101535.3-101577.6" + wire width 4 $0\dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:102137.3-102179.6" + wire $0\dec31_dec_sub8_lk[0:0] + attribute \src "libresoc.v:102395.3-102437.6" + wire width 2 $0\dec31_dec_sub8_out_sel[1:0] + attribute \src "libresoc.v:101621.3-101663.6" + wire width 2 $0\dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:102008.3-102050.6" + wire $0\dec31_dec_sub8_rsrv[0:0] + attribute \src "libresoc.v:102180.3-102222.6" + wire $0\dec31_dec_sub8_sgl_pipe[0:0] + attribute \src "libresoc.v:102094.3-102136.6" + wire $0\dec31_dec_sub8_sgn[0:0] + attribute \src "libresoc.v:101922.3-101964.6" + wire $0\dec31_dec_sub8_sgn_ext[0:0] + attribute \src "libresoc.v:101578.3-101620.6" + wire width 2 $0\dec31_dec_sub8_upd[1:0] + attribute \src "libresoc.v:101235.7-101235.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:101707.3-101749.6" + wire width 8 $1\dec31_dec_sub8_asmcode[7:0] + attribute \src "libresoc.v:101879.3-101921.6" + wire $1\dec31_dec_sub8_br[0:0] + attribute \src "libresoc.v:102438.3-102480.6" + wire width 3 $1\dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:102481.3-102523.6" + wire width 3 $1\dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:101664.3-101706.6" + wire width 2 $1\dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:101836.3-101878.6" + wire $1\dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:102223.3-102265.6" + wire width 5 $1\dec31_dec_sub8_form[4:0] + attribute \src "libresoc.v:101492.3-101534.6" + wire width 12 $1\dec31_dec_sub8_function_unit[11:0] + attribute \src "libresoc.v:102266.3-102308.6" + wire width 3 $1\dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:102309.3-102351.6" + wire width 4 $1\dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:102352.3-102394.6" + wire width 2 $1\dec31_dec_sub8_in3_sel[1:0] + attribute \src "libresoc.v:101965.3-102007.6" + wire width 7 $1\dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:101750.3-101792.6" + wire $1\dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:101793.3-101835.6" + wire $1\dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:102051.3-102093.6" + wire $1\dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:101535.3-101577.6" + wire width 4 $1\dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:102137.3-102179.6" + wire $1\dec31_dec_sub8_lk[0:0] + attribute \src "libresoc.v:102395.3-102437.6" + wire width 2 $1\dec31_dec_sub8_out_sel[1:0] + attribute \src "libresoc.v:101621.3-101663.6" + wire width 2 $1\dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:102008.3-102050.6" + wire $1\dec31_dec_sub8_rsrv[0:0] + attribute \src "libresoc.v:102180.3-102222.6" + wire $1\dec31_dec_sub8_sgl_pipe[0:0] + attribute \src "libresoc.v:102094.3-102136.6" + wire $1\dec31_dec_sub8_sgn[0:0] + attribute \src "libresoc.v:101922.3-101964.6" + wire $1\dec31_dec_sub8_sgn_ext[0:0] + attribute \src "libresoc.v:101578.3-101620.6" + wire width 2 $1\dec31_dec_sub8_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub8_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub8_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub8_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub8_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub8_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub8_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub8_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -15156,16 +159504,39 @@ module \dec2 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" - wire width 12 \tmp_tmp_fn_unit - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" - wire width 2 \tmp_tmp_input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" - wire width 32 \tmp_tmp_insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub8_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub8_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub8_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub8_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -15230,1963 +159601,1793 @@ module \dec2 attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" - wire width 7 \tmp_tmp_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" - wire \tmp_tmp_is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" - wire \tmp_tmp_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" - wire width 64 \tmp_tmp_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \tmp_tmp_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \tmp_tmp_oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \tmp_tmp_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \tmp_tmp_rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" - wire width 13 \tmp_tmp_trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" - wire width 8 \tmp_tmp_traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104" - wire width 3 \tmp_xer_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" - wire \tmp_xer_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" - wire width 13 output 58 \trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" - wire width 8 output 49 \traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104" - wire width 3 output 20 \xer_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" - wire output 21 \xer_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:909" - cell $and $and$libresoc.v:10239$296 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cur_eint - connect \B \cur_msr [15] - connect \Y $and$libresoc.v:10239$296_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:910" - cell $and $and$libresoc.v:10240$297 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cur_dec [63] - connect \B \cur_msr [15] - connect \Y $and$libresoc.v:10240$297_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:911" - cell $and $and$libresoc.v:10241$298 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_priv_insn - connect \B \cur_msr [14] - connect \Y $and$libresoc.v:10241$298_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:960" - cell $eq $eq$libresoc.v:10231$288 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \insn_type - connect \B 7'0111111 - connect \Y $eq$libresoc.v:10231$288_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:961" - cell $eq $eq$libresoc.v:10232$289 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \insn_type - connect \B 7'1001001 - connect \Y $eq$libresoc.v:10232$289_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:970" - cell $eq $eq$libresoc.v:10234$291 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \insn_type - connect \B 7'1000110 - connect \Y $eq$libresoc.v:10234$291_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:878" - cell $eq $eq$libresoc.v:10235$292 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \dec_internal_op - connect \B 7'0101110 - connect \Y $eq$libresoc.v:10235$292_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:880" - cell $eq $eq$libresoc.v:10236$293 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \dec_internal_op - connect \B 7'0001010 - connect \Y $eq$libresoc.v:10236$293_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:882" - cell $eq $eq$libresoc.v:10237$294 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \dec_internal_op - connect \B 7'0110001 - connect \Y $eq$libresoc.v:10237$294_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:886" - cell $eq $eq$libresoc.v:10238$295 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \dec_internal_op - connect \B 7'0111111 - connect \Y $eq$libresoc.v:10238$295_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:912" - cell $eq $eq$libresoc.v:10242$299 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \dec_internal_op - connect \B 7'0000000 - connect \Y $eq$libresoc.v:10242$299_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:961" - cell $or $or$libresoc.v:10233$290 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \B \$30 - connect \Y $or$libresoc.v:10233$290_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:10243.7-10280.4" - cell \dec \dec - connect \BA \dec_BA - connect \BB \dec_BB - connect \BC \dec_BC - connect \BI \dec_BI - connect \BO \dec_BO - connect \BT \dec_BT - connect \FXM \dec_FXM - connect \LK \dec_LK - connect \OE \dec_OE - connect \RA \dec_RA - connect \RB \dec_RB - connect \RS \dec_RS - connect \RT \dec_RT - connect \Rc \dec_Rc - connect \SPR \dec_SPR - connect \XL_BT \dec_XL_BT - connect \XL_XO \dec_XL_XO - connect \X_BF \dec_X_BF - connect \X_BFA \dec_X_BFA - connect \asmcode \dec_asmcode - connect \bigendian \bigendian - connect \cr_in \dec_cr_in - connect \cr_out \dec_cr_out - connect \cry_in \dec_cry_in - connect \function_unit \dec_function_unit - connect \in1_sel \dec_in1_sel - connect \in2_sel \dec_in2_sel - connect \in3_sel \dec_in3_sel - connect \internal_op \dec_internal_op - connect \is_32b \dec_is_32b - connect \lk \dec_lk - connect \opcode_in \dec_opcode_in - connect \out_sel \dec_out_sel - connect \raw_opcode_in \raw_opcode_in - connect \rc_sel \dec_rc_sel - connect \upd \dec_upd - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:10281.9-10295.4" - cell \dec_a \dec_a - connect \BO \dec_BO - connect \RA \dec_RA - connect \RS \dec_RS - connect \SPR \dec_SPR - connect \XL_XO \dec_XL_XO - connect \fast_a \dec_a_fast_a - connect \fast_a_ok \dec_a_fast_a_ok - connect \internal_op \dec_internal_op - connect \reg_a \dec_a_reg_a - connect \reg_a_ok \dec_a_reg_a_ok - connect \sel_in \dec_a_sel_in - connect \spr_a \dec_a_spr_a - connect \spr_a_ok \dec_a_spr_a_ok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:10296.9-10306.4" - cell \dec_b \dec_b - connect \RB \dec_RB - connect \RS \dec_RS - connect \XL_XO \dec_XL_XO - connect \fast_b \dec_b_fast_b - connect \fast_b_ok \dec_b_fast_b_ok - connect \internal_op \dec_internal_op - connect \reg_b \dec_b_reg_b - connect \reg_b_ok \dec_b_reg_b_ok - connect \sel_in \dec_b_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:10307.9-10313.4" - cell \dec_c \dec_c - connect \RB \dec_RB - connect \RS \dec_RS - connect \reg_c \dec_c_reg_c - connect \reg_c_ok \dec_c_reg_c_ok - connect \sel_in \dec_c_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:10314.13-10333.4" - cell \dec_cr_in \dec_cr_in$10 - connect \BA \dec_BA - connect \BB \dec_BB - connect \BC \dec_BC - connect \BI \dec_BI - connect \BT \dec_BT - connect \FXM \dec_FXM - connect \X_BFA \dec_X_BFA - connect \cr_bitfield \dec_cr_in_cr_bitfield - connect \cr_bitfield_b \dec_cr_in_cr_bitfield_b - connect \cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b_ok - connect \cr_bitfield_o \dec_cr_in_cr_bitfield_o - connect \cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o_ok - connect \cr_bitfield_ok \dec_cr_in_cr_bitfield_ok - connect \cr_fxm \dec_cr_in_cr_fxm - connect \cr_fxm_ok \dec_cr_in_cr_fxm_ok - connect \insn_in \dec_cr_in_insn_in - connect \internal_op \dec_internal_op - connect \sel_in \dec_cr_in_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:10334.14-10346.4" - cell \dec_cr_out \dec_cr_out$11 - connect \FXM \dec_FXM - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \cr_bitfield \dec_cr_out_cr_bitfield - connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok - connect \cr_fxm \dec_cr_out_cr_fxm - connect \cr_fxm_ok \dec_cr_out_cr_fxm_ok - connect \insn_in \dec_cr_out_insn_in - connect \internal_op \dec_internal_op - connect \rc_in \dec_cr_out_rc_in - connect \sel_in \dec_cr_out_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:10347.9-10360.4" - cell \dec_o \dec_o - connect \BO \dec_BO - connect \RA \dec_RA - connect \RT \dec_RT - connect \SPR \dec_SPR - connect \fast_o \dec_o_fast_o - connect \fast_o_ok \dec_o_fast_o_ok - connect \internal_op \dec_internal_op - connect \reg_o \dec_o_reg_o - connect \reg_o_ok \dec_o_reg_o_ok - connect \sel_in \dec_o_sel_in - connect \spr_o \dec_o_spr_o - connect \spr_o_ok \dec_o_spr_o_ok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:10361.10-10370.4" - cell \dec_o2 \dec_o2 - connect \RA \dec_RA - connect \fast_o \dec_o2_fast_o - connect \fast_o_ok \dec_o2_fast_o_ok - connect \internal_op \dec_internal_op - connect \lk \dec_o2_lk - connect \reg_o \dec_o2_reg_o - connect \reg_o_ok \dec_o2_reg_o_ok - connect \upd \dec_upd - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:10371.10-10377.4" - cell \dec_oe \dec_oe - connect \OE \dec_OE - connect \internal_op \dec_internal_op - connect \oe \dec_oe_oe - connect \oe_ok \dec_oe_oe_ok - connect \sel_in \dec_oe_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:10378.10-10383.4" - cell \dec_rc \dec_rc - connect \Rc \dec_Rc - connect \rc \dec_rc_rc - connect \rc_ok \dec_rc_rc_ok - connect \sel_in \dec_rc_sel_in - end - attribute \src "libresoc.v:10384.3-10393.6" - process $proc$libresoc.v:10384$300 - assign { } { } + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub8_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub8_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub8_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub8_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub8_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub8_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub8_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub8_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub8_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub8_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub8_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub8_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub8_upd + attribute \src "libresoc.v:101235.7-101235.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:101235.7-101235.20" + process $proc$libresoc.v:101235$4146 assign { } { } - assign $0\tmp_tmp_lk[0:0] $1\tmp_tmp_lk[0:0] - attribute \src "libresoc.v:10385.5-10385.29" - switch \initial - attribute \src "libresoc.v:10385.9-10385.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:762" - switch \dec_lk - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\tmp_tmp_lk[0:0] \dec_LK - case - assign $1\tmp_tmp_lk[0:0] 1'0 - end + assign $0\initial[0:0] 1'0 sync always - update \tmp_tmp_lk $0\tmp_tmp_lk[0:0] + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:10394.3-10409.6" - process $proc$libresoc.v:10394$301 - assign { } { } + attribute \src "libresoc.v:101492.3-101534.6" + process $proc$libresoc.v:101492$4122 assign { } { } assign { } { } - assign $0\tmp_xer_in[2:0] $2\tmp_xer_in[2:0] - attribute \src "libresoc.v:10395.5-10395.29" + assign $0\dec31_dec_sub8_function_unit[11:0] $1\dec31_dec_sub8_function_unit[11:0] + attribute \src "libresoc.v:101493.5-101493.29" switch \initial - attribute \src "libresoc.v:10395.9-10395.17" + attribute \src "libresoc.v:101493.9-101493.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:878" - switch \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 assign { } { } - assign $1\tmp_xer_in[2:0] 3'111 - case - assign $1\tmp_xer_in[2:0] 3'000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:880" - switch \$44 + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10011 assign { } { } - assign $2\tmp_xer_in[2:0] 3'001 - case - assign $2\tmp_xer_in[2:0] $1\tmp_xer_in[2:0] - end - sync always - update \tmp_xer_in $0\tmp_xer_in[2:0] - end - attribute \src "libresoc.v:10410.3-10419.6" - process $proc$libresoc.v:10410$302 - assign { } { } - assign { } { } - assign $0\tmp_xer_out[0:0] $1\tmp_xer_out[0:0] - attribute \src "libresoc.v:10411.5-10411.29" - switch \initial - attribute \src "libresoc.v:10411.9-10411.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:882" - switch \$46 + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 assign { } { } - assign $1\tmp_xer_out[0:0] 1'1 - case - assign $1\tmp_xer_out[0:0] 1'0 - end - sync always - update \tmp_xer_out $0\tmp_xer_out[0:0] - end - attribute \src "libresoc.v:10420.3-10429.6" - process $proc$libresoc.v:10420$303 - assign { } { } - assign { } { } - assign $0\tmp_tmp_trapaddr[12:0] $1\tmp_tmp_trapaddr[12:0] - attribute \src "libresoc.v:10421.5-10421.29" - switch \initial - attribute \src "libresoc.v:10421.9-10421.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:886" - switch \$48 + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10001 assign { } { } - assign $1\tmp_tmp_trapaddr[12:0] 13'0000001110000 - case - assign $1\tmp_tmp_trapaddr[12:0] 13'0000000000000 - end - sync always - update \tmp_tmp_trapaddr $0\tmp_tmp_trapaddr[12:0] - end - attribute \src "libresoc.v:10430.3-10449.6" - process $proc$libresoc.v:10430$304 - assign { } { } - assign { } { } - assign $0\is_priv_insn[0:0] $1\is_priv_insn[0:0] - attribute \src "libresoc.v:10431.5-10431.29" - switch \initial - attribute \src "libresoc.v:10431.9-10431.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:45" - switch \dec_internal_op + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 , 7'1000111 , 7'1001000 , 7'1001010 , 7'1000110 + case 5'00000 assign { } { } - assign $1\is_priv_insn[0:0] 1'1 + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 attribute \src "libresoc.v:0.0-0.0" - case 7'0101110 , 7'0110001 + case 5'10000 assign { } { } - assign $1\is_priv_insn[0:0] $2\is_priv_insn[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:52" - switch \tmp_tmp_insn [20] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\is_priv_insn[0:0] 1'1 - case - assign $2\is_priv_insn[0:0] 1'0 - end + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 case - assign $1\is_priv_insn[0:0] 1'0 + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000000 end sync always - update \is_priv_insn $0\is_priv_insn[0:0] + update \dec31_dec_sub8_function_unit $0\dec31_dec_sub8_function_unit[11:0] end - attribute \src "libresoc.v:10450.3-10607.6" - process $proc$libresoc.v:10450$305 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\cr_out[2:0] $1\cr_out[2:0] - assign $0\lk[0:0] $1\lk[0:0] - assign $0\cia[63:0] $1\cia[63:0] - assign $0\cr_in1[2:0] $1\cr_in1[2:0] - assign $0\cr_in1_ok[0:0] $1\cr_in1_ok[0:0] - assign $0\cr_in2[2:0] $1\cr_in2[2:0] - assign $0\cr_in2$1[2:0]$306 $1\cr_in2$1[2:0]$316 - assign $0\cr_in2_ok[0:0] $1\cr_in2_ok[0:0] - assign $0\cr_in2_ok$2[0:0]$307 $1\cr_in2_ok$2[0:0]$317 - assign $0\cr_out_ok[0:0] $1\cr_out_ok[0:0] - assign $0\cr_rd[7:0] $1\cr_rd[7:0] - assign $0\cr_rd_ok[0:0] $1\cr_rd_ok[0:0] - assign $0\cr_wr[7:0] $1\cr_wr[7:0] - assign $0\cr_wr_ok[0:0] $1\cr_wr_ok[0:0] - assign $0\ea[4:0] $1\ea[4:0] - assign $0\ea_ok[0:0] $1\ea_ok[0:0] - assign $0\exc_$signal[0:0]$308 $1\exc_$signal[0:0]$318 - assign $0\exc_$signal$3[0:0]$309 $1\exc_$signal$3[0:0]$319 - assign $0\exc_$signal$4[0:0]$310 $1\exc_$signal$4[0:0]$320 - assign $0\exc_$signal$5[0:0]$311 $1\exc_$signal$5[0:0]$321 - assign $0\exc_$signal$6[0:0]$312 $1\exc_$signal$6[0:0]$322 - assign $0\exc_$signal$7[0:0]$313 $1\exc_$signal$7[0:0]$323 - assign $0\exc_$signal$8[0:0]$314 $1\exc_$signal$8[0:0]$324 - assign $0\exc_$signal$9[0:0]$315 $1\exc_$signal$9[0:0]$325 - assign { } { } + attribute \src "libresoc.v:101535.3-101577.6" + process $proc$libresoc.v:101535$4123 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fn_unit[11:0] $1\fn_unit[11:0] - assign $0\input_carry[1:0] $1\input_carry[1:0] - assign $0\insn[31:0] $1\insn[31:0] - assign $0\insn_type[6:0] $1\insn_type[6:0] - assign $0\is_32bit[0:0] $1\is_32bit[0:0] - assign $0\msr[63:0] $1\msr[63:0] - assign $0\oe[0:0] $1\oe[0:0] - assign $0\oe_ok[0:0] $1\oe_ok[0:0] - assign $0\rc[0:0] $1\rc[0:0] - assign $0\rc_ok[0:0] $1\rc_ok[0:0] - assign $0\reg1[4:0] $1\reg1[4:0] - assign $0\reg1_ok[0:0] $1\reg1_ok[0:0] - assign $0\reg2[4:0] $1\reg2[4:0] - assign $0\reg2_ok[0:0] $1\reg2_ok[0:0] - assign $0\reg3[4:0] $1\reg3[4:0] - assign $0\reg3_ok[0:0] $1\reg3_ok[0:0] - assign $0\rego[4:0] $1\rego[4:0] - assign $0\rego_ok[0:0] $1\rego_ok[0:0] - assign $0\spr1[9:0] $1\spr1[9:0] - assign $0\spr1_ok[0:0] $1\spr1_ok[0:0] - assign $0\spro[9:0] $1\spro[9:0] - assign $0\spro_ok[0:0] $1\spro_ok[0:0] - assign $0\trapaddr[12:0] $1\trapaddr[12:0] - assign $0\traptype[7:0] $1\traptype[7:0] - assign $0\xer_in[2:0] $1\xer_in[2:0] - assign $0\xer_out[0:0] $1\xer_out[0:0] - assign $0\fasto1[2:0] $5\fasto1[2:0] - assign $0\fasto1_ok[0:0] $5\fasto1_ok[0:0] - assign $0\fasto2[2:0] $5\fasto2[2:0] - assign $0\fasto2_ok[0:0] $5\fasto2_ok[0:0] - assign $0\fast1[2:0] $5\fast1[2:0] - assign $0\fast1_ok[0:0] $5\fast1_ok[0:0] - assign $0\fast2[2:0] $5\fast2[2:0] - assign $0\fast2_ok[0:0] $5\fast2_ok[0:0] - assign $0\asmcode[7:0] \dec_asmcode - attribute \src "libresoc.v:10451.5-10451.29" + assign $0\dec31_dec_sub8_ldst_len[3:0] $1\dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:101536.5-101536.29" switch \initial - attribute \src "libresoc.v:10451.9-10451.17" + attribute \src "libresoc.v:101536.9-101536.17" case 1'1 case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:916" - switch { \illeg_ok \priv_ok \ext_irq_ok \dec_irq_ok \dec2_exc_$signal } - attribute \src "libresoc.v:0.0-0.0" - case 5'----1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\asmcode[7:0] $2\asmcode[7:0] - assign $1\cr_out[2:0] $2\cr_out[2:0] - assign $1\lk[0:0] $2\lk[0:0] - assign $1\cia[63:0] $2\cia[63:0] - assign $1\cr_in1[2:0] $2\cr_in1[2:0] - assign $1\cr_in1_ok[0:0] $2\cr_in1_ok[0:0] - assign $1\cr_in2[2:0] $2\cr_in2[2:0] - assign $1\cr_in2$1[2:0]$316 $2\cr_in2$1[2:0]$326 - assign $1\cr_in2_ok[0:0] $2\cr_in2_ok[0:0] - assign $1\cr_in2_ok$2[0:0]$317 $2\cr_in2_ok$2[0:0]$327 - assign $1\cr_out_ok[0:0] $2\cr_out_ok[0:0] - assign $1\cr_rd[7:0] $2\cr_rd[7:0] - assign $1\cr_rd_ok[0:0] $2\cr_rd_ok[0:0] - assign $1\cr_wr[7:0] $2\cr_wr[7:0] - assign $1\cr_wr_ok[0:0] $2\cr_wr_ok[0:0] - assign $1\ea[4:0] $2\ea[4:0] - assign $1\ea_ok[0:0] $2\ea_ok[0:0] - assign $1\exc_$signal[0:0]$318 $2\exc_$signal[0:0]$328 - assign $1\exc_$signal$3[0:0]$319 $2\exc_$signal$3[0:0]$329 - assign $1\exc_$signal$4[0:0]$320 $2\exc_$signal$4[0:0]$330 - assign $1\exc_$signal$5[0:0]$321 $2\exc_$signal$5[0:0]$331 - assign $1\exc_$signal$6[0:0]$322 $2\exc_$signal$6[0:0]$332 - assign $1\exc_$signal$7[0:0]$323 $2\exc_$signal$7[0:0]$333 - assign $1\exc_$signal$8[0:0]$324 $2\exc_$signal$8[0:0]$334 - assign $1\exc_$signal$9[0:0]$325 $2\exc_$signal$9[0:0]$335 - assign $1\fast1[2:0] $2\fast1[2:0] - assign $1\fast1_ok[0:0] $2\fast1_ok[0:0] - assign $1\fast2[2:0] $2\fast2[2:0] - assign $1\fast2_ok[0:0] $2\fast2_ok[0:0] - assign $1\fasto1[2:0] $2\fasto1[2:0] - assign $1\fasto1_ok[0:0] $2\fasto1_ok[0:0] - assign $1\fasto2[2:0] $2\fasto2[2:0] - assign $1\fasto2_ok[0:0] $2\fasto2_ok[0:0] - assign $1\fn_unit[11:0] $2\fn_unit[11:0] - assign $1\input_carry[1:0] $2\input_carry[1:0] - assign $1\insn[31:0] $2\insn[31:0] - assign $1\insn_type[6:0] $2\insn_type[6:0] - assign $1\is_32bit[0:0] $2\is_32bit[0:0] - assign $1\msr[63:0] $2\msr[63:0] - assign $1\oe[0:0] $2\oe[0:0] - assign $1\oe_ok[0:0] $2\oe_ok[0:0] - assign $1\rc[0:0] $2\rc[0:0] - assign $1\rc_ok[0:0] $2\rc_ok[0:0] - assign $1\reg1[4:0] $2\reg1[4:0] - assign $1\reg1_ok[0:0] $2\reg1_ok[0:0] - assign $1\reg2[4:0] $2\reg2[4:0] - assign $1\reg2_ok[0:0] $2\reg2_ok[0:0] - assign $1\reg3[4:0] $2\reg3[4:0] - assign $1\reg3_ok[0:0] $2\reg3_ok[0:0] - assign $1\rego[4:0] $2\rego[4:0] - assign $1\rego_ok[0:0] $2\rego_ok[0:0] - assign $1\spr1[9:0] $2\spr1[9:0] - assign $1\spr1_ok[0:0] $2\spr1_ok[0:0] - assign $1\spro[9:0] $2\spro[9:0] - assign $1\spro_ok[0:0] $2\spro_ok[0:0] - assign $1\trapaddr[12:0] $2\trapaddr[12:0] - assign $1\traptype[7:0] $2\traptype[7:0] - assign $1\xer_in[2:0] $2\xer_in[2:0] - assign $1\xer_out[0:0] $2\xer_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" - switch { \dec2_exc_$signal$13 \dec2_exc_$signal$12 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $2\is_32bit[0:0] $2\cr_wr_ok[0:0] $2\cr_wr[7:0] $2\cr_rd_ok[0:0] $2\cr_rd[7:0] $2\exc_$signal$9[0:0]$335 $2\exc_$signal$8[0:0]$334 $2\exc_$signal$7[0:0]$333 $2\exc_$signal$6[0:0]$332 $2\exc_$signal$5[0:0]$331 $2\exc_$signal$4[0:0]$330 $2\exc_$signal$3[0:0]$329 $2\exc_$signal[0:0]$328 $2\input_carry[1:0] $2\oe_ok[0:0] $2\oe[0:0] $2\rc_ok[0:0] $2\rc[0:0] $2\lk[0:0] $2\cr_out_ok[0:0] $2\cr_out[2:0] $2\cr_in2_ok$2[0:0]$327 $2\cr_in2$1[2:0]$326 $2\cr_in2_ok[0:0] $2\cr_in2[2:0] $2\cr_in1_ok[0:0] $2\cr_in1[2:0] $2\fasto2_ok[0:0] $2\fasto2[2:0] $2\fasto1_ok[0:0] $2\fasto1[2:0] $2\fast2_ok[0:0] $2\fast2[2:0] $2\fast1_ok[0:0] $2\fast1[2:0] $2\xer_out[0:0] $2\xer_in[2:0] $2\spr1_ok[0:0] $2\spr1[9:0] $2\spro_ok[0:0] $2\spro[9:0] $2\reg3_ok[0:0] $2\reg3[4:0] $2\reg2_ok[0:0] $2\reg2[4:0] $2\reg1_ok[0:0] $2\reg1[4:0] $2\ea_ok[0:0] $2\ea[4:0] $2\rego_ok[0:0] $2\rego[4:0] $2\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $2\insn[31:0] \dec_opcode_in - assign $2\insn_type[6:0] 7'0111111 - assign $2\fn_unit[11:0] 12'000010000000 - assign $2\trapaddr[12:0] 13'0000001100000 - assign $2\traptype[7:0] 8'00000010 - assign $2\msr[63:0] \cur_msr - assign $2\cia[63:0] \cur_pc - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\asmcode[7:0] $3\asmcode[7:0] - assign $2\cr_out[2:0] $3\cr_out[2:0] - assign $2\lk[0:0] $3\lk[0:0] - assign $2\cia[63:0] $3\cia[63:0] - assign $2\cr_in1[2:0] $3\cr_in1[2:0] - assign $2\cr_in1_ok[0:0] $3\cr_in1_ok[0:0] - assign $2\cr_in2[2:0] $3\cr_in2[2:0] - assign $2\cr_in2$1[2:0]$326 $3\cr_in2$1[2:0]$336 - assign $2\cr_in2_ok[0:0] $3\cr_in2_ok[0:0] - assign $2\cr_in2_ok$2[0:0]$327 $3\cr_in2_ok$2[0:0]$337 - assign $2\cr_out_ok[0:0] $3\cr_out_ok[0:0] - assign $2\cr_rd[7:0] $3\cr_rd[7:0] - assign $2\cr_rd_ok[0:0] $3\cr_rd_ok[0:0] - assign $2\cr_wr[7:0] $3\cr_wr[7:0] - assign $2\cr_wr_ok[0:0] $3\cr_wr_ok[0:0] - assign $2\ea[4:0] $3\ea[4:0] - assign $2\ea_ok[0:0] $3\ea_ok[0:0] - assign $2\exc_$signal[0:0]$328 $3\exc_$signal[0:0]$338 - assign $2\exc_$signal$3[0:0]$329 $3\exc_$signal$3[0:0]$339 - assign $2\exc_$signal$4[0:0]$330 $3\exc_$signal$4[0:0]$340 - assign $2\exc_$signal$5[0:0]$331 $3\exc_$signal$5[0:0]$341 - assign $2\exc_$signal$6[0:0]$332 $3\exc_$signal$6[0:0]$342 - assign $2\exc_$signal$7[0:0]$333 $3\exc_$signal$7[0:0]$343 - assign $2\exc_$signal$8[0:0]$334 $3\exc_$signal$8[0:0]$344 - assign $2\exc_$signal$9[0:0]$335 $3\exc_$signal$9[0:0]$345 - assign $2\fast1[2:0] $3\fast1[2:0] - assign $2\fast1_ok[0:0] $3\fast1_ok[0:0] - assign $2\fast2[2:0] $3\fast2[2:0] - assign $2\fast2_ok[0:0] $3\fast2_ok[0:0] - assign $2\fasto1[2:0] $3\fasto1[2:0] - assign $2\fasto1_ok[0:0] $3\fasto1_ok[0:0] - assign $2\fasto2[2:0] $3\fasto2[2:0] - assign $2\fasto2_ok[0:0] $3\fasto2_ok[0:0] - assign $2\fn_unit[11:0] $3\fn_unit[11:0] - assign $2\input_carry[1:0] $3\input_carry[1:0] - assign $2\insn[31:0] $3\insn[31:0] - assign $2\insn_type[6:0] $3\insn_type[6:0] - assign $2\is_32bit[0:0] $3\is_32bit[0:0] - assign $2\msr[63:0] $3\msr[63:0] - assign $2\oe[0:0] $3\oe[0:0] - assign $2\oe_ok[0:0] $3\oe_ok[0:0] - assign $2\rc[0:0] $3\rc[0:0] - assign $2\rc_ok[0:0] $3\rc_ok[0:0] - assign $2\reg1[4:0] $3\reg1[4:0] - assign $2\reg1_ok[0:0] $3\reg1_ok[0:0] - assign $2\reg2[4:0] $3\reg2[4:0] - assign $2\reg2_ok[0:0] $3\reg2_ok[0:0] - assign $2\reg3[4:0] $3\reg3[4:0] - assign $2\reg3_ok[0:0] $3\reg3_ok[0:0] - assign $2\rego[4:0] $3\rego[4:0] - assign $2\rego_ok[0:0] $3\rego_ok[0:0] - assign $2\spr1[9:0] $3\spr1[9:0] - assign $2\spr1_ok[0:0] $3\spr1_ok[0:0] - assign $2\spro[9:0] $3\spro[9:0] - assign $2\spro_ok[0:0] $3\spro_ok[0:0] - assign $2\trapaddr[12:0] $3\trapaddr[12:0] - assign $2\traptype[7:0] $3\traptype[7:0] - assign $2\xer_in[2:0] $3\xer_in[2:0] - assign $2\xer_out[0:0] $3\xer_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - switch \dec2_exc_$signal$14 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\exc_$signal$9[0:0]$345 $3\exc_$signal$8[0:0]$344 $3\exc_$signal$7[0:0]$343 $3\exc_$signal$6[0:0]$342 $3\exc_$signal$5[0:0]$341 $3\exc_$signal$4[0:0]$340 $3\exc_$signal$3[0:0]$339 $3\exc_$signal[0:0]$338 $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[2:0] $3\cr_in2_ok$2[0:0]$337 $3\cr_in2$1[2:0]$336 $3\cr_in2_ok[0:0] $3\cr_in2[2:0] $3\cr_in1_ok[0:0] $3\cr_in1[2:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[4:0] $3\reg2_ok[0:0] $3\reg2[4:0] $3\reg1_ok[0:0] $3\reg1[4:0] $3\ea_ok[0:0] $3\ea[4:0] $3\rego_ok[0:0] $3\rego[4:0] $3\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $3\insn[31:0] \dec_opcode_in - assign $3\insn_type[6:0] 7'0111111 - assign $3\fn_unit[11:0] 12'000010000000 - assign $3\trapaddr[12:0] 13'0000001001000 - assign $3\traptype[7:0] 8'00000010 - assign $3\msr[63:0] \cur_msr - assign $3\cia[63:0] \cur_pc - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[2:0] $3\cr_in2_ok$2[0:0]$337 $3\cr_in2$1[2:0]$336 $3\cr_in2_ok[0:0] $3\cr_in2[2:0] $3\cr_in1_ok[0:0] $3\cr_in1[2:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[4:0] $3\reg2_ok[0:0] $3\reg2[4:0] $3\reg1_ok[0:0] $3\reg1[4:0] $3\ea_ok[0:0] $3\ea[4:0] $3\rego_ok[0:0] $3\rego[4:0] $3\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $3\insn[31:0] \dec_opcode_in - assign $3\insn_type[6:0] 7'0111111 - assign $3\fn_unit[11:0] 12'000010000000 - assign $3\trapaddr[12:0] 13'0000001000000 - assign $3\traptype[7:0] 8'01000000 - assign { $3\exc_$signal$9[0:0]$345 $3\exc_$signal$8[0:0]$344 $3\exc_$signal$7[0:0]$343 $3\exc_$signal$6[0:0]$342 $3\exc_$signal$5[0:0]$341 $3\exc_$signal$4[0:0]$340 $3\exc_$signal$3[0:0]$339 $3\exc_$signal[0:0]$338 } { \dec2_exc_$signal$14 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal$15 \dec2_exc_$signal$13 \dec2_exc_$signal$12 \dec2_exc_$signal } - assign $3\msr[63:0] \cur_msr - assign $3\cia[63:0] \cur_pc - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\asmcode[7:0] $4\asmcode[7:0] - assign $2\cr_out[2:0] $4\cr_out[2:0] - assign $2\lk[0:0] $4\lk[0:0] - assign $2\cia[63:0] $4\cia[63:0] - assign $2\cr_in1[2:0] $4\cr_in1[2:0] - assign $2\cr_in1_ok[0:0] $4\cr_in1_ok[0:0] - assign $2\cr_in2[2:0] $4\cr_in2[2:0] - assign $2\cr_in2$1[2:0]$326 $4\cr_in2$1[2:0]$346 - assign $2\cr_in2_ok[0:0] $4\cr_in2_ok[0:0] - assign $2\cr_in2_ok$2[0:0]$327 $4\cr_in2_ok$2[0:0]$347 - assign $2\cr_out_ok[0:0] $4\cr_out_ok[0:0] - assign $2\cr_rd[7:0] $4\cr_rd[7:0] - assign $2\cr_rd_ok[0:0] $4\cr_rd_ok[0:0] - assign $2\cr_wr[7:0] $4\cr_wr[7:0] - assign $2\cr_wr_ok[0:0] $4\cr_wr_ok[0:0] - assign $2\ea[4:0] $4\ea[4:0] - assign $2\ea_ok[0:0] $4\ea_ok[0:0] - assign $2\exc_$signal[0:0]$328 $4\exc_$signal[0:0]$348 - assign $2\exc_$signal$3[0:0]$329 $4\exc_$signal$3[0:0]$349 - assign $2\exc_$signal$4[0:0]$330 $4\exc_$signal$4[0:0]$350 - assign $2\exc_$signal$5[0:0]$331 $4\exc_$signal$5[0:0]$351 - assign $2\exc_$signal$6[0:0]$332 $4\exc_$signal$6[0:0]$352 - assign $2\exc_$signal$7[0:0]$333 $4\exc_$signal$7[0:0]$353 - assign $2\exc_$signal$8[0:0]$334 $4\exc_$signal$8[0:0]$354 - assign $2\exc_$signal$9[0:0]$335 $4\exc_$signal$9[0:0]$355 - assign $2\fast1[2:0] $4\fast1[2:0] - assign $2\fast1_ok[0:0] $4\fast1_ok[0:0] - assign $2\fast2[2:0] $4\fast2[2:0] - assign $2\fast2_ok[0:0] $4\fast2_ok[0:0] - assign $2\fasto1[2:0] $4\fasto1[2:0] - assign $2\fasto1_ok[0:0] $4\fasto1_ok[0:0] - assign $2\fasto2[2:0] $4\fasto2[2:0] - assign $2\fasto2_ok[0:0] $4\fasto2_ok[0:0] - assign $2\fn_unit[11:0] $4\fn_unit[11:0] - assign $2\input_carry[1:0] $4\input_carry[1:0] - assign $2\insn[31:0] $4\insn[31:0] - assign $2\insn_type[6:0] $4\insn_type[6:0] - assign $2\is_32bit[0:0] $4\is_32bit[0:0] - assign $2\msr[63:0] $4\msr[63:0] - assign $2\oe[0:0] $4\oe[0:0] - assign $2\oe_ok[0:0] $4\oe_ok[0:0] - assign $2\rc[0:0] $4\rc[0:0] - assign $2\rc_ok[0:0] $4\rc_ok[0:0] - assign $2\reg1[4:0] $4\reg1[4:0] - assign $2\reg1_ok[0:0] $4\reg1_ok[0:0] - assign $2\reg2[4:0] $4\reg2[4:0] - assign $2\reg2_ok[0:0] $4\reg2_ok[0:0] - assign $2\reg3[4:0] $4\reg3[4:0] - assign $2\reg3_ok[0:0] $4\reg3_ok[0:0] - assign $2\rego[4:0] $4\rego[4:0] - assign $2\rego_ok[0:0] $4\rego_ok[0:0] - assign $2\spr1[9:0] $4\spr1[9:0] - assign $2\spr1_ok[0:0] $4\spr1_ok[0:0] - assign $2\spro[9:0] $4\spro[9:0] - assign $2\spro_ok[0:0] $4\spro_ok[0:0] - assign $2\trapaddr[12:0] $4\trapaddr[12:0] - assign $2\traptype[7:0] $4\traptype[7:0] - assign $2\xer_in[2:0] $4\xer_in[2:0] - assign $2\xer_out[0:0] $4\xer_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:926" - switch \dec2_exc_$signal$14 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$355 $4\exc_$signal$8[0:0]$354 $4\exc_$signal$7[0:0]$353 $4\exc_$signal$6[0:0]$352 $4\exc_$signal$5[0:0]$351 $4\exc_$signal$4[0:0]$350 $4\exc_$signal$3[0:0]$349 $4\exc_$signal[0:0]$348 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[2:0] $4\cr_in2_ok$2[0:0]$347 $4\cr_in2$1[2:0]$346 $4\cr_in2_ok[0:0] $4\cr_in2[2:0] $4\cr_in1_ok[0:0] $4\cr_in1[2:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[4:0] $4\reg2_ok[0:0] $4\reg2[4:0] $4\reg1_ok[0:0] $4\reg1[4:0] $4\ea_ok[0:0] $4\ea[4:0] $4\rego_ok[0:0] $4\rego[4:0] $4\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $4\insn[31:0] \dec_opcode_in - assign $4\insn_type[6:0] 7'0111111 - assign $4\fn_unit[11:0] 12'000010000000 - assign $4\trapaddr[12:0] 13'0000000111000 - assign $4\traptype[7:0] 8'00000010 - assign $4\msr[63:0] \cur_msr - assign $4\cia[63:0] \cur_pc - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$355 $4\exc_$signal$8[0:0]$354 $4\exc_$signal$7[0:0]$353 $4\exc_$signal$6[0:0]$352 $4\exc_$signal$5[0:0]$351 $4\exc_$signal$4[0:0]$350 $4\exc_$signal$3[0:0]$349 $4\exc_$signal[0:0]$348 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[2:0] $4\cr_in2_ok$2[0:0]$347 $4\cr_in2$1[2:0]$346 $4\cr_in2_ok[0:0] $4\cr_in2[2:0] $4\cr_in1_ok[0:0] $4\cr_in1[2:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[4:0] $4\reg2_ok[0:0] $4\reg2[4:0] $4\reg1_ok[0:0] $4\reg1[4:0] $4\ea_ok[0:0] $4\ea[4:0] $4\rego_ok[0:0] $4\rego[4:0] $4\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $4\insn[31:0] \dec_opcode_in - assign $4\insn_type[6:0] 7'0111111 - assign $4\fn_unit[11:0] 12'000010000000 - assign $4\trapaddr[12:0] 13'0000000110000 - assign $4\traptype[7:0] 8'00000010 - assign $4\msr[63:0] \cur_msr - assign $4\cia[63:0] \cur_pc - end - end - attribute \src "libresoc.v:0.0-0.0" - case 5'---1- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub8_ldst_len $0\dec31_dec_sub8_ldst_len[3:0] + end + attribute \src "libresoc.v:101578.3-101620.6" + process $proc$libresoc.v:101578$4124 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_upd[1:0] $1\dec31_dec_sub8_upd[1:0] + attribute \src "libresoc.v:101579.5-101579.29" + switch \initial + attribute \src "libresoc.v:101579.9-101579.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_upd $0\dec31_dec_sub8_upd[1:0] + end + attribute \src "libresoc.v:101621.3-101663.6" + process $proc$libresoc.v:101621$4125 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_rc_sel[1:0] $1\dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:101622.5-101622.29" + switch \initial + attribute \src "libresoc.v:101622.9-101622.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$325 $1\exc_$signal$8[0:0]$324 $1\exc_$signal$7[0:0]$323 $1\exc_$signal$6[0:0]$322 $1\exc_$signal$5[0:0]$321 $1\exc_$signal$4[0:0]$320 $1\exc_$signal$3[0:0]$319 $1\exc_$signal[0:0]$318 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$317 $1\cr_in2$1[2:0]$316 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $1\insn[31:0] \dec_opcode_in - assign $1\insn_type[6:0] 7'0111111 - assign $1\fn_unit[11:0] 12'000010000000 - assign $1\trapaddr[12:0] 13'0000010010000 - assign $1\traptype[7:0] 8'00100000 - assign $1\msr[63:0] \cur_msr - assign $1\cia[63:0] \cur_pc + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 5'--1-- + case 5'00111 assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_rc_sel $0\dec31_dec_sub8_rc_sel[1:0] + end + attribute \src "libresoc.v:101664.3-101706.6" + process $proc$libresoc.v:101664$4126 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_cry_in[1:0] $1\dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:101665.5-101665.29" + switch \initial + attribute \src "libresoc.v:101665.9-101665.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + case + assign $1\dec31_dec_sub8_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_cry_in $0\dec31_dec_sub8_cry_in[1:0] + end + attribute \src "libresoc.v:101707.3-101749.6" + process $proc$libresoc.v:101707$4127 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_asmcode[7:0] $1\dec31_dec_sub8_asmcode[7:0] + attribute \src "libresoc.v:101708.5-101708.29" + switch \initial + attribute \src "libresoc.v:101708.9-101708.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'10000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'10000101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'10111110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'10111111 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000111 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11001000 + case + assign $1\dec31_dec_sub8_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub8_asmcode $0\dec31_dec_sub8_asmcode[7:0] + end + attribute \src "libresoc.v:101750.3-101792.6" + process $proc$libresoc.v:101750$4128 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_inv_a[0:0] $1\dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:101751.5-101751.29" + switch \initial + attribute \src "libresoc.v:101751.9-101751.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + case + assign $1\dec31_dec_sub8_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_inv_a $0\dec31_dec_sub8_inv_a[0:0] + end + attribute \src "libresoc.v:101793.3-101835.6" + process $proc$libresoc.v:101793$4129 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_inv_out[0:0] $1\dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:101794.5-101794.29" + switch \initial + attribute \src "libresoc.v:101794.9-101794.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_inv_out $0\dec31_dec_sub8_inv_out[0:0] + end + attribute \src "libresoc.v:101836.3-101878.6" + process $proc$libresoc.v:101836$4130 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_cry_out[0:0] $1\dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:101837.5-101837.29" + switch \initial + attribute \src "libresoc.v:101837.9-101837.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$325 $1\exc_$signal$8[0:0]$324 $1\exc_$signal$7[0:0]$323 $1\exc_$signal$6[0:0]$322 $1\exc_$signal$5[0:0]$321 $1\exc_$signal$4[0:0]$320 $1\exc_$signal$3[0:0]$319 $1\exc_$signal[0:0]$318 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$317 $1\cr_in2$1[2:0]$316 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $1\insn[31:0] \dec_opcode_in - assign $1\insn_type[6:0] 7'0111111 - assign $1\fn_unit[11:0] 12'000010000000 - assign $1\trapaddr[12:0] 13'0000001010000 - assign $1\traptype[7:0] 8'00010000 - assign $1\msr[63:0] \cur_msr - assign $1\cia[63:0] \cur_pc + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'-1--- + case 5'10100 assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + case + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_cry_out $0\dec31_dec_sub8_cry_out[0:0] + end + attribute \src "libresoc.v:101879.3-101921.6" + process $proc$libresoc.v:101879$4131 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_br[0:0] $1\dec31_dec_sub8_br[0:0] + attribute \src "libresoc.v:101880.5-101880.29" + switch \initial + attribute \src "libresoc.v:101880.9-101880.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + case + assign $1\dec31_dec_sub8_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_br $0\dec31_dec_sub8_br[0:0] + end + attribute \src "libresoc.v:101922.3-101964.6" + process $proc$libresoc.v:101922$4132 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sgn_ext[0:0] $1\dec31_dec_sub8_sgn_ext[0:0] + attribute \src "libresoc.v:101923.5-101923.29" + switch \initial + attribute \src "libresoc.v:101923.9-101923.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_sgn_ext $0\dec31_dec_sub8_sgn_ext[0:0] + end + attribute \src "libresoc.v:101965.3-102007.6" + process $proc$libresoc.v:101965$4133 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_internal_op[6:0] $1\dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:101966.5-101966.29" + switch \initial + attribute \src "libresoc.v:101966.9-101966.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + case + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub8_internal_op $0\dec31_dec_sub8_internal_op[6:0] + end + attribute \src "libresoc.v:102008.3-102050.6" + process $proc$libresoc.v:102008$4134 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_rsrv[0:0] $1\dec31_dec_sub8_rsrv[0:0] + attribute \src "libresoc.v:102009.5-102009.29" + switch \initial + attribute \src "libresoc.v:102009.9-102009.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_rsrv $0\dec31_dec_sub8_rsrv[0:0] + end + attribute \src "libresoc.v:102051.3-102093.6" + process $proc$libresoc.v:102051$4135 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_is_32b[0:0] $1\dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:102052.5-102052.29" + switch \initial + attribute \src "libresoc.v:102052.9-102052.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$325 $1\exc_$signal$8[0:0]$324 $1\exc_$signal$7[0:0]$323 $1\exc_$signal$6[0:0]$322 $1\exc_$signal$5[0:0]$321 $1\exc_$signal$4[0:0]$320 $1\exc_$signal$3[0:0]$319 $1\exc_$signal[0:0]$318 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$317 $1\cr_in2$1[2:0]$316 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $1\insn[31:0] \dec_opcode_in - assign $1\insn_type[6:0] 7'0111111 - assign $1\fn_unit[11:0] 12'000010000000 - assign $1\trapaddr[12:0] 13'0000001110000 - assign $1\traptype[7:0] 8'00000010 - assign $1\msr[63:0] \cur_msr - assign $1\cia[63:0] \cur_pc + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'1---- + case 5'00100 assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_is_32b $0\dec31_dec_sub8_is_32b[0:0] + end + attribute \src "libresoc.v:102094.3-102136.6" + process $proc$libresoc.v:102094$4136 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sgn[0:0] $1\dec31_dec_sub8_sgn[0:0] + attribute \src "libresoc.v:102095.5-102095.29" + switch \initial + attribute \src "libresoc.v:102095.9-102095.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_sgn $0\dec31_dec_sub8_sgn[0:0] + end + attribute \src "libresoc.v:102137.3-102179.6" + process $proc$libresoc.v:102137$4137 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_lk[0:0] $1\dec31_dec_sub8_lk[0:0] + attribute \src "libresoc.v:102138.5-102138.29" + switch \initial + attribute \src "libresoc.v:102138.9-102138.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_lk $0\dec31_dec_sub8_lk[0:0] + end + attribute \src "libresoc.v:102180.3-102222.6" + process $proc$libresoc.v:102180$4138 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sgl_pipe[0:0] $1\dec31_dec_sub8_sgl_pipe[0:0] + attribute \src "libresoc.v:102181.5-102181.29" + switch \initial + attribute \src "libresoc.v:102181.9-102181.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_sgl_pipe $0\dec31_dec_sub8_sgl_pipe[0:0] + end + attribute \src "libresoc.v:102223.3-102265.6" + process $proc$libresoc.v:102223$4139 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_form[4:0] $1\dec31_dec_sub8_form[4:0] + attribute \src "libresoc.v:102224.5-102224.29" + switch \initial + attribute \src "libresoc.v:102224.9-102224.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + case + assign $1\dec31_dec_sub8_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub8_form $0\dec31_dec_sub8_form[4:0] + end + attribute \src "libresoc.v:102266.3-102308.6" + process $proc$libresoc.v:102266$4140 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_in1_sel[2:0] $1\dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:102267.5-102267.29" + switch \initial + attribute \src "libresoc.v:102267.9-102267.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$325 $1\exc_$signal$8[0:0]$324 $1\exc_$signal$7[0:0]$323 $1\exc_$signal$6[0:0]$322 $1\exc_$signal$5[0:0]$321 $1\exc_$signal$4[0:0]$320 $1\exc_$signal$3[0:0]$319 $1\exc_$signal[0:0]$318 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$317 $1\cr_in2$1[2:0]$316 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $1\insn[31:0] \dec_opcode_in - assign $1\insn_type[6:0] 7'0111111 - assign $1\fn_unit[11:0] 12'000010000000 - assign $1\trapaddr[12:0] 13'0000001110000 - assign $1\traptype[7:0] 8'10000000 - assign $1\msr[63:0] \cur_msr - assign $1\cia[63:0] \cur_pc + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case + case 5'10000 assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_in1_sel $0\dec31_dec_sub8_in1_sel[2:0] + end + attribute \src "libresoc.v:102309.3-102351.6" + process $proc$libresoc.v:102309$4141 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_in2_sel[3:0] $1\dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:102310.5-102310.29" + switch \initial + attribute \src "libresoc.v:102310.9-102310.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub8_in2_sel $0\dec31_dec_sub8_in2_sel[3:0] + end + attribute \src "libresoc.v:102352.3-102394.6" + process $proc$libresoc.v:102352$4142 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_in3_sel[1:0] $1\dec31_dec_sub8_in3_sel[1:0] + attribute \src "libresoc.v:102353.5-102353.29" + switch \initial + attribute \src "libresoc.v:102353.9-102353.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_in3_sel $0\dec31_dec_sub8_in3_sel[1:0] + end + attribute \src "libresoc.v:102395.3-102437.6" + process $proc$libresoc.v:102395$4143 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_out_sel[1:0] $1\dec31_dec_sub8_out_sel[1:0] + attribute \src "libresoc.v:102396.5-102396.29" + switch \initial + attribute \src "libresoc.v:102396.9-102396.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub8_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_out_sel $0\dec31_dec_sub8_out_sel[1:0] + end + attribute \src "libresoc.v:102438.3-102480.6" + process $proc$libresoc.v:102438$4144 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_cr_in[2:0] $1\dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:102439.5-102439.29" + switch \initial + attribute \src "libresoc.v:102439.9-102439.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_cr_in $0\dec31_dec_sub8_cr_in[2:0] + end + attribute \src "libresoc.v:102481.3-102523.6" + process $proc$libresoc.v:102481$4145 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_cr_out[2:0] $1\dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:102482.5-102482.29" + switch \initial + attribute \src "libresoc.v:102482.9-102482.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\trapaddr[12:0] $1\exc_$signal$9[0:0]$325 $1\exc_$signal$8[0:0]$324 $1\exc_$signal$7[0:0]$323 $1\exc_$signal$6[0:0]$322 $1\exc_$signal$5[0:0]$321 $1\exc_$signal$4[0:0]$320 $1\exc_$signal$3[0:0]$319 $1\exc_$signal[0:0]$318 $1\traptype[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\fn_unit[11:0] $1\insn_type[6:0] $1\insn[31:0] $1\cia[63:0] $1\msr[63:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$317 $1\cr_in2$1[2:0]$316 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } { \tmp_tmp_is_32bit \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd \tmp_tmp_trapaddr \tmp_tmp_exc_$signal$27 \tmp_tmp_exc_$signal$26 \tmp_tmp_exc_$signal$25 \tmp_tmp_exc_$signal$24 \tmp_tmp_exc_$signal$23 \tmp_tmp_exc_$signal$22 \tmp_tmp_exc_$signal$21 \tmp_tmp_exc_$signal \tmp_tmp_traptype \tmp_tmp_input_carry \tmp_tmp_oe_ok \tmp_tmp_oe \tmp_tmp_rc_ok \tmp_tmp_rc \tmp_tmp_lk \tmp_tmp_fn_unit \tmp_tmp_insn_type \tmp_tmp_insn \tmp_tmp_cia \tmp_tmp_msr \tmp_cr_out_ok \tmp_cr_out \tmp_cr_in2_ok$20 \tmp_cr_in2$19 \tmp_cr_in2_ok \tmp_cr_in2 \tmp_cr_in1_ok \tmp_cr_in1 \tmp_fasto2_ok \tmp_fasto2 \tmp_fasto1_ok \tmp_fasto1 \tmp_fast2_ok \tmp_fast2 \tmp_fast1_ok \tmp_fast1 \tmp_xer_out \tmp_xer_in \tmp_spr1_ok \tmp_spr1 \tmp_spro_ok \tmp_spro \tmp_reg3_ok \tmp_reg3 \tmp_reg2_ok \tmp_reg2 \tmp_reg1_ok \tmp_reg1 \tmp_ea_ok \tmp_ea \tmp_rego_ok \tmp_rego \tmp_asmcode } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:961" - switch \$32 + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } - assign $5\fasto1[2:0] 3'011 - assign $5\fasto1_ok[0:0] 1'1 - assign $5\fasto2[2:0] 3'100 - assign $5\fasto2_ok[0:0] 1'1 - case - assign $5\fasto1[2:0] $1\fasto1[2:0] - assign $5\fasto1_ok[0:0] $1\fasto1_ok[0:0] - assign $5\fasto2[2:0] $1\fasto2[2:0] - assign $5\fasto2_ok[0:0] $1\fasto2_ok[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:970" - switch \$34 + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00111 assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } - assign $5\fast1[2:0] 3'011 - assign $5\fast1_ok[0:0] 1'1 - assign $5\fast2[2:0] 3'100 - assign $5\fast2_ok[0:0] 1'1 + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 case - assign $5\fast1[2:0] $1\fast1[2:0] - assign $5\fast1_ok[0:0] $1\fast1_ok[0:0] - assign $5\fast2[2:0] $1\fast2[2:0] - assign $5\fast2_ok[0:0] $1\fast2_ok[0:0] + assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 end sync always - update \asmcode $0\asmcode[7:0] - update \cr_out $0\cr_out[2:0] - update \lk $0\lk[0:0] - update \cia $0\cia[63:0] - update \cr_in1 $0\cr_in1[2:0] - update \cr_in1_ok $0\cr_in1_ok[0:0] - update \cr_in2 $0\cr_in2[2:0] - update \cr_in2$1 $0\cr_in2$1[2:0]$306 - update \cr_in2_ok $0\cr_in2_ok[0:0] - update \cr_in2_ok$2 $0\cr_in2_ok$2[0:0]$307 - update \cr_out_ok $0\cr_out_ok[0:0] - update \cr_rd $0\cr_rd[7:0] - update \cr_rd_ok $0\cr_rd_ok[0:0] - update \cr_wr $0\cr_wr[7:0] - update \cr_wr_ok $0\cr_wr_ok[0:0] - update \ea $0\ea[4:0] - update \ea_ok $0\ea_ok[0:0] - update \exc_$signal $0\exc_$signal[0:0]$308 - update \exc_$signal$3 $0\exc_$signal$3[0:0]$309 - update \exc_$signal$4 $0\exc_$signal$4[0:0]$310 - update \exc_$signal$5 $0\exc_$signal$5[0:0]$311 - update \exc_$signal$6 $0\exc_$signal$6[0:0]$312 - update \exc_$signal$7 $0\exc_$signal$7[0:0]$313 - update \exc_$signal$8 $0\exc_$signal$8[0:0]$314 - update \exc_$signal$9 $0\exc_$signal$9[0:0]$315 - update \fast1 $0\fast1[2:0] - update \fast1_ok $0\fast1_ok[0:0] - update \fast2 $0\fast2[2:0] - update \fast2_ok $0\fast2_ok[0:0] - update \fasto1 $0\fasto1[2:0] - update \fasto1_ok $0\fasto1_ok[0:0] - update \fasto2 $0\fasto2[2:0] - update \fasto2_ok $0\fasto2_ok[0:0] - update \fn_unit $0\fn_unit[11:0] - update \input_carry $0\input_carry[1:0] - update \insn $0\insn[31:0] - update \insn_type $0\insn_type[6:0] - update \is_32bit $0\is_32bit[0:0] - update \msr $0\msr[63:0] - update \oe $0\oe[0:0] - update \oe_ok $0\oe_ok[0:0] - update \rc $0\rc[0:0] - update \rc_ok $0\rc_ok[0:0] - update \reg1 $0\reg1[4:0] - update \reg1_ok $0\reg1_ok[0:0] - update \reg2 $0\reg2[4:0] - update \reg2_ok $0\reg2_ok[0:0] - update \reg3 $0\reg3[4:0] - update \reg3_ok $0\reg3_ok[0:0] - update \rego $0\rego[4:0] - update \rego_ok $0\rego_ok[0:0] - update \spr1 $0\spr1[9:0] - update \spr1_ok $0\spr1_ok[0:0] - update \spro $0\spro[9:0] - update \spro_ok $0\spro_ok[0:0] - update \trapaddr $0\trapaddr[12:0] - update \traptype $0\traptype[7:0] - update \xer_in $0\xer_in[2:0] - update \xer_out $0\xer_out[0:0] - end - attribute \src "libresoc.v:8640.7-8640.20" - process $proc$libresoc.v:8640$356 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + update \dec31_dec_sub8_cr_out $0\dec31_dec_sub8_cr_out[2:0] end - connect \$28 $eq$libresoc.v:10231$288_Y - connect \$30 $eq$libresoc.v:10232$289_Y - connect \$32 $or$libresoc.v:10233$290_Y - connect \$34 $eq$libresoc.v:10234$291_Y - connect \$42 $eq$libresoc.v:10235$292_Y - connect \$44 $eq$libresoc.v:10236$293_Y - connect \$46 $eq$libresoc.v:10237$294_Y - connect \$48 $eq$libresoc.v:10238$295_Y - connect \$50 $and$libresoc.v:10239$296_Y - connect \$52 $and$libresoc.v:10240$297_Y - connect \$54 $and$libresoc.v:10241$298_Y - connect \$56 $eq$libresoc.v:10242$299_Y - connect \dec2_exc_$signal 1'0 - connect \dec2_exc_$signal$12 1'0 - connect \dec2_exc_$signal$13 1'0 - connect \dec2_exc_$signal$14 1'0 - connect \dec2_exc_$signal$15 1'0 - connect \dec2_exc_$signal$16 1'0 - connect \dec2_exc_$signal$17 1'0 - connect \dec2_exc_$signal$18 1'0 - connect \tmp_asmcode 8'00000000 - connect \tmp_tmp_traptype 8'00000000 - connect \tmp_tmp_exc_$signal 1'0 - connect \tmp_tmp_exc_$signal$21 1'0 - connect \tmp_tmp_exc_$signal$22 1'0 - connect \tmp_tmp_exc_$signal$23 1'0 - connect \tmp_tmp_exc_$signal$24 1'0 - connect \tmp_tmp_exc_$signal$25 1'0 - connect \tmp_tmp_exc_$signal$26 1'0 - connect \tmp_tmp_exc_$signal$27 1'0 - connect \illeg_ok \$56 - connect \priv_ok \$54 - connect \dec_irq_ok \$52 - connect \ext_irq_ok \$50 - connect { \tmp_cr_out_ok \tmp_cr_out } { \dec_cr_out_cr_bitfield_ok \dec_cr_out_cr_bitfield } - connect { \tmp_cr_in2_ok$20 \tmp_cr_in2$19 } { \dec_cr_in_cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o } - connect { \tmp_cr_in2_ok \tmp_cr_in2 } { \dec_cr_in_cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b } - connect { \tmp_cr_in1_ok \tmp_cr_in1 } { \dec_cr_in_cr_bitfield_ok \dec_cr_in_cr_bitfield } - connect { \tmp_fasto2_ok \tmp_fasto2 } { \dec_o2_fast_o_ok \dec_o2_fast_o } - connect { \tmp_fasto1_ok \tmp_fasto1 } { \dec_o_fast_o_ok \dec_o_fast_o } - connect { \tmp_fast2_ok \tmp_fast2 } { \dec_b_fast_b_ok \dec_b_fast_b } - connect { \tmp_fast1_ok \tmp_fast1 } { \dec_a_fast_a_ok \dec_a_fast_a } - connect { \tmp_spro_ok \tmp_spro } { \dec_o_spr_o_ok \dec_o_spr_o } - connect { \tmp_spr1_ok \tmp_spr1 } { \dec_a_spr_a_ok \dec_a_spr_a } - connect { \tmp_ea_ok \tmp_ea } { \dec_o2_reg_o_ok \dec_o2_reg_o } - connect { \tmp_rego_ok \tmp_rego } { \dec_o_reg_o_ok \dec_o_reg_o } - connect { \tmp_reg3_ok \tmp_reg3 } { \dec_c_reg_c_ok \dec_c_reg_c } - connect { \tmp_reg2_ok \tmp_reg2 } { \dec_b_reg_b_ok \dec_b_reg_b } - connect { \tmp_reg1_ok \tmp_reg1 } { \dec_a_reg_a_ok \dec_a_reg_a } - connect \dec_o2_lk \tmp_tmp_lk - connect \sel_in \dec_out_sel - connect \dec_o_sel_in \dec_out_sel - connect \dec_c_sel_in \dec_in3_sel - connect \dec_b_sel_in \dec_in2_sel - connect \dec_a_sel_in \dec_in1_sel - connect \insn_in$41 \dec_opcode_in - connect \insn_in$40 \dec_opcode_in - connect \insn_in$39 \dec_opcode_in - connect \insn_in$38 \dec_opcode_in - connect \insn_in$37 \dec_opcode_in - connect \tmp_tmp_insn \dec_opcode_in - connect \tmp_tmp_is_32bit \dec_is_32b - connect \tmp_tmp_input_carry \dec_cry_in - connect { \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr } { \dec_cr_out_cr_fxm_ok \dec_cr_out_cr_fxm } - connect { \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd } { \dec_cr_in_cr_fxm_ok \dec_cr_in_cr_fxm } - connect { \tmp_tmp_oe_ok \tmp_tmp_oe } { \dec_oe_oe_ok \dec_oe_oe } - connect { \tmp_tmp_rc_ok \tmp_tmp_rc } { \dec_rc_rc_ok \dec_rc_rc } - connect \tmp_tmp_fn_unit \dec_function_unit - connect \tmp_tmp_insn_type \dec_internal_op - connect \tmp_tmp_cia \cur_pc - connect \tmp_tmp_msr \cur_msr - connect \dec_cr_out_rc_in \dec_rc_rc - connect \dec_cr_out_sel_in \dec_cr_out - connect \dec_cr_in_sel_in \dec_cr_in - connect \dec_oe_sel_in \dec_rc_sel - connect \dec_rc_sel_in \dec_rc_sel - connect \dec_cr_out_insn_in \dec_opcode_in - connect \dec_cr_in_insn_in \dec_opcode_in - connect \insn_in$36 \dec_opcode_in - connect \insn_in \dec_opcode_in + connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:10680.1-11827.10" +attribute \src "libresoc.v:102529.1-104108.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec30" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub9" attribute \generator "nMigen" -module \dec30 - attribute \src "libresoc.v:11123.3-11159.6" - wire width 8 $0\dec30_asmcode[7:0] - attribute \src "libresoc.v:11271.3-11307.6" - wire $0\dec30_br[0:0] - attribute \src "libresoc.v:11752.3-11788.6" - wire width 3 $0\dec30_cr_in[2:0] - attribute \src "libresoc.v:11789.3-11825.6" - wire width 3 $0\dec30_cr_out[2:0] - attribute \src "libresoc.v:11086.3-11122.6" - wire width 2 $0\dec30_cry_in[1:0] - attribute \src "libresoc.v:11234.3-11270.6" - wire $0\dec30_cry_out[0:0] - attribute \src "libresoc.v:11567.3-11603.6" - wire width 5 $0\dec30_form[4:0] - attribute \src "libresoc.v:10938.3-10974.6" - wire width 12 $0\dec30_function_unit[11:0] - attribute \src "libresoc.v:11604.3-11640.6" - wire width 3 $0\dec30_in1_sel[2:0] - attribute \src "libresoc.v:11641.3-11677.6" - wire width 4 $0\dec30_in2_sel[3:0] - attribute \src "libresoc.v:11678.3-11714.6" - wire width 2 $0\dec30_in3_sel[1:0] - attribute \src "libresoc.v:11345.3-11381.6" - wire width 7 $0\dec30_internal_op[6:0] - attribute \src "libresoc.v:11160.3-11196.6" - wire $0\dec30_inv_a[0:0] - attribute \src "libresoc.v:11197.3-11233.6" - wire $0\dec30_inv_out[0:0] - attribute \src "libresoc.v:11419.3-11455.6" - wire $0\dec30_is_32b[0:0] - attribute \src "libresoc.v:10975.3-11011.6" - wire width 4 $0\dec30_ldst_len[3:0] - attribute \src "libresoc.v:11493.3-11529.6" - wire $0\dec30_lk[0:0] - attribute \src "libresoc.v:11715.3-11751.6" - wire width 2 $0\dec30_out_sel[1:0] - attribute \src "libresoc.v:11049.3-11085.6" - wire width 2 $0\dec30_rc_sel[1:0] - attribute \src "libresoc.v:11382.3-11418.6" - wire $0\dec30_rsrv[0:0] - attribute \src "libresoc.v:11530.3-11566.6" - wire $0\dec30_sgl_pipe[0:0] - attribute \src "libresoc.v:11456.3-11492.6" - wire $0\dec30_sgn[0:0] - attribute \src "libresoc.v:11308.3-11344.6" - wire $0\dec30_sgn_ext[0:0] - attribute \src "libresoc.v:11012.3-11048.6" - wire width 2 $0\dec30_upd[1:0] - attribute \src "libresoc.v:10681.7-10681.20" +module \dec31_dec_sub9 + attribute \src "libresoc.v:103062.3-103116.6" + wire width 8 $0\dec31_dec_sub9_asmcode[7:0] + attribute \src "libresoc.v:103282.3-103336.6" + wire $0\dec31_dec_sub9_br[0:0] + attribute \src "libresoc.v:103997.3-104051.6" + wire width 3 $0\dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:104052.3-104106.6" + wire width 3 $0\dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:103007.3-103061.6" + wire width 2 $0\dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:103227.3-103281.6" + wire $0\dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:103722.3-103776.6" + wire width 5 $0\dec31_dec_sub9_form[4:0] + attribute \src "libresoc.v:102787.3-102841.6" + wire width 12 $0\dec31_dec_sub9_function_unit[11:0] + attribute \src "libresoc.v:103777.3-103831.6" + wire width 3 $0\dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:103832.3-103886.6" + wire width 4 $0\dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:103887.3-103941.6" + wire width 2 $0\dec31_dec_sub9_in3_sel[1:0] + attribute \src "libresoc.v:103392.3-103446.6" + wire width 7 $0\dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:103117.3-103171.6" + wire $0\dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:103172.3-103226.6" + wire $0\dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:103502.3-103556.6" + wire $0\dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:102842.3-102896.6" + wire width 4 $0\dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:103612.3-103666.6" + wire $0\dec31_dec_sub9_lk[0:0] + attribute \src "libresoc.v:103942.3-103996.6" + wire width 2 $0\dec31_dec_sub9_out_sel[1:0] + attribute \src "libresoc.v:102952.3-103006.6" + wire width 2 $0\dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:103447.3-103501.6" + wire $0\dec31_dec_sub9_rsrv[0:0] + attribute \src "libresoc.v:103667.3-103721.6" + wire $0\dec31_dec_sub9_sgl_pipe[0:0] + attribute \src "libresoc.v:103557.3-103611.6" + wire $0\dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:103337.3-103391.6" + wire $0\dec31_dec_sub9_sgn_ext[0:0] + attribute \src "libresoc.v:102897.3-102951.6" + wire width 2 $0\dec31_dec_sub9_upd[1:0] + attribute \src "libresoc.v:102530.7-102530.20" wire $0\initial[0:0] - attribute \src "libresoc.v:11123.3-11159.6" - wire width 8 $1\dec30_asmcode[7:0] - attribute \src "libresoc.v:11271.3-11307.6" - wire $1\dec30_br[0:0] - attribute \src "libresoc.v:11752.3-11788.6" - wire width 3 $1\dec30_cr_in[2:0] - attribute \src "libresoc.v:11789.3-11825.6" - wire width 3 $1\dec30_cr_out[2:0] - attribute \src "libresoc.v:11086.3-11122.6" - wire width 2 $1\dec30_cry_in[1:0] - attribute \src "libresoc.v:11234.3-11270.6" - wire $1\dec30_cry_out[0:0] - attribute \src "libresoc.v:11567.3-11603.6" - wire width 5 $1\dec30_form[4:0] - attribute \src "libresoc.v:10938.3-10974.6" - wire width 12 $1\dec30_function_unit[11:0] - attribute \src "libresoc.v:11604.3-11640.6" - wire width 3 $1\dec30_in1_sel[2:0] - attribute \src "libresoc.v:11641.3-11677.6" - wire width 4 $1\dec30_in2_sel[3:0] - attribute \src "libresoc.v:11678.3-11714.6" - wire width 2 $1\dec30_in3_sel[1:0] - attribute \src "libresoc.v:11345.3-11381.6" - wire width 7 $1\dec30_internal_op[6:0] - attribute \src "libresoc.v:11160.3-11196.6" - wire $1\dec30_inv_a[0:0] - attribute \src "libresoc.v:11197.3-11233.6" - wire $1\dec30_inv_out[0:0] - attribute \src "libresoc.v:11419.3-11455.6" - wire $1\dec30_is_32b[0:0] - attribute \src "libresoc.v:10975.3-11011.6" - wire width 4 $1\dec30_ldst_len[3:0] - attribute \src "libresoc.v:11493.3-11529.6" - wire $1\dec30_lk[0:0] - attribute \src "libresoc.v:11715.3-11751.6" - wire width 2 $1\dec30_out_sel[1:0] - attribute \src "libresoc.v:11049.3-11085.6" - wire width 2 $1\dec30_rc_sel[1:0] - attribute \src "libresoc.v:11382.3-11418.6" - wire $1\dec30_rsrv[0:0] - attribute \src "libresoc.v:11530.3-11566.6" - wire $1\dec30_sgl_pipe[0:0] - attribute \src "libresoc.v:11456.3-11492.6" - wire $1\dec30_sgn[0:0] - attribute \src "libresoc.v:11308.3-11344.6" - wire $1\dec30_sgn_ext[0:0] - attribute \src "libresoc.v:11012.3-11048.6" - wire width 2 $1\dec30_upd[1:0] + attribute \src "libresoc.v:103062.3-103116.6" + wire width 8 $1\dec31_dec_sub9_asmcode[7:0] + attribute \src "libresoc.v:103282.3-103336.6" + wire $1\dec31_dec_sub9_br[0:0] + attribute \src "libresoc.v:103997.3-104051.6" + wire width 3 $1\dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:104052.3-104106.6" + wire width 3 $1\dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:103007.3-103061.6" + wire width 2 $1\dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:103227.3-103281.6" + wire $1\dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:103722.3-103776.6" + wire width 5 $1\dec31_dec_sub9_form[4:0] + attribute \src "libresoc.v:102787.3-102841.6" + wire width 12 $1\dec31_dec_sub9_function_unit[11:0] + attribute \src "libresoc.v:103777.3-103831.6" + wire width 3 $1\dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:103832.3-103886.6" + wire width 4 $1\dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:103887.3-103941.6" + wire width 2 $1\dec31_dec_sub9_in3_sel[1:0] + attribute \src "libresoc.v:103392.3-103446.6" + wire width 7 $1\dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:103117.3-103171.6" + wire $1\dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:103172.3-103226.6" + wire $1\dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:103502.3-103556.6" + wire $1\dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:102842.3-102896.6" + wire width 4 $1\dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:103612.3-103666.6" + wire $1\dec31_dec_sub9_lk[0:0] + attribute \src "libresoc.v:103942.3-103996.6" + wire width 2 $1\dec31_dec_sub9_out_sel[1:0] + attribute \src "libresoc.v:102952.3-103006.6" + wire width 2 $1\dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:103447.3-103501.6" + wire $1\dec31_dec_sub9_rsrv[0:0] + attribute \src "libresoc.v:103667.3-103721.6" + wire $1\dec31_dec_sub9_sgl_pipe[0:0] + attribute \src "libresoc.v:103557.3-103611.6" + wire $1\dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:103337.3-103391.6" + wire $1\dec31_dec_sub9_sgn_ext[0:0] + attribute \src "libresoc.v:102897.3-102951.6" + wire width 2 $1\dec31_dec_sub9_upd[1:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec30_asmcode + wire width 8 output 4 \dec31_dec_sub9_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec30_br + wire output 18 \dec31_dec_sub9_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -17196,7 +161397,7 @@ module \dec30 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec30_cr_in + wire width 3 output 9 \dec31_dec_sub9_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -17204,15 +161405,15 @@ module \dec30 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec30_cr_out + wire width 3 output 10 \dec31_dec_sub9_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec30_cry_in + wire width 2 output 14 \dec31_dec_sub9_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec30_cry_out + wire output 17 \dec31_dec_sub9_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -17244,7 +161445,7 @@ module \dec30 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec30_form + wire width 5 output 3 \dec31_dec_sub9_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -17259,7 +161460,7 @@ module \dec30 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec30_function_unit + wire width 12 output 1 \dec31_dec_sub9_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -17267,7 +161468,7 @@ module \dec30 attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec30_in1_sel + wire width 3 output 5 \dec31_dec_sub9_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -17284,13 +161485,13 @@ module \dec30 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec30_in2_sel + wire width 4 output 6 \dec31_dec_sub9_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec30_in3_sel + wire width 2 output 7 \dec31_dec_sub9_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -17366,13 +161567,13 @@ module \dec30 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec30_internal_op + wire width 7 output 2 \dec31_dec_sub9_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec30_inv_a + wire output 15 \dec31_dec_sub9_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec30_inv_out + wire output 16 \dec31_dec_sub9_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec30_is_32b + wire output 21 \dec31_dec_sub9_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" @@ -17380,1836 +161581,2152 @@ module \dec30 attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec30_ldst_len + wire width 4 output 11 \dec31_dec_sub9_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec30_lk + wire output 23 \dec31_dec_sub9_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec30_out_sel + wire width 2 output 8 \dec31_dec_sub9_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec30_rc_sel + wire width 2 output 13 \dec31_dec_sub9_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec30_rsrv + wire output 20 \dec31_dec_sub9_rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec30_sgl_pipe + wire output 24 \dec31_dec_sub9_sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec30_sgn + wire output 22 \dec31_dec_sub9_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec30_sgn_ext + wire output 19 \dec31_dec_sub9_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec30_upd - attribute \src "libresoc.v:10681.7-10681.15" + wire width 2 output 12 \dec31_dec_sub9_upd + attribute \src "libresoc.v:102530.7-102530.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 25 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 4 \opcode_switch - attribute \src "libresoc.v:10681.7-10681.20" - process $proc$libresoc.v:10681$381 + wire width 5 \opcode_switch + attribute \src "libresoc.v:102530.7-102530.20" + process $proc$libresoc.v:102530$4171 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:10938.3-10974.6" - process $proc$libresoc.v:10938$357 + attribute \src "libresoc.v:102787.3-102841.6" + process $proc$libresoc.v:102787$4147 assign { } { } assign { } { } - assign $0\dec30_function_unit[11:0] $1\dec30_function_unit[11:0] - attribute \src "libresoc.v:10939.5-10939.29" + assign $0\dec31_dec_sub9_function_unit[11:0] $1\dec31_dec_sub9_function_unit[11:0] + attribute \src "libresoc.v:102788.5-102788.29" switch \initial - attribute \src "libresoc.v:10939.9-10939.17" + attribute \src "libresoc.v:102788.9-102788.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0100 + case 5'01100 assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 attribute \src "libresoc.v:0.0-0.0" - case 4'0101 + case 5'11100 assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 attribute \src "libresoc.v:0.0-0.0" - case 4'0000 + case 5'01101 assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 attribute \src "libresoc.v:0.0-0.0" - case 4'0001 + case 5'11101 assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 attribute \src "libresoc.v:0.0-0.0" - case 4'0010 + case 5'01110 assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 attribute \src "libresoc.v:0.0-0.0" - case 4'0011 + case 5'11110 assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 attribute \src "libresoc.v:0.0-0.0" - case 4'0110 + case 5'01111 assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 attribute \src "libresoc.v:0.0-0.0" - case 4'0111 + case 5'11111 assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 attribute \src "libresoc.v:0.0-0.0" - case 4'1000 + case 5'01000 assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 attribute \src "libresoc.v:0.0-0.0" - case 4'1001 + case 5'11000 assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 case - assign $1\dec30_function_unit[11:0] 12'000000000000 + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000000000000 end sync always - update \dec30_function_unit $0\dec30_function_unit[11:0] + update \dec31_dec_sub9_function_unit $0\dec31_dec_sub9_function_unit[11:0] end - attribute \src "libresoc.v:10975.3-11011.6" - process $proc$libresoc.v:10975$358 + attribute \src "libresoc.v:102842.3-102896.6" + process $proc$libresoc.v:102842$4148 assign { } { } assign { } { } - assign $0\dec30_ldst_len[3:0] $1\dec30_ldst_len[3:0] - attribute \src "libresoc.v:10976.5-10976.29" + assign $0\dec31_dec_sub9_ldst_len[3:0] $1\dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:102843.5-102843.29" switch \initial - attribute \src "libresoc.v:10976.9-10976.17" + attribute \src "libresoc.v:102843.9-102843.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0100 + case 5'01100 assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 4'0101 + case 5'11100 assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 4'0000 + case 5'01101 assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 4'0001 + case 5'11101 assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 4'0010 + case 5'01110 assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 4'0011 + case 5'11110 assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 4'0110 + case 5'01111 assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 4'0111 + case 5'11111 assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 4'1000 + case 5'01000 assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 4'1001 + case 5'11000 assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 case - assign $1\dec30_ldst_len[3:0] 4'0000 + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 end sync always - update \dec30_ldst_len $0\dec30_ldst_len[3:0] + update \dec31_dec_sub9_ldst_len $0\dec31_dec_sub9_ldst_len[3:0] end - attribute \src "libresoc.v:11012.3-11048.6" - process $proc$libresoc.v:11012$359 + attribute \src "libresoc.v:102897.3-102951.6" + process $proc$libresoc.v:102897$4149 assign { } { } assign { } { } - assign $0\dec30_upd[1:0] $1\dec30_upd[1:0] - attribute \src "libresoc.v:11013.5-11013.29" + assign $0\dec31_dec_sub9_upd[1:0] $1\dec31_dec_sub9_upd[1:0] + attribute \src "libresoc.v:102898.5-102898.29" switch \initial - attribute \src "libresoc.v:11013.9-11013.17" + attribute \src "libresoc.v:102898.9-102898.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0100 + case 5'01100 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 4'0101 + case 5'11100 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 4'0000 + case 5'01101 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 4'0001 + case 5'11101 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 4'0010 + case 5'01110 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 4'0011 + case 5'11110 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 4'0110 + case 5'01111 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 4'0111 + case 5'11111 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 4'1000 + case 5'01000 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 4'1001 + case 5'11000 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 case - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 end sync always - update \dec30_upd $0\dec30_upd[1:0] + update \dec31_dec_sub9_upd $0\dec31_dec_sub9_upd[1:0] end - attribute \src "libresoc.v:11049.3-11085.6" - process $proc$libresoc.v:11049$360 + attribute \src "libresoc.v:102952.3-103006.6" + process $proc$libresoc.v:102952$4150 assign { } { } assign { } { } - assign $0\dec30_rc_sel[1:0] $1\dec30_rc_sel[1:0] - attribute \src "libresoc.v:11050.5-11050.29" + assign $0\dec31_dec_sub9_rc_sel[1:0] $1\dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:102953.5-102953.29" switch \initial - attribute \src "libresoc.v:11050.9-11050.17" + attribute \src "libresoc.v:102953.9-102953.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0100 + case 5'01100 assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 4'0101 + case 5'11100 assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 4'0000 + case 5'01101 assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 4'0001 + case 5'11101 assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 4'0010 + case 5'01110 assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 4'0011 + case 5'11110 assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 4'0110 + case 5'01111 assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 4'0111 + case 5'11111 assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 4'1000 + case 5'01000 assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 4'1001 + case 5'11000 assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 case - assign $1\dec30_rc_sel[1:0] 2'00 + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 end sync always - update \dec30_rc_sel $0\dec30_rc_sel[1:0] + update \dec31_dec_sub9_rc_sel $0\dec31_dec_sub9_rc_sel[1:0] end - attribute \src "libresoc.v:11086.3-11122.6" - process $proc$libresoc.v:11086$361 + attribute \src "libresoc.v:103007.3-103061.6" + process $proc$libresoc.v:103007$4151 assign { } { } assign { } { } - assign $0\dec30_cry_in[1:0] $1\dec30_cry_in[1:0] - attribute \src "libresoc.v:11087.5-11087.29" + assign $0\dec31_dec_sub9_cry_in[1:0] $1\dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:103008.5-103008.29" switch \initial - attribute \src "libresoc.v:11087.9-11087.17" + attribute \src "libresoc.v:103008.9-103008.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0100 + case 5'01100 assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 4'0101 + case 5'11100 assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 4'0000 + case 5'01101 assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 4'0001 + case 5'11101 assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 4'0010 + case 5'01110 assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 4'0011 + case 5'11110 assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 4'0110 + case 5'01111 assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 4'0111 + case 5'11111 assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 4'1000 + case 5'01000 assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 4'1001 + case 5'11000 assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 case - assign $1\dec30_cry_in[1:0] 2'00 + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 end sync always - update \dec30_cry_in $0\dec30_cry_in[1:0] + update \dec31_dec_sub9_cry_in $0\dec31_dec_sub9_cry_in[1:0] end - attribute \src "libresoc.v:11123.3-11159.6" - process $proc$libresoc.v:11123$362 + attribute \src "libresoc.v:103062.3-103116.6" + process $proc$libresoc.v:103062$4152 assign { } { } assign { } { } - assign $0\dec30_asmcode[7:0] $1\dec30_asmcode[7:0] - attribute \src "libresoc.v:11124.5-11124.29" + assign $0\dec31_dec_sub9_asmcode[7:0] $1\dec31_dec_sub9_asmcode[7:0] + attribute \src "libresoc.v:103063.5-103063.29" switch \initial - attribute \src "libresoc.v:11124.9-11124.17" + attribute \src "libresoc.v:103063.9-103063.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0100 + case 5'01100 assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010100 + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110110 attribute \src "libresoc.v:0.0-0.0" - case 4'0101 + case 5'11100 assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010100 + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110111 attribute \src "libresoc.v:0.0-0.0" - case 4'0000 + case 5'01101 assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010101 + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110100 attribute \src "libresoc.v:0.0-0.0" - case 4'0001 + case 5'11101 assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010101 + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110101 attribute \src "libresoc.v:0.0-0.0" - case 4'0010 + case 5'01110 assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010110 + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111001 attribute \src "libresoc.v:0.0-0.0" - case 4'0011 + case 5'11110 assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010110 + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111010 attribute \src "libresoc.v:0.0-0.0" - case 4'0110 + case 5'01111 assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010111 + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110011 attribute \src "libresoc.v:0.0-0.0" - case 4'0111 + case 5'11111 assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010111 + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111000 attribute \src "libresoc.v:0.0-0.0" - case 4'1000 + case 5'01000 assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010010 + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01110100 attribute \src "libresoc.v:0.0-0.0" - case 4'1001 + case 5'11000 assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010011 + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111111 case - assign $1\dec30_asmcode[7:0] 8'00000000 + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00000000 end sync always - update \dec30_asmcode $0\dec30_asmcode[7:0] + update \dec31_dec_sub9_asmcode $0\dec31_dec_sub9_asmcode[7:0] end - attribute \src "libresoc.v:11160.3-11196.6" - process $proc$libresoc.v:11160$363 + attribute \src "libresoc.v:103117.3-103171.6" + process $proc$libresoc.v:103117$4153 assign { } { } assign { } { } - assign $0\dec30_inv_a[0:0] $1\dec30_inv_a[0:0] - attribute \src "libresoc.v:11161.5-11161.29" + assign $0\dec31_dec_sub9_inv_a[0:0] $1\dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:103118.5-103118.29" switch \initial - attribute \src "libresoc.v:11161.9-11161.17" + attribute \src "libresoc.v:103118.9-103118.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0100 + case 5'01100 assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0101 + case 5'11100 assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0000 + case 5'01101 assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0001 + case 5'11101 assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0010 + case 5'01110 assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0011 + case 5'11110 assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0110 + case 5'01111 assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0111 + case 5'11111 assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'1000 + case 5'01000 assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'1001 + case 5'11000 assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 case - assign $1\dec30_inv_a[0:0] 1'0 + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 end sync always - update \dec30_inv_a $0\dec30_inv_a[0:0] + update \dec31_dec_sub9_inv_a $0\dec31_dec_sub9_inv_a[0:0] end - attribute \src "libresoc.v:11197.3-11233.6" - process $proc$libresoc.v:11197$364 + attribute \src "libresoc.v:103172.3-103226.6" + process $proc$libresoc.v:103172$4154 assign { } { } assign { } { } - assign $0\dec30_inv_out[0:0] $1\dec30_inv_out[0:0] - attribute \src "libresoc.v:11198.5-11198.29" + assign $0\dec31_dec_sub9_inv_out[0:0] $1\dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:103173.5-103173.29" switch \initial - attribute \src "libresoc.v:11198.9-11198.17" + attribute \src "libresoc.v:103173.9-103173.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0100 + case 5'01100 assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0101 + case 5'11100 assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0000 + case 5'01101 assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0001 + case 5'11101 assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0010 + case 5'01110 assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0011 + case 5'11110 assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0110 + case 5'01111 assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0111 + case 5'11111 assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'1000 + case 5'01000 assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'1001 + case 5'11000 assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 case - assign $1\dec30_inv_out[0:0] 1'0 + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 end sync always - update \dec30_inv_out $0\dec30_inv_out[0:0] + update \dec31_dec_sub9_inv_out $0\dec31_dec_sub9_inv_out[0:0] end - attribute \src "libresoc.v:11234.3-11270.6" - process $proc$libresoc.v:11234$365 + attribute \src "libresoc.v:103227.3-103281.6" + process $proc$libresoc.v:103227$4155 assign { } { } assign { } { } - assign $0\dec30_cry_out[0:0] $1\dec30_cry_out[0:0] - attribute \src "libresoc.v:11235.5-11235.29" + assign $0\dec31_dec_sub9_cry_out[0:0] $1\dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:103228.5-103228.29" switch \initial - attribute \src "libresoc.v:11235.9-11235.17" + attribute \src "libresoc.v:103228.9-103228.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0100 + case 5'01100 assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0101 + case 5'11100 assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0000 + case 5'01101 assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0001 + case 5'11101 assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0010 + case 5'01110 assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0011 + case 5'11110 assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0110 + case 5'01111 assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0111 + case 5'11111 assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'1000 + case 5'01000 assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'1001 + case 5'11000 assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 case - assign $1\dec30_cry_out[0:0] 1'0 + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 end sync always - update \dec30_cry_out $0\dec30_cry_out[0:0] + update \dec31_dec_sub9_cry_out $0\dec31_dec_sub9_cry_out[0:0] end - attribute \src "libresoc.v:11271.3-11307.6" - process $proc$libresoc.v:11271$366 + attribute \src "libresoc.v:103282.3-103336.6" + process $proc$libresoc.v:103282$4156 assign { } { } assign { } { } - assign $0\dec30_br[0:0] $1\dec30_br[0:0] - attribute \src "libresoc.v:11272.5-11272.29" + assign $0\dec31_dec_sub9_br[0:0] $1\dec31_dec_sub9_br[0:0] + attribute \src "libresoc.v:103283.5-103283.29" switch \initial - attribute \src "libresoc.v:11272.9-11272.17" + attribute \src "libresoc.v:103283.9-103283.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0100 + case 5'01100 assign { } { } - assign $1\dec30_br[0:0] 1'0 + assign $1\dec31_dec_sub9_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0101 + case 5'11100 assign { } { } - assign $1\dec30_br[0:0] 1'0 + assign $1\dec31_dec_sub9_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0000 + case 5'01101 assign { } { } - assign $1\dec30_br[0:0] 1'0 + assign $1\dec31_dec_sub9_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0001 + case 5'11101 assign { } { } - assign $1\dec30_br[0:0] 1'0 + assign $1\dec31_dec_sub9_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0010 + case 5'01110 assign { } { } - assign $1\dec30_br[0:0] 1'0 + assign $1\dec31_dec_sub9_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0011 + case 5'11110 assign { } { } - assign $1\dec30_br[0:0] 1'0 + assign $1\dec31_dec_sub9_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0110 + case 5'01111 assign { } { } - assign $1\dec30_br[0:0] 1'0 + assign $1\dec31_dec_sub9_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0111 + case 5'11111 assign { } { } - assign $1\dec30_br[0:0] 1'0 + assign $1\dec31_dec_sub9_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'1000 + case 5'01000 assign { } { } - assign $1\dec30_br[0:0] 1'0 + assign $1\dec31_dec_sub9_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'1001 + case 5'11000 assign { } { } - assign $1\dec30_br[0:0] 1'0 + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 case - assign $1\dec30_br[0:0] 1'0 + assign $1\dec31_dec_sub9_br[0:0] 1'0 end sync always - update \dec30_br $0\dec30_br[0:0] + update \dec31_dec_sub9_br $0\dec31_dec_sub9_br[0:0] end - attribute \src "libresoc.v:11308.3-11344.6" - process $proc$libresoc.v:11308$367 + attribute \src "libresoc.v:103337.3-103391.6" + process $proc$libresoc.v:103337$4157 assign { } { } assign { } { } - assign $0\dec30_sgn_ext[0:0] $1\dec30_sgn_ext[0:0] - attribute \src "libresoc.v:11309.5-11309.29" + assign $0\dec31_dec_sub9_sgn_ext[0:0] $1\dec31_dec_sub9_sgn_ext[0:0] + attribute \src "libresoc.v:103338.5-103338.29" switch \initial - attribute \src "libresoc.v:11309.9-11309.17" + attribute \src "libresoc.v:103338.9-103338.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0100 + case 5'01100 assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0101 + case 5'11100 assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0000 + case 5'01101 assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0001 + case 5'11101 assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0010 + case 5'01110 assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0011 + case 5'11110 assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0110 + case 5'01111 assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0111 + case 5'11111 assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'1000 + case 5'01000 assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'1001 + case 5'11000 assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 case - assign $1\dec30_sgn_ext[0:0] 1'0 + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 end sync always - update \dec30_sgn_ext $0\dec30_sgn_ext[0:0] + update \dec31_dec_sub9_sgn_ext $0\dec31_dec_sub9_sgn_ext[0:0] end - attribute \src "libresoc.v:11345.3-11381.6" - process $proc$libresoc.v:11345$368 + attribute \src "libresoc.v:103392.3-103446.6" + process $proc$libresoc.v:103392$4158 assign { } { } assign { } { } - assign $0\dec30_internal_op[6:0] $1\dec30_internal_op[6:0] - attribute \src "libresoc.v:11346.5-11346.29" + assign $0\dec31_dec_sub9_internal_op[6:0] $1\dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:103393.5-103393.29" switch \initial - attribute \src "libresoc.v:11346.9-11346.17" + attribute \src "libresoc.v:103393.9-103393.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0100 + case 5'01100 assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111000 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 attribute \src "libresoc.v:0.0-0.0" - case 4'0101 + case 5'11100 assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111000 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 attribute \src "libresoc.v:0.0-0.0" - case 4'0000 + case 5'01101 assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111001 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 attribute \src "libresoc.v:0.0-0.0" - case 4'0001 + case 5'11101 assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111001 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 attribute \src "libresoc.v:0.0-0.0" - case 4'0010 + case 5'01110 assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111010 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 attribute \src "libresoc.v:0.0-0.0" - case 4'0011 + case 5'11110 assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111010 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 attribute \src "libresoc.v:0.0-0.0" - case 4'0110 + case 5'01111 assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111000 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 attribute \src "libresoc.v:0.0-0.0" - case 4'0111 + case 5'11111 assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111000 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 attribute \src "libresoc.v:0.0-0.0" - case 4'1000 + case 5'01000 assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111001 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 attribute \src "libresoc.v:0.0-0.0" - case 4'1001 + case 5'11000 assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111010 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 case - assign $1\dec30_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0000000 end sync always - update \dec30_internal_op $0\dec30_internal_op[6:0] + update \dec31_dec_sub9_internal_op $0\dec31_dec_sub9_internal_op[6:0] end - attribute \src "libresoc.v:11382.3-11418.6" - process $proc$libresoc.v:11382$369 + attribute \src "libresoc.v:103447.3-103501.6" + process $proc$libresoc.v:103447$4159 assign { } { } assign { } { } - assign $0\dec30_rsrv[0:0] $1\dec30_rsrv[0:0] - attribute \src "libresoc.v:11383.5-11383.29" + assign $0\dec31_dec_sub9_rsrv[0:0] $1\dec31_dec_sub9_rsrv[0:0] + attribute \src "libresoc.v:103448.5-103448.29" switch \initial - attribute \src "libresoc.v:11383.9-11383.17" + attribute \src "libresoc.v:103448.9-103448.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0100 + case 5'01100 assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0101 + case 5'11100 assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0000 + case 5'01101 assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0001 + case 5'11101 assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0010 + case 5'01110 assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0011 + case 5'11110 assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0110 + case 5'01111 assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0111 + case 5'11111 assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'1000 + case 5'01000 assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'1001 + case 5'11000 assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 case - assign $1\dec30_rsrv[0:0] 1'0 + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 end sync always - update \dec30_rsrv $0\dec30_rsrv[0:0] + update \dec31_dec_sub9_rsrv $0\dec31_dec_sub9_rsrv[0:0] end - attribute \src "libresoc.v:11419.3-11455.6" - process $proc$libresoc.v:11419$370 + attribute \src "libresoc.v:103502.3-103556.6" + process $proc$libresoc.v:103502$4160 assign { } { } assign { } { } - assign $0\dec30_is_32b[0:0] $1\dec30_is_32b[0:0] - attribute \src "libresoc.v:11420.5-11420.29" + assign $0\dec31_dec_sub9_is_32b[0:0] $1\dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:103503.5-103503.29" switch \initial - attribute \src "libresoc.v:11420.9-11420.17" + attribute \src "libresoc.v:103503.9-103503.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0100 + case 5'01100 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0101 + case 5'11100 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0000 + case 5'01101 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0001 + case 5'11101 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0010 + case 5'01110 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0011 + case 5'11110 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0110 + case 5'01111 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0111 + case 5'11111 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'1000 + case 5'01000 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'1001 + case 5'11000 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 case - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 end sync always - update \dec30_is_32b $0\dec30_is_32b[0:0] + update \dec31_dec_sub9_is_32b $0\dec31_dec_sub9_is_32b[0:0] end - attribute \src "libresoc.v:11456.3-11492.6" - process $proc$libresoc.v:11456$371 + attribute \src "libresoc.v:103557.3-103611.6" + process $proc$libresoc.v:103557$4161 assign { } { } assign { } { } - assign $0\dec30_sgn[0:0] $1\dec30_sgn[0:0] - attribute \src "libresoc.v:11457.5-11457.29" + assign $0\dec31_dec_sub9_sgn[0:0] $1\dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:103558.5-103558.29" switch \initial - attribute \src "libresoc.v:11457.9-11457.17" + attribute \src "libresoc.v:103558.9-103558.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0100 + case 5'01100 assign { } { } - assign $1\dec30_sgn[0:0] 1'0 + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0101 + case 5'11100 assign { } { } - assign $1\dec30_sgn[0:0] 1'0 + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0000 + case 5'01101 assign { } { } - assign $1\dec30_sgn[0:0] 1'0 + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 4'0001 + case 5'11101 assign { } { } - assign $1\dec30_sgn[0:0] 1'0 + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 4'0010 + case 5'01110 assign { } { } - assign $1\dec30_sgn[0:0] 1'0 + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0011 + case 5'11110 assign { } { } - assign $1\dec30_sgn[0:0] 1'0 + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0110 + case 5'01111 assign { } { } - assign $1\dec30_sgn[0:0] 1'0 + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 4'0111 + case 5'11111 assign { } { } - assign $1\dec30_sgn[0:0] 1'0 + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 4'1000 + case 5'01000 assign { } { } - assign $1\dec30_sgn[0:0] 1'0 + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'1001 + case 5'11000 assign { } { } - assign $1\dec30_sgn[0:0] 1'0 + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 case - assign $1\dec30_sgn[0:0] 1'0 + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 end sync always - update \dec30_sgn $0\dec30_sgn[0:0] + update \dec31_dec_sub9_sgn $0\dec31_dec_sub9_sgn[0:0] end - attribute \src "libresoc.v:11493.3-11529.6" - process $proc$libresoc.v:11493$372 + attribute \src "libresoc.v:103612.3-103666.6" + process $proc$libresoc.v:103612$4162 assign { } { } assign { } { } - assign $0\dec30_lk[0:0] $1\dec30_lk[0:0] - attribute \src "libresoc.v:11494.5-11494.29" + assign $0\dec31_dec_sub9_lk[0:0] $1\dec31_dec_sub9_lk[0:0] + attribute \src "libresoc.v:103613.5-103613.29" switch \initial - attribute \src "libresoc.v:11494.9-11494.17" + attribute \src "libresoc.v:103613.9-103613.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0100 + case 5'01100 assign { } { } - assign $1\dec30_lk[0:0] 1'0 + assign $1\dec31_dec_sub9_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0101 + case 5'11100 assign { } { } - assign $1\dec30_lk[0:0] 1'0 + assign $1\dec31_dec_sub9_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0000 + case 5'01101 assign { } { } - assign $1\dec30_lk[0:0] 1'0 + assign $1\dec31_dec_sub9_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0001 + case 5'11101 assign { } { } - assign $1\dec30_lk[0:0] 1'0 + assign $1\dec31_dec_sub9_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0010 + case 5'01110 assign { } { } - assign $1\dec30_lk[0:0] 1'0 + assign $1\dec31_dec_sub9_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0011 + case 5'11110 assign { } { } - assign $1\dec30_lk[0:0] 1'0 + assign $1\dec31_dec_sub9_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0110 + case 5'01111 assign { } { } - assign $1\dec30_lk[0:0] 1'0 + assign $1\dec31_dec_sub9_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0111 + case 5'11111 assign { } { } - assign $1\dec30_lk[0:0] 1'0 + assign $1\dec31_dec_sub9_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'1000 + case 5'01000 assign { } { } - assign $1\dec30_lk[0:0] 1'0 + assign $1\dec31_dec_sub9_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'1001 + case 5'11000 assign { } { } - assign $1\dec30_lk[0:0] 1'0 + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 case - assign $1\dec30_lk[0:0] 1'0 + assign $1\dec31_dec_sub9_lk[0:0] 1'0 end sync always - update \dec30_lk $0\dec30_lk[0:0] + update \dec31_dec_sub9_lk $0\dec31_dec_sub9_lk[0:0] end - attribute \src "libresoc.v:11530.3-11566.6" - process $proc$libresoc.v:11530$373 + attribute \src "libresoc.v:103667.3-103721.6" + process $proc$libresoc.v:103667$4163 assign { } { } assign { } { } - assign $0\dec30_sgl_pipe[0:0] $1\dec30_sgl_pipe[0:0] - attribute \src "libresoc.v:11531.5-11531.29" + assign $0\dec31_dec_sub9_sgl_pipe[0:0] $1\dec31_dec_sub9_sgl_pipe[0:0] + attribute \src "libresoc.v:103668.5-103668.29" switch \initial - attribute \src "libresoc.v:11531.9-11531.17" + attribute \src "libresoc.v:103668.9-103668.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0100 + case 5'01100 assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0101 + case 5'11100 assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0000 + case 5'01101 assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0001 + case 5'11101 assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0010 + case 5'01110 assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0011 + case 5'11110 assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0110 + case 5'01111 assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'0111 + case 5'11111 assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'1000 + case 5'01000 assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 4'1001 + case 5'11000 assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 case - assign $1\dec30_sgl_pipe[0:0] 1'0 + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 end sync always - update \dec30_sgl_pipe $0\dec30_sgl_pipe[0:0] + update \dec31_dec_sub9_sgl_pipe $0\dec31_dec_sub9_sgl_pipe[0:0] end - attribute \src "libresoc.v:11567.3-11603.6" - process $proc$libresoc.v:11567$374 + attribute \src "libresoc.v:103722.3-103776.6" + process $proc$libresoc.v:103722$4164 assign { } { } assign { } { } - assign $0\dec30_form[4:0] $1\dec30_form[4:0] - attribute \src "libresoc.v:11568.5-11568.29" + assign $0\dec31_dec_sub9_form[4:0] $1\dec31_dec_sub9_form[4:0] + attribute \src "libresoc.v:103723.5-103723.29" switch \initial - attribute \src "libresoc.v:11568.9-11568.17" + attribute \src "libresoc.v:103723.9-103723.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0100 + case 5'01100 assign { } { } - assign $1\dec30_form[4:0] 5'10100 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" - case 4'0101 + case 5'11100 assign { } { } - assign $1\dec30_form[4:0] 5'10100 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" - case 4'0000 + case 5'01101 assign { } { } - assign $1\dec30_form[4:0] 5'10101 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" - case 4'0001 + case 5'11101 assign { } { } - assign $1\dec30_form[4:0] 5'10101 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" - case 4'0010 + case 5'01110 assign { } { } - assign $1\dec30_form[4:0] 5'10100 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" - case 4'0011 + case 5'11110 assign { } { } - assign $1\dec30_form[4:0] 5'10100 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" - case 4'0110 + case 5'01111 assign { } { } - assign $1\dec30_form[4:0] 5'10100 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" - case 4'0111 + case 5'11111 assign { } { } - assign $1\dec30_form[4:0] 5'10100 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" - case 4'1000 + case 5'01000 assign { } { } - assign $1\dec30_form[4:0] 5'10100 + assign $1\dec31_dec_sub9_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 4'1001 + case 5'11000 assign { } { } - assign $1\dec30_form[4:0] 5'10100 + assign $1\dec31_dec_sub9_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 case - assign $1\dec30_form[4:0] 5'00000 + assign $1\dec31_dec_sub9_form[4:0] 5'00000 end sync always - update \dec30_form $0\dec30_form[4:0] + update \dec31_dec_sub9_form $0\dec31_dec_sub9_form[4:0] end - attribute \src "libresoc.v:11604.3-11640.6" - process $proc$libresoc.v:11604$375 + attribute \src "libresoc.v:103777.3-103831.6" + process $proc$libresoc.v:103777$4165 assign { } { } assign { } { } - assign $0\dec30_in1_sel[2:0] $1\dec30_in1_sel[2:0] - attribute \src "libresoc.v:11605.5-11605.29" + assign $0\dec31_dec_sub9_in1_sel[2:0] $1\dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:103778.5-103778.29" switch \initial - attribute \src "libresoc.v:11605.9-11605.17" + attribute \src "libresoc.v:103778.9-103778.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0100 + case 5'01100 assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 4'0101 + case 5'11100 assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 4'0000 + case 5'01101 assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 4'0001 + case 5'11101 assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 4'0010 + case 5'01110 assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 4'0011 + case 5'11110 assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 4'0110 + case 5'01111 assign { } { } - assign $1\dec30_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 4'0111 + case 5'11111 assign { } { } - assign $1\dec30_in1_sel[2:0] 3'001 + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 4'1000 + case 5'01000 assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 4'1001 + case 5'11000 assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 case - assign $1\dec30_in1_sel[2:0] 3'000 + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'000 end sync always - update \dec30_in1_sel $0\dec30_in1_sel[2:0] + update \dec31_dec_sub9_in1_sel $0\dec31_dec_sub9_in1_sel[2:0] end - attribute \src "libresoc.v:11641.3-11677.6" - process $proc$libresoc.v:11641$376 + attribute \src "libresoc.v:103832.3-103886.6" + process $proc$libresoc.v:103832$4166 assign { } { } assign { } { } - assign $0\dec30_in2_sel[3:0] $1\dec30_in2_sel[3:0] - attribute \src "libresoc.v:11642.5-11642.29" + assign $0\dec31_dec_sub9_in2_sel[3:0] $1\dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:103833.5-103833.29" switch \initial - attribute \src "libresoc.v:11642.9-11642.17" + attribute \src "libresoc.v:103833.9-103833.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0100 + case 5'01100 assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 4'0101 + case 5'11100 assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 4'0000 + case 5'01101 assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 4'0001 + case 5'11101 assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 4'0010 + case 5'01110 assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 4'0011 + case 5'11110 assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 4'0110 + case 5'01111 assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 4'0111 + case 5'11111 assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 4'1000 + case 5'01000 assign { } { } - assign $1\dec30_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 4'1001 + case 5'11000 assign { } { } - assign $1\dec30_in2_sel[3:0] 4'0001 + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 case - assign $1\dec30_in2_sel[3:0] 4'0000 + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0000 end sync always - update \dec30_in2_sel $0\dec30_in2_sel[3:0] + update \dec31_dec_sub9_in2_sel $0\dec31_dec_sub9_in2_sel[3:0] end - attribute \src "libresoc.v:11678.3-11714.6" - process $proc$libresoc.v:11678$377 + attribute \src "libresoc.v:103887.3-103941.6" + process $proc$libresoc.v:103887$4167 assign { } { } assign { } { } - assign $0\dec30_in3_sel[1:0] $1\dec30_in3_sel[1:0] - attribute \src "libresoc.v:11679.5-11679.29" + assign $0\dec31_dec_sub9_in3_sel[1:0] $1\dec31_dec_sub9_in3_sel[1:0] + attribute \src "libresoc.v:103888.5-103888.29" switch \initial - attribute \src "libresoc.v:11679.9-11679.17" + attribute \src "libresoc.v:103888.9-103888.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0100 + case 5'01100 assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 4'0101 + case 5'11100 assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 4'0000 + case 5'01101 assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 4'0001 + case 5'11101 assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 4'0010 + case 5'01110 assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 4'0011 + case 5'11110 assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 4'0110 + case 5'01111 assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 4'0111 + case 5'11111 assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 4'1000 + case 5'01000 assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 4'1001 + case 5'11000 assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 case - assign $1\dec30_in3_sel[1:0] 2'00 + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 end sync always - update \dec30_in3_sel $0\dec30_in3_sel[1:0] + update \dec31_dec_sub9_in3_sel $0\dec31_dec_sub9_in3_sel[1:0] end - attribute \src "libresoc.v:11715.3-11751.6" - process $proc$libresoc.v:11715$378 + attribute \src "libresoc.v:103942.3-103996.6" + process $proc$libresoc.v:103942$4168 assign { } { } assign { } { } - assign $0\dec30_out_sel[1:0] $1\dec30_out_sel[1:0] - attribute \src "libresoc.v:11716.5-11716.29" + assign $0\dec31_dec_sub9_out_sel[1:0] $1\dec31_dec_sub9_out_sel[1:0] + attribute \src "libresoc.v:103943.5-103943.29" switch \initial - attribute \src "libresoc.v:11716.9-11716.17" + attribute \src "libresoc.v:103943.9-103943.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0100 + case 5'01100 assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 4'0101 + case 5'11100 assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 4'0000 + case 5'01101 assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 4'0001 + case 5'11101 assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 4'0010 + case 5'01110 assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 4'0011 + case 5'11110 assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 4'0110 + case 5'01111 assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 4'0111 + case 5'11111 assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 4'1000 + case 5'01000 assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 4'1001 + case 5'11000 assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 case - assign $1\dec30_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub9_out_sel[1:0] 2'00 end sync always - update \dec30_out_sel $0\dec30_out_sel[1:0] + update \dec31_dec_sub9_out_sel $0\dec31_dec_sub9_out_sel[1:0] end - attribute \src "libresoc.v:11752.3-11788.6" - process $proc$libresoc.v:11752$379 + attribute \src "libresoc.v:103997.3-104051.6" + process $proc$libresoc.v:103997$4169 assign { } { } assign { } { } - assign $0\dec30_cr_in[2:0] $1\dec30_cr_in[2:0] - attribute \src "libresoc.v:11753.5-11753.29" + assign $0\dec31_dec_sub9_cr_in[2:0] $1\dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:103998.5-103998.29" switch \initial - attribute \src "libresoc.v:11753.9-11753.17" + attribute \src "libresoc.v:103998.9-103998.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0100 + case 5'01100 assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 4'0101 + case 5'11100 assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 4'0000 + case 5'01101 assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 4'0001 + case 5'11101 assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 4'0010 + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 4'0011 + case 5'00000 assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 4'0110 + case 5'10010 assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 4'0111 + case 5'10000 assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 4'1000 + case 5'00111 assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 4'1001 + case 5'10111 assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 case - assign $1\dec30_cr_in[2:0] 3'000 + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 end sync always - update \dec30_cr_in $0\dec30_cr_in[2:0] + update \dec31_dec_sub9_cr_in $0\dec31_dec_sub9_cr_in[2:0] end - attribute \src "libresoc.v:11789.3-11825.6" - process $proc$libresoc.v:11789$380 + attribute \src "libresoc.v:104052.3-104106.6" + process $proc$libresoc.v:104052$4170 assign { } { } assign { } { } - assign $0\dec30_cr_out[2:0] $1\dec30_cr_out[2:0] - attribute \src "libresoc.v:11790.5-11790.29" + assign $0\dec31_dec_sub9_cr_out[2:0] $1\dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:104053.5-104053.29" switch \initial - attribute \src "libresoc.v:11790.9-11790.17" + attribute \src "libresoc.v:104053.9-104053.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 4'0100 + case 5'01100 assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 4'0101 + case 5'11100 assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 4'0000 + case 5'01101 assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 4'0001 + case 5'11101 assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 4'0010 + case 5'01110 assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 4'0011 + case 5'11110 assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 4'0110 + case 5'01111 assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 4'0111 + case 5'11111 assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 4'1000 + case 5'01000 assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 4'1001 + case 5'11000 assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 case - assign $1\dec30_cr_out[2:0] 3'000 + assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 end sync always - update \dec30_cr_out $0\dec30_cr_out[2:0] + update \dec31_dec_sub9_cr_out $0\dec31_dec_sub9_cr_out[2:0] end - connect \opcode_switch \opcode_in [4:1] + connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:11831.1-18201.10" +attribute \src "libresoc.v:104112.1-104755.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec58" attribute \generator "nMigen" -module \dec31 - attribute \src "libresoc.v:16900.3-16960.6" - wire width 8 $0\dec31_asmcode[7:0] - attribute \src "libresoc.v:17754.3-17814.6" - wire $0\dec31_br[0:0] - attribute \src "libresoc.v:17205.3-17265.6" - wire width 3 $0\dec31_cr_in[2:0] - attribute \src "libresoc.v:17266.3-17326.6" - wire width 3 $0\dec31_cr_out[2:0] - attribute \src "libresoc.v:17510.3-17570.6" - wire width 2 $0\dec31_cry_in[1:0] - attribute \src "libresoc.v:17693.3-17753.6" - wire $0\dec31_cry_out[0:0] - attribute \src "libresoc.v:16839.3-16899.6" - wire width 5 $0\dec31_form[4:0] - attribute \src "libresoc.v:16717.3-16777.6" - wire width 12 $0\dec31_function_unit[11:0] - attribute \src "libresoc.v:16961.3-17021.6" - wire width 3 $0\dec31_in1_sel[2:0] - attribute \src "libresoc.v:17022.3-17082.6" - wire width 4 $0\dec31_in2_sel[3:0] - attribute \src "libresoc.v:17083.3-17143.6" - wire width 2 $0\dec31_in3_sel[1:0] - attribute \src "libresoc.v:16778.3-16838.6" - wire width 7 $0\dec31_internal_op[6:0] - attribute \src "libresoc.v:17571.3-17631.6" - wire $0\dec31_inv_a[0:0] - attribute \src "libresoc.v:17632.3-17692.6" - wire $0\dec31_inv_out[0:0] - attribute \src "libresoc.v:17937.3-17997.6" - wire $0\dec31_is_32b[0:0] - attribute \src "libresoc.v:17327.3-17387.6" - wire width 4 $0\dec31_ldst_len[3:0] - attribute \src "libresoc.v:18059.3-18119.6" - wire $0\dec31_lk[0:0] - attribute \src "libresoc.v:17144.3-17204.6" - wire width 2 $0\dec31_out_sel[1:0] - attribute \src "libresoc.v:17449.3-17509.6" - wire width 2 $0\dec31_rc_sel[1:0] - attribute \src "libresoc.v:17876.3-17936.6" - wire $0\dec31_rsrv[0:0] - attribute \src "libresoc.v:18120.3-18180.6" - wire $0\dec31_sgl_pipe[0:0] - attribute \src "libresoc.v:17998.3-18058.6" - wire $0\dec31_sgn[0:0] - attribute \src "libresoc.v:17815.3-17875.6" - wire $0\dec31_sgn_ext[0:0] - attribute \src "libresoc.v:17388.3-17448.6" - wire width 2 $0\dec31_upd[1:0] - attribute \src "libresoc.v:11832.7-11832.20" +module \dec58 + attribute \src "libresoc.v:104450.3-104465.6" + wire width 8 $0\dec58_asmcode[7:0] + attribute \src "libresoc.v:104514.3-104529.6" + wire $0\dec58_br[0:0] + attribute \src "libresoc.v:104722.3-104737.6" + wire width 3 $0\dec58_cr_in[2:0] + attribute \src "libresoc.v:104738.3-104753.6" + wire width 3 $0\dec58_cr_out[2:0] + attribute \src "libresoc.v:104434.3-104449.6" + wire width 2 $0\dec58_cry_in[1:0] + attribute \src "libresoc.v:104498.3-104513.6" + wire $0\dec58_cry_out[0:0] + attribute \src "libresoc.v:104642.3-104657.6" + wire width 5 $0\dec58_form[4:0] + attribute \src "libresoc.v:104370.3-104385.6" + wire width 12 $0\dec58_function_unit[11:0] + attribute \src "libresoc.v:104658.3-104673.6" + wire width 3 $0\dec58_in1_sel[2:0] + attribute \src "libresoc.v:104674.3-104689.6" + wire width 4 $0\dec58_in2_sel[3:0] + attribute \src "libresoc.v:104690.3-104705.6" + wire width 2 $0\dec58_in3_sel[1:0] + attribute \src "libresoc.v:104546.3-104561.6" + wire width 7 $0\dec58_internal_op[6:0] + attribute \src "libresoc.v:104466.3-104481.6" + wire $0\dec58_inv_a[0:0] + attribute \src "libresoc.v:104482.3-104497.6" + wire $0\dec58_inv_out[0:0] + attribute \src "libresoc.v:104578.3-104593.6" + wire $0\dec58_is_32b[0:0] + attribute \src "libresoc.v:104386.3-104401.6" + wire width 4 $0\dec58_ldst_len[3:0] + attribute \src "libresoc.v:104610.3-104625.6" + wire $0\dec58_lk[0:0] + attribute \src "libresoc.v:104706.3-104721.6" + wire width 2 $0\dec58_out_sel[1:0] + attribute \src "libresoc.v:104418.3-104433.6" + wire width 2 $0\dec58_rc_sel[1:0] + attribute \src "libresoc.v:104562.3-104577.6" + wire $0\dec58_rsrv[0:0] + attribute \src "libresoc.v:104626.3-104641.6" + wire $0\dec58_sgl_pipe[0:0] + attribute \src "libresoc.v:104594.3-104609.6" + wire $0\dec58_sgn[0:0] + attribute \src "libresoc.v:104530.3-104545.6" + wire $0\dec58_sgn_ext[0:0] + attribute \src "libresoc.v:104402.3-104417.6" + wire width 2 $0\dec58_upd[1:0] + attribute \src "libresoc.v:104113.7-104113.20" wire $0\initial[0:0] - attribute \src "libresoc.v:16900.3-16960.6" - wire width 8 $1\dec31_asmcode[7:0] - attribute \src "libresoc.v:17754.3-17814.6" - wire $1\dec31_br[0:0] - attribute \src "libresoc.v:17205.3-17265.6" - wire width 3 $1\dec31_cr_in[2:0] - attribute \src "libresoc.v:17266.3-17326.6" - wire width 3 $1\dec31_cr_out[2:0] - attribute \src "libresoc.v:17510.3-17570.6" - wire width 2 $1\dec31_cry_in[1:0] - attribute \src "libresoc.v:17693.3-17753.6" - wire $1\dec31_cry_out[0:0] - attribute \src "libresoc.v:16839.3-16899.6" - wire width 5 $1\dec31_form[4:0] - attribute \src "libresoc.v:16717.3-16777.6" - wire width 12 $1\dec31_function_unit[11:0] - attribute \src "libresoc.v:16961.3-17021.6" - wire width 3 $1\dec31_in1_sel[2:0] - attribute \src "libresoc.v:17022.3-17082.6" - wire width 4 $1\dec31_in2_sel[3:0] - attribute \src "libresoc.v:17083.3-17143.6" - wire width 2 $1\dec31_in3_sel[1:0] - attribute \src "libresoc.v:16778.3-16838.6" - wire width 7 $1\dec31_internal_op[6:0] - attribute \src "libresoc.v:17571.3-17631.6" - wire $1\dec31_inv_a[0:0] - attribute \src "libresoc.v:17632.3-17692.6" - wire $1\dec31_inv_out[0:0] - attribute \src "libresoc.v:17937.3-17997.6" - wire $1\dec31_is_32b[0:0] - attribute \src "libresoc.v:17327.3-17387.6" - wire width 4 $1\dec31_ldst_len[3:0] - attribute \src "libresoc.v:18059.3-18119.6" - wire $1\dec31_lk[0:0] - attribute \src "libresoc.v:17144.3-17204.6" - wire width 2 $1\dec31_out_sel[1:0] - attribute \src "libresoc.v:17449.3-17509.6" - wire width 2 $1\dec31_rc_sel[1:0] - attribute \src "libresoc.v:17876.3-17936.6" - wire $1\dec31_rsrv[0:0] - attribute \src "libresoc.v:18120.3-18180.6" - wire $1\dec31_sgl_pipe[0:0] - attribute \src "libresoc.v:17998.3-18058.6" - wire $1\dec31_sgn[0:0] - attribute \src "libresoc.v:17815.3-17875.6" - wire $1\dec31_sgn_ext[0:0] - attribute \src "libresoc.v:17388.3-17448.6" - wire width 2 $1\dec31_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 \dec31_dec_sub0_dec31_dec_sub0_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub0_dec31_dec_sub0_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub0_dec31_dec_sub0_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub0_dec31_dec_sub0_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub0_dec31_dec_sub0_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub0_dec31_dec_sub0_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 \dec31_dec_sub0_dec31_dec_sub0_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec_sub0_dec31_dec_sub0_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub0_dec31_dec_sub0_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec_sub0_dec31_dec_sub0_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub0_dec31_dec_sub0_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec31_dec_sub0_dec31_dec_sub0_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub0_dec31_dec_sub0_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub0_dec31_dec_sub0_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub0_dec31_dec_sub0_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec_sub0_dec31_dec_sub0_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub0_dec31_dec_sub0_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub0_dec31_dec_sub0_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub0_dec31_dec_sub0_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub0_dec31_dec_sub0_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub0_dec31_dec_sub0_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub0_dec31_dec_sub0_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub0_dec31_dec_sub0_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec31_dec_sub0_opcode_in + attribute \src "libresoc.v:104450.3-104465.6" + wire width 8 $1\dec58_asmcode[7:0] + attribute \src "libresoc.v:104514.3-104529.6" + wire $1\dec58_br[0:0] + attribute \src "libresoc.v:104722.3-104737.6" + wire width 3 $1\dec58_cr_in[2:0] + attribute \src "libresoc.v:104738.3-104753.6" + wire width 3 $1\dec58_cr_out[2:0] + attribute \src "libresoc.v:104434.3-104449.6" + wire width 2 $1\dec58_cry_in[1:0] + attribute \src "libresoc.v:104498.3-104513.6" + wire $1\dec58_cry_out[0:0] + attribute \src "libresoc.v:104642.3-104657.6" + wire width 5 $1\dec58_form[4:0] + attribute \src "libresoc.v:104370.3-104385.6" + wire width 12 $1\dec58_function_unit[11:0] + attribute \src "libresoc.v:104658.3-104673.6" + wire width 3 $1\dec58_in1_sel[2:0] + attribute \src "libresoc.v:104674.3-104689.6" + wire width 4 $1\dec58_in2_sel[3:0] + attribute \src "libresoc.v:104690.3-104705.6" + wire width 2 $1\dec58_in3_sel[1:0] + attribute \src "libresoc.v:104546.3-104561.6" + wire width 7 $1\dec58_internal_op[6:0] + attribute \src "libresoc.v:104466.3-104481.6" + wire $1\dec58_inv_a[0:0] + attribute \src "libresoc.v:104482.3-104497.6" + wire $1\dec58_inv_out[0:0] + attribute \src "libresoc.v:104578.3-104593.6" + wire $1\dec58_is_32b[0:0] + attribute \src "libresoc.v:104386.3-104401.6" + wire width 4 $1\dec58_ldst_len[3:0] + attribute \src "libresoc.v:104610.3-104625.6" + wire $1\dec58_lk[0:0] + attribute \src "libresoc.v:104706.3-104721.6" + wire width 2 $1\dec58_out_sel[1:0] + attribute \src "libresoc.v:104418.3-104433.6" + wire width 2 $1\dec58_rc_sel[1:0] + attribute \src "libresoc.v:104562.3-104577.6" + wire $1\dec58_rsrv[0:0] + attribute \src "libresoc.v:104626.3-104641.6" + wire $1\dec58_sgl_pipe[0:0] + attribute \src "libresoc.v:104594.3-104609.6" + wire $1\dec58_sgn[0:0] + attribute \src "libresoc.v:104530.3-104545.6" + wire $1\dec58_sgn_ext[0:0] + attribute \src "libresoc.v:104402.3-104417.6" + wire width 2 $1\dec58_upd[1:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 \dec31_dec_sub10_dec31_dec_sub10_asmcode + wire width 8 output 4 \dec58_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub10_dec31_dec_sub10_br + wire output 18 \dec58_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -19219,7 +163736,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub10_dec31_dec_sub10_cr_in + wire width 3 output 9 \dec58_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -19227,15 +163744,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub10_dec31_dec_sub10_cr_out + wire width 3 output 10 \dec58_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub10_dec31_dec_sub10_cry_in + wire width 2 output 14 \dec58_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub10_dec31_dec_sub10_cry_out + wire output 17 \dec58_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -19267,7 +163784,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 \dec31_dec_sub10_dec31_dec_sub10_form + wire width 5 output 3 \dec58_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -19282,7 +163799,7 @@ module \dec31 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec_sub10_dec31_dec_sub10_function_unit + wire width 12 output 1 \dec58_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -19290,7 +163807,7 @@ module \dec31 attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub10_dec31_dec_sub10_in1_sel + wire width 3 output 5 \dec58_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -19307,13 +163824,13 @@ module \dec31 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec_sub10_dec31_dec_sub10_in2_sel + wire width 4 output 6 \dec58_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub10_dec31_dec_sub10_in3_sel + wire width 2 output 7 \dec58_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -19389,13 +163906,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec31_dec_sub10_dec31_dec_sub10_internal_op + wire width 7 output 2 \dec58_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub10_dec31_dec_sub10_inv_a + wire output 15 \dec58_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub10_dec31_dec_sub10_inv_out + wire output 16 \dec58_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub10_dec31_dec_sub10_is_32b + wire output 21 \dec58_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" @@ -19403,43 +163920,904 @@ module \dec31 attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec_sub10_dec31_dec_sub10_ldst_len + wire width 4 output 11 \dec58_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub10_dec31_dec_sub10_lk + wire output 23 \dec58_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub10_dec31_dec_sub10_out_sel + wire width 2 output 8 \dec58_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub10_dec31_dec_sub10_rc_sel + wire width 2 output 13 \dec58_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub10_dec31_dec_sub10_rsrv + wire output 20 \dec58_rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe + wire output 24 \dec58_sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub10_dec31_dec_sub10_sgn + wire output 22 \dec58_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub10_dec31_dec_sub10_sgn_ext + wire output 19 \dec58_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub10_dec31_dec_sub10_upd + wire width 2 output 12 \dec58_upd + attribute \src "libresoc.v:104113.7-104113.15" + wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec31_dec_sub10_opcode_in + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 2 \opcode_switch + attribute \src "libresoc.v:104113.7-104113.20" + process $proc$libresoc.v:104113$4196 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:104370.3-104385.6" + process $proc$libresoc.v:104370$4172 + assign { } { } + assign { } { } + assign $0\dec58_function_unit[11:0] $1\dec58_function_unit[11:0] + attribute \src "libresoc.v:104371.5-104371.29" + switch \initial + attribute \src "libresoc.v:104371.9-104371.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_function_unit[11:0] 12'000000000100 + case + assign $1\dec58_function_unit[11:0] 12'000000000000 + end + sync always + update \dec58_function_unit $0\dec58_function_unit[11:0] + end + attribute \src "libresoc.v:104386.3-104401.6" + process $proc$libresoc.v:104386$4173 + assign { } { } + assign { } { } + assign $0\dec58_ldst_len[3:0] $1\dec58_ldst_len[3:0] + attribute \src "libresoc.v:104387.5-104387.29" + switch \initial + attribute \src "libresoc.v:104387.9-104387.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_ldst_len[3:0] 4'0100 + case + assign $1\dec58_ldst_len[3:0] 4'0000 + end + sync always + update \dec58_ldst_len $0\dec58_ldst_len[3:0] + end + attribute \src "libresoc.v:104402.3-104417.6" + process $proc$libresoc.v:104402$4174 + assign { } { } + assign { } { } + assign $0\dec58_upd[1:0] $1\dec58_upd[1:0] + attribute \src "libresoc.v:104403.5-104403.29" + switch \initial + attribute \src "libresoc.v:104403.9-104403.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_upd[1:0] 2'00 + case + assign $1\dec58_upd[1:0] 2'00 + end + sync always + update \dec58_upd $0\dec58_upd[1:0] + end + attribute \src "libresoc.v:104418.3-104433.6" + process $proc$libresoc.v:104418$4175 + assign { } { } + assign { } { } + assign $0\dec58_rc_sel[1:0] $1\dec58_rc_sel[1:0] + attribute \src "libresoc.v:104419.5-104419.29" + switch \initial + attribute \src "libresoc.v:104419.9-104419.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_rc_sel[1:0] 2'00 + case + assign $1\dec58_rc_sel[1:0] 2'00 + end + sync always + update \dec58_rc_sel $0\dec58_rc_sel[1:0] + end + attribute \src "libresoc.v:104434.3-104449.6" + process $proc$libresoc.v:104434$4176 + assign { } { } + assign { } { } + assign $0\dec58_cry_in[1:0] $1\dec58_cry_in[1:0] + attribute \src "libresoc.v:104435.5-104435.29" + switch \initial + attribute \src "libresoc.v:104435.9-104435.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_cry_in[1:0] 2'00 + case + assign $1\dec58_cry_in[1:0] 2'00 + end + sync always + update \dec58_cry_in $0\dec58_cry_in[1:0] + end + attribute \src "libresoc.v:104450.3-104465.6" + process $proc$libresoc.v:104450$4177 + assign { } { } + assign { } { } + assign $0\dec58_asmcode[7:0] $1\dec58_asmcode[7:0] + attribute \src "libresoc.v:104451.5-104451.29" + switch \initial + attribute \src "libresoc.v:104451.9-104451.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_asmcode[7:0] 8'01010010 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_asmcode[7:0] 8'01010101 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_asmcode[7:0] 8'01100010 + case + assign $1\dec58_asmcode[7:0] 8'00000000 + end + sync always + update \dec58_asmcode $0\dec58_asmcode[7:0] + end + attribute \src "libresoc.v:104466.3-104481.6" + process $proc$libresoc.v:104466$4178 + assign { } { } + assign { } { } + assign $0\dec58_inv_a[0:0] $1\dec58_inv_a[0:0] + attribute \src "libresoc.v:104467.5-104467.29" + switch \initial + attribute \src "libresoc.v:104467.9-104467.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_inv_a[0:0] 1'0 + case + assign $1\dec58_inv_a[0:0] 1'0 + end + sync always + update \dec58_inv_a $0\dec58_inv_a[0:0] + end + attribute \src "libresoc.v:104482.3-104497.6" + process $proc$libresoc.v:104482$4179 + assign { } { } + assign { } { } + assign $0\dec58_inv_out[0:0] $1\dec58_inv_out[0:0] + attribute \src "libresoc.v:104483.5-104483.29" + switch \initial + attribute \src "libresoc.v:104483.9-104483.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_inv_out[0:0] 1'0 + case + assign $1\dec58_inv_out[0:0] 1'0 + end + sync always + update \dec58_inv_out $0\dec58_inv_out[0:0] + end + attribute \src "libresoc.v:104498.3-104513.6" + process $proc$libresoc.v:104498$4180 + assign { } { } + assign { } { } + assign $0\dec58_cry_out[0:0] $1\dec58_cry_out[0:0] + attribute \src "libresoc.v:104499.5-104499.29" + switch \initial + attribute \src "libresoc.v:104499.9-104499.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_cry_out[0:0] 1'0 + case + assign $1\dec58_cry_out[0:0] 1'0 + end + sync always + update \dec58_cry_out $0\dec58_cry_out[0:0] + end + attribute \src "libresoc.v:104514.3-104529.6" + process $proc$libresoc.v:104514$4181 + assign { } { } + assign { } { } + assign $0\dec58_br[0:0] $1\dec58_br[0:0] + attribute \src "libresoc.v:104515.5-104515.29" + switch \initial + attribute \src "libresoc.v:104515.9-104515.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_br[0:0] 1'0 + case + assign $1\dec58_br[0:0] 1'0 + end + sync always + update \dec58_br $0\dec58_br[0:0] + end + attribute \src "libresoc.v:104530.3-104545.6" + process $proc$libresoc.v:104530$4182 + assign { } { } + assign { } { } + assign $0\dec58_sgn_ext[0:0] $1\dec58_sgn_ext[0:0] + attribute \src "libresoc.v:104531.5-104531.29" + switch \initial + attribute \src "libresoc.v:104531.9-104531.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sgn_ext[0:0] 1'1 + case + assign $1\dec58_sgn_ext[0:0] 1'0 + end + sync always + update \dec58_sgn_ext $0\dec58_sgn_ext[0:0] + end + attribute \src "libresoc.v:104546.3-104561.6" + process $proc$libresoc.v:104546$4183 + assign { } { } + assign { } { } + assign $0\dec58_internal_op[6:0] $1\dec58_internal_op[6:0] + attribute \src "libresoc.v:104547.5-104547.29" + switch \initial + attribute \src "libresoc.v:104547.9-104547.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_internal_op[6:0] 7'0100101 + case + assign $1\dec58_internal_op[6:0] 7'0000000 + end + sync always + update \dec58_internal_op $0\dec58_internal_op[6:0] + end + attribute \src "libresoc.v:104562.3-104577.6" + process $proc$libresoc.v:104562$4184 + assign { } { } + assign { } { } + assign $0\dec58_rsrv[0:0] $1\dec58_rsrv[0:0] + attribute \src "libresoc.v:104563.5-104563.29" + switch \initial + attribute \src "libresoc.v:104563.9-104563.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_rsrv[0:0] 1'0 + case + assign $1\dec58_rsrv[0:0] 1'0 + end + sync always + update \dec58_rsrv $0\dec58_rsrv[0:0] + end + attribute \src "libresoc.v:104578.3-104593.6" + process $proc$libresoc.v:104578$4185 + assign { } { } + assign { } { } + assign $0\dec58_is_32b[0:0] $1\dec58_is_32b[0:0] + attribute \src "libresoc.v:104579.5-104579.29" + switch \initial + attribute \src "libresoc.v:104579.9-104579.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_is_32b[0:0] 1'0 + case + assign $1\dec58_is_32b[0:0] 1'0 + end + sync always + update \dec58_is_32b $0\dec58_is_32b[0:0] + end + attribute \src "libresoc.v:104594.3-104609.6" + process $proc$libresoc.v:104594$4186 + assign { } { } + assign { } { } + assign $0\dec58_sgn[0:0] $1\dec58_sgn[0:0] + attribute \src "libresoc.v:104595.5-104595.29" + switch \initial + attribute \src "libresoc.v:104595.9-104595.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sgn[0:0] 1'0 + case + assign $1\dec58_sgn[0:0] 1'0 + end + sync always + update \dec58_sgn $0\dec58_sgn[0:0] + end + attribute \src "libresoc.v:104610.3-104625.6" + process $proc$libresoc.v:104610$4187 + assign { } { } + assign { } { } + assign $0\dec58_lk[0:0] $1\dec58_lk[0:0] + attribute \src "libresoc.v:104611.5-104611.29" + switch \initial + attribute \src "libresoc.v:104611.9-104611.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_lk[0:0] 1'0 + case + assign $1\dec58_lk[0:0] 1'0 + end + sync always + update \dec58_lk $0\dec58_lk[0:0] + end + attribute \src "libresoc.v:104626.3-104641.6" + process $proc$libresoc.v:104626$4188 + assign { } { } + assign { } { } + assign $0\dec58_sgl_pipe[0:0] $1\dec58_sgl_pipe[0:0] + attribute \src "libresoc.v:104627.5-104627.29" + switch \initial + attribute \src "libresoc.v:104627.9-104627.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sgl_pipe[0:0] 1'1 + case + assign $1\dec58_sgl_pipe[0:0] 1'0 + end + sync always + update \dec58_sgl_pipe $0\dec58_sgl_pipe[0:0] + end + attribute \src "libresoc.v:104642.3-104657.6" + process $proc$libresoc.v:104642$4189 + assign { } { } + assign { } { } + assign $0\dec58_form[4:0] $1\dec58_form[4:0] + attribute \src "libresoc.v:104643.5-104643.29" + switch \initial + attribute \src "libresoc.v:104643.9-104643.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_form[4:0] 5'00101 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_form[4:0] 5'00101 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_form[4:0] 5'00101 + case + assign $1\dec58_form[4:0] 5'00000 + end + sync always + update \dec58_form $0\dec58_form[4:0] + end + attribute \src "libresoc.v:104658.3-104673.6" + process $proc$libresoc.v:104658$4190 + assign { } { } + assign { } { } + assign $0\dec58_in1_sel[2:0] $1\dec58_in1_sel[2:0] + attribute \src "libresoc.v:104659.5-104659.29" + switch \initial + attribute \src "libresoc.v:104659.9-104659.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_in1_sel[2:0] 3'010 + case + assign $1\dec58_in1_sel[2:0] 3'000 + end + sync always + update \dec58_in1_sel $0\dec58_in1_sel[2:0] + end + attribute \src "libresoc.v:104674.3-104689.6" + process $proc$libresoc.v:104674$4191 + assign { } { } + assign { } { } + assign $0\dec58_in2_sel[3:0] $1\dec58_in2_sel[3:0] + attribute \src "libresoc.v:104675.5-104675.29" + switch \initial + attribute \src "libresoc.v:104675.9-104675.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_in2_sel[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_in2_sel[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_in2_sel[3:0] 4'1000 + case + assign $1\dec58_in2_sel[3:0] 4'0000 + end + sync always + update \dec58_in2_sel $0\dec58_in2_sel[3:0] + end + attribute \src "libresoc.v:104690.3-104705.6" + process $proc$libresoc.v:104690$4192 + assign { } { } + assign { } { } + assign $0\dec58_in3_sel[1:0] $1\dec58_in3_sel[1:0] + attribute \src "libresoc.v:104691.5-104691.29" + switch \initial + attribute \src "libresoc.v:104691.9-104691.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_in3_sel[1:0] 2'00 + case + assign $1\dec58_in3_sel[1:0] 2'00 + end + sync always + update \dec58_in3_sel $0\dec58_in3_sel[1:0] + end + attribute \src "libresoc.v:104706.3-104721.6" + process $proc$libresoc.v:104706$4193 + assign { } { } + assign { } { } + assign $0\dec58_out_sel[1:0] $1\dec58_out_sel[1:0] + attribute \src "libresoc.v:104707.5-104707.29" + switch \initial + attribute \src "libresoc.v:104707.9-104707.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_out_sel[1:0] 2'01 + case + assign $1\dec58_out_sel[1:0] 2'00 + end + sync always + update \dec58_out_sel $0\dec58_out_sel[1:0] + end + attribute \src "libresoc.v:104722.3-104737.6" + process $proc$libresoc.v:104722$4194 + assign { } { } + assign { } { } + assign $0\dec58_cr_in[2:0] $1\dec58_cr_in[2:0] + attribute \src "libresoc.v:104723.5-104723.29" + switch \initial + attribute \src "libresoc.v:104723.9-104723.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_cr_in[2:0] 3'000 + case + assign $1\dec58_cr_in[2:0] 3'000 + end + sync always + update \dec58_cr_in $0\dec58_cr_in[2:0] + end + attribute \src "libresoc.v:104738.3-104753.6" + process $proc$libresoc.v:104738$4195 + assign { } { } + assign { } { } + assign $0\dec58_cr_out[2:0] $1\dec58_cr_out[2:0] + attribute \src "libresoc.v:104739.5-104739.29" + switch \initial + attribute \src "libresoc.v:104739.9-104739.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_cr_out[2:0] 3'000 + case + assign $1\dec58_cr_out[2:0] 3'000 + end + sync always + update \dec58_cr_out $0\dec58_cr_out[2:0] + end + connect \opcode_switch \opcode_in [1:0] +end +attribute \src "libresoc.v:104759.1-105330.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec62" +attribute \generator "nMigen" +module \dec62 + attribute \src "libresoc.v:105082.3-105094.6" + wire width 8 $0\dec62_asmcode[7:0] + attribute \src "libresoc.v:105134.3-105146.6" + wire $0\dec62_br[0:0] + attribute \src "libresoc.v:105303.3-105315.6" + wire width 3 $0\dec62_cr_in[2:0] + attribute \src "libresoc.v:105316.3-105328.6" + wire width 3 $0\dec62_cr_out[2:0] + attribute \src "libresoc.v:105069.3-105081.6" + wire width 2 $0\dec62_cry_in[1:0] + attribute \src "libresoc.v:105121.3-105133.6" + wire $0\dec62_cry_out[0:0] + attribute \src "libresoc.v:105238.3-105250.6" + wire width 5 $0\dec62_form[4:0] + attribute \src "libresoc.v:105017.3-105029.6" + wire width 12 $0\dec62_function_unit[11:0] + attribute \src "libresoc.v:105251.3-105263.6" + wire width 3 $0\dec62_in1_sel[2:0] + attribute \src "libresoc.v:105264.3-105276.6" + wire width 4 $0\dec62_in2_sel[3:0] + attribute \src "libresoc.v:105277.3-105289.6" + wire width 2 $0\dec62_in3_sel[1:0] + attribute \src "libresoc.v:105160.3-105172.6" + wire width 7 $0\dec62_internal_op[6:0] + attribute \src "libresoc.v:105095.3-105107.6" + wire $0\dec62_inv_a[0:0] + attribute \src "libresoc.v:105108.3-105120.6" + wire $0\dec62_inv_out[0:0] + attribute \src "libresoc.v:105186.3-105198.6" + wire $0\dec62_is_32b[0:0] + attribute \src "libresoc.v:105030.3-105042.6" + wire width 4 $0\dec62_ldst_len[3:0] + attribute \src "libresoc.v:105212.3-105224.6" + wire $0\dec62_lk[0:0] + attribute \src "libresoc.v:105290.3-105302.6" + wire width 2 $0\dec62_out_sel[1:0] + attribute \src "libresoc.v:105056.3-105068.6" + wire width 2 $0\dec62_rc_sel[1:0] + attribute \src "libresoc.v:105173.3-105185.6" + wire $0\dec62_rsrv[0:0] + attribute \src "libresoc.v:105225.3-105237.6" + wire $0\dec62_sgl_pipe[0:0] + attribute \src "libresoc.v:105199.3-105211.6" + wire $0\dec62_sgn[0:0] + attribute \src "libresoc.v:105147.3-105159.6" + wire $0\dec62_sgn_ext[0:0] + attribute \src "libresoc.v:105043.3-105055.6" + wire width 2 $0\dec62_upd[1:0] + attribute \src "libresoc.v:104760.7-104760.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:105082.3-105094.6" + wire width 8 $1\dec62_asmcode[7:0] + attribute \src "libresoc.v:105134.3-105146.6" + wire $1\dec62_br[0:0] + attribute \src "libresoc.v:105303.3-105315.6" + wire width 3 $1\dec62_cr_in[2:0] + attribute \src "libresoc.v:105316.3-105328.6" + wire width 3 $1\dec62_cr_out[2:0] + attribute \src "libresoc.v:105069.3-105081.6" + wire width 2 $1\dec62_cry_in[1:0] + attribute \src "libresoc.v:105121.3-105133.6" + wire $1\dec62_cry_out[0:0] + attribute \src "libresoc.v:105238.3-105250.6" + wire width 5 $1\dec62_form[4:0] + attribute \src "libresoc.v:105017.3-105029.6" + wire width 12 $1\dec62_function_unit[11:0] + attribute \src "libresoc.v:105251.3-105263.6" + wire width 3 $1\dec62_in1_sel[2:0] + attribute \src "libresoc.v:105264.3-105276.6" + wire width 4 $1\dec62_in2_sel[3:0] + attribute \src "libresoc.v:105277.3-105289.6" + wire width 2 $1\dec62_in3_sel[1:0] + attribute \src "libresoc.v:105160.3-105172.6" + wire width 7 $1\dec62_internal_op[6:0] + attribute \src "libresoc.v:105095.3-105107.6" + wire $1\dec62_inv_a[0:0] + attribute \src "libresoc.v:105108.3-105120.6" + wire $1\dec62_inv_out[0:0] + attribute \src "libresoc.v:105186.3-105198.6" + wire $1\dec62_is_32b[0:0] + attribute \src "libresoc.v:105030.3-105042.6" + wire width 4 $1\dec62_ldst_len[3:0] + attribute \src "libresoc.v:105212.3-105224.6" + wire $1\dec62_lk[0:0] + attribute \src "libresoc.v:105290.3-105302.6" + wire width 2 $1\dec62_out_sel[1:0] + attribute \src "libresoc.v:105056.3-105068.6" + wire width 2 $1\dec62_rc_sel[1:0] + attribute \src "libresoc.v:105173.3-105185.6" + wire $1\dec62_rsrv[0:0] + attribute \src "libresoc.v:105225.3-105237.6" + wire $1\dec62_sgl_pipe[0:0] + attribute \src "libresoc.v:105199.3-105211.6" + wire $1\dec62_sgn[0:0] + attribute \src "libresoc.v:105147.3-105159.6" + wire $1\dec62_sgn_ext[0:0] + attribute \src "libresoc.v:105043.3-105055.6" + wire width 2 $1\dec62_upd[1:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 \dec31_dec_sub11_dec31_dec_sub11_asmcode + wire width 8 output 4 \dec62_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub11_dec31_dec_sub11_br + wire output 18 \dec62_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -19449,7 +164827,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub11_dec31_dec_sub11_cr_in + wire width 3 output 9 \dec62_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -19457,15 +164835,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub11_dec31_dec_sub11_cr_out + wire width 3 output 10 \dec62_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub11_dec31_dec_sub11_cry_in + wire width 2 output 14 \dec62_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub11_dec31_dec_sub11_cry_out + wire output 17 \dec62_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -19497,7 +164875,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 \dec31_dec_sub11_dec31_dec_sub11_form + wire width 5 output 3 \dec62_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -19512,7 +164890,7 @@ module \dec31 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec_sub11_dec31_dec_sub11_function_unit + wire width 12 output 1 \dec62_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -19520,7 +164898,7 @@ module \dec31 attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub11_dec31_dec_sub11_in1_sel + wire width 3 output 5 \dec62_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -19537,13 +164915,13 @@ module \dec31 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec_sub11_dec31_dec_sub11_in2_sel + wire width 4 output 6 \dec62_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub11_dec31_dec_sub11_in3_sel + wire width 2 output 7 \dec62_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -19619,13 +164997,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec31_dec_sub11_dec31_dec_sub11_internal_op + wire width 7 output 2 \dec62_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub11_dec31_dec_sub11_inv_a + wire output 15 \dec62_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub11_dec31_dec_sub11_inv_out + wire output 16 \dec62_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub11_dec31_dec_sub11_is_32b + wire output 21 \dec62_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" @@ -19633,101 +165011,708 @@ module \dec31 attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec_sub11_dec31_dec_sub11_ldst_len + wire width 4 output 11 \dec62_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub11_dec31_dec_sub11_lk + wire output 23 \dec62_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub11_dec31_dec_sub11_out_sel + wire width 2 output 8 \dec62_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub11_dec31_dec_sub11_rc_sel + wire width 2 output 13 \dec62_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub11_dec31_dec_sub11_rsrv + wire output 20 \dec62_rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe + wire output 24 \dec62_sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub11_dec31_dec_sub11_sgn + wire output 22 \dec62_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub11_dec31_dec_sub11_sgn_ext + wire output 19 \dec62_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub11_dec31_dec_sub11_upd + wire width 2 output 12 \dec62_upd + attribute \src "libresoc.v:104760.7-104760.15" + wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec31_dec_sub11_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 \dec31_dec_sub15_dec31_dec_sub15_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub15_dec31_dec_sub15_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub15_dec31_dec_sub15_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub15_dec31_dec_sub15_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub15_dec31_dec_sub15_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub15_dec31_dec_sub15_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 \dec31_dec_sub15_dec31_dec_sub15_form + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 2 \opcode_switch + attribute \src "libresoc.v:104760.7-104760.20" + process $proc$libresoc.v:104760$4221 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:105017.3-105029.6" + process $proc$libresoc.v:105017$4197 + assign { } { } + assign { } { } + assign $0\dec62_function_unit[11:0] $1\dec62_function_unit[11:0] + attribute \src "libresoc.v:105018.5-105018.29" + switch \initial + attribute \src "libresoc.v:105018.9-105018.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_function_unit[11:0] 12'000000000100 + case + assign $1\dec62_function_unit[11:0] 12'000000000000 + end + sync always + update \dec62_function_unit $0\dec62_function_unit[11:0] + end + attribute \src "libresoc.v:105030.3-105042.6" + process $proc$libresoc.v:105030$4198 + assign { } { } + assign { } { } + assign $0\dec62_ldst_len[3:0] $1\dec62_ldst_len[3:0] + attribute \src "libresoc.v:105031.5-105031.29" + switch \initial + attribute \src "libresoc.v:105031.9-105031.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_ldst_len[3:0] 4'1000 + case + assign $1\dec62_ldst_len[3:0] 4'0000 + end + sync always + update \dec62_ldst_len $0\dec62_ldst_len[3:0] + end + attribute \src "libresoc.v:105043.3-105055.6" + process $proc$libresoc.v:105043$4199 + assign { } { } + assign { } { } + assign $0\dec62_upd[1:0] $1\dec62_upd[1:0] + attribute \src "libresoc.v:105044.5-105044.29" + switch \initial + attribute \src "libresoc.v:105044.9-105044.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_upd[1:0] 2'01 + case + assign $1\dec62_upd[1:0] 2'00 + end + sync always + update \dec62_upd $0\dec62_upd[1:0] + end + attribute \src "libresoc.v:105056.3-105068.6" + process $proc$libresoc.v:105056$4200 + assign { } { } + assign { } { } + assign $0\dec62_rc_sel[1:0] $1\dec62_rc_sel[1:0] + attribute \src "libresoc.v:105057.5-105057.29" + switch \initial + attribute \src "libresoc.v:105057.9-105057.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_rc_sel[1:0] 2'00 + case + assign $1\dec62_rc_sel[1:0] 2'00 + end + sync always + update \dec62_rc_sel $0\dec62_rc_sel[1:0] + end + attribute \src "libresoc.v:105069.3-105081.6" + process $proc$libresoc.v:105069$4201 + assign { } { } + assign { } { } + assign $0\dec62_cry_in[1:0] $1\dec62_cry_in[1:0] + attribute \src "libresoc.v:105070.5-105070.29" + switch \initial + attribute \src "libresoc.v:105070.9-105070.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_cry_in[1:0] 2'00 + case + assign $1\dec62_cry_in[1:0] 2'00 + end + sync always + update \dec62_cry_in $0\dec62_cry_in[1:0] + end + attribute \src "libresoc.v:105082.3-105094.6" + process $proc$libresoc.v:105082$4202 + assign { } { } + assign { } { } + assign $0\dec62_asmcode[7:0] $1\dec62_asmcode[7:0] + attribute \src "libresoc.v:105083.5-105083.29" + switch \initial + attribute \src "libresoc.v:105083.9-105083.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_asmcode[7:0] 8'10101100 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_asmcode[7:0] 8'10101111 + case + assign $1\dec62_asmcode[7:0] 8'00000000 + end + sync always + update \dec62_asmcode $0\dec62_asmcode[7:0] + end + attribute \src "libresoc.v:105095.3-105107.6" + process $proc$libresoc.v:105095$4203 + assign { } { } + assign { } { } + assign $0\dec62_inv_a[0:0] $1\dec62_inv_a[0:0] + attribute \src "libresoc.v:105096.5-105096.29" + switch \initial + attribute \src "libresoc.v:105096.9-105096.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_inv_a[0:0] 1'0 + case + assign $1\dec62_inv_a[0:0] 1'0 + end + sync always + update \dec62_inv_a $0\dec62_inv_a[0:0] + end + attribute \src "libresoc.v:105108.3-105120.6" + process $proc$libresoc.v:105108$4204 + assign { } { } + assign { } { } + assign $0\dec62_inv_out[0:0] $1\dec62_inv_out[0:0] + attribute \src "libresoc.v:105109.5-105109.29" + switch \initial + attribute \src "libresoc.v:105109.9-105109.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_inv_out[0:0] 1'0 + case + assign $1\dec62_inv_out[0:0] 1'0 + end + sync always + update \dec62_inv_out $0\dec62_inv_out[0:0] + end + attribute \src "libresoc.v:105121.3-105133.6" + process $proc$libresoc.v:105121$4205 + assign { } { } + assign { } { } + assign $0\dec62_cry_out[0:0] $1\dec62_cry_out[0:0] + attribute \src "libresoc.v:105122.5-105122.29" + switch \initial + attribute \src "libresoc.v:105122.9-105122.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_cry_out[0:0] 1'0 + case + assign $1\dec62_cry_out[0:0] 1'0 + end + sync always + update \dec62_cry_out $0\dec62_cry_out[0:0] + end + attribute \src "libresoc.v:105134.3-105146.6" + process $proc$libresoc.v:105134$4206 + assign { } { } + assign { } { } + assign $0\dec62_br[0:0] $1\dec62_br[0:0] + attribute \src "libresoc.v:105135.5-105135.29" + switch \initial + attribute \src "libresoc.v:105135.9-105135.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_br[0:0] 1'0 + case + assign $1\dec62_br[0:0] 1'0 + end + sync always + update \dec62_br $0\dec62_br[0:0] + end + attribute \src "libresoc.v:105147.3-105159.6" + process $proc$libresoc.v:105147$4207 + assign { } { } + assign { } { } + assign $0\dec62_sgn_ext[0:0] $1\dec62_sgn_ext[0:0] + attribute \src "libresoc.v:105148.5-105148.29" + switch \initial + attribute \src "libresoc.v:105148.9-105148.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sgn_ext[0:0] 1'0 + case + assign $1\dec62_sgn_ext[0:0] 1'0 + end + sync always + update \dec62_sgn_ext $0\dec62_sgn_ext[0:0] + end + attribute \src "libresoc.v:105160.3-105172.6" + process $proc$libresoc.v:105160$4208 + assign { } { } + assign { } { } + assign $0\dec62_internal_op[6:0] $1\dec62_internal_op[6:0] + attribute \src "libresoc.v:105161.5-105161.29" + switch \initial + attribute \src "libresoc.v:105161.9-105161.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_internal_op[6:0] 7'0100110 + case + assign $1\dec62_internal_op[6:0] 7'0000000 + end + sync always + update \dec62_internal_op $0\dec62_internal_op[6:0] + end + attribute \src "libresoc.v:105173.3-105185.6" + process $proc$libresoc.v:105173$4209 + assign { } { } + assign { } { } + assign $0\dec62_rsrv[0:0] $1\dec62_rsrv[0:0] + attribute \src "libresoc.v:105174.5-105174.29" + switch \initial + attribute \src "libresoc.v:105174.9-105174.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_rsrv[0:0] 1'0 + case + assign $1\dec62_rsrv[0:0] 1'0 + end + sync always + update \dec62_rsrv $0\dec62_rsrv[0:0] + end + attribute \src "libresoc.v:105186.3-105198.6" + process $proc$libresoc.v:105186$4210 + assign { } { } + assign { } { } + assign $0\dec62_is_32b[0:0] $1\dec62_is_32b[0:0] + attribute \src "libresoc.v:105187.5-105187.29" + switch \initial + attribute \src "libresoc.v:105187.9-105187.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_is_32b[0:0] 1'0 + case + assign $1\dec62_is_32b[0:0] 1'0 + end + sync always + update \dec62_is_32b $0\dec62_is_32b[0:0] + end + attribute \src "libresoc.v:105199.3-105211.6" + process $proc$libresoc.v:105199$4211 + assign { } { } + assign { } { } + assign $0\dec62_sgn[0:0] $1\dec62_sgn[0:0] + attribute \src "libresoc.v:105200.5-105200.29" + switch \initial + attribute \src "libresoc.v:105200.9-105200.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sgn[0:0] 1'0 + case + assign $1\dec62_sgn[0:0] 1'0 + end + sync always + update \dec62_sgn $0\dec62_sgn[0:0] + end + attribute \src "libresoc.v:105212.3-105224.6" + process $proc$libresoc.v:105212$4212 + assign { } { } + assign { } { } + assign $0\dec62_lk[0:0] $1\dec62_lk[0:0] + attribute \src "libresoc.v:105213.5-105213.29" + switch \initial + attribute \src "libresoc.v:105213.9-105213.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_lk[0:0] 1'0 + case + assign $1\dec62_lk[0:0] 1'0 + end + sync always + update \dec62_lk $0\dec62_lk[0:0] + end + attribute \src "libresoc.v:105225.3-105237.6" + process $proc$libresoc.v:105225$4213 + assign { } { } + assign { } { } + assign $0\dec62_sgl_pipe[0:0] $1\dec62_sgl_pipe[0:0] + attribute \src "libresoc.v:105226.5-105226.29" + switch \initial + attribute \src "libresoc.v:105226.9-105226.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sgl_pipe[0:0] 1'1 + case + assign $1\dec62_sgl_pipe[0:0] 1'0 + end + sync always + update \dec62_sgl_pipe $0\dec62_sgl_pipe[0:0] + end + attribute \src "libresoc.v:105238.3-105250.6" + process $proc$libresoc.v:105238$4214 + assign { } { } + assign { } { } + assign $0\dec62_form[4:0] $1\dec62_form[4:0] + attribute \src "libresoc.v:105239.5-105239.29" + switch \initial + attribute \src "libresoc.v:105239.9-105239.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_form[4:0] 5'00101 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_form[4:0] 5'00101 + case + assign $1\dec62_form[4:0] 5'00000 + end + sync always + update \dec62_form $0\dec62_form[4:0] + end + attribute \src "libresoc.v:105251.3-105263.6" + process $proc$libresoc.v:105251$4215 + assign { } { } + assign { } { } + assign $0\dec62_in1_sel[2:0] $1\dec62_in1_sel[2:0] + attribute \src "libresoc.v:105252.5-105252.29" + switch \initial + attribute \src "libresoc.v:105252.9-105252.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_in1_sel[2:0] 3'010 + case + assign $1\dec62_in1_sel[2:0] 3'000 + end + sync always + update \dec62_in1_sel $0\dec62_in1_sel[2:0] + end + attribute \src "libresoc.v:105264.3-105276.6" + process $proc$libresoc.v:105264$4216 + assign { } { } + assign { } { } + assign $0\dec62_in2_sel[3:0] $1\dec62_in2_sel[3:0] + attribute \src "libresoc.v:105265.5-105265.29" + switch \initial + attribute \src "libresoc.v:105265.9-105265.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_in2_sel[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_in2_sel[3:0] 4'1000 + case + assign $1\dec62_in2_sel[3:0] 4'0000 + end + sync always + update \dec62_in2_sel $0\dec62_in2_sel[3:0] + end + attribute \src "libresoc.v:105277.3-105289.6" + process $proc$libresoc.v:105277$4217 + assign { } { } + assign { } { } + assign $0\dec62_in3_sel[1:0] $1\dec62_in3_sel[1:0] + attribute \src "libresoc.v:105278.5-105278.29" + switch \initial + attribute \src "libresoc.v:105278.9-105278.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_in3_sel[1:0] 2'01 + case + assign $1\dec62_in3_sel[1:0] 2'00 + end + sync always + update \dec62_in3_sel $0\dec62_in3_sel[1:0] + end + attribute \src "libresoc.v:105290.3-105302.6" + process $proc$libresoc.v:105290$4218 + assign { } { } + assign { } { } + assign $0\dec62_out_sel[1:0] $1\dec62_out_sel[1:0] + attribute \src "libresoc.v:105291.5-105291.29" + switch \initial + attribute \src "libresoc.v:105291.9-105291.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_out_sel[1:0] 2'00 + case + assign $1\dec62_out_sel[1:0] 2'00 + end + sync always + update \dec62_out_sel $0\dec62_out_sel[1:0] + end + attribute \src "libresoc.v:105303.3-105315.6" + process $proc$libresoc.v:105303$4219 + assign { } { } + assign { } { } + assign $0\dec62_cr_in[2:0] $1\dec62_cr_in[2:0] + attribute \src "libresoc.v:105304.5-105304.29" + switch \initial + attribute \src "libresoc.v:105304.9-105304.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_cr_in[2:0] 3'000 + case + assign $1\dec62_cr_in[2:0] 3'000 + end + sync always + update \dec62_cr_in $0\dec62_cr_in[2:0] + end + attribute \src "libresoc.v:105316.3-105328.6" + process $proc$libresoc.v:105316$4220 + assign { } { } + assign { } { } + assign $0\dec62_cr_out[2:0] $1\dec62_cr_out[2:0] + attribute \src "libresoc.v:105317.5-105317.29" + switch \initial + attribute \src "libresoc.v:105317.9-105317.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_cr_out[2:0] 3'000 + case + assign $1\dec62_cr_out[2:0] 3'000 + end + sync always + update \dec62_cr_out $0\dec62_cr_out[2:0] + end + connect \opcode_switch \opcode_in [1:0] +end +attribute \src "libresoc.v:105334.1-105867.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU" +attribute \generator "nMigen" +module \dec_ALU + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 18 \ALU__data_len attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -19741,39 +165726,20 @@ module \dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec_sub15_dec31_dec_sub15_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub15_dec31_dec_sub15_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec_sub15_dec31_dec_sub15_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub15_dec31_dec_sub15_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 3 \ALU__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 4 \ALU__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 5 \ALU__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 14 \ALU__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 19 \ALU__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -19848,116 +165814,88 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \ALU__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \ALU__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \ALU__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \ALU__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \ALU__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \ALU__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \ALU__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \ALU__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 7 \ALU__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \ALU__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \ALU__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \ALU__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_ALU_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_ALU_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_ALU_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 \dec_ALU_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_ALU_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_ALU_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 \dec_ALU_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 \dec_ALU_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 24 \dec_ALU_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \dec_ALU_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_ALU_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \dec_ALU_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_ALU_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 \dec_ALU_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 \dec_ALU_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec31_dec_sub15_dec31_dec_sub15_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub15_dec31_dec_sub15_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub15_dec31_dec_sub15_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub15_dec31_dec_sub15_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec_sub15_dec31_dec_sub15_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub15_dec31_dec_sub15_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub15_dec31_dec_sub15_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub15_dec31_dec_sub15_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub15_dec31_dec_sub15_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub15_dec31_dec_sub15_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub15_dec31_dec_sub15_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub15_dec31_dec_sub15_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec31_dec_sub15_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 \dec31_dec_sub16_dec31_dec_sub16_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub16_dec31_dec_sub16_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub16_dec31_dec_sub16_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub16_dec31_dec_sub16_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub16_dec31_dec_sub16_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub16_dec31_dec_sub16_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 \dec31_dec_sub16_dec31_dec_sub16_form + wire width 3 \dec_ALU_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \dec_ALU_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec_ALU_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec_ALU_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -19972,7 +165910,7 @@ module \dec31 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec_sub16_dec31_dec_sub16_function_unit + wire width 12 \dec_ALU_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -19980,7 +165918,7 @@ module \dec31 attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub16_dec31_dec_sub16_in1_sel + wire width 3 \dec_ALU_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -19997,13 +165935,7 @@ module \dec31 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec_sub16_dec31_dec_sub16_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub16_dec31_dec_sub16_in3_sel + wire width 4 \dec_ALU_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -20079,13 +166011,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec31_dec_sub16_dec31_dec_sub16_internal_op + wire width 7 \dec_ALU_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub16_dec31_dec_sub16_inv_a + wire \dec_ALU_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub16_dec31_dec_sub16_inv_out + wire \dec_ALU_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub16_dec31_dec_sub16_is_32b + wire \dec_ALU_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" @@ -20093,43 +166025,56 @@ module \dec31 attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec_sub16_dec31_dec_sub16_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub16_dec31_dec_sub16_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub16_dec31_dec_sub16_out_sel + wire width 4 \dec_ALU_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub16_dec31_dec_sub16_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub16_dec31_dec_sub16_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub16_dec31_dec_sub16_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub16_dec31_dec_sub16_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub16_dec31_dec_sub16_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec31_dec_sub16_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 \dec31_dec_sub18_dec31_dec_sub18_asmcode + wire width 2 \dec_ALU_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub18_dec31_dec_sub18_br + wire \dec_ALU_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 6 \dec_ALU_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + wire \dec_ai_immz_out + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" + wire width 3 \dec_ai_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" + wire width 32 \dec_cr_in_insn_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -20138,56 +166083,194 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub18_dec31_dec_sub18_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" + wire width 3 \dec_cr_in_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_cr_out_cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" + wire \dec_cr_out_rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub18_dec31_dec_sub18_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" + wire width 3 \dec_cr_out_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub18_dec31_dec_sub18_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub18_dec31_dec_sub18_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 \dec31_dec_sub18_dec31_dec_sub18_form + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + wire width 2 \dec_rc_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + wire width 32 input 20 \raw_opcode_in + attribute \module_not_derived 1 + attribute \src "libresoc.v:105751.7-105788.4" + cell \dec \dec + connect \ALU_BA \dec_ALU_BA + connect \ALU_BB \dec_ALU_BB + connect \ALU_BC \dec_ALU_BC + connect \ALU_BD \dec_ALU_BD + connect \ALU_BI \dec_ALU_BI + connect \ALU_BT \dec_ALU_BT + connect \ALU_DS \dec_ALU_DS + connect \ALU_FXM \dec_ALU_FXM + connect \ALU_LI \dec_ALU_LI + connect \ALU_OE \dec_ALU_OE + connect \ALU_RA \dec_ALU_RA + connect \ALU_Rc \dec_ALU_Rc + connect \ALU_SH32 \dec_ALU_SH32 + connect \ALU_SI \dec_ALU_SI + connect \ALU_UI \dec_ALU_UI + connect \ALU_cr_in \dec_ALU_cr_in + connect \ALU_cr_out \dec_ALU_cr_out + connect \ALU_cry_in \dec_ALU_cry_in + connect \ALU_cry_out \dec_ALU_cry_out + connect \ALU_function_unit \dec_ALU_function_unit + connect \ALU_in1_sel \dec_ALU_in1_sel + connect \ALU_in2_sel \dec_ALU_in2_sel + connect \ALU_internal_op \dec_ALU_internal_op + connect \ALU_inv_a \dec_ALU_inv_a + connect \ALU_inv_out \dec_ALU_inv_out + connect \ALU_is_32b \dec_ALU_is_32b + connect \ALU_ldst_len \dec_ALU_ldst_len + connect \ALU_rc_sel \dec_ALU_rc_sel + connect \ALU_sgn \dec_ALU_sgn + connect \ALU_sh \dec_ALU_sh + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:105789.10-105793.4" + cell \dec_ai \dec_ai + connect \ALU_RA \dec_ALU_RA + connect \immz_out \dec_ai_immz_out + connect \sel_in \dec_ai_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:105794.10-105805.4" + cell \dec_bi \dec_bi + connect \ALU_BD \dec_ALU_BD + connect \ALU_DS \dec_ALU_DS + connect \ALU_LI \dec_ALU_LI + connect \ALU_SH32 \dec_ALU_SH32 + connect \ALU_SI \dec_ALU_SI + connect \ALU_UI \dec_ALU_UI + connect \ALU_sh \dec_ALU_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:105806.13-105817.4" + cell \dec_cr_in \dec_cr_in + connect \ALU_BA \dec_ALU_BA + connect \ALU_BB \dec_ALU_BB + connect \ALU_BC \dec_ALU_BC + connect \ALU_BI \dec_ALU_BI + connect \ALU_BT \dec_ALU_BT + connect \ALU_FXM \dec_ALU_FXM + connect \ALU_internal_op \dec_ALU_internal_op + connect \X_BFA \dec_X_BFA + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:105818.14-105827.4" + cell \dec_cr_out \dec_cr_out + connect \ALU_FXM \dec_ALU_FXM + connect \ALU_internal_op \dec_ALU_internal_op + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok + connect \insn_in \dec_cr_out_insn_in + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:105828.10-105834.4" + cell \dec_oe \dec_oe + connect \ALU_OE \dec_ALU_OE + connect \ALU_internal_op \dec_ALU_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:105835.10-105840.4" + cell \dec_rc \dec_rc + connect \ALU_Rc \dec_ALU_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + connect \ALU__is_signed \dec_ALU_sgn + connect \ALU__is_32bit \dec_ALU_is_32b + connect \ALU__output_carry \dec_ALU_cry_out + connect \ALU__input_carry \dec_ALU_cry_in + connect \ALU__invert_out \dec_ALU_inv_out + connect \ALU__invert_in \dec_ALU_inv_a + connect \ALU__data_len \dec_ALU_ldst_len + connect \ALU__write_cr0 \dec_cr_out_cr_bitfield_ok + connect { \ALU__oe__ok \ALU__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \ALU__rc__ok \ALU__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \ALU__imm_data__ok \ALU__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_ALU_in2_sel + connect \ALU__zero_a \dec_ai_immz_out + connect \dec_ai_sel_in \dec_ALU_in1_sel + connect \ALU__fn_unit \dec_ALU_function_unit + connect \ALU__insn_type \dec_ALU_internal_op + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_ALU_cr_out + connect \dec_cr_in_sel_in \dec_ALU_cr_in + connect \dec_oe_sel_in \dec_ALU_rc_sel + connect \dec_rc_sel_in \dec_ALU_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \ALU__insn \dec_opcode_in +end +attribute \src "libresoc.v:105871.1-106323.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH" +attribute \generator "nMigen" +module \dec_BRANCH + attribute \src "libresoc.v:106297.3-106306.6" + wire $0\BRANCH__lk[0:0] + attribute \src "libresoc.v:105872.7-105872.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:106297.3-106306.6" + wire $1\BRANCH__lk[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 3 \BRANCH__cia attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -20201,39 +166284,14 @@ module \dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec_sub18_dec31_dec_sub18_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub18_dec31_dec_sub18_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec_sub18_dec31_dec_sub18_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub18_dec31_dec_sub18_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 5 \BRANCH__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \BRANCH__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \BRANCH__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 6 \BRANCH__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -20308,58 +166366,46 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec31_dec_sub18_dec31_dec_sub18_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub18_dec31_dec_sub18_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub18_dec31_dec_sub18_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub18_dec31_dec_sub18_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec_sub18_dec31_dec_sub18_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub18_dec31_dec_sub18_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub18_dec31_dec_sub18_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub18_dec31_dec_sub18_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub18_dec31_dec_sub18_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub18_dec31_dec_sub18_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub18_dec31_dec_sub18_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub18_dec31_dec_sub18_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec31_dec_sub18_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 \dec31_dec_sub19_dec31_dec_sub19_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub19_dec31_dec_sub19_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 4 \BRANCH__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \BRANCH__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \BRANCH__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + wire input 2 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + wire width 64 input 11 \core_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_BRANCH_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_BRANCH_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_BRANCH_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 \dec_BRANCH_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_BRANCH_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_BRANCH_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 \dec_BRANCH_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 \dec_BRANCH_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 24 \dec_BRANCH_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \dec_BRANCH_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \dec_BRANCH_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \dec_BRANCH_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_BRANCH_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 \dec_BRANCH_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 \dec_BRANCH_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -20369,7 +166415,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub19_dec31_dec_sub19_cr_in + wire width 3 \dec_BRANCH_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -20377,47 +166423,7 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub19_dec31_dec_sub19_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub19_dec31_dec_sub19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub19_dec31_dec_sub19_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 \dec31_dec_sub19_dec31_dec_sub19_form + wire width 3 \dec_BRANCH_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -20432,15 +166438,7 @@ module \dec31 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec_sub19_dec31_dec_sub19_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub19_dec31_dec_sub19_in1_sel + wire width 12 \dec_BRANCH_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -20457,13 +166455,7 @@ module \dec31 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec_sub19_dec31_dec_sub19_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub19_dec31_dec_sub19_in3_sel + wire width 4 \dec_BRANCH_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -20539,57 +166531,48 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec31_dec_sub19_dec31_dec_sub19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub19_dec31_dec_sub19_inv_a + wire width 7 \dec_BRANCH_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub19_dec31_dec_sub19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub19_dec31_dec_sub19_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec_sub19_dec31_dec_sub19_ldst_len + wire \dec_BRANCH_is_32b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub19_dec31_dec_sub19_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub19_dec31_dec_sub19_out_sel + wire \dec_BRANCH_lk attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub19_dec31_dec_sub19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub19_dec31_dec_sub19_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub19_dec31_dec_sub19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub19_dec31_dec_sub19_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub19_dec31_dec_sub19_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec31_dec_sub19_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 \dec31_dec_sub20_dec31_dec_sub20_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub20_dec31_dec_sub20_br + wire width 2 \dec_BRANCH_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 6 \dec_BRANCH_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" + wire width 32 \dec_cr_in_insn_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -20598,56 +166581,184 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub20_dec31_dec_sub20_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" + wire width 3 \dec_cr_in_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" + wire \dec_cr_out_rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub20_dec31_dec_sub20_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" + wire width 3 \dec_cr_out_sel_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub20_dec31_dec_sub20_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub20_dec31_dec_sub20_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 \dec31_dec_sub20_dec31_dec_sub20_form + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + wire width 2 \dec_rc_sel_in + attribute \src "libresoc.v:105872.7-105872.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + wire width 32 input 1 \raw_opcode_in + attribute \module_not_derived 1 + attribute \src "libresoc.v:106222.13-106253.4" + cell \dec$147 \dec + connect \BRANCH_BA \dec_BRANCH_BA + connect \BRANCH_BB \dec_BRANCH_BB + connect \BRANCH_BC \dec_BRANCH_BC + connect \BRANCH_BD \dec_BRANCH_BD + connect \BRANCH_BI \dec_BRANCH_BI + connect \BRANCH_BT \dec_BRANCH_BT + connect \BRANCH_DS \dec_BRANCH_DS + connect \BRANCH_FXM \dec_BRANCH_FXM + connect \BRANCH_LI \dec_BRANCH_LI + connect \BRANCH_LK \dec_BRANCH_LK + connect \BRANCH_OE \dec_BRANCH_OE + connect \BRANCH_Rc \dec_BRANCH_Rc + connect \BRANCH_SH32 \dec_BRANCH_SH32 + connect \BRANCH_SI \dec_BRANCH_SI + connect \BRANCH_UI \dec_BRANCH_UI + connect \BRANCH_cr_in \dec_BRANCH_cr_in + connect \BRANCH_cr_out \dec_BRANCH_cr_out + connect \BRANCH_function_unit \dec_BRANCH_function_unit + connect \BRANCH_in2_sel \dec_BRANCH_in2_sel + connect \BRANCH_internal_op \dec_BRANCH_internal_op + connect \BRANCH_is_32b \dec_BRANCH_is_32b + connect \BRANCH_lk \dec_BRANCH_lk + connect \BRANCH_rc_sel \dec_BRANCH_rc_sel + connect \BRANCH_sh \dec_BRANCH_sh + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:106254.16-106265.4" + cell \dec_bi$154 \dec_bi + connect \BRANCH_BD \dec_BRANCH_BD + connect \BRANCH_DS \dec_BRANCH_DS + connect \BRANCH_LI \dec_BRANCH_LI + connect \BRANCH_SH32 \dec_BRANCH_SH32 + connect \BRANCH_SI \dec_BRANCH_SI + connect \BRANCH_UI \dec_BRANCH_UI + connect \BRANCH_sh \dec_BRANCH_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:106266.19-106277.4" + cell \dec_cr_in$150 \dec_cr_in + connect \BRANCH_BA \dec_BRANCH_BA + connect \BRANCH_BB \dec_BRANCH_BB + connect \BRANCH_BC \dec_BRANCH_BC + connect \BRANCH_BI \dec_BRANCH_BI + connect \BRANCH_BT \dec_BRANCH_BT + connect \BRANCH_FXM \dec_BRANCH_FXM + connect \BRANCH_internal_op \dec_BRANCH_internal_op + connect \X_BFA \dec_X_BFA + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:106278.20-106286.4" + cell \dec_cr_out$152 \dec_cr_out + connect \BRANCH_FXM \dec_BRANCH_FXM + connect \BRANCH_internal_op \dec_BRANCH_internal_op + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \insn_in \dec_cr_out_insn_in + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:106287.16-106291.4" + cell \dec_oe$149 \dec_oe + connect \BRANCH_OE \dec_BRANCH_OE + connect \BRANCH_internal_op \dec_BRANCH_internal_op + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:106292.16-106296.4" + cell \dec_rc$148 \dec_rc + connect \BRANCH_Rc \dec_BRANCH_Rc + connect \rc \dec_rc_rc + connect \sel_in \dec_rc_sel_in + end + attribute \src "libresoc.v:105872.7-105872.20" + process $proc$libresoc.v:105872$4223 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:106297.3-106306.6" + process $proc$libresoc.v:106297$4222 + assign { } { } + assign { } { } + assign $0\BRANCH__lk[0:0] $1\BRANCH__lk[0:0] + attribute \src "libresoc.v:106298.5-106298.29" + switch \initial + attribute \src "libresoc.v:106298.9-106298.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:762" + switch \dec_BRANCH_lk + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\BRANCH__lk[0:0] \dec_BRANCH_LK + case + assign $1\BRANCH__lk[0:0] 1'0 + end + sync always + update \BRANCH__lk $0\BRANCH__lk[0:0] + end + connect \BRANCH__is_32bit \dec_BRANCH_is_32b + connect { \BRANCH__imm_data__ok \BRANCH__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_BRANCH_in2_sel + connect \BRANCH__fn_unit \dec_BRANCH_function_unit + connect \BRANCH__insn_type \dec_BRANCH_internal_op + connect \BRANCH__cia \core_pc + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_BRANCH_cr_out + connect \dec_cr_in_sel_in \dec_BRANCH_cr_in + connect \dec_oe_sel_in \dec_BRANCH_rc_sel + connect \dec_rc_sel_in \dec_BRANCH_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \BRANCH__insn \dec_opcode_in +end +attribute \src "libresoc.v:106327.1-106670.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR" +attribute \generator "nMigen" +module \dec_CR attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -20661,39 +166772,10 @@ module \dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec_sub20_dec31_dec_sub20_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub20_dec31_dec_sub20_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec_sub20_dec31_dec_sub20_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub20_dec31_dec_sub20_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 3 \CR__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 4 \CR__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -20768,58 +166850,26 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec31_dec_sub20_dec31_dec_sub20_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub20_dec31_dec_sub20_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub20_dec31_dec_sub20_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub20_dec31_dec_sub20_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec_sub20_dec31_dec_sub20_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub20_dec31_dec_sub20_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub20_dec31_dec_sub20_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub20_dec31_dec_sub20_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub20_dec31_dec_sub20_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub20_dec31_dec_sub20_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub20_dec31_dec_sub20_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub20_dec31_dec_sub20_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec31_dec_sub20_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 \dec31_dec_sub21_dec31_dec_sub21_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub21_dec31_dec_sub21_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \CR__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_CR_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_CR_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_CR_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_CR_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_CR_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 \dec_CR_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \dec_CR_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \dec_CR_Rc attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -20829,7 +166879,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub21_dec31_dec_sub21_cr_in + wire width 3 \dec_CR_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -20837,47 +166887,7 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub21_dec31_dec_sub21_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub21_dec31_dec_sub21_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub21_dec31_dec_sub21_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 \dec31_dec_sub21_dec31_dec_sub21_form + wire width 3 \dec_CR_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -20892,38 +166902,7 @@ module \dec31 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec_sub21_dec31_dec_sub21_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub21_dec31_dec_sub21_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec_sub21_dec31_dec_sub21_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub21_dec31_dec_sub21_in3_sel + wire width 12 \dec_CR_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -20999,57 +166978,21 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec31_dec_sub21_dec31_dec_sub21_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub21_dec31_dec_sub21_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub21_dec31_dec_sub21_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub21_dec31_dec_sub21_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec_sub21_dec31_dec_sub21_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub21_dec31_dec_sub21_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub21_dec31_dec_sub21_out_sel + wire width 7 \dec_CR_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub21_dec31_dec_sub21_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub21_dec31_dec_sub21_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub21_dec31_dec_sub21_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub21_dec31_dec_sub21_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub21_dec31_dec_sub21_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec31_dec_sub21_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 \dec31_dec_sub22_dec31_dec_sub22_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub22_dec31_dec_sub22_br + wire width 2 \dec_CR_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" + wire width 32 \dec_cr_in_insn_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -21058,56 +167001,307 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub22_dec31_dec_sub22_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" + wire width 3 \dec_cr_in_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" + wire \dec_cr_out_rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub22_dec31_dec_sub22_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" + wire width 3 \dec_cr_out_sel_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + wire width 2 \dec_rc_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + wire width 32 input 5 \raw_opcode_in + attribute \module_not_derived 1 + attribute \src "libresoc.v:106606.13-106626.4" + cell \dec$140 \dec + connect \CR_BA \dec_CR_BA + connect \CR_BB \dec_CR_BB + connect \CR_BC \dec_CR_BC + connect \CR_BI \dec_CR_BI + connect \CR_BT \dec_CR_BT + connect \CR_FXM \dec_CR_FXM + connect \CR_OE \dec_CR_OE + connect \CR_Rc \dec_CR_Rc + connect \CR_cr_in \dec_CR_cr_in + connect \CR_cr_out \dec_CR_cr_out + connect \CR_function_unit \dec_CR_function_unit + connect \CR_internal_op \dec_CR_internal_op + connect \CR_rc_sel \dec_CR_rc_sel + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:106627.19-106638.4" + cell \dec_cr_in$143 \dec_cr_in + connect \CR_BA \dec_CR_BA + connect \CR_BB \dec_CR_BB + connect \CR_BC \dec_CR_BC + connect \CR_BI \dec_CR_BI + connect \CR_BT \dec_CR_BT + connect \CR_FXM \dec_CR_FXM + connect \CR_internal_op \dec_CR_internal_op + connect \X_BFA \dec_X_BFA + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:106639.20-106647.4" + cell \dec_cr_out$145 \dec_cr_out + connect \CR_FXM \dec_CR_FXM + connect \CR_internal_op \dec_CR_internal_op + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \insn_in \dec_cr_out_insn_in + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:106648.16-106652.4" + cell \dec_oe$142 \dec_oe + connect \CR_OE \dec_CR_OE + connect \CR_internal_op \dec_CR_internal_op + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:106653.16-106657.4" + cell \dec_rc$141 \dec_rc + connect \CR_Rc \dec_CR_Rc + connect \rc \dec_rc_rc + connect \sel_in \dec_rc_sel_in + end + connect \CR__fn_unit \dec_CR_function_unit + connect \CR__insn_type \dec_CR_internal_op + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_CR_cr_out + connect \dec_cr_in_sel_in \dec_CR_cr_in + connect \dec_oe_sel_in \dec_CR_rc_sel + connect \dec_rc_sel_in \dec_CR_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \CR__insn \dec_opcode_in +end +attribute \src "libresoc.v:106674.1-107207.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV" +attribute \generator "nMigen" +module \dec_DIV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 18 \DIV__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 3 \DIV__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 4 \DIV__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 5 \DIV__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 12 \DIV__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 19 \DIV__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \DIV__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \DIV__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \DIV__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \DIV__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \DIV__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \DIV__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \DIV__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \DIV__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 7 \DIV__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \DIV__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \DIV__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \DIV__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_DIV_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_DIV_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_DIV_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 \dec_DIV_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_DIV_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_DIV_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 \dec_DIV_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 \dec_DIV_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 24 \dec_DIV_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \dec_DIV_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_DIV_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \dec_DIV_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_DIV_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 \dec_DIV_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 \dec_DIV_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub22_dec31_dec_sub22_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub22_dec31_dec_sub22_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 \dec31_dec_sub22_dec31_dec_sub22_form + wire width 3 \dec_DIV_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \dec_DIV_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec_DIV_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec_DIV_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -21122,7 +167316,7 @@ module \dec31 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec_sub22_dec31_dec_sub22_function_unit + wire width 12 \dec_DIV_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -21130,7 +167324,7 @@ module \dec31 attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub22_dec31_dec_sub22_in1_sel + wire width 3 \dec_DIV_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -21147,13 +167341,7 @@ module \dec31 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec_sub22_dec31_dec_sub22_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub22_dec31_dec_sub22_in3_sel + wire width 4 \dec_DIV_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -21229,13 +167417,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec31_dec_sub22_dec31_dec_sub22_internal_op + wire width 7 \dec_DIV_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub22_dec31_dec_sub22_inv_a + wire \dec_DIV_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub22_dec31_dec_sub22_inv_out + wire \dec_DIV_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub22_dec31_dec_sub22_is_32b + wire \dec_DIV_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" @@ -21243,43 +167431,56 @@ module \dec31 attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec_sub22_dec31_dec_sub22_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub22_dec31_dec_sub22_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub22_dec31_dec_sub22_out_sel + wire width 4 \dec_DIV_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub22_dec31_dec_sub22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub22_dec31_dec_sub22_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub22_dec31_dec_sub22_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub22_dec31_dec_sub22_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub22_dec31_dec_sub22_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec31_dec_sub22_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 \dec31_dec_sub23_dec31_dec_sub23_asmcode + wire width 2 \dec_DIV_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub23_dec31_dec_sub23_br + wire \dec_DIV_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 6 \dec_DIV_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + wire \dec_ai_immz_out + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" + wire width 3 \dec_ai_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" + wire width 32 \dec_cr_in_insn_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -21288,56 +167489,190 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub23_dec31_dec_sub23_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" + wire width 3 \dec_cr_in_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_cr_out_cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" + wire \dec_cr_out_rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub23_dec31_dec_sub23_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" + wire width 3 \dec_cr_out_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub23_dec31_dec_sub23_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub23_dec31_dec_sub23_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 \dec31_dec_sub23_dec31_dec_sub23_form + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + wire width 2 \dec_rc_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + wire width 32 input 20 \raw_opcode_in + attribute \module_not_derived 1 + attribute \src "libresoc.v:107091.13-107128.4" + cell \dec$171 \dec + connect \DIV_BA \dec_DIV_BA + connect \DIV_BB \dec_DIV_BB + connect \DIV_BC \dec_DIV_BC + connect \DIV_BD \dec_DIV_BD + connect \DIV_BI \dec_DIV_BI + connect \DIV_BT \dec_DIV_BT + connect \DIV_DS \dec_DIV_DS + connect \DIV_FXM \dec_DIV_FXM + connect \DIV_LI \dec_DIV_LI + connect \DIV_OE \dec_DIV_OE + connect \DIV_RA \dec_DIV_RA + connect \DIV_Rc \dec_DIV_Rc + connect \DIV_SH32 \dec_DIV_SH32 + connect \DIV_SI \dec_DIV_SI + connect \DIV_UI \dec_DIV_UI + connect \DIV_cr_in \dec_DIV_cr_in + connect \DIV_cr_out \dec_DIV_cr_out + connect \DIV_cry_in \dec_DIV_cry_in + connect \DIV_cry_out \dec_DIV_cry_out + connect \DIV_function_unit \dec_DIV_function_unit + connect \DIV_in1_sel \dec_DIV_in1_sel + connect \DIV_in2_sel \dec_DIV_in2_sel + connect \DIV_internal_op \dec_DIV_internal_op + connect \DIV_inv_a \dec_DIV_inv_a + connect \DIV_inv_out \dec_DIV_inv_out + connect \DIV_is_32b \dec_DIV_is_32b + connect \DIV_ldst_len \dec_DIV_ldst_len + connect \DIV_rc_sel \dec_DIV_rc_sel + connect \DIV_sgn \dec_DIV_sgn + connect \DIV_sh \dec_DIV_sh + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:107129.16-107133.4" + cell \dec_ai$178 \dec_ai + connect \DIV_RA \dec_DIV_RA + connect \immz_out \dec_ai_immz_out + connect \sel_in \dec_ai_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:107134.16-107145.4" + cell \dec_bi$179 \dec_bi + connect \DIV_BD \dec_DIV_BD + connect \DIV_DS \dec_DIV_DS + connect \DIV_LI \dec_DIV_LI + connect \DIV_SH32 \dec_DIV_SH32 + connect \DIV_SI \dec_DIV_SI + connect \DIV_UI \dec_DIV_UI + connect \DIV_sh \dec_DIV_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:107146.19-107157.4" + cell \dec_cr_in$174 \dec_cr_in + connect \DIV_BA \dec_DIV_BA + connect \DIV_BB \dec_DIV_BB + connect \DIV_BC \dec_DIV_BC + connect \DIV_BI \dec_DIV_BI + connect \DIV_BT \dec_DIV_BT + connect \DIV_FXM \dec_DIV_FXM + connect \DIV_internal_op \dec_DIV_internal_op + connect \X_BFA \dec_X_BFA + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:107158.20-107167.4" + cell \dec_cr_out$176 \dec_cr_out + connect \DIV_FXM \dec_DIV_FXM + connect \DIV_internal_op \dec_DIV_internal_op + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok + connect \insn_in \dec_cr_out_insn_in + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:107168.16-107174.4" + cell \dec_oe$173 \dec_oe + connect \DIV_OE \dec_DIV_OE + connect \DIV_internal_op \dec_DIV_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:107175.16-107180.4" + cell \dec_rc$172 \dec_rc + connect \DIV_Rc \dec_DIV_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + connect \DIV__is_signed \dec_DIV_sgn + connect \DIV__is_32bit \dec_DIV_is_32b + connect \DIV__output_carry \dec_DIV_cry_out + connect \DIV__input_carry \dec_DIV_cry_in + connect \DIV__invert_out \dec_DIV_inv_out + connect \DIV__invert_in \dec_DIV_inv_a + connect \DIV__data_len \dec_DIV_ldst_len + connect \DIV__write_cr0 \dec_cr_out_cr_bitfield_ok + connect { \DIV__oe__ok \DIV__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \DIV__rc__ok \DIV__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \DIV__imm_data__ok \DIV__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_DIV_in2_sel + connect \DIV__zero_a \dec_ai_immz_out + connect \dec_ai_sel_in \dec_DIV_in1_sel + connect \DIV__fn_unit \dec_DIV_function_unit + connect \DIV__insn_type \dec_DIV_internal_op + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_DIV_cr_out + connect \dec_cr_in_sel_in \dec_DIV_cr_in + connect \dec_oe_sel_in \dec_DIV_rc_sel + connect \dec_rc_sel_in \dec_DIV_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \DIV__insn \dec_opcode_in +end +attribute \src "libresoc.v:107211.1-107734.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST" +attribute \generator "nMigen" +module \dec_LDST + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \LDST__byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 13 \LDST__data_len attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -21351,39 +167686,14 @@ module \dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec_sub23_dec31_dec_sub23_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub23_dec31_dec_sub23_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec_sub23_dec31_dec_sub23_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub23_dec31_dec_sub23_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 3 \LDST__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 4 \LDST__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 5 \LDST__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 17 \LDST__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -21458,58 +167768,65 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec31_dec_sub23_dec31_dec_sub23_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub23_dec31_dec_sub23_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub23_dec31_dec_sub23_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub23_dec31_dec_sub23_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec_sub23_dec31_dec_sub23_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub23_dec31_dec_sub23_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub23_dec31_dec_sub23_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub23_dec31_dec_sub23_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub23_dec31_dec_sub23_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub23_dec31_dec_sub23_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub23_dec31_dec_sub23_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \LDST__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \LDST__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \LDST__is_signed attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub23_dec31_dec_sub23_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec31_dec_sub23_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 \dec31_dec_sub24_dec31_dec_sub24_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 16 \LDST__ldst_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \LDST__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \LDST__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \LDST__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 7 \LDST__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \LDST__sign_extend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \LDST__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_LDST_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_LDST_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_LDST_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 \dec_LDST_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_LDST_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_LDST_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 \dec_LDST_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 \dec_LDST_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 24 \dec_LDST_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \dec_LDST_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_LDST_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \dec_LDST_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_LDST_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 \dec_LDST_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 \dec_LDST_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub24_dec31_dec_sub24_br + wire \dec_LDST_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -21519,7 +167836,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub24_dec31_dec_sub24_cr_in + wire width 3 \dec_LDST_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -21527,47 +167844,7 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub24_dec31_dec_sub24_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub24_dec31_dec_sub24_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub24_dec31_dec_sub24_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 \dec31_dec_sub24_dec31_dec_sub24_form + wire width 3 \dec_LDST_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -21582,7 +167859,7 @@ module \dec31 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec_sub24_dec31_dec_sub24_function_unit + wire width 12 \dec_LDST_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -21590,7 +167867,7 @@ module \dec31 attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub24_dec31_dec_sub24_in1_sel + wire width 3 \dec_LDST_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -21607,13 +167884,7 @@ module \dec31 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec_sub24_dec31_dec_sub24_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub24_dec31_dec_sub24_in3_sel + wire width 4 \dec_LDST_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -21689,13 +167960,9 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec31_dec_sub24_dec31_dec_sub24_internal_op + wire width 7 \dec_LDST_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub24_dec31_dec_sub24_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub24_dec31_dec_sub24_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub24_dec31_dec_sub24_is_32b + wire \dec_LDST_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" @@ -21703,43 +167970,65 @@ module \dec31 attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec_sub24_dec31_dec_sub24_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub24_dec31_dec_sub24_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub24_dec31_dec_sub24_out_sel + wire width 4 \dec_LDST_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub24_dec31_dec_sub24_rc_sel + wire width 2 \dec_LDST_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub24_dec31_dec_sub24_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub24_dec31_dec_sub24_sgn + wire \dec_LDST_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub24_dec31_dec_sub24_sgn_ext + wire \dec_LDST_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 6 \dec_LDST_sh attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub24_dec31_dec_sub24_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec31_dec_sub24_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 \dec31_dec_sub26_dec31_dec_sub26_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub26_dec31_dec_sub26_br + wire width 2 \dec_LDST_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + wire \dec_ai_immz_out + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" + wire width 3 \dec_ai_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" + wire width 32 \dec_cr_in_insn_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -21748,56 +168037,182 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub26_dec31_dec_sub26_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" + wire width 3 \dec_cr_in_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" + wire \dec_cr_out_rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub26_dec31_dec_sub26_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" + wire width 3 \dec_cr_out_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub26_dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub26_dec31_dec_sub26_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 \dec31_dec_sub26_dec31_dec_sub26_form + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + wire width 2 \dec_rc_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + wire width 32 input 18 \raw_opcode_in + attribute \module_not_derived 1 + attribute \src "libresoc.v:107622.13-107658.4" + cell \dec$196 \dec + connect \LDST_BA \dec_LDST_BA + connect \LDST_BB \dec_LDST_BB + connect \LDST_BC \dec_LDST_BC + connect \LDST_BD \dec_LDST_BD + connect \LDST_BI \dec_LDST_BI + connect \LDST_BT \dec_LDST_BT + connect \LDST_DS \dec_LDST_DS + connect \LDST_FXM \dec_LDST_FXM + connect \LDST_LI \dec_LDST_LI + connect \LDST_OE \dec_LDST_OE + connect \LDST_RA \dec_LDST_RA + connect \LDST_Rc \dec_LDST_Rc + connect \LDST_SH32 \dec_LDST_SH32 + connect \LDST_SI \dec_LDST_SI + connect \LDST_UI \dec_LDST_UI + connect \LDST_br \dec_LDST_br + connect \LDST_cr_in \dec_LDST_cr_in + connect \LDST_cr_out \dec_LDST_cr_out + connect \LDST_function_unit \dec_LDST_function_unit + connect \LDST_in1_sel \dec_LDST_in1_sel + connect \LDST_in2_sel \dec_LDST_in2_sel + connect \LDST_internal_op \dec_LDST_internal_op + connect \LDST_is_32b \dec_LDST_is_32b + connect \LDST_ldst_len \dec_LDST_ldst_len + connect \LDST_rc_sel \dec_LDST_rc_sel + connect \LDST_sgn \dec_LDST_sgn + connect \LDST_sgn_ext \dec_LDST_sgn_ext + connect \LDST_sh \dec_LDST_sh + connect \LDST_upd \dec_LDST_upd + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:107659.16-107663.4" + cell \dec_ai$203 \dec_ai + connect \LDST_RA \dec_LDST_RA + connect \immz_out \dec_ai_immz_out + connect \sel_in \dec_ai_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:107664.16-107675.4" + cell \dec_bi$204 \dec_bi + connect \LDST_BD \dec_LDST_BD + connect \LDST_DS \dec_LDST_DS + connect \LDST_LI \dec_LDST_LI + connect \LDST_SH32 \dec_LDST_SH32 + connect \LDST_SI \dec_LDST_SI + connect \LDST_UI \dec_LDST_UI + connect \LDST_sh \dec_LDST_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:107676.19-107687.4" + cell \dec_cr_in$199 \dec_cr_in + connect \LDST_BA \dec_LDST_BA + connect \LDST_BB \dec_LDST_BB + connect \LDST_BC \dec_LDST_BC + connect \LDST_BI \dec_LDST_BI + connect \LDST_BT \dec_LDST_BT + connect \LDST_FXM \dec_LDST_FXM + connect \LDST_internal_op \dec_LDST_internal_op + connect \X_BFA \dec_X_BFA + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:107688.20-107696.4" + cell \dec_cr_out$201 \dec_cr_out + connect \LDST_FXM \dec_LDST_FXM + connect \LDST_internal_op \dec_LDST_internal_op + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \insn_in \dec_cr_out_insn_in + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:107697.16-107703.4" + cell \dec_oe$198 \dec_oe + connect \LDST_OE \dec_LDST_OE + connect \LDST_internal_op \dec_LDST_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:107704.16-107709.4" + cell \dec_rc$197 \dec_rc + connect \LDST_Rc \dec_LDST_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + connect \LDST__ldst_mode \dec_LDST_upd + connect \LDST__sign_extend \dec_LDST_sgn_ext + connect \LDST__byte_reverse \dec_LDST_br + connect \LDST__is_signed \dec_LDST_sgn + connect \LDST__is_32bit \dec_LDST_is_32b + connect \LDST__data_len \dec_LDST_ldst_len + connect { \LDST__oe__ok \LDST__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \LDST__rc__ok \LDST__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \LDST__imm_data__ok \LDST__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_LDST_in2_sel + connect \LDST__zero_a \dec_ai_immz_out + connect \dec_ai_sel_in \dec_LDST_in1_sel + connect \LDST__fn_unit \dec_LDST_function_unit + connect \LDST__insn_type \dec_LDST_internal_op + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_LDST_cr_out + connect \dec_cr_in_sel_in \dec_LDST_cr_in + connect \dec_oe_sel_in \dec_LDST_rc_sel + connect \dec_rc_sel_in \dec_LDST_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \LDST__insn \dec_opcode_in +end +attribute \src "libresoc.v:107738.1-108271.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL" +attribute \generator "nMigen" +module \dec_LOGICAL + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 18 \LOGICAL__data_len attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -21811,39 +168226,20 @@ module \dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec_sub26_dec31_dec_sub26_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub26_dec31_dec_sub26_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec_sub26_dec31_dec_sub26_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub26_dec31_dec_sub26_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 3 \LOGICAL__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 4 \LOGICAL__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 5 \LOGICAL__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 12 \LOGICAL__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 19 \LOGICAL__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -21918,58 +168314,62 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec31_dec_sub26_dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub26_dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub26_dec31_dec_sub26_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub26_dec31_dec_sub26_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec_sub26_dec31_dec_sub26_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub26_dec31_dec_sub26_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub26_dec31_dec_sub26_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub26_dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub26_dec31_dec_sub26_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub26_dec31_dec_sub26_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub26_dec31_dec_sub26_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub26_dec31_dec_sub26_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec31_dec_sub26_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 \dec31_dec_sub27_dec31_dec_sub27_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub27_dec31_dec_sub27_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \LOGICAL__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \LOGICAL__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \LOGICAL__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \LOGICAL__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \LOGICAL__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \LOGICAL__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \LOGICAL__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \LOGICAL__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 7 \LOGICAL__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \LOGICAL__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \LOGICAL__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \LOGICAL__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_LOGICAL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_LOGICAL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_LOGICAL_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 \dec_LOGICAL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_LOGICAL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_LOGICAL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 \dec_LOGICAL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 \dec_LOGICAL_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 24 \dec_LOGICAL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \dec_LOGICAL_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_LOGICAL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \dec_LOGICAL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_LOGICAL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 \dec_LOGICAL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 \dec_LOGICAL_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -21979,7 +168379,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub27_dec31_dec_sub27_cr_in + wire width 3 \dec_LOGICAL_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -21987,47 +168387,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub27_dec31_dec_sub27_cr_out + wire width 3 \dec_LOGICAL_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub27_dec31_dec_sub27_cry_in + wire width 2 \dec_LOGICAL_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub27_dec31_dec_sub27_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 \dec31_dec_sub27_dec31_dec_sub27_form + wire \dec_LOGICAL_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -22042,7 +168410,7 @@ module \dec31 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec_sub27_dec31_dec_sub27_function_unit + wire width 12 \dec_LOGICAL_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -22050,7 +168418,7 @@ module \dec31 attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub27_dec31_dec_sub27_in1_sel + wire width 3 \dec_LOGICAL_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -22067,13 +168435,7 @@ module \dec31 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec_sub27_dec31_dec_sub27_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub27_dec31_dec_sub27_in3_sel + wire width 4 \dec_LOGICAL_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -22149,13 +168511,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec31_dec_sub27_dec31_dec_sub27_internal_op + wire width 7 \dec_LOGICAL_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub27_dec31_dec_sub27_inv_a + wire \dec_LOGICAL_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub27_dec31_dec_sub27_inv_out + wire \dec_LOGICAL_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub27_dec31_dec_sub27_is_32b + wire \dec_LOGICAL_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" @@ -22163,43 +168525,56 @@ module \dec31 attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec_sub27_dec31_dec_sub27_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub27_dec31_dec_sub27_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub27_dec31_dec_sub27_out_sel + wire width 4 \dec_LOGICAL_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub27_dec31_dec_sub27_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub27_dec31_dec_sub27_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub27_dec31_dec_sub27_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub27_dec31_dec_sub27_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub27_dec31_dec_sub27_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec31_dec_sub27_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 \dec31_dec_sub28_dec31_dec_sub28_asmcode + wire width 2 \dec_LOGICAL_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub28_dec31_dec_sub28_br + wire \dec_LOGICAL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 6 \dec_LOGICAL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + wire \dec_ai_immz_out + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" + wire width 3 \dec_ai_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" + wire width 32 \dec_cr_in_insn_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -22208,56 +168583,186 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub28_dec31_dec_sub28_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" + wire width 3 \dec_cr_in_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_cr_out_cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" + wire \dec_cr_out_rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub28_dec31_dec_sub28_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" + wire width 3 \dec_cr_out_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub28_dec31_dec_sub28_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub28_dec31_dec_sub28_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 \dec31_dec_sub28_dec31_dec_sub28_form + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + wire width 2 \dec_rc_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + wire width 32 input 20 \raw_opcode_in + attribute \module_not_derived 1 + attribute \src "libresoc.v:108155.13-108192.4" + cell \dec$155 \dec + connect \LOGICAL_BA \dec_LOGICAL_BA + connect \LOGICAL_BB \dec_LOGICAL_BB + connect \LOGICAL_BC \dec_LOGICAL_BC + connect \LOGICAL_BD \dec_LOGICAL_BD + connect \LOGICAL_BI \dec_LOGICAL_BI + connect \LOGICAL_BT \dec_LOGICAL_BT + connect \LOGICAL_DS \dec_LOGICAL_DS + connect \LOGICAL_FXM \dec_LOGICAL_FXM + connect \LOGICAL_LI \dec_LOGICAL_LI + connect \LOGICAL_OE \dec_LOGICAL_OE + connect \LOGICAL_RA \dec_LOGICAL_RA + connect \LOGICAL_Rc \dec_LOGICAL_Rc + connect \LOGICAL_SH32 \dec_LOGICAL_SH32 + connect \LOGICAL_SI \dec_LOGICAL_SI + connect \LOGICAL_UI \dec_LOGICAL_UI + connect \LOGICAL_cr_in \dec_LOGICAL_cr_in + connect \LOGICAL_cr_out \dec_LOGICAL_cr_out + connect \LOGICAL_cry_in \dec_LOGICAL_cry_in + connect \LOGICAL_cry_out \dec_LOGICAL_cry_out + connect \LOGICAL_function_unit \dec_LOGICAL_function_unit + connect \LOGICAL_in1_sel \dec_LOGICAL_in1_sel + connect \LOGICAL_in2_sel \dec_LOGICAL_in2_sel + connect \LOGICAL_internal_op \dec_LOGICAL_internal_op + connect \LOGICAL_inv_a \dec_LOGICAL_inv_a + connect \LOGICAL_inv_out \dec_LOGICAL_inv_out + connect \LOGICAL_is_32b \dec_LOGICAL_is_32b + connect \LOGICAL_ldst_len \dec_LOGICAL_ldst_len + connect \LOGICAL_rc_sel \dec_LOGICAL_rc_sel + connect \LOGICAL_sgn \dec_LOGICAL_sgn + connect \LOGICAL_sh \dec_LOGICAL_sh + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:108193.16-108197.4" + cell \dec_ai$162 \dec_ai + connect \LOGICAL_RA \dec_LOGICAL_RA + connect \immz_out \dec_ai_immz_out + connect \sel_in \dec_ai_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:108198.16-108209.4" + cell \dec_bi$163 \dec_bi + connect \LOGICAL_BD \dec_LOGICAL_BD + connect \LOGICAL_DS \dec_LOGICAL_DS + connect \LOGICAL_LI \dec_LOGICAL_LI + connect \LOGICAL_SH32 \dec_LOGICAL_SH32 + connect \LOGICAL_SI \dec_LOGICAL_SI + connect \LOGICAL_UI \dec_LOGICAL_UI + connect \LOGICAL_sh \dec_LOGICAL_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:108210.19-108221.4" + cell \dec_cr_in$158 \dec_cr_in + connect \LOGICAL_BA \dec_LOGICAL_BA + connect \LOGICAL_BB \dec_LOGICAL_BB + connect \LOGICAL_BC \dec_LOGICAL_BC + connect \LOGICAL_BI \dec_LOGICAL_BI + connect \LOGICAL_BT \dec_LOGICAL_BT + connect \LOGICAL_FXM \dec_LOGICAL_FXM + connect \LOGICAL_internal_op \dec_LOGICAL_internal_op + connect \X_BFA \dec_X_BFA + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:108222.20-108231.4" + cell \dec_cr_out$160 \dec_cr_out + connect \LOGICAL_FXM \dec_LOGICAL_FXM + connect \LOGICAL_internal_op \dec_LOGICAL_internal_op + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok + connect \insn_in \dec_cr_out_insn_in + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:108232.16-108238.4" + cell \dec_oe$157 \dec_oe + connect \LOGICAL_OE \dec_LOGICAL_OE + connect \LOGICAL_internal_op \dec_LOGICAL_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:108239.16-108244.4" + cell \dec_rc$156 \dec_rc + connect \LOGICAL_Rc \dec_LOGICAL_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + connect \LOGICAL__is_signed \dec_LOGICAL_sgn + connect \LOGICAL__is_32bit \dec_LOGICAL_is_32b + connect \LOGICAL__output_carry \dec_LOGICAL_cry_out + connect \LOGICAL__input_carry \dec_LOGICAL_cry_in + connect \LOGICAL__invert_out \dec_LOGICAL_inv_out + connect \LOGICAL__invert_in \dec_LOGICAL_inv_a + connect \LOGICAL__data_len \dec_LOGICAL_ldst_len + connect \LOGICAL__write_cr0 \dec_cr_out_cr_bitfield_ok + connect { \LOGICAL__oe__ok \LOGICAL__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \LOGICAL__rc__ok \LOGICAL__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \LOGICAL__imm_data__ok \LOGICAL__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_LOGICAL_in2_sel + connect \LOGICAL__zero_a \dec_ai_immz_out + connect \dec_ai_sel_in \dec_LOGICAL_in1_sel + connect \LOGICAL__fn_unit \dec_LOGICAL_function_unit + connect \LOGICAL__insn_type \dec_LOGICAL_internal_op + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_LOGICAL_cr_out + connect \dec_cr_in_sel_in \dec_LOGICAL_cr_in + connect \dec_oe_sel_in \dec_LOGICAL_rc_sel + connect \dec_rc_sel_in \dec_LOGICAL_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \LOGICAL__insn \dec_opcode_in +end +attribute \src "libresoc.v:108275.1-108733.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL" +attribute \generator "nMigen" +module \dec_MUL attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -22271,39 +168776,14 @@ module \dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec_sub28_dec31_dec_sub28_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub28_dec31_dec_sub28_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec_sub28_dec31_dec_sub28_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub28_dec31_dec_sub28_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 3 \MUL__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 4 \MUL__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 5 \MUL__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 13 \MUL__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -22371,123 +168851,77 @@ module \dec31 attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec31_dec_sub28_dec31_dec_sub28_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub28_dec31_dec_sub28_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub28_dec31_dec_sub28_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub28_dec31_dec_sub28_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec_sub28_dec31_dec_sub28_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub28_dec31_dec_sub28_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub28_dec31_dec_sub28_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub28_dec31_dec_sub28_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub28_dec31_dec_sub28_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub28_dec31_dec_sub28_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub28_dec31_dec_sub28_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub28_dec31_dec_sub28_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec31_dec_sub28_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 \dec31_dec_sub4_dec31_dec_sub4_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub4_dec31_dec_sub4_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub4_dec31_dec_sub4_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub4_dec31_dec_sub4_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub4_dec31_dec_sub4_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub4_dec31_dec_sub4_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \MUL__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \MUL__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \MUL__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \MUL__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \MUL__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 7 \MUL__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \MUL__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \MUL__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_MUL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_MUL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_MUL_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 \dec_MUL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_MUL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_MUL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 \dec_MUL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 \dec_MUL_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 24 \dec_MUL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \dec_MUL_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \dec_MUL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_MUL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 \dec_MUL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 \dec_MUL_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 \dec31_dec_sub4_dec31_dec_sub4_form + wire width 3 \dec_MUL_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \dec_MUL_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -22502,15 +168936,7 @@ module \dec31 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec_sub4_dec31_dec_sub4_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub4_dec31_dec_sub4_in1_sel + wire width 12 \dec_MUL_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -22527,13 +168953,7 @@ module \dec31 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec_sub4_dec31_dec_sub4_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub4_dec31_dec_sub4_in3_sel + wire width 4 \dec_MUL_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -22609,57 +169029,48 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec31_dec_sub4_dec31_dec_sub4_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub4_dec31_dec_sub4_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub4_dec31_dec_sub4_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub4_dec31_dec_sub4_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec_sub4_dec31_dec_sub4_ldst_len + wire width 7 \dec_MUL_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub4_dec31_dec_sub4_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub4_dec31_dec_sub4_out_sel + wire \dec_MUL_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub4_dec31_dec_sub4_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub4_dec31_dec_sub4_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub4_dec31_dec_sub4_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub4_dec31_dec_sub4_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub4_dec31_dec_sub4_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec31_dec_sub4_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 \dec31_dec_sub8_dec31_dec_sub8_asmcode + wire width 2 \dec_MUL_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub8_dec31_dec_sub8_br + wire \dec_MUL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 6 \dec_MUL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" + wire width 32 \dec_cr_in_insn_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -22668,56 +169079,165 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub8_dec31_dec_sub8_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" + wire width 3 \dec_cr_in_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_cr_out_cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" + wire \dec_cr_out_rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub8_dec31_dec_sub8_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" + wire width 3 \dec_cr_out_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub8_dec31_dec_sub8_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub8_dec31_dec_sub8_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 \dec31_dec_sub8_dec31_dec_sub8_form + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + wire width 2 \dec_rc_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + wire width 32 input 14 \raw_opcode_in + attribute \module_not_derived 1 + attribute \src "libresoc.v:108636.13-108666.4" + cell \dec$180 \dec + connect \MUL_BA \dec_MUL_BA + connect \MUL_BB \dec_MUL_BB + connect \MUL_BC \dec_MUL_BC + connect \MUL_BD \dec_MUL_BD + connect \MUL_BI \dec_MUL_BI + connect \MUL_BT \dec_MUL_BT + connect \MUL_DS \dec_MUL_DS + connect \MUL_FXM \dec_MUL_FXM + connect \MUL_LI \dec_MUL_LI + connect \MUL_OE \dec_MUL_OE + connect \MUL_Rc \dec_MUL_Rc + connect \MUL_SH32 \dec_MUL_SH32 + connect \MUL_SI \dec_MUL_SI + connect \MUL_UI \dec_MUL_UI + connect \MUL_cr_in \dec_MUL_cr_in + connect \MUL_cr_out \dec_MUL_cr_out + connect \MUL_function_unit \dec_MUL_function_unit + connect \MUL_in2_sel \dec_MUL_in2_sel + connect \MUL_internal_op \dec_MUL_internal_op + connect \MUL_is_32b \dec_MUL_is_32b + connect \MUL_rc_sel \dec_MUL_rc_sel + connect \MUL_sgn \dec_MUL_sgn + connect \MUL_sh \dec_MUL_sh + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:108667.16-108678.4" + cell \dec_bi$187 \dec_bi + connect \MUL_BD \dec_MUL_BD + connect \MUL_DS \dec_MUL_DS + connect \MUL_LI \dec_MUL_LI + connect \MUL_SH32 \dec_MUL_SH32 + connect \MUL_SI \dec_MUL_SI + connect \MUL_UI \dec_MUL_UI + connect \MUL_sh \dec_MUL_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:108679.19-108690.4" + cell \dec_cr_in$183 \dec_cr_in + connect \MUL_BA \dec_MUL_BA + connect \MUL_BB \dec_MUL_BB + connect \MUL_BC \dec_MUL_BC + connect \MUL_BI \dec_MUL_BI + connect \MUL_BT \dec_MUL_BT + connect \MUL_FXM \dec_MUL_FXM + connect \MUL_internal_op \dec_MUL_internal_op + connect \X_BFA \dec_X_BFA + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:108691.20-108700.4" + cell \dec_cr_out$185 \dec_cr_out + connect \MUL_FXM \dec_MUL_FXM + connect \MUL_internal_op \dec_MUL_internal_op + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok + connect \insn_in \dec_cr_out_insn_in + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:108701.16-108707.4" + cell \dec_oe$182 \dec_oe + connect \MUL_OE \dec_MUL_OE + connect \MUL_internal_op \dec_MUL_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:108708.16-108713.4" + cell \dec_rc$181 \dec_rc + connect \MUL_Rc \dec_MUL_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + connect \MUL__is_signed \dec_MUL_sgn + connect \MUL__is_32bit \dec_MUL_is_32b + connect \MUL__write_cr0 \dec_cr_out_cr_bitfield_ok + connect { \MUL__oe__ok \MUL__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \MUL__rc__ok \MUL__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \MUL__imm_data__ok \MUL__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_MUL_in2_sel + connect \MUL__fn_unit \dec_MUL_function_unit + connect \MUL__insn_type \dec_MUL_internal_op + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_MUL_cr_out + connect \dec_cr_in_sel_in \dec_MUL_cr_in + connect \dec_oe_sel_in \dec_MUL_rc_sel + connect \dec_rc_sel_in \dec_MUL_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \MUL__insn \dec_opcode_in +end +attribute \src "libresoc.v:108737.1-109227.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT" +attribute \generator "nMigen" +module \dec_SHIFT_ROT attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -22731,39 +169251,22 @@ module \dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec_sub8_dec31_dec_sub8_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub8_dec31_dec_sub8_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec_sub8_dec31_dec_sub8_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub8_dec31_dec_sub8_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 3 \SHIFT_ROT__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 4 \SHIFT_ROT__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 5 \SHIFT_ROT__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 12 \SHIFT_ROT__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \SHIFT_ROT__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 18 \SHIFT_ROT__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -22838,58 +169341,58 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec31_dec_sub8_dec31_dec_sub8_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub8_dec31_dec_sub8_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub8_dec31_dec_sub8_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub8_dec31_dec_sub8_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec_sub8_dec31_dec_sub8_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub8_dec31_dec_sub8_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub8_dec31_dec_sub8_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub8_dec31_dec_sub8_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub8_dec31_dec_sub8_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub8_dec31_dec_sub8_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub8_dec31_dec_sub8_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub8_dec31_dec_sub8_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec31_dec_sub8_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 \dec31_dec_sub9_dec31_dec_sub9_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub9_dec31_dec_sub9_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \SHIFT_ROT__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \SHIFT_ROT__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \SHIFT_ROT__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \SHIFT_ROT__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \SHIFT_ROT__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \SHIFT_ROT__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \SHIFT_ROT__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \SHIFT_ROT__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 7 \SHIFT_ROT__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \SHIFT_ROT__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \SHIFT_ROT__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_SHIFT_ROT_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_SHIFT_ROT_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_SHIFT_ROT_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 \dec_SHIFT_ROT_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_SHIFT_ROT_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_SHIFT_ROT_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 \dec_SHIFT_ROT_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 \dec_SHIFT_ROT_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 24 \dec_SHIFT_ROT_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \dec_SHIFT_ROT_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \dec_SHIFT_ROT_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_SHIFT_ROT_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 \dec_SHIFT_ROT_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 \dec_SHIFT_ROT_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -22899,7 +169402,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub9_dec31_dec_sub9_cr_in + wire width 3 \dec_SHIFT_ROT_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -22907,47 +169410,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub9_dec31_dec_sub9_cr_out + wire width 3 \dec_SHIFT_ROT_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub9_dec31_dec_sub9_cry_in + wire width 2 \dec_SHIFT_ROT_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub9_dec31_dec_sub9_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 \dec31_dec_sub9_dec31_dec_sub9_form + wire \dec_SHIFT_ROT_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -22962,15 +169433,7 @@ module \dec31 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec31_dec_sub9_dec31_dec_sub9_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub9_dec31_dec_sub9_in1_sel + wire width 12 \dec_SHIFT_ROT_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -22987,13 +169450,7 @@ module \dec31 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec_sub9_dec31_dec_sub9_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub9_dec31_dec_sub9_in3_sel + wire width 4 \dec_SHIFT_ROT_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -23069,108 +169526,31 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec31_dec_sub9_dec31_dec_sub9_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub9_dec31_dec_sub9_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub9_dec31_dec_sub9_inv_out + wire width 7 \dec_SHIFT_ROT_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub9_dec31_dec_sub9_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec31_dec_sub9_dec31_dec_sub9_ldst_len + wire \dec_SHIFT_ROT_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub9_dec31_dec_sub9_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub9_dec31_dec_sub9_out_sel + wire \dec_SHIFT_ROT_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub9_dec31_dec_sub9_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub9_dec31_dec_sub9_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub9_dec31_dec_sub9_sgn + wire width 2 \dec_SHIFT_ROT_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub9_dec31_dec_sub9_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub9_dec31_dec_sub9_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec31_dec_sub9_opcode_in - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_in1_sel + wire \dec_SHIFT_ROT_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 6 \dec_SHIFT_ROT_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_bi_imm_b_ok attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -23186,14 +169566,202 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_in2_sel - attribute \enum_base_type "In3Sel" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" + wire width 3 \dec_cr_in_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_cr_out_cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" + wire \dec_cr_out_rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" + wire width 3 \dec_cr_out_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_in3_sel + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + wire width 2 \dec_rc_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + wire width 32 input 19 \raw_opcode_in + attribute \module_not_derived 1 + attribute \src "libresoc.v:109122.13-109155.4" + cell \dec$188 \dec + connect \SHIFT_ROT_BA \dec_SHIFT_ROT_BA + connect \SHIFT_ROT_BB \dec_SHIFT_ROT_BB + connect \SHIFT_ROT_BC \dec_SHIFT_ROT_BC + connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD + connect \SHIFT_ROT_BI \dec_SHIFT_ROT_BI + connect \SHIFT_ROT_BT \dec_SHIFT_ROT_BT + connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS + connect \SHIFT_ROT_FXM \dec_SHIFT_ROT_FXM + connect \SHIFT_ROT_LI \dec_SHIFT_ROT_LI + connect \SHIFT_ROT_OE \dec_SHIFT_ROT_OE + connect \SHIFT_ROT_Rc \dec_SHIFT_ROT_Rc + connect \SHIFT_ROT_SH32 \dec_SHIFT_ROT_SH32 + connect \SHIFT_ROT_SI \dec_SHIFT_ROT_SI + connect \SHIFT_ROT_UI \dec_SHIFT_ROT_UI + connect \SHIFT_ROT_cr_in \dec_SHIFT_ROT_cr_in + connect \SHIFT_ROT_cr_out \dec_SHIFT_ROT_cr_out + connect \SHIFT_ROT_cry_in \dec_SHIFT_ROT_cry_in + connect \SHIFT_ROT_cry_out \dec_SHIFT_ROT_cry_out + connect \SHIFT_ROT_function_unit \dec_SHIFT_ROT_function_unit + connect \SHIFT_ROT_in2_sel \dec_SHIFT_ROT_in2_sel + connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op + connect \SHIFT_ROT_inv_a \dec_SHIFT_ROT_inv_a + connect \SHIFT_ROT_is_32b \dec_SHIFT_ROT_is_32b + connect \SHIFT_ROT_rc_sel \dec_SHIFT_ROT_rc_sel + connect \SHIFT_ROT_sgn \dec_SHIFT_ROT_sgn + connect \SHIFT_ROT_sh \dec_SHIFT_ROT_sh + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:109156.16-109167.4" + cell \dec_bi$195 \dec_bi + connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD + connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS + connect \SHIFT_ROT_LI \dec_SHIFT_ROT_LI + connect \SHIFT_ROT_SH32 \dec_SHIFT_ROT_SH32 + connect \SHIFT_ROT_SI \dec_SHIFT_ROT_SI + connect \SHIFT_ROT_UI \dec_SHIFT_ROT_UI + connect \SHIFT_ROT_sh \dec_SHIFT_ROT_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:109168.19-109179.4" + cell \dec_cr_in$191 \dec_cr_in + connect \SHIFT_ROT_BA \dec_SHIFT_ROT_BA + connect \SHIFT_ROT_BB \dec_SHIFT_ROT_BB + connect \SHIFT_ROT_BC \dec_SHIFT_ROT_BC + connect \SHIFT_ROT_BI \dec_SHIFT_ROT_BI + connect \SHIFT_ROT_BT \dec_SHIFT_ROT_BT + connect \SHIFT_ROT_FXM \dec_SHIFT_ROT_FXM + connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op + connect \X_BFA \dec_X_BFA + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:109180.20-109189.4" + cell \dec_cr_out$193 \dec_cr_out + connect \SHIFT_ROT_FXM \dec_SHIFT_ROT_FXM + connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok + connect \insn_in \dec_cr_out_insn_in + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:109190.16-109196.4" + cell \dec_oe$190 \dec_oe + connect \SHIFT_ROT_OE \dec_SHIFT_ROT_OE + connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:109197.16-109202.4" + cell \dec_rc$189 \dec_rc + connect \SHIFT_ROT_Rc \dec_SHIFT_ROT_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + connect \SHIFT_ROT__is_signed \dec_SHIFT_ROT_sgn + connect \SHIFT_ROT__is_32bit \dec_SHIFT_ROT_is_32b + connect \SHIFT_ROT__output_carry \dec_SHIFT_ROT_cry_out + connect \SHIFT_ROT__input_carry \dec_SHIFT_ROT_cry_in + connect \SHIFT_ROT__invert_in \dec_SHIFT_ROT_inv_a + connect \SHIFT_ROT__output_cr \dec_SHIFT_ROT_cr_out [0] + connect \SHIFT_ROT__input_cr \dec_SHIFT_ROT_cr_in [0] + connect \SHIFT_ROT__write_cr0 \dec_cr_out_cr_bitfield_ok + connect { \SHIFT_ROT__oe__ok \SHIFT_ROT__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \SHIFT_ROT__rc__ok \SHIFT_ROT__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \SHIFT_ROT__imm_data__ok \SHIFT_ROT__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_SHIFT_ROT_in2_sel + connect \SHIFT_ROT__fn_unit \dec_SHIFT_ROT_function_unit + connect \SHIFT_ROT__insn_type \dec_SHIFT_ROT_internal_op + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_SHIFT_ROT_cr_out + connect \dec_cr_in_sel_in \dec_SHIFT_ROT_cr_in + connect \dec_oe_sel_in \dec_SHIFT_ROT_rc_sel + connect \dec_rc_sel_in \dec_SHIFT_ROT_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \SHIFT_ROT__insn \dec_opcode_in +end +attribute \src "libresoc.v:109231.1-109580.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR" +attribute \generator "nMigen" +module \dec_SPR + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 3 \SPR__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 4 \SPR__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -23268,4193 +169836,5842 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \SPR__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 5 \SPR__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_SPR_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_SPR_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_SPR_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_SPR_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \dec_SPR_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 \dec_SPR_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \dec_SPR_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \dec_SPR_Rc + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_upd - attribute \src "libresoc.v:11832.7-11832.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329" - wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 10 \opcode_switch - attribute \module_not_derived 1 - attribute \src "libresoc.v:16231.18-16257.4" - cell \dec31_dec_sub0 \dec31_dec_sub0 - connect \dec31_dec_sub0_asmcode \dec31_dec_sub0_dec31_dec_sub0_asmcode - connect \dec31_dec_sub0_br \dec31_dec_sub0_dec31_dec_sub0_br - connect \dec31_dec_sub0_cr_in \dec31_dec_sub0_dec31_dec_sub0_cr_in - connect \dec31_dec_sub0_cr_out \dec31_dec_sub0_dec31_dec_sub0_cr_out - connect \dec31_dec_sub0_cry_in \dec31_dec_sub0_dec31_dec_sub0_cry_in - connect \dec31_dec_sub0_cry_out \dec31_dec_sub0_dec31_dec_sub0_cry_out - connect \dec31_dec_sub0_form \dec31_dec_sub0_dec31_dec_sub0_form - connect \dec31_dec_sub0_function_unit \dec31_dec_sub0_dec31_dec_sub0_function_unit - connect \dec31_dec_sub0_in1_sel \dec31_dec_sub0_dec31_dec_sub0_in1_sel - connect \dec31_dec_sub0_in2_sel \dec31_dec_sub0_dec31_dec_sub0_in2_sel - connect \dec31_dec_sub0_in3_sel \dec31_dec_sub0_dec31_dec_sub0_in3_sel - connect \dec31_dec_sub0_internal_op \dec31_dec_sub0_dec31_dec_sub0_internal_op - connect \dec31_dec_sub0_inv_a \dec31_dec_sub0_dec31_dec_sub0_inv_a - connect \dec31_dec_sub0_inv_out \dec31_dec_sub0_dec31_dec_sub0_inv_out - connect \dec31_dec_sub0_is_32b \dec31_dec_sub0_dec31_dec_sub0_is_32b - connect \dec31_dec_sub0_ldst_len \dec31_dec_sub0_dec31_dec_sub0_ldst_len - connect \dec31_dec_sub0_lk \dec31_dec_sub0_dec31_dec_sub0_lk - connect \dec31_dec_sub0_out_sel \dec31_dec_sub0_dec31_dec_sub0_out_sel - connect \dec31_dec_sub0_rc_sel \dec31_dec_sub0_dec31_dec_sub0_rc_sel - connect \dec31_dec_sub0_rsrv \dec31_dec_sub0_dec31_dec_sub0_rsrv - connect \dec31_dec_sub0_sgl_pipe \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe - connect \dec31_dec_sub0_sgn \dec31_dec_sub0_dec31_dec_sub0_sgn - connect \dec31_dec_sub0_sgn_ext \dec31_dec_sub0_dec31_dec_sub0_sgn_ext - connect \dec31_dec_sub0_upd \dec31_dec_sub0_dec31_dec_sub0_upd - connect \opcode_in \dec31_dec_sub0_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:16258.19-16284.4" - cell \dec31_dec_sub10 \dec31_dec_sub10 - connect \dec31_dec_sub10_asmcode \dec31_dec_sub10_dec31_dec_sub10_asmcode - connect \dec31_dec_sub10_br \dec31_dec_sub10_dec31_dec_sub10_br - connect \dec31_dec_sub10_cr_in \dec31_dec_sub10_dec31_dec_sub10_cr_in - connect \dec31_dec_sub10_cr_out \dec31_dec_sub10_dec31_dec_sub10_cr_out - connect \dec31_dec_sub10_cry_in \dec31_dec_sub10_dec31_dec_sub10_cry_in - connect \dec31_dec_sub10_cry_out \dec31_dec_sub10_dec31_dec_sub10_cry_out - connect \dec31_dec_sub10_form \dec31_dec_sub10_dec31_dec_sub10_form - connect \dec31_dec_sub10_function_unit \dec31_dec_sub10_dec31_dec_sub10_function_unit - connect \dec31_dec_sub10_in1_sel \dec31_dec_sub10_dec31_dec_sub10_in1_sel - connect \dec31_dec_sub10_in2_sel \dec31_dec_sub10_dec31_dec_sub10_in2_sel - connect \dec31_dec_sub10_in3_sel \dec31_dec_sub10_dec31_dec_sub10_in3_sel - connect \dec31_dec_sub10_internal_op \dec31_dec_sub10_dec31_dec_sub10_internal_op - connect \dec31_dec_sub10_inv_a \dec31_dec_sub10_dec31_dec_sub10_inv_a - connect \dec31_dec_sub10_inv_out \dec31_dec_sub10_dec31_dec_sub10_inv_out - connect \dec31_dec_sub10_is_32b \dec31_dec_sub10_dec31_dec_sub10_is_32b - connect \dec31_dec_sub10_ldst_len \dec31_dec_sub10_dec31_dec_sub10_ldst_len - connect \dec31_dec_sub10_lk \dec31_dec_sub10_dec31_dec_sub10_lk - connect \dec31_dec_sub10_out_sel \dec31_dec_sub10_dec31_dec_sub10_out_sel - connect \dec31_dec_sub10_rc_sel \dec31_dec_sub10_dec31_dec_sub10_rc_sel - connect \dec31_dec_sub10_rsrv \dec31_dec_sub10_dec31_dec_sub10_rsrv - connect \dec31_dec_sub10_sgl_pipe \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe - connect \dec31_dec_sub10_sgn \dec31_dec_sub10_dec31_dec_sub10_sgn - connect \dec31_dec_sub10_sgn_ext \dec31_dec_sub10_dec31_dec_sub10_sgn_ext - connect \dec31_dec_sub10_upd \dec31_dec_sub10_dec31_dec_sub10_upd - connect \opcode_in \dec31_dec_sub10_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:16285.19-16311.4" - cell \dec31_dec_sub11 \dec31_dec_sub11 - connect \dec31_dec_sub11_asmcode \dec31_dec_sub11_dec31_dec_sub11_asmcode - connect \dec31_dec_sub11_br \dec31_dec_sub11_dec31_dec_sub11_br - connect \dec31_dec_sub11_cr_in \dec31_dec_sub11_dec31_dec_sub11_cr_in - connect \dec31_dec_sub11_cr_out \dec31_dec_sub11_dec31_dec_sub11_cr_out - connect \dec31_dec_sub11_cry_in \dec31_dec_sub11_dec31_dec_sub11_cry_in - connect \dec31_dec_sub11_cry_out \dec31_dec_sub11_dec31_dec_sub11_cry_out - connect \dec31_dec_sub11_form \dec31_dec_sub11_dec31_dec_sub11_form - connect \dec31_dec_sub11_function_unit \dec31_dec_sub11_dec31_dec_sub11_function_unit - connect \dec31_dec_sub11_in1_sel \dec31_dec_sub11_dec31_dec_sub11_in1_sel - connect \dec31_dec_sub11_in2_sel \dec31_dec_sub11_dec31_dec_sub11_in2_sel - connect \dec31_dec_sub11_in3_sel \dec31_dec_sub11_dec31_dec_sub11_in3_sel - connect \dec31_dec_sub11_internal_op \dec31_dec_sub11_dec31_dec_sub11_internal_op - connect \dec31_dec_sub11_inv_a \dec31_dec_sub11_dec31_dec_sub11_inv_a - connect \dec31_dec_sub11_inv_out \dec31_dec_sub11_dec31_dec_sub11_inv_out - connect \dec31_dec_sub11_is_32b \dec31_dec_sub11_dec31_dec_sub11_is_32b - connect \dec31_dec_sub11_ldst_len \dec31_dec_sub11_dec31_dec_sub11_ldst_len - connect \dec31_dec_sub11_lk \dec31_dec_sub11_dec31_dec_sub11_lk - connect \dec31_dec_sub11_out_sel \dec31_dec_sub11_dec31_dec_sub11_out_sel - connect \dec31_dec_sub11_rc_sel \dec31_dec_sub11_dec31_dec_sub11_rc_sel - connect \dec31_dec_sub11_rsrv \dec31_dec_sub11_dec31_dec_sub11_rsrv - connect \dec31_dec_sub11_sgl_pipe \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe - connect \dec31_dec_sub11_sgn \dec31_dec_sub11_dec31_dec_sub11_sgn - connect \dec31_dec_sub11_sgn_ext \dec31_dec_sub11_dec31_dec_sub11_sgn_ext - connect \dec31_dec_sub11_upd \dec31_dec_sub11_dec31_dec_sub11_upd - connect \opcode_in \dec31_dec_sub11_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:16312.19-16338.4" - cell \dec31_dec_sub15 \dec31_dec_sub15 - connect \dec31_dec_sub15_asmcode \dec31_dec_sub15_dec31_dec_sub15_asmcode - connect \dec31_dec_sub15_br \dec31_dec_sub15_dec31_dec_sub15_br - connect \dec31_dec_sub15_cr_in \dec31_dec_sub15_dec31_dec_sub15_cr_in - connect \dec31_dec_sub15_cr_out \dec31_dec_sub15_dec31_dec_sub15_cr_out - connect \dec31_dec_sub15_cry_in \dec31_dec_sub15_dec31_dec_sub15_cry_in - connect \dec31_dec_sub15_cry_out \dec31_dec_sub15_dec31_dec_sub15_cry_out - connect \dec31_dec_sub15_form \dec31_dec_sub15_dec31_dec_sub15_form - connect \dec31_dec_sub15_function_unit \dec31_dec_sub15_dec31_dec_sub15_function_unit - connect \dec31_dec_sub15_in1_sel \dec31_dec_sub15_dec31_dec_sub15_in1_sel - connect \dec31_dec_sub15_in2_sel \dec31_dec_sub15_dec31_dec_sub15_in2_sel - connect \dec31_dec_sub15_in3_sel \dec31_dec_sub15_dec31_dec_sub15_in3_sel - connect \dec31_dec_sub15_internal_op \dec31_dec_sub15_dec31_dec_sub15_internal_op - connect \dec31_dec_sub15_inv_a \dec31_dec_sub15_dec31_dec_sub15_inv_a - connect \dec31_dec_sub15_inv_out \dec31_dec_sub15_dec31_dec_sub15_inv_out - connect \dec31_dec_sub15_is_32b \dec31_dec_sub15_dec31_dec_sub15_is_32b - connect \dec31_dec_sub15_ldst_len \dec31_dec_sub15_dec31_dec_sub15_ldst_len - connect \dec31_dec_sub15_lk \dec31_dec_sub15_dec31_dec_sub15_lk - connect \dec31_dec_sub15_out_sel \dec31_dec_sub15_dec31_dec_sub15_out_sel - connect \dec31_dec_sub15_rc_sel \dec31_dec_sub15_dec31_dec_sub15_rc_sel - connect \dec31_dec_sub15_rsrv \dec31_dec_sub15_dec31_dec_sub15_rsrv - connect \dec31_dec_sub15_sgl_pipe \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe - connect \dec31_dec_sub15_sgn \dec31_dec_sub15_dec31_dec_sub15_sgn - connect \dec31_dec_sub15_sgn_ext \dec31_dec_sub15_dec31_dec_sub15_sgn_ext - connect \dec31_dec_sub15_upd \dec31_dec_sub15_dec31_dec_sub15_upd - connect \opcode_in \dec31_dec_sub15_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:16339.19-16365.4" - cell \dec31_dec_sub16 \dec31_dec_sub16 - connect \dec31_dec_sub16_asmcode \dec31_dec_sub16_dec31_dec_sub16_asmcode - connect \dec31_dec_sub16_br \dec31_dec_sub16_dec31_dec_sub16_br - connect \dec31_dec_sub16_cr_in \dec31_dec_sub16_dec31_dec_sub16_cr_in - connect \dec31_dec_sub16_cr_out \dec31_dec_sub16_dec31_dec_sub16_cr_out - connect \dec31_dec_sub16_cry_in \dec31_dec_sub16_dec31_dec_sub16_cry_in - connect \dec31_dec_sub16_cry_out \dec31_dec_sub16_dec31_dec_sub16_cry_out - connect \dec31_dec_sub16_form \dec31_dec_sub16_dec31_dec_sub16_form - connect \dec31_dec_sub16_function_unit \dec31_dec_sub16_dec31_dec_sub16_function_unit - connect \dec31_dec_sub16_in1_sel \dec31_dec_sub16_dec31_dec_sub16_in1_sel - connect \dec31_dec_sub16_in2_sel \dec31_dec_sub16_dec31_dec_sub16_in2_sel - connect \dec31_dec_sub16_in3_sel \dec31_dec_sub16_dec31_dec_sub16_in3_sel - connect \dec31_dec_sub16_internal_op \dec31_dec_sub16_dec31_dec_sub16_internal_op - connect \dec31_dec_sub16_inv_a \dec31_dec_sub16_dec31_dec_sub16_inv_a - connect \dec31_dec_sub16_inv_out \dec31_dec_sub16_dec31_dec_sub16_inv_out - connect \dec31_dec_sub16_is_32b \dec31_dec_sub16_dec31_dec_sub16_is_32b - connect \dec31_dec_sub16_ldst_len \dec31_dec_sub16_dec31_dec_sub16_ldst_len - connect \dec31_dec_sub16_lk \dec31_dec_sub16_dec31_dec_sub16_lk - connect \dec31_dec_sub16_out_sel \dec31_dec_sub16_dec31_dec_sub16_out_sel - connect \dec31_dec_sub16_rc_sel \dec31_dec_sub16_dec31_dec_sub16_rc_sel - connect \dec31_dec_sub16_rsrv \dec31_dec_sub16_dec31_dec_sub16_rsrv - connect \dec31_dec_sub16_sgl_pipe \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe - connect \dec31_dec_sub16_sgn \dec31_dec_sub16_dec31_dec_sub16_sgn - connect \dec31_dec_sub16_sgn_ext \dec31_dec_sub16_dec31_dec_sub16_sgn_ext - connect \dec31_dec_sub16_upd \dec31_dec_sub16_dec31_dec_sub16_upd - connect \opcode_in \dec31_dec_sub16_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:16366.19-16392.4" - cell \dec31_dec_sub18 \dec31_dec_sub18 - connect \dec31_dec_sub18_asmcode \dec31_dec_sub18_dec31_dec_sub18_asmcode - connect \dec31_dec_sub18_br \dec31_dec_sub18_dec31_dec_sub18_br - connect \dec31_dec_sub18_cr_in \dec31_dec_sub18_dec31_dec_sub18_cr_in - connect \dec31_dec_sub18_cr_out \dec31_dec_sub18_dec31_dec_sub18_cr_out - connect \dec31_dec_sub18_cry_in \dec31_dec_sub18_dec31_dec_sub18_cry_in - connect \dec31_dec_sub18_cry_out \dec31_dec_sub18_dec31_dec_sub18_cry_out - connect \dec31_dec_sub18_form \dec31_dec_sub18_dec31_dec_sub18_form - connect \dec31_dec_sub18_function_unit \dec31_dec_sub18_dec31_dec_sub18_function_unit - connect \dec31_dec_sub18_in1_sel \dec31_dec_sub18_dec31_dec_sub18_in1_sel - connect \dec31_dec_sub18_in2_sel \dec31_dec_sub18_dec31_dec_sub18_in2_sel - connect \dec31_dec_sub18_in3_sel \dec31_dec_sub18_dec31_dec_sub18_in3_sel - connect \dec31_dec_sub18_internal_op \dec31_dec_sub18_dec31_dec_sub18_internal_op - connect \dec31_dec_sub18_inv_a \dec31_dec_sub18_dec31_dec_sub18_inv_a - connect \dec31_dec_sub18_inv_out \dec31_dec_sub18_dec31_dec_sub18_inv_out - connect \dec31_dec_sub18_is_32b \dec31_dec_sub18_dec31_dec_sub18_is_32b - connect \dec31_dec_sub18_ldst_len \dec31_dec_sub18_dec31_dec_sub18_ldst_len - connect \dec31_dec_sub18_lk \dec31_dec_sub18_dec31_dec_sub18_lk - connect \dec31_dec_sub18_out_sel \dec31_dec_sub18_dec31_dec_sub18_out_sel - connect \dec31_dec_sub18_rc_sel \dec31_dec_sub18_dec31_dec_sub18_rc_sel - connect \dec31_dec_sub18_rsrv \dec31_dec_sub18_dec31_dec_sub18_rsrv - connect \dec31_dec_sub18_sgl_pipe \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe - connect \dec31_dec_sub18_sgn \dec31_dec_sub18_dec31_dec_sub18_sgn - connect \dec31_dec_sub18_sgn_ext \dec31_dec_sub18_dec31_dec_sub18_sgn_ext - connect \dec31_dec_sub18_upd \dec31_dec_sub18_dec31_dec_sub18_upd - connect \opcode_in \dec31_dec_sub18_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:16393.19-16419.4" - cell \dec31_dec_sub19 \dec31_dec_sub19 - connect \dec31_dec_sub19_asmcode \dec31_dec_sub19_dec31_dec_sub19_asmcode - connect \dec31_dec_sub19_br \dec31_dec_sub19_dec31_dec_sub19_br - connect \dec31_dec_sub19_cr_in \dec31_dec_sub19_dec31_dec_sub19_cr_in - connect \dec31_dec_sub19_cr_out \dec31_dec_sub19_dec31_dec_sub19_cr_out - connect \dec31_dec_sub19_cry_in \dec31_dec_sub19_dec31_dec_sub19_cry_in - connect \dec31_dec_sub19_cry_out \dec31_dec_sub19_dec31_dec_sub19_cry_out - connect \dec31_dec_sub19_form \dec31_dec_sub19_dec31_dec_sub19_form - connect \dec31_dec_sub19_function_unit \dec31_dec_sub19_dec31_dec_sub19_function_unit - connect \dec31_dec_sub19_in1_sel \dec31_dec_sub19_dec31_dec_sub19_in1_sel - connect \dec31_dec_sub19_in2_sel \dec31_dec_sub19_dec31_dec_sub19_in2_sel - connect \dec31_dec_sub19_in3_sel \dec31_dec_sub19_dec31_dec_sub19_in3_sel - connect \dec31_dec_sub19_internal_op \dec31_dec_sub19_dec31_dec_sub19_internal_op - connect \dec31_dec_sub19_inv_a \dec31_dec_sub19_dec31_dec_sub19_inv_a - connect \dec31_dec_sub19_inv_out \dec31_dec_sub19_dec31_dec_sub19_inv_out - connect \dec31_dec_sub19_is_32b \dec31_dec_sub19_dec31_dec_sub19_is_32b - connect \dec31_dec_sub19_ldst_len \dec31_dec_sub19_dec31_dec_sub19_ldst_len - connect \dec31_dec_sub19_lk \dec31_dec_sub19_dec31_dec_sub19_lk - connect \dec31_dec_sub19_out_sel \dec31_dec_sub19_dec31_dec_sub19_out_sel - connect \dec31_dec_sub19_rc_sel \dec31_dec_sub19_dec31_dec_sub19_rc_sel - connect \dec31_dec_sub19_rsrv \dec31_dec_sub19_dec31_dec_sub19_rsrv - connect \dec31_dec_sub19_sgl_pipe \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe - connect \dec31_dec_sub19_sgn \dec31_dec_sub19_dec31_dec_sub19_sgn - connect \dec31_dec_sub19_sgn_ext \dec31_dec_sub19_dec31_dec_sub19_sgn_ext - connect \dec31_dec_sub19_upd \dec31_dec_sub19_dec31_dec_sub19_upd - connect \opcode_in \dec31_dec_sub19_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:16420.19-16446.4" - cell \dec31_dec_sub20 \dec31_dec_sub20 - connect \dec31_dec_sub20_asmcode \dec31_dec_sub20_dec31_dec_sub20_asmcode - connect \dec31_dec_sub20_br \dec31_dec_sub20_dec31_dec_sub20_br - connect \dec31_dec_sub20_cr_in \dec31_dec_sub20_dec31_dec_sub20_cr_in - connect \dec31_dec_sub20_cr_out \dec31_dec_sub20_dec31_dec_sub20_cr_out - connect \dec31_dec_sub20_cry_in \dec31_dec_sub20_dec31_dec_sub20_cry_in - connect \dec31_dec_sub20_cry_out \dec31_dec_sub20_dec31_dec_sub20_cry_out - connect \dec31_dec_sub20_form \dec31_dec_sub20_dec31_dec_sub20_form - connect \dec31_dec_sub20_function_unit \dec31_dec_sub20_dec31_dec_sub20_function_unit - connect \dec31_dec_sub20_in1_sel \dec31_dec_sub20_dec31_dec_sub20_in1_sel - connect \dec31_dec_sub20_in2_sel \dec31_dec_sub20_dec31_dec_sub20_in2_sel - connect \dec31_dec_sub20_in3_sel \dec31_dec_sub20_dec31_dec_sub20_in3_sel - connect \dec31_dec_sub20_internal_op \dec31_dec_sub20_dec31_dec_sub20_internal_op - connect \dec31_dec_sub20_inv_a \dec31_dec_sub20_dec31_dec_sub20_inv_a - connect \dec31_dec_sub20_inv_out \dec31_dec_sub20_dec31_dec_sub20_inv_out - connect \dec31_dec_sub20_is_32b \dec31_dec_sub20_dec31_dec_sub20_is_32b - connect \dec31_dec_sub20_ldst_len \dec31_dec_sub20_dec31_dec_sub20_ldst_len - connect \dec31_dec_sub20_lk \dec31_dec_sub20_dec31_dec_sub20_lk - connect \dec31_dec_sub20_out_sel \dec31_dec_sub20_dec31_dec_sub20_out_sel - connect \dec31_dec_sub20_rc_sel \dec31_dec_sub20_dec31_dec_sub20_rc_sel - connect \dec31_dec_sub20_rsrv \dec31_dec_sub20_dec31_dec_sub20_rsrv - connect \dec31_dec_sub20_sgl_pipe \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe - connect \dec31_dec_sub20_sgn \dec31_dec_sub20_dec31_dec_sub20_sgn - connect \dec31_dec_sub20_sgn_ext \dec31_dec_sub20_dec31_dec_sub20_sgn_ext - connect \dec31_dec_sub20_upd \dec31_dec_sub20_dec31_dec_sub20_upd - connect \opcode_in \dec31_dec_sub20_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:16447.19-16473.4" - cell \dec31_dec_sub21 \dec31_dec_sub21 - connect \dec31_dec_sub21_asmcode \dec31_dec_sub21_dec31_dec_sub21_asmcode - connect \dec31_dec_sub21_br \dec31_dec_sub21_dec31_dec_sub21_br - connect \dec31_dec_sub21_cr_in \dec31_dec_sub21_dec31_dec_sub21_cr_in - connect \dec31_dec_sub21_cr_out \dec31_dec_sub21_dec31_dec_sub21_cr_out - connect \dec31_dec_sub21_cry_in \dec31_dec_sub21_dec31_dec_sub21_cry_in - connect \dec31_dec_sub21_cry_out \dec31_dec_sub21_dec31_dec_sub21_cry_out - connect \dec31_dec_sub21_form \dec31_dec_sub21_dec31_dec_sub21_form - connect \dec31_dec_sub21_function_unit \dec31_dec_sub21_dec31_dec_sub21_function_unit - connect \dec31_dec_sub21_in1_sel \dec31_dec_sub21_dec31_dec_sub21_in1_sel - connect \dec31_dec_sub21_in2_sel \dec31_dec_sub21_dec31_dec_sub21_in2_sel - connect \dec31_dec_sub21_in3_sel \dec31_dec_sub21_dec31_dec_sub21_in3_sel - connect \dec31_dec_sub21_internal_op \dec31_dec_sub21_dec31_dec_sub21_internal_op - connect \dec31_dec_sub21_inv_a \dec31_dec_sub21_dec31_dec_sub21_inv_a - connect \dec31_dec_sub21_inv_out \dec31_dec_sub21_dec31_dec_sub21_inv_out - connect \dec31_dec_sub21_is_32b \dec31_dec_sub21_dec31_dec_sub21_is_32b - connect \dec31_dec_sub21_ldst_len \dec31_dec_sub21_dec31_dec_sub21_ldst_len - connect \dec31_dec_sub21_lk \dec31_dec_sub21_dec31_dec_sub21_lk - connect \dec31_dec_sub21_out_sel \dec31_dec_sub21_dec31_dec_sub21_out_sel - connect \dec31_dec_sub21_rc_sel \dec31_dec_sub21_dec31_dec_sub21_rc_sel - connect \dec31_dec_sub21_rsrv \dec31_dec_sub21_dec31_dec_sub21_rsrv - connect \dec31_dec_sub21_sgl_pipe \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe - connect \dec31_dec_sub21_sgn \dec31_dec_sub21_dec31_dec_sub21_sgn - connect \dec31_dec_sub21_sgn_ext \dec31_dec_sub21_dec31_dec_sub21_sgn_ext - connect \dec31_dec_sub21_upd \dec31_dec_sub21_dec31_dec_sub21_upd - connect \opcode_in \dec31_dec_sub21_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:16474.19-16500.4" - cell \dec31_dec_sub22 \dec31_dec_sub22 - connect \dec31_dec_sub22_asmcode \dec31_dec_sub22_dec31_dec_sub22_asmcode - connect \dec31_dec_sub22_br \dec31_dec_sub22_dec31_dec_sub22_br - connect \dec31_dec_sub22_cr_in \dec31_dec_sub22_dec31_dec_sub22_cr_in - connect \dec31_dec_sub22_cr_out \dec31_dec_sub22_dec31_dec_sub22_cr_out - connect \dec31_dec_sub22_cry_in \dec31_dec_sub22_dec31_dec_sub22_cry_in - connect \dec31_dec_sub22_cry_out \dec31_dec_sub22_dec31_dec_sub22_cry_out - connect \dec31_dec_sub22_form \dec31_dec_sub22_dec31_dec_sub22_form - connect \dec31_dec_sub22_function_unit \dec31_dec_sub22_dec31_dec_sub22_function_unit - connect \dec31_dec_sub22_in1_sel \dec31_dec_sub22_dec31_dec_sub22_in1_sel - connect \dec31_dec_sub22_in2_sel \dec31_dec_sub22_dec31_dec_sub22_in2_sel - connect \dec31_dec_sub22_in3_sel \dec31_dec_sub22_dec31_dec_sub22_in3_sel - connect \dec31_dec_sub22_internal_op \dec31_dec_sub22_dec31_dec_sub22_internal_op - connect \dec31_dec_sub22_inv_a \dec31_dec_sub22_dec31_dec_sub22_inv_a - connect \dec31_dec_sub22_inv_out \dec31_dec_sub22_dec31_dec_sub22_inv_out - connect \dec31_dec_sub22_is_32b \dec31_dec_sub22_dec31_dec_sub22_is_32b - connect \dec31_dec_sub22_ldst_len \dec31_dec_sub22_dec31_dec_sub22_ldst_len - connect \dec31_dec_sub22_lk \dec31_dec_sub22_dec31_dec_sub22_lk - connect \dec31_dec_sub22_out_sel \dec31_dec_sub22_dec31_dec_sub22_out_sel - connect \dec31_dec_sub22_rc_sel \dec31_dec_sub22_dec31_dec_sub22_rc_sel - connect \dec31_dec_sub22_rsrv \dec31_dec_sub22_dec31_dec_sub22_rsrv - connect \dec31_dec_sub22_sgl_pipe \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe - connect \dec31_dec_sub22_sgn \dec31_dec_sub22_dec31_dec_sub22_sgn - connect \dec31_dec_sub22_sgn_ext \dec31_dec_sub22_dec31_dec_sub22_sgn_ext - connect \dec31_dec_sub22_upd \dec31_dec_sub22_dec31_dec_sub22_upd - connect \opcode_in \dec31_dec_sub22_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:16501.19-16527.4" - cell \dec31_dec_sub23 \dec31_dec_sub23 - connect \dec31_dec_sub23_asmcode \dec31_dec_sub23_dec31_dec_sub23_asmcode - connect \dec31_dec_sub23_br \dec31_dec_sub23_dec31_dec_sub23_br - connect \dec31_dec_sub23_cr_in \dec31_dec_sub23_dec31_dec_sub23_cr_in - connect \dec31_dec_sub23_cr_out \dec31_dec_sub23_dec31_dec_sub23_cr_out - connect \dec31_dec_sub23_cry_in \dec31_dec_sub23_dec31_dec_sub23_cry_in - connect \dec31_dec_sub23_cry_out \dec31_dec_sub23_dec31_dec_sub23_cry_out - connect \dec31_dec_sub23_form \dec31_dec_sub23_dec31_dec_sub23_form - connect \dec31_dec_sub23_function_unit \dec31_dec_sub23_dec31_dec_sub23_function_unit - connect \dec31_dec_sub23_in1_sel \dec31_dec_sub23_dec31_dec_sub23_in1_sel - connect \dec31_dec_sub23_in2_sel \dec31_dec_sub23_dec31_dec_sub23_in2_sel - connect \dec31_dec_sub23_in3_sel \dec31_dec_sub23_dec31_dec_sub23_in3_sel - connect \dec31_dec_sub23_internal_op \dec31_dec_sub23_dec31_dec_sub23_internal_op - connect \dec31_dec_sub23_inv_a \dec31_dec_sub23_dec31_dec_sub23_inv_a - connect \dec31_dec_sub23_inv_out \dec31_dec_sub23_dec31_dec_sub23_inv_out - connect \dec31_dec_sub23_is_32b \dec31_dec_sub23_dec31_dec_sub23_is_32b - connect \dec31_dec_sub23_ldst_len \dec31_dec_sub23_dec31_dec_sub23_ldst_len - connect \dec31_dec_sub23_lk \dec31_dec_sub23_dec31_dec_sub23_lk - connect \dec31_dec_sub23_out_sel \dec31_dec_sub23_dec31_dec_sub23_out_sel - connect \dec31_dec_sub23_rc_sel \dec31_dec_sub23_dec31_dec_sub23_rc_sel - connect \dec31_dec_sub23_rsrv \dec31_dec_sub23_dec31_dec_sub23_rsrv - connect \dec31_dec_sub23_sgl_pipe \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe - connect \dec31_dec_sub23_sgn \dec31_dec_sub23_dec31_dec_sub23_sgn - connect \dec31_dec_sub23_sgn_ext \dec31_dec_sub23_dec31_dec_sub23_sgn_ext - connect \dec31_dec_sub23_upd \dec31_dec_sub23_dec31_dec_sub23_upd - connect \opcode_in \dec31_dec_sub23_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:16528.19-16554.4" - cell \dec31_dec_sub24 \dec31_dec_sub24 - connect \dec31_dec_sub24_asmcode \dec31_dec_sub24_dec31_dec_sub24_asmcode - connect \dec31_dec_sub24_br \dec31_dec_sub24_dec31_dec_sub24_br - connect \dec31_dec_sub24_cr_in \dec31_dec_sub24_dec31_dec_sub24_cr_in - connect \dec31_dec_sub24_cr_out \dec31_dec_sub24_dec31_dec_sub24_cr_out - connect \dec31_dec_sub24_cry_in \dec31_dec_sub24_dec31_dec_sub24_cry_in - connect \dec31_dec_sub24_cry_out \dec31_dec_sub24_dec31_dec_sub24_cry_out - connect \dec31_dec_sub24_form \dec31_dec_sub24_dec31_dec_sub24_form - connect \dec31_dec_sub24_function_unit \dec31_dec_sub24_dec31_dec_sub24_function_unit - connect \dec31_dec_sub24_in1_sel \dec31_dec_sub24_dec31_dec_sub24_in1_sel - connect \dec31_dec_sub24_in2_sel \dec31_dec_sub24_dec31_dec_sub24_in2_sel - connect \dec31_dec_sub24_in3_sel \dec31_dec_sub24_dec31_dec_sub24_in3_sel - connect \dec31_dec_sub24_internal_op \dec31_dec_sub24_dec31_dec_sub24_internal_op - connect \dec31_dec_sub24_inv_a \dec31_dec_sub24_dec31_dec_sub24_inv_a - connect \dec31_dec_sub24_inv_out \dec31_dec_sub24_dec31_dec_sub24_inv_out - connect \dec31_dec_sub24_is_32b \dec31_dec_sub24_dec31_dec_sub24_is_32b - connect \dec31_dec_sub24_ldst_len \dec31_dec_sub24_dec31_dec_sub24_ldst_len - connect \dec31_dec_sub24_lk \dec31_dec_sub24_dec31_dec_sub24_lk - connect \dec31_dec_sub24_out_sel \dec31_dec_sub24_dec31_dec_sub24_out_sel - connect \dec31_dec_sub24_rc_sel \dec31_dec_sub24_dec31_dec_sub24_rc_sel - connect \dec31_dec_sub24_rsrv \dec31_dec_sub24_dec31_dec_sub24_rsrv - connect \dec31_dec_sub24_sgl_pipe \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe - connect \dec31_dec_sub24_sgn \dec31_dec_sub24_dec31_dec_sub24_sgn - connect \dec31_dec_sub24_sgn_ext \dec31_dec_sub24_dec31_dec_sub24_sgn_ext - connect \dec31_dec_sub24_upd \dec31_dec_sub24_dec31_dec_sub24_upd - connect \opcode_in \dec31_dec_sub24_opcode_in - end + wire width 3 \dec_SPR_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \dec_SPR_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 \dec_SPR_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \dec_SPR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec_SPR_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec_SPR_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" + wire width 3 \dec_cr_in_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" + wire \dec_cr_out_rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" + wire width 3 \dec_cr_out_sel_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + wire width 2 \dec_rc_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + wire width 32 input 6 \raw_opcode_in attribute \module_not_derived 1 - attribute \src "libresoc.v:16555.19-16581.4" - cell \dec31_dec_sub26 \dec31_dec_sub26 - connect \dec31_dec_sub26_asmcode \dec31_dec_sub26_dec31_dec_sub26_asmcode - connect \dec31_dec_sub26_br \dec31_dec_sub26_dec31_dec_sub26_br - connect \dec31_dec_sub26_cr_in \dec31_dec_sub26_dec31_dec_sub26_cr_in - connect \dec31_dec_sub26_cr_out \dec31_dec_sub26_dec31_dec_sub26_cr_out - connect \dec31_dec_sub26_cry_in \dec31_dec_sub26_dec31_dec_sub26_cry_in - connect \dec31_dec_sub26_cry_out \dec31_dec_sub26_dec31_dec_sub26_cry_out - connect \dec31_dec_sub26_form \dec31_dec_sub26_dec31_dec_sub26_form - connect \dec31_dec_sub26_function_unit \dec31_dec_sub26_dec31_dec_sub26_function_unit - connect \dec31_dec_sub26_in1_sel \dec31_dec_sub26_dec31_dec_sub26_in1_sel - connect \dec31_dec_sub26_in2_sel \dec31_dec_sub26_dec31_dec_sub26_in2_sel - connect \dec31_dec_sub26_in3_sel \dec31_dec_sub26_dec31_dec_sub26_in3_sel - connect \dec31_dec_sub26_internal_op \dec31_dec_sub26_dec31_dec_sub26_internal_op - connect \dec31_dec_sub26_inv_a \dec31_dec_sub26_dec31_dec_sub26_inv_a - connect \dec31_dec_sub26_inv_out \dec31_dec_sub26_dec31_dec_sub26_inv_out - connect \dec31_dec_sub26_is_32b \dec31_dec_sub26_dec31_dec_sub26_is_32b - connect \dec31_dec_sub26_ldst_len \dec31_dec_sub26_dec31_dec_sub26_ldst_len - connect \dec31_dec_sub26_lk \dec31_dec_sub26_dec31_dec_sub26_lk - connect \dec31_dec_sub26_out_sel \dec31_dec_sub26_dec31_dec_sub26_out_sel - connect \dec31_dec_sub26_rc_sel \dec31_dec_sub26_dec31_dec_sub26_rc_sel - connect \dec31_dec_sub26_rsrv \dec31_dec_sub26_dec31_dec_sub26_rsrv - connect \dec31_dec_sub26_sgl_pipe \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe - connect \dec31_dec_sub26_sgn \dec31_dec_sub26_dec31_dec_sub26_sgn - connect \dec31_dec_sub26_sgn_ext \dec31_dec_sub26_dec31_dec_sub26_sgn_ext - connect \dec31_dec_sub26_upd \dec31_dec_sub26_dec31_dec_sub26_upd - connect \opcode_in \dec31_dec_sub26_opcode_in + attribute \src "libresoc.v:109514.13-109535.4" + cell \dec$164 \dec + connect \SPR_BA \dec_SPR_BA + connect \SPR_BB \dec_SPR_BB + connect \SPR_BC \dec_SPR_BC + connect \SPR_BI \dec_SPR_BI + connect \SPR_BT \dec_SPR_BT + connect \SPR_FXM \dec_SPR_FXM + connect \SPR_OE \dec_SPR_OE + connect \SPR_Rc \dec_SPR_Rc + connect \SPR_cr_in \dec_SPR_cr_in + connect \SPR_cr_out \dec_SPR_cr_out + connect \SPR_function_unit \dec_SPR_function_unit + connect \SPR_internal_op \dec_SPR_internal_op + connect \SPR_is_32b \dec_SPR_is_32b + connect \SPR_rc_sel \dec_SPR_rc_sel + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:16582.19-16608.4" - cell \dec31_dec_sub27 \dec31_dec_sub27 - connect \dec31_dec_sub27_asmcode \dec31_dec_sub27_dec31_dec_sub27_asmcode - connect \dec31_dec_sub27_br \dec31_dec_sub27_dec31_dec_sub27_br - connect \dec31_dec_sub27_cr_in \dec31_dec_sub27_dec31_dec_sub27_cr_in - connect \dec31_dec_sub27_cr_out \dec31_dec_sub27_dec31_dec_sub27_cr_out - connect \dec31_dec_sub27_cry_in \dec31_dec_sub27_dec31_dec_sub27_cry_in - connect \dec31_dec_sub27_cry_out \dec31_dec_sub27_dec31_dec_sub27_cry_out - connect \dec31_dec_sub27_form \dec31_dec_sub27_dec31_dec_sub27_form - connect \dec31_dec_sub27_function_unit \dec31_dec_sub27_dec31_dec_sub27_function_unit - connect \dec31_dec_sub27_in1_sel \dec31_dec_sub27_dec31_dec_sub27_in1_sel - connect \dec31_dec_sub27_in2_sel \dec31_dec_sub27_dec31_dec_sub27_in2_sel - connect \dec31_dec_sub27_in3_sel \dec31_dec_sub27_dec31_dec_sub27_in3_sel - connect \dec31_dec_sub27_internal_op \dec31_dec_sub27_dec31_dec_sub27_internal_op - connect \dec31_dec_sub27_inv_a \dec31_dec_sub27_dec31_dec_sub27_inv_a - connect \dec31_dec_sub27_inv_out \dec31_dec_sub27_dec31_dec_sub27_inv_out - connect \dec31_dec_sub27_is_32b \dec31_dec_sub27_dec31_dec_sub27_is_32b - connect \dec31_dec_sub27_ldst_len \dec31_dec_sub27_dec31_dec_sub27_ldst_len - connect \dec31_dec_sub27_lk \dec31_dec_sub27_dec31_dec_sub27_lk - connect \dec31_dec_sub27_out_sel \dec31_dec_sub27_dec31_dec_sub27_out_sel - connect \dec31_dec_sub27_rc_sel \dec31_dec_sub27_dec31_dec_sub27_rc_sel - connect \dec31_dec_sub27_rsrv \dec31_dec_sub27_dec31_dec_sub27_rsrv - connect \dec31_dec_sub27_sgl_pipe \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe - connect \dec31_dec_sub27_sgn \dec31_dec_sub27_dec31_dec_sub27_sgn - connect \dec31_dec_sub27_sgn_ext \dec31_dec_sub27_dec31_dec_sub27_sgn_ext - connect \dec31_dec_sub27_upd \dec31_dec_sub27_dec31_dec_sub27_upd - connect \opcode_in \dec31_dec_sub27_opcode_in + attribute \src "libresoc.v:109536.19-109547.4" + cell \dec_cr_in$167 \dec_cr_in + connect \SPR_BA \dec_SPR_BA + connect \SPR_BB \dec_SPR_BB + connect \SPR_BC \dec_SPR_BC + connect \SPR_BI \dec_SPR_BI + connect \SPR_BT \dec_SPR_BT + connect \SPR_FXM \dec_SPR_FXM + connect \SPR_internal_op \dec_SPR_internal_op + connect \X_BFA \dec_X_BFA + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:16609.19-16635.4" - cell \dec31_dec_sub28 \dec31_dec_sub28 - connect \dec31_dec_sub28_asmcode \dec31_dec_sub28_dec31_dec_sub28_asmcode - connect \dec31_dec_sub28_br \dec31_dec_sub28_dec31_dec_sub28_br - connect \dec31_dec_sub28_cr_in \dec31_dec_sub28_dec31_dec_sub28_cr_in - connect \dec31_dec_sub28_cr_out \dec31_dec_sub28_dec31_dec_sub28_cr_out - connect \dec31_dec_sub28_cry_in \dec31_dec_sub28_dec31_dec_sub28_cry_in - connect \dec31_dec_sub28_cry_out \dec31_dec_sub28_dec31_dec_sub28_cry_out - connect \dec31_dec_sub28_form \dec31_dec_sub28_dec31_dec_sub28_form - connect \dec31_dec_sub28_function_unit \dec31_dec_sub28_dec31_dec_sub28_function_unit - connect \dec31_dec_sub28_in1_sel \dec31_dec_sub28_dec31_dec_sub28_in1_sel - connect \dec31_dec_sub28_in2_sel \dec31_dec_sub28_dec31_dec_sub28_in2_sel - connect \dec31_dec_sub28_in3_sel \dec31_dec_sub28_dec31_dec_sub28_in3_sel - connect \dec31_dec_sub28_internal_op \dec31_dec_sub28_dec31_dec_sub28_internal_op - connect \dec31_dec_sub28_inv_a \dec31_dec_sub28_dec31_dec_sub28_inv_a - connect \dec31_dec_sub28_inv_out \dec31_dec_sub28_dec31_dec_sub28_inv_out - connect \dec31_dec_sub28_is_32b \dec31_dec_sub28_dec31_dec_sub28_is_32b - connect \dec31_dec_sub28_ldst_len \dec31_dec_sub28_dec31_dec_sub28_ldst_len - connect \dec31_dec_sub28_lk \dec31_dec_sub28_dec31_dec_sub28_lk - connect \dec31_dec_sub28_out_sel \dec31_dec_sub28_dec31_dec_sub28_out_sel - connect \dec31_dec_sub28_rc_sel \dec31_dec_sub28_dec31_dec_sub28_rc_sel - connect \dec31_dec_sub28_rsrv \dec31_dec_sub28_dec31_dec_sub28_rsrv - connect \dec31_dec_sub28_sgl_pipe \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe - connect \dec31_dec_sub28_sgn \dec31_dec_sub28_dec31_dec_sub28_sgn - connect \dec31_dec_sub28_sgn_ext \dec31_dec_sub28_dec31_dec_sub28_sgn_ext - connect \dec31_dec_sub28_upd \dec31_dec_sub28_dec31_dec_sub28_upd - connect \opcode_in \dec31_dec_sub28_opcode_in + attribute \src "libresoc.v:109548.20-109556.4" + cell \dec_cr_out$169 \dec_cr_out + connect \SPR_FXM \dec_SPR_FXM + connect \SPR_internal_op \dec_SPR_internal_op + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \insn_in \dec_cr_out_insn_in + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:16636.18-16662.4" - cell \dec31_dec_sub4 \dec31_dec_sub4 - connect \dec31_dec_sub4_asmcode \dec31_dec_sub4_dec31_dec_sub4_asmcode - connect \dec31_dec_sub4_br \dec31_dec_sub4_dec31_dec_sub4_br - connect \dec31_dec_sub4_cr_in \dec31_dec_sub4_dec31_dec_sub4_cr_in - connect \dec31_dec_sub4_cr_out \dec31_dec_sub4_dec31_dec_sub4_cr_out - connect \dec31_dec_sub4_cry_in \dec31_dec_sub4_dec31_dec_sub4_cry_in - connect \dec31_dec_sub4_cry_out \dec31_dec_sub4_dec31_dec_sub4_cry_out - connect \dec31_dec_sub4_form \dec31_dec_sub4_dec31_dec_sub4_form - connect \dec31_dec_sub4_function_unit \dec31_dec_sub4_dec31_dec_sub4_function_unit - connect \dec31_dec_sub4_in1_sel \dec31_dec_sub4_dec31_dec_sub4_in1_sel - connect \dec31_dec_sub4_in2_sel \dec31_dec_sub4_dec31_dec_sub4_in2_sel - connect \dec31_dec_sub4_in3_sel \dec31_dec_sub4_dec31_dec_sub4_in3_sel - connect \dec31_dec_sub4_internal_op \dec31_dec_sub4_dec31_dec_sub4_internal_op - connect \dec31_dec_sub4_inv_a \dec31_dec_sub4_dec31_dec_sub4_inv_a - connect \dec31_dec_sub4_inv_out \dec31_dec_sub4_dec31_dec_sub4_inv_out - connect \dec31_dec_sub4_is_32b \dec31_dec_sub4_dec31_dec_sub4_is_32b - connect \dec31_dec_sub4_ldst_len \dec31_dec_sub4_dec31_dec_sub4_ldst_len - connect \dec31_dec_sub4_lk \dec31_dec_sub4_dec31_dec_sub4_lk - connect \dec31_dec_sub4_out_sel \dec31_dec_sub4_dec31_dec_sub4_out_sel - connect \dec31_dec_sub4_rc_sel \dec31_dec_sub4_dec31_dec_sub4_rc_sel - connect \dec31_dec_sub4_rsrv \dec31_dec_sub4_dec31_dec_sub4_rsrv - connect \dec31_dec_sub4_sgl_pipe \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe - connect \dec31_dec_sub4_sgn \dec31_dec_sub4_dec31_dec_sub4_sgn - connect \dec31_dec_sub4_sgn_ext \dec31_dec_sub4_dec31_dec_sub4_sgn_ext - connect \dec31_dec_sub4_upd \dec31_dec_sub4_dec31_dec_sub4_upd - connect \opcode_in \dec31_dec_sub4_opcode_in + attribute \src "libresoc.v:109557.16-109561.4" + cell \dec_oe$166 \dec_oe + connect \SPR_OE \dec_SPR_OE + connect \SPR_internal_op \dec_SPR_internal_op + connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:16663.18-16689.4" - cell \dec31_dec_sub8 \dec31_dec_sub8 - connect \dec31_dec_sub8_asmcode \dec31_dec_sub8_dec31_dec_sub8_asmcode - connect \dec31_dec_sub8_br \dec31_dec_sub8_dec31_dec_sub8_br - connect \dec31_dec_sub8_cr_in \dec31_dec_sub8_dec31_dec_sub8_cr_in - connect \dec31_dec_sub8_cr_out \dec31_dec_sub8_dec31_dec_sub8_cr_out - connect \dec31_dec_sub8_cry_in \dec31_dec_sub8_dec31_dec_sub8_cry_in - connect \dec31_dec_sub8_cry_out \dec31_dec_sub8_dec31_dec_sub8_cry_out - connect \dec31_dec_sub8_form \dec31_dec_sub8_dec31_dec_sub8_form - connect \dec31_dec_sub8_function_unit \dec31_dec_sub8_dec31_dec_sub8_function_unit - connect \dec31_dec_sub8_in1_sel \dec31_dec_sub8_dec31_dec_sub8_in1_sel - connect \dec31_dec_sub8_in2_sel \dec31_dec_sub8_dec31_dec_sub8_in2_sel - connect \dec31_dec_sub8_in3_sel \dec31_dec_sub8_dec31_dec_sub8_in3_sel - connect \dec31_dec_sub8_internal_op \dec31_dec_sub8_dec31_dec_sub8_internal_op - connect \dec31_dec_sub8_inv_a \dec31_dec_sub8_dec31_dec_sub8_inv_a - connect \dec31_dec_sub8_inv_out \dec31_dec_sub8_dec31_dec_sub8_inv_out - connect \dec31_dec_sub8_is_32b \dec31_dec_sub8_dec31_dec_sub8_is_32b - connect \dec31_dec_sub8_ldst_len \dec31_dec_sub8_dec31_dec_sub8_ldst_len - connect \dec31_dec_sub8_lk \dec31_dec_sub8_dec31_dec_sub8_lk - connect \dec31_dec_sub8_out_sel \dec31_dec_sub8_dec31_dec_sub8_out_sel - connect \dec31_dec_sub8_rc_sel \dec31_dec_sub8_dec31_dec_sub8_rc_sel - connect \dec31_dec_sub8_rsrv \dec31_dec_sub8_dec31_dec_sub8_rsrv - connect \dec31_dec_sub8_sgl_pipe \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe - connect \dec31_dec_sub8_sgn \dec31_dec_sub8_dec31_dec_sub8_sgn - connect \dec31_dec_sub8_sgn_ext \dec31_dec_sub8_dec31_dec_sub8_sgn_ext - connect \dec31_dec_sub8_upd \dec31_dec_sub8_dec31_dec_sub8_upd - connect \opcode_in \dec31_dec_sub8_opcode_in + attribute \src "libresoc.v:109562.16-109566.4" + cell \dec_rc$165 \dec_rc + connect \SPR_Rc \dec_SPR_Rc + connect \rc \dec_rc_rc + connect \sel_in \dec_rc_sel_in end - attribute \module_not_derived 1 - attribute \src "libresoc.v:16690.18-16716.4" - cell \dec31_dec_sub9 \dec31_dec_sub9 - connect \dec31_dec_sub9_asmcode \dec31_dec_sub9_dec31_dec_sub9_asmcode - connect \dec31_dec_sub9_br \dec31_dec_sub9_dec31_dec_sub9_br - connect \dec31_dec_sub9_cr_in \dec31_dec_sub9_dec31_dec_sub9_cr_in - connect \dec31_dec_sub9_cr_out \dec31_dec_sub9_dec31_dec_sub9_cr_out - connect \dec31_dec_sub9_cry_in \dec31_dec_sub9_dec31_dec_sub9_cry_in - connect \dec31_dec_sub9_cry_out \dec31_dec_sub9_dec31_dec_sub9_cry_out - connect \dec31_dec_sub9_form \dec31_dec_sub9_dec31_dec_sub9_form - connect \dec31_dec_sub9_function_unit \dec31_dec_sub9_dec31_dec_sub9_function_unit - connect \dec31_dec_sub9_in1_sel \dec31_dec_sub9_dec31_dec_sub9_in1_sel - connect \dec31_dec_sub9_in2_sel \dec31_dec_sub9_dec31_dec_sub9_in2_sel - connect \dec31_dec_sub9_in3_sel \dec31_dec_sub9_dec31_dec_sub9_in3_sel - connect \dec31_dec_sub9_internal_op \dec31_dec_sub9_dec31_dec_sub9_internal_op - connect \dec31_dec_sub9_inv_a \dec31_dec_sub9_dec31_dec_sub9_inv_a - connect \dec31_dec_sub9_inv_out \dec31_dec_sub9_dec31_dec_sub9_inv_out - connect \dec31_dec_sub9_is_32b \dec31_dec_sub9_dec31_dec_sub9_is_32b - connect \dec31_dec_sub9_ldst_len \dec31_dec_sub9_dec31_dec_sub9_ldst_len - connect \dec31_dec_sub9_lk \dec31_dec_sub9_dec31_dec_sub9_lk - connect \dec31_dec_sub9_out_sel \dec31_dec_sub9_dec31_dec_sub9_out_sel - connect \dec31_dec_sub9_rc_sel \dec31_dec_sub9_dec31_dec_sub9_rc_sel - connect \dec31_dec_sub9_rsrv \dec31_dec_sub9_dec31_dec_sub9_rsrv - connect \dec31_dec_sub9_sgl_pipe \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe - connect \dec31_dec_sub9_sgn \dec31_dec_sub9_dec31_dec_sub9_sgn - connect \dec31_dec_sub9_sgn_ext \dec31_dec_sub9_dec31_dec_sub9_sgn_ext - connect \dec31_dec_sub9_upd \dec31_dec_sub9_dec31_dec_sub9_upd - connect \opcode_in \dec31_dec_sub9_opcode_in + connect \SPR__is_32bit \dec_SPR_is_32b + connect \SPR__fn_unit \dec_SPR_function_unit + connect \SPR__insn_type \dec_SPR_internal_op + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_SPR_cr_out + connect \dec_cr_in_sel_in \dec_SPR_cr_in + connect \dec_oe_sel_in \dec_SPR_rc_sel + connect \dec_rc_sel_in \dec_SPR_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \SPR__insn \dec_opcode_in +end +attribute \src "libresoc.v:109584.1-110089.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a" +attribute \generator "nMigen" +module \dec_a + attribute \src "libresoc.v:110018.3-110053.6" + wire width 3 $0\fast_a[2:0] + attribute \src "libresoc.v:110018.3-110053.6" + wire $0\fast_a_ok[0:0] + attribute \src "libresoc.v:109585.7-109585.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:109986.3-110001.6" + wire width 5 $0\reg_a[4:0] + attribute \src "libresoc.v:110002.3-110017.6" + wire $0\reg_a_ok[0:0] + attribute \src "libresoc.v:110054.3-110064.6" + wire width 10 $0\spr[9:0] + attribute \src "libresoc.v:110076.3-110087.6" + wire width 10 $0\spr_a[9:0] + attribute \src "libresoc.v:110076.3-110087.6" + wire $0\spr_a_ok[0:0] + attribute \src "libresoc.v:110065.3-110075.6" + wire width 10 $0\sprmap_spr_i[9:0] + attribute \src "libresoc.v:110018.3-110053.6" + wire width 3 $1\fast_a[2:0] + attribute \src "libresoc.v:110018.3-110053.6" + wire $1\fast_a_ok[0:0] + attribute \src "libresoc.v:109986.3-110001.6" + wire width 5 $1\reg_a[4:0] + attribute \src "libresoc.v:110002.3-110017.6" + wire $1\reg_a_ok[0:0] + attribute \src "libresoc.v:110054.3-110064.6" + wire width 10 $1\spr[9:0] + attribute \src "libresoc.v:110076.3-110087.6" + wire width 10 $1\spr_a[9:0] + attribute \src "libresoc.v:110076.3-110087.6" + wire $1\spr_a_ok[0:0] + attribute \src "libresoc.v:110065.3-110075.6" + wire width 10 $1\sprmap_spr_i[9:0] + attribute \src "libresoc.v:110018.3-110053.6" + wire width 3 $2\fast_a[2:0] + attribute \src "libresoc.v:110018.3-110053.6" + wire $2\fast_a_ok[0:0] + attribute \src "libresoc.v:109986.3-110001.6" + wire width 5 $2\reg_a[4:0] + attribute \src "libresoc.v:110002.3-110017.6" + wire $2\reg_a_ok[0:0] + attribute \src "libresoc.v:110018.3-110053.6" + wire width 3 $3\fast_a[2:0] + attribute \src "libresoc.v:110018.3-110053.6" + wire $3\fast_a_ok[0:0] + attribute \src "libresoc.v:109970.18-109970.110" + wire $and$libresoc.v:109970$4230_Y + attribute \src "libresoc.v:109975.18-109975.113" + wire $and$libresoc.v:109975$4235_Y + attribute \src "libresoc.v:109978.17-109978.107" + wire $and$libresoc.v:109978$4238_Y + attribute \src "libresoc.v:109965.18-109965.112" + wire $eq$libresoc.v:109965$4225_Y + attribute \src "libresoc.v:109966.18-109966.112" + wire $eq$libresoc.v:109966$4226_Y + attribute \src "libresoc.v:109967.18-109967.112" + wire $eq$libresoc.v:109967$4227_Y + attribute \src "libresoc.v:109969.17-109969.111" + wire $eq$libresoc.v:109969$4229_Y + attribute \src "libresoc.v:109972.18-109972.112" + wire $eq$libresoc.v:109972$4232_Y + attribute \src "libresoc.v:109976.17-109976.111" + wire $eq$libresoc.v:109976$4236_Y + attribute \src "libresoc.v:109968.18-109968.109" + wire $ne$libresoc.v:109968$4228_Y + attribute \src "libresoc.v:109977.17-109977.108" + wire $ne$libresoc.v:109977$4237_Y + attribute \src "libresoc.v:109973.18-109973.105" + wire $not$libresoc.v:109973$4233_Y + attribute \src "libresoc.v:109974.18-109974.108" + wire $not$libresoc.v:109974$4234_Y + attribute \src "libresoc.v:109964.17-109964.107" + wire $or$libresoc.v:109964$4224_Y + attribute \src "libresoc.v:109971.18-109971.110" + wire $or$libresoc.v:109971$4231_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:119" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 10 \BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 9 \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 8 \RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 10 input 11 \SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 input 12 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 6 \fast_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 7 \fast_a_ok + attribute \src "libresoc.v:109585.7-109585.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 input 13 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" + wire width 5 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 output 2 \reg_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \reg_a_ok + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:133" + wire width 10 \spr + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 output 4 \spr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 5 \spr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \sprmap_fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \sprmap_fast_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62" + wire width 10 \sprmap_spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 \sprmap_spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \sprmap_spr_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + cell $and $and$libresoc.v:109970$4230 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$15 + connect \B \$17 + connect \Y $and$libresoc.v:109970$4230_Y end - attribute \src "libresoc.v:11832.7-11832.20" - process $proc$libresoc.v:11832$406 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + cell $and $and$libresoc.v:109975$4235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \XL_XO [9] + connect \B \$27 + connect \Y $and$libresoc.v:109975$4235_Y end - attribute \src "libresoc.v:16717.3-16777.6" - process $proc$libresoc.v:16717$382 - assign { } { } - assign { } { } - assign $0\dec31_function_unit[11:0] $1\dec31_function_unit[11:0] - attribute \src "libresoc.v:16718.5-16718.29" - switch \initial - attribute \src "libresoc.v:16718.9-16718.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub10_dec31_dec_sub10_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub28_dec31_dec_sub28_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub0_dec31_dec_sub0_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub26_dec31_dec_sub26_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub19_dec31_dec_sub19_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub22_dec31_dec_sub22_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub9_dec31_dec_sub9_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub11_dec31_dec_sub11_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub27_dec31_dec_sub27_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub15_dec31_dec_sub15_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub20_dec31_dec_sub20_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub21_dec31_dec_sub21_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub23_dec31_dec_sub23_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub16_dec31_dec_sub16_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub18_dec31_dec_sub18_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub8_dec31_dec_sub8_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub24_dec31_dec_sub24_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub4_dec31_dec_sub4_function_unit - case - assign $1\dec31_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_function_unit $0\dec31_function_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + cell $and $and$libresoc.v:109978$4238 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \$5 + connect \Y $and$libresoc.v:109978$4238_Y end - attribute \src "libresoc.v:16778.3-16838.6" - process $proc$libresoc.v:16778$383 - assign { } { } - assign { } { } - assign $0\dec31_internal_op[6:0] $1\dec31_internal_op[6:0] - attribute \src "libresoc.v:16779.5-16779.29" - switch \initial - attribute \src "libresoc.v:16779.9-16779.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub10_dec31_dec_sub10_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub28_dec31_dec_sub28_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub0_dec31_dec_sub0_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub26_dec31_dec_sub26_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub19_dec31_dec_sub19_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub22_dec31_dec_sub22_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub9_dec31_dec_sub9_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub11_dec31_dec_sub11_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub27_dec31_dec_sub27_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub15_dec31_dec_sub15_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub20_dec31_dec_sub20_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub21_dec31_dec_sub21_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub23_dec31_dec_sub23_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub16_dec31_dec_sub16_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub18_dec31_dec_sub18_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub8_dec31_dec_sub8_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub24_dec31_dec_sub24_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub4_dec31_dec_sub4_internal_op - case - assign $1\dec31_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_internal_op $0\dec31_internal_op[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109" + cell $eq $eq$libresoc.v:109965$4225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'100 + connect \Y $eq$libresoc.v:109965$4225_Y end - attribute \src "libresoc.v:16839.3-16899.6" - process $proc$libresoc.v:16839$384 - assign { } { } - assign { } { } - assign $0\dec31_form[4:0] $1\dec31_form[4:0] - attribute \src "libresoc.v:16840.5-16840.29" - switch \initial - attribute \src "libresoc.v:16840.9-16840.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub10_dec31_dec_sub10_form - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub28_dec31_dec_sub28_form - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub0_dec31_dec_sub0_form - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub26_dec31_dec_sub26_form - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub19_dec31_dec_sub19_form - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub22_dec31_dec_sub22_form - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub9_dec31_dec_sub9_form - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub11_dec31_dec_sub11_form - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub27_dec31_dec_sub27_form - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub15_dec31_dec_sub15_form - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub20_dec31_dec_sub20_form - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub21_dec31_dec_sub21_form - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub23_dec31_dec_sub23_form - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub16_dec31_dec_sub16_form - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub18_dec31_dec_sub18_form - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub8_dec31_dec_sub8_form - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub24_dec31_dec_sub24_form - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub4_dec31_dec_sub4_form - case - assign $1\dec31_form[4:0] 5'00000 - end - sync always - update \dec31_form $0\dec31_form[4:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102" + cell $eq $eq$libresoc.v:109966$4226 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'001 + connect \Y $eq$libresoc.v:109966$4226_Y end - attribute \src "libresoc.v:16900.3-16960.6" - process $proc$libresoc.v:16900$385 - assign { } { } - assign { } { } - assign $0\dec31_asmcode[7:0] $1\dec31_asmcode[7:0] - attribute \src "libresoc.v:16901.5-16901.29" - switch \initial - attribute \src "libresoc.v:16901.9-16901.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub10_dec31_dec_sub10_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub28_dec31_dec_sub28_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub0_dec31_dec_sub0_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub26_dec31_dec_sub26_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub19_dec31_dec_sub19_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub22_dec31_dec_sub22_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub9_dec31_dec_sub9_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub11_dec31_dec_sub11_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub27_dec31_dec_sub27_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub15_dec31_dec_sub15_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub20_dec31_dec_sub20_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub21_dec31_dec_sub21_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub23_dec31_dec_sub23_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub16_dec31_dec_sub16_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub18_dec31_dec_sub18_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub8_dec31_dec_sub8_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub24_dec31_dec_sub24_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub4_dec31_dec_sub4_asmcode - case - assign $1\dec31_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_asmcode $0\dec31_asmcode[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103" + cell $eq $eq$libresoc.v:109967$4227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'010 + connect \Y $eq$libresoc.v:109967$4227_Y end - attribute \src "libresoc.v:16961.3-17021.6" - process $proc$libresoc.v:16961$386 - assign { } { } - assign { } { } - assign $0\dec31_in1_sel[2:0] $1\dec31_in1_sel[2:0] - attribute \src "libresoc.v:16962.5-16962.29" - switch \initial - attribute \src "libresoc.v:16962.9-16962.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub10_dec31_dec_sub10_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub28_dec31_dec_sub28_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub0_dec31_dec_sub0_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub26_dec31_dec_sub26_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub19_dec31_dec_sub19_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub22_dec31_dec_sub22_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub9_dec31_dec_sub9_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub11_dec31_dec_sub11_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub27_dec31_dec_sub27_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub15_dec31_dec_sub15_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub20_dec31_dec_sub20_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub21_dec31_dec_sub21_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub23_dec31_dec_sub23_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub16_dec31_dec_sub16_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub18_dec31_dec_sub18_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub8_dec31_dec_sub8_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub24_dec31_dec_sub24_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub4_dec31_dec_sub4_in1_sel - case - assign $1\dec31_in1_sel[2:0] 3'000 - end - sync always - update \dec31_in1_sel $0\dec31_in1_sel[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102" + cell $eq $eq$libresoc.v:109969$4229 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'001 + connect \Y $eq$libresoc.v:109969$4229_Y end - attribute \src "libresoc.v:17022.3-17082.6" - process $proc$libresoc.v:17022$387 - assign { } { } - assign { } { } - assign $0\dec31_in2_sel[3:0] $1\dec31_in2_sel[3:0] - attribute \src "libresoc.v:17023.5-17023.29" - switch \initial - attribute \src "libresoc.v:17023.9-17023.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub10_dec31_dec_sub10_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub28_dec31_dec_sub28_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub0_dec31_dec_sub0_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub26_dec31_dec_sub26_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub19_dec31_dec_sub19_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub22_dec31_dec_sub22_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub9_dec31_dec_sub9_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub11_dec31_dec_sub11_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub27_dec31_dec_sub27_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub15_dec31_dec_sub15_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub20_dec31_dec_sub20_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub21_dec31_dec_sub21_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub23_dec31_dec_sub23_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub16_dec31_dec_sub16_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub18_dec31_dec_sub18_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub8_dec31_dec_sub8_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub24_dec31_dec_sub24_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub4_dec31_dec_sub4_in2_sel - case - assign $1\dec31_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_in2_sel $0\dec31_in2_sel[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109" + cell $eq $eq$libresoc.v:109972$4232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'100 + connect \Y $eq$libresoc.v:109972$4232_Y end - attribute \src "libresoc.v:17083.3-17143.6" - process $proc$libresoc.v:17083$388 - assign { } { } - assign { } { } - assign $0\dec31_in3_sel[1:0] $1\dec31_in3_sel[1:0] - attribute \src "libresoc.v:17084.5-17084.29" - switch \initial - attribute \src "libresoc.v:17084.9-17084.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_in3_sel - case - assign $1\dec31_in3_sel[1:0] 2'00 - end - sync always - update \dec31_in3_sel $0\dec31_in3_sel[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103" + cell $eq $eq$libresoc.v:109976$4236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'010 + connect \Y $eq$libresoc.v:109976$4236_Y end - attribute \src "libresoc.v:17144.3-17204.6" - process $proc$libresoc.v:17144$389 - assign { } { } - assign { } { } - assign $0\dec31_out_sel[1:0] $1\dec31_out_sel[1:0] - attribute \src "libresoc.v:17145.5-17145.29" - switch \initial - attribute \src "libresoc.v:17145.9-17145.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_out_sel - case - assign $1\dec31_out_sel[1:0] 2'00 - end - sync always - update \dec31_out_sel $0\dec31_out_sel[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + cell $ne $ne$libresoc.v:109968$4228 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \ra + connect \B 5'00000 + connect \Y $ne$libresoc.v:109968$4228_Y end - attribute \src "libresoc.v:17205.3-17265.6" - process $proc$libresoc.v:17205$390 - assign { } { } - assign { } { } - assign $0\dec31_cr_in[2:0] $1\dec31_cr_in[2:0] - attribute \src "libresoc.v:17206.5-17206.29" - switch \initial - attribute \src "libresoc.v:17206.9-17206.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub10_dec31_dec_sub10_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub28_dec31_dec_sub28_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub0_dec31_dec_sub0_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub26_dec31_dec_sub26_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub19_dec31_dec_sub19_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub22_dec31_dec_sub22_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub9_dec31_dec_sub9_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub11_dec31_dec_sub11_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub27_dec31_dec_sub27_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub15_dec31_dec_sub15_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub20_dec31_dec_sub20_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub21_dec31_dec_sub21_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub23_dec31_dec_sub23_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub16_dec31_dec_sub16_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub18_dec31_dec_sub18_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub8_dec31_dec_sub8_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub24_dec31_dec_sub24_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub4_dec31_dec_sub4_cr_in - case - assign $1\dec31_cr_in[2:0] 3'000 - end - sync always - update \dec31_cr_in $0\dec31_cr_in[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + cell $ne $ne$libresoc.v:109977$4237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \ra + connect \B 5'00000 + connect \Y $ne$libresoc.v:109977$4237_Y end - attribute \src "libresoc.v:17266.3-17326.6" - process $proc$libresoc.v:17266$391 - assign { } { } - assign { } { } - assign $0\dec31_cr_out[2:0] $1\dec31_cr_out[2:0] - attribute \src "libresoc.v:17267.5-17267.29" - switch \initial - attribute \src "libresoc.v:17267.9-17267.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub10_dec31_dec_sub10_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub28_dec31_dec_sub28_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub0_dec31_dec_sub0_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub26_dec31_dec_sub26_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub19_dec31_dec_sub19_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub22_dec31_dec_sub22_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub9_dec31_dec_sub9_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub11_dec31_dec_sub11_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub27_dec31_dec_sub27_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub15_dec31_dec_sub15_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub20_dec31_dec_sub20_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub21_dec31_dec_sub21_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub23_dec31_dec_sub23_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub16_dec31_dec_sub16_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub18_dec31_dec_sub18_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub8_dec31_dec_sub8_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub24_dec31_dec_sub24_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub4_dec31_dec_sub4_cr_out - case - assign $1\dec31_cr_out[2:0] 3'000 - end - sync always - update \dec31_cr_out $0\dec31_cr_out[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:119" + cell $not $not$libresoc.v:109973$4233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \BO [2] + connect \Y $not$libresoc.v:109973$4233_Y end - attribute \src "libresoc.v:17327.3-17387.6" - process $proc$libresoc.v:17327$392 - assign { } { } - assign { } { } - assign $0\dec31_ldst_len[3:0] $1\dec31_ldst_len[3:0] - attribute \src "libresoc.v:17328.5-17328.29" - switch \initial - attribute \src "libresoc.v:17328.9-17328.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub10_dec31_dec_sub10_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub28_dec31_dec_sub28_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub0_dec31_dec_sub0_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub26_dec31_dec_sub26_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub19_dec31_dec_sub19_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub22_dec31_dec_sub22_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub9_dec31_dec_sub9_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub11_dec31_dec_sub11_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub27_dec31_dec_sub27_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub15_dec31_dec_sub15_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub20_dec31_dec_sub20_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub21_dec31_dec_sub21_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub23_dec31_dec_sub23_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub16_dec31_dec_sub16_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub18_dec31_dec_sub18_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub8_dec31_dec_sub8_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub24_dec31_dec_sub24_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub4_dec31_dec_sub4_ldst_len - case - assign $1\dec31_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_ldst_len $0\dec31_ldst_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + cell $not $not$libresoc.v:109974$4234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \XL_XO [5] + connect \Y $not$libresoc.v:109974$4234_Y end - attribute \src "libresoc.v:17388.3-17448.6" - process $proc$libresoc.v:17388$393 - assign { } { } - assign { } { } - assign $0\dec31_upd[1:0] $1\dec31_upd[1:0] - attribute \src "libresoc.v:17389.5-17389.29" - switch \initial - attribute \src "libresoc.v:17389.9-17389.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub10_dec31_dec_sub10_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub28_dec31_dec_sub28_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub0_dec31_dec_sub0_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub26_dec31_dec_sub26_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub19_dec31_dec_sub19_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub22_dec31_dec_sub22_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub9_dec31_dec_sub9_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub11_dec31_dec_sub11_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub27_dec31_dec_sub27_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub15_dec31_dec_sub15_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub20_dec31_dec_sub20_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub21_dec31_dec_sub21_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub23_dec31_dec_sub23_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub16_dec31_dec_sub16_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub18_dec31_dec_sub18_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub8_dec31_dec_sub8_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub24_dec31_dec_sub24_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub4_dec31_dec_sub4_upd - case - assign $1\dec31_upd[1:0] 2'00 - end - sync always - update \dec31_upd $0\dec31_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + cell $or $or$libresoc.v:109964$4224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \$7 + connect \Y $or$libresoc.v:109964$4224_Y end - attribute \src "libresoc.v:17449.3-17509.6" - process $proc$libresoc.v:17449$394 - assign { } { } - assign { } { } - assign $0\dec31_rc_sel[1:0] $1\dec31_rc_sel[1:0] - attribute \src "libresoc.v:17450.5-17450.29" - switch \initial - attribute \src "libresoc.v:17450.9-17450.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_rc_sel - case - assign $1\dec31_rc_sel[1:0] 2'00 - end - sync always - update \dec31_rc_sel $0\dec31_rc_sel[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + cell $or $or$libresoc.v:109971$4231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$13 + connect \B \$19 + connect \Y $or$libresoc.v:109971$4231_Y end - attribute \src "libresoc.v:17510.3-17570.6" - process $proc$libresoc.v:17510$395 - assign { } { } + attribute \module_not_derived 1 + attribute \src "libresoc.v:109979.10-109985.4" + cell \sprmap \sprmap + connect \fast_o \sprmap_fast_o + connect \fast_o_ok \sprmap_fast_o_ok + connect \spr_i \sprmap_spr_i + connect \spr_o \sprmap_spr_o + connect \spr_o_ok \sprmap_spr_o_ok + end + attribute \src "libresoc.v:109585.7-109585.20" + process $proc$libresoc.v:109585$4245 assign { } { } - assign $0\dec31_cry_in[1:0] $1\dec31_cry_in[1:0] - attribute \src "libresoc.v:17511.5-17511.29" - switch \initial - attribute \src "libresoc.v:17511.9-17511.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub10_dec31_dec_sub10_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub28_dec31_dec_sub28_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub0_dec31_dec_sub0_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub26_dec31_dec_sub26_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub19_dec31_dec_sub19_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub22_dec31_dec_sub22_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub9_dec31_dec_sub9_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub11_dec31_dec_sub11_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub27_dec31_dec_sub27_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub15_dec31_dec_sub15_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub20_dec31_dec_sub20_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub21_dec31_dec_sub21_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub23_dec31_dec_sub23_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub16_dec31_dec_sub16_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub18_dec31_dec_sub18_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub8_dec31_dec_sub8_cry_in + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:109986.3-110001.6" + process $proc$libresoc.v:109986$4239 + assign { } { } + assign { } { } + assign { } { } + assign $0\reg_a[4:0] $2\reg_a[4:0] + attribute \src "libresoc.v:109987.5-109987.29" + switch \initial + attribute \src "libresoc.v:109987.9-109987.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + switch \$9 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 1'1 assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub24_dec31_dec_sub24_cry_in + assign $1\reg_a[4:0] \ra + case + assign $1\reg_a[4:0] 5'00000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109" + switch \$11 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 1'1 assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub4_dec31_dec_sub4_cry_in + assign $2\reg_a[4:0] \RS case - assign $1\dec31_cry_in[1:0] 2'00 + assign $2\reg_a[4:0] $1\reg_a[4:0] end sync always - update \dec31_cry_in $0\dec31_cry_in[1:0] + update \reg_a $0\reg_a[4:0] end - attribute \src "libresoc.v:17571.3-17631.6" - process $proc$libresoc.v:17571$396 + attribute \src "libresoc.v:110002.3-110017.6" + process $proc$libresoc.v:110002$4240 assign { } { } assign { } { } - assign $0\dec31_inv_a[0:0] $1\dec31_inv_a[0:0] - attribute \src "libresoc.v:17572.5-17572.29" + assign { } { } + assign $0\reg_a_ok[0:0] $2\reg_a_ok[0:0] + attribute \src "libresoc.v:110003.5-110003.29" switch \initial - attribute \src "libresoc.v:17572.9-17572.17" + attribute \src "libresoc.v:110003.9-110003.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub10_dec31_dec_sub10_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub28_dec31_dec_sub28_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub0_dec31_dec_sub0_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub26_dec31_dec_sub26_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub19_dec31_dec_sub19_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub22_dec31_dec_sub22_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub9_dec31_dec_sub9_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub11_dec31_dec_sub11_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub27_dec31_dec_sub27_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub15_dec31_dec_sub15_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub20_dec31_dec_sub20_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub21_dec31_dec_sub21_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub23_dec31_dec_sub23_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub16_dec31_dec_sub16_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub18_dec31_dec_sub18_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub8_dec31_dec_sub8_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + switch \$21 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 1'1 assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub24_dec31_dec_sub24_inv_a + assign $1\reg_a_ok[0:0] 1'1 + case + assign $1\reg_a_ok[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109" + switch \$23 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 1'1 assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub4_dec31_dec_sub4_inv_a + assign $2\reg_a_ok[0:0] 1'1 case - assign $1\dec31_inv_a[0:0] 1'0 + assign $2\reg_a_ok[0:0] $1\reg_a_ok[0:0] end sync always - update \dec31_inv_a $0\dec31_inv_a[0:0] + update \reg_a_ok $0\reg_a_ok[0:0] end - attribute \src "libresoc.v:17632.3-17692.6" - process $proc$libresoc.v:17632$397 + attribute \src "libresoc.v:110018.3-110053.6" + process $proc$libresoc.v:110018$4241 assign { } { } assign { } { } - assign $0\dec31_inv_out[0:0] $1\dec31_inv_out[0:0] - attribute \src "libresoc.v:17633.5-17633.29" + assign { } { } + assign { } { } + assign $0\fast_a[2:0] $1\fast_a[2:0] + assign $0\fast_a_ok[0:0] $1\fast_a_ok[0:0] + attribute \src "libresoc.v:110019.5-110019.29" switch \initial - attribute \src "libresoc.v:17633.9-17633.17" + attribute \src "libresoc.v:110019.9-110019.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub10_dec31_dec_sub10_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub28_dec31_dec_sub28_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub0_dec31_dec_sub0_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub26_dec31_dec_sub26_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub19_dec31_dec_sub19_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub22_dec31_dec_sub22_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub9_dec31_dec_sub9_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub11_dec31_dec_sub11_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub27_dec31_dec_sub27_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub15_dec31_dec_sub15_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub20_dec31_dec_sub20_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub21_dec31_dec_sub21_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115" + switch \internal_op attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 7'0000111 assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub23_dec31_dec_sub23_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub16_dec31_dec_sub16_inv_out + assign $1\fast_a[2:0] $2\fast_a[2:0] + assign $1\fast_a_ok[0:0] $2\fast_a_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:119" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $2\fast_a[2:0] 3'000 + assign $2\fast_a_ok[0:0] 1'1 + case + assign $2\fast_a[2:0] 3'000 + assign $2\fast_a_ok[0:0] 1'0 + end attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 7'0001000 assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub18_dec31_dec_sub18_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub8_dec31_dec_sub8_inv_out + assign $1\fast_a[2:0] $3\fast_a[2:0] + assign $1\fast_a_ok[0:0] $3\fast_a_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $3\fast_a[2:0] 3'000 + assign $3\fast_a_ok[0:0] 1'1 + case + assign $3\fast_a[2:0] 3'000 + assign $3\fast_a_ok[0:0] 1'0 + end attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 7'0101110 assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub24_dec31_dec_sub24_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub4_dec31_dec_sub4_inv_out + assign { $1\fast_a_ok[0:0] $1\fast_a[2:0] } { \sprmap_fast_o_ok \sprmap_fast_o } case - assign $1\dec31_inv_out[0:0] 1'0 + assign $1\fast_a[2:0] 3'000 + assign $1\fast_a_ok[0:0] 1'0 end sync always - update \dec31_inv_out $0\dec31_inv_out[0:0] + update \fast_a $0\fast_a[2:0] + update \fast_a_ok $0\fast_a_ok[0:0] end - attribute \src "libresoc.v:17693.3-17753.6" - process $proc$libresoc.v:17693$398 + attribute \src "libresoc.v:110054.3-110064.6" + process $proc$libresoc.v:110054$4242 assign { } { } assign { } { } - assign $0\dec31_cry_out[0:0] $1\dec31_cry_out[0:0] - attribute \src "libresoc.v:17694.5-17694.29" + assign $0\spr[9:0] $1\spr[9:0] + attribute \src "libresoc.v:110055.5-110055.29" switch \initial - attribute \src "libresoc.v:17694.9-17694.17" + attribute \src "libresoc.v:110055.9-110055.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub10_dec31_dec_sub10_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub28_dec31_dec_sub28_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub0_dec31_dec_sub0_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub26_dec31_dec_sub26_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub19_dec31_dec_sub19_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub22_dec31_dec_sub22_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub9_dec31_dec_sub9_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub11_dec31_dec_sub11_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub27_dec31_dec_sub27_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub15_dec31_dec_sub15_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub20_dec31_dec_sub20_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub21_dec31_dec_sub21_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub23_dec31_dec_sub23_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub16_dec31_dec_sub16_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub18_dec31_dec_sub18_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub8_dec31_dec_sub8_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub24_dec31_dec_sub24_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115" + switch \internal_op attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 7'0101110 assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub4_dec31_dec_sub4_cry_out + assign $1\spr[9:0] { \SPR [4:0] \SPR [9:5] } case - assign $1\dec31_cry_out[0:0] 1'0 + assign $1\spr[9:0] 10'0000000000 end sync always - update \dec31_cry_out $0\dec31_cry_out[0:0] + update \spr $0\spr[9:0] end - attribute \src "libresoc.v:17754.3-17814.6" - process $proc$libresoc.v:17754$399 + attribute \src "libresoc.v:110065.3-110075.6" + process $proc$libresoc.v:110065$4243 assign { } { } assign { } { } - assign $0\dec31_br[0:0] $1\dec31_br[0:0] - attribute \src "libresoc.v:17755.5-17755.29" + assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] + attribute \src "libresoc.v:110066.5-110066.29" switch \initial - attribute \src "libresoc.v:17755.9-17755.17" + attribute \src "libresoc.v:110066.9-110066.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub10_dec31_dec_sub10_br - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub28_dec31_dec_sub28_br - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub0_dec31_dec_sub0_br - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub26_dec31_dec_sub26_br - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub19_dec31_dec_sub19_br - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub22_dec31_dec_sub22_br - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub9_dec31_dec_sub9_br - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub11_dec31_dec_sub11_br - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub27_dec31_dec_sub27_br - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub15_dec31_dec_sub15_br - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub20_dec31_dec_sub20_br - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub21_dec31_dec_sub21_br - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub23_dec31_dec_sub23_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115" + switch \internal_op attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 7'0101110 assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub16_dec31_dec_sub16_br + assign $1\sprmap_spr_i[9:0] \spr + case + assign $1\sprmap_spr_i[9:0] 10'0000000000 + end + sync always + update \sprmap_spr_i $0\sprmap_spr_i[9:0] + end + attribute \src "libresoc.v:110076.3-110087.6" + process $proc$libresoc.v:110076$4244 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\spr_a[9:0] $1\spr_a[9:0] + assign $0\spr_a_ok[0:0] $1\spr_a_ok[0:0] + attribute \src "libresoc.v:110077.5-110077.29" + switch \initial + attribute \src "libresoc.v:110077.9-110077.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115" + switch \internal_op attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 7'0101110 assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub18_dec31_dec_sub18_br - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub8_dec31_dec_sub8_br + assign { $1\spr_a_ok[0:0] $1\spr_a[9:0] } { \sprmap_spr_o_ok \sprmap_spr_o } + case + assign $1\spr_a[9:0] 10'0000000000 + assign $1\spr_a_ok[0:0] 1'0 + end + sync always + update \spr_a $0\spr_a[9:0] + update \spr_a_ok $0\spr_a_ok[0:0] + end + connect \$9 $or$libresoc.v:109964$4224_Y + connect \$11 $eq$libresoc.v:109965$4225_Y + connect \$13 $eq$libresoc.v:109966$4226_Y + connect \$15 $eq$libresoc.v:109967$4227_Y + connect \$17 $ne$libresoc.v:109968$4228_Y + connect \$1 $eq$libresoc.v:109969$4229_Y + connect \$19 $and$libresoc.v:109970$4230_Y + connect \$21 $or$libresoc.v:109971$4231_Y + connect \$23 $eq$libresoc.v:109972$4232_Y + connect \$25 $not$libresoc.v:109973$4233_Y + connect \$27 $not$libresoc.v:109974$4234_Y + connect \$29 $and$libresoc.v:109975$4235_Y + connect \$3 $eq$libresoc.v:109976$4236_Y + connect \$5 $ne$libresoc.v:109977$4237_Y + connect \$7 $and$libresoc.v:109978$4238_Y + connect \ra \RA +end +attribute \src "libresoc.v:110093.1-110130.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_ai" +attribute \generator "nMigen" +module \dec_ai + attribute \src "libresoc.v:110119.3-110128.6" + wire $0\immz_out[0:0] + attribute \src "libresoc.v:110094.7-110094.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:110119.3-110128.6" + wire $1\immz_out[0:0] + attribute \src "libresoc.v:110118.17-110118.107" + wire $and$libresoc.v:110118$4248_Y + attribute \src "libresoc.v:110116.17-110116.111" + wire $eq$libresoc.v:110116$4246_Y + attribute \src "libresoc.v:110117.17-110117.108" + wire $eq$libresoc.v:110117$4247_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 2 \ALU_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + wire output 1 \immz_out + attribute \src "libresoc.v:110094.7-110094.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:159" + wire width 5 \ra + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" + wire width 3 input 3 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" + cell $and $and$libresoc.v:110118$4248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \$3 + connect \Y $and$libresoc.v:110118$4248_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" + cell $eq $eq$libresoc.v:110116$4246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'010 + connect \Y $eq$libresoc.v:110116$4246_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" + cell $eq $eq$libresoc.v:110117$4247 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \ra + connect \B 5'00000 + connect \Y $eq$libresoc.v:110117$4247_Y + end + attribute \src "libresoc.v:110094.7-110094.20" + process $proc$libresoc.v:110094$4250 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:110119.3-110128.6" + process $proc$libresoc.v:110119$4249 + assign { } { } + assign { } { } + assign $0\immz_out[0:0] $1\immz_out[0:0] + attribute \src "libresoc.v:110120.5-110120.29" + switch \initial + attribute \src "libresoc.v:110120.9-110120.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" + switch \$5 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 1'1 assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub24_dec31_dec_sub24_br + assign $1\immz_out[0:0] 1'1 + case + assign $1\immz_out[0:0] 1'0 + end + sync always + update \immz_out $0\immz_out[0:0] + end + connect \$1 $eq$libresoc.v:110116$4246_Y + connect \$3 $eq$libresoc.v:110117$4247_Y + connect \$5 $and$libresoc.v:110118$4248_Y + connect \ra \ALU_RA +end +attribute \src "libresoc.v:110134.1-110171.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_ai" +attribute \generator "nMigen" +module \dec_ai$162 + attribute \src "libresoc.v:110160.3-110169.6" + wire $0\immz_out[0:0] + attribute \src "libresoc.v:110135.7-110135.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:110160.3-110169.6" + wire $1\immz_out[0:0] + attribute \src "libresoc.v:110159.17-110159.107" + wire $and$libresoc.v:110159$4253_Y + attribute \src "libresoc.v:110157.17-110157.111" + wire $eq$libresoc.v:110157$4251_Y + attribute \src "libresoc.v:110158.17-110158.108" + wire $eq$libresoc.v:110158$4252_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 2 \LOGICAL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + wire output 1 \immz_out + attribute \src "libresoc.v:110135.7-110135.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:159" + wire width 5 \ra + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" + wire width 3 input 3 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" + cell $and $and$libresoc.v:110159$4253 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \$3 + connect \Y $and$libresoc.v:110159$4253_Y + end + attribute \src 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"RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:178" + wire width 4 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + cell $eq $eq$libresoc.v:110378$4266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0001000 + connect \Y $eq$libresoc.v:110378$4266_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + cell $eq $eq$libresoc.v:110380$4268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0001000 + connect \Y $eq$libresoc.v:110380$4268_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204" + cell $not $not$libresoc.v:110379$4267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \XL_XO [9] + connect \Y $not$libresoc.v:110379$4267_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204" + cell $not $not$libresoc.v:110381$4269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \XL_XO [9] + connect \Y $not$libresoc.v:110381$4269_Y + end + attribute \src "libresoc.v:110258.7-110258.20" + process $proc$libresoc.v:110258$4274 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:110382.3-110396.6" + process $proc$libresoc.v:110382$4270 + assign { } { } + assign { } { } + assign $0\reg_b[4:0] $1\reg_b[4:0] + attribute \src "libresoc.v:110383.5-110383.29" + switch \initial + attribute \src "libresoc.v:110383.9-110383.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 4'0001 assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgn_ext + assign $1\reg_b[4:0] \RB attribute \src "libresoc.v:0.0-0.0" - case 5'11010 + case 4'1101 assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgn_ext + assign $1\reg_b[4:0] \RS + case + assign $1\reg_b[4:0] 5'00000 + end + sync always + update \reg_b $0\reg_b[4:0] + end + attribute \src "libresoc.v:110397.3-110411.6" + process $proc$libresoc.v:110397$4271 + assign { } { } + assign { } { } + assign $0\reg_b_ok[0:0] $1\reg_b_ok[0:0] + attribute \src "libresoc.v:110398.5-110398.29" + switch \initial + attribute \src "libresoc.v:110398.9-110398.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10011 + case 4'0001 assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgn_ext + assign $1\reg_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 4'1101 assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgn_ext + assign $1\reg_b_ok[0:0] 1'1 + case + assign $1\reg_b_ok[0:0] 1'0 + end + sync always + update \reg_b_ok $0\reg_b_ok[0:0] + end + attribute \src "libresoc.v:110412.3-110429.6" + process $proc$libresoc.v:110412$4272 + assign { } { } + assign { } { } + assign $0\fast_b[2:0] $1\fast_b[2:0] + attribute \src "libresoc.v:110413.5-110413.29" + switch \initial + attribute \src "libresoc.v:110413.9-110413.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + switch \$1 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 1'1 assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgn_ext + assign $1\fast_b[2:0] $2\fast_b[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204" + switch { \XL_XO [5] \$3 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\fast_b[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\fast_b[2:0] 3'010 + case + assign $2\fast_b[2:0] 3'000 + end + case + assign $1\fast_b[2:0] 3'000 + end + sync always + update \fast_b $0\fast_b[2:0] + end + attribute \src "libresoc.v:110430.3-110447.6" + process $proc$libresoc.v:110430$4273 + assign { } { } + assign { } { } + assign $0\fast_b_ok[0:0] $1\fast_b_ok[0:0] + attribute \src "libresoc.v:110431.5-110431.29" + switch \initial + attribute \src "libresoc.v:110431.9-110431.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + switch \$5 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 1'1 assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgn_ext + assign $1\fast_b_ok[0:0] $2\fast_b_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204" + switch { \XL_XO [5] \$7 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\fast_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\fast_b_ok[0:0] 1'1 + case + assign $2\fast_b_ok[0:0] 1'0 + end + case + assign $1\fast_b_ok[0:0] 1'0 + end + sync always + update \fast_b_ok $0\fast_b_ok[0:0] + end + connect \$1 $eq$libresoc.v:110378$4266_Y + connect \$3 $not$libresoc.v:110379$4267_Y + connect \$5 $eq$libresoc.v:110380$4268_Y + connect \$7 $not$libresoc.v:110381$4269_Y +end +attribute \src "libresoc.v:110452.1-110705.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_bi" +attribute \generator "nMigen" +module \dec_bi + attribute \src "libresoc.v:110679.3-110689.6" + wire width 16 $0\bd[15:0] + attribute \src "libresoc.v:110690.3-110700.6" + wire width 16 $0\ds[15:0] + attribute \src "libresoc.v:110541.3-110587.6" + wire width 64 $0\imm_b[63:0] + attribute \src "libresoc.v:110588.3-110634.6" + wire $0\imm_b_ok[0:0] + attribute \src "libresoc.v:110453.7-110453.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:110668.3-110678.6" + wire width 26 $0\li[25:0] + attribute \src "libresoc.v:110635.3-110645.6" + wire width 16 $0\si[15:0] + attribute \src "libresoc.v:110646.3-110656.6" + wire width 32 $0\si_hi[31:0] + attribute \src "libresoc.v:110657.3-110667.6" + wire width 16 $0\ui[15:0] + attribute \src "libresoc.v:110679.3-110689.6" + wire width 16 $1\bd[15:0] + attribute \src "libresoc.v:110690.3-110700.6" + wire width 16 $1\ds[15:0] + attribute \src "libresoc.v:110541.3-110587.6" + wire width 64 $1\imm_b[63:0] + attribute \src "libresoc.v:110588.3-110634.6" + wire $1\imm_b_ok[0:0] + attribute \src "libresoc.v:110668.3-110678.6" + wire width 26 $1\li[25:0] + attribute \src "libresoc.v:110635.3-110645.6" + wire width 16 $1\si[15:0] + attribute \src "libresoc.v:110646.3-110656.6" + wire width 32 $1\si_hi[31:0] + attribute \src "libresoc.v:110657.3-110667.6" + wire width 16 $1\ui[15:0] + attribute \src "libresoc.v:110531.17-110531.104" + wire width 64 $extend$libresoc.v:110531$4275_Y + attribute \src "libresoc.v:110532.18-110532.107" + wire width 64 $extend$libresoc.v:110532$4277_Y + attribute \src "libresoc.v:110535.17-110535.104" + wire width 64 $extend$libresoc.v:110535$4281_Y + attribute \src "libresoc.v:110539.17-110539.102" + wire width 64 $extend$libresoc.v:110539$4286_Y + attribute \src "libresoc.v:110531.17-110531.104" + wire width 64 $pos$libresoc.v:110531$4276_Y + attribute \src "libresoc.v:110532.18-110532.107" + wire width 64 $pos$libresoc.v:110532$4278_Y + attribute \src "libresoc.v:110535.17-110535.104" + wire width 64 $pos$libresoc.v:110535$4282_Y + attribute \src "libresoc.v:110539.17-110539.102" + wire width 64 $pos$libresoc.v:110539$4287_Y + attribute \src "libresoc.v:110533.18-110533.114" + wire width 47 $sshl$libresoc.v:110533$4279_Y + attribute \src "libresoc.v:110534.18-110534.113" + wire width 27 $sshl$libresoc.v:110534$4280_Y + attribute \src "libresoc.v:110536.18-110536.113" + wire width 17 $sshl$libresoc.v:110536$4283_Y + attribute \src "libresoc.v:110537.18-110537.113" + wire width 17 $sshl$libresoc.v:110537$4284_Y + attribute \src "libresoc.v:110538.17-110538.109" + wire width 47 $sshl$libresoc.v:110538$4285_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 64 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 64 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + wire width 47 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + wire width 47 \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + wire width 27 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + wire width 27 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + wire width 17 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + wire width 17 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + wire width 17 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + wire width 17 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + wire width 47 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:262" + wire width 64 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 64 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 input 8 \ALU_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 input 9 \ALU_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 24 input 7 \ALU_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 5 \ALU_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 input 3 \ALU_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 input 4 \ALU_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 6 input 6 \ALU_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:257" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \imm_b_ok + attribute \src "libresoc.v:110453.7-110453.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:247" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:232" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:110531$4275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \ALU_sh + connect \Y $extend$libresoc.v:110531$4275_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:110532$4277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \ALU_SH32 + connect \Y $extend$libresoc.v:110532$4277_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:110535$4281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \ALU_UI + connect \Y $extend$libresoc.v:110535$4281_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $pos $extend$libresoc.v:110539$4286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$libresoc.v:110539$4286_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:110531$4276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:110531$4275_Y + connect \Y $pos$libresoc.v:110531$4276_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:110532$4278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:110532$4277_Y + connect \Y $pos$libresoc.v:110532$4278_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:110535$4282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:110535$4281_Y + connect \Y $pos$libresoc.v:110535$4282_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $pos $pos$libresoc.v:110539$4287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:110539$4286_Y + connect \Y $pos$libresoc.v:110539$4287_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + cell $sshl $sshl$libresoc.v:110533$4279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ALU_SI + connect \B 5'10000 + connect \Y $sshl$libresoc.v:110533$4279_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + cell $sshl $sshl$libresoc.v:110534$4280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \ALU_LI + connect \B 2'10 + connect \Y $sshl$libresoc.v:110534$4280_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + cell $sshl $sshl$libresoc.v:110536$4283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \ALU_BD + connect \B 2'10 + connect \Y $sshl$libresoc.v:110536$4283_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + cell $sshl $sshl$libresoc.v:110537$4284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \ALU_DS + connect \B 2'10 + connect \Y $sshl$libresoc.v:110537$4284_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $sshl $sshl$libresoc.v:110538$4285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$libresoc.v:110538$4285_Y + end + attribute \src "libresoc.v:110453.7-110453.20" + process $proc$libresoc.v:110453$4296 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:110541.3-110587.6" + process $proc$libresoc.v:110541$4288 + assign { } { } + assign { } { } + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "libresoc.v:110542.5-110542.29" + switch \initial + attribute \src "libresoc.v:110542.9-110542.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 4'0010 assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgn_ext + assign $1\imm_b[63:0] \$1 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 4'0011 assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgn_ext + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 4'0101 assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgn_ext + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } attribute \src "libresoc.v:0.0-0.0" - case 5'10101 + case 4'0100 assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgn_ext + assign $1\imm_b[63:0] \$3 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 4'0110 assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgn_ext + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 4'0111 assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgn_ext + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 4'1000 assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgn_ext + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 4'1001 assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgn_ext + assign $1\imm_b[63:0] \$7 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 4'1010 assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgn_ext + assign $1\imm_b[63:0] \$9 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 4'1011 assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgn_ext + assign $1\imm_b[63:0] \$11 case - assign $1\dec31_sgn_ext[0:0] 1'0 + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \dec31_sgn_ext $0\dec31_sgn_ext[0:0] + update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:17876.3-17936.6" - process $proc$libresoc.v:17876$401 + attribute \src "libresoc.v:110588.3-110634.6" + process $proc$libresoc.v:110588$4289 assign { } { } assign { } { } - assign $0\dec31_rsrv[0:0] $1\dec31_rsrv[0:0] - attribute \src "libresoc.v:17877.5-17877.29" + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "libresoc.v:110589.5-110589.29" switch \initial - attribute \src "libresoc.v:17877.9-17877.17" + attribute \src "libresoc.v:110589.9-110589.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub10_dec31_dec_sub10_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub28_dec31_dec_sub28_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub0_dec31_dec_sub0_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub26_dec31_dec_sub26_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub19_dec31_dec_sub19_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub22_dec31_dec_sub22_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub9_dec31_dec_sub9_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub11_dec31_dec_sub11_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 4'0010 assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub27_dec31_dec_sub27_rsrv + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 4'0011 assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub15_dec31_dec_sub15_rsrv + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 4'0101 assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub20_dec31_dec_sub20_rsrv + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10101 + case 4'0100 assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub21_dec31_dec_sub21_rsrv + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 4'0110 assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub23_dec31_dec_sub23_rsrv + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 4'0111 assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub16_dec31_dec_sub16_rsrv + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 4'1000 assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub18_dec31_dec_sub18_rsrv + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 4'1001 assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub8_dec31_dec_sub8_rsrv + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 4'1010 assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub24_dec31_dec_sub24_rsrv + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 4'1011 assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub4_dec31_dec_sub4_rsrv + assign $1\imm_b_ok[0:0] 1'1 case - assign $1\dec31_rsrv[0:0] 1'0 + assign $1\imm_b_ok[0:0] 1'0 end sync always - update \dec31_rsrv $0\dec31_rsrv[0:0] + update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:17937.3-17997.6" - process $proc$libresoc.v:17937$402 + attribute \src "libresoc.v:110635.3-110645.6" + process $proc$libresoc.v:110635$4290 assign { } { } assign { } { } - assign $0\dec31_is_32b[0:0] $1\dec31_is_32b[0:0] - attribute \src "libresoc.v:17938.5-17938.29" + assign $0\si[15:0] $1\si[15:0] + attribute \src "libresoc.v:110636.5-110636.29" switch \initial - attribute \src "libresoc.v:17938.9-17938.17" + attribute \src "libresoc.v:110636.9-110636.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub10_dec31_dec_sub10_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub28_dec31_dec_sub28_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 4'0011 assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub0_dec31_dec_sub0_is_32b + assign $1\si[15:0] \ALU_SI + case + assign $1\si[15:0] 16'0000000000000000 + end + sync always + update \si $0\si[15:0] + end + attribute \src "libresoc.v:110646.3-110656.6" + process $proc$libresoc.v:110646$4291 + assign { } { } + assign { } { } + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "libresoc.v:110647.5-110647.29" + switch \initial + attribute \src "libresoc.v:110647.9-110647.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11010 + case 4'0101 assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub26_dec31_dec_sub26_is_32b + assign $1\si_hi[31:0] \$13 [31:0] + case + assign $1\si_hi[31:0] 0 + end + sync always + update \si_hi $0\si_hi[31:0] + end + attribute \src "libresoc.v:110657.3-110667.6" + process $proc$libresoc.v:110657$4292 + assign { } { } + assign { } { } + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "libresoc.v:110658.5-110658.29" + switch \initial + attribute \src "libresoc.v:110658.9-110658.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10011 + case 4'0100 assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub19_dec31_dec_sub19_is_32b + assign $1\ui[15:0] \ALU_UI + case + assign $1\ui[15:0] 16'0000000000000000 + end + sync always + update \ui $0\ui[15:0] + end + attribute \src "libresoc.v:110668.3-110678.6" + process $proc$libresoc.v:110668$4293 + assign { } { } + assign { } { } + assign $0\li[25:0] $1\li[25:0] + attribute \src "libresoc.v:110669.5-110669.29" + switch \initial + attribute \src "libresoc.v:110669.9-110669.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 4'0110 assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub22_dec31_dec_sub22_is_32b + assign $1\li[25:0] \$16 [25:0] + case + assign $1\li[25:0] 26'00000000000000000000000000 + end + sync always + update \li $0\li[25:0] + end + attribute \src "libresoc.v:110679.3-110689.6" + process $proc$libresoc.v:110679$4294 + assign { } { } + assign { } { } + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "libresoc.v:110680.5-110680.29" + switch \initial + attribute \src "libresoc.v:110680.9-110680.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 4'0111 assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub9_dec31_dec_sub9_is_32b + assign $1\bd[15:0] \$19 [15:0] + case + assign $1\bd[15:0] 16'0000000000000000 + end + sync always + update \bd $0\bd[15:0] + end + attribute \src "libresoc.v:110690.3-110700.6" + process $proc$libresoc.v:110690$4295 + assign { } { } + assign { } { } + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "libresoc.v:110691.5-110691.29" + switch \initial + attribute \src "libresoc.v:110691.9-110691.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 4'1000 assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub11_dec31_dec_sub11_is_32b + assign $1\ds[15:0] \$22 [15:0] + case + assign $1\ds[15:0] 16'0000000000000000 + end + sync always + update \ds $0\ds[15:0] + end + connect \$9 $pos$libresoc.v:110531$4276_Y + connect \$11 $pos$libresoc.v:110532$4278_Y + connect \$14 $sshl$libresoc.v:110533$4279_Y + connect \$17 $sshl$libresoc.v:110534$4280_Y + connect \$1 $pos$libresoc.v:110535$4282_Y + connect \$20 $sshl$libresoc.v:110536$4283_Y + connect \$23 $sshl$libresoc.v:110537$4284_Y + connect \$4 $sshl$libresoc.v:110538$4285_Y + connect \$3 $pos$libresoc.v:110539$4287_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 +end +attribute \src "libresoc.v:110709.1-110962.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_bi" +attribute \generator "nMigen" +module \dec_bi$154 + attribute \src "libresoc.v:110936.3-110946.6" + wire width 16 $0\bd[15:0] + attribute \src "libresoc.v:110947.3-110957.6" + wire width 16 $0\ds[15:0] + attribute \src "libresoc.v:110798.3-110844.6" + wire width 64 $0\imm_b[63:0] + attribute \src "libresoc.v:110845.3-110891.6" + wire $0\imm_b_ok[0:0] + attribute \src "libresoc.v:110710.7-110710.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:110925.3-110935.6" + wire width 26 $0\li[25:0] + attribute \src "libresoc.v:110892.3-110902.6" + wire width 16 $0\si[15:0] + attribute \src "libresoc.v:110903.3-110913.6" + wire width 32 $0\si_hi[31:0] + attribute \src "libresoc.v:110914.3-110924.6" + wire width 16 $0\ui[15:0] + attribute \src "libresoc.v:110936.3-110946.6" + wire width 16 $1\bd[15:0] + attribute \src "libresoc.v:110947.3-110957.6" + wire width 16 $1\ds[15:0] + attribute \src "libresoc.v:110798.3-110844.6" + wire width 64 $1\imm_b[63:0] + attribute \src "libresoc.v:110845.3-110891.6" + wire $1\imm_b_ok[0:0] + attribute \src "libresoc.v:110925.3-110935.6" + wire width 26 $1\li[25:0] + attribute \src "libresoc.v:110892.3-110902.6" + wire width 16 $1\si[15:0] + attribute \src "libresoc.v:110903.3-110913.6" + wire width 32 $1\si_hi[31:0] + attribute \src "libresoc.v:110914.3-110924.6" + wire width 16 $1\ui[15:0] + attribute \src "libresoc.v:110788.17-110788.107" + wire width 64 $extend$libresoc.v:110788$4297_Y + attribute \src "libresoc.v:110789.18-110789.110" + wire width 64 $extend$libresoc.v:110789$4299_Y + attribute \src "libresoc.v:110792.17-110792.107" + wire width 64 $extend$libresoc.v:110792$4303_Y + attribute \src "libresoc.v:110796.17-110796.102" + wire width 64 $extend$libresoc.v:110796$4308_Y + attribute \src "libresoc.v:110788.17-110788.107" + wire width 64 $pos$libresoc.v:110788$4298_Y + attribute \src "libresoc.v:110789.18-110789.110" + wire width 64 $pos$libresoc.v:110789$4300_Y + attribute \src "libresoc.v:110792.17-110792.107" + wire width 64 $pos$libresoc.v:110792$4304_Y + attribute \src "libresoc.v:110796.17-110796.102" + wire width 64 $pos$libresoc.v:110796$4309_Y + attribute \src "libresoc.v:110790.18-110790.117" + wire width 47 $sshl$libresoc.v:110790$4301_Y + attribute \src "libresoc.v:110791.18-110791.116" + wire width 27 $sshl$libresoc.v:110791$4302_Y + attribute \src "libresoc.v:110793.18-110793.116" + wire width 17 $sshl$libresoc.v:110793$4305_Y + attribute \src "libresoc.v:110794.18-110794.116" + wire width 17 $sshl$libresoc.v:110794$4306_Y + attribute \src "libresoc.v:110795.17-110795.109" + wire width 47 $sshl$libresoc.v:110795$4307_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 64 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 64 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + wire width 47 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + wire width 47 \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + wire width 27 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + wire width 27 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + wire width 17 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + wire width 17 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + wire width 17 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + wire width 17 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + wire width 47 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:262" + wire width 64 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 64 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 input 8 \BRANCH_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 input 9 \BRANCH_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 24 input 7 \BRANCH_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 5 \BRANCH_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 input 3 \BRANCH_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 input 4 \BRANCH_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 6 input 6 \BRANCH_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:257" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \imm_b_ok + attribute \src "libresoc.v:110710.7-110710.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:247" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:232" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:110788$4297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \BRANCH_sh + connect \Y $extend$libresoc.v:110788$4297_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:110789$4299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \BRANCH_SH32 + connect \Y $extend$libresoc.v:110789$4299_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:110792$4303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \BRANCH_UI + connect \Y $extend$libresoc.v:110792$4303_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $pos $extend$libresoc.v:110796$4308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$libresoc.v:110796$4308_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:110788$4298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:110788$4297_Y + connect \Y $pos$libresoc.v:110788$4298_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:110789$4300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:110789$4299_Y + connect \Y $pos$libresoc.v:110789$4300_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:110792$4304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:110792$4303_Y + connect \Y $pos$libresoc.v:110792$4304_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $pos $pos$libresoc.v:110796$4309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:110796$4308_Y + connect \Y $pos$libresoc.v:110796$4309_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + cell $sshl $sshl$libresoc.v:110790$4301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \BRANCH_SI + connect \B 5'10000 + connect \Y $sshl$libresoc.v:110790$4301_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + cell $sshl $sshl$libresoc.v:110791$4302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \BRANCH_LI + connect \B 2'10 + connect \Y $sshl$libresoc.v:110791$4302_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + cell $sshl $sshl$libresoc.v:110793$4305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \BRANCH_BD + connect \B 2'10 + connect \Y $sshl$libresoc.v:110793$4305_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + cell $sshl $sshl$libresoc.v:110794$4306 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \BRANCH_DS + connect \B 2'10 + connect \Y $sshl$libresoc.v:110794$4306_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $sshl $sshl$libresoc.v:110795$4307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$libresoc.v:110795$4307_Y + end + attribute \src "libresoc.v:110710.7-110710.20" + process $proc$libresoc.v:110710$4318 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:110798.3-110844.6" + process $proc$libresoc.v:110798$4310 + assign { } { } + assign { } { } + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "libresoc.v:110799.5-110799.29" + switch \initial + attribute \src "libresoc.v:110799.9-110799.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 4'0010 assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub27_dec31_dec_sub27_is_32b + assign $1\imm_b[63:0] \$1 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 4'0011 assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub15_dec31_dec_sub15_is_32b + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 4'0101 assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub20_dec31_dec_sub20_is_32b + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } attribute \src "libresoc.v:0.0-0.0" - case 5'10101 + case 4'0100 assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub21_dec31_dec_sub21_is_32b + assign $1\imm_b[63:0] \$3 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 4'0110 assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub23_dec31_dec_sub23_is_32b + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 4'0111 assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub16_dec31_dec_sub16_is_32b + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 4'1000 assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub18_dec31_dec_sub18_is_32b + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 4'1001 assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub8_dec31_dec_sub8_is_32b + assign $1\imm_b[63:0] \$7 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 4'1010 assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub24_dec31_dec_sub24_is_32b + assign $1\imm_b[63:0] \$9 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 4'1011 assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub4_dec31_dec_sub4_is_32b + assign $1\imm_b[63:0] \$11 case - assign $1\dec31_is_32b[0:0] 1'0 + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \dec31_is_32b $0\dec31_is_32b[0:0] + update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:17998.3-18058.6" - process $proc$libresoc.v:17998$403 + attribute \src "libresoc.v:110845.3-110891.6" + process $proc$libresoc.v:110845$4311 assign { } { } assign { } { } - assign $0\dec31_sgn[0:0] $1\dec31_sgn[0:0] - attribute \src "libresoc.v:17999.5-17999.29" + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "libresoc.v:110846.5-110846.29" switch \initial - attribute \src "libresoc.v:17999.9-17999.17" + attribute \src "libresoc.v:110846.9-110846.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 4'0010 assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgn + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 4'0011 assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgn + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 4'0101 assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgn + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10101 + case 4'0100 assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgn + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 4'0110 assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgn + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 4'0111 assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgn + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 4'1000 assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgn + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 4'1001 assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgn + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 4'1010 assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgn + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 4'1011 assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgn + assign $1\imm_b_ok[0:0] 1'1 case - assign $1\dec31_sgn[0:0] 1'0 + assign $1\imm_b_ok[0:0] 1'0 end sync always - update \dec31_sgn $0\dec31_sgn[0:0] + update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:18059.3-18119.6" - process $proc$libresoc.v:18059$404 + attribute \src "libresoc.v:110892.3-110902.6" + process $proc$libresoc.v:110892$4312 assign { } { } assign { } { } - assign $0\dec31_lk[0:0] $1\dec31_lk[0:0] - attribute \src "libresoc.v:18060.5-18060.29" + assign $0\si[15:0] $1\si[15:0] + attribute \src "libresoc.v:110893.5-110893.29" switch \initial - attribute \src "libresoc.v:18060.9-18060.17" + attribute \src "libresoc.v:110893.9-110893.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub10_dec31_dec_sub10_lk - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub28_dec31_dec_sub28_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 4'0011 assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub0_dec31_dec_sub0_lk + assign $1\si[15:0] \BRANCH_SI + case + assign $1\si[15:0] 16'0000000000000000 + end + sync always + update \si $0\si[15:0] + end + attribute \src "libresoc.v:110903.3-110913.6" + process $proc$libresoc.v:110903$4313 + assign { } { } + assign { } { } + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "libresoc.v:110904.5-110904.29" + switch \initial + attribute \src "libresoc.v:110904.9-110904.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11010 + case 4'0101 assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub26_dec31_dec_sub26_lk + assign $1\si_hi[31:0] \$13 [31:0] + case + assign $1\si_hi[31:0] 0 + end + sync always + update \si_hi $0\si_hi[31:0] + end + attribute \src "libresoc.v:110914.3-110924.6" + process $proc$libresoc.v:110914$4314 + assign { } { } + assign { } { } + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "libresoc.v:110915.5-110915.29" + switch \initial + attribute \src "libresoc.v:110915.9-110915.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10011 + case 4'0100 assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub19_dec31_dec_sub19_lk + assign $1\ui[15:0] \BRANCH_UI + case + assign $1\ui[15:0] 16'0000000000000000 + end + sync always + update \ui $0\ui[15:0] + end + attribute \src "libresoc.v:110925.3-110935.6" + process $proc$libresoc.v:110925$4315 + assign { } { } + assign { } { } + assign $0\li[25:0] $1\li[25:0] + attribute \src "libresoc.v:110926.5-110926.29" + switch \initial + attribute \src "libresoc.v:110926.9-110926.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 4'0110 assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub22_dec31_dec_sub22_lk + assign $1\li[25:0] \$16 [25:0] + case + assign $1\li[25:0] 26'00000000000000000000000000 + end + sync always + update \li $0\li[25:0] + end + attribute \src "libresoc.v:110936.3-110946.6" + process $proc$libresoc.v:110936$4316 + assign { } { } + assign { } { } + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "libresoc.v:110937.5-110937.29" + switch \initial + attribute \src "libresoc.v:110937.9-110937.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 4'0111 assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub9_dec31_dec_sub9_lk + assign $1\bd[15:0] \$19 [15:0] + case + assign $1\bd[15:0] 16'0000000000000000 + end + sync always + update \bd $0\bd[15:0] + end + attribute \src "libresoc.v:110947.3-110957.6" + process $proc$libresoc.v:110947$4317 + assign { } { } + assign { } { } + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "libresoc.v:110948.5-110948.29" + switch \initial + attribute \src "libresoc.v:110948.9-110948.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 4'1000 assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub11_dec31_dec_sub11_lk + assign $1\ds[15:0] \$22 [15:0] + case + assign $1\ds[15:0] 16'0000000000000000 + end + sync always + update \ds $0\ds[15:0] + end + connect \$9 $pos$libresoc.v:110788$4298_Y + connect \$11 $pos$libresoc.v:110789$4300_Y + connect \$14 $sshl$libresoc.v:110790$4301_Y + connect \$17 $sshl$libresoc.v:110791$4302_Y + connect \$1 $pos$libresoc.v:110792$4304_Y + connect \$20 $sshl$libresoc.v:110793$4305_Y + connect \$23 $sshl$libresoc.v:110794$4306_Y + connect \$4 $sshl$libresoc.v:110795$4307_Y + connect \$3 $pos$libresoc.v:110796$4309_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 +end +attribute \src "libresoc.v:110966.1-111219.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_bi" +attribute \generator "nMigen" +module \dec_bi$163 + attribute \src "libresoc.v:111193.3-111203.6" + wire width 16 $0\bd[15:0] + attribute \src "libresoc.v:111204.3-111214.6" + wire width 16 $0\ds[15:0] + attribute \src "libresoc.v:111055.3-111101.6" + wire width 64 $0\imm_b[63:0] + attribute \src "libresoc.v:111102.3-111148.6" + wire $0\imm_b_ok[0:0] + attribute \src "libresoc.v:110967.7-110967.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:111182.3-111192.6" + wire width 26 $0\li[25:0] + attribute \src "libresoc.v:111149.3-111159.6" + wire width 16 $0\si[15:0] + attribute \src "libresoc.v:111160.3-111170.6" + wire width 32 $0\si_hi[31:0] + attribute \src "libresoc.v:111171.3-111181.6" + wire width 16 $0\ui[15:0] + attribute \src "libresoc.v:111193.3-111203.6" + wire width 16 $1\bd[15:0] + attribute \src "libresoc.v:111204.3-111214.6" + wire width 16 $1\ds[15:0] + attribute \src "libresoc.v:111055.3-111101.6" + wire width 64 $1\imm_b[63:0] + attribute \src "libresoc.v:111102.3-111148.6" + wire $1\imm_b_ok[0:0] + attribute \src "libresoc.v:111182.3-111192.6" + wire width 26 $1\li[25:0] + attribute \src "libresoc.v:111149.3-111159.6" + wire width 16 $1\si[15:0] + attribute \src "libresoc.v:111160.3-111170.6" + wire width 32 $1\si_hi[31:0] + attribute \src "libresoc.v:111171.3-111181.6" + wire width 16 $1\ui[15:0] + attribute \src "libresoc.v:111045.17-111045.108" + wire width 64 $extend$libresoc.v:111045$4319_Y + attribute \src "libresoc.v:111046.18-111046.111" + wire width 64 $extend$libresoc.v:111046$4321_Y + attribute \src "libresoc.v:111049.17-111049.108" + wire width 64 $extend$libresoc.v:111049$4325_Y + attribute \src "libresoc.v:111053.17-111053.102" + wire width 64 $extend$libresoc.v:111053$4330_Y + attribute \src "libresoc.v:111045.17-111045.108" + wire width 64 $pos$libresoc.v:111045$4320_Y + attribute \src "libresoc.v:111046.18-111046.111" + wire width 64 $pos$libresoc.v:111046$4322_Y + attribute \src "libresoc.v:111049.17-111049.108" + wire width 64 $pos$libresoc.v:111049$4326_Y + attribute \src "libresoc.v:111053.17-111053.102" + wire width 64 $pos$libresoc.v:111053$4331_Y + attribute \src "libresoc.v:111047.18-111047.118" + wire width 47 $sshl$libresoc.v:111047$4323_Y + attribute \src "libresoc.v:111048.18-111048.117" + wire width 27 $sshl$libresoc.v:111048$4324_Y + attribute \src "libresoc.v:111050.18-111050.117" + wire width 17 $sshl$libresoc.v:111050$4327_Y + attribute \src "libresoc.v:111051.18-111051.117" + wire width 17 $sshl$libresoc.v:111051$4328_Y + attribute \src "libresoc.v:111052.17-111052.109" + wire width 47 $sshl$libresoc.v:111052$4329_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 64 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 64 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + wire width 47 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + wire width 47 \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + wire width 27 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + wire width 27 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + wire width 17 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + wire width 17 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + wire width 17 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + wire width 17 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + wire width 47 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:262" + wire width 64 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 64 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 input 8 \LOGICAL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 input 9 \LOGICAL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 24 input 7 \LOGICAL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 5 \LOGICAL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 input 3 \LOGICAL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 input 4 \LOGICAL_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 6 input 6 \LOGICAL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:257" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \imm_b_ok + attribute \src "libresoc.v:110967.7-110967.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:247" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:232" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:111045$4319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \LOGICAL_sh + connect \Y $extend$libresoc.v:111045$4319_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:111046$4321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \LOGICAL_SH32 + connect \Y $extend$libresoc.v:111046$4321_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:111049$4325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \LOGICAL_UI + connect \Y $extend$libresoc.v:111049$4325_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $pos $extend$libresoc.v:111053$4330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$libresoc.v:111053$4330_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:111045$4320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:111045$4319_Y + connect \Y $pos$libresoc.v:111045$4320_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:111046$4322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:111046$4321_Y + connect \Y $pos$libresoc.v:111046$4322_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:111049$4326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:111049$4325_Y + connect \Y $pos$libresoc.v:111049$4326_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $pos $pos$libresoc.v:111053$4331 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:111053$4330_Y + connect \Y $pos$libresoc.v:111053$4331_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + cell $sshl $sshl$libresoc.v:111047$4323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \LOGICAL_SI + connect \B 5'10000 + connect \Y $sshl$libresoc.v:111047$4323_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + cell $sshl $sshl$libresoc.v:111048$4324 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \LOGICAL_LI + connect \B 2'10 + connect \Y $sshl$libresoc.v:111048$4324_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + cell $sshl $sshl$libresoc.v:111050$4327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \LOGICAL_BD + connect \B 2'10 + connect \Y $sshl$libresoc.v:111050$4327_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + cell $sshl $sshl$libresoc.v:111051$4328 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \LOGICAL_DS + connect \B 2'10 + connect \Y $sshl$libresoc.v:111051$4328_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $sshl $sshl$libresoc.v:111052$4329 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$libresoc.v:111052$4329_Y + end + attribute \src "libresoc.v:110967.7-110967.20" + process $proc$libresoc.v:110967$4340 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:111055.3-111101.6" + process $proc$libresoc.v:111055$4332 + assign { } { } + assign { } { } + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "libresoc.v:111056.5-111056.29" + switch \initial + attribute \src "libresoc.v:111056.9-111056.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 4'0010 assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub27_dec31_dec_sub27_lk + assign $1\imm_b[63:0] \$1 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 4'0011 assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub15_dec31_dec_sub15_lk + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 4'0101 assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub20_dec31_dec_sub20_lk + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } attribute \src "libresoc.v:0.0-0.0" - case 5'10101 + case 4'0100 assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub21_dec31_dec_sub21_lk + assign $1\imm_b[63:0] \$3 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 4'0110 assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub23_dec31_dec_sub23_lk + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 4'0111 assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub16_dec31_dec_sub16_lk + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 4'1000 assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub18_dec31_dec_sub18_lk + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 4'1001 assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub8_dec31_dec_sub8_lk + assign $1\imm_b[63:0] \$7 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 4'1010 assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub24_dec31_dec_sub24_lk + assign $1\imm_b[63:0] \$9 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 4'1011 assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub4_dec31_dec_sub4_lk + assign $1\imm_b[63:0] \$11 case - assign $1\dec31_lk[0:0] 1'0 + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \dec31_lk $0\dec31_lk[0:0] + update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:18120.3-18180.6" - process $proc$libresoc.v:18120$405 + attribute \src "libresoc.v:111102.3-111148.6" + process $proc$libresoc.v:111102$4333 assign { } { } assign { } { } - assign $0\dec31_sgl_pipe[0:0] $1\dec31_sgl_pipe[0:0] - attribute \src "libresoc.v:18121.5-18121.29" + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "libresoc.v:111103.5-111103.29" switch \initial - attribute \src "libresoc.v:18121.9-18121.17" + attribute \src "libresoc.v:111103.9-111103.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 4'0010 assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 4'0011 assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 4'0101 assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 4'0100 assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 4'0110 assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10101 + case 4'0111 assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 4'1000 assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 4'1001 assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 4'1010 assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 4'1011 assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe + assign $1\imm_b_ok[0:0] 1'1 + case + assign $1\imm_b_ok[0:0] 1'0 + end + sync always + update \imm_b_ok $0\imm_b_ok[0:0] + end + attribute \src "libresoc.v:111149.3-111159.6" + process $proc$libresoc.v:111149$4334 + assign { } { } + assign { } { } + assign $0\si[15:0] $1\si[15:0] + attribute \src "libresoc.v:111150.5-111150.29" + switch \initial + attribute \src "libresoc.v:111150.9-111150.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 4'0011 assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe + assign $1\si[15:0] \LOGICAL_SI + case + assign $1\si[15:0] 16'0000000000000000 + end + sync always + update \si $0\si[15:0] + end + attribute \src "libresoc.v:111160.3-111170.6" + process $proc$libresoc.v:111160$4335 + assign { } { } + assign { } { } + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "libresoc.v:111161.5-111161.29" + switch \initial + attribute \src "libresoc.v:111161.9-111161.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 4'0101 assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe + assign $1\si_hi[31:0] \$13 [31:0] case - assign $1\dec31_sgl_pipe[0:0] 1'0 + assign $1\si_hi[31:0] 0 end sync always - update \dec31_sgl_pipe $0\dec31_sgl_pipe[0:0] + update \si_hi $0\si_hi[31:0] end - connect \dec31_dec_sub4_opcode_in \opcode_in - connect \dec31_dec_sub24_opcode_in \opcode_in - connect \dec31_dec_sub8_opcode_in \opcode_in - connect \dec31_dec_sub18_opcode_in \opcode_in - connect \dec31_dec_sub16_opcode_in \opcode_in - connect \dec31_dec_sub23_opcode_in \opcode_in - connect \dec31_dec_sub21_opcode_in \opcode_in - connect \dec31_dec_sub20_opcode_in \opcode_in - connect \dec31_dec_sub15_opcode_in \opcode_in - connect \dec31_dec_sub27_opcode_in \opcode_in - connect \dec31_dec_sub11_opcode_in \opcode_in - connect \dec31_dec_sub9_opcode_in \opcode_in - connect \dec31_dec_sub22_opcode_in \opcode_in - connect \dec31_dec_sub19_opcode_in \opcode_in - connect \dec31_dec_sub26_opcode_in \opcode_in - connect \dec31_dec_sub0_opcode_in \opcode_in - connect \dec31_dec_sub28_opcode_in \opcode_in - connect \dec31_dec_sub10_opcode_in \opcode_in - connect \opc_in \opcode_switch [4:0] - connect \opcode_switch \opcode_in [10:1] -end -attribute \src "libresoc.v:18205.1-18920.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub0" -attribute \generator "nMigen" -module \dec31_dec_sub0 - attribute \src "libresoc.v:18558.3-18576.6" - wire width 8 $0\dec31_dec_sub0_asmcode[7:0] - attribute \src "libresoc.v:18634.3-18652.6" - wire $0\dec31_dec_sub0_br[0:0] - attribute \src "libresoc.v:18881.3-18899.6" - wire width 3 $0\dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:18900.3-18918.6" - wire width 3 $0\dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:18539.3-18557.6" - wire width 2 $0\dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:18615.3-18633.6" - wire $0\dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:18786.3-18804.6" - wire width 5 $0\dec31_dec_sub0_form[4:0] - attribute \src "libresoc.v:18463.3-18481.6" - wire width 12 $0\dec31_dec_sub0_function_unit[11:0] - attribute \src "libresoc.v:18805.3-18823.6" - wire width 3 $0\dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:18824.3-18842.6" - wire width 4 $0\dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:18843.3-18861.6" - wire width 2 $0\dec31_dec_sub0_in3_sel[1:0] - attribute \src "libresoc.v:18672.3-18690.6" - wire width 7 $0\dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:18577.3-18595.6" - wire $0\dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:18596.3-18614.6" - wire $0\dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:18710.3-18728.6" - wire $0\dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:18482.3-18500.6" - wire width 4 $0\dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:18748.3-18766.6" - wire $0\dec31_dec_sub0_lk[0:0] - attribute \src "libresoc.v:18862.3-18880.6" - wire width 2 $0\dec31_dec_sub0_out_sel[1:0] - attribute \src "libresoc.v:18520.3-18538.6" - wire width 2 $0\dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:18691.3-18709.6" - wire $0\dec31_dec_sub0_rsrv[0:0] - attribute \src "libresoc.v:18767.3-18785.6" - wire $0\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "libresoc.v:18729.3-18747.6" - wire $0\dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:18653.3-18671.6" - wire $0\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "libresoc.v:18501.3-18519.6" - wire width 2 $0\dec31_dec_sub0_upd[1:0] - attribute \src "libresoc.v:18206.7-18206.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:18558.3-18576.6" - wire width 8 $1\dec31_dec_sub0_asmcode[7:0] - attribute \src "libresoc.v:18634.3-18652.6" - wire $1\dec31_dec_sub0_br[0:0] - attribute \src "libresoc.v:18881.3-18899.6" - wire width 3 $1\dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:18900.3-18918.6" - wire width 3 $1\dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:18539.3-18557.6" - wire width 2 $1\dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:18615.3-18633.6" - wire $1\dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:18786.3-18804.6" - wire width 5 $1\dec31_dec_sub0_form[4:0] - attribute \src "libresoc.v:18463.3-18481.6" - wire width 12 $1\dec31_dec_sub0_function_unit[11:0] - attribute \src "libresoc.v:18805.3-18823.6" - wire width 3 $1\dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:18824.3-18842.6" - wire width 4 $1\dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:18843.3-18861.6" - wire width 2 $1\dec31_dec_sub0_in3_sel[1:0] - attribute \src "libresoc.v:18672.3-18690.6" - wire width 7 $1\dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:18577.3-18595.6" - wire $1\dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:18596.3-18614.6" - wire $1\dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:18710.3-18728.6" - wire $1\dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:18482.3-18500.6" - wire width 4 $1\dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:18748.3-18766.6" - wire $1\dec31_dec_sub0_lk[0:0] - attribute \src "libresoc.v:18862.3-18880.6" - wire width 2 $1\dec31_dec_sub0_out_sel[1:0] - attribute \src "libresoc.v:18520.3-18538.6" - wire width 2 $1\dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:18691.3-18709.6" - wire $1\dec31_dec_sub0_rsrv[0:0] - attribute \src "libresoc.v:18767.3-18785.6" - wire $1\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "libresoc.v:18729.3-18747.6" - wire $1\dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:18653.3-18671.6" - wire $1\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "libresoc.v:18501.3-18519.6" - wire width 2 $1\dec31_dec_sub0_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub0_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub0_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub0_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub0_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub0_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub0_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub0_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub0_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub0_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub0_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub0_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + wire width 17 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + wire width 17 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + wire width 17 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + wire width 17 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + wire width 47 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:262" + wire width 64 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 64 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 input 8 \DIV_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 input 9 \DIV_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 24 input 7 \DIV_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 5 \DIV_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 input 3 \DIV_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 input 4 \DIV_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 6 input 6 \DIV_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:257" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \imm_b_ok + attribute \src "libresoc.v:111224.7-111224.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:247" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:232" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:111302$4341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \DIV_sh + connect \Y $extend$libresoc.v:111302$4341_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:111303$4343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \DIV_SH32 + connect \Y $extend$libresoc.v:111303$4343_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:111306$4347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \DIV_UI + connect \Y $extend$libresoc.v:111306$4347_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $pos $extend$libresoc.v:111310$4352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$libresoc.v:111310$4352_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:111302$4342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:111302$4341_Y + connect \Y $pos$libresoc.v:111302$4342_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:111303$4344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:111303$4343_Y + connect \Y $pos$libresoc.v:111303$4344_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:111306$4348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:111306$4347_Y + connect \Y $pos$libresoc.v:111306$4348_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $pos $pos$libresoc.v:111310$4353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:111310$4352_Y + connect \Y $pos$libresoc.v:111310$4353_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + cell $sshl $sshl$libresoc.v:111304$4345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \DIV_SI + connect \B 5'10000 + connect \Y $sshl$libresoc.v:111304$4345_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + cell $sshl $sshl$libresoc.v:111305$4346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \DIV_LI + connect \B 2'10 + connect \Y $sshl$libresoc.v:111305$4346_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + cell $sshl $sshl$libresoc.v:111307$4349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \DIV_BD + connect \B 2'10 + connect \Y $sshl$libresoc.v:111307$4349_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + cell $sshl $sshl$libresoc.v:111308$4350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \DIV_DS + connect \B 2'10 + connect \Y $sshl$libresoc.v:111308$4350_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $sshl $sshl$libresoc.v:111309$4351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$libresoc.v:111309$4351_Y end - attribute \src "libresoc.v:18520.3-18538.6" - process $proc$libresoc.v:18520$410 + attribute \src "libresoc.v:111224.7-111224.20" + process $proc$libresoc.v:111224$4362 assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:111312.3-111358.6" + process $proc$libresoc.v:111312$4354 assign { } { } - assign $0\dec31_dec_sub0_rc_sel[1:0] $1\dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:18521.5-18521.29" + assign { } { } + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "libresoc.v:111313.5-111313.29" switch \initial - attribute \src "libresoc.v:18521.9-18521.17" + attribute \src "libresoc.v:111313.9-111313.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 4'0010 assign { } { } - assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + assign $1\imm_b[63:0] \$1 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 4'0011 assign { } { } - assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 4'0101 assign { } { } - assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 4'0100 assign { } { } - assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + assign $1\imm_b[63:0] \$3 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 case - assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \dec31_dec_sub0_rc_sel $0\dec31_dec_sub0_rc_sel[1:0] + update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:18539.3-18557.6" - process $proc$libresoc.v:18539$411 + attribute \src "libresoc.v:111359.3-111405.6" + process $proc$libresoc.v:111359$4355 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_cry_in[1:0] $1\dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:18540.5-18540.29" + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "libresoc.v:111360.5-111360.29" switch \initial - attribute \src "libresoc.v:18540.9-18540.17" + attribute \src "libresoc.v:111360.9-111360.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 4'0010 assign { } { } - assign $1\dec31_dec_sub0_cry_in[1:0] 2'01 + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 4'0011 assign { } { } - assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 4'0101 assign { } { } - assign $1\dec31_dec_sub0_cry_in[1:0] 2'01 + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 4'0100 assign { } { } - assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 case - assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 + assign $1\imm_b_ok[0:0] 1'0 end sync always - update \dec31_dec_sub0_cry_in $0\dec31_dec_sub0_cry_in[1:0] + update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:18558.3-18576.6" - process $proc$libresoc.v:18558$412 + attribute \src "libresoc.v:111406.3-111416.6" + process $proc$libresoc.v:111406$4356 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_asmcode[7:0] $1\dec31_dec_sub0_asmcode[7:0] - attribute \src "libresoc.v:18559.5-18559.29" + assign $0\si[15:0] $1\si[15:0] + attribute \src "libresoc.v:111407.5-111407.29" switch \initial - attribute \src "libresoc.v:18559.9-18559.17" + attribute \src "libresoc.v:111407.9-111407.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 4'0011 assign { } { } - assign $1\dec31_dec_sub0_asmcode[7:0] 8'10011011 + assign $1\si[15:0] \DIV_SI case - assign $1\dec31_dec_sub0_asmcode[7:0] 8'00000000 + assign $1\si[15:0] 16'0000000000000000 end sync always - update \dec31_dec_sub0_asmcode $0\dec31_dec_sub0_asmcode[7:0] + update \si $0\si[15:0] end - attribute \src "libresoc.v:18577.3-18595.6" - process $proc$libresoc.v:18577$413 + attribute \src "libresoc.v:111417.3-111427.6" + process $proc$libresoc.v:111417$4357 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_inv_a[0:0] $1\dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:18578.5-18578.29" + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "libresoc.v:111418.5-111418.29" switch \initial - attribute \src "libresoc.v:18578.9-18578.17" + attribute \src "libresoc.v:111418.9-111418.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_inv_a[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 4'0101 assign { } { } - assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 + assign $1\si_hi[31:0] \$13 [31:0] case - assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 + assign $1\si_hi[31:0] 0 end sync always - update \dec31_dec_sub0_inv_a $0\dec31_dec_sub0_inv_a[0:0] + update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:18596.3-18614.6" - process $proc$libresoc.v:18596$414 + attribute \src "libresoc.v:111428.3-111438.6" + process $proc$libresoc.v:111428$4358 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_inv_out[0:0] $1\dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:18597.5-18597.29" + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "libresoc.v:111429.5-111429.29" switch \initial - attribute \src "libresoc.v:18597.9-18597.17" + attribute \src "libresoc.v:111429.9-111429.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 4'0100 assign { } { } - assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + assign $1\ui[15:0] \DIV_UI + case + assign $1\ui[15:0] 16'0000000000000000 + end + sync always + update \ui $0\ui[15:0] + end + attribute \src "libresoc.v:111439.3-111449.6" + process $proc$libresoc.v:111439$4359 + assign { } { } + assign { } { } + assign $0\li[25:0] $1\li[25:0] + attribute \src "libresoc.v:111440.5-111440.29" + switch \initial + attribute \src "libresoc.v:111440.9-111440.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 4'0110 assign { } { } - assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + assign $1\li[25:0] \$16 [25:0] + case + assign $1\li[25:0] 26'00000000000000000000000000 + end + sync always + update \li $0\li[25:0] + end + attribute \src "libresoc.v:111450.3-111460.6" + process $proc$libresoc.v:111450$4360 + assign { } { } + assign { } { } + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "libresoc.v:111451.5-111451.29" + switch \initial + attribute \src "libresoc.v:111451.9-111451.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 4'0111 assign { } { } - assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + assign $1\bd[15:0] \$19 [15:0] + case + assign $1\bd[15:0] 16'0000000000000000 + end + sync always + update \bd $0\bd[15:0] + end + attribute \src "libresoc.v:111461.3-111471.6" + process $proc$libresoc.v:111461$4361 + assign { } { } + assign { } { } + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "libresoc.v:111462.5-111462.29" + switch \initial + attribute \src "libresoc.v:111462.9-111462.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 4'1000 assign { } { } - assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + assign $1\ds[15:0] \$22 [15:0] case - assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + assign $1\ds[15:0] 16'0000000000000000 end sync always - update \dec31_dec_sub0_inv_out $0\dec31_dec_sub0_inv_out[0:0] + update \ds $0\ds[15:0] + end + connect \$9 $pos$libresoc.v:111302$4342_Y + connect \$11 $pos$libresoc.v:111303$4344_Y + connect \$14 $sshl$libresoc.v:111304$4345_Y + connect \$17 $sshl$libresoc.v:111305$4346_Y + connect \$1 $pos$libresoc.v:111306$4348_Y + connect \$20 $sshl$libresoc.v:111307$4349_Y + connect \$23 $sshl$libresoc.v:111308$4350_Y + connect \$4 $sshl$libresoc.v:111309$4351_Y + connect \$3 $pos$libresoc.v:111310$4353_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 +end +attribute \src "libresoc.v:111480.1-111733.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_bi" +attribute \generator "nMigen" +module \dec_bi$187 + attribute \src "libresoc.v:111707.3-111717.6" + wire width 16 $0\bd[15:0] + attribute \src "libresoc.v:111718.3-111728.6" + wire width 16 $0\ds[15:0] + attribute \src "libresoc.v:111569.3-111615.6" + wire width 64 $0\imm_b[63:0] + attribute \src "libresoc.v:111616.3-111662.6" + wire $0\imm_b_ok[0:0] + attribute \src "libresoc.v:111481.7-111481.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:111696.3-111706.6" + wire width 26 $0\li[25:0] + attribute \src "libresoc.v:111663.3-111673.6" + wire width 16 $0\si[15:0] + attribute \src "libresoc.v:111674.3-111684.6" + wire width 32 $0\si_hi[31:0] + attribute \src "libresoc.v:111685.3-111695.6" + wire width 16 $0\ui[15:0] + attribute \src "libresoc.v:111707.3-111717.6" + wire width 16 $1\bd[15:0] + attribute \src "libresoc.v:111718.3-111728.6" + wire width 16 $1\ds[15:0] + attribute \src "libresoc.v:111569.3-111615.6" + wire width 64 $1\imm_b[63:0] + attribute \src "libresoc.v:111616.3-111662.6" + wire $1\imm_b_ok[0:0] + attribute \src "libresoc.v:111696.3-111706.6" + wire width 26 $1\li[25:0] + attribute \src "libresoc.v:111663.3-111673.6" + wire width 16 $1\si[15:0] + attribute \src "libresoc.v:111674.3-111684.6" + wire width 32 $1\si_hi[31:0] + attribute \src "libresoc.v:111685.3-111695.6" + wire width 16 $1\ui[15:0] + attribute \src "libresoc.v:111559.17-111559.104" + wire width 64 $extend$libresoc.v:111559$4363_Y + attribute \src "libresoc.v:111560.18-111560.107" + wire width 64 $extend$libresoc.v:111560$4365_Y + attribute \src "libresoc.v:111563.17-111563.104" + wire width 64 $extend$libresoc.v:111563$4369_Y + attribute \src "libresoc.v:111567.17-111567.102" + wire width 64 $extend$libresoc.v:111567$4374_Y + attribute \src "libresoc.v:111559.17-111559.104" + wire width 64 $pos$libresoc.v:111559$4364_Y + attribute \src "libresoc.v:111560.18-111560.107" + wire width 64 $pos$libresoc.v:111560$4366_Y + attribute \src "libresoc.v:111563.17-111563.104" + wire width 64 $pos$libresoc.v:111563$4370_Y + attribute \src "libresoc.v:111567.17-111567.102" + wire width 64 $pos$libresoc.v:111567$4375_Y + attribute \src "libresoc.v:111561.18-111561.114" + wire width 47 $sshl$libresoc.v:111561$4367_Y + attribute \src "libresoc.v:111562.18-111562.113" + wire width 27 $sshl$libresoc.v:111562$4368_Y + attribute \src "libresoc.v:111564.18-111564.113" + wire width 17 $sshl$libresoc.v:111564$4371_Y + attribute \src "libresoc.v:111565.18-111565.113" + wire width 17 $sshl$libresoc.v:111565$4372_Y + attribute \src "libresoc.v:111566.17-111566.109" + wire width 47 $sshl$libresoc.v:111566$4373_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 64 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 64 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + wire width 47 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + wire width 47 \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + wire width 27 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + wire width 27 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + wire width 17 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + wire width 17 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + wire width 17 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + wire width 17 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + wire width 47 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:262" + wire width 64 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 64 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 input 8 \MUL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 input 9 \MUL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 24 input 7 \MUL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 5 \MUL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 input 3 \MUL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 input 4 \MUL_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 6 input 6 \MUL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:257" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \imm_b_ok + attribute \src "libresoc.v:111481.7-111481.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:247" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:232" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:111559$4363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \MUL_sh + connect \Y $extend$libresoc.v:111559$4363_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:111560$4365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \MUL_SH32 + connect \Y $extend$libresoc.v:111560$4365_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:111563$4369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \MUL_UI + connect \Y $extend$libresoc.v:111563$4369_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $pos $extend$libresoc.v:111567$4374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$libresoc.v:111567$4374_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:111559$4364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:111559$4363_Y + connect \Y $pos$libresoc.v:111559$4364_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:111560$4366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:111560$4365_Y + connect \Y $pos$libresoc.v:111560$4366_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:111563$4370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:111563$4369_Y + connect \Y $pos$libresoc.v:111563$4370_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $pos $pos$libresoc.v:111567$4375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:111567$4374_Y + connect \Y $pos$libresoc.v:111567$4375_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + cell $sshl $sshl$libresoc.v:111561$4367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \MUL_SI + connect \B 5'10000 + connect \Y $sshl$libresoc.v:111561$4367_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + cell $sshl $sshl$libresoc.v:111562$4368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \MUL_LI + connect \B 2'10 + connect \Y $sshl$libresoc.v:111562$4368_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + cell $sshl $sshl$libresoc.v:111564$4371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \MUL_BD + connect \B 2'10 + connect \Y $sshl$libresoc.v:111564$4371_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + cell $sshl $sshl$libresoc.v:111565$4372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \MUL_DS + connect \B 2'10 + connect \Y $sshl$libresoc.v:111565$4372_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $sshl $sshl$libresoc.v:111566$4373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$libresoc.v:111566$4373_Y + end + attribute \src "libresoc.v:111481.7-111481.20" + process $proc$libresoc.v:111481$4384 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:18615.3-18633.6" - process $proc$libresoc.v:18615$415 + attribute \src "libresoc.v:111569.3-111615.6" + process $proc$libresoc.v:111569$4376 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_cry_out[0:0] $1\dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:18616.5-18616.29" + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "libresoc.v:111570.5-111570.29" switch \initial - attribute \src "libresoc.v:18616.9-18616.17" + attribute \src "libresoc.v:111570.9-111570.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 4'0010 assign { } { } - assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + assign $1\imm_b[63:0] \$1 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 4'0011 assign { } { } - assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 4'0101 assign { } { } - assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 4'0100 assign { } { } - assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + assign $1\imm_b[63:0] \$3 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 case - assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \dec31_dec_sub0_cry_out $0\dec31_dec_sub0_cry_out[0:0] + update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:18634.3-18652.6" - process $proc$libresoc.v:18634$416 + attribute \src "libresoc.v:111616.3-111662.6" + process $proc$libresoc.v:111616$4377 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_br[0:0] $1\dec31_dec_sub0_br[0:0] - attribute \src "libresoc.v:18635.5-18635.29" + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "libresoc.v:111617.5-111617.29" switch \initial - attribute \src "libresoc.v:18635.9-18635.17" + attribute \src "libresoc.v:111617.9-111617.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 4'0010 assign { } { } - assign $1\dec31_dec_sub0_br[0:0] 1'0 + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 4'0011 assign { } { } - assign $1\dec31_dec_sub0_br[0:0] 1'0 + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 4'0101 assign { } { } - assign $1\dec31_dec_sub0_br[0:0] 1'0 + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 4'0100 assign { } { } - assign $1\dec31_dec_sub0_br[0:0] 1'0 + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 case - assign $1\dec31_dec_sub0_br[0:0] 1'0 + assign $1\imm_b_ok[0:0] 1'0 end sync always - update \dec31_dec_sub0_br $0\dec31_dec_sub0_br[0:0] + update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:18653.3-18671.6" - process $proc$libresoc.v:18653$417 + attribute \src "libresoc.v:111663.3-111673.6" + process $proc$libresoc.v:111663$4378 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_sgn_ext[0:0] $1\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "libresoc.v:18654.5-18654.29" + assign $0\si[15:0] $1\si[15:0] + attribute \src "libresoc.v:111664.5-111664.29" switch \initial - attribute \src "libresoc.v:18654.9-18654.17" + attribute \src "libresoc.v:111664.9-111664.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 4'0011 assign { } { } - assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + assign $1\si[15:0] \MUL_SI + case + assign $1\si[15:0] 16'0000000000000000 + end + sync always + update \si $0\si[15:0] + end + attribute \src "libresoc.v:111674.3-111684.6" + process $proc$libresoc.v:111674$4379 + assign { } { } + assign { } { } + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "libresoc.v:111675.5-111675.29" + switch \initial + attribute \src "libresoc.v:111675.9-111675.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 4'0101 assign { } { } - assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + assign $1\si_hi[31:0] \$13 [31:0] case - assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + assign $1\si_hi[31:0] 0 end sync always - update \dec31_dec_sub0_sgn_ext $0\dec31_dec_sub0_sgn_ext[0:0] + update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:18672.3-18690.6" - process $proc$libresoc.v:18672$418 + attribute \src "libresoc.v:111685.3-111695.6" + process $proc$libresoc.v:111685$4380 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_internal_op[6:0] $1\dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:18673.5-18673.29" + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "libresoc.v:111686.5-111686.29" switch \initial - attribute \src "libresoc.v:18673.9-18673.17" + attribute \src "libresoc.v:111686.9-111686.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 4'0100 assign { } { } - assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 + assign $1\ui[15:0] \MUL_UI + case + assign $1\ui[15:0] 16'0000000000000000 + end + sync always + update \ui $0\ui[15:0] + end + attribute \src "libresoc.v:111696.3-111706.6" + process $proc$libresoc.v:111696$4381 + assign { } { } + assign { } { } + assign $0\li[25:0] $1\li[25:0] + attribute \src "libresoc.v:111697.5-111697.29" + switch \initial + attribute \src "libresoc.v:111697.9-111697.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 4'0110 assign { } { } - assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001100 + assign $1\li[25:0] \$16 [25:0] + case + assign $1\li[25:0] 26'00000000000000000000000000 + end + sync always + update \li $0\li[25:0] + end + attribute \src "libresoc.v:111707.3-111717.6" + process $proc$libresoc.v:111707$4382 + assign { } { } + assign { } { } + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "libresoc.v:111708.5-111708.29" + switch \initial + attribute \src "libresoc.v:111708.9-111708.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 4'0111 assign { } { } - assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 + assign $1\bd[15:0] \$19 [15:0] + case + assign $1\bd[15:0] 16'0000000000000000 + end + sync always + update \bd $0\bd[15:0] + end + attribute \src "libresoc.v:111718.3-111728.6" + process $proc$libresoc.v:111718$4383 + assign { } { } + assign { } { } + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "libresoc.v:111719.5-111719.29" + switch \initial + attribute \src "libresoc.v:111719.9-111719.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 4'1000 assign { } { } - assign $1\dec31_dec_sub0_internal_op[6:0] 7'0111011 + assign $1\ds[15:0] \$22 [15:0] case - assign $1\dec31_dec_sub0_internal_op[6:0] 7'0000000 + assign $1\ds[15:0] 16'0000000000000000 end sync always - update \dec31_dec_sub0_internal_op $0\dec31_dec_sub0_internal_op[6:0] + update \ds $0\ds[15:0] + end + connect \$9 $pos$libresoc.v:111559$4364_Y + connect \$11 $pos$libresoc.v:111560$4366_Y + connect \$14 $sshl$libresoc.v:111561$4367_Y + connect \$17 $sshl$libresoc.v:111562$4368_Y + connect \$1 $pos$libresoc.v:111563$4370_Y + connect \$20 $sshl$libresoc.v:111564$4371_Y + connect \$23 $sshl$libresoc.v:111565$4372_Y + connect \$4 $sshl$libresoc.v:111566$4373_Y + connect \$3 $pos$libresoc.v:111567$4375_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 +end +attribute \src "libresoc.v:111737.1-111990.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_bi" +attribute \generator "nMigen" +module \dec_bi$195 + attribute \src "libresoc.v:111964.3-111974.6" + wire width 16 $0\bd[15:0] + attribute \src "libresoc.v:111975.3-111985.6" + wire width 16 $0\ds[15:0] + attribute \src "libresoc.v:111826.3-111872.6" + wire width 64 $0\imm_b[63:0] + attribute \src "libresoc.v:111873.3-111919.6" + wire $0\imm_b_ok[0:0] + attribute \src "libresoc.v:111738.7-111738.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:111953.3-111963.6" + wire width 26 $0\li[25:0] + attribute \src "libresoc.v:111920.3-111930.6" + wire width 16 $0\si[15:0] + attribute \src "libresoc.v:111931.3-111941.6" + wire width 32 $0\si_hi[31:0] + attribute \src "libresoc.v:111942.3-111952.6" + wire width 16 $0\ui[15:0] + attribute \src "libresoc.v:111964.3-111974.6" + wire width 16 $1\bd[15:0] + attribute \src "libresoc.v:111975.3-111985.6" + wire width 16 $1\ds[15:0] + attribute \src "libresoc.v:111826.3-111872.6" + wire width 64 $1\imm_b[63:0] + attribute \src "libresoc.v:111873.3-111919.6" + wire $1\imm_b_ok[0:0] + attribute \src "libresoc.v:111953.3-111963.6" + wire width 26 $1\li[25:0] + attribute \src "libresoc.v:111920.3-111930.6" + wire width 16 $1\si[15:0] + attribute \src "libresoc.v:111931.3-111941.6" + wire width 32 $1\si_hi[31:0] + attribute \src "libresoc.v:111942.3-111952.6" + wire width 16 $1\ui[15:0] + attribute \src "libresoc.v:111816.17-111816.110" + wire width 64 $extend$libresoc.v:111816$4385_Y + attribute \src "libresoc.v:111817.18-111817.113" + wire width 64 $extend$libresoc.v:111817$4387_Y + attribute \src "libresoc.v:111820.17-111820.110" + wire width 64 $extend$libresoc.v:111820$4391_Y + attribute \src "libresoc.v:111824.17-111824.102" + wire width 64 $extend$libresoc.v:111824$4396_Y + attribute \src "libresoc.v:111816.17-111816.110" + wire width 64 $pos$libresoc.v:111816$4386_Y + attribute \src "libresoc.v:111817.18-111817.113" + wire width 64 $pos$libresoc.v:111817$4388_Y + attribute \src "libresoc.v:111820.17-111820.110" + wire width 64 $pos$libresoc.v:111820$4392_Y + attribute \src "libresoc.v:111824.17-111824.102" + wire width 64 $pos$libresoc.v:111824$4397_Y + attribute \src "libresoc.v:111818.18-111818.120" + wire width 47 $sshl$libresoc.v:111818$4389_Y + attribute \src "libresoc.v:111819.18-111819.119" + wire width 27 $sshl$libresoc.v:111819$4390_Y + attribute \src "libresoc.v:111821.18-111821.119" + wire width 17 $sshl$libresoc.v:111821$4393_Y + attribute \src "libresoc.v:111822.18-111822.119" + wire width 17 $sshl$libresoc.v:111822$4394_Y + attribute \src "libresoc.v:111823.17-111823.109" + wire width 47 $sshl$libresoc.v:111823$4395_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 64 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 64 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + wire width 47 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + wire width 47 \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + wire width 27 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + wire width 27 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + wire width 17 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + wire width 17 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + wire width 17 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + wire width 17 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + wire width 47 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:262" + wire width 64 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 64 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 input 8 \SHIFT_ROT_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 input 9 \SHIFT_ROT_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 24 input 7 \SHIFT_ROT_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 5 \SHIFT_ROT_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 input 3 \SHIFT_ROT_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 input 4 \SHIFT_ROT_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 6 input 6 \SHIFT_ROT_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:257" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \imm_b_ok + attribute \src "libresoc.v:111738.7-111738.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:247" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:232" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:111816$4385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \SHIFT_ROT_sh + connect \Y $extend$libresoc.v:111816$4385_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:111817$4387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \SHIFT_ROT_SH32 + connect \Y $extend$libresoc.v:111817$4387_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:111820$4391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \SHIFT_ROT_UI + connect \Y $extend$libresoc.v:111820$4391_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $pos $extend$libresoc.v:111824$4396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$libresoc.v:111824$4396_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:111816$4386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:111816$4385_Y + connect \Y $pos$libresoc.v:111816$4386_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:111817$4388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:111817$4387_Y + connect \Y $pos$libresoc.v:111817$4388_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:111820$4392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:111820$4391_Y + connect \Y $pos$libresoc.v:111820$4392_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $pos $pos$libresoc.v:111824$4397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:111824$4396_Y + connect \Y $pos$libresoc.v:111824$4397_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + cell $sshl $sshl$libresoc.v:111818$4389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \SHIFT_ROT_SI + connect \B 5'10000 + connect \Y $sshl$libresoc.v:111818$4389_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + cell $sshl $sshl$libresoc.v:111819$4390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \SHIFT_ROT_LI + connect \B 2'10 + connect \Y $sshl$libresoc.v:111819$4390_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + cell $sshl $sshl$libresoc.v:111821$4393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \SHIFT_ROT_BD + connect \B 2'10 + connect \Y $sshl$libresoc.v:111821$4393_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + cell $sshl $sshl$libresoc.v:111822$4394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \SHIFT_ROT_DS + connect \B 2'10 + connect \Y $sshl$libresoc.v:111822$4394_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $sshl $sshl$libresoc.v:111823$4395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$libresoc.v:111823$4395_Y + end + attribute \src "libresoc.v:111738.7-111738.20" + process $proc$libresoc.v:111738$4406 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:18691.3-18709.6" - process $proc$libresoc.v:18691$419 + attribute \src "libresoc.v:111826.3-111872.6" + process $proc$libresoc.v:111826$4398 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_rsrv[0:0] $1\dec31_dec_sub0_rsrv[0:0] - attribute \src "libresoc.v:18692.5-18692.29" + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "libresoc.v:111827.5-111827.29" switch \initial - attribute \src "libresoc.v:18692.9-18692.17" + attribute \src "libresoc.v:111827.9-111827.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 4'0010 assign { } { } - assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + assign $1\imm_b[63:0] \$1 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 4'0011 assign { } { } - assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 4'0101 assign { } { } - assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 4'0100 assign { } { } - assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + assign $1\imm_b[63:0] \$3 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 case - assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \dec31_dec_sub0_rsrv $0\dec31_dec_sub0_rsrv[0:0] + update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:18710.3-18728.6" - process $proc$libresoc.v:18710$420 + attribute \src "libresoc.v:111873.3-111919.6" + process $proc$libresoc.v:111873$4399 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_is_32b[0:0] $1\dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:18711.5-18711.29" + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "libresoc.v:111874.5-111874.29" switch \initial - attribute \src "libresoc.v:18711.9-18711.17" + attribute \src "libresoc.v:111874.9-111874.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 4'0010 assign { } { } - assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 4'0011 assign { } { } - assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 4'0101 assign { } { } - assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 4'0100 assign { } { } - assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 case - assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + assign $1\imm_b_ok[0:0] 1'0 end sync always - update \dec31_dec_sub0_is_32b $0\dec31_dec_sub0_is_32b[0:0] + update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:18729.3-18747.6" - process $proc$libresoc.v:18729$421 + attribute \src "libresoc.v:111920.3-111930.6" + process $proc$libresoc.v:111920$4400 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_sgn[0:0] $1\dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:18730.5-18730.29" + assign $0\si[15:0] $1\si[15:0] + attribute \src "libresoc.v:111921.5-111921.29" switch \initial - attribute \src "libresoc.v:18730.9-18730.17" + attribute \src "libresoc.v:111921.9-111921.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 4'0011 assign { } { } - assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + assign $1\si[15:0] \SHIFT_ROT_SI + case + assign $1\si[15:0] 16'0000000000000000 + end + sync always + update \si $0\si[15:0] + end + attribute \src "libresoc.v:111931.3-111941.6" + process $proc$libresoc.v:111931$4401 + assign { } { } + assign { } { } + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "libresoc.v:111932.5-111932.29" + switch \initial + attribute \src "libresoc.v:111932.9-111932.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 4'0101 assign { } { } - assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + assign $1\si_hi[31:0] \$13 [31:0] case - assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + assign $1\si_hi[31:0] 0 end sync always - update \dec31_dec_sub0_sgn $0\dec31_dec_sub0_sgn[0:0] + update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:18748.3-18766.6" - process $proc$libresoc.v:18748$422 + attribute \src "libresoc.v:111942.3-111952.6" + process $proc$libresoc.v:111942$4402 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_lk[0:0] $1\dec31_dec_sub0_lk[0:0] - attribute \src "libresoc.v:18749.5-18749.29" + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "libresoc.v:111943.5-111943.29" switch \initial - attribute \src "libresoc.v:18749.9-18749.17" + attribute \src "libresoc.v:111943.9-111943.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 4'0100 assign { } { } - assign $1\dec31_dec_sub0_lk[0:0] 1'0 + assign $1\ui[15:0] \SHIFT_ROT_UI + case + assign $1\ui[15:0] 16'0000000000000000 + end + sync always + update \ui $0\ui[15:0] + end + attribute \src "libresoc.v:111953.3-111963.6" + process $proc$libresoc.v:111953$4403 + assign { } { } + assign { } { } + assign $0\li[25:0] $1\li[25:0] + attribute \src "libresoc.v:111954.5-111954.29" + switch \initial + attribute \src "libresoc.v:111954.9-111954.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 4'0110 assign { } { } - assign $1\dec31_dec_sub0_lk[0:0] 1'0 + assign $1\li[25:0] \$16 [25:0] + case + assign $1\li[25:0] 26'00000000000000000000000000 + end + sync always + update \li $0\li[25:0] + end + attribute \src "libresoc.v:111964.3-111974.6" + process $proc$libresoc.v:111964$4404 + assign { } { } + assign { } { } + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "libresoc.v:111965.5-111965.29" + switch \initial + attribute \src "libresoc.v:111965.9-111965.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 4'0111 assign { } { } - assign $1\dec31_dec_sub0_lk[0:0] 1'0 + assign $1\bd[15:0] \$19 [15:0] + case + assign $1\bd[15:0] 16'0000000000000000 + end + sync always + update \bd $0\bd[15:0] + end + attribute \src "libresoc.v:111975.3-111985.6" + process $proc$libresoc.v:111975$4405 + assign { } { } + assign { } { } + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "libresoc.v:111976.5-111976.29" + switch \initial + attribute \src "libresoc.v:111976.9-111976.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 4'1000 assign { } { } - assign $1\dec31_dec_sub0_lk[0:0] 1'0 + assign $1\ds[15:0] \$22 [15:0] case - assign $1\dec31_dec_sub0_lk[0:0] 1'0 + assign $1\ds[15:0] 16'0000000000000000 end sync always - update \dec31_dec_sub0_lk $0\dec31_dec_sub0_lk[0:0] + update \ds $0\ds[15:0] + end + connect \$9 $pos$libresoc.v:111816$4386_Y + connect \$11 $pos$libresoc.v:111817$4388_Y + connect \$14 $sshl$libresoc.v:111818$4389_Y + connect \$17 $sshl$libresoc.v:111819$4390_Y + connect \$1 $pos$libresoc.v:111820$4392_Y + connect \$20 $sshl$libresoc.v:111821$4393_Y + connect \$23 $sshl$libresoc.v:111822$4394_Y + connect \$4 $sshl$libresoc.v:111823$4395_Y + connect \$3 $pos$libresoc.v:111824$4397_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 +end +attribute \src "libresoc.v:111994.1-112247.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_bi" +attribute \generator "nMigen" +module \dec_bi$204 + attribute \src "libresoc.v:112221.3-112231.6" + wire width 16 $0\bd[15:0] + attribute \src "libresoc.v:112232.3-112242.6" + wire width 16 $0\ds[15:0] + attribute \src "libresoc.v:112083.3-112129.6" + wire width 64 $0\imm_b[63:0] + attribute \src "libresoc.v:112130.3-112176.6" + wire $0\imm_b_ok[0:0] + attribute \src "libresoc.v:111995.7-111995.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:112210.3-112220.6" + wire width 26 $0\li[25:0] + attribute \src "libresoc.v:112177.3-112187.6" + wire width 16 $0\si[15:0] + attribute \src "libresoc.v:112188.3-112198.6" + wire width 32 $0\si_hi[31:0] + attribute \src "libresoc.v:112199.3-112209.6" + wire width 16 $0\ui[15:0] + attribute \src "libresoc.v:112221.3-112231.6" + wire width 16 $1\bd[15:0] + attribute \src "libresoc.v:112232.3-112242.6" + wire width 16 $1\ds[15:0] + attribute \src "libresoc.v:112083.3-112129.6" + wire width 64 $1\imm_b[63:0] + attribute \src "libresoc.v:112130.3-112176.6" + wire $1\imm_b_ok[0:0] + attribute \src "libresoc.v:112210.3-112220.6" + wire width 26 $1\li[25:0] + attribute \src "libresoc.v:112177.3-112187.6" + wire width 16 $1\si[15:0] + attribute \src "libresoc.v:112188.3-112198.6" + wire width 32 $1\si_hi[31:0] + attribute \src "libresoc.v:112199.3-112209.6" + wire width 16 $1\ui[15:0] + attribute \src "libresoc.v:112073.17-112073.105" + wire width 64 $extend$libresoc.v:112073$4407_Y + attribute \src "libresoc.v:112074.18-112074.108" + wire width 64 $extend$libresoc.v:112074$4409_Y + attribute \src "libresoc.v:112077.17-112077.105" + wire width 64 $extend$libresoc.v:112077$4413_Y + attribute \src "libresoc.v:112081.17-112081.102" + wire width 64 $extend$libresoc.v:112081$4418_Y + attribute \src "libresoc.v:112073.17-112073.105" + wire width 64 $pos$libresoc.v:112073$4408_Y + attribute \src "libresoc.v:112074.18-112074.108" + wire width 64 $pos$libresoc.v:112074$4410_Y + attribute \src "libresoc.v:112077.17-112077.105" + wire width 64 $pos$libresoc.v:112077$4414_Y + attribute \src "libresoc.v:112081.17-112081.102" + wire width 64 $pos$libresoc.v:112081$4419_Y + attribute \src "libresoc.v:112075.18-112075.115" + wire width 47 $sshl$libresoc.v:112075$4411_Y + attribute \src "libresoc.v:112076.18-112076.114" + wire width 27 $sshl$libresoc.v:112076$4412_Y + attribute \src "libresoc.v:112078.18-112078.114" + wire width 17 $sshl$libresoc.v:112078$4415_Y + attribute \src "libresoc.v:112079.18-112079.114" + wire width 17 $sshl$libresoc.v:112079$4416_Y + attribute \src "libresoc.v:112080.17-112080.109" + wire width 47 $sshl$libresoc.v:112080$4417_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 64 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 64 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + wire width 47 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + wire width 47 \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + wire width 27 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + wire width 27 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + wire width 17 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + wire width 17 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + wire width 17 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + wire width 17 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + wire width 47 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:262" + wire width 64 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 64 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 input 8 \LDST_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 input 9 \LDST_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 24 input 7 \LDST_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 5 \LDST_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 input 3 \LDST_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 input 4 \LDST_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 6 input 6 \LDST_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:257" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \imm_b_ok + attribute \src "libresoc.v:111995.7-111995.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:247" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:232" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:112073$4407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \LDST_sh + connect \Y $extend$libresoc.v:112073$4407_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:112074$4409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \LDST_SH32 + connect \Y $extend$libresoc.v:112074$4409_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:112077$4413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \LDST_UI + connect \Y $extend$libresoc.v:112077$4413_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $pos $extend$libresoc.v:112081$4418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$libresoc.v:112081$4418_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:112073$4408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:112073$4407_Y + connect \Y $pos$libresoc.v:112073$4408_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:112074$4410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:112074$4409_Y + connect \Y $pos$libresoc.v:112074$4410_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:112077$4414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:112077$4413_Y + connect \Y $pos$libresoc.v:112077$4414_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $pos $pos$libresoc.v:112081$4419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:112081$4418_Y + connect \Y $pos$libresoc.v:112081$4419_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + cell $sshl $sshl$libresoc.v:112075$4411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \LDST_SI + connect \B 5'10000 + connect \Y $sshl$libresoc.v:112075$4411_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + cell $sshl $sshl$libresoc.v:112076$4412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \LDST_LI + connect \B 2'10 + connect \Y $sshl$libresoc.v:112076$4412_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + cell $sshl $sshl$libresoc.v:112078$4415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \LDST_BD + connect \B 2'10 + connect \Y $sshl$libresoc.v:112078$4415_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + cell $sshl $sshl$libresoc.v:112079$4416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \LDST_DS + connect \B 2'10 + connect \Y $sshl$libresoc.v:112079$4416_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $sshl $sshl$libresoc.v:112080$4417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$libresoc.v:112080$4417_Y + end + attribute \src "libresoc.v:111995.7-111995.20" + process $proc$libresoc.v:111995$4428 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:18767.3-18785.6" - process $proc$libresoc.v:18767$423 + attribute \src "libresoc.v:112083.3-112129.6" + process $proc$libresoc.v:112083$4420 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_sgl_pipe[0:0] $1\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "libresoc.v:18768.5-18768.29" + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "libresoc.v:112084.5-112084.29" switch \initial - attribute \src "libresoc.v:18768.9-18768.17" + attribute \src "libresoc.v:112084.9-112084.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 4'0010 assign { } { } - assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + assign $1\imm_b[63:0] \$1 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 4'0011 assign { } { } - assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 4'0101 assign { } { } - assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 4'0100 assign { } { } - assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + assign $1\imm_b[63:0] \$3 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 case - assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \dec31_dec_sub0_sgl_pipe $0\dec31_dec_sub0_sgl_pipe[0:0] + update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:18786.3-18804.6" - process $proc$libresoc.v:18786$424 + attribute \src "libresoc.v:112130.3-112176.6" + process $proc$libresoc.v:112130$4421 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_form[4:0] $1\dec31_dec_sub0_form[4:0] - attribute \src "libresoc.v:18787.5-18787.29" + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "libresoc.v:112131.5-112131.29" switch \initial - attribute \src "libresoc.v:18787.9-18787.17" + attribute \src "libresoc.v:112131.9-112131.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 4'0010 assign { } { } - assign $1\dec31_dec_sub0_form[4:0] 5'01000 + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 4'0011 assign { } { } - assign $1\dec31_dec_sub0_form[4:0] 5'01000 + assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 4'0101 assign { } { } - assign $1\dec31_dec_sub0_form[4:0] 5'01000 + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + case + assign $1\imm_b_ok[0:0] 1'0 + end + sync always + update \imm_b_ok $0\imm_b_ok[0:0] + end + attribute \src "libresoc.v:112177.3-112187.6" + process $proc$libresoc.v:112177$4422 + assign { } { } + assign { } { } + assign $0\si[15:0] $1\si[15:0] + attribute \src "libresoc.v:112178.5-112178.29" + switch \initial + attribute \src "libresoc.v:112178.9-112178.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 4'0011 assign { } { } - assign $1\dec31_dec_sub0_form[4:0] 5'11000 + assign $1\si[15:0] \LDST_SI case - assign $1\dec31_dec_sub0_form[4:0] 5'00000 + assign $1\si[15:0] 16'0000000000000000 end sync always - update \dec31_dec_sub0_form $0\dec31_dec_sub0_form[4:0] + update \si $0\si[15:0] end - attribute \src "libresoc.v:18805.3-18823.6" - process $proc$libresoc.v:18805$425 + attribute \src "libresoc.v:112188.3-112198.6" + process $proc$libresoc.v:112188$4423 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_in1_sel[2:0] $1\dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:18806.5-18806.29" + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "libresoc.v:112189.5-112189.29" switch \initial - attribute \src "libresoc.v:18806.9-18806.17" + attribute \src "libresoc.v:112189.9-112189.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 4'0101 assign { } { } - assign $1\dec31_dec_sub0_in1_sel[2:0] 3'000 + assign $1\si_hi[31:0] \$13 [31:0] case - assign $1\dec31_dec_sub0_in1_sel[2:0] 3'000 + assign $1\si_hi[31:0] 0 end sync always - update \dec31_dec_sub0_in1_sel $0\dec31_dec_sub0_in1_sel[2:0] + update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:18824.3-18842.6" - process $proc$libresoc.v:18824$426 + attribute \src "libresoc.v:112199.3-112209.6" + process $proc$libresoc.v:112199$4424 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_in2_sel[3:0] $1\dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:18825.5-18825.29" + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "libresoc.v:112200.5-112200.29" switch \initial - attribute \src "libresoc.v:18825.9-18825.17" + attribute \src "libresoc.v:112200.9-112200.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 4'0100 assign { } { } - assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0000 + assign $1\ui[15:0] \LDST_UI case - assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0000 + assign $1\ui[15:0] 16'0000000000000000 end sync always - update \dec31_dec_sub0_in2_sel $0\dec31_dec_sub0_in2_sel[3:0] + update \ui $0\ui[15:0] end - attribute \src "libresoc.v:18843.3-18861.6" - process $proc$libresoc.v:18843$427 + attribute \src "libresoc.v:112210.3-112220.6" + process $proc$libresoc.v:112210$4425 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_in3_sel[1:0] $1\dec31_dec_sub0_in3_sel[1:0] - attribute \src "libresoc.v:18844.5-18844.29" + assign $0\li[25:0] $1\li[25:0] + attribute \src "libresoc.v:112211.5-112211.29" switch \initial - attribute \src "libresoc.v:18844.9-18844.17" + attribute \src "libresoc.v:112211.9-112211.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 4'0110 assign { } { } - assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + assign $1\li[25:0] \$16 [25:0] case - assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + assign $1\li[25:0] 26'00000000000000000000000000 end sync always - update \dec31_dec_sub0_in3_sel $0\dec31_dec_sub0_in3_sel[1:0] + update \li $0\li[25:0] end - attribute \src "libresoc.v:18862.3-18880.6" - process $proc$libresoc.v:18862$428 + attribute \src "libresoc.v:112221.3-112231.6" + process $proc$libresoc.v:112221$4426 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_out_sel[1:0] $1\dec31_dec_sub0_out_sel[1:0] - attribute \src "libresoc.v:18863.5-18863.29" + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "libresoc.v:112222.5-112222.29" switch \initial - attribute \src "libresoc.v:18863.9-18863.17" + attribute \src "libresoc.v:112222.9-112222.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 4'0111 assign { } { } - assign $1\dec31_dec_sub0_out_sel[1:0] 2'01 + assign $1\bd[15:0] \$19 [15:0] case - assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + assign $1\bd[15:0] 16'0000000000000000 end sync always - update \dec31_dec_sub0_out_sel $0\dec31_dec_sub0_out_sel[1:0] + update \bd $0\bd[15:0] end - attribute \src "libresoc.v:18881.3-18899.6" - process $proc$libresoc.v:18881$429 + attribute \src "libresoc.v:112232.3-112242.6" + process $proc$libresoc.v:112232$4427 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_cr_in[2:0] $1\dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:18882.5-18882.29" + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "libresoc.v:112233.5-112233.29" switch \initial - attribute \src "libresoc.v:18882.9-18882.17" + attribute \src "libresoc.v:112233.9-112233.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 4'1000 assign { } { } - assign $1\dec31_dec_sub0_cr_in[2:0] 3'011 + assign $1\ds[15:0] \$22 [15:0] case - assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + assign $1\ds[15:0] 16'0000000000000000 end sync always - update \dec31_dec_sub0_cr_in $0\dec31_dec_sub0_cr_in[2:0] + update \ds $0\ds[15:0] + end + connect \$9 $pos$libresoc.v:112073$4408_Y + connect \$11 $pos$libresoc.v:112074$4410_Y + connect \$14 $sshl$libresoc.v:112075$4411_Y + connect \$17 $sshl$libresoc.v:112076$4412_Y + connect \$1 $pos$libresoc.v:112077$4414_Y + connect \$20 $sshl$libresoc.v:112078$4415_Y + connect \$23 $sshl$libresoc.v:112079$4416_Y + connect \$4 $sshl$libresoc.v:112080$4417_Y + connect \$3 $pos$libresoc.v:112081$4419_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 +end +attribute \src "libresoc.v:112251.1-112299.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_c" +attribute \generator "nMigen" +module \dec_c + attribute \src "libresoc.v:112252.7-112252.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:112269.3-112283.6" + wire width 5 $0\reg_c[4:0] + attribute \src "libresoc.v:112284.3-112298.6" + wire $0\reg_c_ok[0:0] + attribute \src "libresoc.v:112269.3-112283.6" + wire width 5 $1\reg_c[4:0] + attribute \src "libresoc.v:112284.3-112298.6" + wire $1\reg_c_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 4 \RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 3 \RS + attribute \src "libresoc.v:112252.7-112252.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 output 1 \reg_c + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \reg_c_ok + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:282" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:112252.7-112252.20" + process $proc$libresoc.v:112252$4431 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:18900.3-18918.6" - process $proc$libresoc.v:18900$430 + attribute \src "libresoc.v:112269.3-112283.6" + process $proc$libresoc.v:112269$4429 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_cr_out[2:0] $1\dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:18901.5-18901.29" + assign $0\reg_c[4:0] $1\reg_c[4:0] + attribute \src "libresoc.v:112270.5-112270.29" switch \initial - attribute \src "libresoc.v:18901.9-18901.17" + attribute \src "libresoc.v:112270.9-112270.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 2'10 assign { } { } - assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 + assign $1\reg_c[4:0] \RB attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 2'01 assign { } { } - assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 + assign $1\reg_c[4:0] \RS + case + assign $1\reg_c[4:0] 5'00000 + end + sync always + update \reg_c $0\reg_c[4:0] + end + attribute \src "libresoc.v:112284.3-112298.6" + process $proc$libresoc.v:112284$4430 + assign { } { } + assign { } { } + assign $0\reg_c_ok[0:0] $1\reg_c_ok[0:0] + attribute \src "libresoc.v:112285.5-112285.29" + switch \initial + attribute \src "libresoc.v:112285.9-112285.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 2'10 assign { } { } - assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 + assign $1\reg_c_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 2'01 assign { } { } - assign $1\dec31_dec_sub0_cr_out[2:0] 3'000 + assign $1\reg_c_ok[0:0] 1'1 case - assign $1\dec31_dec_sub0_cr_out[2:0] 3'000 + assign $1\reg_c_ok[0:0] 1'0 end sync always - update \dec31_dec_sub0_cr_out $0\dec31_dec_sub0_cr_out[2:0] + update \reg_c_ok $0\reg_c_ok[0:0] end - connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:18924.1-20071.10" +attribute \src "libresoc.v:112303.1-112600.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub10" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_cr_in" attribute \generator "nMigen" -module \dec31_dec_sub10 - attribute \src "libresoc.v:19367.3-19403.6" - wire width 8 $0\dec31_dec_sub10_asmcode[7:0] - attribute \src "libresoc.v:19515.3-19551.6" - wire $0\dec31_dec_sub10_br[0:0] - attribute \src "libresoc.v:19996.3-20032.6" - wire width 3 $0\dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:20033.3-20069.6" - wire width 3 $0\dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:19330.3-19366.6" - wire width 2 $0\dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:19478.3-19514.6" - wire $0\dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:19811.3-19847.6" - wire width 5 $0\dec31_dec_sub10_form[4:0] - attribute \src "libresoc.v:19182.3-19218.6" - wire width 12 $0\dec31_dec_sub10_function_unit[11:0] - attribute \src "libresoc.v:19848.3-19884.6" - wire width 3 $0\dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:19885.3-19921.6" - wire width 4 $0\dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:19922.3-19958.6" - wire width 2 $0\dec31_dec_sub10_in3_sel[1:0] - attribute \src "libresoc.v:19589.3-19625.6" - wire width 7 $0\dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:19404.3-19440.6" - wire $0\dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:19441.3-19477.6" - wire $0\dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:19663.3-19699.6" - wire $0\dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:19219.3-19255.6" - wire width 4 $0\dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:19737.3-19773.6" - wire $0\dec31_dec_sub10_lk[0:0] - attribute \src "libresoc.v:19959.3-19995.6" - wire width 2 $0\dec31_dec_sub10_out_sel[1:0] - attribute \src "libresoc.v:19293.3-19329.6" - wire width 2 $0\dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:19626.3-19662.6" - wire $0\dec31_dec_sub10_rsrv[0:0] - attribute \src "libresoc.v:19774.3-19810.6" - wire $0\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "libresoc.v:19700.3-19736.6" - wire $0\dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:19552.3-19588.6" - wire $0\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "libresoc.v:19256.3-19292.6" - wire width 2 $0\dec31_dec_sub10_upd[1:0] - attribute \src "libresoc.v:18925.7-18925.20" +module \dec_cr_in + attribute \src "libresoc.v:112494.3-112520.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:112521.3-112531.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "libresoc.v:112472.3-112482.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:112532.3-112542.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "libresoc.v:112543.3-112553.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:112445.3-112471.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:112581.3-112599.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:112483.3-112493.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:112304.7-112304.20" wire $0\initial[0:0] - attribute \src "libresoc.v:19367.3-19403.6" - wire width 8 $1\dec31_dec_sub10_asmcode[7:0] - attribute \src "libresoc.v:19515.3-19551.6" - wire $1\dec31_dec_sub10_br[0:0] - attribute \src "libresoc.v:19996.3-20032.6" - wire width 3 $1\dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:20033.3-20069.6" - wire width 3 $1\dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:19330.3-19366.6" - wire width 2 $1\dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:19478.3-19514.6" - wire $1\dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:19811.3-19847.6" - wire width 5 $1\dec31_dec_sub10_form[4:0] - attribute \src "libresoc.v:19182.3-19218.6" - wire width 12 $1\dec31_dec_sub10_function_unit[11:0] - attribute \src "libresoc.v:19848.3-19884.6" - wire width 3 $1\dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:19885.3-19921.6" - wire width 4 $1\dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:19922.3-19958.6" - wire width 2 $1\dec31_dec_sub10_in3_sel[1:0] - attribute \src "libresoc.v:19589.3-19625.6" - wire width 7 $1\dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:19404.3-19440.6" - wire $1\dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:19441.3-19477.6" - wire $1\dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:19663.3-19699.6" - wire $1\dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:19219.3-19255.6" - wire width 4 $1\dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:19737.3-19773.6" - wire $1\dec31_dec_sub10_lk[0:0] - attribute \src "libresoc.v:19959.3-19995.6" - wire width 2 $1\dec31_dec_sub10_out_sel[1:0] - attribute \src "libresoc.v:19293.3-19329.6" - wire width 2 $1\dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:19626.3-19662.6" - wire $1\dec31_dec_sub10_rsrv[0:0] - attribute \src "libresoc.v:19774.3-19810.6" - wire $1\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "libresoc.v:19700.3-19736.6" - wire $1\dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:19552.3-19588.6" - wire $1\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "libresoc.v:19256.3-19292.6" - wire width 2 $1\dec31_dec_sub10_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub10_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub10_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub10_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub10_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub10_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub10_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub10_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub10_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub10_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub10_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub10_in3_sel + attribute \src "libresoc.v:112554.3-112564.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:112565.3-112580.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:112494.3-112520.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:112521.3-112531.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:112472.3-112482.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:112532.3-112542.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:112543.3-112553.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:112445.3-112471.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:112581.3-112599.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:112483.3-112493.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:112554.3-112564.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:112565.3-112580.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:112581.3-112599.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:112565.3-112580.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:112438.17-112438.112" + wire $and$libresoc.v:112438$4433_Y + attribute \src "libresoc.v:112440.17-112440.112" + wire $and$libresoc.v:112440$4435_Y + attribute \src "libresoc.v:112437.17-112437.121" + wire $eq$libresoc.v:112437$4432_Y + attribute \src "libresoc.v:112439.17-112439.121" + wire $eq$libresoc.v:112439$4434_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 4 \ALU_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 3 \ALU_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 8 \ALU_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 7 \ALU_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 5 \ALU_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 input 6 \ALU_FXM attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -27530,1694 +175747,1545 @@ module \dec31_dec_sub10 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub10_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub10_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub10_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub10_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub10_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub10_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub10_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub10_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub10_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub10_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub10_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub10_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub10_upd - attribute \src "libresoc.v:18925.7-18925.15" + wire width 7 input 2 \ALU_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_fxm_ok + attribute \src "libresoc.v:112304.7-112304.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:18925.7-18925.20" - process $proc$libresoc.v:18925$456 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" + wire width 32 input 10 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:112438$4433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$libresoc.v:112438$4433_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:112440$4435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$libresoc.v:112440$4435_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:112437$4432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \ALU_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:112437$4432_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:112439$4434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \ALU_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:112439$4434_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:112441.9-112444.4" + cell \ppick \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:112304.7-112304.20" + process $proc$libresoc.v:112304$4446 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:19182.3-19218.6" - process $proc$libresoc.v:19182$432 + attribute \src "libresoc.v:112445.3-112471.6" + process $proc$libresoc.v:112445$4436 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_function_unit[11:0] $1\dec31_dec_sub10_function_unit[11:0] - attribute \src "libresoc.v:19183.5-19183.29" + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:112446.5-112446.29" switch \initial - attribute \src "libresoc.v:19183.9-19183.17" + attribute \src "libresoc.v:112446.9-112446.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 3'001 assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 3'010 assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 3'011 assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 3'100 assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 3'101 assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + assign $1\cr_bitfield_ok[0:0] 1'1 case - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000000 + assign $1\cr_bitfield_ok[0:0] 1'0 end sync always - update \dec31_dec_sub10_function_unit $0\dec31_dec_sub10_function_unit[11:0] + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:19219.3-19255.6" - process $proc$libresoc.v:19219$433 + attribute \src "libresoc.v:112472.3-112482.6" + process $proc$libresoc.v:112472$4437 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_ldst_len[3:0] $1\dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:19220.5-19220.29" + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:112473.5-112473.29" switch \initial - attribute \src "libresoc.v:19220.9-19220.17" + attribute \src "libresoc.v:112473.9-112473.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 3'100 assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + assign $1\cr_bitfield_b_ok[0:0] 1'1 case - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + assign $1\cr_bitfield_b_ok[0:0] 1'0 end sync always - update \dec31_dec_sub10_ldst_len $0\dec31_dec_sub10_ldst_len[3:0] + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] end - attribute \src "libresoc.v:19256.3-19292.6" - process $proc$libresoc.v:19256$434 + attribute \src "libresoc.v:112483.3-112493.6" + process $proc$libresoc.v:112483$4438 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_upd[1:0] $1\dec31_dec_sub10_upd[1:0] - attribute \src "libresoc.v:19257.5-19257.29" + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:112484.5-112484.29" switch \initial - attribute \src "libresoc.v:19257.9-19257.17" + attribute \src "libresoc.v:112484.9-112484.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 3'110 assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 + assign $1\cr_fxm_ok[0:0] 1'1 case - assign $1\dec31_dec_sub10_upd[1:0] 2'00 + assign $1\cr_fxm_ok[0:0] 1'0 end sync always - update \dec31_dec_sub10_upd $0\dec31_dec_sub10_upd[1:0] + update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:19293.3-19329.6" - process $proc$libresoc.v:19293$435 + attribute \src "libresoc.v:112494.3-112520.6" + process $proc$libresoc.v:112494$4439 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_rc_sel[1:0] $1\dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:19294.5-19294.29" + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:112495.5-112495.29" switch \initial - attribute \src "libresoc.v:19294.9-19294.17" + attribute \src "libresoc.v:112495.9-112495.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 3'001 assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + assign $1\cr_bitfield[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 3'010 assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + assign $1\cr_bitfield[2:0] \ALU_BI [4:2] attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 3'011 assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + assign $1\cr_bitfield[2:0] \X_BFA attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 3'100 assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + assign $1\cr_bitfield[2:0] \ALU_BA [4:2] attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 3'101 assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + assign $1\cr_bitfield[2:0] \ALU_BC [4:2] case - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'00 + assign $1\cr_bitfield[2:0] 3'000 end sync always - update \dec31_dec_sub10_rc_sel $0\dec31_dec_sub10_rc_sel[1:0] + update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:19330.3-19366.6" - process $proc$libresoc.v:19330$436 + attribute \src "libresoc.v:112521.3-112531.6" + process $proc$libresoc.v:112521$4440 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_cry_in[1:0] $1\dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:19331.5-19331.29" + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:112522.5-112522.29" switch \initial - attribute \src "libresoc.v:19331.9-19331.17" + attribute \src "libresoc.v:112522.9-112522.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 3'100 assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + assign $1\cr_bitfield_b[2:0] \ALU_BB [4:2] case - assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + assign $1\cr_bitfield_b[2:0] 3'000 end sync always - update \dec31_dec_sub10_cry_in $0\dec31_dec_sub10_cry_in[1:0] + update \cr_bitfield_b $0\cr_bitfield_b[2:0] end - attribute \src "libresoc.v:19367.3-19403.6" - process $proc$libresoc.v:19367$437 + attribute \src "libresoc.v:112532.3-112542.6" + process $proc$libresoc.v:112532$4441 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_asmcode[7:0] $1\dec31_dec_sub10_asmcode[7:0] - attribute \src "libresoc.v:19368.5-19368.29" + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:112533.5-112533.29" switch \initial - attribute \src "libresoc.v:19368.9-19368.17" + attribute \src "libresoc.v:112533.9-112533.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 3'100 assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000101 + assign $1\cr_bitfield_o[2:0] \ALU_BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] + end + attribute \src "libresoc.v:112543.3-112553.6" + process $proc$libresoc.v:112543$4442 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:112544.5-112544.29" + switch \initial + attribute \src "libresoc.v:112544.9-112544.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 3'100 assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001010 + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "libresoc.v:112554.3-112564.6" + process $proc$libresoc.v:112554$4443 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:112555.5-112555.29" + switch \initial + attribute \src "libresoc.v:112555.9-112555.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 3'110 assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001011 + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:112565.3-112580.6" + process $proc$libresoc.v:112565$4444 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:112566.5-112566.29" + switch \initial + attribute \src "libresoc.v:112566.9-112566.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 3'110 assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001101 + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \ALU_FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:112581.3-112599.6" + process $proc$libresoc.v:112581$4445 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:112582.5-112582.29" + switch \initial + attribute \src "libresoc.v:112582.9-112582.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 3'110 assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001110 + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end case - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000000 + assign $1\cr_fxm[7:0] 8'00000000 end sync always - update \dec31_dec_sub10_asmcode $0\dec31_dec_sub10_asmcode[7:0] + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:112437$4432_Y + connect \$3 $and$libresoc.v:112438$4433_Y + connect \$5 $eq$libresoc.v:112439$4434_Y + connect \$7 $and$libresoc.v:112440$4435_Y +end +attribute \src "libresoc.v:112604.1-112901.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_cr_in" +attribute \generator "nMigen" +module \dec_cr_in$143 + attribute \src "libresoc.v:112795.3-112821.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:112822.3-112832.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "libresoc.v:112773.3-112783.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:112833.3-112843.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "libresoc.v:112844.3-112854.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:112746.3-112772.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:112882.3-112900.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:112784.3-112794.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:112605.7-112605.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:112855.3-112865.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:112866.3-112881.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:112795.3-112821.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:112822.3-112832.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:112773.3-112783.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:112833.3-112843.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:112844.3-112854.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:112746.3-112772.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:112882.3-112900.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:112784.3-112794.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:112855.3-112865.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:112866.3-112881.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:112882.3-112900.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:112866.3-112881.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:112739.17-112739.112" + wire $and$libresoc.v:112739$4448_Y + attribute \src "libresoc.v:112741.17-112741.112" + wire $and$libresoc.v:112741$4450_Y + attribute \src "libresoc.v:112738.17-112738.120" + wire $eq$libresoc.v:112738$4447_Y + attribute \src "libresoc.v:112740.17-112740.120" + wire $eq$libresoc.v:112740$4449_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 4 \CR_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 3 \CR_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 8 \CR_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 7 \CR_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 5 \CR_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 input 6 \CR_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 input 2 \CR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_fxm_ok + attribute \src "libresoc.v:112605.7-112605.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" + wire width 32 input 10 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:112739$4448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$libresoc.v:112739$4448_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:112741$4450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$libresoc.v:112741$4450_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:112738$4447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \CR_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:112738$4447_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:112740$4449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \CR_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:112740$4449_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:112742.15-112745.4" + cell \ppick$144 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:112605.7-112605.20" + process $proc$libresoc.v:112605$4461 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:19404.3-19440.6" - process $proc$libresoc.v:19404$438 + attribute \src "libresoc.v:112746.3-112772.6" + process $proc$libresoc.v:112746$4451 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_inv_a[0:0] $1\dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:19405.5-19405.29" + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:112747.5-112747.29" switch \initial - attribute \src "libresoc.v:19405.9-19405.17" + attribute \src "libresoc.v:112747.9-112747.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 3'001 assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 3'010 assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 3'011 assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 3'100 assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 3'101 assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + assign $1\cr_bitfield_ok[0:0] 1'1 case - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + assign $1\cr_bitfield_ok[0:0] 1'0 end sync always - update \dec31_dec_sub10_inv_a $0\dec31_dec_sub10_inv_a[0:0] + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:19441.3-19477.6" - process $proc$libresoc.v:19441$439 + attribute \src "libresoc.v:112773.3-112783.6" + process $proc$libresoc.v:112773$4452 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_inv_out[0:0] $1\dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:19442.5-19442.29" + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:112774.5-112774.29" switch \initial - attribute \src "libresoc.v:19442.9-19442.17" + attribute \src "libresoc.v:112774.9-112774.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 3'100 assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + assign $1\cr_bitfield_b_ok[0:0] 1'1 case - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + assign $1\cr_bitfield_b_ok[0:0] 1'0 end sync always - update \dec31_dec_sub10_inv_out $0\dec31_dec_sub10_inv_out[0:0] + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] end - attribute \src "libresoc.v:19478.3-19514.6" - process $proc$libresoc.v:19478$440 + attribute \src "libresoc.v:112784.3-112794.6" + process $proc$libresoc.v:112784$4453 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_cry_out[0:0] $1\dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:19479.5-19479.29" + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:112785.5-112785.29" switch \initial - attribute \src "libresoc.v:19479.9-19479.17" + attribute \src "libresoc.v:112785.9-112785.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 3'110 assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + assign $1\cr_fxm_ok[0:0] 1'1 case - assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 + assign $1\cr_fxm_ok[0:0] 1'0 end sync always - update \dec31_dec_sub10_cry_out $0\dec31_dec_sub10_cry_out[0:0] + update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:19515.3-19551.6" - process $proc$libresoc.v:19515$441 + attribute \src "libresoc.v:112795.3-112821.6" + process $proc$libresoc.v:112795$4454 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_br[0:0] $1\dec31_dec_sub10_br[0:0] - attribute \src "libresoc.v:19516.5-19516.29" + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:112796.5-112796.29" switch \initial - attribute \src "libresoc.v:19516.9-19516.17" + attribute \src "libresoc.v:112796.9-112796.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 3'001 assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 + assign $1\cr_bitfield[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 3'010 assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 + assign $1\cr_bitfield[2:0] \CR_BI [4:2] attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 3'011 assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 + assign $1\cr_bitfield[2:0] \X_BFA attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 3'100 assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 + assign $1\cr_bitfield[2:0] \CR_BA [4:2] attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 3'101 assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 + assign $1\cr_bitfield[2:0] \CR_BC [4:2] case - assign $1\dec31_dec_sub10_br[0:0] 1'0 + assign $1\cr_bitfield[2:0] 3'000 end sync always - update \dec31_dec_sub10_br $0\dec31_dec_sub10_br[0:0] + update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:19552.3-19588.6" - process $proc$libresoc.v:19552$442 + attribute \src "libresoc.v:112822.3-112832.6" + process $proc$libresoc.v:112822$4455 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_sgn_ext[0:0] $1\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "libresoc.v:19553.5-19553.29" + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:112823.5-112823.29" switch \initial - attribute \src "libresoc.v:19553.9-19553.17" + attribute \src "libresoc.v:112823.9-112823.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 3'100 assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + assign $1\cr_bitfield_b[2:0] \CR_BB [4:2] case - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + assign $1\cr_bitfield_b[2:0] 3'000 end sync always - update \dec31_dec_sub10_sgn_ext $0\dec31_dec_sub10_sgn_ext[0:0] + update \cr_bitfield_b $0\cr_bitfield_b[2:0] end - attribute \src "libresoc.v:19589.3-19625.6" - process $proc$libresoc.v:19589$443 + attribute \src "libresoc.v:112833.3-112843.6" + process $proc$libresoc.v:112833$4456 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_internal_op[6:0] $1\dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:19590.5-19590.29" + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:112834.5-112834.29" switch \initial - attribute \src "libresoc.v:19590.9-19590.17" + attribute \src "libresoc.v:112834.9-112834.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 3'100 assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + assign $1\cr_bitfield_o[2:0] \CR_BT [4:2] case - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000000 + assign $1\cr_bitfield_o[2:0] 3'000 end sync always - update \dec31_dec_sub10_internal_op $0\dec31_dec_sub10_internal_op[6:0] + update \cr_bitfield_o $0\cr_bitfield_o[2:0] end - attribute \src "libresoc.v:19626.3-19662.6" - process $proc$libresoc.v:19626$444 + attribute \src "libresoc.v:112844.3-112854.6" + process $proc$libresoc.v:112844$4457 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_rsrv[0:0] $1\dec31_dec_sub10_rsrv[0:0] - attribute \src "libresoc.v:19627.5-19627.29" + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:112845.5-112845.29" switch \initial - attribute \src "libresoc.v:19627.9-19627.17" + attribute \src "libresoc.v:112845.9-112845.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 3'100 assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + assign $1\cr_bitfield_o_ok[0:0] 1'1 case - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + assign $1\cr_bitfield_o_ok[0:0] 1'0 end sync always - update \dec31_dec_sub10_rsrv $0\dec31_dec_sub10_rsrv[0:0] + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] end - attribute \src "libresoc.v:19663.3-19699.6" - process $proc$libresoc.v:19663$445 + attribute \src "libresoc.v:112855.3-112865.6" + process $proc$libresoc.v:112855$4458 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_is_32b[0:0] $1\dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:19664.5-19664.29" + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:112856.5-112856.29" switch \initial - attribute \src "libresoc.v:19664.9-19664.17" + attribute \src "libresoc.v:112856.9-112856.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 3'110 assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + assign $1\move_one[0:0] \insn_in [20] case - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + assign $1\move_one[0:0] 1'0 end sync always - update \dec31_dec_sub10_is_32b $0\dec31_dec_sub10_is_32b[0:0] + update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:19700.3-19736.6" - process $proc$libresoc.v:19700$446 + attribute \src "libresoc.v:112866.3-112881.6" + process $proc$libresoc.v:112866$4459 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_sgn[0:0] $1\dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:19701.5-19701.29" + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:112867.5-112867.29" switch \initial - attribute \src "libresoc.v:19701.9-19701.17" + attribute \src "libresoc.v:112867.9-112867.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 3'110 assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \CR_FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end case - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + assign $1\ppick_i[7:0] 8'00000000 end sync always - update \dec31_dec_sub10_sgn $0\dec31_dec_sub10_sgn[0:0] + update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:19737.3-19773.6" - process $proc$libresoc.v:19737$447 + attribute \src "libresoc.v:112882.3-112900.6" + process $proc$libresoc.v:112882$4460 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_lk[0:0] $1\dec31_dec_sub10_lk[0:0] - attribute \src "libresoc.v:19738.5-19738.29" + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:112883.5-112883.29" switch \initial - attribute \src "libresoc.v:19738.9-19738.17" + attribute \src "libresoc.v:112883.9-112883.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 3'110 assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end case - assign $1\dec31_dec_sub10_lk[0:0] 1'0 + assign $1\cr_fxm[7:0] 8'00000000 end sync always - update \dec31_dec_sub10_lk $0\dec31_dec_sub10_lk[0:0] + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:112738$4447_Y + connect \$3 $and$libresoc.v:112739$4448_Y + connect \$5 $eq$libresoc.v:112740$4449_Y + connect \$7 $and$libresoc.v:112741$4450_Y +end +attribute \src "libresoc.v:112905.1-113202.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_cr_in" +attribute \generator "nMigen" +module \dec_cr_in$150 + attribute \src "libresoc.v:113096.3-113122.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:113123.3-113133.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "libresoc.v:113074.3-113084.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:113134.3-113144.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "libresoc.v:113145.3-113155.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:113047.3-113073.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:113183.3-113201.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:113085.3-113095.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:112906.7-112906.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:113156.3-113166.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:113167.3-113182.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:113096.3-113122.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:113123.3-113133.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:113074.3-113084.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:113134.3-113144.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:113145.3-113155.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:113047.3-113073.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:113183.3-113201.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:113085.3-113095.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:113156.3-113166.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:113167.3-113182.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:113183.3-113201.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:113167.3-113182.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:113040.17-113040.112" + wire $and$libresoc.v:113040$4463_Y + attribute \src "libresoc.v:113042.17-113042.112" + wire $and$libresoc.v:113042$4465_Y + attribute \src "libresoc.v:113039.17-113039.124" + wire $eq$libresoc.v:113039$4462_Y + attribute \src "libresoc.v:113041.17-113041.124" + wire $eq$libresoc.v:113041$4464_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 4 \BRANCH_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 3 \BRANCH_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 8 \BRANCH_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 7 \BRANCH_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 5 \BRANCH_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 input 6 \BRANCH_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 input 2 \BRANCH_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_fxm_ok + attribute \src "libresoc.v:112906.7-112906.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" + wire width 32 input 10 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:113040$4463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$libresoc.v:113040$4463_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:113042$4465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$libresoc.v:113042$4465_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:113039$4462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \BRANCH_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:113039$4462_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:113041$4464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \BRANCH_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:113041$4464_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:113043.15-113046.4" + cell \ppick$151 \ppick + connect \i \ppick_i + connect \o \ppick_o end - attribute \src "libresoc.v:19774.3-19810.6" - process $proc$libresoc.v:19774$448 + attribute \src "libresoc.v:112906.7-112906.20" + process $proc$libresoc.v:112906$4476 assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:113047.3-113073.6" + process $proc$libresoc.v:113047$4466 assign { } { } - assign $0\dec31_dec_sub10_sgl_pipe[0:0] $1\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "libresoc.v:19775.5-19775.29" + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:113048.5-113048.29" switch \initial - attribute \src "libresoc.v:19775.9-19775.17" + attribute \src "libresoc.v:113048.9-113048.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 3'001 assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 3'010 assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 3'011 assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 3'100 assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 3'101 assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + assign $1\cr_bitfield_ok[0:0] 1'1 case - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + assign $1\cr_bitfield_ok[0:0] 1'0 end sync always - update \dec31_dec_sub10_sgl_pipe $0\dec31_dec_sub10_sgl_pipe[0:0] + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:19811.3-19847.6" - process $proc$libresoc.v:19811$449 + attribute \src "libresoc.v:113074.3-113084.6" + process $proc$libresoc.v:113074$4467 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_form[4:0] $1\dec31_dec_sub10_form[4:0] - attribute \src "libresoc.v:19812.5-19812.29" + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:113075.5-113075.29" switch \initial - attribute \src "libresoc.v:19812.9-19812.17" + attribute \src "libresoc.v:113075.9-113075.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 3'100 assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 + assign $1\cr_bitfield_b_ok[0:0] 1'1 case - assign $1\dec31_dec_sub10_form[4:0] 5'00000 + assign $1\cr_bitfield_b_ok[0:0] 1'0 end sync always - update \dec31_dec_sub10_form $0\dec31_dec_sub10_form[4:0] + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] end - attribute \src "libresoc.v:19848.3-19884.6" - process $proc$libresoc.v:19848$450 + attribute \src "libresoc.v:113085.3-113095.6" + process $proc$libresoc.v:113085$4468 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_in1_sel[2:0] $1\dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:19849.5-19849.29" + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:113086.5-113086.29" switch \initial - attribute \src "libresoc.v:19849.9-19849.17" + attribute \src "libresoc.v:113086.9-113086.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 3'110 assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + assign $1\cr_fxm_ok[0:0] 1'1 case - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'000 + assign $1\cr_fxm_ok[0:0] 1'0 end sync always - update \dec31_dec_sub10_in1_sel $0\dec31_dec_sub10_in1_sel[2:0] + update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:19885.3-19921.6" - process $proc$libresoc.v:19885$451 + attribute \src "libresoc.v:113096.3-113122.6" + process $proc$libresoc.v:113096$4469 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_in2_sel[3:0] $1\dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:19886.5-19886.29" + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:113097.5-113097.29" switch \initial - attribute \src "libresoc.v:19886.9-19886.17" + attribute \src "libresoc.v:113097.9-113097.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 3'001 assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + assign $1\cr_bitfield[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 3'010 assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'1001 + assign $1\cr_bitfield[2:0] \BRANCH_BI [4:2] attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 3'011 assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'1001 + assign $1\cr_bitfield[2:0] \X_BFA attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 3'100 assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 + assign $1\cr_bitfield[2:0] \BRANCH_BA [4:2] attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 3'101 assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 + assign $1\cr_bitfield[2:0] \BRANCH_BC [4:2] case - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 + assign $1\cr_bitfield[2:0] 3'000 end sync always - update \dec31_dec_sub10_in2_sel $0\dec31_dec_sub10_in2_sel[3:0] + update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:19922.3-19958.6" - process $proc$libresoc.v:19922$452 + attribute \src "libresoc.v:113123.3-113133.6" + process $proc$libresoc.v:113123$4470 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_in3_sel[1:0] $1\dec31_dec_sub10_in3_sel[1:0] - attribute \src "libresoc.v:19923.5-19923.29" + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:113124.5-113124.29" switch \initial - attribute \src "libresoc.v:19923.9-19923.17" + attribute \src "libresoc.v:113124.9-113124.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 3'100 assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + assign $1\cr_bitfield_b[2:0] \BRANCH_BB [4:2] case - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + assign $1\cr_bitfield_b[2:0] 3'000 end sync always - update \dec31_dec_sub10_in3_sel $0\dec31_dec_sub10_in3_sel[1:0] + update \cr_bitfield_b $0\cr_bitfield_b[2:0] end - attribute \src "libresoc.v:19959.3-19995.6" - process $proc$libresoc.v:19959$453 + attribute \src "libresoc.v:113134.3-113144.6" + process $proc$libresoc.v:113134$4471 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_out_sel[1:0] $1\dec31_dec_sub10_out_sel[1:0] - attribute \src "libresoc.v:19960.5-19960.29" + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:113135.5-113135.29" switch \initial - attribute \src "libresoc.v:19960.9-19960.17" + attribute \src "libresoc.v:113135.9-113135.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 3'100 assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + assign $1\cr_bitfield_o[2:0] \BRANCH_BT [4:2] case - assign $1\dec31_dec_sub10_out_sel[1:0] 2'00 + assign $1\cr_bitfield_o[2:0] 3'000 end sync always - update \dec31_dec_sub10_out_sel $0\dec31_dec_sub10_out_sel[1:0] + update \cr_bitfield_o $0\cr_bitfield_o[2:0] end - attribute \src "libresoc.v:19996.3-20032.6" - process $proc$libresoc.v:19996$454 + attribute \src "libresoc.v:113145.3-113155.6" + process $proc$libresoc.v:113145$4472 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_cr_in[2:0] $1\dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:19997.5-19997.29" + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:113146.5-113146.29" switch \initial - attribute \src "libresoc.v:19997.9-19997.17" + attribute \src "libresoc.v:113146.9-113146.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 3'100 assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + assign $1\cr_bitfield_o_ok[0:0] 1'1 case - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + assign $1\cr_bitfield_o_ok[0:0] 1'0 end sync always - update \dec31_dec_sub10_cr_in $0\dec31_dec_sub10_cr_in[2:0] + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] end - attribute \src "libresoc.v:20033.3-20069.6" - process $proc$libresoc.v:20033$455 + attribute \src "libresoc.v:113156.3-113166.6" + process $proc$libresoc.v:113156$4473 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_cr_out[2:0] $1\dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:20034.5-20034.29" + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:113157.5-113157.29" switch \initial - attribute \src "libresoc.v:20034.9-20034.17" + attribute \src "libresoc.v:113157.9-113157.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 3'110 assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:113167.3-113182.6" + process $proc$libresoc.v:113167$4474 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:113168.5-113168.29" + switch \initial + attribute \src "libresoc.v:113168.9-113168.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 3'110 assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \BRANCH_FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:113183.3-113201.6" + process $proc$libresoc.v:113183$4475 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:113184.5-113184.29" + switch \initial + attribute \src "libresoc.v:113184.9-113184.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 3'110 assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end case - assign $1\dec31_dec_sub10_cr_out[2:0] 3'000 + assign $1\cr_fxm[7:0] 8'00000000 end sync always - update \dec31_dec_sub10_cr_out $0\dec31_dec_sub10_cr_out[2:0] + update \cr_fxm $0\cr_fxm[7:0] end - connect \opcode_switch \opcode_in [10:6] + connect \$1 $eq$libresoc.v:113039$4462_Y + connect \$3 $and$libresoc.v:113040$4463_Y + connect \$5 $eq$libresoc.v:113041$4464_Y + connect \$7 $and$libresoc.v:113042$4465_Y end -attribute \src "libresoc.v:20075.1-21654.10" +attribute \src "libresoc.v:113206.1-113503.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub11" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_cr_in" attribute \generator "nMigen" -module \dec31_dec_sub11 - attribute \src "libresoc.v:20608.3-20662.6" - wire width 8 $0\dec31_dec_sub11_asmcode[7:0] - attribute \src "libresoc.v:20828.3-20882.6" - wire $0\dec31_dec_sub11_br[0:0] - attribute \src "libresoc.v:21543.3-21597.6" - wire width 3 $0\dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:21598.3-21652.6" - wire width 3 $0\dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:20553.3-20607.6" - wire width 2 $0\dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:20773.3-20827.6" - wire $0\dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:21268.3-21322.6" - wire width 5 $0\dec31_dec_sub11_form[4:0] - attribute \src "libresoc.v:20333.3-20387.6" - wire width 12 $0\dec31_dec_sub11_function_unit[11:0] - attribute \src "libresoc.v:21323.3-21377.6" - wire width 3 $0\dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:21378.3-21432.6" - wire width 4 $0\dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:21433.3-21487.6" - wire width 2 $0\dec31_dec_sub11_in3_sel[1:0] - attribute \src "libresoc.v:20938.3-20992.6" - wire width 7 $0\dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:20663.3-20717.6" - wire $0\dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:20718.3-20772.6" - wire $0\dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:21048.3-21102.6" - wire $0\dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:20388.3-20442.6" - wire width 4 $0\dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:21158.3-21212.6" - wire $0\dec31_dec_sub11_lk[0:0] - attribute \src "libresoc.v:21488.3-21542.6" - wire width 2 $0\dec31_dec_sub11_out_sel[1:0] - attribute \src "libresoc.v:20498.3-20552.6" - wire width 2 $0\dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:20993.3-21047.6" - wire $0\dec31_dec_sub11_rsrv[0:0] - attribute \src "libresoc.v:21213.3-21267.6" - wire $0\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "libresoc.v:21103.3-21157.6" - wire $0\dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:20883.3-20937.6" - wire $0\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "libresoc.v:20443.3-20497.6" - wire width 2 $0\dec31_dec_sub11_upd[1:0] - attribute \src "libresoc.v:20076.7-20076.20" +module \dec_cr_in$158 + attribute \src "libresoc.v:113397.3-113423.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:113424.3-113434.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "libresoc.v:113375.3-113385.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:113435.3-113445.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "libresoc.v:113446.3-113456.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:113348.3-113374.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:113484.3-113502.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:113386.3-113396.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:113207.7-113207.20" wire $0\initial[0:0] - attribute \src "libresoc.v:20608.3-20662.6" - wire width 8 $1\dec31_dec_sub11_asmcode[7:0] - attribute \src "libresoc.v:20828.3-20882.6" - wire $1\dec31_dec_sub11_br[0:0] - attribute \src "libresoc.v:21543.3-21597.6" - wire width 3 $1\dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:21598.3-21652.6" - wire width 3 $1\dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:20553.3-20607.6" - wire width 2 $1\dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:20773.3-20827.6" - wire $1\dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:21268.3-21322.6" - wire width 5 $1\dec31_dec_sub11_form[4:0] - attribute \src "libresoc.v:20333.3-20387.6" - wire width 12 $1\dec31_dec_sub11_function_unit[11:0] - attribute \src "libresoc.v:21323.3-21377.6" - wire width 3 $1\dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:21378.3-21432.6" - wire width 4 $1\dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:21433.3-21487.6" - wire width 2 $1\dec31_dec_sub11_in3_sel[1:0] - attribute \src "libresoc.v:20938.3-20992.6" - wire width 7 $1\dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:20663.3-20717.6" - wire $1\dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:20718.3-20772.6" - wire $1\dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:21048.3-21102.6" - wire $1\dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:20388.3-20442.6" - wire width 4 $1\dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:21158.3-21212.6" - wire $1\dec31_dec_sub11_lk[0:0] - attribute \src "libresoc.v:21488.3-21542.6" - wire width 2 $1\dec31_dec_sub11_out_sel[1:0] - attribute \src "libresoc.v:20498.3-20552.6" - wire width 2 $1\dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:20993.3-21047.6" - wire $1\dec31_dec_sub11_rsrv[0:0] - attribute \src "libresoc.v:21213.3-21267.6" - wire $1\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "libresoc.v:21103.3-21157.6" - wire $1\dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:20883.3-20937.6" - wire $1\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "libresoc.v:20443.3-20497.6" - wire width 2 $1\dec31_dec_sub11_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub11_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub11_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub11_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub11_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub11_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub11_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub11_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub11_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub11_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub11_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub11_in3_sel + attribute \src "libresoc.v:113457.3-113467.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:113468.3-113483.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:113397.3-113423.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:113424.3-113434.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:113375.3-113385.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:113435.3-113445.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:113446.3-113456.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:113348.3-113374.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:113484.3-113502.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:113386.3-113396.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:113457.3-113467.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:113468.3-113483.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:113484.3-113502.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:113468.3-113483.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:113341.17-113341.112" + wire $and$libresoc.v:113341$4478_Y + attribute \src "libresoc.v:113343.17-113343.112" + wire $and$libresoc.v:113343$4480_Y + attribute \src "libresoc.v:113340.17-113340.125" + wire $eq$libresoc.v:113340$4477_Y + attribute \src "libresoc.v:113342.17-113342.125" + wire $eq$libresoc.v:113342$4479_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 4 \LOGICAL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 3 \LOGICAL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 8 \LOGICAL_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 7 \LOGICAL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 5 \LOGICAL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 input 6 \LOGICAL_FXM attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -29293,2270 +177361,2083 @@ module \dec31_dec_sub11 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub11_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub11_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub11_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub11_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub11_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub11_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub11_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub11_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub11_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub11_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub11_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub11_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub11_upd - attribute \src "libresoc.v:20076.7-20076.15" + wire width 7 input 2 \LOGICAL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_fxm_ok + attribute \src "libresoc.v:113207.7-113207.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:20076.7-20076.20" - process $proc$libresoc.v:20076$481 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" + wire width 32 input 10 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:113341$4478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$libresoc.v:113341$4478_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:113343$4480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$libresoc.v:113343$4480_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:113340$4477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LOGICAL_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:113340$4477_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:113342$4479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LOGICAL_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:113342$4479_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:113344.15-113347.4" + cell \ppick$159 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:113207.7-113207.20" + process $proc$libresoc.v:113207$4491 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:20333.3-20387.6" - process $proc$libresoc.v:20333$457 + attribute \src "libresoc.v:113348.3-113374.6" + process $proc$libresoc.v:113348$4481 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_function_unit[11:0] $1\dec31_dec_sub11_function_unit[11:0] - attribute \src "libresoc.v:20334.5-20334.29" + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:113349.5-113349.29" switch \initial - attribute \src "libresoc.v:20334.9-20334.17" + attribute \src "libresoc.v:113349.9-113349.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 3'001 assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 3'010 assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 3'011 assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 3'100 assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 3'101 assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + assign $1\cr_bitfield_ok[0:0] 1'1 case - assign $1\dec31_dec_sub11_function_unit[11:0] 12'000000000000 + assign $1\cr_bitfield_ok[0:0] 1'0 end sync always - update \dec31_dec_sub11_function_unit $0\dec31_dec_sub11_function_unit[11:0] + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:20388.3-20442.6" - process $proc$libresoc.v:20388$458 + attribute \src "libresoc.v:113375.3-113385.6" + process $proc$libresoc.v:113375$4482 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_ldst_len[3:0] $1\dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:20389.5-20389.29" + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:113376.5-113376.29" switch \initial - attribute \src "libresoc.v:20389.9-20389.17" + attribute \src "libresoc.v:113376.9-113376.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 3'100 assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + assign $1\cr_bitfield_b_ok[0:0] 1'1 case - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + assign $1\cr_bitfield_b_ok[0:0] 1'0 end sync always - update \dec31_dec_sub11_ldst_len $0\dec31_dec_sub11_ldst_len[3:0] + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] end - attribute \src "libresoc.v:20443.3-20497.6" - process $proc$libresoc.v:20443$459 + attribute \src "libresoc.v:113386.3-113396.6" + process $proc$libresoc.v:113386$4483 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_upd[1:0] $1\dec31_dec_sub11_upd[1:0] - attribute \src "libresoc.v:20444.5-20444.29" + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:113387.5-113387.29" switch \initial - attribute \src "libresoc.v:20444.9-20444.17" + attribute \src "libresoc.v:113387.9-113387.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 3'110 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\cr_fxm_ok[0:0] 1'1 case - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\cr_fxm_ok[0:0] 1'0 end sync always - update \dec31_dec_sub11_upd $0\dec31_dec_sub11_upd[1:0] + update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:20498.3-20552.6" - process $proc$libresoc.v:20498$460 + attribute \src "libresoc.v:113397.3-113423.6" + process $proc$libresoc.v:113397$4484 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_rc_sel[1:0] $1\dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:20499.5-20499.29" + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:113398.5-113398.29" switch \initial - attribute \src "libresoc.v:20499.9-20499.17" + attribute \src "libresoc.v:113398.9-113398.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 3'001 assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + assign $1\cr_bitfield[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 3'010 assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + assign $1\cr_bitfield[2:0] \LOGICAL_BI [4:2] attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 3'011 assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + assign $1\cr_bitfield[2:0] \X_BFA attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 3'100 assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 + assign $1\cr_bitfield[2:0] \LOGICAL_BA [4:2] attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 3'101 assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 + assign $1\cr_bitfield[2:0] \LOGICAL_BC [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:113424.3-113434.6" + process $proc$libresoc.v:113424$4485 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:113425.5-113425.29" + switch \initial + attribute \src "libresoc.v:113425.9-113425.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 3'100 assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + assign $1\cr_bitfield_b[2:0] \LOGICAL_BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end + sync always + update \cr_bitfield_b $0\cr_bitfield_b[2:0] + end + attribute \src "libresoc.v:113435.3-113445.6" + process $proc$libresoc.v:113435$4486 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:113436.5-113436.29" + switch \initial + attribute \src "libresoc.v:113436.9-113436.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 3'100 assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + assign $1\cr_bitfield_o[2:0] \LOGICAL_BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] + end + attribute \src "libresoc.v:113446.3-113456.6" + process $proc$libresoc.v:113446$4487 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:113447.5-113447.29" + switch \initial + attribute \src "libresoc.v:113447.9-113447.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 3'100 assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "libresoc.v:113457.3-113467.6" + process $proc$libresoc.v:113457$4488 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:113458.5-113458.29" + switch \initial + attribute \src "libresoc.v:113458.9-113458.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 3'110 assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:113468.3-113483.6" + process $proc$libresoc.v:113468$4489 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:113469.5-113469.29" + switch \initial + attribute \src "libresoc.v:113469.9-113469.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 3'110 assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \LOGICAL_FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:113484.3-113502.6" + process $proc$libresoc.v:113484$4490 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:113485.5-113485.29" + switch \initial + attribute \src "libresoc.v:113485.9-113485.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 3'110 assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end case - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 + assign $1\cr_fxm[7:0] 8'00000000 end sync always - update \dec31_dec_sub11_rc_sel $0\dec31_dec_sub11_rc_sel[1:0] + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:113340$4477_Y + connect \$3 $and$libresoc.v:113341$4478_Y + connect \$5 $eq$libresoc.v:113342$4479_Y + connect \$7 $and$libresoc.v:113343$4480_Y +end +attribute \src "libresoc.v:113507.1-113804.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_cr_in" +attribute \generator "nMigen" +module \dec_cr_in$167 + attribute \src "libresoc.v:113698.3-113724.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:113725.3-113735.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "libresoc.v:113676.3-113686.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:113736.3-113746.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "libresoc.v:113747.3-113757.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:113649.3-113675.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:113785.3-113803.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:113687.3-113697.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:113508.7-113508.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:113758.3-113768.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:113769.3-113784.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:113698.3-113724.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:113725.3-113735.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:113676.3-113686.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:113736.3-113746.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:113747.3-113757.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:113649.3-113675.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:113785.3-113803.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:113687.3-113697.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:113758.3-113768.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:113769.3-113784.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:113785.3-113803.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:113769.3-113784.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:113642.17-113642.112" + wire $and$libresoc.v:113642$4493_Y + attribute \src "libresoc.v:113644.17-113644.112" + wire $and$libresoc.v:113644$4495_Y + attribute \src "libresoc.v:113641.17-113641.121" + wire $eq$libresoc.v:113641$4492_Y + attribute \src "libresoc.v:113643.17-113643.121" + wire $eq$libresoc.v:113643$4494_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 4 \SPR_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 3 \SPR_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 8 \SPR_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 7 \SPR_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 5 \SPR_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 input 6 \SPR_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 input 2 \SPR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_fxm_ok + attribute \src "libresoc.v:113508.7-113508.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" + wire width 32 input 10 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:113642$4493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$libresoc.v:113642$4493_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:113644$4495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$libresoc.v:113644$4495_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:113641$4492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SPR_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:113641$4492_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:113643$4494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SPR_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:113643$4494_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:113645.15-113648.4" + cell \ppick$168 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:113508.7-113508.20" + process $proc$libresoc.v:113508$4506 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:20553.3-20607.6" - process $proc$libresoc.v:20553$461 + attribute \src "libresoc.v:113649.3-113675.6" + process $proc$libresoc.v:113649$4496 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_cry_in[1:0] $1\dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:20554.5-20554.29" + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:113650.5-113650.29" switch \initial - attribute \src "libresoc.v:20554.9-20554.17" + attribute \src "libresoc.v:113650.9-113650.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 3'001 assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 3'010 assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 3'011 assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 3'100 assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 3'101 assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + assign $1\cr_bitfield_ok[0:0] 1'1 case - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + assign $1\cr_bitfield_ok[0:0] 1'0 end sync always - update \dec31_dec_sub11_cry_in $0\dec31_dec_sub11_cry_in[1:0] + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:20608.3-20662.6" - process $proc$libresoc.v:20608$462 + attribute \src "libresoc.v:113676.3-113686.6" + process $proc$libresoc.v:113676$4497 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_asmcode[7:0] $1\dec31_dec_sub11_asmcode[7:0] - attribute \src "libresoc.v:20609.5-20609.29" + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:113677.5-113677.29" switch \initial - attribute \src "libresoc.v:20609.9-20609.17" + attribute \src "libresoc.v:113677.9-113677.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111111 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01110101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01110011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'10000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 3'100 assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'10000010 + assign $1\cr_bitfield_b_ok[0:0] 1'1 case - assign $1\dec31_dec_sub11_asmcode[7:0] 8'00000000 + assign $1\cr_bitfield_b_ok[0:0] 1'0 end sync always - update \dec31_dec_sub11_asmcode $0\dec31_dec_sub11_asmcode[7:0] + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] end - attribute \src "libresoc.v:20663.3-20717.6" - process $proc$libresoc.v:20663$463 + attribute \src "libresoc.v:113687.3-113697.6" + process $proc$libresoc.v:113687$4498 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_inv_a[0:0] $1\dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:20664.5-20664.29" + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:113688.5-113688.29" switch \initial - attribute \src "libresoc.v:20664.9-20664.17" + attribute \src "libresoc.v:113688.9-113688.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 3'110 assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + assign $1\cr_fxm_ok[0:0] 1'1 case - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + assign $1\cr_fxm_ok[0:0] 1'0 end sync always - update \dec31_dec_sub11_inv_a $0\dec31_dec_sub11_inv_a[0:0] + update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:20718.3-20772.6" - process $proc$libresoc.v:20718$464 + attribute \src "libresoc.v:113698.3-113724.6" + process $proc$libresoc.v:113698$4499 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_inv_out[0:0] $1\dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:20719.5-20719.29" + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:113699.5-113699.29" switch \initial - attribute \src "libresoc.v:20719.9-20719.17" + attribute \src "libresoc.v:113699.9-113699.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 3'001 assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + assign $1\cr_bitfield[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 3'010 assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + assign $1\cr_bitfield[2:0] \SPR_BI [4:2] attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 3'011 assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + assign $1\cr_bitfield[2:0] \X_BFA attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 3'100 assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + assign $1\cr_bitfield[2:0] \SPR_BA [4:2] attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 3'101 assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + assign $1\cr_bitfield[2:0] \SPR_BC [4:2] case - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + assign $1\cr_bitfield[2:0] 3'000 end sync always - update \dec31_dec_sub11_inv_out $0\dec31_dec_sub11_inv_out[0:0] + update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:20773.3-20827.6" - process $proc$libresoc.v:20773$465 + attribute \src "libresoc.v:113725.3-113735.6" + process $proc$libresoc.v:113725$4500 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_cry_out[0:0] $1\dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:20774.5-20774.29" + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:113726.5-113726.29" switch \initial - attribute \src "libresoc.v:20774.9-20774.17" + attribute \src "libresoc.v:113726.9-113726.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 3'100 assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + assign $1\cr_bitfield_b[2:0] \SPR_BB [4:2] case - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + assign $1\cr_bitfield_b[2:0] 3'000 end sync always - update \dec31_dec_sub11_cry_out $0\dec31_dec_sub11_cry_out[0:0] + update \cr_bitfield_b $0\cr_bitfield_b[2:0] end - attribute \src "libresoc.v:20828.3-20882.6" - process $proc$libresoc.v:20828$466 + attribute \src "libresoc.v:113736.3-113746.6" + process $proc$libresoc.v:113736$4501 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_br[0:0] $1\dec31_dec_sub11_br[0:0] - attribute \src "libresoc.v:20829.5-20829.29" + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:113737.5-113737.29" switch \initial - attribute \src "libresoc.v:20829.9-20829.17" + attribute \src "libresoc.v:113737.9-113737.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 3'100 assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 + assign $1\cr_bitfield_o[2:0] \SPR_BT [4:2] case - assign $1\dec31_dec_sub11_br[0:0] 1'0 + assign $1\cr_bitfield_o[2:0] 3'000 end sync always - update \dec31_dec_sub11_br $0\dec31_dec_sub11_br[0:0] + update \cr_bitfield_o $0\cr_bitfield_o[2:0] end - attribute \src "libresoc.v:20883.3-20937.6" - process $proc$libresoc.v:20883$467 + attribute \src "libresoc.v:113747.3-113757.6" + process $proc$libresoc.v:113747$4502 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_sgn_ext[0:0] $1\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "libresoc.v:20884.5-20884.29" + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:113748.5-113748.29" switch \initial - attribute \src "libresoc.v:20884.9-20884.17" + attribute \src "libresoc.v:113748.9-113748.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 3'100 assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + assign $1\cr_bitfield_o_ok[0:0] 1'1 case - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + assign $1\cr_bitfield_o_ok[0:0] 1'0 end sync always - update \dec31_dec_sub11_sgn_ext $0\dec31_dec_sub11_sgn_ext[0:0] + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] end - attribute \src "libresoc.v:20938.3-20992.6" - process $proc$libresoc.v:20938$468 + attribute \src "libresoc.v:113758.3-113768.6" + process $proc$libresoc.v:113758$4503 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_internal_op[6:0] $1\dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:20939.5-20939.29" + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:113759.5-113759.29" switch \initial - attribute \src "libresoc.v:20939.9-20939.17" + attribute \src "libresoc.v:113759.9-113759.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 3'110 assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010 + assign $1\move_one[0:0] \insn_in [20] case - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0000000 + assign $1\move_one[0:0] 1'0 end sync always - update \dec31_dec_sub11_internal_op $0\dec31_dec_sub11_internal_op[6:0] + update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:20993.3-21047.6" - process $proc$libresoc.v:20993$469 + attribute \src "libresoc.v:113769.3-113784.6" + process $proc$libresoc.v:113769$4504 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_rsrv[0:0] $1\dec31_dec_sub11_rsrv[0:0] - attribute \src "libresoc.v:20994.5-20994.29" + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:113770.5-113770.29" switch \initial - attribute \src "libresoc.v:20994.9-20994.17" + attribute \src "libresoc.v:113770.9-113770.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 3'110 assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \SPR_FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end case - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + assign $1\ppick_i[7:0] 8'00000000 end sync always - update \dec31_dec_sub11_rsrv $0\dec31_dec_sub11_rsrv[0:0] + update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:21048.3-21102.6" - process $proc$libresoc.v:21048$470 + attribute \src "libresoc.v:113785.3-113803.6" + process $proc$libresoc.v:113785$4505 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_is_32b[0:0] $1\dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:21049.5-21049.29" + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:113786.5-113786.29" switch \initial - attribute \src "libresoc.v:21049.9-21049.17" + attribute \src "libresoc.v:113786.9-113786.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 3'110 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end case - assign $1\dec31_dec_sub11_is_32b[0:0] 1'0 + assign $1\cr_fxm[7:0] 8'00000000 end sync always - update \dec31_dec_sub11_is_32b $0\dec31_dec_sub11_is_32b[0:0] + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:113641$4492_Y + connect \$3 $and$libresoc.v:113642$4493_Y + connect \$5 $eq$libresoc.v:113643$4494_Y + connect \$7 $and$libresoc.v:113644$4495_Y +end +attribute \src "libresoc.v:113808.1-114105.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_cr_in" +attribute \generator "nMigen" +module \dec_cr_in$174 + attribute \src "libresoc.v:113999.3-114025.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:114026.3-114036.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "libresoc.v:113977.3-113987.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:114037.3-114047.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "libresoc.v:114048.3-114058.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:113950.3-113976.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:114086.3-114104.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:113988.3-113998.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:113809.7-113809.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:114059.3-114069.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:114070.3-114085.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:113999.3-114025.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:114026.3-114036.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:113977.3-113987.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:114037.3-114047.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:114048.3-114058.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:113950.3-113976.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:114086.3-114104.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:113988.3-113998.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:114059.3-114069.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:114070.3-114085.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:114086.3-114104.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:114070.3-114085.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:113943.17-113943.112" + wire $and$libresoc.v:113943$4508_Y + attribute \src "libresoc.v:113945.17-113945.112" + wire $and$libresoc.v:113945$4510_Y + attribute \src "libresoc.v:113942.17-113942.121" + wire $eq$libresoc.v:113942$4507_Y + attribute \src "libresoc.v:113944.17-113944.121" + wire $eq$libresoc.v:113944$4509_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 4 \DIV_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 3 \DIV_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 8 \DIV_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 7 \DIV_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 5 \DIV_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 input 6 \DIV_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 input 2 \DIV_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_fxm_ok + attribute \src "libresoc.v:113809.7-113809.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" + wire width 32 input 10 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:113943$4508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$libresoc.v:113943$4508_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:113945$4510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$libresoc.v:113945$4510_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:113942$4507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \DIV_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:113942$4507_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:113944$4509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \DIV_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:113944$4509_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:113946.15-113949.4" + cell \ppick$175 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:113809.7-113809.20" + process $proc$libresoc.v:113809$4521 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:21103.3-21157.6" - process $proc$libresoc.v:21103$471 + attribute \src "libresoc.v:113950.3-113976.6" + process $proc$libresoc.v:113950$4511 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_sgn[0:0] $1\dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:21104.5-21104.29" + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:113951.5-113951.29" switch \initial - attribute \src "libresoc.v:21104.9-21104.17" + attribute \src "libresoc.v:113951.9-113951.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 3'001 assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 3'010 assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 3'011 assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 3'100 assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 3'101 assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + assign $1\cr_bitfield_ok[0:0] 1'1 case - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + assign $1\cr_bitfield_ok[0:0] 1'0 end sync always - update \dec31_dec_sub11_sgn $0\dec31_dec_sub11_sgn[0:0] + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:21158.3-21212.6" - process $proc$libresoc.v:21158$472 + attribute \src "libresoc.v:113977.3-113987.6" + process $proc$libresoc.v:113977$4512 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_lk[0:0] $1\dec31_dec_sub11_lk[0:0] - attribute \src "libresoc.v:21159.5-21159.29" + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:113978.5-113978.29" switch \initial - attribute \src "libresoc.v:21159.9-21159.17" + attribute \src "libresoc.v:113978.9-113978.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 3'100 assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 + assign $1\cr_bitfield_b_ok[0:0] 1'1 case - assign $1\dec31_dec_sub11_lk[0:0] 1'0 + assign $1\cr_bitfield_b_ok[0:0] 1'0 end sync always - update \dec31_dec_sub11_lk $0\dec31_dec_sub11_lk[0:0] + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] end - attribute \src "libresoc.v:21213.3-21267.6" - process $proc$libresoc.v:21213$473 + attribute \src "libresoc.v:113988.3-113998.6" + process $proc$libresoc.v:113988$4513 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_sgl_pipe[0:0] $1\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "libresoc.v:21214.5-21214.29" + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:113989.5-113989.29" switch \initial - attribute \src "libresoc.v:21214.9-21214.17" + attribute \src "libresoc.v:113989.9-113989.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 3'110 assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + assign $1\cr_fxm_ok[0:0] 1'1 case - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + assign $1\cr_fxm_ok[0:0] 1'0 end sync always - update \dec31_dec_sub11_sgl_pipe $0\dec31_dec_sub11_sgl_pipe[0:0] + update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:21268.3-21322.6" - process $proc$libresoc.v:21268$474 + attribute \src "libresoc.v:113999.3-114025.6" + process $proc$libresoc.v:113999$4514 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_form[4:0] $1\dec31_dec_sub11_form[4:0] - attribute \src "libresoc.v:21269.5-21269.29" + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:114000.5-114000.29" switch \initial - attribute \src "libresoc.v:21269.9-21269.17" + attribute \src "libresoc.v:114000.9-114000.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 3'001 assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 + assign $1\cr_bitfield[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 3'010 assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 + assign $1\cr_bitfield[2:0] \DIV_BI [4:2] attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 3'011 assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 + assign $1\cr_bitfield[2:0] \X_BFA attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 3'100 assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 + assign $1\cr_bitfield[2:0] \DIV_BA [4:2] attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 3'101 assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 + assign $1\cr_bitfield[2:0] \DIV_BC [4:2] case - assign $1\dec31_dec_sub11_form[4:0] 5'00000 + assign $1\cr_bitfield[2:0] 3'000 end sync always - update \dec31_dec_sub11_form $0\dec31_dec_sub11_form[4:0] + update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:21323.3-21377.6" - process $proc$libresoc.v:21323$475 + attribute \src "libresoc.v:114026.3-114036.6" + process $proc$libresoc.v:114026$4515 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_in1_sel[2:0] $1\dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:21324.5-21324.29" + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:114027.5-114027.29" switch \initial - attribute \src "libresoc.v:21324.9-21324.17" + attribute \src "libresoc.v:114027.9-114027.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 3'100 assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + assign $1\cr_bitfield_b[2:0] \DIV_BB [4:2] case - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'000 + assign $1\cr_bitfield_b[2:0] 3'000 end sync always - update \dec31_dec_sub11_in1_sel $0\dec31_dec_sub11_in1_sel[2:0] + update \cr_bitfield_b $0\cr_bitfield_b[2:0] end - attribute \src "libresoc.v:21378.3-21432.6" - process $proc$libresoc.v:21378$476 + attribute \src "libresoc.v:114037.3-114047.6" + process $proc$libresoc.v:114037$4516 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_in2_sel[3:0] $1\dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:21379.5-21379.29" + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:114038.5-114038.29" switch \initial - attribute \src "libresoc.v:21379.9-21379.17" + attribute \src "libresoc.v:114038.9-114038.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 3'100 assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + assign $1\cr_bitfield_o[2:0] \DIV_BT [4:2] case - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0000 + assign $1\cr_bitfield_o[2:0] 3'000 end sync always - update \dec31_dec_sub11_in2_sel $0\dec31_dec_sub11_in2_sel[3:0] + update \cr_bitfield_o $0\cr_bitfield_o[2:0] end - attribute \src "libresoc.v:21433.3-21487.6" - process $proc$libresoc.v:21433$477 + attribute \src "libresoc.v:114048.3-114058.6" + process $proc$libresoc.v:114048$4517 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_in3_sel[1:0] $1\dec31_dec_sub11_in3_sel[1:0] - attribute \src "libresoc.v:21434.5-21434.29" + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:114049.5-114049.29" switch \initial - attribute \src "libresoc.v:21434.9-21434.17" + attribute \src "libresoc.v:114049.9-114049.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 3'100 assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + assign $1\cr_bitfield_o_ok[0:0] 1'1 case - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + assign $1\cr_bitfield_o_ok[0:0] 1'0 end sync always - update \dec31_dec_sub11_in3_sel $0\dec31_dec_sub11_in3_sel[1:0] + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] end - attribute \src "libresoc.v:21488.3-21542.6" - process $proc$libresoc.v:21488$478 + attribute \src "libresoc.v:114059.3-114069.6" + process $proc$libresoc.v:114059$4518 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_out_sel[1:0] $1\dec31_dec_sub11_out_sel[1:0] - attribute \src "libresoc.v:21489.5-21489.29" + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:114060.5-114060.29" switch \initial - attribute \src "libresoc.v:21489.9-21489.17" + attribute \src "libresoc.v:114060.9-114060.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 3'110 assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + assign $1\move_one[0:0] \insn_in [20] case - assign $1\dec31_dec_sub11_out_sel[1:0] 2'00 + assign $1\move_one[0:0] 1'0 end sync always - update \dec31_dec_sub11_out_sel $0\dec31_dec_sub11_out_sel[1:0] + update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:21543.3-21597.6" - process $proc$libresoc.v:21543$479 + attribute \src "libresoc.v:114070.3-114085.6" + process $proc$libresoc.v:114070$4519 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_cr_in[2:0] $1\dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:21544.5-21544.29" + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:114071.5-114071.29" switch \initial - attribute \src "libresoc.v:21544.9-21544.17" + attribute \src "libresoc.v:114071.9-114071.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 3'110 assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \DIV_FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:114086.3-114104.6" + process $proc$libresoc.v:114086$4520 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:114087.5-114087.29" + switch \initial + attribute \src "libresoc.v:114087.9-114087.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 3'110 assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:113942$4507_Y + connect \$3 $and$libresoc.v:113943$4508_Y + connect \$5 $eq$libresoc.v:113944$4509_Y + connect \$7 $and$libresoc.v:113945$4510_Y +end +attribute \src "libresoc.v:114109.1-114406.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_cr_in" +attribute \generator "nMigen" +module \dec_cr_in$183 + attribute \src "libresoc.v:114300.3-114326.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:114327.3-114337.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "libresoc.v:114278.3-114288.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:114338.3-114348.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "libresoc.v:114349.3-114359.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:114251.3-114277.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:114387.3-114405.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:114289.3-114299.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:114110.7-114110.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:114360.3-114370.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:114371.3-114386.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:114300.3-114326.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:114327.3-114337.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:114278.3-114288.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:114338.3-114348.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:114349.3-114359.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:114251.3-114277.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:114387.3-114405.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:114289.3-114299.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:114360.3-114370.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:114371.3-114386.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:114387.3-114405.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:114371.3-114386.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:114244.17-114244.112" + wire $and$libresoc.v:114244$4523_Y + attribute \src "libresoc.v:114246.17-114246.112" + wire $and$libresoc.v:114246$4525_Y + attribute \src "libresoc.v:114243.17-114243.121" + wire $eq$libresoc.v:114243$4522_Y + attribute \src "libresoc.v:114245.17-114245.121" + wire $eq$libresoc.v:114245$4524_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 4 \MUL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 3 \MUL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 8 \MUL_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 7 \MUL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 5 \MUL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 input 6 \MUL_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 input 2 \MUL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_fxm_ok + attribute \src "libresoc.v:114110.7-114110.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" + wire width 32 input 10 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:114244$4523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$libresoc.v:114244$4523_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:114246$4525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$libresoc.v:114246$4525_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:114243$4522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \MUL_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:114243$4522_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:114245$4524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \MUL_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:114245$4524_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:114247.15-114250.4" + cell \ppick$184 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:114110.7-114110.20" + process $proc$libresoc.v:114110$4536 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:114251.3-114277.6" + process $proc$libresoc.v:114251$4526 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:114252.5-114252.29" + switch \initial + attribute \src "libresoc.v:114252.9-114252.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 3'001 assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 3'010 assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 3'011 assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 3'100 assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 3'101 assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + assign $1\cr_bitfield_ok[0:0] 1'1 case - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + assign $1\cr_bitfield_ok[0:0] 1'0 end sync always - update \dec31_dec_sub11_cr_in $0\dec31_dec_sub11_cr_in[2:0] + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:21598.3-21652.6" - process $proc$libresoc.v:21598$480 + attribute \src "libresoc.v:114278.3-114288.6" + process $proc$libresoc.v:114278$4527 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_cr_out[2:0] $1\dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:21599.5-21599.29" + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:114279.5-114279.29" switch \initial - attribute \src "libresoc.v:21599.9-21599.17" + attribute \src "libresoc.v:114279.9-114279.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 3'100 assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + assign $1\cr_bitfield_b_ok[0:0] 1'1 + case + assign $1\cr_bitfield_b_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + end + attribute \src "libresoc.v:114289.3-114299.6" + process $proc$libresoc.v:114289$4528 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:114290.5-114290.29" + switch \initial + attribute \src "libresoc.v:114290.9-114290.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 3'110 assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:114300.3-114326.6" + process $proc$libresoc.v:114300$4529 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:114301.5-114301.29" + switch \initial + attribute \src "libresoc.v:114301.9-114301.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 3'001 assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + assign $1\cr_bitfield[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 3'010 assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + assign $1\cr_bitfield[2:0] \MUL_BI [4:2] attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 3'011 assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + assign $1\cr_bitfield[2:0] \X_BFA attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 3'100 assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 + assign $1\cr_bitfield[2:0] \MUL_BA [4:2] attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 3'101 assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 + assign $1\cr_bitfield[2:0] \MUL_BC [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:114327.3-114337.6" + process $proc$libresoc.v:114327$4530 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:114328.5-114328.29" + switch \initial + attribute \src "libresoc.v:114328.9-114328.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00010 + case 3'100 assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + assign $1\cr_bitfield_b[2:0] \MUL_BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end + sync always + update \cr_bitfield_b $0\cr_bitfield_b[2:0] + end + attribute \src "libresoc.v:114338.3-114348.6" + process $proc$libresoc.v:114338$4531 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:114339.5-114339.29" + switch \initial + attribute \src "libresoc.v:114339.9-114339.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 3'100 assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + assign $1\cr_bitfield_o[2:0] \MUL_BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] + end + attribute \src "libresoc.v:114349.3-114359.6" + process $proc$libresoc.v:114349$4532 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:114350.5-114350.29" + switch \initial + attribute \src "libresoc.v:114350.9-114350.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 3'100 assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "libresoc.v:114360.3-114370.6" + process $proc$libresoc.v:114360$4533 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:114361.5-114361.29" + switch \initial + attribute \src "libresoc.v:114361.9-114361.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 3'110 assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:114371.3-114386.6" + process $proc$libresoc.v:114371$4534 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:114372.5-114372.29" + switch \initial + attribute \src "libresoc.v:114372.9-114372.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 3'110 assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \MUL_FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:114387.3-114405.6" + process $proc$libresoc.v:114387$4535 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:114388.5-114388.29" + switch \initial + attribute \src "libresoc.v:114388.9-114388.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 3'110 assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end case - assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 + assign $1\cr_fxm[7:0] 8'00000000 end sync always - update \dec31_dec_sub11_cr_out $0\dec31_dec_sub11_cr_out[2:0] + update \cr_fxm $0\cr_fxm[7:0] end - connect \opcode_switch \opcode_in [10:6] + connect \$1 $eq$libresoc.v:114243$4522_Y + connect \$3 $and$libresoc.v:114244$4523_Y + connect \$5 $eq$libresoc.v:114245$4524_Y + connect \$7 $and$libresoc.v:114246$4525_Y end -attribute \src "libresoc.v:21658.1-24389.10" +attribute \src "libresoc.v:114410.1-114707.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub15" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_cr_in" attribute \generator "nMigen" -module \dec31_dec_sub15 - attribute \src "libresoc.v:22431.3-22533.6" - wire width 8 $0\dec31_dec_sub15_asmcode[7:0] - attribute \src "libresoc.v:22843.3-22945.6" - wire $0\dec31_dec_sub15_br[0:0] - attribute \src "libresoc.v:24182.3-24284.6" - wire width 3 $0\dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:24285.3-24387.6" - wire width 3 $0\dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:22328.3-22430.6" - wire width 2 $0\dec31_dec_sub15_cry_in[1:0] - attribute \src "libresoc.v:22740.3-22842.6" - wire $0\dec31_dec_sub15_cry_out[0:0] - attribute \src "libresoc.v:23667.3-23769.6" - wire width 5 $0\dec31_dec_sub15_form[4:0] - attribute \src "libresoc.v:21916.3-22018.6" - wire width 12 $0\dec31_dec_sub15_function_unit[11:0] - attribute \src "libresoc.v:23770.3-23872.6" - wire width 3 $0\dec31_dec_sub15_in1_sel[2:0] - attribute \src "libresoc.v:23873.3-23975.6" - wire width 4 $0\dec31_dec_sub15_in2_sel[3:0] - attribute \src "libresoc.v:23976.3-24078.6" - wire width 2 $0\dec31_dec_sub15_in3_sel[1:0] - attribute \src "libresoc.v:23049.3-23151.6" - wire width 7 $0\dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:22534.3-22636.6" - wire $0\dec31_dec_sub15_inv_a[0:0] - attribute \src "libresoc.v:22637.3-22739.6" - wire $0\dec31_dec_sub15_inv_out[0:0] - attribute \src "libresoc.v:23255.3-23357.6" - wire $0\dec31_dec_sub15_is_32b[0:0] - attribute \src "libresoc.v:22019.3-22121.6" - wire width 4 $0\dec31_dec_sub15_ldst_len[3:0] - attribute \src "libresoc.v:23461.3-23563.6" - wire $0\dec31_dec_sub15_lk[0:0] - attribute \src "libresoc.v:24079.3-24181.6" - wire width 2 $0\dec31_dec_sub15_out_sel[1:0] - attribute \src "libresoc.v:22225.3-22327.6" - wire width 2 $0\dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:23152.3-23254.6" - wire $0\dec31_dec_sub15_rsrv[0:0] - attribute \src "libresoc.v:23564.3-23666.6" - wire $0\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "libresoc.v:23358.3-23460.6" - wire $0\dec31_dec_sub15_sgn[0:0] - attribute \src "libresoc.v:22946.3-23048.6" - wire $0\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "libresoc.v:22122.3-22224.6" - wire width 2 $0\dec31_dec_sub15_upd[1:0] - attribute \src "libresoc.v:21659.7-21659.20" +module \dec_cr_in$191 + attribute \src "libresoc.v:114601.3-114627.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:114628.3-114638.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "libresoc.v:114579.3-114589.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:114639.3-114649.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "libresoc.v:114650.3-114660.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:114552.3-114578.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:114688.3-114706.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:114590.3-114600.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:114411.7-114411.20" wire $0\initial[0:0] - attribute \src "libresoc.v:22431.3-22533.6" - wire width 8 $1\dec31_dec_sub15_asmcode[7:0] - attribute \src "libresoc.v:22843.3-22945.6" - wire $1\dec31_dec_sub15_br[0:0] - attribute \src "libresoc.v:24182.3-24284.6" - wire width 3 $1\dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:24285.3-24387.6" - wire width 3 $1\dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:22328.3-22430.6" - wire width 2 $1\dec31_dec_sub15_cry_in[1:0] - attribute \src "libresoc.v:22740.3-22842.6" - wire $1\dec31_dec_sub15_cry_out[0:0] - attribute \src "libresoc.v:23667.3-23769.6" - wire width 5 $1\dec31_dec_sub15_form[4:0] - attribute \src "libresoc.v:21916.3-22018.6" - wire width 12 $1\dec31_dec_sub15_function_unit[11:0] - attribute \src "libresoc.v:23770.3-23872.6" - wire width 3 $1\dec31_dec_sub15_in1_sel[2:0] - attribute \src "libresoc.v:23873.3-23975.6" - wire width 4 $1\dec31_dec_sub15_in2_sel[3:0] - attribute \src "libresoc.v:23976.3-24078.6" - wire width 2 $1\dec31_dec_sub15_in3_sel[1:0] - attribute \src "libresoc.v:23049.3-23151.6" - wire width 7 $1\dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:22534.3-22636.6" - wire $1\dec31_dec_sub15_inv_a[0:0] - attribute \src "libresoc.v:22637.3-22739.6" - wire $1\dec31_dec_sub15_inv_out[0:0] - attribute \src "libresoc.v:23255.3-23357.6" - wire $1\dec31_dec_sub15_is_32b[0:0] - attribute \src "libresoc.v:22019.3-22121.6" - wire width 4 $1\dec31_dec_sub15_ldst_len[3:0] - attribute \src "libresoc.v:23461.3-23563.6" - wire $1\dec31_dec_sub15_lk[0:0] - attribute \src "libresoc.v:24079.3-24181.6" - wire width 2 $1\dec31_dec_sub15_out_sel[1:0] - attribute \src "libresoc.v:22225.3-22327.6" - wire width 2 $1\dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:23152.3-23254.6" - wire $1\dec31_dec_sub15_rsrv[0:0] - attribute \src "libresoc.v:23564.3-23666.6" - wire $1\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "libresoc.v:23358.3-23460.6" - wire $1\dec31_dec_sub15_sgn[0:0] - attribute \src "libresoc.v:22946.3-23048.6" - wire $1\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "libresoc.v:22122.3-22224.6" - wire width 2 $1\dec31_dec_sub15_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub15_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub15_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub15_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub15_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub15_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub15_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub15_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub15_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub15_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub15_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub15_in3_sel + attribute \src "libresoc.v:114661.3-114671.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:114672.3-114687.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:114601.3-114627.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:114628.3-114638.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:114579.3-114589.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:114639.3-114649.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:114650.3-114660.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:114552.3-114578.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:114688.3-114706.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:114590.3-114600.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:114661.3-114671.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:114672.3-114687.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:114688.3-114706.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:114672.3-114687.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:114545.17-114545.112" + wire $and$libresoc.v:114545$4538_Y + attribute \src "libresoc.v:114547.17-114547.112" + wire $and$libresoc.v:114547$4540_Y + attribute \src "libresoc.v:114544.17-114544.127" + wire $eq$libresoc.v:114544$4537_Y + attribute \src "libresoc.v:114546.17-114546.127" + wire $eq$libresoc.v:114546$4539_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 4 \SHIFT_ROT_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 3 \SHIFT_ROT_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 8 \SHIFT_ROT_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 7 \SHIFT_ROT_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 5 \SHIFT_ROT_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 input 6 \SHIFT_ROT_FXM attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -31632,3806 +179513,3953 @@ module \dec31_dec_sub15 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub15_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub15_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub15_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub15_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub15_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub15_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub15_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub15_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub15_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub15_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub15_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub15_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub15_upd - attribute \src "libresoc.v:21659.7-21659.15" + wire width 7 input 2 \SHIFT_ROT_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_fxm_ok + attribute \src "libresoc.v:114411.7-114411.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:21659.7-21659.20" - process $proc$libresoc.v:21659$506 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" + wire width 32 input 10 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:114545$4538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$libresoc.v:114545$4538_Y end - attribute \src "libresoc.v:21916.3-22018.6" - process $proc$libresoc.v:21916$482 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_function_unit[11:0] $1\dec31_dec_sub15_function_unit[11:0] - attribute \src "libresoc.v:21917.5-21917.29" - switch \initial - attribute \src "libresoc.v:21917.9-21917.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - case - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub15_function_unit $0\dec31_dec_sub15_function_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:114547$4540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$libresoc.v:114547$4540_Y end - attribute \src "libresoc.v:22019.3-22121.6" - process $proc$libresoc.v:22019$483 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_ldst_len[3:0] $1\dec31_dec_sub15_ldst_len[3:0] - attribute \src "libresoc.v:22020.5-22020.29" - switch \initial - attribute \src "libresoc.v:22020.9-22020.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub15_ldst_len $0\dec31_dec_sub15_ldst_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:114544$4537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SHIFT_ROT_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:114544$4537_Y end - attribute \src "libresoc.v:22122.3-22224.6" - process $proc$libresoc.v:22122$484 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_upd[1:0] $1\dec31_dec_sub15_upd[1:0] - attribute \src "libresoc.v:22123.5-22123.29" - switch \initial - attribute \src "libresoc.v:22123.9-22123.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub15_upd $0\dec31_dec_sub15_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:114546$4539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SHIFT_ROT_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:114546$4539_Y end - attribute \src "libresoc.v:22225.3-22327.6" - process $proc$libresoc.v:22225$485 - assign { } { } + attribute \module_not_derived 1 + attribute \src "libresoc.v:114548.15-114551.4" + cell \ppick$192 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:114411.7-114411.20" + process $proc$libresoc.v:114411$4551 assign { } { } - assign $0\dec31_dec_sub15_rc_sel[1:0] $1\dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:22226.5-22226.29" - switch \initial - attribute \src "libresoc.v:22226.9-22226.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - end + assign $0\initial[0:0] 1'0 sync always - update \dec31_dec_sub15_rc_sel $0\dec31_dec_sub15_rc_sel[1:0] + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:22328.3-22430.6" - process $proc$libresoc.v:22328$486 + attribute \src "libresoc.v:114552.3-114578.6" + process $proc$libresoc.v:114552$4541 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_cry_in[1:0] $1\dec31_dec_sub15_cry_in[1:0] - attribute \src "libresoc.v:22329.5-22329.29" + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:114553.5-114553.29" switch \initial - attribute \src "libresoc.v:22329.9-22329.17" + attribute \src "libresoc.v:114553.9-114553.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 3'001 assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 3'010 assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 3'011 assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 3'101 assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\cr_bitfield_ok[0:0] 1'1 case - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + assign $1\cr_bitfield_ok[0:0] 1'0 end sync always - update \dec31_dec_sub15_cry_in $0\dec31_dec_sub15_cry_in[1:0] + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:22431.3-22533.6" - process $proc$libresoc.v:22431$487 + attribute \src "libresoc.v:114579.3-114589.6" + process $proc$libresoc.v:114579$4542 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_asmcode[7:0] $1\dec31_dec_sub15_asmcode[7:0] - attribute \src "libresoc.v:22432.5-22432.29" + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:114580.5-114580.29" switch \initial - attribute \src "libresoc.v:22432.9-22432.17" + attribute \src "libresoc.v:114580.9-114580.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + assign $1\cr_bitfield_b_ok[0:0] 1'1 case - assign $1\dec31_dec_sub15_asmcode[7:0] 8'00000000 + assign $1\cr_bitfield_b_ok[0:0] 1'0 end sync always - update \dec31_dec_sub15_asmcode $0\dec31_dec_sub15_asmcode[7:0] + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] end - attribute \src "libresoc.v:22534.3-22636.6" - process $proc$libresoc.v:22534$488 + attribute \src "libresoc.v:114590.3-114600.6" + process $proc$libresoc.v:114590$4543 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_inv_a[0:0] $1\dec31_dec_sub15_inv_a[0:0] - attribute \src "libresoc.v:22535.5-22535.29" + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:114591.5-114591.29" switch \initial - attribute \src "libresoc.v:22535.9-22535.17" + attribute \src "libresoc.v:114591.9-114591.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11010 + case 3'110 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:114601.3-114627.6" + process $proc$libresoc.v:114601$4544 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:114602.5-114602.29" + switch \initial + attribute \src "libresoc.v:114602.9-114602.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 3'001 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\cr_bitfield[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 3'010 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\cr_bitfield[2:0] \SHIFT_ROT_BI [4:2] attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 3'011 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\cr_bitfield[2:0] \X_BFA attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\cr_bitfield[2:0] \SHIFT_ROT_BA [4:2] attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 3'101 assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\cr_bitfield[2:0] \SHIFT_ROT_BC [4:2] case - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + assign $1\cr_bitfield[2:0] 3'000 end sync always - update \dec31_dec_sub15_inv_a $0\dec31_dec_sub15_inv_a[0:0] + update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:22637.3-22739.6" - process $proc$libresoc.v:22637$489 + attribute \src "libresoc.v:114628.3-114638.6" + process $proc$libresoc.v:114628$4545 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_inv_out[0:0] $1\dec31_dec_sub15_inv_out[0:0] - attribute \src "libresoc.v:22638.5-22638.29" + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:114629.5-114629.29" switch \initial - attribute \src "libresoc.v:22638.9-22638.17" + attribute \src "libresoc.v:114629.9-114629.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\cr_bitfield_b[2:0] \SHIFT_ROT_BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end + sync always + update \cr_bitfield_b $0\cr_bitfield_b[2:0] + end + attribute \src "libresoc.v:114639.3-114649.6" + process $proc$libresoc.v:114639$4546 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:114640.5-114640.29" + switch \initial + attribute \src "libresoc.v:114640.9-114640.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\cr_bitfield_o[2:0] \SHIFT_ROT_BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] + end + attribute \src "libresoc.v:114650.3-114660.6" + process $proc$libresoc.v:114650$4547 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:114651.5-114651.29" + switch \initial + attribute \src "libresoc.v:114651.9-114651.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "libresoc.v:114661.3-114671.6" + process $proc$libresoc.v:114661$4548 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:114662.5-114662.29" + switch \initial + attribute \src "libresoc.v:114662.9-114662.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 3'110 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:114672.3-114687.6" + process $proc$libresoc.v:114672$4549 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:114673.5-114673.29" + switch \initial + attribute \src "libresoc.v:114673.9-114673.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 3'110 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \SHIFT_ROT_FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:114688.3-114706.6" + process $proc$libresoc.v:114688$4550 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:114689.5-114689.29" + switch \initial + attribute \src "libresoc.v:114689.9-114689.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 3'110 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:114544$4537_Y + connect \$3 $and$libresoc.v:114545$4538_Y + connect \$5 $eq$libresoc.v:114546$4539_Y + connect \$7 $and$libresoc.v:114547$4540_Y +end +attribute \src "libresoc.v:114711.1-115008.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_cr_in" +attribute \generator "nMigen" +module \dec_cr_in$199 + attribute \src "libresoc.v:114902.3-114928.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:114929.3-114939.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "libresoc.v:114880.3-114890.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:114940.3-114950.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "libresoc.v:114951.3-114961.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:114853.3-114879.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:114989.3-115007.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:114891.3-114901.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:114712.7-114712.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:114962.3-114972.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:114973.3-114988.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:114902.3-114928.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:114929.3-114939.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:114880.3-114890.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:114940.3-114950.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:114951.3-114961.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:114853.3-114879.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:114989.3-115007.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:114891.3-114901.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:114962.3-114972.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:114973.3-114988.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:114989.3-115007.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:114973.3-114988.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:114846.17-114846.112" + wire $and$libresoc.v:114846$4553_Y + attribute \src "libresoc.v:114848.17-114848.112" + wire $and$libresoc.v:114848$4555_Y + attribute \src "libresoc.v:114845.17-114845.122" + wire $eq$libresoc.v:114845$4552_Y + attribute \src "libresoc.v:114847.17-114847.122" + wire $eq$libresoc.v:114847$4554_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 4 \LDST_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 3 \LDST_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 8 \LDST_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 7 \LDST_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 5 \LDST_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 input 6 \LDST_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 input 2 \LDST_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_fxm_ok + attribute \src "libresoc.v:114712.7-114712.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" + wire width 32 input 10 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:114846$4553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$libresoc.v:114846$4553_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:114848$4555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$libresoc.v:114848$4555_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:114845$4552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LDST_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:114845$4552_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:114847$4554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LDST_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:114847$4554_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:114849.15-114852.4" + cell \ppick$200 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:114712.7-114712.20" + process $proc$libresoc.v:114712$4566 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:114853.3-114879.6" + process $proc$libresoc.v:114853$4556 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:114854.5-114854.29" + switch \initial + attribute \src "libresoc.v:114854.9-114854.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 3'001 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 3'010 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 3'011 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 3'101 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:114880.3-114890.6" + process $proc$libresoc.v:114880$4557 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:114881.5-114881.29" + switch \initial + attribute \src "libresoc.v:114881.9-114881.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\cr_bitfield_b_ok[0:0] 1'1 + case + assign $1\cr_bitfield_b_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + end + attribute \src "libresoc.v:114891.3-114901.6" + process $proc$libresoc.v:114891$4558 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:114892.5-114892.29" + switch \initial + attribute \src "libresoc.v:114892.9-114892.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 3'110 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:114902.3-114928.6" + process $proc$libresoc.v:114902$4559 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:114903.5-114903.29" + switch \initial + attribute \src "libresoc.v:114903.9-114903.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 3'001 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\cr_bitfield[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10001 + case 3'010 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\cr_bitfield[2:0] \LDST_BI [4:2] attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 3'011 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\cr_bitfield[2:0] \X_BFA attribute \src "libresoc.v:0.0-0.0" - case 5'10011 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\cr_bitfield[2:0] \LDST_BA [4:2] attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 3'101 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\cr_bitfield[2:0] \LDST_BC [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:114929.3-114939.6" + process $proc$libresoc.v:114929$4560 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:114930.5-114930.29" + switch \initial + attribute \src "libresoc.v:114930.9-114930.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10101 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\cr_bitfield_b[2:0] \LDST_BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end + sync always + update \cr_bitfield_b $0\cr_bitfield_b[2:0] + end + attribute \src "libresoc.v:114940.3-114950.6" + process $proc$libresoc.v:114940$4561 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:114941.5-114941.29" + switch \initial + attribute \src "libresoc.v:114941.9-114941.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\cr_bitfield_o[2:0] \LDST_BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] + end + attribute \src "libresoc.v:114951.3-114961.6" + process $proc$libresoc.v:114951$4562 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:114952.5-114952.29" + switch \initial + attribute \src "libresoc.v:114952.9-114952.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "libresoc.v:114962.3-114972.6" + process $proc$libresoc.v:114962$4563 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:114963.5-114963.29" + switch \initial + attribute \src "libresoc.v:114963.9-114963.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 3'110 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:114973.3-114988.6" + process $proc$libresoc.v:114973$4564 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:114974.5-114974.29" + switch \initial + attribute \src "libresoc.v:114974.9-114974.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 3'110 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \LDST_FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:114989.3-115007.6" + process $proc$libresoc.v:114989$4565 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:114990.5-114990.29" + switch \initial + attribute \src "libresoc.v:114990.9-114990.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11010 + case 3'110 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:114845$4552_Y + connect \$3 $and$libresoc.v:114846$4553_Y + connect \$5 $eq$libresoc.v:114847$4554_Y + connect \$7 $and$libresoc.v:114848$4555_Y +end +attribute \src "libresoc.v:115012.1-115317.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in" +attribute \generator "nMigen" +module \dec_cr_in$208 + attribute \src "libresoc.v:115211.3-115237.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:115238.3-115248.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "libresoc.v:115189.3-115199.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:115249.3-115259.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "libresoc.v:115260.3-115270.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:115162.3-115188.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:115298.3-115316.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:115200.3-115210.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:115013.7-115013.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:115271.3-115281.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:115282.3-115297.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:115211.3-115237.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:115238.3-115248.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:115189.3-115199.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:115249.3-115259.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:115260.3-115270.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:115162.3-115188.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:115298.3-115316.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:115200.3-115210.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:115271.3-115281.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:115282.3-115297.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:115298.3-115316.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:115282.3-115297.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:115155.17-115155.112" + wire $and$libresoc.v:115155$4568_Y + attribute \src "libresoc.v:115157.17-115157.112" + wire $and$libresoc.v:115157$4570_Y + attribute \src "libresoc.v:115154.17-115154.117" + wire $eq$libresoc.v:115154$4567_Y + attribute \src "libresoc.v:115156.17-115156.117" + wire $eq$libresoc.v:115156$4569_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 12 \BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 11 \BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 16 \BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 15 \BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 13 \BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 input 14 \FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 input 17 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 5 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 7 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 8 \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 9 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 10 \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 6 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 output 3 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \cr_fxm_ok + attribute \src "libresoc.v:115013.7-115013.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" + wire width 32 input 18 \insn_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 input 2 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:115155$4568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$libresoc.v:115155$4568_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:115157$4570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$libresoc.v:115157$4570_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:115154$4567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:115154$4567_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:115156$4569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:115156$4569_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:115158.15-115161.4" + cell \ppick$209 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:115013.7-115013.20" + process $proc$libresoc.v:115013$4581 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:115162.3-115188.6" + process $proc$libresoc.v:115162$4571 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:115163.5-115163.29" + switch \initial + attribute \src "libresoc.v:115163.9-115163.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 3'001 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 3'010 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 3'011 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 3'101 assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\cr_bitfield_ok[0:0] 1'1 case - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + assign $1\cr_bitfield_ok[0:0] 1'0 end sync always - update \dec31_dec_sub15_inv_out $0\dec31_dec_sub15_inv_out[0:0] + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:22740.3-22842.6" - process $proc$libresoc.v:22740$490 + attribute \src "libresoc.v:115189.3-115199.6" + process $proc$libresoc.v:115189$4572 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_cry_out[0:0] $1\dec31_dec_sub15_cry_out[0:0] - attribute \src "libresoc.v:22741.5-22741.29" + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:115190.5-115190.29" switch \initial - attribute \src "libresoc.v:22741.9-22741.17" + attribute \src "libresoc.v:115190.9-115190.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + assign $1\cr_bitfield_b_ok[0:0] 1'1 case - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + assign $1\cr_bitfield_b_ok[0:0] 1'0 end sync always - update \dec31_dec_sub15_cry_out $0\dec31_dec_sub15_cry_out[0:0] + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] end - attribute \src "libresoc.v:22843.3-22945.6" - process $proc$libresoc.v:22843$491 + attribute \src "libresoc.v:115200.3-115210.6" + process $proc$libresoc.v:115200$4573 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_br[0:0] $1\dec31_dec_sub15_br[0:0] - attribute \src "libresoc.v:22844.5-22844.29" + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:115201.5-115201.29" switch \initial - attribute \src "libresoc.v:22844.9-22844.17" + attribute \src "libresoc.v:115201.9-115201.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 3'110 assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 + assign $1\cr_fxm_ok[0:0] 1'1 case - assign $1\dec31_dec_sub15_br[0:0] 1'0 + assign $1\cr_fxm_ok[0:0] 1'0 end sync always - update \dec31_dec_sub15_br $0\dec31_dec_sub15_br[0:0] + update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:22946.3-23048.6" - process $proc$libresoc.v:22946$492 + attribute \src "libresoc.v:115211.3-115237.6" + process $proc$libresoc.v:115211$4574 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_sgn_ext[0:0] $1\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "libresoc.v:22947.5-22947.29" + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:115212.5-115212.29" switch \initial - attribute \src "libresoc.v:22947.9-22947.17" + attribute \src "libresoc.v:115212.9-115212.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 3'001 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\cr_bitfield[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 3'010 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\cr_bitfield[2:0] \BI [4:2] attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 3'011 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\cr_bitfield[2:0] \X_BFA attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\cr_bitfield[2:0] \BA [4:2] attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 3'101 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\cr_bitfield[2:0] \BC [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:115238.3-115248.6" + process $proc$libresoc.v:115238$4575 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:115239.5-115239.29" + switch \initial + attribute \src "libresoc.v:115239.9-115239.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\cr_bitfield_b[2:0] \BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end + sync always + update \cr_bitfield_b $0\cr_bitfield_b[2:0] + end + attribute \src "libresoc.v:115249.3-115259.6" + process $proc$libresoc.v:115249$4576 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:115250.5-115250.29" + switch \initial + attribute \src "libresoc.v:115250.9-115250.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\cr_bitfield_o[2:0] \BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] + end + attribute \src "libresoc.v:115260.3-115270.6" + process $proc$libresoc.v:115260$4577 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:115261.5-115261.29" + switch \initial + attribute \src "libresoc.v:115261.9-115261.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "libresoc.v:115271.3-115281.6" + process $proc$libresoc.v:115271$4578 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:115272.5-115272.29" + switch \initial + attribute \src "libresoc.v:115272.9-115272.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 3'110 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:115282.3-115297.6" + process $proc$libresoc.v:115282$4579 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:115283.5-115283.29" + switch \initial + attribute \src "libresoc.v:115283.9-115283.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10001 + case 3'110 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:115298.3-115316.6" + process $proc$libresoc.v:115298$4580 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:115299.5-115299.29" + switch \initial + attribute \src "libresoc.v:115299.9-115299.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 3'110 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:115154$4567_Y + connect \$3 $and$libresoc.v:115155$4568_Y + connect \$5 $eq$libresoc.v:115156$4569_Y + connect \$7 $and$libresoc.v:115157$4570_Y +end +attribute \src "libresoc.v:115321.1-115561.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out + attribute \src "libresoc.v:115475.3-115493.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:115445.3-115463.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:115526.3-115560.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:115464.3-115474.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:115322.7-115322.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:115494.3-115504.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:115505.3-115525.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:115475.3-115493.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:115445.3-115463.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:115526.3-115560.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:115464.3-115474.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:115494.3-115504.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:115505.3-115525.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:115526.3-115560.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:115505.3-115525.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:115526.3-115560.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "libresoc.v:115505.3-115525.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "libresoc.v:115526.3-115560.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "libresoc.v:115438.17-115438.121" + wire $eq$libresoc.v:115438$4582_Y + attribute \src "libresoc.v:115439.17-115439.121" + wire $eq$libresoc.v:115439$4583_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 input 5 \ALU_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 input 3 \ALU_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 input 7 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 input 6 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_fxm_ok + attribute \src "libresoc.v:115322.7-115322.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" + wire width 32 input 8 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:115438$4582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \ALU_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:115438$4582_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:115439$4583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \ALU_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:115439$4583_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:115440.15-115444.4" + cell \ppick$139 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:115322.7-115322.20" + process $proc$libresoc.v:115322$4590 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:115445.3-115463.6" + process $proc$libresoc.v:115445$4584 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:115446.5-115446.29" + switch \initial + attribute \src "libresoc.v:115446.9-115446.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10011 + case 3'001 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\cr_bitfield_ok[0:0] \rc_in attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 3'010 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10101 + case 3'011 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:115464.3-115474.6" + process $proc$libresoc.v:115464$4585 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:115465.5-115465.29" + switch \initial + attribute \src "libresoc.v:115465.9-115465.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:115475.3-115493.6" + process $proc$libresoc.v:115475$4586 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:115476.5-115476.29" + switch \initial + attribute \src "libresoc.v:115476.9-115476.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 3'001 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\cr_bitfield[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 3'010 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\cr_bitfield[2:0] \X_BF attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 3'011 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:115494.3-115504.6" + process $proc$libresoc.v:115494$4587 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:115495.5-115495.29" + switch \initial + attribute \src "libresoc.v:115495.9-115495.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11010 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:115505.3-115525.6" + process $proc$libresoc.v:115505$4588 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:115506.5-115506.29" + switch \initial + attribute \src "libresoc.v:115506.9-115506.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \ALU_FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:115526.3-115560.6" + process $proc$libresoc.v:115526$4589 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:115527.5-115527.29" + switch \initial + attribute \src "libresoc.v:115527.9-115527.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" + switch \ppick_en_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \ALU_FXM + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:115438$4582_Y + connect \$3 $eq$libresoc.v:115439$4583_Y +end +attribute \src "libresoc.v:115565.1-115804.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out$145 + attribute \src "libresoc.v:115718.3-115736.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:115688.3-115706.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:115769.3-115803.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:115707.3-115717.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:115566.7-115566.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:115737.3-115747.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:115748.3-115768.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:115718.3-115736.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:115688.3-115706.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:115769.3-115803.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:115707.3-115717.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:115737.3-115747.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:115748.3-115768.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:115769.3-115803.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:115748.3-115768.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:115769.3-115803.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "libresoc.v:115748.3-115768.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "libresoc.v:115769.3-115803.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "libresoc.v:115681.17-115681.120" + wire $eq$libresoc.v:115681$4591_Y + attribute \src "libresoc.v:115682.17-115682.120" + wire $eq$libresoc.v:115682$4592_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 input 4 \CR_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 input 3 \CR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 input 6 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 input 5 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_fxm_ok + attribute \src "libresoc.v:115566.7-115566.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" + wire width 32 input 7 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:115681$4591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \CR_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:115681$4591_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:115682$4592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \CR_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:115682$4592_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:115683.15-115687.4" + cell \ppick$146 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:115566.7-115566.20" + process $proc$libresoc.v:115566$4599 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:115688.3-115706.6" + process $proc$libresoc.v:115688$4593 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:115689.5-115689.29" + switch \initial + attribute \src "libresoc.v:115689.9-115689.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 3'001 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\cr_bitfield_ok[0:0] \rc_in attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 3'010 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 3'011 assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\cr_bitfield_ok[0:0] 1'1 case - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + assign $1\cr_bitfield_ok[0:0] 1'0 end sync always - update \dec31_dec_sub15_sgn_ext $0\dec31_dec_sub15_sgn_ext[0:0] + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:23049.3-23151.6" - process $proc$libresoc.v:23049$493 + attribute \src "libresoc.v:115707.3-115717.6" + process $proc$libresoc.v:115707$4594 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_internal_op[6:0] $1\dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:23050.5-23050.29" + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:115708.5-115708.29" switch \initial - attribute \src "libresoc.v:23050.9-23050.17" + attribute \src "libresoc.v:115708.9-115708.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:115718.3-115736.6" + process $proc$libresoc.v:115718$4595 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:115719.5-115719.29" + switch \initial + attribute \src "libresoc.v:115719.9-115719.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00110 + case 3'001 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\cr_bitfield[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00111 + case 3'010 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\cr_bitfield[2:0] \X_BF attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 3'011 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:115737.3-115747.6" + process $proc$libresoc.v:115737$4596 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:115738.5-115738.29" + switch \initial + attribute \src "libresoc.v:115738.9-115738.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:115748.3-115768.6" + process $proc$libresoc.v:115748$4597 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:115749.5-115749.29" + switch \initial + attribute \src "libresoc.v:115749.9-115749.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \CR_FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:115769.3-115803.6" + process $proc$libresoc.v:115769$4598 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:115770.5-115770.29" + switch \initial + attribute \src "libresoc.v:115770.9-115770.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" + switch \ppick_en_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \CR_FXM + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:115681$4591_Y + connect \$3 $eq$libresoc.v:115682$4592_Y +end +attribute \src "libresoc.v:115808.1-116047.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out$152 + attribute \src "libresoc.v:115961.3-115979.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:115931.3-115949.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:116012.3-116046.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:115950.3-115960.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:115809.7-115809.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:115980.3-115990.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:115991.3-116011.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:115961.3-115979.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:115931.3-115949.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:116012.3-116046.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:115950.3-115960.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:115980.3-115990.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:115991.3-116011.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:116012.3-116046.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:115991.3-116011.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:116012.3-116046.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "libresoc.v:115991.3-116011.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "libresoc.v:116012.3-116046.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "libresoc.v:115924.17-115924.124" + wire $eq$libresoc.v:115924$4600_Y + attribute \src "libresoc.v:115925.17-115925.124" + wire $eq$libresoc.v:115925$4601_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 input 4 \BRANCH_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 input 3 \BRANCH_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 input 6 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 input 5 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_fxm_ok + attribute \src "libresoc.v:115809.7-115809.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" + wire width 32 input 7 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:115924$4600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \BRANCH_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:115924$4600_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:115925$4601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \BRANCH_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:115925$4601_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:115926.15-115930.4" + cell \ppick$153 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:115809.7-115809.20" + process $proc$libresoc.v:115809$4608 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:115931.3-115949.6" + process $proc$libresoc.v:115931$4602 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:115932.5-115932.29" + switch \initial + attribute \src "libresoc.v:115932.9-115932.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 3'001 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\cr_bitfield_ok[0:0] \rc_in attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 3'010 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 + case 3'011 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:115950.3-115960.6" + process $proc$libresoc.v:115950$4603 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:115951.5-115951.29" + switch \initial + attribute \src "libresoc.v:115951.9-115951.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:115961.3-115979.6" + process $proc$libresoc.v:115961$4604 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:115962.5-115962.29" + switch \initial + attribute \src "libresoc.v:115962.9-115962.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10000 + case 3'001 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\cr_bitfield[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'10001 + case 3'010 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\cr_bitfield[2:0] \X_BF attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 3'011 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:115980.3-115990.6" + process $proc$libresoc.v:115980$4605 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:115981.5-115981.29" + switch \initial + attribute \src "libresoc.v:115981.9-115981.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10011 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:115991.3-116011.6" + process $proc$libresoc.v:115991$4606 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:115992.5-115992.29" + switch \initial + attribute \src "libresoc.v:115992.9-115992.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \BRANCH_FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:116012.3-116046.6" + process $proc$libresoc.v:116012$4607 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:116013.5-116013.29" + switch \initial + attribute \src "libresoc.v:116013.9-116013.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10101 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" + switch \ppick_en_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \BRANCH_FXM + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:115924$4600_Y + connect \$3 $eq$libresoc.v:115925$4601_Y +end +attribute \src "libresoc.v:116051.1-116291.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out$160 + attribute \src "libresoc.v:116205.3-116223.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:116175.3-116193.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:116256.3-116290.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:116194.3-116204.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:116052.7-116052.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:116224.3-116234.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:116235.3-116255.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:116205.3-116223.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:116175.3-116193.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:116256.3-116290.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:116194.3-116204.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:116224.3-116234.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:116235.3-116255.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:116256.3-116290.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:116235.3-116255.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:116256.3-116290.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "libresoc.v:116235.3-116255.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "libresoc.v:116256.3-116290.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "libresoc.v:116168.17-116168.125" + wire $eq$libresoc.v:116168$4609_Y + attribute \src "libresoc.v:116169.17-116169.125" + wire $eq$libresoc.v:116169$4610_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 input 5 \LOGICAL_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 input 3 \LOGICAL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 input 7 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 input 6 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_fxm_ok + attribute \src "libresoc.v:116052.7-116052.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" + wire width 32 input 8 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:116168$4609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LOGICAL_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:116168$4609_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:116169$4610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LOGICAL_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:116169$4610_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:116170.15-116174.4" + cell \ppick$161 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:116052.7-116052.20" + process $proc$libresoc.v:116052$4617 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:116175.3-116193.6" + process $proc$libresoc.v:116175$4611 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:116176.5-116176.29" + switch \initial + attribute \src "libresoc.v:116176.9-116176.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case 3'001 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\cr_bitfield_ok[0:0] \rc_in attribute \src "libresoc.v:0.0-0.0" - case 5'10111 + case 3'010 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 3'011 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:116194.3-116204.6" + process $proc$libresoc.v:116194$4612 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:116195.5-116195.29" + switch \initial + attribute \src "libresoc.v:116195.9-116195.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:116205.3-116223.6" + process $proc$libresoc.v:116205$4613 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:116206.5-116206.29" + switch \initial + attribute \src "libresoc.v:116206.9-116206.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11010 + case 3'001 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\cr_bitfield[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 3'010 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\cr_bitfield[2:0] \X_BF attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 3'011 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:116224.3-116234.6" + process $proc$libresoc.v:116224$4614 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:116225.5-116225.29" + switch \initial + attribute \src "libresoc.v:116225.9-116225.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:116235.3-116255.6" + process $proc$libresoc.v:116235$4615 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:116236.5-116236.29" + switch \initial + attribute \src "libresoc.v:116236.9-116236.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \LOGICAL_FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:116256.3-116290.6" + process $proc$libresoc.v:116256$4616 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:116257.5-116257.29" + switch \initial + attribute \src "libresoc.v:116257.9-116257.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" + switch \ppick_en_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \LOGICAL_FXM + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end case - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0000000 + assign $1\cr_fxm[7:0] 8'00000000 end sync always - update \dec31_dec_sub15_internal_op $0\dec31_dec_sub15_internal_op[6:0] + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:116168$4609_Y + connect \$3 $eq$libresoc.v:116169$4610_Y +end +attribute \src "libresoc.v:116295.1-116534.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out$169 + attribute \src "libresoc.v:116448.3-116466.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:116418.3-116436.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:116499.3-116533.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:116437.3-116447.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:116296.7-116296.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:116467.3-116477.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:116478.3-116498.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:116448.3-116466.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:116418.3-116436.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:116499.3-116533.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:116437.3-116447.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:116467.3-116477.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:116478.3-116498.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:116499.3-116533.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:116478.3-116498.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:116499.3-116533.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "libresoc.v:116478.3-116498.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "libresoc.v:116499.3-116533.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "libresoc.v:116411.17-116411.121" + wire $eq$libresoc.v:116411$4618_Y + attribute \src "libresoc.v:116412.17-116412.121" + wire $eq$libresoc.v:116412$4619_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 input 4 \SPR_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 input 3 \SPR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 input 6 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 input 5 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_fxm_ok + attribute \src "libresoc.v:116296.7-116296.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" + wire width 32 input 7 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:116411$4618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SPR_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:116411$4618_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:116412$4619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SPR_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:116412$4619_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:116413.15-116417.4" + cell \ppick$170 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:116296.7-116296.20" + process $proc$libresoc.v:116296$4626 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:23152.3-23254.6" - process $proc$libresoc.v:23152$494 + attribute \src "libresoc.v:116418.3-116436.6" + process $proc$libresoc.v:116418$4620 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_rsrv[0:0] $1\dec31_dec_sub15_rsrv[0:0] - attribute \src "libresoc.v:23153.5-23153.29" + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:116419.5-116419.29" switch \initial - attribute \src "libresoc.v:23153.9-23153.17" + attribute \src "libresoc.v:116419.9-116419.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 3'001 assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + assign $1\cr_bitfield_ok[0:0] \rc_in attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 3'010 assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 3'011 assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + assign $1\cr_bitfield_ok[0:0] 1'1 case - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + assign $1\cr_bitfield_ok[0:0] 1'0 end sync always - update \dec31_dec_sub15_rsrv $0\dec31_dec_sub15_rsrv[0:0] + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:23255.3-23357.6" - process $proc$libresoc.v:23255$495 + attribute \src "libresoc.v:116437.3-116447.6" + process $proc$libresoc.v:116437$4621 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_is_32b[0:0] $1\dec31_dec_sub15_is_32b[0:0] - attribute \src "libresoc.v:23256.5-23256.29" + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:116438.5-116438.29" switch \initial - attribute \src "libresoc.v:23256.9-23256.17" + attribute \src "libresoc.v:116438.9-116438.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\cr_fxm_ok[0:0] 1'1 case - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\cr_fxm_ok[0:0] 1'0 end sync always - update \dec31_dec_sub15_is_32b $0\dec31_dec_sub15_is_32b[0:0] + update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:23358.3-23460.6" - process $proc$libresoc.v:23358$496 + attribute \src "libresoc.v:116448.3-116466.6" + process $proc$libresoc.v:116448$4622 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_sgn[0:0] $1\dec31_dec_sub15_sgn[0:0] - attribute \src "libresoc.v:23359.5-23359.29" + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:116449.5-116449.29" switch \initial - attribute \src "libresoc.v:23359.9-23359.17" + attribute \src "libresoc.v:116449.9-116449.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 3'001 assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + assign $1\cr_bitfield[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 3'010 assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + assign $1\cr_bitfield[2:0] \X_BF attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 3'011 assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + assign $1\cr_bitfield[2:0] \XL_BT [4:2] case - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + assign $1\cr_bitfield[2:0] 3'000 end sync always - update \dec31_dec_sub15_sgn $0\dec31_dec_sub15_sgn[0:0] + update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:23461.3-23563.6" - process $proc$libresoc.v:23461$497 + attribute \src "libresoc.v:116467.3-116477.6" + process $proc$libresoc.v:116467$4623 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_lk[0:0] $1\dec31_dec_sub15_lk[0:0] - attribute \src "libresoc.v:23462.5-23462.29" + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:116468.5-116468.29" switch \initial - attribute \src "libresoc.v:23462.9-23462.17" + attribute \src "libresoc.v:116468.9-116468.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 + assign $1\move_one[0:0] \insn_in [20] case - assign $1\dec31_dec_sub15_lk[0:0] 1'0 + assign $1\move_one[0:0] 1'0 end sync always - update \dec31_dec_sub15_lk $0\dec31_dec_sub15_lk[0:0] + update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:23564.3-23666.6" - process $proc$libresoc.v:23564$498 + attribute \src "libresoc.v:116478.3-116498.6" + process $proc$libresoc.v:116478$4624 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_sgl_pipe[0:0] $1\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "libresoc.v:23565.5-23565.29" + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:116479.5-116479.29" switch \initial - attribute \src "libresoc.v:23565.9-23565.17" + attribute \src "libresoc.v:116479.9-116479.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \SPR_FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end case - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'0 + assign $1\ppick_i[7:0] 8'00000000 end sync always - update \dec31_dec_sub15_sgl_pipe $0\dec31_dec_sub15_sgl_pipe[0:0] + update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:23667.3-23769.6" - process $proc$libresoc.v:23667$499 + attribute \src "libresoc.v:116499.3-116533.6" + process $proc$libresoc.v:116499$4625 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_form[4:0] $1\dec31_dec_sub15_form[4:0] - attribute \src "libresoc.v:23668.5-23668.29" + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:116500.5-116500.29" switch \initial - attribute \src "libresoc.v:23668.9-23668.17" + attribute \src "libresoc.v:116500.9-116500.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" + switch \ppick_en_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \SPR_FXM + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end case - assign $1\dec31_dec_sub15_form[4:0] 5'00000 + assign $1\cr_fxm[7:0] 8'00000000 end sync always - update \dec31_dec_sub15_form $0\dec31_dec_sub15_form[4:0] + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:116411$4618_Y + connect \$3 $eq$libresoc.v:116412$4619_Y +end +attribute \src "libresoc.v:116538.1-116778.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out$176 + attribute \src "libresoc.v:116692.3-116710.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:116662.3-116680.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:116743.3-116777.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:116681.3-116691.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:116539.7-116539.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:116711.3-116721.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:116722.3-116742.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:116692.3-116710.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:116662.3-116680.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:116743.3-116777.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:116681.3-116691.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:116711.3-116721.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:116722.3-116742.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:116743.3-116777.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:116722.3-116742.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:116743.3-116777.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "libresoc.v:116722.3-116742.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "libresoc.v:116743.3-116777.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "libresoc.v:116655.17-116655.121" + wire $eq$libresoc.v:116655$4627_Y + attribute \src "libresoc.v:116656.17-116656.121" + wire $eq$libresoc.v:116656$4628_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 input 5 \DIV_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 input 3 \DIV_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 input 7 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 input 6 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_fxm_ok + attribute \src "libresoc.v:116539.7-116539.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" + wire width 32 input 8 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:116655$4627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \DIV_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:116655$4627_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:116656$4628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \DIV_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:116656$4628_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:116657.15-116661.4" + cell \ppick$177 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:116539.7-116539.20" + process $proc$libresoc.v:116539$4635 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:23770.3-23872.6" - process $proc$libresoc.v:23770$500 + attribute \src "libresoc.v:116662.3-116680.6" + process $proc$libresoc.v:116662$4629 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_in1_sel[2:0] $1\dec31_dec_sub15_in1_sel[2:0] - attribute \src "libresoc.v:23771.5-23771.29" + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:116663.5-116663.29" switch \initial - attribute \src "libresoc.v:23771.9-23771.17" + attribute \src "libresoc.v:116663.9-116663.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 3'001 assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + assign $1\cr_bitfield_ok[0:0] \rc_in attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 3'010 assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 3'011 assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + assign $1\cr_bitfield_ok[0:0] 1'1 case - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'000 + assign $1\cr_bitfield_ok[0:0] 1'0 end sync always - update \dec31_dec_sub15_in1_sel $0\dec31_dec_sub15_in1_sel[2:0] + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:23873.3-23975.6" - process $proc$libresoc.v:23873$501 + attribute \src "libresoc.v:116681.3-116691.6" + process $proc$libresoc.v:116681$4630 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_in2_sel[3:0] $1\dec31_dec_sub15_in2_sel[3:0] - attribute \src "libresoc.v:23874.5-23874.29" + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:116682.5-116682.29" switch \initial - attribute \src "libresoc.v:23874.9-23874.17" + attribute \src "libresoc.v:116682.9-116682.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + assign $1\cr_fxm_ok[0:0] 1'1 case - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0000 + assign $1\cr_fxm_ok[0:0] 1'0 end sync always - update \dec31_dec_sub15_in2_sel $0\dec31_dec_sub15_in2_sel[3:0] + update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:23976.3-24078.6" - process $proc$libresoc.v:23976$502 + attribute \src "libresoc.v:116692.3-116710.6" + process $proc$libresoc.v:116692$4631 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_in3_sel[1:0] $1\dec31_dec_sub15_in3_sel[1:0] - attribute \src "libresoc.v:23977.5-23977.29" + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:116693.5-116693.29" switch \initial - attribute \src "libresoc.v:23977.9-23977.17" + attribute \src "libresoc.v:116693.9-116693.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 3'001 assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + assign $1\cr_bitfield[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 3'010 assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + assign $1\cr_bitfield[2:0] \X_BF attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 3'011 assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + assign $1\cr_bitfield[2:0] \XL_BT [4:2] case - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + assign $1\cr_bitfield[2:0] 3'000 end sync always - update \dec31_dec_sub15_in3_sel $0\dec31_dec_sub15_in3_sel[1:0] + update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:24079.3-24181.6" - process $proc$libresoc.v:24079$503 + attribute \src "libresoc.v:116711.3-116721.6" + process $proc$libresoc.v:116711$4632 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_out_sel[1:0] $1\dec31_dec_sub15_out_sel[1:0] - attribute \src "libresoc.v:24080.5-24080.29" + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:116712.5-116712.29" switch \initial - attribute \src "libresoc.v:24080.9-24080.17" + attribute \src "libresoc.v:116712.9-116712.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\move_one[0:0] \insn_in [20] case - assign $1\dec31_dec_sub15_out_sel[1:0] 2'00 + assign $1\move_one[0:0] 1'0 end sync always - update \dec31_dec_sub15_out_sel $0\dec31_dec_sub15_out_sel[1:0] + update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:24182.3-24284.6" - process $proc$libresoc.v:24182$504 + attribute \src "libresoc.v:116722.3-116742.6" + process $proc$libresoc.v:116722$4633 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_cr_in[2:0] $1\dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:24183.5-24183.29" + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:116723.5-116723.29" switch \initial - attribute \src "libresoc.v:24183.9-24183.17" + attribute \src "libresoc.v:116723.9-116723.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \DIV_FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end case - assign $1\dec31_dec_sub15_cr_in[2:0] 3'000 + assign $1\ppick_i[7:0] 8'00000000 end sync always - update \dec31_dec_sub15_cr_in $0\dec31_dec_sub15_cr_in[2:0] + update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:24285.3-24387.6" - process $proc$libresoc.v:24285$505 + attribute \src "libresoc.v:116743.3-116777.6" + process $proc$libresoc.v:116743$4634 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_cr_out[2:0] $1\dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:24286.5-24286.29" + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:116744.5-116744.29" switch \initial - attribute \src "libresoc.v:24286.9-24286.17" + attribute \src "libresoc.v:116744.9-116744.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 3'100 assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - case - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub15_cr_out $0\dec31_dec_sub15_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:24393.1-24892.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub16" -attribute \generator "nMigen" -module \dec31_dec_sub16 - attribute \src "libresoc.v:24701.3-24710.6" - wire width 8 $0\dec31_dec_sub16_asmcode[7:0] - attribute \src "libresoc.v:24741.3-24750.6" - wire $0\dec31_dec_sub16_br[0:0] - attribute \src "libresoc.v:24871.3-24880.6" - wire width 3 $0\dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:24881.3-24890.6" - wire width 3 $0\dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:24691.3-24700.6" - wire width 2 $0\dec31_dec_sub16_cry_in[1:0] - attribute \src "libresoc.v:24731.3-24740.6" - wire $0\dec31_dec_sub16_cry_out[0:0] - attribute \src "libresoc.v:24821.3-24830.6" - wire width 5 $0\dec31_dec_sub16_form[4:0] - attribute \src "libresoc.v:24651.3-24660.6" - wire width 12 $0\dec31_dec_sub16_function_unit[11:0] - attribute \src "libresoc.v:24831.3-24840.6" - wire width 3 $0\dec31_dec_sub16_in1_sel[2:0] - attribute \src "libresoc.v:24841.3-24850.6" - wire width 4 $0\dec31_dec_sub16_in2_sel[3:0] - attribute \src "libresoc.v:24851.3-24860.6" - wire width 2 $0\dec31_dec_sub16_in3_sel[1:0] - attribute \src "libresoc.v:24761.3-24770.6" - wire width 7 $0\dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:24711.3-24720.6" - wire $0\dec31_dec_sub16_inv_a[0:0] - attribute \src "libresoc.v:24721.3-24730.6" - wire $0\dec31_dec_sub16_inv_out[0:0] - attribute \src "libresoc.v:24781.3-24790.6" - wire $0\dec31_dec_sub16_is_32b[0:0] - attribute \src "libresoc.v:24661.3-24670.6" - wire width 4 $0\dec31_dec_sub16_ldst_len[3:0] - attribute \src "libresoc.v:24801.3-24810.6" - wire $0\dec31_dec_sub16_lk[0:0] - attribute \src "libresoc.v:24861.3-24870.6" - wire width 2 $0\dec31_dec_sub16_out_sel[1:0] - attribute \src "libresoc.v:24681.3-24690.6" - wire width 2 $0\dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:24771.3-24780.6" - wire $0\dec31_dec_sub16_rsrv[0:0] - attribute \src "libresoc.v:24811.3-24820.6" - wire $0\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "libresoc.v:24791.3-24800.6" - wire $0\dec31_dec_sub16_sgn[0:0] - attribute \src "libresoc.v:24751.3-24760.6" - wire $0\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "libresoc.v:24671.3-24680.6" - wire width 2 $0\dec31_dec_sub16_upd[1:0] - attribute \src "libresoc.v:24394.7-24394.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:24701.3-24710.6" - wire width 8 $1\dec31_dec_sub16_asmcode[7:0] - attribute \src "libresoc.v:24741.3-24750.6" - wire $1\dec31_dec_sub16_br[0:0] - attribute \src "libresoc.v:24871.3-24880.6" - wire width 3 $1\dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:24881.3-24890.6" - wire width 3 $1\dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:24691.3-24700.6" - wire width 2 $1\dec31_dec_sub16_cry_in[1:0] - attribute \src "libresoc.v:24731.3-24740.6" - wire $1\dec31_dec_sub16_cry_out[0:0] - attribute \src "libresoc.v:24821.3-24830.6" - wire width 5 $1\dec31_dec_sub16_form[4:0] - attribute \src "libresoc.v:24651.3-24660.6" - wire width 12 $1\dec31_dec_sub16_function_unit[11:0] - attribute \src "libresoc.v:24831.3-24840.6" - wire width 3 $1\dec31_dec_sub16_in1_sel[2:0] - attribute \src "libresoc.v:24841.3-24850.6" - wire width 4 $1\dec31_dec_sub16_in2_sel[3:0] - attribute \src "libresoc.v:24851.3-24860.6" - wire width 2 $1\dec31_dec_sub16_in3_sel[1:0] - attribute \src "libresoc.v:24761.3-24770.6" - wire width 7 $1\dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:24711.3-24720.6" - wire $1\dec31_dec_sub16_inv_a[0:0] - attribute \src "libresoc.v:24721.3-24730.6" - wire $1\dec31_dec_sub16_inv_out[0:0] - attribute \src "libresoc.v:24781.3-24790.6" - wire $1\dec31_dec_sub16_is_32b[0:0] - attribute \src "libresoc.v:24661.3-24670.6" - wire width 4 $1\dec31_dec_sub16_ldst_len[3:0] - attribute \src "libresoc.v:24801.3-24810.6" - wire $1\dec31_dec_sub16_lk[0:0] - attribute \src "libresoc.v:24861.3-24870.6" - wire width 2 $1\dec31_dec_sub16_out_sel[1:0] - attribute \src "libresoc.v:24681.3-24690.6" - wire width 2 $1\dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:24771.3-24780.6" - wire $1\dec31_dec_sub16_rsrv[0:0] - attribute \src "libresoc.v:24811.3-24820.6" - wire $1\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "libresoc.v:24791.3-24800.6" - wire $1\dec31_dec_sub16_sgn[0:0] - attribute \src "libresoc.v:24751.3-24760.6" - wire $1\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "libresoc.v:24671.3-24680.6" - wire width 2 $1\dec31_dec_sub16_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub16_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub16_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub16_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub16_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub16_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub16_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub16_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub16_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub16_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub16_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub16_in3_sel + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" + switch \ppick_en_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \DIV_FXM + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:116655$4627_Y + connect \$3 $eq$libresoc.v:116656$4628_Y +end +attribute \src "libresoc.v:116782.1-117022.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out$185 + attribute \src "libresoc.v:116936.3-116954.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:116906.3-116924.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:116987.3-117021.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:116925.3-116935.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:116783.7-116783.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:116955.3-116965.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:116966.3-116986.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:116936.3-116954.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:116906.3-116924.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:116987.3-117021.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:116925.3-116935.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:116955.3-116965.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:116966.3-116986.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:116987.3-117021.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:116966.3-116986.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:116987.3-117021.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "libresoc.v:116966.3-116986.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "libresoc.v:116987.3-117021.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "libresoc.v:116899.17-116899.121" + wire $eq$libresoc.v:116899$4636_Y + attribute \src "libresoc.v:116900.17-116900.121" + wire $eq$libresoc.v:116900$4637_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 input 5 \MUL_FXM attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -35507,830 +183535,1165 @@ module \dec31_dec_sub16 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub16_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub16_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub16_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub16_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub16_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub16_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub16_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub16_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub16_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub16_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub16_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub16_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub16_upd - attribute \src "libresoc.v:24394.7-24394.15" + wire width 7 input 3 \MUL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 input 7 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 input 6 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_fxm_ok + attribute \src "libresoc.v:116783.7-116783.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:24394.7-24394.20" - process $proc$libresoc.v:24394$531 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" + wire width 32 input 8 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:116899$4636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \MUL_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:116899$4636_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:116900$4637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \MUL_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:116900$4637_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:116901.15-116905.4" + cell \ppick$186 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:116783.7-116783.20" + process $proc$libresoc.v:116783$4644 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:24651.3-24660.6" - process $proc$libresoc.v:24651$507 + attribute \src "libresoc.v:116906.3-116924.6" + process $proc$libresoc.v:116906$4638 assign { } { } assign { } { } - assign $0\dec31_dec_sub16_function_unit[11:0] $1\dec31_dec_sub16_function_unit[11:0] - attribute \src "libresoc.v:24652.5-24652.29" + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:116907.5-116907.29" switch \initial - attribute \src "libresoc.v:24652.9-24652.17" + attribute \src "libresoc.v:116907.9-116907.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 3'001 assign { } { } - assign $1\dec31_dec_sub16_function_unit[11:0] 12'000001000000 - case - assign $1\dec31_dec_sub16_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub16_function_unit $0\dec31_dec_sub16_function_unit[11:0] - end - attribute \src "libresoc.v:24661.3-24670.6" - process $proc$libresoc.v:24661$508 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_ldst_len[3:0] $1\dec31_dec_sub16_ldst_len[3:0] - attribute \src "libresoc.v:24662.5-24662.29" - switch \initial - attribute \src "libresoc.v:24662.9-24662.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\cr_bitfield_ok[0:0] \rc_in attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 3'010 assign { } { } - assign $1\dec31_dec_sub16_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub16_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub16_ldst_len $0\dec31_dec_sub16_ldst_len[3:0] - end - attribute \src "libresoc.v:24671.3-24680.6" - process $proc$libresoc.v:24671$509 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_upd[1:0] $1\dec31_dec_sub16_upd[1:0] - attribute \src "libresoc.v:24672.5-24672.29" - switch \initial - attribute \src "libresoc.v:24672.9-24672.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 3'011 assign { } { } - assign $1\dec31_dec_sub16_upd[1:0] 2'00 + assign $1\cr_bitfield_ok[0:0] 1'1 case - assign $1\dec31_dec_sub16_upd[1:0] 2'00 + assign $1\cr_bitfield_ok[0:0] 1'0 end sync always - update \dec31_dec_sub16_upd $0\dec31_dec_sub16_upd[1:0] + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:24681.3-24690.6" - process $proc$libresoc.v:24681$510 + attribute \src "libresoc.v:116925.3-116935.6" + process $proc$libresoc.v:116925$4639 assign { } { } assign { } { } - assign $0\dec31_dec_sub16_rc_sel[1:0] $1\dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:24682.5-24682.29" + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:116926.5-116926.29" switch \initial - attribute \src "libresoc.v:24682.9-24682.17" + attribute \src "libresoc.v:116926.9-116926.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 3'100 assign { } { } - assign $1\dec31_dec_sub16_rc_sel[1:0] 2'00 + assign $1\cr_fxm_ok[0:0] 1'1 case - assign $1\dec31_dec_sub16_rc_sel[1:0] 2'00 + assign $1\cr_fxm_ok[0:0] 1'0 end sync always - update \dec31_dec_sub16_rc_sel $0\dec31_dec_sub16_rc_sel[1:0] + update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:24691.3-24700.6" - process $proc$libresoc.v:24691$511 + attribute \src "libresoc.v:116936.3-116954.6" + process $proc$libresoc.v:116936$4640 assign { } { } assign { } { } - assign $0\dec31_dec_sub16_cry_in[1:0] $1\dec31_dec_sub16_cry_in[1:0] - attribute \src "libresoc.v:24692.5-24692.29" + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:116937.5-116937.29" switch \initial - attribute \src "libresoc.v:24692.9-24692.17" + attribute \src "libresoc.v:116937.9-116937.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 3'001 assign { } { } - assign $1\dec31_dec_sub16_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub16_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub16_cry_in $0\dec31_dec_sub16_cry_in[1:0] - end - attribute \src "libresoc.v:24701.3-24710.6" - process $proc$libresoc.v:24701$512 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_asmcode[7:0] $1\dec31_dec_sub16_asmcode[7:0] - attribute \src "libresoc.v:24702.5-24702.29" - switch \initial - attribute \src "libresoc.v:24702.9-24702.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\cr_bitfield[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 3'010 assign { } { } - assign $1\dec31_dec_sub16_asmcode[7:0] 8'01110110 - case - assign $1\dec31_dec_sub16_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub16_asmcode $0\dec31_dec_sub16_asmcode[7:0] - end - attribute \src "libresoc.v:24711.3-24720.6" - process $proc$libresoc.v:24711$513 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_inv_a[0:0] $1\dec31_dec_sub16_inv_a[0:0] - attribute \src "libresoc.v:24712.5-24712.29" - switch \initial - attribute \src "libresoc.v:24712.9-24712.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + assign $1\cr_bitfield[2:0] \X_BF attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 3'011 assign { } { } - assign $1\dec31_dec_sub16_inv_a[0:0] 1'0 + assign $1\cr_bitfield[2:0] \XL_BT [4:2] case - assign $1\dec31_dec_sub16_inv_a[0:0] 1'0 + assign $1\cr_bitfield[2:0] 3'000 end sync always - update \dec31_dec_sub16_inv_a $0\dec31_dec_sub16_inv_a[0:0] + update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:24721.3-24730.6" - process $proc$libresoc.v:24721$514 + attribute \src "libresoc.v:116955.3-116965.6" + process $proc$libresoc.v:116955$4641 assign { } { } assign { } { } - assign $0\dec31_dec_sub16_inv_out[0:0] $1\dec31_dec_sub16_inv_out[0:0] - attribute \src "libresoc.v:24722.5-24722.29" + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:116956.5-116956.29" switch \initial - attribute \src "libresoc.v:24722.9-24722.17" + attribute \src "libresoc.v:116956.9-116956.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 3'100 assign { } { } - assign $1\dec31_dec_sub16_inv_out[0:0] 1'0 + assign $1\move_one[0:0] \insn_in [20] case - assign $1\dec31_dec_sub16_inv_out[0:0] 1'0 + assign $1\move_one[0:0] 1'0 end sync always - update \dec31_dec_sub16_inv_out $0\dec31_dec_sub16_inv_out[0:0] + update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:24731.3-24740.6" - process $proc$libresoc.v:24731$515 + attribute \src "libresoc.v:116966.3-116986.6" + process $proc$libresoc.v:116966$4642 assign { } { } assign { } { } - assign $0\dec31_dec_sub16_cry_out[0:0] $1\dec31_dec_sub16_cry_out[0:0] - attribute \src "libresoc.v:24732.5-24732.29" + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:116967.5-116967.29" switch \initial - attribute \src "libresoc.v:24732.9-24732.17" + attribute \src "libresoc.v:116967.9-116967.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 3'100 assign { } { } - assign $1\dec31_dec_sub16_cry_out[0:0] 1'0 + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \MUL_FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end case - assign $1\dec31_dec_sub16_cry_out[0:0] 1'0 + assign $1\ppick_i[7:0] 8'00000000 end sync always - update \dec31_dec_sub16_cry_out $0\dec31_dec_sub16_cry_out[0:0] + update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:24741.3-24750.6" - process $proc$libresoc.v:24741$516 + attribute \src "libresoc.v:116987.3-117021.6" + process $proc$libresoc.v:116987$4643 assign { } { } assign { } { } - assign $0\dec31_dec_sub16_br[0:0] $1\dec31_dec_sub16_br[0:0] - attribute \src "libresoc.v:24742.5-24742.29" + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:116988.5-116988.29" switch \initial - attribute \src "libresoc.v:24742.9-24742.17" + attribute \src "libresoc.v:116988.9-116988.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 3'100 assign { } { } - assign $1\dec31_dec_sub16_br[0:0] 1'0 + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" + switch \ppick_en_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \MUL_FXM + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end case - assign $1\dec31_dec_sub16_br[0:0] 1'0 + assign $1\cr_fxm[7:0] 8'00000000 end sync always - update \dec31_dec_sub16_br $0\dec31_dec_sub16_br[0:0] + update \cr_fxm $0\cr_fxm[7:0] end - attribute \src "libresoc.v:24751.3-24760.6" - process $proc$libresoc.v:24751$517 - assign { } { } + connect \$1 $eq$libresoc.v:116899$4636_Y + connect \$3 $eq$libresoc.v:116900$4637_Y +end +attribute \src "libresoc.v:117026.1-117266.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out$193 + attribute \src "libresoc.v:117180.3-117198.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:117150.3-117168.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:117231.3-117265.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:117169.3-117179.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:117027.7-117027.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:117199.3-117209.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:117210.3-117230.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:117180.3-117198.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:117150.3-117168.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:117231.3-117265.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:117169.3-117179.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:117199.3-117209.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:117210.3-117230.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:117231.3-117265.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:117210.3-117230.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:117231.3-117265.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "libresoc.v:117210.3-117230.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "libresoc.v:117231.3-117265.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "libresoc.v:117143.17-117143.127" + wire $eq$libresoc.v:117143$4645_Y + attribute \src "libresoc.v:117144.17-117144.127" + wire $eq$libresoc.v:117144$4646_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 input 5 \SHIFT_ROT_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 input 3 \SHIFT_ROT_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 input 7 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 input 6 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_fxm_ok + attribute \src "libresoc.v:117027.7-117027.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" + wire width 32 input 8 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:117143$4645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SHIFT_ROT_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:117143$4645_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:117144$4646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SHIFT_ROT_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:117144$4646_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:117145.15-117149.4" + cell \ppick$194 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:117027.7-117027.20" + process $proc$libresoc.v:117027$4653 assign { } { } - assign $0\dec31_dec_sub16_sgn_ext[0:0] $1\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "libresoc.v:24752.5-24752.29" - switch \initial - attribute \src "libresoc.v:24752.9-24752.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub16_sgn_ext[0:0] 1'0 - end + assign $0\initial[0:0] 1'0 sync always - update \dec31_dec_sub16_sgn_ext $0\dec31_dec_sub16_sgn_ext[0:0] + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:24761.3-24770.6" - process $proc$libresoc.v:24761$518 + attribute \src "libresoc.v:117150.3-117168.6" + process $proc$libresoc.v:117150$4647 assign { } { } assign { } { } - assign $0\dec31_dec_sub16_internal_op[6:0] $1\dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:24762.5-24762.29" + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:117151.5-117151.29" switch \initial - attribute \src "libresoc.v:24762.9-24762.17" + attribute \src "libresoc.v:117151.9-117151.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 3'001 assign { } { } - assign $1\dec31_dec_sub16_internal_op[6:0] 7'0110000 + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 case - assign $1\dec31_dec_sub16_internal_op[6:0] 7'0000000 + assign $1\cr_bitfield_ok[0:0] 1'0 end sync always - update \dec31_dec_sub16_internal_op $0\dec31_dec_sub16_internal_op[6:0] + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:24771.3-24780.6" - process $proc$libresoc.v:24771$519 + attribute \src "libresoc.v:117169.3-117179.6" + process $proc$libresoc.v:117169$4648 assign { } { } assign { } { } - assign $0\dec31_dec_sub16_rsrv[0:0] $1\dec31_dec_sub16_rsrv[0:0] - attribute \src "libresoc.v:24772.5-24772.29" + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:117170.5-117170.29" switch \initial - attribute \src "libresoc.v:24772.9-24772.17" + attribute \src "libresoc.v:117170.9-117170.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 3'100 assign { } { } - assign $1\dec31_dec_sub16_rsrv[0:0] 1'0 + assign $1\cr_fxm_ok[0:0] 1'1 case - assign $1\dec31_dec_sub16_rsrv[0:0] 1'0 + assign $1\cr_fxm_ok[0:0] 1'0 end sync always - update \dec31_dec_sub16_rsrv $0\dec31_dec_sub16_rsrv[0:0] + update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:24781.3-24790.6" - process $proc$libresoc.v:24781$520 + attribute \src "libresoc.v:117180.3-117198.6" + process $proc$libresoc.v:117180$4649 assign { } { } assign { } { } - assign $0\dec31_dec_sub16_is_32b[0:0] $1\dec31_dec_sub16_is_32b[0:0] - attribute \src "libresoc.v:24782.5-24782.29" + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:117181.5-117181.29" switch \initial - attribute \src "libresoc.v:24782.9-24782.17" + attribute \src "libresoc.v:117181.9-117181.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 3'001 assign { } { } - assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BF + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \XL_BT [4:2] case - assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 + assign $1\cr_bitfield[2:0] 3'000 end sync always - update \dec31_dec_sub16_is_32b $0\dec31_dec_sub16_is_32b[0:0] + update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:24791.3-24800.6" - process $proc$libresoc.v:24791$521 + attribute \src "libresoc.v:117199.3-117209.6" + process $proc$libresoc.v:117199$4650 assign { } { } assign { } { } - assign $0\dec31_dec_sub16_sgn[0:0] $1\dec31_dec_sub16_sgn[0:0] - attribute \src "libresoc.v:24792.5-24792.29" + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:117200.5-117200.29" switch \initial - attribute \src "libresoc.v:24792.9-24792.17" + attribute \src "libresoc.v:117200.9-117200.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 3'100 assign { } { } - assign $1\dec31_dec_sub16_sgn[0:0] 1'0 + assign $1\move_one[0:0] \insn_in [20] case - assign $1\dec31_dec_sub16_sgn[0:0] 1'0 + assign $1\move_one[0:0] 1'0 end sync always - update \dec31_dec_sub16_sgn $0\dec31_dec_sub16_sgn[0:0] + update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:24801.3-24810.6" - process $proc$libresoc.v:24801$522 + attribute \src "libresoc.v:117210.3-117230.6" + process $proc$libresoc.v:117210$4651 assign { } { } assign { } { } - assign $0\dec31_dec_sub16_lk[0:0] $1\dec31_dec_sub16_lk[0:0] - attribute \src "libresoc.v:24802.5-24802.29" + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:117211.5-117211.29" switch \initial - attribute \src "libresoc.v:24802.9-24802.17" + attribute \src "libresoc.v:117211.9-117211.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 3'100 assign { } { } - assign $1\dec31_dec_sub16_lk[0:0] 1'0 + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \SHIFT_ROT_FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end case - assign $1\dec31_dec_sub16_lk[0:0] 1'0 + assign $1\ppick_i[7:0] 8'00000000 end sync always - update \dec31_dec_sub16_lk $0\dec31_dec_sub16_lk[0:0] + update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:24811.3-24820.6" - process $proc$libresoc.v:24811$523 + attribute \src "libresoc.v:117231.3-117265.6" + process $proc$libresoc.v:117231$4652 assign { } { } assign { } { } - assign $0\dec31_dec_sub16_sgl_pipe[0:0] $1\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "libresoc.v:24812.5-24812.29" + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:117232.5-117232.29" switch \initial - attribute \src "libresoc.v:24812.9-24812.17" + attribute \src "libresoc.v:117232.9-117232.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 3'100 assign { } { } - assign $1\dec31_dec_sub16_sgl_pipe[0:0] 1'0 + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" + switch \ppick_en_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \SHIFT_ROT_FXM + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end case - assign $1\dec31_dec_sub16_sgl_pipe[0:0] 1'0 + assign $1\cr_fxm[7:0] 8'00000000 end sync always - update \dec31_dec_sub16_sgl_pipe $0\dec31_dec_sub16_sgl_pipe[0:0] + update \cr_fxm $0\cr_fxm[7:0] end - attribute \src "libresoc.v:24821.3-24830.6" - process $proc$libresoc.v:24821$524 - assign { } { } + connect \$1 $eq$libresoc.v:117143$4645_Y + connect \$3 $eq$libresoc.v:117144$4646_Y +end +attribute \src "libresoc.v:117270.1-117509.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out$201 + attribute \src "libresoc.v:117423.3-117441.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:117393.3-117411.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:117474.3-117508.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:117412.3-117422.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:117271.7-117271.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:117442.3-117452.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:117453.3-117473.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:117423.3-117441.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:117393.3-117411.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:117474.3-117508.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:117412.3-117422.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:117442.3-117452.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:117453.3-117473.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:117474.3-117508.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:117453.3-117473.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:117474.3-117508.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "libresoc.v:117453.3-117473.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "libresoc.v:117474.3-117508.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "libresoc.v:117386.17-117386.122" + wire $eq$libresoc.v:117386$4654_Y + attribute \src "libresoc.v:117387.17-117387.122" + wire $eq$libresoc.v:117387$4655_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 input 4 \LDST_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 input 3 \LDST_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 input 6 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 input 5 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_fxm_ok + attribute \src "libresoc.v:117271.7-117271.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" + wire width 32 input 7 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:117386$4654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LDST_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:117386$4654_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:117387$4655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LDST_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:117387$4655_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:117388.15-117392.4" + cell \ppick$202 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:117271.7-117271.20" + process $proc$libresoc.v:117271$4662 assign { } { } - assign $0\dec31_dec_sub16_form[4:0] $1\dec31_dec_sub16_form[4:0] - attribute \src "libresoc.v:24822.5-24822.29" - switch \initial - attribute \src "libresoc.v:24822.9-24822.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_form[4:0] 5'01010 - case - assign $1\dec31_dec_sub16_form[4:0] 5'00000 - end + assign $0\initial[0:0] 1'0 sync always - update \dec31_dec_sub16_form $0\dec31_dec_sub16_form[4:0] + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:24831.3-24840.6" - process $proc$libresoc.v:24831$525 + attribute \src "libresoc.v:117393.3-117411.6" + process $proc$libresoc.v:117393$4656 assign { } { } assign { } { } - assign $0\dec31_dec_sub16_in1_sel[2:0] $1\dec31_dec_sub16_in1_sel[2:0] - attribute \src "libresoc.v:24832.5-24832.29" + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:117394.5-117394.29" switch \initial - attribute \src "libresoc.v:24832.9-24832.17" + attribute \src "libresoc.v:117394.9-117394.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 3'001 assign { } { } - assign $1\dec31_dec_sub16_in1_sel[2:0] 3'100 + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 case - assign $1\dec31_dec_sub16_in1_sel[2:0] 3'000 + assign $1\cr_bitfield_ok[0:0] 1'0 end sync always - update \dec31_dec_sub16_in1_sel $0\dec31_dec_sub16_in1_sel[2:0] + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:24841.3-24850.6" - process $proc$libresoc.v:24841$526 + attribute \src "libresoc.v:117412.3-117422.6" + process $proc$libresoc.v:117412$4657 assign { } { } assign { } { } - assign $0\dec31_dec_sub16_in2_sel[3:0] $1\dec31_dec_sub16_in2_sel[3:0] - attribute \src "libresoc.v:24842.5-24842.29" + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:117413.5-117413.29" switch \initial - attribute \src "libresoc.v:24842.9-24842.17" + attribute \src "libresoc.v:117413.9-117413.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 3'100 assign { } { } - assign $1\dec31_dec_sub16_in2_sel[3:0] 4'0000 + assign $1\cr_fxm_ok[0:0] 1'1 case - assign $1\dec31_dec_sub16_in2_sel[3:0] 4'0000 + assign $1\cr_fxm_ok[0:0] 1'0 end sync always - update \dec31_dec_sub16_in2_sel $0\dec31_dec_sub16_in2_sel[3:0] + update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:24851.3-24860.6" - process $proc$libresoc.v:24851$527 + attribute \src "libresoc.v:117423.3-117441.6" + process $proc$libresoc.v:117423$4658 assign { } { } assign { } { } - assign $0\dec31_dec_sub16_in3_sel[1:0] $1\dec31_dec_sub16_in3_sel[1:0] - attribute \src "libresoc.v:24852.5-24852.29" + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:117424.5-117424.29" switch \initial - attribute \src "libresoc.v:24852.9-24852.17" + attribute \src "libresoc.v:117424.9-117424.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 3'001 assign { } { } - assign $1\dec31_dec_sub16_in3_sel[1:0] 2'00 + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BF + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \XL_BT [4:2] case - assign $1\dec31_dec_sub16_in3_sel[1:0] 2'00 + assign $1\cr_bitfield[2:0] 3'000 end sync always - update \dec31_dec_sub16_in3_sel $0\dec31_dec_sub16_in3_sel[1:0] + update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:24861.3-24870.6" - process $proc$libresoc.v:24861$528 + attribute \src "libresoc.v:117442.3-117452.6" + process $proc$libresoc.v:117442$4659 assign { } { } assign { } { } - assign $0\dec31_dec_sub16_out_sel[1:0] $1\dec31_dec_sub16_out_sel[1:0] - attribute \src "libresoc.v:24862.5-24862.29" + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:117443.5-117443.29" switch \initial - attribute \src "libresoc.v:24862.9-24862.17" + attribute \src "libresoc.v:117443.9-117443.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 3'100 assign { } { } - assign $1\dec31_dec_sub16_out_sel[1:0] 2'00 + assign $1\move_one[0:0] \insn_in [20] case - assign $1\dec31_dec_sub16_out_sel[1:0] 2'00 + assign $1\move_one[0:0] 1'0 end sync always - update \dec31_dec_sub16_out_sel $0\dec31_dec_sub16_out_sel[1:0] + update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:24871.3-24880.6" - process $proc$libresoc.v:24871$529 + attribute \src "libresoc.v:117453.3-117473.6" + process $proc$libresoc.v:117453$4660 assign { } { } assign { } { } - assign $0\dec31_dec_sub16_cr_in[2:0] $1\dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:24872.5-24872.29" + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:117454.5-117454.29" switch \initial - attribute \src "libresoc.v:24872.9-24872.17" + attribute \src "libresoc.v:117454.9-117454.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 3'100 assign { } { } - assign $1\dec31_dec_sub16_cr_in[2:0] 3'110 + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \LDST_FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end case - assign $1\dec31_dec_sub16_cr_in[2:0] 3'000 + assign $1\ppick_i[7:0] 8'00000000 end sync always - update \dec31_dec_sub16_cr_in $0\dec31_dec_sub16_cr_in[2:0] + update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:24881.3-24890.6" - process $proc$libresoc.v:24881$530 + attribute \src "libresoc.v:117474.3-117508.6" + process $proc$libresoc.v:117474$4661 assign { } { } assign { } { } - assign $0\dec31_dec_sub16_cr_out[2:0] $1\dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:24882.5-24882.29" + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:117475.5-117475.29" switch \initial - attribute \src "libresoc.v:24882.9-24882.17" + attribute \src "libresoc.v:117475.9-117475.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 3'100 assign { } { } - assign $1\dec31_dec_sub16_cr_out[2:0] 3'100 + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" + switch \ppick_en_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \LDST_FXM + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end case - assign $1\dec31_dec_sub16_cr_out[2:0] 3'000 + assign $1\cr_fxm[7:0] 8'00000000 end sync always - update \dec31_dec_sub16_cr_out $0\dec31_dec_sub16_cr_out[2:0] + update \cr_fxm $0\cr_fxm[7:0] end - connect \opcode_switch \opcode_in [10:6] + connect \$1 $eq$libresoc.v:117386$4654_Y + connect \$3 $eq$libresoc.v:117387$4655_Y end -attribute \src "libresoc.v:24896.1-25683.10" +attribute \src "libresoc.v:117513.1-117756.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub18" -attribute \generator "nMigen" -module \dec31_dec_sub18 - attribute \src "libresoc.v:25264.3-25285.6" - wire width 8 $0\dec31_dec_sub18_asmcode[7:0] - attribute \src "libresoc.v:25352.3-25373.6" - wire $0\dec31_dec_sub18_br[0:0] - attribute \src "libresoc.v:25638.3-25659.6" - wire width 3 $0\dec31_dec_sub18_cr_in[2:0] - attribute \src "libresoc.v:25660.3-25681.6" - wire width 3 $0\dec31_dec_sub18_cr_out[2:0] - attribute \src "libresoc.v:25242.3-25263.6" - wire width 2 $0\dec31_dec_sub18_cry_in[1:0] - attribute \src "libresoc.v:25330.3-25351.6" - wire $0\dec31_dec_sub18_cry_out[0:0] - attribute \src "libresoc.v:25528.3-25549.6" - wire width 5 $0\dec31_dec_sub18_form[4:0] - attribute \src "libresoc.v:25154.3-25175.6" - wire width 12 $0\dec31_dec_sub18_function_unit[11:0] - attribute \src "libresoc.v:25550.3-25571.6" - wire width 3 $0\dec31_dec_sub18_in1_sel[2:0] - attribute \src "libresoc.v:25572.3-25593.6" - wire width 4 $0\dec31_dec_sub18_in2_sel[3:0] - attribute \src "libresoc.v:25594.3-25615.6" - wire width 2 $0\dec31_dec_sub18_in3_sel[1:0] - attribute \src "libresoc.v:25396.3-25417.6" - wire width 7 $0\dec31_dec_sub18_internal_op[6:0] - attribute \src "libresoc.v:25286.3-25307.6" - wire $0\dec31_dec_sub18_inv_a[0:0] - attribute \src "libresoc.v:25308.3-25329.6" - wire $0\dec31_dec_sub18_inv_out[0:0] - attribute \src "libresoc.v:25440.3-25461.6" - wire $0\dec31_dec_sub18_is_32b[0:0] - attribute \src "libresoc.v:25176.3-25197.6" - wire width 4 $0\dec31_dec_sub18_ldst_len[3:0] - attribute \src "libresoc.v:25484.3-25505.6" - wire $0\dec31_dec_sub18_lk[0:0] - attribute \src "libresoc.v:25616.3-25637.6" - wire width 2 $0\dec31_dec_sub18_out_sel[1:0] - attribute \src "libresoc.v:25220.3-25241.6" - wire width 2 $0\dec31_dec_sub18_rc_sel[1:0] - attribute \src "libresoc.v:25418.3-25439.6" - wire $0\dec31_dec_sub18_rsrv[0:0] - attribute \src "libresoc.v:25506.3-25527.6" - wire $0\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "libresoc.v:25462.3-25483.6" - wire $0\dec31_dec_sub18_sgn[0:0] - attribute \src "libresoc.v:25374.3-25395.6" - wire $0\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "libresoc.v:25198.3-25219.6" - wire width 2 $0\dec31_dec_sub18_upd[1:0] - attribute \src "libresoc.v:24897.7-24897.20" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out$210 + attribute \src "libresoc.v:117670.3-117688.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:117640.3-117658.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:117721.3-117755.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:117659.3-117669.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:117514.7-117514.20" wire $0\initial[0:0] - attribute \src "libresoc.v:25264.3-25285.6" - wire width 8 $1\dec31_dec_sub18_asmcode[7:0] - attribute \src "libresoc.v:25352.3-25373.6" - wire $1\dec31_dec_sub18_br[0:0] - attribute \src "libresoc.v:25638.3-25659.6" - wire width 3 $1\dec31_dec_sub18_cr_in[2:0] - attribute \src "libresoc.v:25660.3-25681.6" - wire width 3 $1\dec31_dec_sub18_cr_out[2:0] - attribute \src "libresoc.v:25242.3-25263.6" - wire width 2 $1\dec31_dec_sub18_cry_in[1:0] - attribute \src "libresoc.v:25330.3-25351.6" - wire $1\dec31_dec_sub18_cry_out[0:0] - attribute \src "libresoc.v:25528.3-25549.6" - wire width 5 $1\dec31_dec_sub18_form[4:0] - attribute \src "libresoc.v:25154.3-25175.6" - wire width 12 $1\dec31_dec_sub18_function_unit[11:0] - attribute \src "libresoc.v:25550.3-25571.6" - wire width 3 $1\dec31_dec_sub18_in1_sel[2:0] - attribute \src "libresoc.v:25572.3-25593.6" - wire width 4 $1\dec31_dec_sub18_in2_sel[3:0] - attribute \src "libresoc.v:25594.3-25615.6" - wire width 2 $1\dec31_dec_sub18_in3_sel[1:0] - attribute \src "libresoc.v:25396.3-25417.6" - wire width 7 $1\dec31_dec_sub18_internal_op[6:0] - attribute \src "libresoc.v:25286.3-25307.6" - wire $1\dec31_dec_sub18_inv_a[0:0] - attribute \src "libresoc.v:25308.3-25329.6" - wire $1\dec31_dec_sub18_inv_out[0:0] - attribute \src "libresoc.v:25440.3-25461.6" - wire $1\dec31_dec_sub18_is_32b[0:0] - attribute \src "libresoc.v:25176.3-25197.6" - wire width 4 $1\dec31_dec_sub18_ldst_len[3:0] - attribute \src "libresoc.v:25484.3-25505.6" - wire $1\dec31_dec_sub18_lk[0:0] - attribute \src "libresoc.v:25616.3-25637.6" - wire width 2 $1\dec31_dec_sub18_out_sel[1:0] - attribute \src "libresoc.v:25220.3-25241.6" - wire width 2 $1\dec31_dec_sub18_rc_sel[1:0] - attribute \src "libresoc.v:25418.3-25439.6" - wire $1\dec31_dec_sub18_rsrv[0:0] - attribute \src "libresoc.v:25506.3-25527.6" - wire $1\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "libresoc.v:25462.3-25483.6" - wire $1\dec31_dec_sub18_sgn[0:0] - attribute \src "libresoc.v:25374.3-25395.6" - wire $1\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "libresoc.v:25198.3-25219.6" - wire width 2 $1\dec31_dec_sub18_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub18_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub18_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub18_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub18_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub18_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub18_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub18_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub18_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub18_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub18_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub18_in3_sel + attribute \src "libresoc.v:117689.3-117699.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:117700.3-117720.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:117670.3-117688.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:117640.3-117658.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:117721.3-117755.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:117659.3-117669.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:117689.3-117699.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:117700.3-117720.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:117721.3-117755.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:117700.3-117720.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:117721.3-117755.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "libresoc.v:117700.3-117720.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "libresoc.v:117721.3-117755.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "libresoc.v:117633.17-117633.117" + wire $eq$libresoc.v:117633$4663_Y + attribute \src "libresoc.v:117634.17-117634.117" + wire $eq$libresoc.v:117634$4664_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 input 8 \FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 input 10 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 input 9 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 6 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 7 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 output 4 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 5 \cr_fxm_ok + attribute \src "libresoc.v:117514.7-117514.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" + wire width 32 input 11 \insn_in attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -36406,1214 +184769,1631 @@ module \dec31_dec_sub18 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub18_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub18_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub18_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub18_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub18_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub18_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub18_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub18_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub18_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub18_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub18_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub18_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub18_upd - attribute \src "libresoc.v:24897.7-24897.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:24897.7-24897.20" - process $proc$libresoc.v:24897$556 + wire width 7 input 3 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:117633$4663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:117633$4663_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:117634$4664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:117634$4664_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:117635.15-117639.4" + cell \ppick$211 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:117514.7-117514.20" + process $proc$libresoc.v:117514$4671 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:25154.3-25175.6" - process $proc$libresoc.v:25154$532 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_function_unit[11:0] $1\dec31_dec_sub18_function_unit[11:0] - attribute \src "libresoc.v:25155.5-25155.29" - switch \initial - attribute \src "libresoc.v:25155.9-25155.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_function_unit[11:0] 12'000010000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_function_unit[11:0] 12'000010000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_function_unit[11:0] 12'100000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_function_unit[11:0] 12'100000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_function_unit[11:0] 12'100000000000 - case - assign $1\dec31_dec_sub18_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub18_function_unit $0\dec31_dec_sub18_function_unit[11:0] - end - attribute \src "libresoc.v:25176.3-25197.6" - process $proc$libresoc.v:25176$533 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_ldst_len[3:0] $1\dec31_dec_sub18_ldst_len[3:0] - attribute \src "libresoc.v:25177.5-25177.29" - switch \initial - attribute \src "libresoc.v:25177.9-25177.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub18_ldst_len $0\dec31_dec_sub18_ldst_len[3:0] - end - attribute \src "libresoc.v:25198.3-25219.6" - process $proc$libresoc.v:25198$534 + attribute \src "libresoc.v:117640.3-117658.6" + process $proc$libresoc.v:117640$4665 assign { } { } assign { } { } - assign $0\dec31_dec_sub18_upd[1:0] $1\dec31_dec_sub18_upd[1:0] - attribute \src "libresoc.v:25199.5-25199.29" + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:117641.5-117641.29" switch \initial - attribute \src "libresoc.v:25199.9-25199.17" + attribute \src "libresoc.v:117641.9-117641.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 3'001 assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 + assign $1\cr_bitfield_ok[0:0] \rc_in attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 3'010 assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 + assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 3'011 assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 + assign $1\cr_bitfield_ok[0:0] 1'1 case - assign $1\dec31_dec_sub18_upd[1:0] 2'00 + assign $1\cr_bitfield_ok[0:0] 1'0 end sync always - update \dec31_dec_sub18_upd $0\dec31_dec_sub18_upd[1:0] + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:25220.3-25241.6" - process $proc$libresoc.v:25220$535 + attribute \src "libresoc.v:117659.3-117669.6" + process $proc$libresoc.v:117659$4666 assign { } { } assign { } { } - assign $0\dec31_dec_sub18_rc_sel[1:0] $1\dec31_dec_sub18_rc_sel[1:0] - attribute \src "libresoc.v:25221.5-25221.29" + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:117660.5-117660.29" switch \initial - attribute \src "libresoc.v:25221.9-25221.17" + attribute \src "libresoc.v:117660.9-117660.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 3'100 assign { } { } - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + assign $1\cr_fxm_ok[0:0] 1'1 case - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + assign $1\cr_fxm_ok[0:0] 1'0 end sync always - update \dec31_dec_sub18_rc_sel $0\dec31_dec_sub18_rc_sel[1:0] + update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:25242.3-25263.6" - process $proc$libresoc.v:25242$536 + attribute \src "libresoc.v:117670.3-117688.6" + process $proc$libresoc.v:117670$4667 assign { } { } assign { } { } - assign $0\dec31_dec_sub18_cry_in[1:0] $1\dec31_dec_sub18_cry_in[1:0] - attribute \src "libresoc.v:25243.5-25243.29" + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:117671.5-117671.29" switch \initial - attribute \src "libresoc.v:25243.9-25243.17" + attribute \src "libresoc.v:117671.9-117671.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'01111 + case 3'001 assign { } { } - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + assign $1\cr_bitfield[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 3'010 assign { } { } - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + assign $1\cr_bitfield[2:0] \X_BF attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 3'011 assign { } { } - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + assign $1\cr_bitfield[2:0] \XL_BT [4:2] case - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + assign $1\cr_bitfield[2:0] 3'000 end sync always - update \dec31_dec_sub18_cry_in $0\dec31_dec_sub18_cry_in[1:0] + update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:25264.3-25285.6" - process $proc$libresoc.v:25264$537 + attribute \src "libresoc.v:117689.3-117699.6" + process $proc$libresoc.v:117689$4668 assign { } { } assign { } { } - assign $0\dec31_dec_sub18_asmcode[7:0] $1\dec31_dec_sub18_asmcode[7:0] - attribute \src "libresoc.v:25265.5-25265.29" + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:117690.5-117690.29" switch \initial - attribute \src "libresoc.v:25265.9-25265.17" + attribute \src "libresoc.v:117690.9-117690.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_asmcode[7:0] 8'01111000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_asmcode[7:0] 8'01110111 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_asmcode[7:0] 8'10011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_asmcode[7:0] 8'11001100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 3'100 assign { } { } - assign $1\dec31_dec_sub18_asmcode[7:0] 8'11001101 + assign $1\move_one[0:0] \insn_in [20] case - assign $1\dec31_dec_sub18_asmcode[7:0] 8'00000000 + assign $1\move_one[0:0] 1'0 end sync always - update \dec31_dec_sub18_asmcode $0\dec31_dec_sub18_asmcode[7:0] + update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:25286.3-25307.6" - process $proc$libresoc.v:25286$538 + attribute \src "libresoc.v:117700.3-117720.6" + process $proc$libresoc.v:117700$4669 assign { } { } assign { } { } - assign $0\dec31_dec_sub18_inv_a[0:0] $1\dec31_dec_sub18_inv_a[0:0] - attribute \src "libresoc.v:25287.5-25287.29" + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:117701.5-117701.29" switch \initial - attribute \src "libresoc.v:25287.9-25287.17" + attribute \src "libresoc.v:117701.9-117701.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 3'100 assign { } { } - assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end case - assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + assign $1\ppick_i[7:0] 8'00000000 end sync always - update \dec31_dec_sub18_inv_a $0\dec31_dec_sub18_inv_a[0:0] + update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:25308.3-25329.6" - process $proc$libresoc.v:25308$539 + attribute \src "libresoc.v:117721.3-117755.6" + process $proc$libresoc.v:117721$4670 assign { } { } assign { } { } - assign $0\dec31_dec_sub18_inv_out[0:0] $1\dec31_dec_sub18_inv_out[0:0] - attribute \src "libresoc.v:25309.5-25309.29" + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:117722.5-117722.29" switch \initial - attribute \src "libresoc.v:25309.9-25309.17" + attribute \src "libresoc.v:117722.9-117722.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 3'100 assign { } { } - assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" + switch \ppick_en_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \FXM + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end case - assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + assign $1\cr_fxm[7:0] 8'00000000 end sync always - update \dec31_dec_sub18_inv_out $0\dec31_dec_sub18_inv_out[0:0] + update \cr_fxm $0\cr_fxm[7:0] end - attribute \src "libresoc.v:25330.3-25351.6" - process $proc$libresoc.v:25330$540 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_cry_out[0:0] $1\dec31_dec_sub18_cry_out[0:0] - attribute \src "libresoc.v:25331.5-25331.29" - switch \initial - attribute \src "libresoc.v:25331.9-25331.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_cry_out $0\dec31_dec_sub18_cry_out[0:0] + connect \$1 $eq$libresoc.v:117633$4663_Y + connect \$3 $eq$libresoc.v:117634$4664_Y +end +attribute \src "libresoc.v:117760.1-118237.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o" +attribute \generator "nMigen" +module \dec_o + attribute \src "libresoc.v:118198.3-118236.6" + wire width 3 $0\fast_o[2:0] + attribute \src "libresoc.v:118198.3-118236.6" + wire $0\fast_o_ok[0:0] + attribute \src "libresoc.v:117761.7-117761.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:118124.3-118138.6" + wire width 5 $0\reg_o[4:0] + attribute \src "libresoc.v:118139.3-118153.6" + wire $0\reg_o_ok[0:0] + attribute \src "libresoc.v:118154.3-118164.6" + wire width 10 $0\spr[9:0] + attribute \src "libresoc.v:118181.3-118197.6" + wire width 10 $0\spr_o[9:0] + attribute \src "libresoc.v:118181.3-118197.6" + wire $0\spr_o_ok[0:0] + attribute \src "libresoc.v:118165.3-118180.6" + wire width 10 $0\sprmap_spr_i[9:0] + attribute \src "libresoc.v:118198.3-118236.6" + wire width 3 $1\fast_o[2:0] + attribute \src "libresoc.v:118198.3-118236.6" + wire $1\fast_o_ok[0:0] + attribute \src "libresoc.v:118124.3-118138.6" + wire width 5 $1\reg_o[4:0] + attribute \src "libresoc.v:118139.3-118153.6" + wire $1\reg_o_ok[0:0] + attribute \src "libresoc.v:118154.3-118164.6" + wire width 10 $1\spr[9:0] + attribute \src "libresoc.v:118181.3-118197.6" + wire width 10 $1\spr_o[9:0] + attribute \src "libresoc.v:118181.3-118197.6" + wire $1\spr_o_ok[0:0] + attribute \src "libresoc.v:118165.3-118180.6" + wire width 10 $1\sprmap_spr_i[9:0] + attribute \src "libresoc.v:118198.3-118236.6" + wire width 3 $2\fast_o[2:0] + attribute \src "libresoc.v:118198.3-118236.6" + wire $2\fast_o_ok[0:0] + attribute \src "libresoc.v:118181.3-118197.6" + wire width 10 $2\spr_o[9:0] + attribute \src "libresoc.v:118181.3-118197.6" + wire $2\spr_o_ok[0:0] + attribute \src "libresoc.v:118165.3-118180.6" + wire width 10 $2\sprmap_spr_i[9:0] + attribute \src "libresoc.v:118198.3-118236.6" + wire width 3 $3\fast_o[2:0] + attribute \src "libresoc.v:118198.3-118236.6" + wire $3\fast_o_ok[0:0] + attribute \src "libresoc.v:118198.3-118236.6" + wire width 3 $4\fast_o[2:0] + attribute \src "libresoc.v:118198.3-118236.6" + wire $4\fast_o_ok[0:0] + attribute \src "libresoc.v:118113.17-118113.117" + wire $eq$libresoc.v:118113$4672_Y + attribute \src "libresoc.v:118114.17-118114.117" + wire $eq$libresoc.v:118114$4673_Y + attribute \src "libresoc.v:118115.17-118115.117" + wire $eq$libresoc.v:118115$4674_Y + attribute \src "libresoc.v:118116.17-118116.104" + wire $not$libresoc.v:118116$4675_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 10 \BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 9 \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 8 \RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 10 input 11 \SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 6 \fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 7 \fast_o_ok + attribute \src "libresoc.v:117761.7-117761.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 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attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 input 12 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 output 2 \reg_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \reg_o_ok + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311" + wire width 2 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + wire width 10 \spr + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 output 4 \spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 5 \spr_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \sprmap_fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \sprmap_fast_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62" + wire width 10 \sprmap_spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 \sprmap_spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \sprmap_spr_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + cell $eq $eq$libresoc.v:118113$4672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:118113$4672_Y end - attribute \src "libresoc.v:25352.3-25373.6" - process $proc$libresoc.v:25352$541 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_br[0:0] $1\dec31_dec_sub18_br[0:0] - attribute \src "libresoc.v:25353.5-25353.29" - switch \initial - attribute \src "libresoc.v:25353.9-25353.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_br[0:0] 1'0 - case - assign $1\dec31_dec_sub18_br[0:0] 1'0 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + cell $eq $eq$libresoc.v:118114$4673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:118114$4673_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + cell $eq $eq$libresoc.v:118115$4674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:118115$4674_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" + cell $not $not$libresoc.v:118116$4675 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \BO [2] + connect \Y $not$libresoc.v:118116$4675_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:118117.16-118123.4" + cell \sprmap$212 \sprmap + connect \fast_o \sprmap_fast_o + connect \fast_o_ok \sprmap_fast_o_ok + connect \spr_i \sprmap_spr_i + connect \spr_o \sprmap_spr_o + connect \spr_o_ok \sprmap_spr_o_ok + end + attribute \src "libresoc.v:117761.7-117761.20" + process $proc$libresoc.v:117761$4682 + assign { } { } + assign $0\initial[0:0] 1'0 sync always - update \dec31_dec_sub18_br $0\dec31_dec_sub18_br[0:0] + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:25374.3-25395.6" - process $proc$libresoc.v:25374$542 + attribute \src "libresoc.v:118124.3-118138.6" + process $proc$libresoc.v:118124$4676 assign { } { } assign { } { } - assign $0\dec31_dec_sub18_sgn_ext[0:0] $1\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "libresoc.v:25375.5-25375.29" + assign $0\reg_o[4:0] $1\reg_o[4:0] + attribute \src "libresoc.v:118125.5-118125.29" switch \initial - attribute \src "libresoc.v:25375.9-25375.17" + attribute \src "libresoc.v:118125.9-118125.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 2'01 assign { } { } - assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + assign $1\reg_o[4:0] \RT attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 2'10 assign { } { } - assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + assign $1\reg_o[4:0] \RA case - assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + assign $1\reg_o[4:0] 5'00000 end sync always - update \dec31_dec_sub18_sgn_ext $0\dec31_dec_sub18_sgn_ext[0:0] + update \reg_o $0\reg_o[4:0] end - attribute \src "libresoc.v:25396.3-25417.6" - process $proc$libresoc.v:25396$543 + attribute \src "libresoc.v:118139.3-118153.6" + process $proc$libresoc.v:118139$4677 assign { } { } assign { } { } - assign $0\dec31_dec_sub18_internal_op[6:0] $1\dec31_dec_sub18_internal_op[6:0] - attribute \src "libresoc.v:25397.5-25397.29" + assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0] + attribute \src "libresoc.v:118140.5-118140.29" switch \initial - attribute \src "libresoc.v:25397.9-25397.17" + attribute \src "libresoc.v:118140.9-118140.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 2'01 assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + assign $1\reg_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 2'10 assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + assign $1\reg_o_ok[0:0] 1'1 case - assign $1\dec31_dec_sub18_internal_op[6:0] 7'0000000 + assign $1\reg_o_ok[0:0] 1'0 end sync always - update \dec31_dec_sub18_internal_op $0\dec31_dec_sub18_internal_op[6:0] + update \reg_o_ok $0\reg_o_ok[0:0] end - attribute \src "libresoc.v:25418.3-25439.6" - process $proc$libresoc.v:25418$544 + attribute \src "libresoc.v:118154.3-118164.6" + process $proc$libresoc.v:118154$4678 assign { } { } assign { } { } - assign $0\dec31_dec_sub18_rsrv[0:0] $1\dec31_dec_sub18_rsrv[0:0] - attribute \src "libresoc.v:25419.5-25419.29" + assign $0\spr[9:0] $1\spr[9:0] + attribute \src "libresoc.v:118155.5-118155.29" switch \initial - attribute \src "libresoc.v:25419.9-25419.17" + attribute \src "libresoc.v:118155.9-118155.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 2'11 assign { } { } - assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + assign $1\spr[9:0] { \SPR [4:0] \SPR [9:5] } case - assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + assign $1\spr[9:0] 10'0000000000 end sync always - update \dec31_dec_sub18_rsrv $0\dec31_dec_sub18_rsrv[0:0] + update \spr $0\spr[9:0] end - attribute \src "libresoc.v:25440.3-25461.6" - process $proc$libresoc.v:25440$545 + attribute \src "libresoc.v:118165.3-118180.6" + process $proc$libresoc.v:118165$4679 assign { } { } assign { } { } - assign $0\dec31_dec_sub18_is_32b[0:0] $1\dec31_dec_sub18_is_32b[0:0] - attribute \src "libresoc.v:25441.5-25441.29" + assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] + attribute \src "libresoc.v:118166.5-118166.29" switch \initial - attribute \src "libresoc.v:25441.9-25441.17" + attribute \src "libresoc.v:118166.9-118166.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 2'11 assign { } { } - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + assign $1\sprmap_spr_i[9:0] $2\sprmap_spr_i[9:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sprmap_spr_i[9:0] \spr + case + assign $2\sprmap_spr_i[9:0] 10'0000000000 + end case - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + assign $1\sprmap_spr_i[9:0] 10'0000000000 end sync always - update \dec31_dec_sub18_is_32b $0\dec31_dec_sub18_is_32b[0:0] + update \sprmap_spr_i $0\sprmap_spr_i[9:0] end - attribute \src "libresoc.v:25462.3-25483.6" - process $proc$libresoc.v:25462$546 + attribute \src "libresoc.v:118181.3-118197.6" + process $proc$libresoc.v:118181$4680 assign { } { } assign { } { } - assign $0\dec31_dec_sub18_sgn[0:0] $1\dec31_dec_sub18_sgn[0:0] - attribute \src "libresoc.v:25463.5-25463.29" + assign { } { } + assign { } { } + assign $0\spr_o[9:0] $1\spr_o[9:0] + assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] + attribute \src "libresoc.v:118182.5-118182.29" switch \initial - attribute \src "libresoc.v:25463.9-25463.17" + attribute \src "libresoc.v:118182.9-118182.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 2'11 assign { } { } - assign $1\dec31_dec_sub18_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 assign { } { } - assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + assign $1\spr_o[9:0] $2\spr_o[9:0] + assign $1\spr_o_ok[0:0] $2\spr_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\spr_o_ok[0:0] $2\spr_o[9:0] } { \sprmap_spr_o_ok \sprmap_spr_o } + case + assign $2\spr_o[9:0] 10'0000000000 + assign $2\spr_o_ok[0:0] 1'0 + end case - assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + assign $1\spr_o[9:0] 10'0000000000 + assign $1\spr_o_ok[0:0] 1'0 end sync always - update \dec31_dec_sub18_sgn $0\dec31_dec_sub18_sgn[0:0] + update \spr_o $0\spr_o[9:0] + update \spr_o_ok $0\spr_o_ok[0:0] end - attribute \src "libresoc.v:25484.3-25505.6" - process $proc$libresoc.v:25484$547 + attribute \src "libresoc.v:118198.3-118236.6" + process $proc$libresoc.v:118198$4681 assign { } { } assign { } { } - assign $0\dec31_dec_sub18_lk[0:0] $1\dec31_dec_sub18_lk[0:0] - attribute \src "libresoc.v:25485.5-25485.29" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast_o[2:0] $3\fast_o[2:0] + assign $0\fast_o_ok[0:0] $3\fast_o_ok[0:0] + attribute \src "libresoc.v:118199.5-118199.29" switch \initial - attribute \src "libresoc.v:25485.9-25485.17" + attribute \src "libresoc.v:118199.9-118199.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 2'11 assign { } { } - assign $1\dec31_dec_sub18_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 assign { } { } - assign $1\dec31_dec_sub18_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub18_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_lk $0\dec31_dec_sub18_lk[0:0] - end - attribute \src "libresoc.v:25506.3-25527.6" - process $proc$libresoc.v:25506$548 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_sgl_pipe[0:0] $1\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "libresoc.v:25507.5-25507.29" - switch \initial - attribute \src "libresoc.v:25507.9-25507.17" - case 1'1 + assign $1\fast_o[2:0] $2\fast_o[2:0] + assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + switch \$5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\fast_o_ok[0:0] $2\fast_o[2:0] } { \sprmap_fast_o_ok \sprmap_fast_o } + case + assign $2\fast_o[2:0] 3'000 + assign $2\fast_o_ok[0:0] 1'0 + end case + assign $1\fast_o[2:0] 3'000 + assign $1\fast_o_ok[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:340" + switch \internal_op attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 7'0000111 , 7'0001000 assign { } { } - assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 assign { } { } - assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + assign $3\fast_o[2:0] $4\fast_o[2:0] + assign $3\fast_o_ok[0:0] $4\fast_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $4\fast_o[2:0] 3'000 + assign $4\fast_o_ok[0:0] 1'1 + case + assign $4\fast_o[2:0] $1\fast_o[2:0] + assign $4\fast_o_ok[0:0] $1\fast_o_ok[0:0] + end attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 7'1000110 assign { } { } - assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 assign { } { } - assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + assign $3\fast_o[2:0] 3'011 + assign $3\fast_o_ok[0:0] 1'1 case - assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + assign $3\fast_o[2:0] $1\fast_o[2:0] + assign $3\fast_o_ok[0:0] $1\fast_o_ok[0:0] end sync always - update \dec31_dec_sub18_sgl_pipe $0\dec31_dec_sub18_sgl_pipe[0:0] + update \fast_o $0\fast_o[2:0] + update \fast_o_ok $0\fast_o_ok[0:0] end - attribute \src "libresoc.v:25528.3-25549.6" - process $proc$libresoc.v:25528$549 - assign { } { } + connect \$1 $eq$libresoc.v:118113$4672_Y + connect \$3 $eq$libresoc.v:118114$4673_Y + connect \$5 $eq$libresoc.v:118115$4674_Y + connect \$7 $not$libresoc.v:118116$4675_Y +end +attribute \src "libresoc.v:118241.1-118402.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o2" +attribute \generator "nMigen" +module \dec_o2 + attribute \src "libresoc.v:118362.3-118381.6" + wire width 3 $0\fast_o[2:0] + attribute \src "libresoc.v:118382.3-118401.6" + wire $0\fast_o_ok[0:0] + attribute \src "libresoc.v:118242.7-118242.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:118348.3-118361.6" + wire width 5 $0\reg_o[4:0] + attribute \src "libresoc.v:118348.3-118361.6" + wire $0\reg_o_ok[0:0] + attribute \src "libresoc.v:118362.3-118381.6" + wire width 3 $1\fast_o[2:0] + attribute \src "libresoc.v:118382.3-118401.6" + wire $1\fast_o_ok[0:0] + attribute \src "libresoc.v:118348.3-118361.6" + wire width 5 $1\reg_o[4:0] + attribute \src "libresoc.v:118348.3-118361.6" + wire $1\reg_o_ok[0:0] + attribute \src "libresoc.v:118362.3-118381.6" + wire width 3 $2\fast_o[2:0] + attribute \src "libresoc.v:118382.3-118401.6" + wire $2\fast_o_ok[0:0] + attribute \src "libresoc.v:118346.17-118346.108" + wire $eq$libresoc.v:118346$4683_Y + attribute \src "libresoc.v:118347.17-118347.100" + wire width 6 $extend$libresoc.v:118347$4684_Y + attribute \src "libresoc.v:118347.17-118347.100" + wire width 6 $pos$libresoc.v:118347$4685_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:377" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 6 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 7 \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 4 \fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 5 \fast_o_ok + attribute \src "libresoc.v:118242.7-118242.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 input 8 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:366" + wire input 1 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 output 2 \reg_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \reg_o_ok + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 input 6 \upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:377" + cell $eq $eq$libresoc.v:118346$4683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \upd + connect \B 2'01 + connect \Y $eq$libresoc.v:118346$4683_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:118347$4684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 6 + connect \A \RA + connect \Y $extend$libresoc.v:118347$4684_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:118347$4685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A $extend$libresoc.v:118347$4684_Y + connect \Y $pos$libresoc.v:118347$4685_Y + end + attribute \src "libresoc.v:118242.7-118242.20" + process $proc$libresoc.v:118242$4689 assign { } { } - assign $0\dec31_dec_sub18_form[4:0] $1\dec31_dec_sub18_form[4:0] - attribute \src "libresoc.v:25529.5-25529.29" - switch \initial - attribute \src "libresoc.v:25529.9-25529.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_form[4:0] 5'01000 - case - assign $1\dec31_dec_sub18_form[4:0] 5'00000 - end + assign $0\initial[0:0] 1'0 sync always - update \dec31_dec_sub18_form $0\dec31_dec_sub18_form[4:0] + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:25550.3-25571.6" - process $proc$libresoc.v:25550$550 + attribute \src "libresoc.v:118348.3-118361.6" + process $proc$libresoc.v:118348$4686 assign { } { } assign { } { } - assign $0\dec31_dec_sub18_in1_sel[2:0] $1\dec31_dec_sub18_in1_sel[2:0] - attribute \src "libresoc.v:25551.5-25551.29" + assign { } { } + assign { } { } + assign $0\reg_o[4:0] $1\reg_o[4:0] + assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0] + attribute \src "libresoc.v:118349.5-118349.29" switch \initial - attribute \src "libresoc.v:25551.9-25551.17" + attribute \src "libresoc.v:118349.9-118349.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:377" + switch \$1 attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 1'1 assign { } { } - assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 assign { } { } - assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + assign $1\reg_o[4:0] \$3 [4:0] + assign $1\reg_o_ok[0:0] 1'1 case - assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + assign $1\reg_o[4:0] 5'00000 + assign $1\reg_o_ok[0:0] 1'0 end sync always - update \dec31_dec_sub18_in1_sel $0\dec31_dec_sub18_in1_sel[2:0] + update \reg_o $0\reg_o[4:0] + update \reg_o_ok $0\reg_o_ok[0:0] end - attribute \src "libresoc.v:25572.3-25593.6" - process $proc$libresoc.v:25572$551 + attribute \src "libresoc.v:118362.3-118381.6" + process $proc$libresoc.v:118362$4687 assign { } { } assign { } { } - assign $0\dec31_dec_sub18_in2_sel[3:0] $1\dec31_dec_sub18_in2_sel[3:0] - attribute \src "libresoc.v:25573.5-25573.29" + assign $0\fast_o[2:0] $1\fast_o[2:0] + attribute \src "libresoc.v:118363.5-118363.29" switch \initial - attribute \src "libresoc.v:25573.9-25573.17" + attribute \src "libresoc.v:118363.9-118363.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + switch \internal_op attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 7'0000111 , 7'0000110 , 7'0001000 assign { } { } - assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0001 + assign $1\fast_o[2:0] $2\fast_o[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:388" + switch \lk + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast_o[2:0] 3'001 + case + assign $2\fast_o[2:0] 3'000 + end attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 7'1000110 assign { } { } - assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0001 + assign $1\fast_o[2:0] 3'100 case - assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + assign $1\fast_o[2:0] 3'000 end sync always - update \dec31_dec_sub18_in2_sel $0\dec31_dec_sub18_in2_sel[3:0] + update \fast_o $0\fast_o[2:0] end - attribute \src "libresoc.v:25594.3-25615.6" - process $proc$libresoc.v:25594$552 + attribute \src "libresoc.v:118382.3-118401.6" + process $proc$libresoc.v:118382$4688 assign { } { } assign { } { } - assign $0\dec31_dec_sub18_in3_sel[1:0] $1\dec31_dec_sub18_in3_sel[1:0] - attribute \src "libresoc.v:25595.5-25595.29" + assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] + attribute \src "libresoc.v:118383.5-118383.29" switch \initial - attribute \src "libresoc.v:25595.9-25595.17" + attribute \src "libresoc.v:118383.9-118383.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + switch \internal_op attribute \src "libresoc.v:0.0-0.0" - case 5'01001 + case 7'0000111 , 7'0000110 , 7'0001000 assign { } { } - assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:388" + switch \lk + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast_o_ok[0:0] 1'1 + case + assign $2\fast_o_ok[0:0] 1'0 + end attribute \src "libresoc.v:0.0-0.0" - case 5'01000 + case 7'1000110 assign { } { } - assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + assign $1\fast_o_ok[0:0] 1'1 case - assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + assign $1\fast_o_ok[0:0] 1'0 end sync always - update \dec31_dec_sub18_in3_sel $0\dec31_dec_sub18_in3_sel[1:0] + update \fast_o_ok $0\fast_o_ok[0:0] end - attribute \src "libresoc.v:25616.3-25637.6" - process $proc$libresoc.v:25616$553 - assign { } { } + connect \$1 $eq$libresoc.v:118346$4683_Y + connect \$3 $pos$libresoc.v:118347$4685_Y +end +attribute \src "libresoc.v:118406.1-118540.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_oe" +attribute \generator "nMigen" +module \dec_oe + attribute \src "libresoc.v:118407.7-118407.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:118498.3-118518.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:118519.3-118539.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:118498.3-118518.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:118519.3-118539.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:118498.3-118518.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:118519.3-118539.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire input 4 \ALU_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 input 1 \ALU_internal_op + attribute \src "libresoc.v:118407.7-118407.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:118407.7-118407.20" + process $proc$libresoc.v:118407$4692 assign { } { } - assign $0\dec31_dec_sub18_out_sel[1:0] $1\dec31_dec_sub18_out_sel[1:0] - attribute \src "libresoc.v:25617.5-25617.29" - switch \initial - attribute \src "libresoc.v:25617.9-25617.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 - end + assign $0\initial[0:0] 1'0 sync always - update \dec31_dec_sub18_out_sel $0\dec31_dec_sub18_out_sel[1:0] + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:25638.3-25659.6" - process $proc$libresoc.v:25638$554 + attribute \src "libresoc.v:118498.3-118518.6" + process $proc$libresoc.v:118498$4690 assign { } { } assign { } { } - assign $0\dec31_dec_sub18_cr_in[2:0] $1\dec31_dec_sub18_cr_in[2:0] - attribute \src "libresoc.v:25639.5-25639.29" + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:118499.5-118499.29" switch \initial - attribute \src "libresoc.v:25639.9-25639.17" + attribute \src "libresoc.v:118499.9-118499.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + switch \ALU_internal_op attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 case - assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \ALU_OE + case + assign $2\oe[0:0] 1'0 + end end sync always - update \dec31_dec_sub18_cr_in $0\dec31_dec_sub18_cr_in[2:0] + update \oe $0\oe[0:0] end - attribute \src "libresoc.v:25660.3-25681.6" - process $proc$libresoc.v:25660$555 + attribute \src "libresoc.v:118519.3-118539.6" + process $proc$libresoc.v:118519$4691 assign { } { } assign { } { } - assign $0\dec31_dec_sub18_cr_out[2:0] $1\dec31_dec_sub18_cr_out[2:0] - attribute \src "libresoc.v:25661.5-25661.29" + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:118520.5-118520.29" switch \initial - attribute \src "libresoc.v:25661.9-25661.17" + attribute \src "libresoc.v:118520.9-118520.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + switch \ALU_internal_op attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 case - assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end end sync always - update \dec31_dec_sub18_cr_out $0\dec31_dec_sub18_cr_out[2:0] + update \oe_ok $0\oe_ok[0:0] end - connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:25687.1-26402.10" +attribute \src "libresoc.v:118544.1-118676.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub19" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_oe" attribute \generator "nMigen" -module \dec31_dec_sub19 - attribute \src "libresoc.v:26040.3-26058.6" - wire width 8 $0\dec31_dec_sub19_asmcode[7:0] - attribute \src "libresoc.v:26116.3-26134.6" - wire $0\dec31_dec_sub19_br[0:0] - attribute \src "libresoc.v:26363.3-26381.6" - wire width 3 $0\dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:26382.3-26400.6" - wire width 3 $0\dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:26021.3-26039.6" - wire width 2 $0\dec31_dec_sub19_cry_in[1:0] - attribute \src "libresoc.v:26097.3-26115.6" - wire $0\dec31_dec_sub19_cry_out[0:0] - attribute \src "libresoc.v:26268.3-26286.6" - wire width 5 $0\dec31_dec_sub19_form[4:0] - attribute \src "libresoc.v:25945.3-25963.6" - wire width 12 $0\dec31_dec_sub19_function_unit[11:0] - attribute \src "libresoc.v:26287.3-26305.6" - wire width 3 $0\dec31_dec_sub19_in1_sel[2:0] - attribute \src "libresoc.v:26306.3-26324.6" - wire width 4 $0\dec31_dec_sub19_in2_sel[3:0] - attribute \src "libresoc.v:26325.3-26343.6" - wire width 2 $0\dec31_dec_sub19_in3_sel[1:0] - attribute \src "libresoc.v:26154.3-26172.6" - wire width 7 $0\dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:26059.3-26077.6" - wire $0\dec31_dec_sub19_inv_a[0:0] - attribute \src "libresoc.v:26078.3-26096.6" - wire $0\dec31_dec_sub19_inv_out[0:0] - attribute \src "libresoc.v:26192.3-26210.6" - wire $0\dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:25964.3-25982.6" - wire width 4 $0\dec31_dec_sub19_ldst_len[3:0] - attribute \src "libresoc.v:26230.3-26248.6" - wire $0\dec31_dec_sub19_lk[0:0] - attribute \src "libresoc.v:26344.3-26362.6" - wire width 2 $0\dec31_dec_sub19_out_sel[1:0] - attribute \src "libresoc.v:26002.3-26020.6" - wire width 2 $0\dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:26173.3-26191.6" - wire $0\dec31_dec_sub19_rsrv[0:0] - attribute \src "libresoc.v:26249.3-26267.6" - wire $0\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "libresoc.v:26211.3-26229.6" - wire $0\dec31_dec_sub19_sgn[0:0] - attribute \src "libresoc.v:26135.3-26153.6" - wire $0\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "libresoc.v:25983.3-26001.6" - wire width 2 $0\dec31_dec_sub19_upd[1:0] - attribute \src "libresoc.v:25688.7-25688.20" +module \dec_oe$142 + attribute \src "libresoc.v:118545.7-118545.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26040.3-26058.6" - wire width 8 $1\dec31_dec_sub19_asmcode[7:0] - attribute \src "libresoc.v:26116.3-26134.6" - wire $1\dec31_dec_sub19_br[0:0] - attribute \src "libresoc.v:26363.3-26381.6" - wire width 3 $1\dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:26382.3-26400.6" - wire width 3 $1\dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:26021.3-26039.6" - wire width 2 $1\dec31_dec_sub19_cry_in[1:0] - attribute \src "libresoc.v:26097.3-26115.6" - wire $1\dec31_dec_sub19_cry_out[0:0] - attribute \src "libresoc.v:26268.3-26286.6" - wire width 5 $1\dec31_dec_sub19_form[4:0] - attribute \src "libresoc.v:25945.3-25963.6" - wire width 12 $1\dec31_dec_sub19_function_unit[11:0] - attribute \src "libresoc.v:26287.3-26305.6" - wire width 3 $1\dec31_dec_sub19_in1_sel[2:0] - attribute \src "libresoc.v:26306.3-26324.6" - wire width 4 $1\dec31_dec_sub19_in2_sel[3:0] - attribute \src "libresoc.v:26325.3-26343.6" - wire width 2 $1\dec31_dec_sub19_in3_sel[1:0] - attribute \src "libresoc.v:26154.3-26172.6" - wire width 7 $1\dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:26059.3-26077.6" - wire $1\dec31_dec_sub19_inv_a[0:0] - attribute \src "libresoc.v:26078.3-26096.6" - wire $1\dec31_dec_sub19_inv_out[0:0] - attribute \src "libresoc.v:26192.3-26210.6" - wire $1\dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:25964.3-25982.6" - wire width 4 $1\dec31_dec_sub19_ldst_len[3:0] - attribute \src "libresoc.v:26230.3-26248.6" - wire $1\dec31_dec_sub19_lk[0:0] - attribute \src "libresoc.v:26344.3-26362.6" - wire width 2 $1\dec31_dec_sub19_out_sel[1:0] - attribute \src "libresoc.v:26002.3-26020.6" - wire width 2 $1\dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:26173.3-26191.6" - wire $1\dec31_dec_sub19_rsrv[0:0] - attribute \src "libresoc.v:26249.3-26267.6" - wire $1\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "libresoc.v:26211.3-26229.6" - wire $1\dec31_dec_sub19_sgn[0:0] - attribute \src "libresoc.v:26135.3-26153.6" - wire $1\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "libresoc.v:25983.3-26001.6" - wire width 2 $1\dec31_dec_sub19_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub19_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub19_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub19_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub19_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub19_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub19_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub19_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub19_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" + attribute \src "libresoc.v:118634.3-118654.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:118655.3-118675.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:118634.3-118654.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:118655.3-118675.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:118634.3-118654.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:118655.3-118675.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire input 2 \CR_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub19_in2_sel - attribute \enum_base_type "In3Sel" + wire width 7 input 1 \CR_internal_op + attribute \src "libresoc.v:118545.7-118545.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \oe_ok + attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub19_in3_sel + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + wire width 2 input 3 \sel_in + attribute \src "libresoc.v:118545.7-118545.20" + process $proc$libresoc.v:118545$4695 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:118634.3-118654.6" + process $proc$libresoc.v:118634$4693 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:118635.5-118635.29" + switch \initial + attribute \src "libresoc.v:118635.9-118635.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + switch \CR_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \CR_OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "libresoc.v:118655.3-118675.6" + process $proc$libresoc.v:118655$4694 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:118656.5-118656.29" + switch \initial + attribute \src "libresoc.v:118656.9-118656.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + switch \CR_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "libresoc.v:118680.1-118812.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_oe" +attribute \generator "nMigen" +module \dec_oe$149 + attribute \src "libresoc.v:118681.7-118681.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:118770.3-118790.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:118791.3-118811.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:118770.3-118790.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:118791.3-118811.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:118770.3-118790.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:118791.3-118811.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire input 2 \BRANCH_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -37689,1118 +186469,1221 @@ module \dec31_dec_sub19 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub19_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub19_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub19_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub19_out_sel + wire width 7 input 1 \BRANCH_internal_op + attribute \src "libresoc.v:118681.7-118681.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub19_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub19_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub19_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub19_upd - attribute \src "libresoc.v:25688.7-25688.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:25688.7-25688.20" - process $proc$libresoc.v:25688$581 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + wire width 2 input 3 \sel_in + attribute \src "libresoc.v:118681.7-118681.20" + process $proc$libresoc.v:118681$4698 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:25945.3-25963.6" - process $proc$libresoc.v:25945$557 + attribute \src "libresoc.v:118770.3-118790.6" + process $proc$libresoc.v:118770$4696 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_function_unit[11:0] $1\dec31_dec_sub19_function_unit[11:0] - attribute \src "libresoc.v:25946.5-25946.29" + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:118771.5-118771.29" switch \initial - attribute \src "libresoc.v:25946.9-25946.17" + attribute \src "libresoc.v:118771.9-118771.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_function_unit[11:0] 12'000010000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + switch \BRANCH_internal_op attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_function_unit[11:0] 12'010000000000 + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_function_unit[11:0] 12'010000000000 - case - assign $1\dec31_dec_sub19_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub19_function_unit $0\dec31_dec_sub19_function_unit[11:0] - end - attribute \src "libresoc.v:25964.3-25982.6" - process $proc$libresoc.v:25964$558 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_ldst_len[3:0] $1\dec31_dec_sub19_ldst_len[3:0] - attribute \src "libresoc.v:25965.5-25965.29" - switch \initial - attribute \src "libresoc.v:25965.9-25965.17" - case 1'1 case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 assign { } { } - assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \BRANCH_OE + case + assign $2\oe[0:0] 1'0 + end end sync always - update \dec31_dec_sub19_ldst_len $0\dec31_dec_sub19_ldst_len[3:0] + update \oe $0\oe[0:0] end - attribute \src "libresoc.v:25983.3-26001.6" - process $proc$libresoc.v:25983$559 + attribute \src "libresoc.v:118791.3-118811.6" + process $proc$libresoc.v:118791$4697 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_upd[1:0] $1\dec31_dec_sub19_upd[1:0] - attribute \src "libresoc.v:25984.5-25984.29" + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:118792.5-118792.29" switch \initial - attribute \src "libresoc.v:25984.9-25984.17" + attribute \src "libresoc.v:118792.9-118792.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_upd[1:0] 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + switch \BRANCH_internal_op attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_upd[1:0] 2'00 + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub19_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub19_upd $0\dec31_dec_sub19_upd[1:0] - end - attribute \src "libresoc.v:26002.3-26020.6" - process $proc$libresoc.v:26002$560 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_rc_sel[1:0] $1\dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:26003.5-26003.29" - switch \initial - attribute \src "libresoc.v:26003.9-26003.17" - case 1'1 case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 assign { } { } - assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end end sync always - update \dec31_dec_sub19_rc_sel $0\dec31_dec_sub19_rc_sel[1:0] + update \oe_ok $0\oe_ok[0:0] end - attribute \src "libresoc.v:26021.3-26039.6" - process $proc$libresoc.v:26021$561 - assign { } { } +end +attribute \src "libresoc.v:118816.1-118950.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_oe" +attribute \generator "nMigen" +module \dec_oe$157 + attribute \src "libresoc.v:118817.7-118817.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:118908.3-118928.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:118929.3-118949.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:118908.3-118928.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:118929.3-118949.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:118908.3-118928.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:118929.3-118949.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire input 4 \LOGICAL_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 input 1 \LOGICAL_internal_op + attribute \src "libresoc.v:118817.7-118817.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:118817.7-118817.20" + process $proc$libresoc.v:118817$4701 assign { } { } - assign $0\dec31_dec_sub19_cry_in[1:0] $1\dec31_dec_sub19_cry_in[1:0] - attribute \src "libresoc.v:26022.5-26022.29" - switch \initial - attribute \src "libresoc.v:26022.9-26022.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 - end + assign $0\initial[0:0] 1'0 sync always - update \dec31_dec_sub19_cry_in $0\dec31_dec_sub19_cry_in[1:0] + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:26040.3-26058.6" - process $proc$libresoc.v:26040$562 + attribute \src "libresoc.v:118908.3-118928.6" + process $proc$libresoc.v:118908$4699 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_asmcode[7:0] $1\dec31_dec_sub19_asmcode[7:0] - attribute \src "libresoc.v:26041.5-26041.29" + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:118909.5-118909.29" switch \initial - attribute \src "libresoc.v:26041.9-26041.17" + attribute \src "libresoc.v:118909.9-118909.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_asmcode[7:0] 8'01101111 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + switch \LOGICAL_internal_op attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110001 + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_asmcode[7:0] 8'01111001 - case - assign $1\dec31_dec_sub19_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub19_asmcode $0\dec31_dec_sub19_asmcode[7:0] - end - attribute \src "libresoc.v:26059.3-26077.6" - process $proc$libresoc.v:26059$563 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_inv_a[0:0] $1\dec31_dec_sub19_inv_a[0:0] - attribute \src "libresoc.v:26060.5-26060.29" - switch \initial - attribute \src "libresoc.v:26060.9-26060.17" - case 1'1 case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 assign { } { } - assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \LOGICAL_OE + case + assign $2\oe[0:0] 1'0 + end end sync always - update \dec31_dec_sub19_inv_a $0\dec31_dec_sub19_inv_a[0:0] + update \oe $0\oe[0:0] end - attribute \src "libresoc.v:26078.3-26096.6" - process $proc$libresoc.v:26078$564 + attribute \src "libresoc.v:118929.3-118949.6" + process $proc$libresoc.v:118929$4700 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_inv_out[0:0] $1\dec31_dec_sub19_inv_out[0:0] - attribute \src "libresoc.v:26079.5-26079.29" + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:118930.5-118930.29" switch \initial - attribute \src "libresoc.v:26079.9-26079.17" + attribute \src "libresoc.v:118930.9-118930.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + switch \LOGICAL_internal_op attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub19_inv_out $0\dec31_dec_sub19_inv_out[0:0] - end - attribute \src "libresoc.v:26097.3-26115.6" - process $proc$libresoc.v:26097$565 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_cry_out[0:0] $1\dec31_dec_sub19_cry_out[0:0] - attribute \src "libresoc.v:26098.5-26098.29" - switch \initial - attribute \src "libresoc.v:26098.9-26098.17" - case 1'1 case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 assign { } { } - assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end end sync always - update \dec31_dec_sub19_cry_out $0\dec31_dec_sub19_cry_out[0:0] + update \oe_ok $0\oe_ok[0:0] end - attribute \src "libresoc.v:26116.3-26134.6" - process $proc$libresoc.v:26116$566 - assign { } { } +end +attribute \src "libresoc.v:118954.1-119086.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_oe" +attribute \generator "nMigen" +module \dec_oe$166 + attribute \src "libresoc.v:118955.7-118955.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:119044.3-119064.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:119065.3-119085.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:119044.3-119064.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:119065.3-119085.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:119044.3-119064.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:119065.3-119085.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire input 2 \SPR_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 input 1 \SPR_internal_op + attribute \src "libresoc.v:118955.7-118955.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + wire width 2 input 3 \sel_in + attribute \src "libresoc.v:118955.7-118955.20" + process $proc$libresoc.v:118955$4704 assign { } { } - assign $0\dec31_dec_sub19_br[0:0] $1\dec31_dec_sub19_br[0:0] - attribute \src "libresoc.v:26117.5-26117.29" - switch \initial - attribute \src "libresoc.v:26117.9-26117.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_br[0:0] 1'0 - case - assign $1\dec31_dec_sub19_br[0:0] 1'0 - end + assign $0\initial[0:0] 1'0 sync always - update \dec31_dec_sub19_br $0\dec31_dec_sub19_br[0:0] + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:26135.3-26153.6" - process $proc$libresoc.v:26135$567 + attribute \src "libresoc.v:119044.3-119064.6" + process $proc$libresoc.v:119044$4702 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_sgn_ext[0:0] $1\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "libresoc.v:26136.5-26136.29" + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:119045.5-119045.29" switch \initial - attribute \src "libresoc.v:26136.9-26136.17" + attribute \src "libresoc.v:119045.9-119045.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + switch \SPR_internal_op attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 case - assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \SPR_OE + case + assign $2\oe[0:0] 1'0 + end end sync always - update \dec31_dec_sub19_sgn_ext $0\dec31_dec_sub19_sgn_ext[0:0] + update \oe $0\oe[0:0] end - attribute \src "libresoc.v:26154.3-26172.6" - process $proc$libresoc.v:26154$568 + attribute \src "libresoc.v:119065.3-119085.6" + process $proc$libresoc.v:119065$4703 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_internal_op[6:0] $1\dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:26155.5-26155.29" + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:119066.5-119066.29" switch \initial - attribute \src "libresoc.v:26155.9-26155.17" + attribute \src "libresoc.v:119066.9-119066.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_internal_op[6:0] 7'1000111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + switch \SPR_internal_op attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101110 + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_internal_op[6:0] 7'0110001 case - assign $1\dec31_dec_sub19_internal_op[6:0] 7'0000000 + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end end sync always - update \dec31_dec_sub19_internal_op $0\dec31_dec_sub19_internal_op[6:0] + update \oe_ok $0\oe_ok[0:0] end - attribute \src "libresoc.v:26173.3-26191.6" - process $proc$libresoc.v:26173$569 - assign { } { } +end +attribute \src "libresoc.v:119090.1-119224.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_oe" +attribute \generator "nMigen" +module \dec_oe$173 + attribute \src "libresoc.v:119091.7-119091.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:119182.3-119202.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:119203.3-119223.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:119182.3-119202.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:119203.3-119223.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:119182.3-119202.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:119203.3-119223.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire input 4 \DIV_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 input 1 \DIV_internal_op + attribute \src "libresoc.v:119091.7-119091.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:119091.7-119091.20" + process $proc$libresoc.v:119091$4707 assign { } { } - assign $0\dec31_dec_sub19_rsrv[0:0] $1\dec31_dec_sub19_rsrv[0:0] - attribute \src "libresoc.v:26174.5-26174.29" - switch \initial - attribute \src "libresoc.v:26174.9-26174.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 - end + assign $0\initial[0:0] 1'0 sync always - update \dec31_dec_sub19_rsrv $0\dec31_dec_sub19_rsrv[0:0] + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:26192.3-26210.6" - process $proc$libresoc.v:26192$570 + attribute \src "libresoc.v:119182.3-119202.6" + process $proc$libresoc.v:119182$4705 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_is_32b[0:0] $1\dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:26193.5-26193.29" + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:119183.5-119183.29" switch \initial - attribute \src "libresoc.v:26193.9-26193.17" + attribute \src "libresoc.v:119183.9-119183.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + switch \DIV_internal_op attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 case - assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \DIV_OE + case + assign $2\oe[0:0] 1'0 + end end sync always - update \dec31_dec_sub19_is_32b $0\dec31_dec_sub19_is_32b[0:0] + update \oe $0\oe[0:0] end - attribute \src "libresoc.v:26211.3-26229.6" - process $proc$libresoc.v:26211$571 + attribute \src "libresoc.v:119203.3-119223.6" + process $proc$libresoc.v:119203$4706 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_sgn[0:0] $1\dec31_dec_sub19_sgn[0:0] - attribute \src "libresoc.v:26212.5-26212.29" + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:119204.5-119204.29" switch \initial - attribute \src "libresoc.v:26212.9-26212.17" + attribute \src "libresoc.v:119204.9-119204.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + switch \DIV_internal_op attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_sgn[0:0] 1'0 case - assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end end sync always - update \dec31_dec_sub19_sgn $0\dec31_dec_sub19_sgn[0:0] + update \oe_ok $0\oe_ok[0:0] end - attribute \src "libresoc.v:26230.3-26248.6" - process $proc$libresoc.v:26230$572 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_lk[0:0] $1\dec31_dec_sub19_lk[0:0] - attribute \src "libresoc.v:26231.5-26231.29" - switch \initial - attribute \src "libresoc.v:26231.9-26231.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub19_lk[0:0] 1'0 - end +end +attribute \src "libresoc.v:119228.1-119362.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_oe" +attribute \generator "nMigen" +module \dec_oe$182 + attribute \src "libresoc.v:119229.7-119229.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:119320.3-119340.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:119341.3-119361.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:119320.3-119340.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:119341.3-119361.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:119320.3-119340.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:119341.3-119361.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire input 4 \MUL_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 input 1 \MUL_internal_op + attribute \src "libresoc.v:119229.7-119229.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:119229.7-119229.20" + process $proc$libresoc.v:119229$4710 + assign { } { } + assign $0\initial[0:0] 1'0 sync always - update \dec31_dec_sub19_lk $0\dec31_dec_sub19_lk[0:0] + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:26249.3-26267.6" - process $proc$libresoc.v:26249$573 + attribute \src "libresoc.v:119320.3-119340.6" + process $proc$libresoc.v:119320$4708 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_sgl_pipe[0:0] $1\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "libresoc.v:26250.5-26250.29" + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:119321.5-119321.29" switch \initial - attribute \src "libresoc.v:26250.9-26250.17" + attribute \src "libresoc.v:119321.9-119321.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + switch \MUL_internal_op attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 case - assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \MUL_OE + case + assign $2\oe[0:0] 1'0 + end end sync always - update \dec31_dec_sub19_sgl_pipe $0\dec31_dec_sub19_sgl_pipe[0:0] + update \oe $0\oe[0:0] end - attribute \src "libresoc.v:26268.3-26286.6" - process $proc$libresoc.v:26268$574 + attribute \src "libresoc.v:119341.3-119361.6" + process $proc$libresoc.v:119341$4709 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_form[4:0] $1\dec31_dec_sub19_form[4:0] - attribute \src "libresoc.v:26269.5-26269.29" + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:119342.5-119342.29" switch \initial - attribute \src "libresoc.v:26269.9-26269.17" + attribute \src "libresoc.v:119342.9-119342.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_form[4:0] 5'01010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_form[4:0] 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + switch \MUL_internal_op attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_form[4:0] 5'01010 + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_form[4:0] 5'01010 case - assign $1\dec31_dec_sub19_form[4:0] 5'00000 + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end end sync always - update \dec31_dec_sub19_form $0\dec31_dec_sub19_form[4:0] + update \oe_ok $0\oe_ok[0:0] end - attribute \src "libresoc.v:26287.3-26305.6" - process $proc$libresoc.v:26287$575 - assign { } { } +end +attribute \src "libresoc.v:119366.1-119500.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_oe" +attribute \generator "nMigen" +module \dec_oe$190 + attribute \src "libresoc.v:119367.7-119367.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:119458.3-119478.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:119479.3-119499.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:119458.3-119478.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:119479.3-119499.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:119458.3-119478.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:119479.3-119499.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire input 4 \SHIFT_ROT_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 input 1 \SHIFT_ROT_internal_op + attribute \src "libresoc.v:119367.7-119367.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:119367.7-119367.20" + process $proc$libresoc.v:119367$4713 assign { } { } - assign $0\dec31_dec_sub19_in1_sel[2:0] $1\dec31_dec_sub19_in1_sel[2:0] - attribute \src "libresoc.v:26288.5-26288.29" - switch \initial - attribute \src "libresoc.v:26288.9-26288.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_in1_sel[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_in1_sel[2:0] 3'100 - case - assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 - end + assign $0\initial[0:0] 1'0 sync always - update \dec31_dec_sub19_in1_sel $0\dec31_dec_sub19_in1_sel[2:0] + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:26306.3-26324.6" - process $proc$libresoc.v:26306$576 + attribute \src "libresoc.v:119458.3-119478.6" + process $proc$libresoc.v:119458$4711 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_in2_sel[3:0] $1\dec31_dec_sub19_in2_sel[3:0] - attribute \src "libresoc.v:26307.5-26307.29" + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:119459.5-119459.29" switch \initial - attribute \src "libresoc.v:26307.9-26307.17" + attribute \src "libresoc.v:119459.9-119459.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + switch \SHIFT_ROT_internal_op attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 case - assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \SHIFT_ROT_OE + case + assign $2\oe[0:0] 1'0 + end end sync always - update \dec31_dec_sub19_in2_sel $0\dec31_dec_sub19_in2_sel[3:0] + update \oe $0\oe[0:0] end - attribute \src "libresoc.v:26325.3-26343.6" - process $proc$libresoc.v:26325$577 + attribute \src "libresoc.v:119479.3-119499.6" + process $proc$libresoc.v:119479$4712 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_in3_sel[1:0] $1\dec31_dec_sub19_in3_sel[1:0] - attribute \src "libresoc.v:26326.5-26326.29" + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:119480.5-119480.29" switch \initial - attribute \src "libresoc.v:26326.9-26326.17" + attribute \src "libresoc.v:119480.9-119480.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + switch \SHIFT_ROT_internal_op attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 case - assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end end sync always - update \dec31_dec_sub19_in3_sel $0\dec31_dec_sub19_in3_sel[1:0] + update \oe_ok $0\oe_ok[0:0] end - attribute \src "libresoc.v:26344.3-26362.6" - process $proc$libresoc.v:26344$578 - assign { } { } +end +attribute \src "libresoc.v:119504.1-119638.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_oe" +attribute \generator "nMigen" +module \dec_oe$198 + attribute \src "libresoc.v:119505.7-119505.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:119596.3-119616.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:119617.3-119637.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:119596.3-119616.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:119617.3-119637.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:119596.3-119616.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:119617.3-119637.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire input 4 \LDST_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 input 1 \LDST_internal_op + attribute \src "libresoc.v:119505.7-119505.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:119505.7-119505.20" + process $proc$libresoc.v:119505$4716 assign { } { } - assign $0\dec31_dec_sub19_out_sel[1:0] $1\dec31_dec_sub19_out_sel[1:0] - attribute \src "libresoc.v:26345.5-26345.29" - switch \initial - attribute \src "libresoc.v:26345.9-26345.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_out_sel[1:0] 2'11 - case - assign $1\dec31_dec_sub19_out_sel[1:0] 2'00 - end + assign $0\initial[0:0] 1'0 sync always - update \dec31_dec_sub19_out_sel $0\dec31_dec_sub19_out_sel[1:0] + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:26363.3-26381.6" - process $proc$libresoc.v:26363$579 + attribute \src "libresoc.v:119596.3-119616.6" + process $proc$libresoc.v:119596$4714 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_cr_in[2:0] $1\dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:26364.5-26364.29" + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:119597.5-119597.29" switch \initial - attribute \src "libresoc.v:26364.9-26364.17" + attribute \src "libresoc.v:119597.9-119597.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_cr_in[2:0] 3'110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + switch \LDST_internal_op attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 case - assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \LDST_OE + case + assign $2\oe[0:0] 1'0 + end end sync always - update \dec31_dec_sub19_cr_in $0\dec31_dec_sub19_cr_in[2:0] + update \oe $0\oe[0:0] end - attribute \src "libresoc.v:26382.3-26400.6" - process $proc$libresoc.v:26382$580 + attribute \src "libresoc.v:119617.3-119637.6" + process $proc$libresoc.v:119617$4715 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_cr_out[2:0] $1\dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:26383.5-26383.29" + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:119618.5-119618.29" switch \initial - attribute \src "libresoc.v:26383.9-26383.17" + attribute \src "libresoc.v:119618.9-119618.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + switch \LDST_internal_op attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 case - assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end end sync always - update \dec31_dec_sub19_cr_out $0\dec31_dec_sub19_cr_out[2:0] + update \oe_ok $0\oe_ok[0:0] end - connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:26406.1-27265.10" +attribute \src "libresoc.v:119642.1-119776.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub20" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_oe" attribute \generator "nMigen" -module \dec31_dec_sub20 - attribute \src "libresoc.v:26789.3-26813.6" - wire width 8 $0\dec31_dec_sub20_asmcode[7:0] - attribute \src "libresoc.v:26889.3-26913.6" - wire $0\dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:27214.3-27238.6" - wire width 3 $0\dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:27239.3-27263.6" - wire width 3 $0\dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:26764.3-26788.6" - wire width 2 $0\dec31_dec_sub20_cry_in[1:0] - attribute \src "libresoc.v:26864.3-26888.6" - wire $0\dec31_dec_sub20_cry_out[0:0] - attribute \src "libresoc.v:27089.3-27113.6" - wire width 5 $0\dec31_dec_sub20_form[4:0] - attribute \src "libresoc.v:26664.3-26688.6" - wire width 12 $0\dec31_dec_sub20_function_unit[11:0] - attribute \src "libresoc.v:27114.3-27138.6" - wire width 3 $0\dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:27139.3-27163.6" - wire width 4 $0\dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:27164.3-27188.6" - wire width 2 $0\dec31_dec_sub20_in3_sel[1:0] - attribute \src "libresoc.v:26939.3-26963.6" - wire width 7 $0\dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:26814.3-26838.6" - wire $0\dec31_dec_sub20_inv_a[0:0] - attribute \src "libresoc.v:26839.3-26863.6" - wire $0\dec31_dec_sub20_inv_out[0:0] - attribute \src "libresoc.v:26989.3-27013.6" - wire $0\dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:26689.3-26713.6" - wire width 4 $0\dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:27039.3-27063.6" - wire $0\dec31_dec_sub20_lk[0:0] - attribute \src "libresoc.v:27189.3-27213.6" - wire width 2 $0\dec31_dec_sub20_out_sel[1:0] - attribute \src "libresoc.v:26739.3-26763.6" - wire width 2 $0\dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:26964.3-26988.6" - wire $0\dec31_dec_sub20_rsrv[0:0] - attribute \src "libresoc.v:27064.3-27088.6" - wire $0\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "libresoc.v:27014.3-27038.6" - wire $0\dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:26914.3-26938.6" - wire $0\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:26714.3-26738.6" - wire width 2 $0\dec31_dec_sub20_upd[1:0] - attribute \src "libresoc.v:26407.7-26407.20" +module \dec_oe$207 + attribute \src "libresoc.v:119643.7-119643.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26789.3-26813.6" - wire width 8 $1\dec31_dec_sub20_asmcode[7:0] - attribute \src "libresoc.v:26889.3-26913.6" - wire $1\dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:27214.3-27238.6" - wire width 3 $1\dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:27239.3-27263.6" - wire width 3 $1\dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:26764.3-26788.6" - wire width 2 $1\dec31_dec_sub20_cry_in[1:0] - attribute \src "libresoc.v:26864.3-26888.6" - wire $1\dec31_dec_sub20_cry_out[0:0] - attribute \src "libresoc.v:27089.3-27113.6" - wire width 5 $1\dec31_dec_sub20_form[4:0] - attribute \src "libresoc.v:26664.3-26688.6" - wire width 12 $1\dec31_dec_sub20_function_unit[11:0] - attribute \src "libresoc.v:27114.3-27138.6" - wire width 3 $1\dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:27139.3-27163.6" - wire width 4 $1\dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:27164.3-27188.6" - wire width 2 $1\dec31_dec_sub20_in3_sel[1:0] - attribute \src "libresoc.v:26939.3-26963.6" - wire width 7 $1\dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:26814.3-26838.6" - wire $1\dec31_dec_sub20_inv_a[0:0] - attribute \src "libresoc.v:26839.3-26863.6" - wire $1\dec31_dec_sub20_inv_out[0:0] - attribute \src "libresoc.v:26989.3-27013.6" - wire $1\dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:26689.3-26713.6" - wire width 4 $1\dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:27039.3-27063.6" - wire $1\dec31_dec_sub20_lk[0:0] - attribute \src "libresoc.v:27189.3-27213.6" - wire width 2 $1\dec31_dec_sub20_out_sel[1:0] - attribute \src "libresoc.v:26739.3-26763.6" - wire width 2 $1\dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:26964.3-26988.6" - wire $1\dec31_dec_sub20_rsrv[0:0] - attribute \src "libresoc.v:27064.3-27088.6" - wire $1\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "libresoc.v:27014.3-27038.6" - wire $1\dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:26914.3-26938.6" - wire $1\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:26714.3-26738.6" - wire width 2 $1\dec31_dec_sub20_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub20_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub20_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub20_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub20_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub20_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub20_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub20_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub20_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub20_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub20_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub20_in3_sel + attribute \src "libresoc.v:119734.3-119754.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:119755.3-119775.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:119734.3-119754.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:119755.3-119775.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:119734.3-119754.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:119755.3-119775.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire input 4 \OE + attribute \src "libresoc.v:119643.7-119643.15" + wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -38876,1264 +187759,1767 @@ module \dec31_dec_sub20 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub20_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub20_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub20_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub20_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub20_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub20_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub20_out_sel + wire width 7 input 1 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub20_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub20_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub20_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub20_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub20_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub20_upd - attribute \src "libresoc.v:26407.7-26407.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:26407.7-26407.20" - process $proc$libresoc.v:26407$606 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:119643.7-119643.20" + process $proc$libresoc.v:119643$4719 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26664.3-26688.6" - process $proc$libresoc.v:26664$582 + attribute \src "libresoc.v:119734.3-119754.6" + process $proc$libresoc.v:119734$4717 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_function_unit[11:0] $1\dec31_dec_sub20_function_unit[11:0] - attribute \src "libresoc.v:26665.5-26665.29" + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:119735.5-119735.29" switch \initial - attribute \src "libresoc.v:26665.9-26665.17" + attribute \src "libresoc.v:119735.9-119735.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + switch \internal_op attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 case - assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000000 + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \OE + case + assign $2\oe[0:0] 1'0 + end end sync always - update \dec31_dec_sub20_function_unit $0\dec31_dec_sub20_function_unit[11:0] + update \oe $0\oe[0:0] end - attribute \src "libresoc.v:26689.3-26713.6" - process $proc$libresoc.v:26689$583 + attribute \src "libresoc.v:119755.3-119775.6" + process $proc$libresoc.v:119755$4718 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_ldst_len[3:0] $1\dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:26690.5-26690.29" + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:119756.5-119756.29" switch \initial - attribute \src "libresoc.v:26690.9-26690.17" + attribute \src "libresoc.v:119756.9-119756.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + switch \internal_op attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0100 + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 case - assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0000 + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end end sync always - update \dec31_dec_sub20_ldst_len $0\dec31_dec_sub20_ldst_len[3:0] + update \oe_ok $0\oe_ok[0:0] end - attribute \src "libresoc.v:26714.3-26738.6" - process $proc$libresoc.v:26714$584 - assign { } { } +end +attribute \src "libresoc.v:119780.1-119834.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_rc" +attribute \generator "nMigen" +module \dec_rc + attribute \src "libresoc.v:119781.7-119781.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:119796.3-119814.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:119815.3-119833.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:119796.3-119814.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:119815.3-119833.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire input 3 \ALU_Rc + attribute \src "libresoc.v:119781.7-119781.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:119781.7-119781.20" + process $proc$libresoc.v:119781$4722 assign { } { } - assign $0\dec31_dec_sub20_upd[1:0] $1\dec31_dec_sub20_upd[1:0] - attribute \src "libresoc.v:26715.5-26715.29" - switch \initial - attribute \src "libresoc.v:26715.9-26715.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub20_upd[1:0] 2'00 - end + assign $0\initial[0:0] 1'0 sync always - update \dec31_dec_sub20_upd $0\dec31_dec_sub20_upd[1:0] + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:26739.3-26763.6" - process $proc$libresoc.v:26739$585 + attribute \src "libresoc.v:119796.3-119814.6" + process $proc$libresoc.v:119796$4720 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_rc_sel[1:0] $1\dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:26740.5-26740.29" + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:119797.5-119797.29" switch \initial - attribute \src "libresoc.v:26740.9-26740.17" + attribute \src "libresoc.v:119797.9-119797.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 2'10 assign { } { } - assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + assign $1\rc[0:0] \ALU_Rc attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 2'01 assign { } { } - assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + assign $1\rc[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 2'00 assign { } { } - assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + assign $1\rc[0:0] 1'0 case - assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + assign $1\rc[0:0] 1'0 end sync always - update \dec31_dec_sub20_rc_sel $0\dec31_dec_sub20_rc_sel[1:0] + update \rc $0\rc[0:0] end - attribute \src "libresoc.v:26764.3-26788.6" - process $proc$libresoc.v:26764$586 + attribute \src "libresoc.v:119815.3-119833.6" + process $proc$libresoc.v:119815$4721 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_cry_in[1:0] $1\dec31_dec_sub20_cry_in[1:0] - attribute \src "libresoc.v:26765.5-26765.29" + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:119816.5-119816.29" switch \initial - attribute \src "libresoc.v:26765.9-26765.17" + attribute \src "libresoc.v:119816.9-119816.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 2'10 assign { } { } - assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 2'01 assign { } { } - assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 2'00 assign { } { } - assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + assign $1\rc_ok[0:0] 1'1 case - assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + assign $1\rc_ok[0:0] 1'0 end sync always - update \dec31_dec_sub20_cry_in $0\dec31_dec_sub20_cry_in[1:0] + update \rc_ok $0\rc_ok[0:0] end - attribute \src "libresoc.v:26789.3-26813.6" - process $proc$libresoc.v:26789$587 - assign { } { } +end +attribute \src "libresoc.v:119838.1-119891.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_rc" +attribute \generator "nMigen" +module \dec_rc$141 + attribute \src "libresoc.v:119839.7-119839.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:119853.3-119871.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:119872.3-119890.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:119853.3-119871.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:119872.3-119890.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire input 2 \CR_Rc + attribute \src "libresoc.v:119839.7-119839.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + wire width 2 input 3 \sel_in + attribute \src "libresoc.v:119839.7-119839.20" + process $proc$libresoc.v:119839$4725 assign { } { } - assign $0\dec31_dec_sub20_asmcode[7:0] $1\dec31_dec_sub20_asmcode[7:0] - attribute \src "libresoc.v:26790.5-26790.29" - switch \initial - attribute \src "libresoc.v:26790.9-26790.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_asmcode[7:0] 8'01001101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_asmcode[7:0] 8'01010011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_asmcode[7:0] 8'01010100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_asmcode[7:0] 8'01011001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_asmcode[7:0] 8'01100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_asmcode[7:0] 8'10101101 - case - assign $1\dec31_dec_sub20_asmcode[7:0] 8'00000000 - end + assign $0\initial[0:0] 1'0 sync always - update \dec31_dec_sub20_asmcode $0\dec31_dec_sub20_asmcode[7:0] + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:26814.3-26838.6" - process $proc$libresoc.v:26814$588 + attribute \src "libresoc.v:119853.3-119871.6" + process $proc$libresoc.v:119853$4723 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_inv_a[0:0] $1\dec31_dec_sub20_inv_a[0:0] - attribute \src "libresoc.v:26815.5-26815.29" + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:119854.5-119854.29" switch \initial - attribute \src "libresoc.v:26815.9-26815.17" + attribute \src "libresoc.v:119854.9-119854.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 2'10 assign { } { } - assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + assign $1\rc[0:0] \CR_Rc attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 2'01 assign { } { } - assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + assign $1\rc[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 2'00 assign { } { } - assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + assign $1\rc[0:0] 1'0 case - assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + assign $1\rc[0:0] 1'0 end sync always - update \dec31_dec_sub20_inv_a $0\dec31_dec_sub20_inv_a[0:0] + update \rc $0\rc[0:0] end - attribute \src "libresoc.v:26839.3-26863.6" - process $proc$libresoc.v:26839$589 + attribute \src "libresoc.v:119872.3-119890.6" + process $proc$libresoc.v:119872$4724 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_inv_out[0:0] $1\dec31_dec_sub20_inv_out[0:0] - attribute \src "libresoc.v:26840.5-26840.29" + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:119873.5-119873.29" switch \initial - attribute \src "libresoc.v:26840.9-26840.17" + attribute \src "libresoc.v:119873.9-119873.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 2'10 assign { } { } - assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 2'01 assign { } { } - assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 2'00 assign { } { } - assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + assign $1\rc_ok[0:0] 1'1 case - assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + assign $1\rc_ok[0:0] 1'0 end sync always - update \dec31_dec_sub20_inv_out $0\dec31_dec_sub20_inv_out[0:0] + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:119895.1-119948.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_rc" +attribute \generator "nMigen" +module \dec_rc$148 + attribute \src "libresoc.v:119896.7-119896.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:119910.3-119928.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:119929.3-119947.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:119910.3-119928.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:119929.3-119947.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire input 2 \BRANCH_Rc + attribute \src "libresoc.v:119896.7-119896.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + wire width 2 input 3 \sel_in + attribute \src "libresoc.v:119896.7-119896.20" + process $proc$libresoc.v:119896$4728 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:26864.3-26888.6" - process $proc$libresoc.v:26864$590 + attribute \src "libresoc.v:119910.3-119928.6" + process $proc$libresoc.v:119910$4726 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_cry_out[0:0] $1\dec31_dec_sub20_cry_out[0:0] - attribute \src "libresoc.v:26865.5-26865.29" + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:119911.5-119911.29" switch \initial - attribute \src "libresoc.v:26865.9-26865.17" + attribute \src "libresoc.v:119911.9-119911.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 2'10 assign { } { } - assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + assign $1\rc[0:0] \BRANCH_Rc attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 2'01 assign { } { } - assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + assign $1\rc[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 2'00 assign { } { } - assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + assign $1\rc[0:0] 1'0 case - assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + assign $1\rc[0:0] 1'0 end sync always - update \dec31_dec_sub20_cry_out $0\dec31_dec_sub20_cry_out[0:0] + update \rc $0\rc[0:0] end - attribute \src "libresoc.v:26889.3-26913.6" - process $proc$libresoc.v:26889$591 + attribute \src "libresoc.v:119929.3-119947.6" + process $proc$libresoc.v:119929$4727 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_br[0:0] $1\dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:26890.5-26890.29" + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:119930.5-119930.29" switch \initial - attribute \src "libresoc.v:26890.9-26890.17" + attribute \src "libresoc.v:119930.9-119930.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_br[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 2'10 assign { } { } - assign $1\dec31_dec_sub20_br[0:0] 1'0 + assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 2'01 assign { } { } - assign $1\dec31_dec_sub20_br[0:0] 1'0 + assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 2'00 assign { } { } - assign $1\dec31_dec_sub20_br[0:0] 1'1 + assign $1\rc_ok[0:0] 1'1 case - assign $1\dec31_dec_sub20_br[0:0] 1'0 + assign $1\rc_ok[0:0] 1'0 end sync always - update \dec31_dec_sub20_br $0\dec31_dec_sub20_br[0:0] + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:119952.1-120006.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_rc" +attribute \generator "nMigen" +module \dec_rc$156 + attribute \src "libresoc.v:119953.7-119953.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:119968.3-119986.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:119987.3-120005.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:119968.3-119986.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:119987.3-120005.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire input 3 \LOGICAL_Rc + attribute \src "libresoc.v:119953.7-119953.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:119953.7-119953.20" + process $proc$libresoc.v:119953$4731 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:26914.3-26938.6" - process $proc$libresoc.v:26914$592 + attribute \src "libresoc.v:119968.3-119986.6" + process $proc$libresoc.v:119968$4729 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_sgn_ext[0:0] $1\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:26915.5-26915.29" + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:119969.5-119969.29" switch \initial - attribute \src "libresoc.v:26915.9-26915.17" + attribute \src "libresoc.v:119969.9-119969.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 2'10 assign { } { } - assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + assign $1\rc[0:0] \LOGICAL_Rc attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 2'01 assign { } { } - assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + assign $1\rc[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 2'00 assign { } { } - assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + assign $1\rc[0:0] 1'0 case - assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + assign $1\rc[0:0] 1'0 end sync always - update \dec31_dec_sub20_sgn_ext $0\dec31_dec_sub20_sgn_ext[0:0] + update \rc $0\rc[0:0] end - attribute \src "libresoc.v:26939.3-26963.6" - process $proc$libresoc.v:26939$593 + attribute \src "libresoc.v:119987.3-120005.6" + process $proc$libresoc.v:119987$4730 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_internal_op[6:0] $1\dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:26940.5-26940.29" + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:119988.5-119988.29" switch \initial - attribute \src "libresoc.v:26940.9-26940.17" + attribute \src "libresoc.v:119988.9-119988.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 2'10 assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 2'01 assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 2'00 assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100110 + assign $1\rc_ok[0:0] 1'1 case - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0000000 + assign $1\rc_ok[0:0] 1'0 end sync always - update \dec31_dec_sub20_internal_op $0\dec31_dec_sub20_internal_op[6:0] + update \rc_ok $0\rc_ok[0:0] end - attribute \src "libresoc.v:26964.3-26988.6" - process $proc$libresoc.v:26964$594 +end +attribute \src "libresoc.v:120010.1-120063.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_rc" +attribute \generator "nMigen" +module \dec_rc$165 + attribute \src "libresoc.v:120011.7-120011.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:120025.3-120043.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:120044.3-120062.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:120025.3-120043.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:120044.3-120062.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire input 2 \SPR_Rc + attribute \src "libresoc.v:120011.7-120011.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + wire width 2 input 3 \sel_in + attribute \src "libresoc.v:120011.7-120011.20" + process $proc$libresoc.v:120011$4734 assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:120025.3-120043.6" + process $proc$libresoc.v:120025$4732 assign { } { } - assign $0\dec31_dec_sub20_rsrv[0:0] $1\dec31_dec_sub20_rsrv[0:0] - attribute \src "libresoc.v:26965.5-26965.29" + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:120026.5-120026.29" switch \initial - attribute \src "libresoc.v:26965.9-26965.17" + attribute \src "libresoc.v:120026.9-120026.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 2'10 assign { } { } - assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + assign $1\rc[0:0] \SPR_Rc attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 2'01 assign { } { } - assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + assign $1\rc[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 2'00 assign { } { } - assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 + assign $1\rc[0:0] 1'0 case - assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 + assign $1\rc[0:0] 1'0 end sync always - update \dec31_dec_sub20_rsrv $0\dec31_dec_sub20_rsrv[0:0] + update \rc $0\rc[0:0] end - attribute \src "libresoc.v:26989.3-27013.6" - process $proc$libresoc.v:26989$595 + attribute \src "libresoc.v:120044.3-120062.6" + process $proc$libresoc.v:120044$4733 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_is_32b[0:0] $1\dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:26990.5-26990.29" + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:120045.5-120045.29" switch \initial - attribute \src "libresoc.v:26990.9-26990.17" + attribute \src "libresoc.v:120045.9-120045.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 2'10 assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 2'01 assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 2'00 assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + assign $1\rc_ok[0:0] 1'1 case - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + assign $1\rc_ok[0:0] 1'0 end sync always - update \dec31_dec_sub20_is_32b $0\dec31_dec_sub20_is_32b[0:0] + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:120067.1-120121.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_rc" +attribute \generator "nMigen" +module \dec_rc$172 + attribute \src "libresoc.v:120068.7-120068.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:120083.3-120101.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:120102.3-120120.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:120083.3-120101.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:120102.3-120120.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire input 3 \DIV_Rc + attribute \src "libresoc.v:120068.7-120068.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:120068.7-120068.20" + process $proc$libresoc.v:120068$4737 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:27014.3-27038.6" - process $proc$libresoc.v:27014$596 + attribute \src "libresoc.v:120083.3-120101.6" + process $proc$libresoc.v:120083$4735 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_sgn[0:0] $1\dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:27015.5-27015.29" + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:120084.5-120084.29" switch \initial - attribute \src "libresoc.v:27015.9-27015.17" + attribute \src "libresoc.v:120084.9-120084.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 2'10 assign { } { } - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + assign $1\rc[0:0] \DIV_Rc attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 2'01 assign { } { } - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + assign $1\rc[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 2'00 assign { } { } - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + assign $1\rc[0:0] 1'0 case - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + assign $1\rc[0:0] 1'0 end sync always - update \dec31_dec_sub20_sgn $0\dec31_dec_sub20_sgn[0:0] + update \rc $0\rc[0:0] end - attribute \src "libresoc.v:27039.3-27063.6" - process $proc$libresoc.v:27039$597 + attribute \src "libresoc.v:120102.3-120120.6" + process $proc$libresoc.v:120102$4736 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_lk[0:0] $1\dec31_dec_sub20_lk[0:0] - attribute \src "libresoc.v:27040.5-27040.29" + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:120103.5-120103.29" switch \initial - attribute \src "libresoc.v:27040.9-27040.17" + attribute \src "libresoc.v:120103.9-120103.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 2'10 assign { } { } - assign $1\dec31_dec_sub20_lk[0:0] 1'0 + assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 2'01 assign { } { } - assign $1\dec31_dec_sub20_lk[0:0] 1'0 + assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 2'00 assign { } { } - assign $1\dec31_dec_sub20_lk[0:0] 1'0 + assign $1\rc_ok[0:0] 1'1 case - assign $1\dec31_dec_sub20_lk[0:0] 1'0 + assign $1\rc_ok[0:0] 1'0 end sync always - update \dec31_dec_sub20_lk $0\dec31_dec_sub20_lk[0:0] + update \rc_ok $0\rc_ok[0:0] end - attribute \src "libresoc.v:27064.3-27088.6" - process $proc$libresoc.v:27064$598 +end +attribute \src "libresoc.v:120125.1-120179.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_rc" +attribute \generator "nMigen" +module \dec_rc$181 + attribute \src "libresoc.v:120126.7-120126.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:120141.3-120159.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:120160.3-120178.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:120141.3-120159.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:120160.3-120178.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire input 3 \MUL_Rc + attribute \src "libresoc.v:120126.7-120126.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:120126.7-120126.20" + process $proc$libresoc.v:120126$4740 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:120141.3-120159.6" + process $proc$libresoc.v:120141$4738 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_sgl_pipe[0:0] $1\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "libresoc.v:27065.5-27065.29" + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:120142.5-120142.29" switch \initial - attribute \src "libresoc.v:27065.9-27065.17" + attribute \src "libresoc.v:120142.9-120142.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 2'10 assign { } { } - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + assign $1\rc[0:0] \MUL_Rc attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 2'01 assign { } { } - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + assign $1\rc[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 2'00 assign { } { } - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + assign $1\rc[0:0] 1'0 case - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'0 + assign $1\rc[0:0] 1'0 end sync always - update \dec31_dec_sub20_sgl_pipe $0\dec31_dec_sub20_sgl_pipe[0:0] + update \rc $0\rc[0:0] end - attribute \src "libresoc.v:27089.3-27113.6" - process $proc$libresoc.v:27089$599 + attribute \src "libresoc.v:120160.3-120178.6" + process $proc$libresoc.v:120160$4739 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_form[4:0] $1\dec31_dec_sub20_form[4:0] - attribute \src "libresoc.v:27090.5-27090.29" + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:120161.5-120161.29" switch \initial - attribute \src "libresoc.v:27090.9-27090.17" + attribute \src "libresoc.v:120161.9-120161.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 2'10 assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 + assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 2'01 assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 + assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 2'00 assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 + assign $1\rc_ok[0:0] 1'1 case - assign $1\dec31_dec_sub20_form[4:0] 5'00000 + assign $1\rc_ok[0:0] 1'0 end sync always - update \dec31_dec_sub20_form $0\dec31_dec_sub20_form[4:0] + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:120183.1-120237.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_rc" +attribute \generator "nMigen" +module \dec_rc$189 + attribute \src "libresoc.v:120184.7-120184.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:120199.3-120217.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:120218.3-120236.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:120199.3-120217.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:120218.3-120236.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire input 3 \SHIFT_ROT_Rc + attribute \src "libresoc.v:120184.7-120184.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:120184.7-120184.20" + process $proc$libresoc.v:120184$4743 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:27114.3-27138.6" - process $proc$libresoc.v:27114$600 + attribute \src "libresoc.v:120199.3-120217.6" + process $proc$libresoc.v:120199$4741 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_in1_sel[2:0] $1\dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:27115.5-27115.29" + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:120200.5-120200.29" switch \initial - attribute \src "libresoc.v:27115.9-27115.17" + attribute \src "libresoc.v:120200.9-120200.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 2'10 assign { } { } - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + assign $1\rc[0:0] \SHIFT_ROT_Rc attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 2'01 assign { } { } - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + assign $1\rc[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 2'00 assign { } { } - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + assign $1\rc[0:0] 1'0 case - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'000 + assign $1\rc[0:0] 1'0 end sync always - update \dec31_dec_sub20_in1_sel $0\dec31_dec_sub20_in1_sel[2:0] + update \rc $0\rc[0:0] end - attribute \src "libresoc.v:27139.3-27163.6" - process $proc$libresoc.v:27139$601 + attribute \src "libresoc.v:120218.3-120236.6" + process $proc$libresoc.v:120218$4742 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_in2_sel[3:0] $1\dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:27140.5-27140.29" + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:120219.5-120219.29" switch \initial - attribute \src "libresoc.v:27140.9-27140.17" + attribute \src "libresoc.v:120219.9-120219.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 2'10 assign { } { } - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 2'01 assign { } { } - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 2'00 assign { } { } - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + assign $1\rc_ok[0:0] 1'1 case - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0000 + assign $1\rc_ok[0:0] 1'0 end sync always - update \dec31_dec_sub20_in2_sel $0\dec31_dec_sub20_in2_sel[3:0] + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:120241.1-120295.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_rc" +attribute \generator "nMigen" +module \dec_rc$197 + attribute \src "libresoc.v:120242.7-120242.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:120257.3-120275.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:120276.3-120294.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:120257.3-120275.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:120276.3-120294.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire input 3 \LDST_Rc + attribute \src "libresoc.v:120242.7-120242.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:120242.7-120242.20" + process $proc$libresoc.v:120242$4746 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:27164.3-27188.6" - process $proc$libresoc.v:27164$602 + attribute \src "libresoc.v:120257.3-120275.6" + process $proc$libresoc.v:120257$4744 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_in3_sel[1:0] $1\dec31_dec_sub20_in3_sel[1:0] - attribute \src "libresoc.v:27165.5-27165.29" + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:120258.5-120258.29" switch \initial - attribute \src "libresoc.v:27165.9-27165.17" + attribute \src "libresoc.v:120258.9-120258.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 2'10 assign { } { } - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + assign $1\rc[0:0] \LDST_Rc attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 2'01 assign { } { } - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + assign $1\rc[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 2'00 assign { } { } - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'01 + assign $1\rc[0:0] 1'0 case - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + assign $1\rc[0:0] 1'0 end sync always - update \dec31_dec_sub20_in3_sel $0\dec31_dec_sub20_in3_sel[1:0] + update \rc $0\rc[0:0] end - attribute \src "libresoc.v:27189.3-27213.6" - process $proc$libresoc.v:27189$603 + attribute \src "libresoc.v:120276.3-120294.6" + process $proc$libresoc.v:120276$4745 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_out_sel[1:0] $1\dec31_dec_sub20_out_sel[1:0] - attribute \src "libresoc.v:27190.5-27190.29" + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:120277.5-120277.29" switch \initial - attribute \src "libresoc.v:27190.9-27190.17" + attribute \src "libresoc.v:120277.9-120277.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 2'10 assign { } { } - assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 2'01 assign { } { } - assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 2'00 assign { } { } - assign $1\dec31_dec_sub20_out_sel[1:0] 2'00 + assign $1\rc_ok[0:0] 1'1 case - assign $1\dec31_dec_sub20_out_sel[1:0] 2'00 + assign $1\rc_ok[0:0] 1'0 end sync always - update \dec31_dec_sub20_out_sel $0\dec31_dec_sub20_out_sel[1:0] + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:120299.1-120353.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_rc" +attribute \generator "nMigen" +module \dec_rc$206 + attribute \src "libresoc.v:120300.7-120300.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:120315.3-120333.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:120334.3-120352.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:120315.3-120333.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:120334.3-120352.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire input 3 \Rc + attribute \src "libresoc.v:120300.7-120300.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:120300.7-120300.20" + process $proc$libresoc.v:120300$4749 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:27214.3-27238.6" - process $proc$libresoc.v:27214$604 + attribute \src "libresoc.v:120315.3-120333.6" + process $proc$libresoc.v:120315$4747 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_cr_in[2:0] $1\dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:27215.5-27215.29" + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:120316.5-120316.29" switch \initial - attribute \src "libresoc.v:27215.9-27215.17" + attribute \src "libresoc.v:120316.9-120316.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 2'10 assign { } { } - assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + assign $1\rc[0:0] \Rc attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 2'01 assign { } { } - assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + assign $1\rc[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 2'00 assign { } { } - assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + assign $1\rc[0:0] 1'0 case - assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + assign $1\rc[0:0] 1'0 end sync always - update \dec31_dec_sub20_cr_in $0\dec31_dec_sub20_cr_in[2:0] + update \rc $0\rc[0:0] end - attribute \src "libresoc.v:27239.3-27263.6" - process $proc$libresoc.v:27239$605 + attribute \src "libresoc.v:120334.3-120352.6" + process $proc$libresoc.v:120334$4748 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_cr_out[2:0] $1\dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:27240.5-27240.29" + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:120335.5-120335.29" switch \initial - attribute \src "libresoc.v:27240.9-27240.17" + attribute \src "libresoc.v:120335.9-120335.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 5'00011 + case 2'10 assign { } { } - assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 2'01 assign { } { } - assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 2'00 assign { } { } - assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + assign $1\rc_ok[0:0] 1'1 case - assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + assign $1\rc_ok[0:0] 1'0 end sync always - update \dec31_dec_sub20_cr_out $0\dec31_dec_sub20_cr_out[2:0] + update \rc_ok $0\rc_ok[0:0] end - connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:27269.1-28686.10" +attribute \src "libresoc.v:120357.1-121595.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub21" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0" attribute \generator "nMigen" -module \dec31_dec_sub21 - attribute \src "libresoc.v:28311.3-28341.6" - wire width 8 $0\dec31_dec_sub21_asmcode[7:0] - attribute \src "libresoc.v:27919.3-27967.6" - wire $0\dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:28587.3-28635.6" - wire width 3 $0\dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:28636.3-28684.6" - wire width 3 $0\dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:27723.3-27771.6" - wire width 2 $0\dec31_dec_sub21_cry_in[1:0] - attribute \src "libresoc.v:27870.3-27918.6" - wire $0\dec31_dec_sub21_cry_out[0:0] - attribute \src "libresoc.v:28342.3-28390.6" - wire width 5 $0\dec31_dec_sub21_form[4:0] - attribute \src "libresoc.v:27527.3-27575.6" - wire width 12 $0\dec31_dec_sub21_function_unit[11:0] - attribute \src "libresoc.v:28391.3-28439.6" - wire width 3 $0\dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:28440.3-28488.6" - wire width 4 $0\dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:28489.3-28537.6" - wire width 2 $0\dec31_dec_sub21_in3_sel[1:0] - attribute \src "libresoc.v:28066.3-28114.6" - wire width 7 $0\dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:27772.3-27820.6" - wire $0\dec31_dec_sub21_inv_a[0:0] - attribute \src "libresoc.v:27821.3-27869.6" - wire $0\dec31_dec_sub21_inv_out[0:0] - attribute \src "libresoc.v:28115.3-28163.6" - wire $0\dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:27576.3-27624.6" - wire width 4 $0\dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:28213.3-28261.6" - wire $0\dec31_dec_sub21_lk[0:0] - attribute \src "libresoc.v:28538.3-28586.6" - wire width 2 $0\dec31_dec_sub21_out_sel[1:0] - attribute \src "libresoc.v:27674.3-27722.6" - wire width 2 $0\dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:28017.3-28065.6" - wire $0\dec31_dec_sub21_rsrv[0:0] - attribute \src "libresoc.v:28262.3-28310.6" - wire $0\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "libresoc.v:28164.3-28212.6" - wire $0\dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:27968.3-28016.6" - wire $0\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:27625.3-27673.6" - wire width 2 $0\dec31_dec_sub21_upd[1:0] - attribute \src "libresoc.v:27270.7-27270.20" +module \div0 + attribute \src "libresoc.v:121152.3-121153.25" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:121339.3-121377.6" + wire width 4 $0\alu_div0_logical_op__data_len$next[3:0]$4889 + attribute \src "libresoc.v:121124.3-121125.75" + wire width 4 $0\alu_div0_logical_op__data_len[3:0] + attribute \src "libresoc.v:121339.3-121377.6" + wire width 12 $0\alu_div0_logical_op__fn_unit$next[11:0]$4890 + attribute \src "libresoc.v:121094.3-121095.73" + wire width 12 $0\alu_div0_logical_op__fn_unit[11:0] + attribute \src "libresoc.v:121339.3-121377.6" + wire width 64 $0\alu_div0_logical_op__imm_data__data$next[63:0]$4891 + attribute \src "libresoc.v:121096.3-121097.87" + wire width 64 $0\alu_div0_logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:121339.3-121377.6" + wire $0\alu_div0_logical_op__imm_data__ok$next[0:0]$4892 + attribute \src "libresoc.v:121098.3-121099.83" + wire $0\alu_div0_logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:121339.3-121377.6" + wire width 2 $0\alu_div0_logical_op__input_carry$next[1:0]$4893 + attribute \src "libresoc.v:121112.3-121113.81" + wire width 2 $0\alu_div0_logical_op__input_carry[1:0] + attribute \src "libresoc.v:121339.3-121377.6" + wire width 32 $0\alu_div0_logical_op__insn$next[31:0]$4894 + attribute \src "libresoc.v:121126.3-121127.67" + wire width 32 $0\alu_div0_logical_op__insn[31:0] + attribute \src "libresoc.v:121339.3-121377.6" + wire width 7 $0\alu_div0_logical_op__insn_type$next[6:0]$4895 + attribute \src "libresoc.v:121092.3-121093.77" + wire width 7 $0\alu_div0_logical_op__insn_type[6:0] + attribute \src "libresoc.v:121339.3-121377.6" + wire $0\alu_div0_logical_op__invert_in$next[0:0]$4896 + attribute \src "libresoc.v:121108.3-121109.77" + wire $0\alu_div0_logical_op__invert_in[0:0] + attribute \src "libresoc.v:121339.3-121377.6" + wire $0\alu_div0_logical_op__invert_out$next[0:0]$4897 + attribute \src "libresoc.v:121114.3-121115.79" + wire $0\alu_div0_logical_op__invert_out[0:0] + attribute \src "libresoc.v:121339.3-121377.6" + wire $0\alu_div0_logical_op__is_32bit$next[0:0]$4898 + attribute \src "libresoc.v:121120.3-121121.75" + wire $0\alu_div0_logical_op__is_32bit[0:0] + attribute \src "libresoc.v:121339.3-121377.6" + wire $0\alu_div0_logical_op__is_signed$next[0:0]$4899 + attribute \src "libresoc.v:121122.3-121123.77" + wire $0\alu_div0_logical_op__is_signed[0:0] + attribute \src "libresoc.v:121339.3-121377.6" + wire $0\alu_div0_logical_op__oe__oe$next[0:0]$4900 + attribute \src "libresoc.v:121104.3-121105.71" + wire $0\alu_div0_logical_op__oe__oe[0:0] + attribute \src "libresoc.v:121339.3-121377.6" + wire $0\alu_div0_logical_op__oe__ok$next[0:0]$4901 + attribute \src "libresoc.v:121106.3-121107.71" + wire $0\alu_div0_logical_op__oe__ok[0:0] + attribute \src "libresoc.v:121339.3-121377.6" + wire $0\alu_div0_logical_op__output_carry$next[0:0]$4902 + attribute \src "libresoc.v:121118.3-121119.83" + wire $0\alu_div0_logical_op__output_carry[0:0] + attribute \src "libresoc.v:121339.3-121377.6" + wire $0\alu_div0_logical_op__rc__ok$next[0:0]$4903 + attribute \src "libresoc.v:121102.3-121103.71" + wire $0\alu_div0_logical_op__rc__ok[0:0] + attribute \src "libresoc.v:121339.3-121377.6" + wire $0\alu_div0_logical_op__rc__rc$next[0:0]$4904 + attribute \src "libresoc.v:121100.3-121101.71" + wire $0\alu_div0_logical_op__rc__rc[0:0] + attribute \src "libresoc.v:121339.3-121377.6" + wire $0\alu_div0_logical_op__write_cr0$next[0:0]$4905 + attribute \src "libresoc.v:121116.3-121117.77" + wire $0\alu_div0_logical_op__write_cr0[0:0] + attribute \src "libresoc.v:121339.3-121377.6" + wire $0\alu_div0_logical_op__zero_a$next[0:0]$4906 + attribute \src "libresoc.v:121110.3-121111.71" + wire $0\alu_div0_logical_op__zero_a[0:0] + attribute \src "libresoc.v:121150.3-121151.40" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:121505.3-121513.6" + wire $0\alu_l_r_alu$next[0:0]$4976 + attribute \src "libresoc.v:121066.3-121067.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:121496.3-121504.6" + wire $0\alui_l_r_alui$next[0:0]$4973 + attribute \src "libresoc.v:121068.3-121069.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:121378.3-121399.6" + wire width 64 $0\data_r0__o$next[63:0]$4932 + attribute \src "libresoc.v:121088.3-121089.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "libresoc.v:121378.3-121399.6" + wire $0\data_r0__o_ok$next[0:0]$4933 + attribute \src "libresoc.v:121090.3-121091.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "libresoc.v:121400.3-121421.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$4940 + attribute \src "libresoc.v:121084.3-121085.43" + wire width 4 $0\data_r1__cr_a[3:0] + attribute \src "libresoc.v:121400.3-121421.6" + wire $0\data_r1__cr_a_ok$next[0:0]$4941 + attribute \src "libresoc.v:121086.3-121087.49" + wire $0\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:121422.3-121443.6" + wire width 2 $0\data_r2__xer_ov$next[1:0]$4948 + attribute \src "libresoc.v:121080.3-121081.47" + wire width 2 $0\data_r2__xer_ov[1:0] + attribute \src "libresoc.v:121422.3-121443.6" + wire $0\data_r2__xer_ov_ok$next[0:0]$4949 + attribute \src "libresoc.v:121082.3-121083.53" + wire $0\data_r2__xer_ov_ok[0:0] + attribute \src "libresoc.v:121444.3-121465.6" + wire $0\data_r3__xer_so$next[0:0]$4956 + attribute \src "libresoc.v:121076.3-121077.47" + wire $0\data_r3__xer_so[0:0] + attribute \src "libresoc.v:121444.3-121465.6" + wire $0\data_r3__xer_so_ok$next[0:0]$4957 + attribute \src "libresoc.v:121078.3-121079.53" + wire $0\data_r3__xer_so_ok[0:0] + attribute \src "libresoc.v:121514.3-121523.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:121524.3-121533.6" + wire width 4 $0\dest2_o[3:0] + attribute \src "libresoc.v:121534.3-121543.6" + wire width 2 $0\dest3_o[1:0] + attribute \src "libresoc.v:121544.3-121553.6" + wire $0\dest4_o[0:0] + attribute \src "libresoc.v:120358.7-120358.20" wire $0\initial[0:0] - attribute \src "libresoc.v:28311.3-28341.6" - wire width 8 $1\dec31_dec_sub21_asmcode[7:0] - attribute \src "libresoc.v:27919.3-27967.6" - wire $1\dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:28587.3-28635.6" - wire width 3 $1\dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:28636.3-28684.6" - wire width 3 $1\dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:27723.3-27771.6" - wire width 2 $1\dec31_dec_sub21_cry_in[1:0] - attribute \src "libresoc.v:27870.3-27918.6" - wire $1\dec31_dec_sub21_cry_out[0:0] - attribute \src "libresoc.v:28342.3-28390.6" - wire width 5 $1\dec31_dec_sub21_form[4:0] - attribute \src "libresoc.v:27527.3-27575.6" - wire width 12 $1\dec31_dec_sub21_function_unit[11:0] - attribute \src "libresoc.v:28391.3-28439.6" - wire width 3 $1\dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:28440.3-28488.6" - wire width 4 $1\dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:28489.3-28537.6" - wire width 2 $1\dec31_dec_sub21_in3_sel[1:0] - attribute \src "libresoc.v:28066.3-28114.6" - wire width 7 $1\dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:27772.3-27820.6" - wire $1\dec31_dec_sub21_inv_a[0:0] - attribute \src "libresoc.v:27821.3-27869.6" - wire $1\dec31_dec_sub21_inv_out[0:0] - attribute \src "libresoc.v:28115.3-28163.6" - wire $1\dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:27576.3-27624.6" - wire width 4 $1\dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:28213.3-28261.6" - wire $1\dec31_dec_sub21_lk[0:0] - attribute \src "libresoc.v:28538.3-28586.6" - wire width 2 $1\dec31_dec_sub21_out_sel[1:0] - attribute \src "libresoc.v:27674.3-27722.6" - wire width 2 $1\dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:28017.3-28065.6" - wire $1\dec31_dec_sub21_rsrv[0:0] - attribute \src "libresoc.v:28262.3-28310.6" - wire $1\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "libresoc.v:28164.3-28212.6" - wire $1\dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:27968.3-28016.6" - wire $1\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:27625.3-27673.6" - wire width 2 $1\dec31_dec_sub21_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub21_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub21_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub21_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub21_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub21_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub21_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub21_form + attribute \src "libresoc.v:121294.3-121302.6" + wire $0\opc_l_r_opc$next[0:0]$4874 + attribute \src "libresoc.v:121136.3-121137.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:121285.3-121293.6" + wire $0\opc_l_s_opc$next[0:0]$4871 + attribute \src "libresoc.v:121138.3-121139.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:121554.3-121562.6" + wire width 4 $0\prev_wr_go$next[3:0]$4983 + attribute \src "libresoc.v:121148.3-121149.37" + wire width 4 $0\prev_wr_go[3:0] + attribute \src "libresoc.v:121239.3-121248.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:121330.3-121338.6" + wire width 4 $0\req_l_r_req$next[3:0]$4886 + attribute \src "libresoc.v:121128.3-121129.39" + wire width 4 $0\req_l_r_req[3:0] + attribute \src "libresoc.v:121321.3-121329.6" + wire width 4 $0\req_l_s_req$next[3:0]$4883 + attribute \src "libresoc.v:121130.3-121131.39" + wire width 4 $0\req_l_s_req[3:0] + attribute \src "libresoc.v:121258.3-121266.6" + wire $0\rok_l_r_rdok$next[0:0]$4862 + attribute \src "libresoc.v:121144.3-121145.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:121249.3-121257.6" + wire $0\rok_l_s_rdok$next[0:0]$4859 + attribute \src "libresoc.v:121146.3-121147.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:121276.3-121284.6" + wire $0\rst_l_r_rst$next[0:0]$4868 + attribute \src "libresoc.v:121140.3-121141.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:121267.3-121275.6" + wire $0\rst_l_s_rst$next[0:0]$4865 + attribute \src "libresoc.v:121142.3-121143.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:121312.3-121320.6" + wire width 3 $0\src_l_r_src$next[2:0]$4880 + attribute \src "libresoc.v:121132.3-121133.39" + wire width 3 $0\src_l_r_src[2:0] + attribute \src "libresoc.v:121303.3-121311.6" + wire width 3 $0\src_l_s_src$next[2:0]$4877 + attribute \src "libresoc.v:121134.3-121135.39" + wire width 3 $0\src_l_s_src[2:0] + attribute \src "libresoc.v:121466.3-121475.6" + wire width 64 $0\src_r0$next[63:0]$4964 + attribute \src "libresoc.v:121074.3-121075.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:121476.3-121485.6" + wire width 64 $0\src_r1$next[63:0]$4967 + attribute \src "libresoc.v:121072.3-121073.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:121486.3-121495.6" + wire $0\src_r2$next[0:0]$4970 + attribute \src "libresoc.v:121070.3-121071.29" + wire $0\src_r2[0:0] + attribute \src "libresoc.v:120488.7-120488.24" + wire $1\all_rd_dly[0:0] + attribute \src "libresoc.v:121339.3-121377.6" + wire width 4 $1\alu_div0_logical_op__data_len$next[3:0]$4907 + attribute \src "libresoc.v:120498.13-120498.49" + wire width 4 $1\alu_div0_logical_op__data_len[3:0] + attribute \src "libresoc.v:121339.3-121377.6" + wire width 12 $1\alu_div0_logical_op__fn_unit$next[11:0]$4908 + attribute \src "libresoc.v:120515.14-120515.52" + wire width 12 $1\alu_div0_logical_op__fn_unit[11:0] + attribute \src "libresoc.v:121339.3-121377.6" + wire width 64 $1\alu_div0_logical_op__imm_data__data$next[63:0]$4909 + attribute \src "libresoc.v:120519.14-120519.72" + wire width 64 $1\alu_div0_logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:121339.3-121377.6" + wire $1\alu_div0_logical_op__imm_data__ok$next[0:0]$4910 + attribute \src "libresoc.v:120523.7-120523.47" + wire $1\alu_div0_logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:121339.3-121377.6" + wire width 2 $1\alu_div0_logical_op__input_carry$next[1:0]$4911 + attribute \src "libresoc.v:120531.13-120531.52" + wire width 2 $1\alu_div0_logical_op__input_carry[1:0] + attribute \src "libresoc.v:121339.3-121377.6" + wire width 32 $1\alu_div0_logical_op__insn$next[31:0]$4912 + attribute \src "libresoc.v:120535.14-120535.47" + wire width 32 $1\alu_div0_logical_op__insn[31:0] + attribute \src "libresoc.v:121339.3-121377.6" + wire width 7 $1\alu_div0_logical_op__insn_type$next[6:0]$4913 + attribute \src "libresoc.v:120613.13-120613.51" + wire width 7 $1\alu_div0_logical_op__insn_type[6:0] + attribute \src "libresoc.v:121339.3-121377.6" + wire $1\alu_div0_logical_op__invert_in$next[0:0]$4914 + attribute \src "libresoc.v:120617.7-120617.44" + wire $1\alu_div0_logical_op__invert_in[0:0] + attribute \src "libresoc.v:121339.3-121377.6" + wire $1\alu_div0_logical_op__invert_out$next[0:0]$4915 + attribute \src "libresoc.v:120621.7-120621.45" + wire $1\alu_div0_logical_op__invert_out[0:0] + attribute \src "libresoc.v:121339.3-121377.6" + wire $1\alu_div0_logical_op__is_32bit$next[0:0]$4916 + attribute \src "libresoc.v:120625.7-120625.43" + wire $1\alu_div0_logical_op__is_32bit[0:0] + attribute \src "libresoc.v:121339.3-121377.6" + wire $1\alu_div0_logical_op__is_signed$next[0:0]$4917 + attribute \src "libresoc.v:120629.7-120629.44" + wire $1\alu_div0_logical_op__is_signed[0:0] + attribute \src "libresoc.v:121339.3-121377.6" + wire $1\alu_div0_logical_op__oe__oe$next[0:0]$4918 + attribute \src "libresoc.v:120633.7-120633.41" + wire $1\alu_div0_logical_op__oe__oe[0:0] + attribute \src "libresoc.v:121339.3-121377.6" + wire $1\alu_div0_logical_op__oe__ok$next[0:0]$4919 + attribute \src "libresoc.v:120637.7-120637.41" + wire $1\alu_div0_logical_op__oe__ok[0:0] + attribute \src "libresoc.v:121339.3-121377.6" + wire $1\alu_div0_logical_op__output_carry$next[0:0]$4920 + attribute \src "libresoc.v:120641.7-120641.47" + wire $1\alu_div0_logical_op__output_carry[0:0] + attribute \src "libresoc.v:121339.3-121377.6" + wire $1\alu_div0_logical_op__rc__ok$next[0:0]$4921 + attribute \src "libresoc.v:120645.7-120645.41" + wire $1\alu_div0_logical_op__rc__ok[0:0] + attribute \src "libresoc.v:121339.3-121377.6" + wire $1\alu_div0_logical_op__rc__rc$next[0:0]$4922 + attribute \src "libresoc.v:120649.7-120649.41" + wire $1\alu_div0_logical_op__rc__rc[0:0] + attribute \src "libresoc.v:121339.3-121377.6" + wire $1\alu_div0_logical_op__write_cr0$next[0:0]$4923 + attribute \src "libresoc.v:120653.7-120653.44" + wire $1\alu_div0_logical_op__write_cr0[0:0] + attribute \src "libresoc.v:121339.3-121377.6" + wire $1\alu_div0_logical_op__zero_a$next[0:0]$4924 + attribute \src "libresoc.v:120657.7-120657.41" + wire $1\alu_div0_logical_op__zero_a[0:0] + attribute \src "libresoc.v:120683.7-120683.26" + wire $1\alu_done_dly[0:0] + attribute \src "libresoc.v:121505.3-121513.6" + wire $1\alu_l_r_alu$next[0:0]$4977 + attribute \src "libresoc.v:120691.7-120691.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "libresoc.v:121496.3-121504.6" + wire $1\alui_l_r_alui$next[0:0]$4974 + attribute \src "libresoc.v:120703.7-120703.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "libresoc.v:121378.3-121399.6" + wire width 64 $1\data_r0__o$next[63:0]$4934 + attribute \src "libresoc.v:120737.14-120737.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "libresoc.v:121378.3-121399.6" + wire $1\data_r0__o_ok$next[0:0]$4935 + attribute \src "libresoc.v:120741.7-120741.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "libresoc.v:121400.3-121421.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$4942 + attribute \src "libresoc.v:120745.13-120745.33" + wire width 4 $1\data_r1__cr_a[3:0] + attribute \src "libresoc.v:121400.3-121421.6" + wire $1\data_r1__cr_a_ok$next[0:0]$4943 + attribute \src "libresoc.v:120749.7-120749.30" + wire $1\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:121422.3-121443.6" + wire width 2 $1\data_r2__xer_ov$next[1:0]$4950 + attribute \src "libresoc.v:120753.13-120753.35" + wire width 2 $1\data_r2__xer_ov[1:0] + attribute \src "libresoc.v:121422.3-121443.6" + wire $1\data_r2__xer_ov_ok$next[0:0]$4951 + attribute \src "libresoc.v:120757.7-120757.32" + wire $1\data_r2__xer_ov_ok[0:0] + attribute \src "libresoc.v:121444.3-121465.6" + wire $1\data_r3__xer_so$next[0:0]$4958 + attribute \src "libresoc.v:120761.7-120761.29" + wire $1\data_r3__xer_so[0:0] + attribute \src "libresoc.v:121444.3-121465.6" + wire $1\data_r3__xer_so_ok$next[0:0]$4959 + attribute \src "libresoc.v:120765.7-120765.32" + wire $1\data_r3__xer_so_ok[0:0] + attribute \src "libresoc.v:121514.3-121523.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "libresoc.v:121524.3-121533.6" + wire width 4 $1\dest2_o[3:0] + attribute \src "libresoc.v:121534.3-121543.6" + wire width 2 $1\dest3_o[1:0] + attribute \src "libresoc.v:121544.3-121553.6" + wire $1\dest4_o[0:0] + attribute \src "libresoc.v:121294.3-121302.6" + wire $1\opc_l_r_opc$next[0:0]$4875 + attribute \src "libresoc.v:120785.7-120785.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "libresoc.v:121285.3-121293.6" + wire $1\opc_l_s_opc$next[0:0]$4872 + attribute \src "libresoc.v:120789.7-120789.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "libresoc.v:121554.3-121562.6" + wire width 4 $1\prev_wr_go$next[3:0]$4984 + attribute \src "libresoc.v:120920.13-120920.30" + wire width 4 $1\prev_wr_go[3:0] + attribute \src "libresoc.v:121239.3-121248.6" + wire $1\req_done[0:0] + attribute \src "libresoc.v:121330.3-121338.6" + wire width 4 $1\req_l_r_req$next[3:0]$4887 + attribute \src "libresoc.v:120928.13-120928.31" + wire width 4 $1\req_l_r_req[3:0] + attribute \src "libresoc.v:121321.3-121329.6" + wire width 4 $1\req_l_s_req$next[3:0]$4884 + attribute \src "libresoc.v:120932.13-120932.31" + wire width 4 $1\req_l_s_req[3:0] + attribute \src "libresoc.v:121258.3-121266.6" + wire $1\rok_l_r_rdok$next[0:0]$4863 + attribute \src "libresoc.v:120944.7-120944.26" + wire $1\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:121249.3-121257.6" + wire $1\rok_l_s_rdok$next[0:0]$4860 + attribute \src "libresoc.v:120948.7-120948.26" + wire $1\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:121276.3-121284.6" + wire $1\rst_l_r_rst$next[0:0]$4869 + attribute \src "libresoc.v:120952.7-120952.25" + wire $1\rst_l_r_rst[0:0] + attribute \src "libresoc.v:121267.3-121275.6" + wire $1\rst_l_s_rst$next[0:0]$4866 + attribute \src "libresoc.v:120956.7-120956.25" + wire $1\rst_l_s_rst[0:0] + attribute \src "libresoc.v:121312.3-121320.6" + wire width 3 $1\src_l_r_src$next[2:0]$4881 + attribute \src "libresoc.v:120970.13-120970.31" + wire width 3 $1\src_l_r_src[2:0] + attribute \src "libresoc.v:121303.3-121311.6" + wire width 3 $1\src_l_s_src$next[2:0]$4878 + attribute \src "libresoc.v:120974.13-120974.31" + wire width 3 $1\src_l_s_src[2:0] + attribute \src "libresoc.v:121466.3-121475.6" + wire width 64 $1\src_r0$next[63:0]$4965 + attribute \src "libresoc.v:120982.14-120982.43" + wire width 64 $1\src_r0[63:0] + attribute \src "libresoc.v:121476.3-121485.6" + wire width 64 $1\src_r1$next[63:0]$4968 + attribute \src "libresoc.v:120986.14-120986.43" + wire width 64 $1\src_r1[63:0] + attribute \src "libresoc.v:121486.3-121495.6" + wire $1\src_r2$next[0:0]$4971 + attribute \src "libresoc.v:120990.7-120990.20" + wire $1\src_r2[0:0] + attribute \src "libresoc.v:121339.3-121377.6" + wire width 64 $2\alu_div0_logical_op__imm_data__data$next[63:0]$4925 + attribute \src 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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \all_rd_dly$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" + wire \all_rd_pulse + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \all_rd_rise + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \alu_div0_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_div0_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_div0_logical_op__data_len$next attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -40147,39 +189533,311 @@ module \dec31_dec_sub21 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub21_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub21_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub21_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub21_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_div0_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_div0_logical_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_div0_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_div0_logical_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_div0_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_div0_logical_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_div0_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_div0_logical_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_div0_logical_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_div0_logical_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__zero_a$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \alu_div0_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \alu_div0_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \alu_div0_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \alu_div0_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \alu_div0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_div0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_div0_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \alu_div0_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \alu_div0_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \alu_div0_xer_so$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" + wire \alu_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \alu_done_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \alu_done_dly$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \alu_done_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \alu_l_q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alu_l_r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alu_l_r_alu$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \alu_l_s_alu + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" + wire \alu_pulse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + wire width 4 \alu_pulsem + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \alui_l_s_alui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 38 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 32 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 21 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 20 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 24 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 23 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 22 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 30 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 29 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 4 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 31 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 33 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 35 \dest3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 37 \dest4_o + attribute \src "libresoc.v:120358.7-120358.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 28 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \opc_l_q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 18 \oper_i_alu_div0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 3 \oper_i_alu_div0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 4 \oper_i_alu_div0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \oper_i_alu_div0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 12 \oper_i_alu_div0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 19 \oper_i_alu_div0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -40254,2009 +189912,4262 @@ module \dec31_dec_sub21 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub21_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub21_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub21_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub21_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub21_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub21_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub21_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub21_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub21_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub21_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub21_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub21_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub21_upd - attribute \src "libresoc.v:27270.7-27270.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:27270.7-27270.20" - process $proc$libresoc.v:27270$631 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 2 \oper_i_alu_div0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \oper_i_alu_div0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \oper_i_alu_div0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \oper_i_alu_div0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \oper_i_alu_div0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \oper_i_alu_div0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \oper_i_alu_div0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \oper_i_alu_div0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \oper_i_alu_div0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \oper_i_alu_div0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \oper_i_alu_div0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \oper_i_alu_div0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 4 \prev_wr_go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 4 \prev_wr_go$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" + wire \req_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 4 \req_l_q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 \req_l_r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 \req_l_r_req$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 \req_l_s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 \req_l_s_req$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + wire \reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" + wire width 3 \reset_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" + wire width 4 \reset_w + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \rok_l_q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rok_l_r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rok_l_r_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rok_l_s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rok_l_s_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rst_l_r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rst_l_r_rst$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rst_l_s_rst$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + wire \rst_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 25 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 26 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 27 \src3_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 \src_l_q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \src_l_r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \src_l_r_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \src_l_s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \src_l_s_src$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" + wire width 64 \src_or_imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" + wire width 64 \src_or_imm$85 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire \src_r2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire \src_r2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" + wire \src_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" + wire \src_sel$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + wire \wr_any + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 34 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 36 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:121005$4752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$98 + connect \B { 1'1 \$102 \$100 } + connect \Y $and$libresoc.v:121005$4752_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:121007$4754 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$104 + connect \B \$106 + connect \Y $and$libresoc.v:121007$4754_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $and $and$libresoc.v:121008$4755 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$2 + connect \B \$4 + connect \Y $and$libresoc.v:121008$4755_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:121009$4756 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:121009$4756_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:121010$4757 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:121010$4757_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:121011$4758 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:121011$4758_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:121012$4759 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:121012$4759_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $and$libresoc.v:121013$4760 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \req_l_q_req + connect \B { \$110 \$112 \$114 \$116 } + connect \Y $and$libresoc.v:121013$4760_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $and$libresoc.v:121014$4761 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$118 + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:121014$4761_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:121015$4762 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [0] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:121015$4762_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:121016$4763 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [1] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:121016$4763_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:121017$4764 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [2] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:121017$4764_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:121018$4765 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [3] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:121018$4765_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:121020$4767 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd + connect \B \$12 + connect \Y $and$libresoc.v:121020$4767_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:121022$4769 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done + connect \B \$16 + connect \Y $and$libresoc.v:121022$4769_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + cell $and $and$libresoc.v:121023$4770 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wr__go_i + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$libresoc.v:121023$4770_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $and$libresoc.v:121025$4772 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wr__rel_o + connect \B \$24 + connect \Y $and$libresoc.v:121025$4772_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + cell $and $and$libresoc.v:121028$4775 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \rok_l_q_rdok + connect \Y $and$libresoc.v:121028$4775_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $and$libresoc.v:121029$4776 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \$22 + connect \Y $and$libresoc.v:121029$4776_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $and $and$libresoc.v:121034$4781 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_any + connect \B \$38 + connect \Y $and$libresoc.v:121034$4781_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$libresoc.v:121035$4782 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \req_l_q_req + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:121035$4782_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$libresoc.v:121037$4784 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$40 + connect \B \$44 + connect \Y $and$libresoc.v:121037$4784_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:121039$4786 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$48 + connect \B \alu_div0_n_ready_i + connect \Y $and$libresoc.v:121039$4786_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:121040$4787 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$50 + connect \B \alu_div0_n_valid_o + connect \Y $and$libresoc.v:121040$4787_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:121041$4788 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$52 + connect \B \cu_busy_o + connect \Y $and$libresoc.v:121041$4788_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + cell $and $and$libresoc.v:121047$4794 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_div0_n_valid_o + connect \B \cu_busy_o + connect \Y $and$libresoc.v:121047$4794_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + cell $and $and$libresoc.v:121048$4795 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \alu_pulsem + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:121048$4795_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:121050$4797 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:121050$4797_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:121051$4798 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cr_a_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:121051$4798_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:121052$4799 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_ov_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:121052$4799_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:121053$4800 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_so_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:121053$4800_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + cell $and $and$libresoc.v:121063$4810 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_div0_p_ready_o + connect \B \alui_l_q_alui + connect \Y $and$libresoc.v:121063$4810_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + cell $and $and$libresoc.v:121064$4811 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_div0_n_valid_o + connect \B \alu_l_q_alu + connect \Y $and$libresoc.v:121064$4811_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:121065$4812 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \src_l_q_src + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$libresoc.v:121065$4812_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $eq$libresoc.v:121036$4783 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$42 + connect \B 1'0 + connect \Y $eq$libresoc.v:121036$4783_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $eq$libresoc.v:121038$4785 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $eq$libresoc.v:121038$4785_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$libresoc.v:121003$4750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_div0_logical_op__zero_a + connect \Y $not$libresoc.v:121003$4750_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$libresoc.v:121004$4751 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_div0_logical_op__imm_data__ok + connect \Y $not$libresoc.v:121004$4751_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$libresoc.v:121006$4753 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rdmaskn_i + connect \Y $not$libresoc.v:121006$4753_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:121019$4766 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $not$libresoc.v:121019$4766_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:121021$4768 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $not$libresoc.v:121021$4768_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:121024$4771 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wrmask_o + connect \Y $not$libresoc.v:121024$4771_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:121027$4774 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$23 + connect \Y $not$libresoc.v:121027$4774_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$libresoc.v:121033$4780 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_div0_n_ready_i + connect \Y $not$libresoc.v:121033$4780_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$libresoc.v:121044$4791 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__rel_o + connect \Y $not$libresoc.v:121044$4791_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$libresoc.v:121032$4779 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$32 + connect \B \$34 + connect \Y $or$libresoc.v:121032$4779_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$libresoc.v:121042$4789 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:121042$4789_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$libresoc.v:121043$4790 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:121043$4790_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$libresoc.v:121045$4792 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:121045$4792_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$libresoc.v:121046$4793 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:121046$4793_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:121049$4796 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$libresoc.v:121049$4796_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:121055$4802 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$5 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:121055$4802_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:121060$4807 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$7 + connect \Y $reduce_and$libresoc.v:121060$4807_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:121026$4773 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \Y $reduce_or$libresoc.v:121026$4773_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:121030$4777 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:121030$4777_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:121031$4778 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:121031$4778_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:121054$4801 + parameter \WIDTH 1 + connect \A \src_l_q_src [0] + connect \B \opc_l_q_opc + connect \S \alu_div0_logical_op__zero_a + connect \Y $ternary$libresoc.v:121054$4801_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:121056$4803 + parameter \WIDTH 64 + connect \A \src1_i + connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \S \alu_div0_logical_op__zero_a + connect \Y $ternary$libresoc.v:121056$4803_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:121057$4804 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_div0_logical_op__imm_data__ok + connect \Y $ternary$libresoc.v:121057$4804_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:121058$4805 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_div0_logical_op__imm_data__data + connect \S \alu_div0_logical_op__imm_data__ok + connect \Y $ternary$libresoc.v:121058$4805_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:121059$4806 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $ternary$libresoc.v:121059$4806_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:121061$4808 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm$85 + connect \S \src_sel$82 + connect \Y $ternary$libresoc.v:121061$4808_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:121062$4809 + parameter \WIDTH 1 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:121062$4809_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:121154.12-121190.4" + cell \alu_div0 \alu_div0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \alu_div0_cr_a + connect \cr_a_ok \cr_a_ok + connect \logical_op__data_len \alu_div0_logical_op__data_len + connect \logical_op__fn_unit \alu_div0_logical_op__fn_unit + connect \logical_op__imm_data__data \alu_div0_logical_op__imm_data__data + connect \logical_op__imm_data__ok \alu_div0_logical_op__imm_data__ok + connect \logical_op__input_carry \alu_div0_logical_op__input_carry + connect \logical_op__insn \alu_div0_logical_op__insn + connect \logical_op__insn_type \alu_div0_logical_op__insn_type + connect \logical_op__invert_in \alu_div0_logical_op__invert_in + connect \logical_op__invert_out \alu_div0_logical_op__invert_out + connect \logical_op__is_32bit \alu_div0_logical_op__is_32bit + connect \logical_op__is_signed \alu_div0_logical_op__is_signed + connect \logical_op__oe__oe \alu_div0_logical_op__oe__oe + connect \logical_op__oe__ok \alu_div0_logical_op__oe__ok + connect \logical_op__output_carry \alu_div0_logical_op__output_carry + connect \logical_op__rc__ok \alu_div0_logical_op__rc__ok + connect \logical_op__rc__rc \alu_div0_logical_op__rc__rc + connect \logical_op__write_cr0 \alu_div0_logical_op__write_cr0 + connect \logical_op__zero_a \alu_div0_logical_op__zero_a + connect \n_ready_i \alu_div0_n_ready_i + connect \n_valid_o \alu_div0_n_valid_o + connect \o \alu_div0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_div0_p_ready_o + connect \p_valid_i \alu_div0_p_valid_i + connect \ra \alu_div0_ra + connect \rb \alu_div0_rb + connect \xer_ov \alu_div0_xer_ov + connect \xer_ov_ok \xer_ov_ok + connect \xer_so \alu_div0_xer_so + connect \xer_so$1 \alu_div0_xer_so$1 + connect \xer_so_ok \xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:121191.14-121197.4" + cell \alu_l$90 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:121198.15-121204.4" + cell \alui_l$89 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:121205.14-121211.4" + cell \opc_l$85 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:121212.14-121218.4" + cell \req_l$86 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:121219.14-121225.4" + cell \rok_l$88 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:121226.14-121231.4" + cell \rst_l$87 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:121232.14-121238.4" + cell \src_l$84 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "libresoc.v:120358.7-120358.20" + process $proc$libresoc.v:120358$4985 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:27527.3-27575.6" - process $proc$libresoc.v:27527$607 + attribute \src "libresoc.v:120488.7-120488.24" + process $proc$libresoc.v:120488$4986 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "libresoc.v:120498.13-120498.49" + process $proc$libresoc.v:120498$4987 assign { } { } + assign $1\alu_div0_logical_op__data_len[3:0] 4'0000 + sync always + sync init + update \alu_div0_logical_op__data_len $1\alu_div0_logical_op__data_len[3:0] + end + attribute \src "libresoc.v:120515.14-120515.52" + process $proc$libresoc.v:120515$4988 assign { } { } - assign $0\dec31_dec_sub21_function_unit[11:0] $1\dec31_dec_sub21_function_unit[11:0] - attribute \src "libresoc.v:27528.5-27528.29" + assign $1\alu_div0_logical_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \alu_div0_logical_op__fn_unit $1\alu_div0_logical_op__fn_unit[11:0] + end + attribute \src "libresoc.v:120519.14-120519.72" + process $proc$libresoc.v:120519$4989 + assign { } { } + assign $1\alu_div0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_div0_logical_op__imm_data__data $1\alu_div0_logical_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:120523.7-120523.47" + process $proc$libresoc.v:120523$4990 + assign { } { } + assign $1\alu_div0_logical_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__imm_data__ok $1\alu_div0_logical_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:120531.13-120531.52" + process $proc$libresoc.v:120531$4991 + assign { } { } + assign $1\alu_div0_logical_op__input_carry[1:0] 2'00 + sync always + sync init + update \alu_div0_logical_op__input_carry $1\alu_div0_logical_op__input_carry[1:0] + end + attribute \src "libresoc.v:120535.14-120535.47" + process $proc$libresoc.v:120535$4992 + assign { } { } + assign $1\alu_div0_logical_op__insn[31:0] 0 + sync always + sync init + update \alu_div0_logical_op__insn $1\alu_div0_logical_op__insn[31:0] + end + attribute \src "libresoc.v:120613.13-120613.51" + process $proc$libresoc.v:120613$4993 + assign { } { } + assign $1\alu_div0_logical_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_div0_logical_op__insn_type $1\alu_div0_logical_op__insn_type[6:0] + end + attribute \src "libresoc.v:120617.7-120617.44" + process $proc$libresoc.v:120617$4994 + assign { } { } + assign $1\alu_div0_logical_op__invert_in[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__invert_in $1\alu_div0_logical_op__invert_in[0:0] + end + attribute \src "libresoc.v:120621.7-120621.45" + process $proc$libresoc.v:120621$4995 + assign { } { } + assign $1\alu_div0_logical_op__invert_out[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__invert_out $1\alu_div0_logical_op__invert_out[0:0] + end + attribute \src "libresoc.v:120625.7-120625.43" + process $proc$libresoc.v:120625$4996 + assign { } { } + assign $1\alu_div0_logical_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__is_32bit $1\alu_div0_logical_op__is_32bit[0:0] + end + attribute \src "libresoc.v:120629.7-120629.44" + process $proc$libresoc.v:120629$4997 + assign { } { } + assign $1\alu_div0_logical_op__is_signed[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__is_signed $1\alu_div0_logical_op__is_signed[0:0] + end + attribute \src "libresoc.v:120633.7-120633.41" + process $proc$libresoc.v:120633$4998 + assign { } { } + assign $1\alu_div0_logical_op__oe__oe[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__oe__oe $1\alu_div0_logical_op__oe__oe[0:0] + end + attribute \src "libresoc.v:120637.7-120637.41" + process $proc$libresoc.v:120637$4999 + assign { } { } + assign $1\alu_div0_logical_op__oe__ok[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__oe__ok $1\alu_div0_logical_op__oe__ok[0:0] + end + attribute \src "libresoc.v:120641.7-120641.47" + process $proc$libresoc.v:120641$5000 + assign { } { } + assign $1\alu_div0_logical_op__output_carry[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__output_carry $1\alu_div0_logical_op__output_carry[0:0] + end + attribute \src "libresoc.v:120645.7-120645.41" + process $proc$libresoc.v:120645$5001 + assign { } { } + assign $1\alu_div0_logical_op__rc__ok[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__rc__ok $1\alu_div0_logical_op__rc__ok[0:0] + end + attribute \src "libresoc.v:120649.7-120649.41" + process $proc$libresoc.v:120649$5002 + assign { } { } + assign $1\alu_div0_logical_op__rc__rc[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__rc__rc $1\alu_div0_logical_op__rc__rc[0:0] + end + attribute \src "libresoc.v:120653.7-120653.44" + process $proc$libresoc.v:120653$5003 + assign { } { } + assign $1\alu_div0_logical_op__write_cr0[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__write_cr0 $1\alu_div0_logical_op__write_cr0[0:0] + end + attribute \src "libresoc.v:120657.7-120657.41" + process $proc$libresoc.v:120657$5004 + assign { } { } + assign $1\alu_div0_logical_op__zero_a[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__zero_a $1\alu_div0_logical_op__zero_a[0:0] + end + attribute \src "libresoc.v:120683.7-120683.26" + process $proc$libresoc.v:120683$5005 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "libresoc.v:120691.7-120691.25" + process $proc$libresoc.v:120691$5006 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:120703.7-120703.27" + process $proc$libresoc.v:120703$5007 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:120737.14-120737.47" + process $proc$libresoc.v:120737$5008 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "libresoc.v:120741.7-120741.27" + process $proc$libresoc.v:120741$5009 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:120745.13-120745.33" + process $proc$libresoc.v:120745$5010 + assign { } { } + assign $1\data_r1__cr_a[3:0] 4'0000 + sync always + sync init + update \data_r1__cr_a $1\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:120749.7-120749.30" + process $proc$libresoc.v:120749$5011 + assign { } { } + assign $1\data_r1__cr_a_ok[0:0] 1'0 + sync always + sync init + update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:120753.13-120753.35" + process $proc$libresoc.v:120753$5012 + assign { } { } + assign $1\data_r2__xer_ov[1:0] 2'00 + sync always + sync init + update \data_r2__xer_ov $1\data_r2__xer_ov[1:0] + end + attribute \src "libresoc.v:120757.7-120757.32" + process $proc$libresoc.v:120757$5013 + assign { } { } + assign $1\data_r2__xer_ov_ok[0:0] 1'0 + sync always + sync init + update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0] + end + attribute \src "libresoc.v:120761.7-120761.29" + process $proc$libresoc.v:120761$5014 + assign { } { } + assign $1\data_r3__xer_so[0:0] 1'0 + sync always + sync init + update \data_r3__xer_so $1\data_r3__xer_so[0:0] + end + attribute \src "libresoc.v:120765.7-120765.32" + process $proc$libresoc.v:120765$5015 + assign { } { } + assign $1\data_r3__xer_so_ok[0:0] 1'0 + sync always + sync init + update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] + end + attribute \src "libresoc.v:120785.7-120785.25" + process $proc$libresoc.v:120785$5016 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:120789.7-120789.25" + process $proc$libresoc.v:120789$5017 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:120920.13-120920.30" + process $proc$libresoc.v:120920$5018 + assign { } { } + assign $1\prev_wr_go[3:0] 4'0000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[3:0] + end + attribute \src "libresoc.v:120928.13-120928.31" + process $proc$libresoc.v:120928$5019 + assign { } { } + assign $1\req_l_r_req[3:0] 4'1111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[3:0] + end + attribute \src "libresoc.v:120932.13-120932.31" + process $proc$libresoc.v:120932$5020 + assign { } { } + assign $1\req_l_s_req[3:0] 4'0000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[3:0] + end + attribute \src "libresoc.v:120944.7-120944.26" + process $proc$libresoc.v:120944$5021 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:120948.7-120948.26" + process $proc$libresoc.v:120948$5022 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:120952.7-120952.25" + process $proc$libresoc.v:120952$5023 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:120956.7-120956.25" + process $proc$libresoc.v:120956$5024 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:120970.13-120970.31" + process $proc$libresoc.v:120970$5025 + assign { } { } + assign $1\src_l_r_src[2:0] 3'111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[2:0] + end + attribute \src "libresoc.v:120974.13-120974.31" + process $proc$libresoc.v:120974$5026 + assign { } { } + assign $1\src_l_s_src[2:0] 3'000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[2:0] + end + attribute \src "libresoc.v:120982.14-120982.43" + process $proc$libresoc.v:120982$5027 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:120986.14-120986.43" + process $proc$libresoc.v:120986$5028 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:120990.7-120990.20" + process $proc$libresoc.v:120990$5029 + assign { } { } + assign $1\src_r2[0:0] 1'0 + sync always + sync init + update \src_r2 $1\src_r2[0:0] + end + attribute \src "libresoc.v:121066.3-121067.39" + process $proc$libresoc.v:121066$4813 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:121068.3-121069.43" + process $proc$libresoc.v:121068$4814 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:121070.3-121071.29" + process $proc$libresoc.v:121070$4815 + assign { } { } + assign $0\src_r2[0:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[0:0] + end + attribute \src "libresoc.v:121072.3-121073.29" + process $proc$libresoc.v:121072$4816 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:121074.3-121075.29" + process $proc$libresoc.v:121074$4817 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:121076.3-121077.47" + process $proc$libresoc.v:121076$4818 + assign { } { } + assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next + sync posedge \coresync_clk + update \data_r3__xer_so $0\data_r3__xer_so[0:0] + end + attribute \src "libresoc.v:121078.3-121079.53" + process $proc$libresoc.v:121078$4819 + assign { } { } + assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next + sync posedge \coresync_clk + update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] + end + attribute \src "libresoc.v:121080.3-121081.47" + process $proc$libresoc.v:121080$4820 + assign { } { } + assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next + sync posedge \coresync_clk + update \data_r2__xer_ov $0\data_r2__xer_ov[1:0] + end + attribute \src "libresoc.v:121082.3-121083.53" + process $proc$libresoc.v:121082$4821 + assign { } { } + assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next + sync posedge \coresync_clk + update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0] + end + attribute \src "libresoc.v:121084.3-121085.43" + process $proc$libresoc.v:121084$4822 + assign { } { } + assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next + sync posedge \coresync_clk + update \data_r1__cr_a $0\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:121086.3-121087.49" + process $proc$libresoc.v:121086$4823 + assign { } { } + assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next + sync posedge \coresync_clk + update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:121088.3-121089.37" + process $proc$libresoc.v:121088$4824 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "libresoc.v:121090.3-121091.43" + process $proc$libresoc.v:121090$4825 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:121092.3-121093.77" + process $proc$libresoc.v:121092$4826 + assign { } { } + assign $0\alu_div0_logical_op__insn_type[6:0] \alu_div0_logical_op__insn_type$next + sync posedge \coresync_clk + update \alu_div0_logical_op__insn_type $0\alu_div0_logical_op__insn_type[6:0] + end + attribute \src "libresoc.v:121094.3-121095.73" + process $proc$libresoc.v:121094$4827 + assign { } { } + assign $0\alu_div0_logical_op__fn_unit[11:0] \alu_div0_logical_op__fn_unit$next + sync posedge \coresync_clk + update \alu_div0_logical_op__fn_unit $0\alu_div0_logical_op__fn_unit[11:0] + end + attribute \src "libresoc.v:121096.3-121097.87" + process $proc$libresoc.v:121096$4828 + assign { } { } + assign $0\alu_div0_logical_op__imm_data__data[63:0] \alu_div0_logical_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_div0_logical_op__imm_data__data $0\alu_div0_logical_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:121098.3-121099.83" + process $proc$libresoc.v:121098$4829 + assign { } { } + assign $0\alu_div0_logical_op__imm_data__ok[0:0] \alu_div0_logical_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_div0_logical_op__imm_data__ok $0\alu_div0_logical_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:121100.3-121101.71" + process $proc$libresoc.v:121100$4830 + assign { } { } + assign $0\alu_div0_logical_op__rc__rc[0:0] \alu_div0_logical_op__rc__rc$next + sync posedge \coresync_clk + update \alu_div0_logical_op__rc__rc $0\alu_div0_logical_op__rc__rc[0:0] + end + attribute \src "libresoc.v:121102.3-121103.71" + process $proc$libresoc.v:121102$4831 + assign { } { } + assign $0\alu_div0_logical_op__rc__ok[0:0] \alu_div0_logical_op__rc__ok$next + sync posedge \coresync_clk + update \alu_div0_logical_op__rc__ok $0\alu_div0_logical_op__rc__ok[0:0] + end + attribute \src "libresoc.v:121104.3-121105.71" + process $proc$libresoc.v:121104$4832 + assign { } { } + assign $0\alu_div0_logical_op__oe__oe[0:0] \alu_div0_logical_op__oe__oe$next + sync posedge \coresync_clk + update \alu_div0_logical_op__oe__oe $0\alu_div0_logical_op__oe__oe[0:0] + end + attribute \src "libresoc.v:121106.3-121107.71" + process $proc$libresoc.v:121106$4833 + assign { } { } + assign $0\alu_div0_logical_op__oe__ok[0:0] \alu_div0_logical_op__oe__ok$next + sync posedge \coresync_clk + update \alu_div0_logical_op__oe__ok $0\alu_div0_logical_op__oe__ok[0:0] + end + attribute \src "libresoc.v:121108.3-121109.77" + process $proc$libresoc.v:121108$4834 + assign { } { } + assign $0\alu_div0_logical_op__invert_in[0:0] \alu_div0_logical_op__invert_in$next + sync posedge \coresync_clk + update \alu_div0_logical_op__invert_in $0\alu_div0_logical_op__invert_in[0:0] + end + attribute \src "libresoc.v:121110.3-121111.71" + process $proc$libresoc.v:121110$4835 + assign { } { } + assign $0\alu_div0_logical_op__zero_a[0:0] \alu_div0_logical_op__zero_a$next + sync posedge \coresync_clk + update \alu_div0_logical_op__zero_a $0\alu_div0_logical_op__zero_a[0:0] + end + attribute \src "libresoc.v:121112.3-121113.81" + process $proc$libresoc.v:121112$4836 + assign { } { } + assign $0\alu_div0_logical_op__input_carry[1:0] \alu_div0_logical_op__input_carry$next + sync posedge \coresync_clk + update \alu_div0_logical_op__input_carry $0\alu_div0_logical_op__input_carry[1:0] + end + attribute \src "libresoc.v:121114.3-121115.79" + process $proc$libresoc.v:121114$4837 + assign { } { } + assign $0\alu_div0_logical_op__invert_out[0:0] \alu_div0_logical_op__invert_out$next + sync posedge \coresync_clk + update \alu_div0_logical_op__invert_out $0\alu_div0_logical_op__invert_out[0:0] + end + attribute \src "libresoc.v:121116.3-121117.77" + process $proc$libresoc.v:121116$4838 + assign { } { } + assign $0\alu_div0_logical_op__write_cr0[0:0] \alu_div0_logical_op__write_cr0$next + sync posedge \coresync_clk + update \alu_div0_logical_op__write_cr0 $0\alu_div0_logical_op__write_cr0[0:0] + end + attribute \src "libresoc.v:121118.3-121119.83" + process $proc$libresoc.v:121118$4839 + assign { } { } + assign $0\alu_div0_logical_op__output_carry[0:0] \alu_div0_logical_op__output_carry$next + sync posedge \coresync_clk + update \alu_div0_logical_op__output_carry $0\alu_div0_logical_op__output_carry[0:0] + end + attribute \src "libresoc.v:121120.3-121121.75" + process $proc$libresoc.v:121120$4840 + assign { } { } + assign $0\alu_div0_logical_op__is_32bit[0:0] \alu_div0_logical_op__is_32bit$next + sync posedge \coresync_clk + update \alu_div0_logical_op__is_32bit $0\alu_div0_logical_op__is_32bit[0:0] + end + attribute \src "libresoc.v:121122.3-121123.77" + process $proc$libresoc.v:121122$4841 + assign { } { } + assign $0\alu_div0_logical_op__is_signed[0:0] \alu_div0_logical_op__is_signed$next + sync posedge \coresync_clk + update \alu_div0_logical_op__is_signed $0\alu_div0_logical_op__is_signed[0:0] + end + attribute \src "libresoc.v:121124.3-121125.75" + process $proc$libresoc.v:121124$4842 + assign { } { } + assign $0\alu_div0_logical_op__data_len[3:0] \alu_div0_logical_op__data_len$next + sync posedge \coresync_clk + update \alu_div0_logical_op__data_len $0\alu_div0_logical_op__data_len[3:0] + end + attribute \src "libresoc.v:121126.3-121127.67" + process $proc$libresoc.v:121126$4843 + assign { } { } + assign $0\alu_div0_logical_op__insn[31:0] \alu_div0_logical_op__insn$next + sync posedge \coresync_clk + update \alu_div0_logical_op__insn $0\alu_div0_logical_op__insn[31:0] + end + attribute \src "libresoc.v:121128.3-121129.39" + process $proc$libresoc.v:121128$4844 + assign { } { } + assign $0\req_l_r_req[3:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[3:0] + end + attribute \src "libresoc.v:121130.3-121131.39" + process $proc$libresoc.v:121130$4845 + assign { } { } + assign $0\req_l_s_req[3:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[3:0] + end + attribute \src "libresoc.v:121132.3-121133.39" + process $proc$libresoc.v:121132$4846 + assign { } { } + assign $0\src_l_r_src[2:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[2:0] + end + attribute \src "libresoc.v:121134.3-121135.39" + process $proc$libresoc.v:121134$4847 + assign { } { } + assign $0\src_l_s_src[2:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[2:0] + end + attribute \src "libresoc.v:121136.3-121137.39" + process $proc$libresoc.v:121136$4848 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:121138.3-121139.39" + process $proc$libresoc.v:121138$4849 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:121140.3-121141.39" + process $proc$libresoc.v:121140$4850 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:121142.3-121143.39" + process $proc$libresoc.v:121142$4851 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:121144.3-121145.41" + process $proc$libresoc.v:121144$4852 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:121146.3-121147.41" + process $proc$libresoc.v:121146$4853 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:121148.3-121149.37" + process $proc$libresoc.v:121148$4854 + assign { } { } + assign $0\prev_wr_go[3:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[3:0] + end + attribute \src "libresoc.v:121150.3-121151.40" + process $proc$libresoc.v:121150$4855 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_div0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "libresoc.v:121152.3-121153.25" + process $proc$libresoc.v:121152$4856 + assign { } { } + assign $0\all_rd_dly[0:0] \$10 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "libresoc.v:121239.3-121248.6" + process $proc$libresoc.v:121239$4857 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:121240.5-121240.29" switch \initial - attribute \src "libresoc.v:27528.9-27528.17" + attribute \src "libresoc.v:121240.9-121240.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$54 attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + assign $1\req_done[0:0] 1'1 case - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000000 + assign $1\req_done[0:0] \$46 end sync always - update \dec31_dec_sub21_function_unit $0\dec31_dec_sub21_function_unit[11:0] + update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:27576.3-27624.6" - process $proc$libresoc.v:27576$608 + attribute \src "libresoc.v:121249.3-121257.6" + process $proc$libresoc.v:121249$4858 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_ldst_len[3:0] $1\dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:27577.5-27577.29" + assign $0\rok_l_s_rdok$next[0:0]$4859 $1\rok_l_s_rdok$next[0:0]$4860 + attribute \src "libresoc.v:121250.5-121250.29" switch \initial - attribute \src "libresoc.v:27577.9-27577.17" + attribute \src "libresoc.v:121250.9-121250.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0010 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + assign $1\rok_l_s_rdok$next[0:0]$4860 1'0 case - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0000 + assign $1\rok_l_s_rdok$next[0:0]$4860 \cu_issue_i end sync always - update \dec31_dec_sub21_ldst_len $0\dec31_dec_sub21_ldst_len[3:0] + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$4859 end - attribute \src "libresoc.v:27625.3-27673.6" - process $proc$libresoc.v:27625$609 + attribute \src "libresoc.v:121258.3-121266.6" + process $proc$libresoc.v:121258$4861 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_upd[1:0] $1\dec31_dec_sub21_upd[1:0] - attribute \src "libresoc.v:27626.5-27626.29" + assign $0\rok_l_r_rdok$next[0:0]$4862 $1\rok_l_r_rdok$next[0:0]$4863 + attribute \src "libresoc.v:121259.5-121259.29" switch \initial - attribute \src "libresoc.v:27626.9-27626.17" + attribute \src "libresoc.v:121259.9-121259.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 + assign $1\rok_l_r_rdok$next[0:0]$4863 1'1 case - assign $1\dec31_dec_sub21_upd[1:0] 2'00 + assign $1\rok_l_r_rdok$next[0:0]$4863 \$64 end sync always - update \dec31_dec_sub21_upd $0\dec31_dec_sub21_upd[1:0] + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$4862 end - attribute \src "libresoc.v:27674.3-27722.6" - process $proc$libresoc.v:27674$610 + attribute \src "libresoc.v:121267.3-121275.6" + process $proc$libresoc.v:121267$4864 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_rc_sel[1:0] $1\dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:27675.5-27675.29" + assign $0\rst_l_s_rst$next[0:0]$4865 $1\rst_l_s_rst$next[0:0]$4866 + attribute \src "libresoc.v:121268.5-121268.29" switch \initial - attribute \src "libresoc.v:27675.9-27675.17" + attribute \src "libresoc.v:121268.9-121268.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + assign $1\rst_l_s_rst$next[0:0]$4866 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$4866 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$4865 + end + attribute \src "libresoc.v:121276.3-121284.6" + process $proc$libresoc.v:121276$4867 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$4868 $1\rst_l_r_rst$next[0:0]$4869 + attribute \src "libresoc.v:121277.5-121277.29" + switch \initial + attribute \src "libresoc.v:121277.9-121277.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + assign $1\rst_l_r_rst$next[0:0]$4869 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$4869 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$4868 + end + attribute \src "libresoc.v:121285.3-121293.6" + process $proc$libresoc.v:121285$4870 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$4871 $1\opc_l_s_opc$next[0:0]$4872 + attribute \src "libresoc.v:121286.5-121286.29" + switch \initial + attribute \src "libresoc.v:121286.9-121286.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + assign $1\opc_l_s_opc$next[0:0]$4872 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$4872 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$4871 + end + attribute \src "libresoc.v:121294.3-121302.6" + process $proc$libresoc.v:121294$4873 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$4874 $1\opc_l_r_opc$next[0:0]$4875 + attribute \src "libresoc.v:121295.5-121295.29" + switch \initial + attribute \src "libresoc.v:121295.9-121295.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + assign $1\opc_l_r_opc$next[0:0]$4875 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$4875 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$4874 + end + attribute \src "libresoc.v:121303.3-121311.6" + process $proc$libresoc.v:121303$4876 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[2:0]$4877 $1\src_l_s_src$next[2:0]$4878 + attribute \src "libresoc.v:121304.5-121304.29" + switch \initial + attribute \src "libresoc.v:121304.9-121304.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + assign $1\src_l_s_src$next[2:0]$4878 3'000 + case + assign $1\src_l_s_src$next[2:0]$4878 { \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$4877 + end + attribute \src "libresoc.v:121312.3-121320.6" + process $proc$libresoc.v:121312$4879 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[2:0]$4880 $1\src_l_r_src$next[2:0]$4881 + attribute \src "libresoc.v:121313.5-121313.29" + switch \initial + attribute \src "libresoc.v:121313.9-121313.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + assign $1\src_l_r_src$next[2:0]$4881 3'111 case - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + assign $1\src_l_r_src$next[2:0]$4881 \reset_r end sync always - update \dec31_dec_sub21_rc_sel $0\dec31_dec_sub21_rc_sel[1:0] + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$4880 end - attribute \src "libresoc.v:27723.3-27771.6" - process $proc$libresoc.v:27723$611 + attribute \src "libresoc.v:121321.3-121329.6" + process $proc$libresoc.v:121321$4882 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_cry_in[1:0] $1\dec31_dec_sub21_cry_in[1:0] - attribute \src "libresoc.v:27724.5-27724.29" + assign $0\req_l_s_req$next[3:0]$4883 $1\req_l_s_req$next[3:0]$4884 + attribute \src "libresoc.v:121322.5-121322.29" switch \initial - attribute \src "libresoc.v:27724.9-27724.17" + attribute \src "libresoc.v:121322.9-121322.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + assign $1\req_l_s_req$next[3:0]$4884 4'0000 case - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + assign $1\req_l_s_req$next[3:0]$4884 \$66 end sync always - update \dec31_dec_sub21_cry_in $0\dec31_dec_sub21_cry_in[1:0] + update \req_l_s_req$next $0\req_l_s_req$next[3:0]$4883 end - attribute \src "libresoc.v:27772.3-27820.6" - process $proc$libresoc.v:27772$612 + attribute \src "libresoc.v:121330.3-121338.6" + process $proc$libresoc.v:121330$4885 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_inv_a[0:0] $1\dec31_dec_sub21_inv_a[0:0] - attribute \src "libresoc.v:27773.5-27773.29" + assign $0\req_l_r_req$next[3:0]$4886 $1\req_l_r_req$next[3:0]$4887 + attribute \src "libresoc.v:121331.5-121331.29" switch \initial - attribute \src "libresoc.v:27773.9-27773.17" + attribute \src "libresoc.v:121331.9-121331.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + assign $1\req_l_r_req$next[3:0]$4887 4'1111 case - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + assign $1\req_l_r_req$next[3:0]$4887 \$68 end sync always - update \dec31_dec_sub21_inv_a $0\dec31_dec_sub21_inv_a[0:0] + update \req_l_r_req$next $0\req_l_r_req$next[3:0]$4886 end - attribute \src "libresoc.v:27821.3-27869.6" - process $proc$libresoc.v:27821$613 + attribute \src "libresoc.v:121339.3-121377.6" + process $proc$libresoc.v:121339$4888 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_inv_out[0:0] $1\dec31_dec_sub21_inv_out[0:0] - attribute \src "libresoc.v:27822.5-27822.29" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_div0_logical_op__data_len$next[3:0]$4889 $1\alu_div0_logical_op__data_len$next[3:0]$4907 + assign $0\alu_div0_logical_op__fn_unit$next[11:0]$4890 $1\alu_div0_logical_op__fn_unit$next[11:0]$4908 + assign { } { } + assign { } { } + assign $0\alu_div0_logical_op__input_carry$next[1:0]$4893 $1\alu_div0_logical_op__input_carry$next[1:0]$4911 + assign $0\alu_div0_logical_op__insn$next[31:0]$4894 $1\alu_div0_logical_op__insn$next[31:0]$4912 + assign $0\alu_div0_logical_op__insn_type$next[6:0]$4895 $1\alu_div0_logical_op__insn_type$next[6:0]$4913 + assign $0\alu_div0_logical_op__invert_in$next[0:0]$4896 $1\alu_div0_logical_op__invert_in$next[0:0]$4914 + assign $0\alu_div0_logical_op__invert_out$next[0:0]$4897 $1\alu_div0_logical_op__invert_out$next[0:0]$4915 + assign $0\alu_div0_logical_op__is_32bit$next[0:0]$4898 $1\alu_div0_logical_op__is_32bit$next[0:0]$4916 + assign $0\alu_div0_logical_op__is_signed$next[0:0]$4899 $1\alu_div0_logical_op__is_signed$next[0:0]$4917 + assign { } { } + assign { } { } + assign $0\alu_div0_logical_op__output_carry$next[0:0]$4902 $1\alu_div0_logical_op__output_carry$next[0:0]$4920 + assign { } { } + assign { } { } + assign $0\alu_div0_logical_op__write_cr0$next[0:0]$4905 $1\alu_div0_logical_op__write_cr0$next[0:0]$4923 + assign $0\alu_div0_logical_op__zero_a$next[0:0]$4906 $1\alu_div0_logical_op__zero_a$next[0:0]$4924 + assign $0\alu_div0_logical_op__imm_data__data$next[63:0]$4891 $2\alu_div0_logical_op__imm_data__data$next[63:0]$4925 + assign $0\alu_div0_logical_op__imm_data__ok$next[0:0]$4892 $2\alu_div0_logical_op__imm_data__ok$next[0:0]$4926 + assign $0\alu_div0_logical_op__oe__oe$next[0:0]$4900 $2\alu_div0_logical_op__oe__oe$next[0:0]$4927 + assign $0\alu_div0_logical_op__oe__ok$next[0:0]$4901 $2\alu_div0_logical_op__oe__ok$next[0:0]$4928 + assign $0\alu_div0_logical_op__rc__ok$next[0:0]$4903 $2\alu_div0_logical_op__rc__ok$next[0:0]$4929 + assign $0\alu_div0_logical_op__rc__rc$next[0:0]$4904 $2\alu_div0_logical_op__rc__rc$next[0:0]$4930 + attribute \src "libresoc.v:121340.5-121340.29" switch \initial - attribute \src "libresoc.v:27822.9-27822.17" + attribute \src "libresoc.v:121340.9-121340.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub21_inv_out $0\dec31_dec_sub21_inv_out[0:0] - end - attribute \src "libresoc.v:27870.3-27918.6" - process $proc$libresoc.v:27870$614 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_cry_out[0:0] $1\dec31_dec_sub21_cry_out[0:0] - attribute \src "libresoc.v:27871.5-27871.29" - switch \initial - attribute \src "libresoc.v:27871.9-27871.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + assign { $1\alu_div0_logical_op__insn$next[31:0]$4912 $1\alu_div0_logical_op__data_len$next[3:0]$4907 $1\alu_div0_logical_op__is_signed$next[0:0]$4917 $1\alu_div0_logical_op__is_32bit$next[0:0]$4916 $1\alu_div0_logical_op__output_carry$next[0:0]$4920 $1\alu_div0_logical_op__write_cr0$next[0:0]$4923 $1\alu_div0_logical_op__invert_out$next[0:0]$4915 $1\alu_div0_logical_op__input_carry$next[1:0]$4911 $1\alu_div0_logical_op__zero_a$next[0:0]$4924 $1\alu_div0_logical_op__invert_in$next[0:0]$4914 $1\alu_div0_logical_op__oe__ok$next[0:0]$4919 $1\alu_div0_logical_op__oe__oe$next[0:0]$4918 $1\alu_div0_logical_op__rc__ok$next[0:0]$4921 $1\alu_div0_logical_op__rc__rc$next[0:0]$4922 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$4910 $1\alu_div0_logical_op__imm_data__data$next[63:0]$4909 $1\alu_div0_logical_op__fn_unit$next[11:0]$4908 $1\alu_div0_logical_op__insn_type$next[6:0]$4913 } { \oper_i_alu_div0__insn \oper_i_alu_div0__data_len \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_32bit \oper_i_alu_div0__output_carry \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__invert_out \oper_i_alu_div0__input_carry \oper_i_alu_div0__zero_a \oper_i_alu_div0__invert_in \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__oe \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__rc \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__fn_unit \oper_i_alu_div0__insn_type } + case + assign $1\alu_div0_logical_op__data_len$next[3:0]$4907 \alu_div0_logical_op__data_len + assign $1\alu_div0_logical_op__fn_unit$next[11:0]$4908 \alu_div0_logical_op__fn_unit + assign $1\alu_div0_logical_op__imm_data__data$next[63:0]$4909 \alu_div0_logical_op__imm_data__data + assign $1\alu_div0_logical_op__imm_data__ok$next[0:0]$4910 \alu_div0_logical_op__imm_data__ok + assign $1\alu_div0_logical_op__input_carry$next[1:0]$4911 \alu_div0_logical_op__input_carry + assign $1\alu_div0_logical_op__insn$next[31:0]$4912 \alu_div0_logical_op__insn + assign $1\alu_div0_logical_op__insn_type$next[6:0]$4913 \alu_div0_logical_op__insn_type + assign $1\alu_div0_logical_op__invert_in$next[0:0]$4914 \alu_div0_logical_op__invert_in + assign $1\alu_div0_logical_op__invert_out$next[0:0]$4915 \alu_div0_logical_op__invert_out + assign $1\alu_div0_logical_op__is_32bit$next[0:0]$4916 \alu_div0_logical_op__is_32bit + assign $1\alu_div0_logical_op__is_signed$next[0:0]$4917 \alu_div0_logical_op__is_signed + assign $1\alu_div0_logical_op__oe__oe$next[0:0]$4918 \alu_div0_logical_op__oe__oe + assign $1\alu_div0_logical_op__oe__ok$next[0:0]$4919 \alu_div0_logical_op__oe__ok + assign $1\alu_div0_logical_op__output_carry$next[0:0]$4920 \alu_div0_logical_op__output_carry + assign $1\alu_div0_logical_op__rc__ok$next[0:0]$4921 \alu_div0_logical_op__rc__ok + assign $1\alu_div0_logical_op__rc__rc$next[0:0]$4922 \alu_div0_logical_op__rc__rc + assign $1\alu_div0_logical_op__write_cr0$next[0:0]$4923 \alu_div0_logical_op__write_cr0 + assign $1\alu_div0_logical_op__zero_a$next[0:0]$4924 \alu_div0_logical_op__zero_a + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$4925 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$4926 1'0 + assign $2\alu_div0_logical_op__rc__rc$next[0:0]$4930 1'0 + assign $2\alu_div0_logical_op__rc__ok$next[0:0]$4929 1'0 + assign $2\alu_div0_logical_op__oe__oe$next[0:0]$4927 1'0 + assign $2\alu_div0_logical_op__oe__ok$next[0:0]$4928 1'0 case - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$4925 $1\alu_div0_logical_op__imm_data__data$next[63:0]$4909 + assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$4926 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$4910 + assign $2\alu_div0_logical_op__oe__oe$next[0:0]$4927 $1\alu_div0_logical_op__oe__oe$next[0:0]$4918 + assign $2\alu_div0_logical_op__oe__ok$next[0:0]$4928 $1\alu_div0_logical_op__oe__ok$next[0:0]$4919 + assign $2\alu_div0_logical_op__rc__ok$next[0:0]$4929 $1\alu_div0_logical_op__rc__ok$next[0:0]$4921 + assign $2\alu_div0_logical_op__rc__rc$next[0:0]$4930 $1\alu_div0_logical_op__rc__rc$next[0:0]$4922 end sync always - update \dec31_dec_sub21_cry_out $0\dec31_dec_sub21_cry_out[0:0] + update \alu_div0_logical_op__data_len$next $0\alu_div0_logical_op__data_len$next[3:0]$4889 + update \alu_div0_logical_op__fn_unit$next $0\alu_div0_logical_op__fn_unit$next[11:0]$4890 + update \alu_div0_logical_op__imm_data__data$next $0\alu_div0_logical_op__imm_data__data$next[63:0]$4891 + update \alu_div0_logical_op__imm_data__ok$next $0\alu_div0_logical_op__imm_data__ok$next[0:0]$4892 + update \alu_div0_logical_op__input_carry$next $0\alu_div0_logical_op__input_carry$next[1:0]$4893 + update \alu_div0_logical_op__insn$next $0\alu_div0_logical_op__insn$next[31:0]$4894 + update \alu_div0_logical_op__insn_type$next $0\alu_div0_logical_op__insn_type$next[6:0]$4895 + update \alu_div0_logical_op__invert_in$next $0\alu_div0_logical_op__invert_in$next[0:0]$4896 + update \alu_div0_logical_op__invert_out$next $0\alu_div0_logical_op__invert_out$next[0:0]$4897 + update \alu_div0_logical_op__is_32bit$next $0\alu_div0_logical_op__is_32bit$next[0:0]$4898 + update \alu_div0_logical_op__is_signed$next $0\alu_div0_logical_op__is_signed$next[0:0]$4899 + update \alu_div0_logical_op__oe__oe$next $0\alu_div0_logical_op__oe__oe$next[0:0]$4900 + update \alu_div0_logical_op__oe__ok$next $0\alu_div0_logical_op__oe__ok$next[0:0]$4901 + update \alu_div0_logical_op__output_carry$next $0\alu_div0_logical_op__output_carry$next[0:0]$4902 + update \alu_div0_logical_op__rc__ok$next $0\alu_div0_logical_op__rc__ok$next[0:0]$4903 + update \alu_div0_logical_op__rc__rc$next $0\alu_div0_logical_op__rc__rc$next[0:0]$4904 + update \alu_div0_logical_op__write_cr0$next $0\alu_div0_logical_op__write_cr0$next[0:0]$4905 + update \alu_div0_logical_op__zero_a$next $0\alu_div0_logical_op__zero_a$next[0:0]$4906 end - attribute \src "libresoc.v:27919.3-27967.6" - process $proc$libresoc.v:27919$615 + attribute \src "libresoc.v:121378.3-121399.6" + process $proc$libresoc.v:121378$4931 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_br[0:0] $1\dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:27920.5-27920.29" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$4932 $2\data_r0__o$next[63:0]$4936 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$4933 $3\data_r0__o_ok$next[0:0]$4938 + attribute \src "libresoc.v:121379.5-121379.29" switch \initial - attribute \src "libresoc.v:27920.9-27920.17" + attribute \src "libresoc.v:121379.9-121379.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 + assign { $1\data_r0__o_ok$next[0:0]$4935 $1\data_r0__o$next[63:0]$4934 } { \o_ok \alu_div0_o } + case + assign $1\data_r0__o$next[63:0]$4934 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$4935 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 + assign { $2\data_r0__o_ok$next[0:0]$4937 $2\data_r0__o$next[63:0]$4936 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$4936 $1\data_r0__o$next[63:0]$4934 + assign $2\data_r0__o_ok$next[0:0]$4937 $1\data_r0__o_ok$next[0:0]$4935 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 + assign $3\data_r0__o_ok$next[0:0]$4938 1'0 case - assign $1\dec31_dec_sub21_br[0:0] 1'0 + assign $3\data_r0__o_ok$next[0:0]$4938 $2\data_r0__o_ok$next[0:0]$4937 end sync always - update \dec31_dec_sub21_br $0\dec31_dec_sub21_br[0:0] + update \data_r0__o$next $0\data_r0__o$next[63:0]$4932 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$4933 end - attribute \src "libresoc.v:27968.3-28016.6" - process $proc$libresoc.v:27968$616 + attribute \src "libresoc.v:121400.3-121421.6" + process $proc$libresoc.v:121400$4939 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_sgn_ext[0:0] $1\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:27969.5-27969.29" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__cr_a$next[3:0]$4940 $2\data_r1__cr_a$next[3:0]$4944 + assign { } { } + assign $0\data_r1__cr_a_ok$next[0:0]$4941 $3\data_r1__cr_a_ok$next[0:0]$4946 + attribute \src "libresoc.v:121401.5-121401.29" switch \initial - attribute \src "libresoc.v:27969.9-27969.17" + attribute \src "libresoc.v:121401.9-121401.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + assign { $1\data_r1__cr_a_ok$next[0:0]$4943 $1\data_r1__cr_a$next[3:0]$4942 } { \cr_a_ok \alu_div0_cr_a } + case + assign $1\data_r1__cr_a$next[3:0]$4942 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$4943 \data_r1__cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + assign { $2\data_r1__cr_a_ok$next[0:0]$4945 $2\data_r1__cr_a$next[3:0]$4944 } 5'00000 + case + assign $2\data_r1__cr_a$next[3:0]$4944 $1\data_r1__cr_a$next[3:0]$4942 + assign $2\data_r1__cr_a_ok$next[0:0]$4945 $1\data_r1__cr_a_ok$next[0:0]$4943 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + assign $3\data_r1__cr_a_ok$next[0:0]$4946 1'0 case - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + assign $3\data_r1__cr_a_ok$next[0:0]$4946 $2\data_r1__cr_a_ok$next[0:0]$4945 end sync always - update \dec31_dec_sub21_sgn_ext $0\dec31_dec_sub21_sgn_ext[0:0] + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$4940 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$4941 end - attribute \src "libresoc.v:28017.3-28065.6" - process $proc$libresoc.v:28017$617 + attribute \src "libresoc.v:121422.3-121443.6" + process $proc$libresoc.v:121422$4947 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_rsrv[0:0] $1\dec31_dec_sub21_rsrv[0:0] - attribute \src "libresoc.v:28018.5-28018.29" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__xer_ov$next[1:0]$4948 $2\data_r2__xer_ov$next[1:0]$4952 + assign { } { } + assign $0\data_r2__xer_ov_ok$next[0:0]$4949 $3\data_r2__xer_ov_ok$next[0:0]$4954 + attribute \src "libresoc.v:121423.5-121423.29" switch \initial - attribute \src "libresoc.v:28018.9-28018.17" + attribute \src "libresoc.v:121423.9-121423.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + assign { $1\data_r2__xer_ov_ok$next[0:0]$4951 $1\data_r2__xer_ov$next[1:0]$4950 } { \xer_ov_ok \alu_div0_xer_ov } + case + assign $1\data_r2__xer_ov$next[1:0]$4950 \data_r2__xer_ov + assign $1\data_r2__xer_ov_ok$next[0:0]$4951 \data_r2__xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + assign { $2\data_r2__xer_ov_ok$next[0:0]$4953 $2\data_r2__xer_ov$next[1:0]$4952 } 3'000 + case + assign $2\data_r2__xer_ov$next[1:0]$4952 $1\data_r2__xer_ov$next[1:0]$4950 + assign $2\data_r2__xer_ov_ok$next[0:0]$4953 $1\data_r2__xer_ov_ok$next[0:0]$4951 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + assign $3\data_r2__xer_ov_ok$next[0:0]$4954 1'0 case - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + assign $3\data_r2__xer_ov_ok$next[0:0]$4954 $2\data_r2__xer_ov_ok$next[0:0]$4953 end sync always - update \dec31_dec_sub21_rsrv $0\dec31_dec_sub21_rsrv[0:0] + update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$4948 + update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$4949 end - attribute \src "libresoc.v:28066.3-28114.6" - process $proc$libresoc.v:28066$618 + attribute \src "libresoc.v:121444.3-121465.6" + process $proc$libresoc.v:121444$4955 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_internal_op[6:0] $1\dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:28067.5-28067.29" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r3__xer_so$next[0:0]$4956 $2\data_r3__xer_so$next[0:0]$4960 + assign { } { } + assign $0\data_r3__xer_so_ok$next[0:0]$4957 $3\data_r3__xer_so_ok$next[0:0]$4962 + attribute \src "libresoc.v:121445.5-121445.29" switch \initial - attribute \src "libresoc.v:28067.9-28067.17" + attribute \src "libresoc.v:121445.9-121445.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + assign { $1\data_r3__xer_so_ok$next[0:0]$4959 $1\data_r3__xer_so$next[0:0]$4958 } { \xer_so_ok \alu_div0_xer_so } + case + assign $1\data_r3__xer_so$next[0:0]$4958 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$4959 \data_r3__xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + assign { $2\data_r3__xer_so_ok$next[0:0]$4961 $2\data_r3__xer_so$next[0:0]$4960 } 2'00 + case + assign $2\data_r3__xer_so$next[0:0]$4960 $1\data_r3__xer_so$next[0:0]$4958 + assign $2\data_r3__xer_so_ok$next[0:0]$4961 $1\data_r3__xer_so_ok$next[0:0]$4959 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + assign $3\data_r3__xer_so_ok$next[0:0]$4962 1'0 case - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0000000 + assign $3\data_r3__xer_so_ok$next[0:0]$4962 $2\data_r3__xer_so_ok$next[0:0]$4961 end sync always - update \dec31_dec_sub21_internal_op $0\dec31_dec_sub21_internal_op[6:0] + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$4956 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$4957 end - attribute \src "libresoc.v:28115.3-28163.6" - process $proc$libresoc.v:28115$619 + attribute \src "libresoc.v:121466.3-121475.6" + process $proc$libresoc.v:121466$4963 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_is_32b[0:0] $1\dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:28116.5-28116.29" + assign $0\src_r0$next[63:0]$4964 $1\src_r0$next[63:0]$4965 + attribute \src "libresoc.v:121467.5-121467.29" switch \initial - attribute \src "libresoc.v:28116.9-28116.17" + attribute \src "libresoc.v:121467.9-121467.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_sel attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + assign $1\src_r0$next[63:0]$4965 \src_or_imm + case + assign $1\src_r0$next[63:0]$4965 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$4964 + end + attribute \src "libresoc.v:121476.3-121485.6" + process $proc$libresoc.v:121476$4966 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$4967 $1\src_r1$next[63:0]$4968 + attribute \src "libresoc.v:121477.5-121477.29" + switch \initial + attribute \src "libresoc.v:121477.9-121477.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_sel$82 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + assign $1\src_r1$next[63:0]$4968 \src_or_imm$85 case - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + assign $1\src_r1$next[63:0]$4968 \src_r1 end sync always - update \dec31_dec_sub21_is_32b $0\dec31_dec_sub21_is_32b[0:0] + update \src_r1$next $0\src_r1$next[63:0]$4967 end - attribute \src "libresoc.v:28164.3-28212.6" - process $proc$libresoc.v:28164$620 + attribute \src "libresoc.v:121486.3-121495.6" + process $proc$libresoc.v:121486$4969 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_sgn[0:0] $1\dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:28165.5-28165.29" + assign $0\src_r2$next[0:0]$4970 $1\src_r2$next[0:0]$4971 + attribute \src "libresoc.v:121487.5-121487.29" switch \initial - attribute \src "libresoc.v:28165.9-28165.17" + attribute \src "libresoc.v:121487.9-121487.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [2] attribute \src "libresoc.v:0.0-0.0" - case 5'11010 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\src_r2$next[0:0]$4971 \src3_i + case + assign $1\src_r2$next[0:0]$4971 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[0:0]$4970 + end + attribute \src "libresoc.v:121496.3-121504.6" + process $proc$libresoc.v:121496$4972 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$4973 $1\alui_l_r_alui$next[0:0]$4974 + attribute \src "libresoc.v:121497.5-121497.29" + switch \initial + attribute \src "libresoc.v:121497.9-121497.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 5'11011 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\alui_l_r_alui$next[0:0]$4974 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$4974 \$94 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$4973 + end + attribute \src "libresoc.v:121505.3-121513.6" + process $proc$libresoc.v:121505$4975 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$4976 $1\alu_l_r_alu$next[0:0]$4977 + attribute \src "libresoc.v:121506.5-121506.29" + switch \initial + attribute \src "libresoc.v:121506.9-121506.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 5'00001 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\alu_l_r_alu$next[0:0]$4977 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$4977 \$96 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$4976 + end + attribute \src "libresoc.v:121514.3-121523.6" + process $proc$libresoc.v:121514$4978 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:121515.5-121515.29" + switch \initial + attribute \src "libresoc.v:121515.9-121515.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$122 attribute \src "libresoc.v:0.0-0.0" - case 5'00000 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dest1_o[63:0] \data_r0__o + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "libresoc.v:121524.3-121533.6" + process $proc$libresoc.v:121524$4979 + assign { } { } + assign { } { } + assign $0\dest2_o[3:0] $1\dest2_o[3:0] + attribute \src "libresoc.v:121525.5-121525.29" + switch \initial + attribute \src "libresoc.v:121525.9-121525.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$124 attribute \src "libresoc.v:0.0-0.0" - case 5'11001 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dest2_o[3:0] \data_r1__cr_a + case + assign $1\dest2_o[3:0] 4'0000 + end + sync always + update \dest2_o $0\dest2_o[3:0] + end + attribute \src "libresoc.v:121534.3-121543.6" + process $proc$libresoc.v:121534$4980 + assign { } { } + assign { } { } + assign $0\dest3_o[1:0] $1\dest3_o[1:0] + attribute \src "libresoc.v:121535.5-121535.29" + switch \initial + attribute \src "libresoc.v:121535.9-121535.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$126 attribute \src "libresoc.v:0.0-0.0" - case 5'01011 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dest3_o[1:0] \data_r2__xer_ov + case + assign $1\dest3_o[1:0] 2'00 + end + sync always + update \dest3_o $0\dest3_o[1:0] + end + attribute \src "libresoc.v:121544.3-121553.6" + process $proc$libresoc.v:121544$4981 + assign { } { } + assign { } { } + assign $0\dest4_o[0:0] $1\dest4_o[0:0] + attribute \src "libresoc.v:121545.5-121545.29" + switch \initial + attribute \src "libresoc.v:121545.9-121545.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$128 attribute \src "libresoc.v:0.0-0.0" - case 5'01010 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dest4_o[0:0] \data_r3__xer_so + case + assign $1\dest4_o[0:0] 1'0 + end + sync always + update \dest4_o $0\dest4_o[0:0] + end + attribute \src "libresoc.v:121554.3-121562.6" + process $proc$libresoc.v:121554$4982 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[3:0]$4983 $1\prev_wr_go$next[3:0]$4984 + attribute \src "libresoc.v:121555.5-121555.29" + switch \initial + attribute \src "libresoc.v:121555.9-121555.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 5'11000 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\prev_wr_go$next[3:0]$4984 4'0000 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\B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \i_q_bits_known + connect \B 1'1 + connect \Y $add$libresoc.v:121648$5030_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" + cell $ge $ge$libresoc.v:121649$5031 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \i_q_bits_known + connect \B 7'1000000 + connect \Y $ge$libresoc.v:121649$5031_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" + cell $ge $ge$libresoc.v:121653$5035 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \i_q_bits_known + connect \B 7'1000000 + connect \Y $ge$libresoc.v:121653$5035_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:70" + cell $not $not$libresoc.v:121652$5034 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect 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$proc$libresoc.v:121654$5036 + assign { } { } + assign $0\value[127:0] $1\value[127:0] + attribute \src "libresoc.v:121655.5-121655.29" + switch \initial + attribute \src "libresoc.v:121655.9-121655.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:72" + switch \next_quotient_bit attribute \src "libresoc.v:0.0-0.0" - case 5'11110 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\value[127:0] \difference attribute \src "libresoc.v:0.0-0.0" - case 5'11111 + case assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\value[127:0] \i_dividend_quotient + end + sync always + update \value $0\value[127:0] + end + attribute \src "libresoc.v:121666.3-121677.6" + process $proc$libresoc.v:121666$5037 + assign { } { } + assign $0\o_q_bits_known[6:0] $1\o_q_bits_known[6:0] + attribute \src "libresoc.v:121667.5-121667.29" + switch \initial + attribute \src "libresoc.v:121667.9-121667.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:77" + switch \$8 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\o_q_bits_known[6:0] \i_q_bits_known attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\o_q_bits_known[6:0] \$10 [6:0] + end + sync always + update \o_q_bits_known $0\o_q_bits_known[6:0] + end + attribute \src "libresoc.v:121678.3-121689.6" + process $proc$libresoc.v:121678$5038 + assign { } { } + assign $0\o_dividend_quotient[127:0] $1\o_dividend_quotient[127:0] + attribute \src "libresoc.v:121679.5-121679.29" + switch \initial + attribute \src "libresoc.v:121679.9-121679.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:77" + switch \$13 attribute \src "libresoc.v:0.0-0.0" - case 5'11101 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \trap_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 16 \trap_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 3 \trap_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 17 \trap_op__insn$4 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \trap_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 15 \trap_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \trap_op__is_32bit$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 9 \trap_op__ldst_exc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 output 23 \trap_op__ldst_exc$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 4 \trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 18 \trap_op__msr$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 8 \trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 22 \trap_op__trapaddr$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 7 \trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 output 21 \trap_op__traptype$8 + connect \fast2$14 \fast2 + connect \fast1$13 \fast1 + connect \rb$12 \rb + connect \ra$11 \ra + connect { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } + connect \muxid$1 \muxid +end +attribute \src "libresoc.v:121939.1-122110.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fast" +attribute \generator "nMigen" +module \fast + attribute \src "libresoc.v:122034.3-122040.6" + wire width 3 $0$memwr$\memory$libresoc.v:122038$5048_ADDR[2:0]$5056 + attribute \src "libresoc.v:122034.3-122040.6" + wire width 64 $0$memwr$\memory$libresoc.v:122038$5048_DATA[63:0]$5057 + attribute \src "libresoc.v:122034.3-122040.6" + wire width 64 $0$memwr$\memory$libresoc.v:122038$5048_EN[63:0]$5058 + attribute \src "libresoc.v:122034.3-122040.6" + wire width 3 $0$memwr$\memory$libresoc.v:122039$5049_ADDR[2:0]$5059 + attribute \src "libresoc.v:122034.3-122040.6" + wire width 64 $0$memwr$\memory$libresoc.v:122039$5049_DATA[63:0]$5060 + attribute \src "libresoc.v:122034.3-122040.6" + wire width 64 $0$memwr$\memory$libresoc.v:122039$5049_EN[63:0]$5061 + attribute \src "libresoc.v:122034.3-122040.6" + wire width 3 $0\_0_[2:0] + attribute \src "libresoc.v:122034.3-122040.6" + wire width 3 $0\_1_[2:0] + attribute \src "libresoc.v:122034.3-122040.6" + wire width 3 $0\_2_[2:0] + attribute \src "libresoc.v:121940.7-121940.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:122091.3-122100.6" + wire width 64 $0\issue__data_o[63:0] + attribute \src "libresoc.v:122063.3-122071.6" + wire $0\ren_delay$10$next[0:0]$5070 + attribute \src "libresoc.v:122016.3-122017.43" + wire $0\ren_delay$10[0:0]$5053 + attribute \src "libresoc.v:121991.7-121991.28" + wire $0\ren_delay$10[0:0]$5090 + attribute \src "libresoc.v:122082.3-122090.6" + wire $0\ren_delay$11$next[0:0]$5074 + attribute \src "libresoc.v:122014.3-122015.43" + wire $0\ren_delay$11[0:0]$5051 + attribute \src "libresoc.v:121995.7-121995.28" + wire $0\ren_delay$11[0:0]$5092 + attribute \src "libresoc.v:122044.3-122052.6" + wire $0\ren_delay$next[0:0]$5066 + attribute \src "libresoc.v:122018.3-122019.35" + wire $0\ren_delay[0:0] + attribute \src "libresoc.v:122053.3-122062.6" + wire width 64 $0\src1__data_o[63:0] + attribute \src "libresoc.v:122072.3-122081.6" + wire width 64 $0\src2__data_o[63:0] + attribute \src "libresoc.v:122091.3-122100.6" + wire width 64 $1\issue__data_o[63:0] + attribute \src "libresoc.v:122063.3-122071.6" + wire $1\ren_delay$10$next[0:0]$5071 + attribute \src "libresoc.v:122082.3-122090.6" + wire $1\ren_delay$11$next[0:0]$5075 + attribute \src "libresoc.v:122044.3-122052.6" + wire $1\ren_delay$next[0:0]$5067 + attribute \src "libresoc.v:121989.7-121989.23" + wire $1\ren_delay[0:0] + attribute \src "libresoc.v:122053.3-122062.6" + wire width 64 $1\src1__data_o[63:0] + attribute \src "libresoc.v:122072.3-122081.6" + wire width 64 $1\src2__data_o[63:0] + attribute \src "libresoc.v:122041.26-122041.32" + wire width 64 $memrd$\memory$libresoc.v:122041$5062_DATA + attribute \src "libresoc.v:122042.30-122042.36" + wire width 64 $memrd$\memory$libresoc.v:122042$5063_DATA + attribute \src "libresoc.v:122043.30-122043.36" + wire width 64 $memrd$\memory$libresoc.v:122043$5064_DATA + attribute \src "libresoc.v:0.0-0.0" + wire width 3 $memwr$\memory$libresoc.v:122038$5048_ADDR + attribute \src "libresoc.v:0.0-0.0" + wire width 64 $memwr$\memory$libresoc.v:122038$5048_DATA + attribute \src "libresoc.v:0.0-0.0" + wire width 64 $memwr$\memory$libresoc.v:122038$5048_EN + attribute \src "libresoc.v:0.0-0.0" + wire width 3 $memwr$\memory$libresoc.v:122039$5049_ADDR + attribute \src "libresoc.v:0.0-0.0" + wire width 64 $memwr$\memory$libresoc.v:122039$5049_DATA + attribute \src "libresoc.v:0.0-0.0" + wire width 64 $memwr$\memory$libresoc.v:122039$5049_EN + attribute \src "libresoc.v:122031.13-122031.16" + wire width 3 \_0_ + attribute \src "libresoc.v:122032.13-122032.16" + wire width 3 \_1_ + attribute \src "libresoc.v:122033.13-122033.16" + wire width 3 \_2_ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 17 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 15 \dest1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 14 \dest1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 16 \dest1__wen + attribute \src "libresoc.v:121940.7-121940.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 2 \issue__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 5 \issue__addr$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 7 \issue__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 4 \issue__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 3 \issue__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \issue__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 3 \memory_r_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 3 \memory_r_addr$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 3 \memory_r_addr$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 3 \memory_w_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 3 \memory_w_addr$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 64 \memory_w_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 64 \memory_w_data$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire \memory_w_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire \memory_w_en$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 9 \src1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 8 \src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 12 \src2__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 11 \src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 13 \src2__ren + attribute \src "libresoc.v:122020.14-122020.20" + memory width 64 size 8 \memory + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5077 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5077 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 0 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5078 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5078 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 1 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5079 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5079 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 2 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5080 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5080 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 3 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5081 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5081 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 4 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5082 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5082 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 5 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5083 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5083 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 6 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5084 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5084 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 7 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:122041.26-122041.32" + cell $memrd $memrd$\memory$libresoc.v:122041$5062 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_0_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:122041$5062_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:122042.30-122042.36" + cell $memrd $memrd$\memory$libresoc.v:122042$5063 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_1_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:122042$5063_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:122043.30-122043.36" + cell $memrd $memrd$\memory$libresoc.v:122043$5064 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_2_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:122043$5064_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:0.0-0.0" + cell $memwr $memwr$\memory$libresoc.v:0$5085 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \PRIORITY 5085 + parameter \WIDTH 64 + connect \ADDR $memwr$\memory$libresoc.v:122038$5048_ADDR + connect \CLK 1'x + connect \DATA $memwr$\memory$libresoc.v:122038$5048_DATA + connect \EN $memwr$\memory$libresoc.v:122038$5048_EN + end + attribute \src "libresoc.v:0.0-0.0" + cell $memwr $memwr$\memory$libresoc.v:0$5086 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \PRIORITY 5086 + parameter \WIDTH 64 + connect \ADDR $memwr$\memory$libresoc.v:122039$5049_ADDR + connect \CLK 1'x + connect \DATA $memwr$\memory$libresoc.v:122039$5049_DATA + connect \EN $memwr$\memory$libresoc.v:122039$5049_EN + end + attribute \src "libresoc.v:0.0-0.0" + process $proc$libresoc.v:0$5093 + sync always + sync init end - attribute \src "libresoc.v:28213.3-28261.6" - process $proc$libresoc.v:28213$621 + attribute \src "libresoc.v:121940.7-121940.20" + process $proc$libresoc.v:121940$5087 assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:121989.7-121989.23" + process $proc$libresoc.v:121989$5088 assign { } { } - assign $0\dec31_dec_sub21_lk[0:0] $1\dec31_dec_sub21_lk[0:0] - attribute \src "libresoc.v:28214.5-28214.29" - switch \initial - attribute \src "libresoc.v:28214.9-28214.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - end + assign $1\ren_delay[0:0] 1'0 sync always - update \dec31_dec_sub21_lk $0\dec31_dec_sub21_lk[0:0] + sync init + update \ren_delay $1\ren_delay[0:0] end - attribute \src "libresoc.v:28262.3-28310.6" - process $proc$libresoc.v:28262$622 + attribute \src "libresoc.v:121991.7-121991.28" + process $proc$libresoc.v:121991$5089 assign { } { } + assign $0\ren_delay$10[0:0]$5090 1'0 + sync always + sync init + update \ren_delay$10 $0\ren_delay$10[0:0]$5090 + end + attribute \src "libresoc.v:121995.7-121995.28" + process $proc$libresoc.v:121995$5091 assign { } { } - assign $0\dec31_dec_sub21_sgl_pipe[0:0] $1\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "libresoc.v:28263.5-28263.29" - switch \initial - attribute \src "libresoc.v:28263.9-28263.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - case - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 - end + assign $0\ren_delay$11[0:0]$5092 1'0 sync always - update \dec31_dec_sub21_sgl_pipe $0\dec31_dec_sub21_sgl_pipe[0:0] + sync init + update \ren_delay$11 $0\ren_delay$11[0:0]$5092 end - attribute \src "libresoc.v:28311.3-28341.6" - process $proc$libresoc.v:28311$623 + attribute \src "libresoc.v:122014.3-122015.43" + process $proc$libresoc.v:122014$5050 assign { } { } + assign $0\ren_delay$11[0:0]$5051 \ren_delay$11$next + sync posedge \coresync_clk + update \ren_delay$11 $0\ren_delay$11[0:0]$5051 + end + attribute \src "libresoc.v:122016.3-122017.43" + process $proc$libresoc.v:122016$5052 assign { } { } - assign $0\dec31_dec_sub21_asmcode[7:0] $1\dec31_dec_sub21_asmcode[7:0] - attribute \src "libresoc.v:28312.5-28312.29" - switch \initial - attribute \src "libresoc.v:28312.9-28312.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010111 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'01100100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'01100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'01101000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'10100111 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'10110000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'10110001 - case - assign $1\dec31_dec_sub21_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub21_asmcode $0\dec31_dec_sub21_asmcode[7:0] + assign $0\ren_delay$10[0:0]$5053 \ren_delay$10$next + sync posedge \coresync_clk + update \ren_delay$10 $0\ren_delay$10[0:0]$5053 end - attribute \src "libresoc.v:28342.3-28390.6" - process $proc$libresoc.v:28342$624 + attribute \src "libresoc.v:122018.3-122019.35" + process $proc$libresoc.v:122018$5054 assign { } { } + assign $0\ren_delay[0:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[0:0] + end + attribute \src "libresoc.v:122034.3-122040.6" + process $proc$libresoc.v:122034$5055 assign { } { } - assign $0\dec31_dec_sub21_form[4:0] $1\dec31_dec_sub21_form[4:0] - attribute \src "libresoc.v:28343.5-28343.29" - switch \initial - attribute \src "libresoc.v:28343.9-28343.17" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\memory$libresoc.v:122039$5049_ADDR[2:0]$5059 3'xxx + assign $0$memwr$\memory$libresoc.v:122039$5049_DATA[63:0]$5060 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:122039$5049_EN[63:0]$5061 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\memory$libresoc.v:122038$5048_ADDR[2:0]$5056 3'xxx + assign $0$memwr$\memory$libresoc.v:122038$5048_DATA[63:0]$5057 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:122038$5048_EN[63:0]$5058 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\_0_[2:0] \src1__addr + assign $0\_1_[2:0] \src2__addr + assign $0\_2_[2:0] \issue__addr + attribute \src "libresoc.v:122038.5-122038.62" + switch \issue__wen + attribute \src "libresoc.v:122038.9-122038.19" case 1'1 + assign $0$memwr$\memory$libresoc.v:122038$5048_ADDR[2:0]$5056 \issue__addr$1 + assign $0$memwr$\memory$libresoc.v:122038$5048_DATA[63:0]$5057 \issue__data_i + assign $0$memwr$\memory$libresoc.v:122038$5048_EN[63:0]$5058 64'1111111111111111111111111111111111111111111111111111111111111111 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:122039.5-122039.58" + switch \dest1__wen + attribute \src "libresoc.v:122039.9-122039.19" + case 1'1 + assign $0$memwr$\memory$libresoc.v:122039$5049_ADDR[2:0]$5059 \dest1__addr + assign $0$memwr$\memory$libresoc.v:122039$5049_DATA[63:0]$5060 \dest1__data_i + assign $0$memwr$\memory$libresoc.v:122039$5049_EN[63:0]$5061 64'1111111111111111111111111111111111111111111111111111111111111111 case - assign $1\dec31_dec_sub21_form[4:0] 5'00000 end - sync always - update \dec31_dec_sub21_form $0\dec31_dec_sub21_form[4:0] - end - attribute \src "libresoc.v:28391.3-28439.6" - process $proc$libresoc.v:28391$625 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_in1_sel[2:0] $1\dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:28392.5-28392.29" + sync posedge \coresync_clk + update \_0_ $0\_0_[2:0] + update \_1_ $0\_1_[2:0] + update \_2_ $0\_2_[2:0] + update $memwr$\memory$libresoc.v:122038$5048_ADDR $0$memwr$\memory$libresoc.v:122038$5048_ADDR[2:0]$5056 + update $memwr$\memory$libresoc.v:122038$5048_DATA $0$memwr$\memory$libresoc.v:122038$5048_DATA[63:0]$5057 + update $memwr$\memory$libresoc.v:122038$5048_EN $0$memwr$\memory$libresoc.v:122038$5048_EN[63:0]$5058 + update $memwr$\memory$libresoc.v:122039$5049_ADDR $0$memwr$\memory$libresoc.v:122039$5049_ADDR[2:0]$5059 + update $memwr$\memory$libresoc.v:122039$5049_DATA $0$memwr$\memory$libresoc.v:122039$5049_DATA[63:0]$5060 + update $memwr$\memory$libresoc.v:122039$5049_EN $0$memwr$\memory$libresoc.v:122039$5049_EN[63:0]$5061 + end + attribute \src "libresoc.v:122044.3-122052.6" + process $proc$libresoc.v:122044$5065 + assign { } { } + assign { } { } + assign $0\ren_delay$next[0:0]$5066 $1\ren_delay$next[0:0]$5067 + attribute \src "libresoc.v:122045.5-122045.29" switch \initial - attribute \src "libresoc.v:28392.9-28392.17" + attribute \src "libresoc.v:122045.9-122045.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + assign $1\ren_delay$next[0:0]$5067 1'0 case - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'000 + assign $1\ren_delay$next[0:0]$5067 \src1__ren end sync always - update \dec31_dec_sub21_in1_sel $0\dec31_dec_sub21_in1_sel[2:0] + update \ren_delay$next $0\ren_delay$next[0:0]$5066 end - attribute \src "libresoc.v:28440.3-28488.6" - process $proc$libresoc.v:28440$626 + attribute \src "libresoc.v:122053.3-122062.6" + process $proc$libresoc.v:122053$5068 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_in2_sel[3:0] $1\dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:28441.5-28441.29" + assign $0\src1__data_o[63:0] $1\src1__data_o[63:0] + attribute \src "libresoc.v:122054.5-122054.29" switch \initial - attribute \src "libresoc.v:28441.9-28441.17" + attribute \src "libresoc.v:122054.9-122054.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + assign $1\src1__data_o[63:0] \memory_r_data case - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0000 + assign $1\src1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \dec31_dec_sub21_in2_sel $0\dec31_dec_sub21_in2_sel[3:0] + update \src1__data_o $0\src1__data_o[63:0] end - attribute \src "libresoc.v:28489.3-28537.6" - process $proc$libresoc.v:28489$627 + attribute \src "libresoc.v:122063.3-122071.6" + process $proc$libresoc.v:122063$5069 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_in3_sel[1:0] $1\dec31_dec_sub21_in3_sel[1:0] - attribute \src "libresoc.v:28490.5-28490.29" + assign $0\ren_delay$10$next[0:0]$5070 $1\ren_delay$10$next[0:0]$5071 + attribute \src "libresoc.v:122064.5-122064.29" switch \initial - attribute \src "libresoc.v:28490.9-28490.17" + attribute \src "libresoc.v:122064.9-122064.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + assign $1\ren_delay$10$next[0:0]$5071 1'0 case - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + assign $1\ren_delay$10$next[0:0]$5071 \src2__ren end sync always - update \dec31_dec_sub21_in3_sel $0\dec31_dec_sub21_in3_sel[1:0] + update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5070 end - attribute \src "libresoc.v:28538.3-28586.6" - process $proc$libresoc.v:28538$628 + attribute \src "libresoc.v:122072.3-122081.6" + process $proc$libresoc.v:122072$5072 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_out_sel[1:0] $1\dec31_dec_sub21_out_sel[1:0] - attribute \src "libresoc.v:28539.5-28539.29" + assign $0\src2__data_o[63:0] $1\src2__data_o[63:0] + attribute \src "libresoc.v:122073.5-122073.29" switch \initial - attribute \src "libresoc.v:28539.9-28539.17" + attribute \src "libresoc.v:122073.9-122073.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay$10 attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + assign $1\src2__data_o[63:0] \memory_r_data$4 case - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + assign $1\src2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \dec31_dec_sub21_out_sel $0\dec31_dec_sub21_out_sel[1:0] + update \src2__data_o $0\src2__data_o[63:0] end - attribute \src "libresoc.v:28587.3-28635.6" - process $proc$libresoc.v:28587$629 + attribute \src "libresoc.v:122082.3-122090.6" + process $proc$libresoc.v:122082$5073 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_cr_in[2:0] $1\dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:28588.5-28588.29" + assign $0\ren_delay$11$next[0:0]$5074 $1\ren_delay$11$next[0:0]$5075 + attribute \src "libresoc.v:122083.5-122083.29" switch \initial - attribute \src "libresoc.v:28588.9-28588.17" + attribute \src "libresoc.v:122083.9-122083.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + assign $1\ren_delay$11$next[0:0]$5075 1'0 case - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + assign $1\ren_delay$11$next[0:0]$5075 \issue__ren end sync always - update \dec31_dec_sub21_cr_in $0\dec31_dec_sub21_cr_in[2:0] + update \ren_delay$11$next $0\ren_delay$11$next[0:0]$5074 end - attribute \src "libresoc.v:28636.3-28684.6" - process $proc$libresoc.v:28636$630 + attribute \src "libresoc.v:122091.3-122100.6" + process $proc$libresoc.v:122091$5076 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_cr_out[2:0] $1\dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:28637.5-28637.29" + assign $0\issue__data_o[63:0] $1\issue__data_o[63:0] + attribute \src "libresoc.v:122092.5-122092.29" switch \initial - attribute \src "libresoc.v:28637.9-28637.17" + attribute \src "libresoc.v:122092.9-122092.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay$11 attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + assign $1\issue__data_o[63:0] \memory_r_data$6 case - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + assign $1\issue__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \dec31_dec_sub21_cr_out $0\dec31_dec_sub21_cr_out[2:0] + update \issue__data_o $0\issue__data_o[63:0] end - connect \opcode_switch \opcode_in [10:6] + connect \memory_r_data $memrd$\memory$libresoc.v:122041$5062_DATA + connect \memory_r_data$4 $memrd$\memory$libresoc.v:122042$5063_DATA + connect \memory_r_data$6 $memrd$\memory$libresoc.v:122043$5064_DATA + connect \memory_w_data$9 \issue__data_i + connect \memory_w_en$7 \issue__wen + connect \memory_w_addr$8 \issue__addr$1 + connect \memory_w_data \dest1__data_i + connect \memory_w_en \dest1__wen + connect \memory_w_addr \dest1__addr + connect \memory_r_addr$5 \issue__addr + connect \memory_r_addr$3 \src2__addr + connect \memory_r_addr \src1__addr end -attribute \src "libresoc.v:28690.1-30269.10" +attribute \src "libresoc.v:122114.1-124034.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub22" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus" attribute \generator "nMigen" -module \dec31_dec_sub22 - attribute \src "libresoc.v:29223.3-29277.6" - wire width 8 $0\dec31_dec_sub22_asmcode[7:0] - attribute \src "libresoc.v:29443.3-29497.6" - wire $0\dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:30158.3-30212.6" - wire width 3 $0\dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:30213.3-30267.6" - wire width 3 $0\dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:29168.3-29222.6" - wire width 2 $0\dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:29388.3-29442.6" - wire $0\dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:29883.3-29937.6" - wire width 5 $0\dec31_dec_sub22_form[4:0] - attribute \src "libresoc.v:28948.3-29002.6" - wire width 12 $0\dec31_dec_sub22_function_unit[11:0] - attribute \src "libresoc.v:29938.3-29992.6" - wire width 3 $0\dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:29993.3-30047.6" - wire width 4 $0\dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:30048.3-30102.6" - wire width 2 $0\dec31_dec_sub22_in3_sel[1:0] - attribute \src "libresoc.v:29553.3-29607.6" - wire width 7 $0\dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:29278.3-29332.6" - wire $0\dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:29333.3-29387.6" - wire $0\dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:29663.3-29717.6" - wire $0\dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:29003.3-29057.6" - wire width 4 $0\dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:29773.3-29827.6" - wire $0\dec31_dec_sub22_lk[0:0] - attribute \src "libresoc.v:30103.3-30157.6" - wire width 2 $0\dec31_dec_sub22_out_sel[1:0] - attribute \src "libresoc.v:29113.3-29167.6" - wire width 2 $0\dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:29608.3-29662.6" - wire $0\dec31_dec_sub22_rsrv[0:0] - attribute \src "libresoc.v:29828.3-29882.6" - wire $0\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "libresoc.v:29718.3-29772.6" - wire $0\dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:29498.3-29552.6" - wire $0\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:29058.3-29112.6" - wire width 2 $0\dec31_dec_sub22_upd[1:0] - attribute \src "libresoc.v:28691.7-28691.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:29223.3-29277.6" - wire width 8 $1\dec31_dec_sub22_asmcode[7:0] - attribute \src "libresoc.v:29443.3-29497.6" - wire $1\dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:30158.3-30212.6" - wire width 3 $1\dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:30213.3-30267.6" - wire width 3 $1\dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:29168.3-29222.6" - wire width 2 $1\dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:29388.3-29442.6" - wire $1\dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:29883.3-29937.6" - wire width 5 $1\dec31_dec_sub22_form[4:0] - attribute \src "libresoc.v:28948.3-29002.6" - wire width 12 $1\dec31_dec_sub22_function_unit[11:0] - attribute \src "libresoc.v:29938.3-29992.6" - wire width 3 $1\dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:29993.3-30047.6" - wire width 4 $1\dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:30048.3-30102.6" - wire width 2 $1\dec31_dec_sub22_in3_sel[1:0] - attribute \src "libresoc.v:29553.3-29607.6" - wire width 7 $1\dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:29278.3-29332.6" - wire $1\dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:29333.3-29387.6" - wire $1\dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:29663.3-29717.6" - wire $1\dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:29003.3-29057.6" - wire width 4 $1\dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:29773.3-29827.6" - wire $1\dec31_dec_sub22_lk[0:0] - attribute \src "libresoc.v:30103.3-30157.6" - wire width 2 $1\dec31_dec_sub22_out_sel[1:0] - attribute \src "libresoc.v:29113.3-29167.6" - wire width 2 $1\dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:29608.3-29662.6" - wire $1\dec31_dec_sub22_rsrv[0:0] - attribute \src "libresoc.v:29828.3-29882.6" - wire $1\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "libresoc.v:29718.3-29772.6" - wire $1\dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:29498.3-29552.6" - wire $1\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:29058.3-29112.6" - wire width 2 $1\dec31_dec_sub22_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub22_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub22_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub22_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub22_cr_out +module \fus + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 330 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 257 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 258 \cr_a_ok$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 259 \cr_a_ok$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 260 \cr_a_ok$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 261 \cr_a_ok$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 262 \cr_a_ok$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire input 3 \cu_ad__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire output 4 \cu_ad__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 25 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 75 \cu_busy_o$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 82 \cu_busy_o$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 103 \cu_busy_o$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 31 \cu_busy_o$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 118 \cu_busy_o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 138 \cu_busy_o$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 157 \cu_busy_o$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 42 \cu_busy_o$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 54 \cu_busy_o$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 24 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 30 \cu_issue_i$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 74 \cu_issue_i$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 81 \cu_issue_i$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 102 \cu_issue_i$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 117 \cu_issue_i$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 137 \cu_issue_i$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 156 \cu_issue_i$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 41 \cu_issue_i$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 53 \cu_issue_i$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 160 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 input 163 \cu_rd__go_i$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 166 \cu_rd__go_i$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 169 \cu_rd__go_i$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 input 172 \cu_rd__go_i$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 175 \cu_rd__go_i$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 178 \cu_rd__go_i$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 input 181 \cu_rd__go_i$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 184 \cu_rd__go_i$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 209 \cu_rd__go_i$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 159 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 output 162 \cu_rd__rel_o$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 165 \cu_rd__rel_o$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 168 \cu_rd__rel_o$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 output 171 \cu_rd__rel_o$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 174 \cu_rd__rel_o$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 177 \cu_rd__rel_o$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 output 180 \cu_rd__rel_o$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 183 \cu_rd__rel_o$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 208 \cu_rd__rel_o$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 4 input 26 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 76 \cu_rdmaskn_i$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 6 input 83 \cu_rdmaskn_i$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 104 \cu_rdmaskn_i$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 119 \cu_rdmaskn_i$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 5 input 139 \cu_rdmaskn_i$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 158 \cu_rdmaskn_i$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 6 input 32 \cu_rdmaskn_i$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 43 \cu_rdmaskn_i$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 4 input 55 \cu_rdmaskn_i$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire input 5 \cu_st__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire output 2 \cu_st__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 input 221 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 242 \cu_wr__go_i$100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 input 244 \cu_wr__go_i$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 293 \cu_wr__go_i$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 224 \cu_wr__go_i$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 input 227 \cu_wr__go_i$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 input 230 \cu_wr__go_i$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 input 233 \cu_wr__go_i$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 236 \cu_wr__go_i$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 239 \cu_wr__go_i$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 output 220 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 output 243 \cu_wr__rel_o$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 292 \cu_wr__rel_o$136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 223 \cu_wr__rel_o$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 output 226 \cu_wr__rel_o$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 output 229 \cu_wr__rel_o$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 output 232 \cu_wr__rel_o$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 235 \cu_wr__rel_o$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 238 \cu_wr__rel_o$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 241 \cu_wr__rel_o$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 245 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 246 \dest1_o$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 247 \dest1_o$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 248 \dest1_o$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 249 \dest1_o$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 250 \dest1_o$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 251 \dest1_o$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 252 \dest1_o$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 298 \dest1_o$141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 32 output 256 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 263 \dest2_o$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 265 \dest2_o$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 266 \dest2_o$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 267 \dest2_o$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 268 \dest2_o$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 299 \dest2_o$142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 301 \dest2_o$144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 310 \dest2_o$150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 264 \dest3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 272 \dest3_o$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 274 \dest3_o$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 281 \dest3_o$127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 282 \dest3_o$128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 300 \dest3_o$143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 302 \dest3_o$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 305 \dest3_o$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 279 \dest4_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 288 \dest4_o$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 289 \dest4_o$134 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 290 \dest4_o$135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 306 \dest4_o$148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 280 \dest5_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 287 \dest5_o$132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 308 \dest5_o$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 273 \dest6_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 254 \ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 291 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 294 \fast1_ok$138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 295 \fast1_ok$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 296 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 297 \fast2_ok$140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 255 \full_cr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 96 output 315 \ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 316 \ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire input 325 \ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire input 311 \ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 output 314 \ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 317 \ldst_port0_exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 318 \ldst_port0_exc_$signal$151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 319 \ldst_port0_exc_$signal$152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 320 \ldst_port0_exc_$signal$153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 321 \ldst_port0_exc_$signal$154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 322 \ldst_port0_exc_$signal$155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 323 \ldst_port0_exc_$signal$156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 324 \ldst_port0_exc_$signal$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire output 312 \ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire output 313 \ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 326 \ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 327 \ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 328 \ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 329 \ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 307 \msr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 303 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 304 \nia_ok$146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 253 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 219 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 222 \o_ok$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 225 \o_ok$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 228 \o_ok$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 231 \o_ok$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 234 \o_ok$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 237 \o_ok$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 240 \o_ok$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 22 \oper_i_alu_alu0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 7 \oper_i_alu_alu0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 8 \oper_i_alu_alu0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \oper_i_alu_alu0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 18 \oper_i_alu_alu0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 23 \oper_i_alu_alu0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 6 \oper_i_alu_alu0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \oper_i_alu_alu0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \oper_i_alu_alu0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \oper_i_alu_alu0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 21 \oper_i_alu_alu0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \oper_i_alu_alu0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \oper_i_alu_alu0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \oper_i_alu_alu0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \oper_i_alu_alu0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \oper_i_alu_alu0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \oper_i_alu_alu0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \oper_i_alu_alu0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 33 \oper_i_alu_branch0__cia + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 35 \oper_i_alu_branch0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 37 \oper_i_alu_branch0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 38 \oper_i_alu_branch0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 36 \oper_i_alu_branch0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute 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"OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 34 \oper_i_alu_branch0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 40 \oper_i_alu_branch0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 39 \oper_i_alu_branch0__lk + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 28 \oper_i_alu_cr0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 29 \oper_i_alu_cr0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 27 \oper_i_alu_cr0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 100 \oper_i_alu_div0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 85 \oper_i_alu_div0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 86 \oper_i_alu_div0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 87 \oper_i_alu_div0__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub22_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub22_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub22_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 94 \oper_i_alu_div0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 101 \oper_i_alu_div0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 84 \oper_i_alu_div0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 92 \oper_i_alu_div0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 95 \oper_i_alu_div0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 98 \oper_i_alu_div0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 99 \oper_i_alu_div0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 90 \oper_i_alu_div0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 91 \oper_i_alu_div0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 97 \oper_i_alu_div0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 89 \oper_i_alu_div0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 88 \oper_i_alu_div0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 96 \oper_i_alu_div0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 93 \oper_i_alu_div0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 72 \oper_i_alu_logical0__data_len attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -42270,39 +194181,20 @@ module \dec31_dec_sub22 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub22_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub22_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub22_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub22_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 57 \oper_i_alu_logical0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 58 \oper_i_alu_logical0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 59 \oper_i_alu_logical0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 66 \oper_i_alu_logical0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 73 \oper_i_alu_logical0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -42377,2225 +194269,3842 @@ module \dec31_dec_sub22 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub22_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub22_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub22_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub22_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub22_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub22_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 56 \oper_i_alu_logical0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 64 \oper_i_alu_logical0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 67 \oper_i_alu_logical0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 70 \oper_i_alu_logical0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 71 \oper_i_alu_logical0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 62 \oper_i_alu_logical0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 63 \oper_i_alu_logical0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 69 \oper_i_alu_logical0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 61 \oper_i_alu_logical0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 60 \oper_i_alu_logical0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 68 \oper_i_alu_logical0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 65 \oper_i_alu_logical0__zero_a + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 106 \oper_i_alu_mul0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 107 \oper_i_alu_mul0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 108 \oper_i_alu_mul0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 116 \oper_i_alu_mul0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 105 \oper_i_alu_mul0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 114 \oper_i_alu_mul0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 115 \oper_i_alu_mul0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 111 \oper_i_alu_mul0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 112 \oper_i_alu_mul0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 110 \oper_i_alu_mul0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 109 \oper_i_alu_mul0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 113 \oper_i_alu_mul0__write_cr0 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 121 \oper_i_alu_shift_rot0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 122 \oper_i_alu_shift_rot0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 123 \oper_i_alu_shift_rot0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub22_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub22_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub22_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub22_sgn_ext + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 130 \oper_i_alu_shift_rot0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 132 \oper_i_alu_shift_rot0__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 136 \oper_i_alu_shift_rot0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 120 \oper_i_alu_shift_rot0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 129 \oper_i_alu_shift_rot0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 134 \oper_i_alu_shift_rot0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 135 \oper_i_alu_shift_rot0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 126 \oper_i_alu_shift_rot0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 127 \oper_i_alu_shift_rot0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 131 \oper_i_alu_shift_rot0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 133 \oper_i_alu_shift_rot0__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 125 \oper_i_alu_shift_rot0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 124 \oper_i_alu_shift_rot0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 128 \oper_i_alu_shift_rot0__write_cr0 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 78 \oper_i_alu_spr0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 79 \oper_i_alu_spr0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 77 \oper_i_alu_spr0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 80 \oper_i_alu_spr0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 48 \oper_i_alu_trap0__cia + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 45 \oper_i_alu_trap0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 46 \oper_i_alu_trap0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 44 \oper_i_alu_trap0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 49 \oper_i_alu_trap0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 52 \oper_i_alu_trap0__ldst_exc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 47 \oper_i_alu_trap0__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 51 \oper_i_alu_trap0__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 50 \oper_i_alu_trap0__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 152 \oper_i_ldst_ldst0__byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 151 \oper_i_ldst_ldst0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 141 \oper_i_ldst_ldst0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 142 \oper_i_ldst_ldst0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 143 \oper_i_ldst_ldst0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 155 \oper_i_ldst_ldst0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 140 \oper_i_ldst_ldst0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 149 \oper_i_ldst_ldst0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 150 \oper_i_ldst_ldst0__is_signed attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub22_upd - attribute \src "libresoc.v:28691.7-28691.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 154 \oper_i_ldst_ldst0__ldst_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 147 \oper_i_ldst_ldst0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 148 \oper_i_ldst_ldst0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 146 \oper_i_ldst_ldst0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 145 \oper_i_ldst_ldst0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 153 \oper_i_ldst_ldst0__sign_extend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 144 \oper_i_ldst_ldst0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 309 \spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 161 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 164 \src1_i$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 167 \src1_i$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 170 \src1_i$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 173 \src1_i$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 176 \src1_i$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 179 \src1_i$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 182 \src1_i$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 185 \src1_i$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 213 \src1_i$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 186 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 187 \src2_i$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 188 \src2_i$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 189 \src2_i$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 190 \src2_i$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 191 \src2_i$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 192 \src2_i$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 193 \src2_i$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 216 \src2_i$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 218 \src2_i$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 194 \src3_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 195 \src3_i$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 196 \src3_i$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 197 \src3_i$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 199 \src3_i$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 200 \src3_i$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 32 input 206 \src3_i$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 210 \src3_i$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 214 \src3_i$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 215 \src3_i$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 198 \src4_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 201 \src4_i$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 202 \src4_i$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 207 \src4_i$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 217 \src4_i$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 204 \src5_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 205 \src5_i$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 211 \src5_i$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 203 \src6_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 212 \src6_i$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 269 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 270 \xer_ca_ok$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 271 \xer_ca_ok$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 275 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 276 \xer_ov_ok$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 277 \xer_ov_ok$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 278 \xer_ov_ok$126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 283 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 284 \xer_so_ok$129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 285 \xer_so_ok$130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 286 \xer_so_ok$131 + attribute \module_not_derived 1 + attribute \src "libresoc.v:123666.8-123708.4" + cell \alu0 \alu0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \cr_a_ok + connect \cu_busy_o \cu_busy_o + connect \cu_issue_i \cu_issue_i + connect \cu_rd__go_i \cu_rd__go_i + connect \cu_rd__rel_o \cu_rd__rel_o + connect \cu_rdmaskn_i \cu_rdmaskn_i + connect \cu_wr__go_i \cu_wr__go_i + connect \cu_wr__rel_o \cu_wr__rel_o + connect \dest1_o \dest1_o + connect \dest2_o \dest2_o$115 + connect \dest3_o \dest3_o$122 + connect \dest4_o \dest4_o + connect \dest5_o \dest5_o$132 + connect \o_ok \o_ok + connect \oper_i_alu_alu0__data_len \oper_i_alu_alu0__data_len + connect \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__fn_unit + connect \oper_i_alu_alu0__imm_data__data \oper_i_alu_alu0__imm_data__data + connect \oper_i_alu_alu0__imm_data__ok \oper_i_alu_alu0__imm_data__ok + connect \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__input_carry + connect \oper_i_alu_alu0__insn \oper_i_alu_alu0__insn + connect \oper_i_alu_alu0__insn_type \oper_i_alu_alu0__insn_type + connect \oper_i_alu_alu0__invert_in \oper_i_alu_alu0__invert_in + connect \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__invert_out + connect \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__is_32bit + connect \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_signed + connect \oper_i_alu_alu0__oe__oe \oper_i_alu_alu0__oe__oe + connect \oper_i_alu_alu0__oe__ok \oper_i_alu_alu0__oe__ok + connect \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__output_carry + connect \oper_i_alu_alu0__rc__ok \oper_i_alu_alu0__rc__ok + connect \oper_i_alu_alu0__rc__rc \oper_i_alu_alu0__rc__rc + connect \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__write_cr0 + connect \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__zero_a + connect \src1_i \src1_i + connect \src2_i \src2_i + connect \src3_i \src3_i$60 + connect \src4_i \src4_i$65 + connect \xer_ca_ok \xer_ca_ok + connect \xer_ov_ok \xer_ov_ok + connect \xer_so_ok \xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:123709.11-123736.4" + cell \branch0 \branch0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cu_busy_o \cu_busy_o$5 + connect \cu_issue_i \cu_issue_i$4 + connect \cu_rd__go_i \cu_rd__go_i$70 + connect \cu_rd__rel_o \cu_rd__rel_o$69 + connect \cu_rdmaskn_i \cu_rdmaskn_i$6 + connect \cu_wr__go_i \cu_wr__go_i$137 + connect \cu_wr__rel_o \cu_wr__rel_o$136 + connect \dest1_o \dest1_o$141 + connect \dest2_o \dest2_o$144 + connect \dest3_o \dest3_o$147 + connect \fast1_ok \fast1_ok + connect \fast2_ok \fast2_ok + connect \nia_ok \nia_ok + connect \oper_i_alu_branch0__cia \oper_i_alu_branch0__cia + connect \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__fn_unit + connect \oper_i_alu_branch0__imm_data__data \oper_i_alu_branch0__imm_data__data + connect \oper_i_alu_branch0__imm_data__ok \oper_i_alu_branch0__imm_data__ok + connect \oper_i_alu_branch0__insn \oper_i_alu_branch0__insn + connect \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__insn_type + connect \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__is_32bit + connect \oper_i_alu_branch0__lk \oper_i_alu_branch0__lk + connect \src1_i \src1_i$74 + connect \src2_i \src2_i$77 + connect \src3_i \src3_i$71 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:123737.7-123762.4" + cell \cr0 \cr0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \cr_a_ok$110 + connect \cu_busy_o \cu_busy_o$2 + connect \cu_issue_i \cu_issue_i$1 + connect \cu_rd__go_i \cu_rd__go_i$29 + connect \cu_rd__rel_o \cu_rd__rel_o$28 + connect \cu_rdmaskn_i \cu_rdmaskn_i$3 + connect \cu_wr__go_i \cu_wr__go_i$82 + connect \cu_wr__rel_o \cu_wr__rel_o$81 + connect \dest1_o \dest1_o$103 + connect \dest2_o \dest2_o + connect \dest3_o \dest3_o + connect \full_cr_ok \full_cr_ok + connect \o_ok \o_ok$80 + connect \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__fn_unit + connect \oper_i_alu_cr0__insn \oper_i_alu_cr0__insn + connect \oper_i_alu_cr0__insn_type \oper_i_alu_cr0__insn_type + connect \src1_i \src1_i$30 + connect \src2_i \src2_i$52 + connect \src3_i \src3_i$67 + connect \src4_i \src4_i$68 + connect \src5_i \src5_i$72 + connect \src6_i \src6_i$73 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:123763.8-123802.4" + cell \div0 \div0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \cr_a_ok$112 + connect \cu_busy_o \cu_busy_o$17 + connect \cu_issue_i \cu_issue_i$16 + connect \cu_rd__go_i \cu_rd__go_i$41 + connect \cu_rd__rel_o \cu_rd__rel_o$40 + connect \cu_rdmaskn_i \cu_rdmaskn_i$18 + connect \cu_wr__go_i \cu_wr__go_i$94 + connect \cu_wr__rel_o \cu_wr__rel_o$93 + connect \dest1_o \dest1_o$107 + connect \dest2_o \dest2_o$117 + connect \dest3_o \dest3_o$127 + connect \dest4_o \dest4_o$134 + connect \o_ok \o_ok$92 + connect \oper_i_alu_div0__data_len \oper_i_alu_div0__data_len + connect \oper_i_alu_div0__fn_unit \oper_i_alu_div0__fn_unit + connect \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__imm_data__data + connect \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__ok + connect \oper_i_alu_div0__input_carry \oper_i_alu_div0__input_carry + connect \oper_i_alu_div0__insn \oper_i_alu_div0__insn + connect \oper_i_alu_div0__insn_type \oper_i_alu_div0__insn_type + connect \oper_i_alu_div0__invert_in \oper_i_alu_div0__invert_in + connect \oper_i_alu_div0__invert_out \oper_i_alu_div0__invert_out + connect \oper_i_alu_div0__is_32bit \oper_i_alu_div0__is_32bit + connect \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_signed + connect \oper_i_alu_div0__oe__oe \oper_i_alu_div0__oe__oe + connect \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__ok + connect \oper_i_alu_div0__output_carry \oper_i_alu_div0__output_carry + connect \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__ok + connect \oper_i_alu_div0__rc__rc \oper_i_alu_div0__rc__rc + connect \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__write_cr0 + connect \oper_i_alu_div0__zero_a \oper_i_alu_div0__zero_a + connect \src1_i \src1_i$42 + connect \src2_i \src2_i$55 + connect \src3_i \src3_i$62 + connect \xer_ov_ok \xer_ov_ok$125 + connect \xer_so_ok \xer_so_ok$130 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:123803.9-123857.4" + cell \ldst0 \ldst0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cu_ad__go_i \cu_ad__go_i + connect \cu_ad__rel_o \cu_ad__rel_o + connect \cu_busy_o \cu_busy_o$26 + connect \cu_issue_i \cu_issue_i$25 + connect \cu_rd__go_i \cu_rd__go_i$50 + connect \cu_rd__rel_o \cu_rd__rel_o$49 + connect \cu_rdmaskn_i \cu_rdmaskn_i$27 + connect \cu_st__go_i \cu_st__go_i + connect \cu_st__rel_o \cu_st__rel_o + connect \cu_wr__go_i \cu_wr__go_i$102 + connect \cu_wr__rel_o \cu_wr__rel_o$101 + connect \ea \ea + connect \ldst_port0_addr_i \ldst_port0_addr_i + connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok + connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o + connect \ldst_port0_busy_o \ldst_port0_busy_o + connect \ldst_port0_data_len \ldst_port0_data_len + connect \ldst_port0_exc_$signal \ldst_port0_exc_$signal + connect \ldst_port0_exc_$signal$1 \ldst_port0_exc_$signal$151 + connect \ldst_port0_exc_$signal$2 \ldst_port0_exc_$signal$152 + connect \ldst_port0_exc_$signal$3 \ldst_port0_exc_$signal$153 + connect \ldst_port0_exc_$signal$4 \ldst_port0_exc_$signal$154 + connect \ldst_port0_exc_$signal$5 \ldst_port0_exc_$signal$155 + connect \ldst_port0_exc_$signal$6 \ldst_port0_exc_$signal$156 + connect \ldst_port0_exc_$signal$7 \ldst_port0_exc_$signal$157 + connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i + connect \ldst_port0_is_st_i \ldst_port0_is_st_i + connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok + connect \ldst_port0_st_data_i \ldst_port0_st_data_i + connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok + connect \o \o + connect \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__byte_reverse + connect \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__data_len + connect \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__fn_unit + connect \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__imm_data__data + connect \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__ok + connect \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__insn + connect \oper_i_ldst_ldst0__insn_type \oper_i_ldst_ldst0__insn_type + connect \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__is_32bit + connect \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_signed + connect \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__ldst_mode + connect \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__oe__oe + connect \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__ok + connect \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__ok + connect \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__rc__rc + connect \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__sign_extend + connect \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__zero_a + connect \src1_i \src1_i$51 + connect \src2_i \src2_i$58 + connect \src3_i \src3_i$59 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:123858.12-123893.4" + cell \logical0 \logical0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \cr_a_ok$111 + connect \cu_busy_o \cu_busy_o$11 + connect \cu_issue_i \cu_issue_i$10 + connect \cu_rd__go_i \cu_rd__go_i$35 + connect \cu_rd__rel_o \cu_rd__rel_o$34 + connect \cu_rdmaskn_i \cu_rdmaskn_i$12 + connect \cu_wr__go_i \cu_wr__go_i$88 + connect \cu_wr__rel_o \cu_wr__rel_o$87 + connect \dest1_o \dest1_o$105 + connect \dest2_o \dest2_o$116 + connect \o_ok \o_ok$86 + connect \oper_i_alu_logical0__data_len \oper_i_alu_logical0__data_len + connect \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__fn_unit + connect \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__imm_data__data + connect \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__ok + connect \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__input_carry + connect \oper_i_alu_logical0__insn \oper_i_alu_logical0__insn + connect \oper_i_alu_logical0__insn_type \oper_i_alu_logical0__insn_type + connect \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__invert_in + connect \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__invert_out + connect \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__is_32bit + connect \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_signed + connect \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__oe__oe + connect \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__ok + connect \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__output_carry + connect \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__ok + connect \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__rc__rc + connect \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__write_cr0 + connect \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__zero_a + connect \src1_i \src1_i$36 + connect \src2_i \src2_i$54 + connect \src3_i \src3_i$61 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:123894.8-123927.4" + cell \mul0 \mul0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \cr_a_ok$113 + connect \cu_busy_o \cu_busy_o$20 + connect \cu_issue_i \cu_issue_i$19 + connect \cu_rd__go_i \cu_rd__go_i$44 + connect \cu_rd__rel_o \cu_rd__rel_o$43 + connect \cu_rdmaskn_i \cu_rdmaskn_i$21 + connect \cu_wr__go_i \cu_wr__go_i$97 + connect \cu_wr__rel_o \cu_wr__rel_o$96 + connect \dest1_o \dest1_o$108 + connect \dest2_o \dest2_o$118 + connect \dest3_o \dest3_o$128 + connect \dest4_o \dest4_o$135 + connect \o_ok \o_ok$95 + connect \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__fn_unit + connect \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__imm_data__data + connect \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__ok + connect \oper_i_alu_mul0__insn \oper_i_alu_mul0__insn + connect \oper_i_alu_mul0__insn_type \oper_i_alu_mul0__insn_type + connect \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__is_32bit + connect \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_signed + connect \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__oe__oe + connect \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__ok + connect \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__ok + connect \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__rc__rc + connect \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__write_cr0 + connect \src1_i \src1_i$45 + connect \src2_i \src2_i$56 + connect \src3_i \src3_i$63 + connect \xer_ov_ok \xer_ov_ok$126 + connect \xer_so_ok \xer_so_ok$131 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:123928.13-123966.4" + cell \shiftrot0 \shiftrot0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \cr_a_ok$114 + connect \cu_busy_o \cu_busy_o$23 + connect \cu_issue_i \cu_issue_i$22 + connect \cu_rd__go_i \cu_rd__go_i$47 + connect \cu_rd__rel_o \cu_rd__rel_o$46 + connect \cu_rdmaskn_i \cu_rdmaskn_i$24 + connect \cu_wr__go_i \cu_wr__go_i$100 + connect \cu_wr__rel_o \cu_wr__rel_o$99 + connect \dest1_o \dest1_o$109 + connect \dest2_o \dest2_o$119 + connect \dest3_o \dest3_o$123 + connect \o_ok \o_ok$98 + connect \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__fn_unit + connect \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__imm_data__data + connect \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__ok + connect \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__input_carry + connect \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__input_cr + connect \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__insn + connect \oper_i_alu_shift_rot0__insn_type \oper_i_alu_shift_rot0__insn_type + connect \oper_i_alu_shift_rot0__invert_in \oper_i_alu_shift_rot0__invert_in + connect \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__is_32bit + connect \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_signed + connect \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__oe__oe + connect \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__ok + connect \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__output_carry + connect \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__output_cr + connect \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__ok + connect \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__rc__rc + connect \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__write_cr0 + connect \src1_i \src1_i$48 + connect \src2_i \src2_i$57 + connect \src3_i \src3_i + connect \src4_i \src4_i$64 + connect \src5_i \src5_i + connect \xer_ca_ok \xer_ca_ok$121 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:123967.8-123999.4" + cell \spr0 \spr0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cu_busy_o \cu_busy_o$14 + connect \cu_issue_i \cu_issue_i$13 + connect \cu_rd__go_i \cu_rd__go_i$38 + connect \cu_rd__rel_o \cu_rd__rel_o$37 + connect \cu_rdmaskn_i \cu_rdmaskn_i$15 + connect \cu_wr__go_i \cu_wr__go_i$91 + connect \cu_wr__rel_o \cu_wr__rel_o$90 + connect \dest1_o \dest1_o$106 + connect \dest2_o \dest2_o$150 + connect \dest3_o \dest3_o$143 + connect \dest4_o \dest4_o$133 + connect \dest5_o \dest5_o + connect \dest6_o \dest6_o + connect \fast1_ok \fast1_ok$139 + connect \o_ok \o_ok$89 + connect \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__fn_unit + connect \oper_i_alu_spr0__insn \oper_i_alu_spr0__insn + connect \oper_i_alu_spr0__insn_type \oper_i_alu_spr0__insn_type + connect \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__is_32bit + connect \spr1_ok \spr1_ok + connect \src1_i \src1_i$39 + connect \src2_i \src2_i$79 + connect \src3_i \src3_i$76 + connect \src4_i \src4_i + connect \src5_i \src5_i$66 + connect \src6_i \src6_i + connect \xer_ca_ok \xer_ca_ok$120 + connect \xer_ov_ok \xer_ov_ok$124 + connect \xer_so_ok \xer_so_ok$129 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:124000.9-124033.4" + cell \trap0 \trap0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cu_busy_o \cu_busy_o$8 + connect \cu_issue_i \cu_issue_i$7 + connect \cu_rd__go_i \cu_rd__go_i$32 + connect \cu_rd__rel_o \cu_rd__rel_o$31 + connect \cu_rdmaskn_i \cu_rdmaskn_i$9 + connect \cu_wr__go_i \cu_wr__go_i$85 + connect \cu_wr__rel_o \cu_wr__rel_o$84 + connect \dest1_o \dest1_o$104 + connect \dest2_o \dest2_o$142 + connect \dest3_o \dest3_o$145 + connect \dest4_o \dest4_o$148 + connect \dest5_o \dest5_o$149 + connect \fast1_ok \fast1_ok$138 + connect \fast2_ok \fast2_ok$140 + connect \msr_ok \msr_ok + connect \nia_ok \nia_ok$146 + connect \o_ok \o_ok$83 + connect \oper_i_alu_trap0__cia \oper_i_alu_trap0__cia + connect \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__fn_unit + connect \oper_i_alu_trap0__insn \oper_i_alu_trap0__insn + connect \oper_i_alu_trap0__insn_type \oper_i_alu_trap0__insn_type + connect \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__is_32bit + connect \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__ldst_exc + connect \oper_i_alu_trap0__msr \oper_i_alu_trap0__msr + connect \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__trapaddr + connect \oper_i_alu_trap0__traptype \oper_i_alu_trap0__traptype + connect \src1_i \src1_i$33 + connect \src2_i \src2_i$53 + connect \src3_i \src3_i$75 + connect \src4_i \src4_i$78 + end +end +attribute \src "libresoc.v:124038.1-124096.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.idx_l" +attribute \generator "nMigen" +module \idx_l + attribute \src "libresoc.v:124039.7-124039.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:124084.3-124092.6" + wire $0\q_int$next[0:0]$5104 + attribute \src "libresoc.v:124082.3-124083.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:124084.3-124092.6" + wire $1\q_int$next[0:0]$5105 + attribute \src "libresoc.v:124063.7-124063.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:124074.17-124074.96" + wire $and$libresoc.v:124074$5094_Y + attribute \src "libresoc.v:124079.17-124079.96" + wire $and$libresoc.v:124079$5099_Y + attribute \src "libresoc.v:124076.18-124076.95" + wire $not$libresoc.v:124076$5096_Y + attribute \src "libresoc.v:124078.17-124078.94" + wire $not$libresoc.v:124078$5098_Y + attribute \src "libresoc.v:124081.17-124081.94" + wire $not$libresoc.v:124081$5101_Y + attribute \src "libresoc.v:124075.18-124075.100" + wire $or$libresoc.v:124075$5095_Y + attribute \src "libresoc.v:124077.18-124077.101" + wire $or$libresoc.v:124077$5097_Y + attribute \src "libresoc.v:124080.17-124080.99" + wire $or$libresoc.v:124080$5100_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:124039.7-124039.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:28691.7-28691.20" - process $proc$libresoc.v:28691$656 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 4 \r_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 3 \s_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:124074$5094 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:124074$5094_Y end - attribute \src "libresoc.v:28948.3-29002.6" - process $proc$libresoc.v:28948$632 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_function_unit[11:0] $1\dec31_dec_sub22_function_unit[11:0] - attribute \src "libresoc.v:28949.5-28949.29" - switch \initial - attribute \src "libresoc.v:28949.9-28949.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'100000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 - case - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub22_function_unit $0\dec31_dec_sub22_function_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:124079$5099 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:124079$5099_Y end - attribute \src "libresoc.v:29003.3-29057.6" - process $proc$libresoc.v:29003$633 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_ldst_len[3:0] $1\dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:29004.5-29004.29" - switch \initial - attribute \src "libresoc.v:29004.9-29004.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub22_ldst_len $0\dec31_dec_sub22_ldst_len[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:124076$5096 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_idx_l + connect \Y $not$libresoc.v:124076$5096_Y end - attribute \src "libresoc.v:29058.3-29112.6" - process $proc$libresoc.v:29058$634 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_upd[1:0] $1\dec31_dec_sub22_upd[1:0] - attribute \src "libresoc.v:29059.5-29059.29" - switch \initial - attribute \src "libresoc.v:29059.9-29059.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub22_upd $0\dec31_dec_sub22_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:124078$5098 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_idx_l + connect \Y $not$libresoc.v:124078$5098_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:124081$5101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_idx_l + connect \Y $not$libresoc.v:124081$5101_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:124075$5095 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_idx_l + connect \Y $or$libresoc.v:124075$5095_Y end - attribute \src "libresoc.v:29113.3-29167.6" - process $proc$libresoc.v:29113$635 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:124077$5097 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_idx_l + connect \B \q_int + connect \Y $or$libresoc.v:124077$5097_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:124080$5100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_idx_l + connect \Y $or$libresoc.v:124080$5100_Y + end + attribute \src "libresoc.v:124039.7-124039.20" + process $proc$libresoc.v:124039$5106 assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:124063.7-124063.19" + process $proc$libresoc.v:124063$5107 assign { } { } - assign $0\dec31_dec_sub22_rc_sel[1:0] $1\dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:29114.5-29114.29" - switch \initial - attribute \src "libresoc.v:29114.9-29114.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - end + assign $1\q_int[0:0] 1'0 sync always - update \dec31_dec_sub22_rc_sel $0\dec31_dec_sub22_rc_sel[1:0] + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:124082.3-124083.27" + process $proc$libresoc.v:124082$5102 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:29168.3-29222.6" - process $proc$libresoc.v:29168$636 + attribute \src "libresoc.v:124084.3-124092.6" + process $proc$libresoc.v:124084$5103 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_cry_in[1:0] $1\dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:29169.5-29169.29" + assign $0\q_int$next[0:0]$5104 $1\q_int$next[0:0]$5105 + attribute \src "libresoc.v:124085.5-124085.29" switch \initial - attribute \src "libresoc.v:29169.9-29169.17" + attribute \src "libresoc.v:124085.9-124085.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 1'1 assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + assign $1\q_int$next[0:0]$5105 1'0 case - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + assign $1\q_int$next[0:0]$5105 \$5 end sync always - update \dec31_dec_sub22_cry_in $0\dec31_dec_sub22_cry_in[1:0] + update \q_int$next $0\q_int$next[0:0]$5104 + end + connect \$9 $and$libresoc.v:124074$5094_Y + connect \$11 $or$libresoc.v:124075$5095_Y + connect \$13 $not$libresoc.v:124076$5096_Y + connect \$15 $or$libresoc.v:124077$5097_Y + connect \$1 $not$libresoc.v:124078$5098_Y + connect \$3 $and$libresoc.v:124079$5099_Y + connect \$5 $or$libresoc.v:124080$5100_Y + connect \$7 $not$libresoc.v:124081$5101_Y + connect \qlq_idx_l \$15 + connect \qn_idx_l \$13 + connect \q_idx_l \$11 +end +attribute \src "libresoc.v:124100.1-124479.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.imem" +attribute \generator "nMigen" +module \imem + attribute \src "libresoc.v:124431.3-124440.6" + wire $0\a_busy_o[0:0] + attribute \src "libresoc.v:124411.3-124430.6" + wire width 45 $0\f_badaddr_o$next[44:0]$5176 + attribute \src "libresoc.v:124242.3-124243.39" + wire width 45 $0\f_badaddr_o[44:0] + attribute \src "libresoc.v:124441.3-124458.6" + wire $0\f_busy_o[0:0] + attribute \src "libresoc.v:124388.3-124410.6" + wire $0\f_fetch_err_o$next[0:0]$5171 + attribute \src "libresoc.v:124244.3-124245.43" + wire $0\f_fetch_err_o[0:0] + attribute \src "libresoc.v:124459.3-124476.6" + wire width 64 $0\f_instr_o[63:0] + attribute \src "libresoc.v:124365.3-124387.6" + wire width 45 $0\ibus__adr$next[44:0]$5166 + attribute \src "libresoc.v:124246.3-124247.35" + wire width 45 $0\ibus__adr[44:0] + attribute \src "libresoc.v:124256.3-124283.6" + wire $0\ibus__cyc$next[0:0]$5142 + attribute \src "libresoc.v:124254.3-124255.35" + wire $0\ibus__cyc[0:0] + attribute \src "libresoc.v:124312.3-124339.6" + wire width 8 $0\ibus__sel$next[7:0]$5154 + attribute \src "libresoc.v:124250.3-124251.35" + wire width 8 $0\ibus__sel[7:0] + attribute \src "libresoc.v:124284.3-124311.6" + wire $0\ibus__stb$next[0:0]$5148 + attribute \src "libresoc.v:124252.3-124253.35" + wire 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parameter \Y_WIDTH 1 + connect \A \f_stall_i + connect \Y $not$libresoc.v:124237$5129_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" + cell $not $not$libresoc.v:124239$5131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_stall_i + connect \Y $not$libresoc.v:124239$5131_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $not $not$libresoc.v:124241$5133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_valid_i + connect \Y $not$libresoc.v:124241$5133_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:124216$5108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \$7 + connect \Y $or$libresoc.v:124216$5108_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:124219$5111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $or$libresoc.v:124219$5111_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:124222$5114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$15 + connect \B \$17 + connect \Y $or$libresoc.v:124222$5114_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:124225$5117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $or$libresoc.v:124225$5117_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:124227$5119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$25 + connect \B \$27 + connect \Y $or$libresoc.v:124227$5119_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:124230$5122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $or$libresoc.v:124230$5122_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:124233$5125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$35 + connect \B \$37 + connect \Y $or$libresoc.v:124233$5125_Y end - attribute \src "libresoc.v:29223.3-29277.6" - process $proc$libresoc.v:29223$637 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:124240$5132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $or$libresoc.v:124240$5132_Y + end + attribute \src "libresoc.v:124101.7-124101.20" + process $proc$libresoc.v:124101$5183 assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:124165.14-124165.44" + process $proc$libresoc.v:124165$5184 assign { } { } - assign $0\dec31_dec_sub22_asmcode[7:0] $1\dec31_dec_sub22_asmcode[7:0] - attribute \src "libresoc.v:29224.5-29224.29" - switch \initial - attribute \src "libresoc.v:29224.9-29224.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'00101110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'00101111 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'01001001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'01001010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'01011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'01100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'10101000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'10101110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'10110011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'10110100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'10111001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'10111010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'11001001 - case - assign $1\dec31_dec_sub22_asmcode[7:0] 8'00000000 - end + assign $1\f_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 sync always - update \dec31_dec_sub22_asmcode $0\dec31_dec_sub22_asmcode[7:0] + sync init + update \f_badaddr_o $1\f_badaddr_o[44:0] end - attribute \src "libresoc.v:29278.3-29332.6" - process $proc$libresoc.v:29278$638 + attribute \src "libresoc.v:124172.7-124172.27" + process $proc$libresoc.v:124172$5185 assign { } { } + assign $1\f_fetch_err_o[0:0] 1'0 + sync always + sync init + update \f_fetch_err_o $1\f_fetch_err_o[0:0] + end + attribute \src "libresoc.v:124186.14-124186.42" + process $proc$libresoc.v:124186$5186 assign { } { } - assign $0\dec31_dec_sub22_inv_a[0:0] $1\dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:29279.5-29279.29" - switch \initial - attribute \src "libresoc.v:29279.9-29279.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - end + assign $1\ibus__adr[44:0] 45'000000000000000000000000000000000000000000000 sync always - update \dec31_dec_sub22_inv_a $0\dec31_dec_sub22_inv_a[0:0] + sync init + update \ibus__adr $1\ibus__adr[44:0] end - attribute \src "libresoc.v:29333.3-29387.6" - process $proc$libresoc.v:29333$639 + attribute \src "libresoc.v:124191.7-124191.23" + process $proc$libresoc.v:124191$5187 assign { } { } + assign $1\ibus__cyc[0:0] 1'0 + sync always + sync init + update \ibus__cyc $1\ibus__cyc[0:0] + end + attribute \src "libresoc.v:124200.13-124200.30" + process $proc$libresoc.v:124200$5188 assign { } { } - assign $0\dec31_dec_sub22_inv_out[0:0] $1\dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:29334.5-29334.29" - switch \initial - attribute \src "libresoc.v:29334.9-29334.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - end + assign $1\ibus__sel[7:0] 8'00000000 sync always - update \dec31_dec_sub22_inv_out $0\dec31_dec_sub22_inv_out[0:0] + sync init + update \ibus__sel $1\ibus__sel[7:0] end - attribute \src "libresoc.v:29388.3-29442.6" - process $proc$libresoc.v:29388$640 + attribute \src "libresoc.v:124205.7-124205.23" + process $proc$libresoc.v:124205$5189 assign { } { } + assign $1\ibus__stb[0:0] 1'0 + sync always + sync init + update \ibus__stb $1\ibus__stb[0:0] + end + attribute \src "libresoc.v:124209.14-124209.47" + process $proc$libresoc.v:124209$5190 assign { } { } - assign $0\dec31_dec_sub22_cry_out[0:0] $1\dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:29389.5-29389.29" - switch \initial - attribute \src "libresoc.v:29389.9-29389.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - end + assign $1\ibus_rdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always - update \dec31_dec_sub22_cry_out $0\dec31_dec_sub22_cry_out[0:0] + sync init + update \ibus_rdata $1\ibus_rdata[63:0] end - attribute \src "libresoc.v:29443.3-29497.6" - process $proc$libresoc.v:29443$641 + attribute \src "libresoc.v:124242.3-124243.39" + process $proc$libresoc.v:124242$5134 assign { } { } + assign $0\f_badaddr_o[44:0] \f_badaddr_o$next + sync posedge \clk + update \f_badaddr_o $0\f_badaddr_o[44:0] + end + attribute \src "libresoc.v:124244.3-124245.43" + process $proc$libresoc.v:124244$5135 assign { } { } - assign $0\dec31_dec_sub22_br[0:0] $1\dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:29444.5-29444.29" - switch \initial - attribute \src "libresoc.v:29444.9-29444.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - case - assign $1\dec31_dec_sub22_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub22_br $0\dec31_dec_sub22_br[0:0] + assign $0\f_fetch_err_o[0:0] \f_fetch_err_o$next + sync posedge \clk + update \f_fetch_err_o $0\f_fetch_err_o[0:0] end - attribute \src "libresoc.v:29498.3-29552.6" - process $proc$libresoc.v:29498$642 + attribute \src "libresoc.v:124246.3-124247.35" + process $proc$libresoc.v:124246$5136 assign { } { } + assign $0\ibus__adr[44:0] \ibus__adr$next + sync posedge \clk + update \ibus__adr $0\ibus__adr[44:0] + end + attribute \src "libresoc.v:124248.3-124249.37" + process $proc$libresoc.v:124248$5137 assign { } { } - assign $0\dec31_dec_sub22_sgn_ext[0:0] $1\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:29499.5-29499.29" + assign $0\ibus_rdata[63:0] \ibus_rdata$next + sync posedge \clk + update \ibus_rdata $0\ibus_rdata[63:0] + end + attribute \src "libresoc.v:124250.3-124251.35" + process $proc$libresoc.v:124250$5138 + assign { } { } + assign $0\ibus__sel[7:0] \ibus__sel$next + sync posedge \clk + update \ibus__sel $0\ibus__sel[7:0] + end + attribute \src "libresoc.v:124252.3-124253.35" + process $proc$libresoc.v:124252$5139 + assign { } { } + assign $0\ibus__stb[0:0] \ibus__stb$next + sync posedge \clk + update \ibus__stb $0\ibus__stb[0:0] + end + attribute \src "libresoc.v:124254.3-124255.35" + process $proc$libresoc.v:124254$5140 + assign { } { } + assign $0\ibus__cyc[0:0] \ibus__cyc$next + sync posedge \clk + update \ibus__cyc $0\ibus__cyc[0:0] + end + attribute \src "libresoc.v:124256.3-124283.6" + process $proc$libresoc.v:124256$5141 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus__cyc$next[0:0]$5142 $4\ibus__cyc$next[0:0]$5146 + attribute \src "libresoc.v:124257.5-124257.29" switch \initial - attribute \src "libresoc.v:29499.9-29499.17" + attribute \src "libresoc.v:124257.9-124257.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + assign $1\ibus__cyc$next[0:0]$5143 $2\ibus__cyc$next[0:0]$5144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" + switch { \$3 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\ibus__cyc$next[0:0]$5144 $3\ibus__cyc$next[0:0]$5145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__cyc$next[0:0]$5145 1'0 + case + assign $3\ibus__cyc$next[0:0]$5145 \ibus__cyc + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\ibus__cyc$next[0:0]$5144 1'1 + case + assign $2\ibus__cyc$next[0:0]$5144 \ibus__cyc + end + case + assign $1\ibus__cyc$next[0:0]$5143 \ibus__cyc + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 1'1 assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + assign $4\ibus__cyc$next[0:0]$5146 1'0 case - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + assign $4\ibus__cyc$next[0:0]$5146 $1\ibus__cyc$next[0:0]$5143 end sync always - update \dec31_dec_sub22_sgn_ext $0\dec31_dec_sub22_sgn_ext[0:0] + update \ibus__cyc$next $0\ibus__cyc$next[0:0]$5142 end - attribute \src "libresoc.v:29553.3-29607.6" - process $proc$libresoc.v:29553$643 + attribute \src "libresoc.v:124284.3-124311.6" + process $proc$libresoc.v:124284$5147 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_internal_op[6:0] $1\dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:29554.5-29554.29" + assign { } { } + assign $0\ibus__stb$next[0:0]$5148 $4\ibus__stb$next[0:0]$5152 + attribute \src "libresoc.v:124285.5-124285.29" switch \initial - attribute \src "libresoc.v:29554.9-29554.17" + attribute \src "libresoc.v:124285.9-124285.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0011100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + assign $1\ibus__stb$next[0:0]$5149 $2\ibus__stb$next[0:0]$5150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" + switch { \$13 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\ibus__stb$next[0:0]$5150 $3\ibus__stb$next[0:0]$5151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__stb$next[0:0]$5151 1'0 + case + assign $3\ibus__stb$next[0:0]$5151 \ibus__stb + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\ibus__stb$next[0:0]$5150 1'1 + case + assign $2\ibus__stb$next[0:0]$5150 \ibus__stb + end + case + assign $1\ibus__stb$next[0:0]$5149 \ibus__stb + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 1'1 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + assign $4\ibus__stb$next[0:0]$5152 1'0 case - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000000 + assign $4\ibus__stb$next[0:0]$5152 $1\ibus__stb$next[0:0]$5149 end sync always - update \dec31_dec_sub22_internal_op $0\dec31_dec_sub22_internal_op[6:0] + update \ibus__stb$next $0\ibus__stb$next[0:0]$5148 end - attribute \src "libresoc.v:29608.3-29662.6" - process $proc$libresoc.v:29608$644 + attribute \src "libresoc.v:124312.3-124339.6" + process $proc$libresoc.v:124312$5153 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_rsrv[0:0] $1\dec31_dec_sub22_rsrv[0:0] - attribute \src "libresoc.v:29609.5-29609.29" + assign { } { } + assign $0\ibus__sel$next[7:0]$5154 $4\ibus__sel$next[7:0]$5158 + attribute \src "libresoc.v:124313.5-124313.29" switch \initial - attribute \src "libresoc.v:29609.9-29609.17" + attribute \src "libresoc.v:124313.9-124313.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + assign $1\ibus__sel$next[7:0]$5155 $2\ibus__sel$next[7:0]$5156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" + switch { \$23 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\ibus__sel$next[7:0]$5156 $3\ibus__sel$next[7:0]$5157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__sel$next[7:0]$5157 8'00000000 + case + assign $3\ibus__sel$next[7:0]$5157 \ibus__sel + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\ibus__sel$next[7:0]$5156 8'11111111 + case + assign $2\ibus__sel$next[7:0]$5156 \ibus__sel + end + case + assign $1\ibus__sel$next[7:0]$5155 \ibus__sel + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 1'1 assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + assign $4\ibus__sel$next[7:0]$5158 8'00000000 case - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + assign $4\ibus__sel$next[7:0]$5158 $1\ibus__sel$next[7:0]$5155 end sync always - update \dec31_dec_sub22_rsrv $0\dec31_dec_sub22_rsrv[0:0] + update \ibus__sel$next $0\ibus__sel$next[7:0]$5154 end - attribute \src "libresoc.v:29663.3-29717.6" - process $proc$libresoc.v:29663$645 + attribute \src "libresoc.v:124340.3-124364.6" + process $proc$libresoc.v:124340$5159 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_is_32b[0:0] $1\dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:29664.5-29664.29" + assign { } { } + assign $0\ibus_rdata$next[63:0]$5160 $4\ibus_rdata$next[63:0]$5164 + attribute \src "libresoc.v:124341.5-124341.29" switch \initial - attribute \src "libresoc.v:29664.9-29664.17" + attribute \src "libresoc.v:124341.9-124341.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\ibus_rdata$next[63:0]$5161 $2\ibus_rdata$next[63:0]$5162 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" + switch { \$33 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\ibus_rdata$next[63:0]$5162 $3\ibus_rdata$next[63:0]$5163 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + switch \$39 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus_rdata$next[63:0]$5163 \ibus__dat_r + case + assign $3\ibus_rdata$next[63:0]$5163 \ibus_rdata + end + case + assign $2\ibus_rdata$next[63:0]$5162 \ibus_rdata + end + case + assign $1\ibus_rdata$next[63:0]$5161 \ibus_rdata + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 1'1 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $4\ibus_rdata$next[63:0]$5164 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $4\ibus_rdata$next[63:0]$5164 $1\ibus_rdata$next[63:0]$5161 end sync always - update \dec31_dec_sub22_is_32b $0\dec31_dec_sub22_is_32b[0:0] + update \ibus_rdata$next $0\ibus_rdata$next[63:0]$5160 end - attribute \src "libresoc.v:29718.3-29772.6" - process $proc$libresoc.v:29718$646 + attribute \src "libresoc.v:124365.3-124387.6" + process $proc$libresoc.v:124365$5165 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_sgn[0:0] $1\dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:29719.5-29719.29" + assign { } { } + assign $0\ibus__adr$next[44:0]$5166 $3\ibus__adr$next[44:0]$5169 + attribute \src "libresoc.v:124366.5-124366.29" switch \initial - attribute \src "libresoc.v:29719.9-29719.17" + attribute \src "libresoc.v:124366.9-124366.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + assign $1\ibus__adr$next[44:0]$5167 $2\ibus__adr$next[44:0]$5168 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" + switch { \$43 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign $2\ibus__adr$next[44:0]$5168 \ibus__adr + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\ibus__adr$next[44:0]$5168 \a_pc_i [47:3] + case + assign $2\ibus__adr$next[44:0]$5168 \ibus__adr + end + case + assign $1\ibus__adr$next[44:0]$5167 \ibus__adr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 1'1 assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + assign $3\ibus__adr$next[44:0]$5169 45'000000000000000000000000000000000000000000000 case - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + assign $3\ibus__adr$next[44:0]$5169 $1\ibus__adr$next[44:0]$5167 end sync always - update \dec31_dec_sub22_sgn $0\dec31_dec_sub22_sgn[0:0] + update \ibus__adr$next $0\ibus__adr$next[44:0]$5166 end - attribute \src "libresoc.v:29773.3-29827.6" - process $proc$libresoc.v:29773$647 + attribute \src "libresoc.v:124388.3-124410.6" + process $proc$libresoc.v:124388$5170 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_lk[0:0] $1\dec31_dec_sub22_lk[0:0] - attribute \src "libresoc.v:29774.5-29774.29" + assign { } { } + assign $0\f_fetch_err_o$next[0:0]$5171 $3\f_fetch_err_o$next[0:0]$5174 + attribute \src "libresoc.v:124389.5-124389.29" switch \initial - attribute \src "libresoc.v:29774.9-29774.17" + attribute \src "libresoc.v:124389.9-124389.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 + assign $1\f_fetch_err_o$next[0:0]$5172 $2\f_fetch_err_o$next[0:0]$5173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + switch { \$47 \$45 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\f_fetch_err_o$next[0:0]$5173 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\f_fetch_err_o$next[0:0]$5173 1'0 + case + assign $2\f_fetch_err_o$next[0:0]$5173 \f_fetch_err_o + end + case + assign $1\f_fetch_err_o$next[0:0]$5172 \f_fetch_err_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 1'1 assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 + assign $3\f_fetch_err_o$next[0:0]$5174 1'0 case - assign $1\dec31_dec_sub22_lk[0:0] 1'0 + assign $3\f_fetch_err_o$next[0:0]$5174 $1\f_fetch_err_o$next[0:0]$5172 end sync always - update \dec31_dec_sub22_lk $0\dec31_dec_sub22_lk[0:0] + update \f_fetch_err_o$next $0\f_fetch_err_o$next[0:0]$5171 end - attribute \src "libresoc.v:29828.3-29882.6" - process $proc$libresoc.v:29828$648 + attribute \src "libresoc.v:124411.3-124430.6" + process $proc$libresoc.v:124411$5175 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_sgl_pipe[0:0] $1\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "libresoc.v:29829.5-29829.29" + assign { } { } + assign $0\f_badaddr_o$next[44:0]$5176 $3\f_badaddr_o$next[44:0]$5179 + attribute \src "libresoc.v:124412.5-124412.29" switch \initial - attribute \src "libresoc.v:29829.9-29829.17" + attribute \src "libresoc.v:124412.9-124412.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + assign $1\f_badaddr_o$next[44:0]$5177 $2\f_badaddr_o$next[44:0]$5178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + switch { \$51 \$49 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\f_badaddr_o$next[44:0]$5178 \ibus__adr + case + assign $2\f_badaddr_o$next[44:0]$5178 \f_badaddr_o + end + case + assign $1\f_badaddr_o$next[44:0]$5177 \f_badaddr_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 1'1 assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + assign $3\f_badaddr_o$next[44:0]$5179 45'000000000000000000000000000000000000000000000 case - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'0 + assign $3\f_badaddr_o$next[44:0]$5179 $1\f_badaddr_o$next[44:0]$5177 end sync always - update \dec31_dec_sub22_sgl_pipe $0\dec31_dec_sub22_sgl_pipe[0:0] + update \f_badaddr_o$next $0\f_badaddr_o$next[44:0]$5176 end - attribute \src "libresoc.v:29883.3-29937.6" - process $proc$libresoc.v:29883$649 + attribute \src "libresoc.v:124431.3-124440.6" + process $proc$libresoc.v:124431$5180 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_form[4:0] $1\dec31_dec_sub22_form[4:0] - attribute \src "libresoc.v:29884.5-29884.29" + assign $0\a_busy_o[0:0] $1\a_busy_o[0:0] + attribute \src "libresoc.v:124432.5-124432.29" switch \initial - attribute \src "libresoc.v:29884.9-29884.17" + attribute \src "libresoc.v:124432.9-124432.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 1'1 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\a_busy_o[0:0] \ibus__cyc case - assign $1\dec31_dec_sub22_form[4:0] 5'00000 + assign $1\a_busy_o[0:0] 1'0 end sync always - update \dec31_dec_sub22_form $0\dec31_dec_sub22_form[4:0] + update \a_busy_o $0\a_busy_o[0:0] end - attribute \src "libresoc.v:29938.3-29992.6" - process $proc$libresoc.v:29938$650 + attribute \src "libresoc.v:124441.3-124458.6" + process $proc$libresoc.v:124441$5181 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_in1_sel[2:0] $1\dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:29939.5-29939.29" + assign $0\f_busy_o[0:0] $1\f_busy_o[0:0] + attribute \src "libresoc.v:124442.5-124442.29" switch \initial - attribute \src "libresoc.v:29939.9-29939.17" + attribute \src "libresoc.v:124442.9-124442.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 1'1 assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + assign $1\f_busy_o[0:0] $2\f_busy_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:96" + switch \f_fetch_err_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\f_busy_o[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\f_busy_o[0:0] \ibus__cyc + end case - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + assign $1\f_busy_o[0:0] 1'0 end sync always - update \dec31_dec_sub22_in1_sel $0\dec31_dec_sub22_in1_sel[2:0] + update \f_busy_o $0\f_busy_o[0:0] end - attribute \src "libresoc.v:29993.3-30047.6" - process $proc$libresoc.v:29993$651 + attribute \src "libresoc.v:124459.3-124476.6" + process $proc$libresoc.v:124459$5182 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_in2_sel[3:0] $1\dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:29994.5-29994.29" + assign $0\f_instr_o[63:0] $1\f_instr_o[63:0] + attribute \src "libresoc.v:124460.5-124460.29" switch \initial - attribute \src "libresoc.v:29994.9-29994.17" + attribute \src "libresoc.v:124460.9-124460.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 1'1 assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + assign $1\f_instr_o[63:0] $2\f_instr_o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:96" + switch \f_fetch_err_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\f_instr_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\f_instr_o[63:0] \ibus_rdata + end case - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + assign $1\f_instr_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \dec31_dec_sub22_in2_sel $0\dec31_dec_sub22_in2_sel[3:0] + update \f_instr_o $0\f_instr_o[63:0] end - attribute \src "libresoc.v:30048.3-30102.6" - process $proc$libresoc.v:30048$652 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_in3_sel[1:0] $1\dec31_dec_sub22_in3_sel[1:0] - attribute \src "libresoc.v:30049.5-30049.29" - switch \initial - attribute \src "libresoc.v:30049.9-30049.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + connect \$9 $or$libresoc.v:124216$5108_Y + connect \$11 $not$libresoc.v:124217$5109_Y + connect \$13 $and$libresoc.v:124218$5110_Y + connect \$15 $or$libresoc.v:124219$5111_Y + connect \$17 $not$libresoc.v:124220$5112_Y + connect \$1 $not$libresoc.v:124221$5113_Y + connect \$19 $or$libresoc.v:124222$5114_Y + connect \$21 $not$libresoc.v:124223$5115_Y + connect \$23 $and$libresoc.v:124224$5116_Y + connect \$25 $or$libresoc.v:124225$5117_Y + connect \$27 $not$libresoc.v:124226$5118_Y + connect \$29 $or$libresoc.v:124227$5119_Y + connect \$31 $not$libresoc.v:124228$5120_Y + connect \$33 $and$libresoc.v:124229$5121_Y + connect \$35 $or$libresoc.v:124230$5122_Y + connect \$37 $not$libresoc.v:124231$5123_Y + connect \$3 $and$libresoc.v:124232$5124_Y + connect \$39 $or$libresoc.v:124233$5125_Y + connect \$41 $not$libresoc.v:124234$5126_Y + connect \$43 $and$libresoc.v:124235$5127_Y + connect \$45 $and$libresoc.v:124236$5128_Y + connect \$47 $not$libresoc.v:124237$5129_Y + connect \$49 $and$libresoc.v:124238$5130_Y + connect \$51 $not$libresoc.v:124239$5131_Y + connect \$5 $or$libresoc.v:124240$5132_Y + connect \$7 $not$libresoc.v:124241$5133_Y + connect \a_stall_i 1'0 + connect \f_stall_i 1'0 +end +attribute \src "libresoc.v:124483.1-124804.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.input" +attribute \generator "nMigen" +module \input + attribute \src "libresoc.v:124767.3-124778.6" + wire width 64 $0\a[63:0] + attribute \src "libresoc.v:124484.7-124484.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:124779.3-124797.6" + wire width 2 $0\xer_ca$23[1:0]$5194 + attribute \src "libresoc.v:124767.3-124778.6" + wire width 64 $1\a[63:0] + attribute \src "libresoc.v:124779.3-124797.6" + wire width 2 $1\xer_ca$23[1:0]$5195 + attribute \src "libresoc.v:124766.18-124766.100" + wire width 64 $not$libresoc.v:124766$5191_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + wire width 64 \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" + wire width 64 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 40 \alu_op__data_len$18 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 25 \alu_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 26 \alu_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \alu_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 13 \alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 36 \alu_op__input_carry$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 41 \alu_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 24 \alu_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \alu_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \alu_op__invert_out$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \alu_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \alu_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \alu_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \alu_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \alu_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \alu_op__write_cr0$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" + wire width 64 \b + attribute \src "libresoc.v:124484.7-124484.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 46 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 23 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 42 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 43 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 22 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 output 45 \xer_ca$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 44 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + cell $not $not$libresoc.v:124766$5191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \Y $not$libresoc.v:124766$5191_Y + end + attribute \src "libresoc.v:124484.7-124484.20" + process $proc$libresoc.v:124484$5196 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:124767.3-124778.6" + process $proc$libresoc.v:124767$5192 + assign { } { } + assign $0\a[63:0] $1\a[63:0] + attribute \src "libresoc.v:124768.5-124768.29" + switch \initial + attribute \src "libresoc.v:124768.9-124768.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" + switch \alu_op__invert_in attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + assign $1\a[63:0] \$24 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 case - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + assign { } { } + assign $1\a[63:0] \ra end sync always - update \dec31_dec_sub22_in3_sel $0\dec31_dec_sub22_in3_sel[1:0] + update \a $0\a[63:0] end - attribute \src "libresoc.v:30103.3-30157.6" - process $proc$libresoc.v:30103$653 + attribute \src "libresoc.v:124779.3-124797.6" + process $proc$libresoc.v:124779$5193 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_out_sel[1:0] $1\dec31_dec_sub22_out_sel[1:0] - attribute \src "libresoc.v:30104.5-30104.29" + assign $0\xer_ca$23[1:0]$5194 $1\xer_ca$23[1:0]$5195 + attribute \src "libresoc.v:124780.5-124780.29" switch \initial - attribute \src "libresoc.v:30104.9-30104.17" + attribute \src "libresoc.v:124780.9-124780.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:55" + switch \alu_op__input_carry attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 2'00 assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + assign $1\xer_ca$23[1:0]$5195 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 2'01 assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + assign $1\xer_ca$23[1:0]$5195 2'11 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 2'10 assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + assign $1\xer_ca$23[1:0]$5195 \xer_ca case - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + assign $1\xer_ca$23[1:0]$5195 2'00 end sync always - update \dec31_dec_sub22_out_sel $0\dec31_dec_sub22_out_sel[1:0] + update \xer_ca$23 $0\xer_ca$23[1:0]$5194 + end + connect \$24 $not$libresoc.v:124766$5191_Y + connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$22 \xer_so + connect \rb$21 \rb + connect \b \rb + connect \ra$20 \a +end +attribute \src "libresoc.v:124808.1-125130.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.input" +attribute \generator "nMigen" +module \input$113 + attribute \src "libresoc.v:125092.3-125103.6" + wire width 64 $0\a[63:0] + attribute \src "libresoc.v:124809.7-124809.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:125104.3-125122.6" + wire width 2 $0\xer_ca$23[1:0]$5200 + attribute \src "libresoc.v:125092.3-125103.6" + wire width 64 $1\a[63:0] + attribute \src "libresoc.v:125104.3-125122.6" + wire width 2 $1\xer_ca$23[1:0]$5201 + attribute \src "libresoc.v:125091.18-125091.100" + wire width 64 $not$libresoc.v:125091$5197_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + wire width 64 \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" + wire width 64 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" + wire width 64 \b + attribute \src "libresoc.v:124809.7-124809.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 46 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 23 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 18 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 41 \ra$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 42 \rb$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 43 \rc$21 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 25 \sr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 26 \sr_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \sr_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 34 \sr_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \sr_op__input_cr$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 17 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 40 \sr_op__insn$18 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 24 \sr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \sr_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \sr_op__invert_in$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \sr_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \sr_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \sr_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \sr_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \sr_op__output_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \sr_op__output_cr$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \sr_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \sr_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \sr_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 22 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 output 45 \xer_ca$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 44 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + cell $not $not$libresoc.v:125091$5197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \Y $not$libresoc.v:125091$5197_Y end - attribute \src "libresoc.v:30158.3-30212.6" - process $proc$libresoc.v:30158$654 + attribute \src "libresoc.v:124809.7-124809.20" + process $proc$libresoc.v:124809$5202 assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:125092.3-125103.6" + process $proc$libresoc.v:125092$5198 assign { } { } - assign $0\dec31_dec_sub22_cr_in[2:0] $1\dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:30159.5-30159.29" + assign $0\a[63:0] $1\a[63:0] + attribute \src "libresoc.v:125093.5-125093.29" switch \initial - attribute \src "libresoc.v:30159.9-30159.17" + attribute \src "libresoc.v:125093.9-125093.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" + switch \sr_op__invert_in attribute \src "libresoc.v:0.0-0.0" - case 5'11100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + assign $1\a[63:0] \$24 attribute \src "libresoc.v:0.0-0.0" - case 5'10110 + case assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + assign $1\a[63:0] \ra + end + sync always + update \a $0\a[63:0] + end + attribute \src "libresoc.v:125104.3-125122.6" + process $proc$libresoc.v:125104$5199 + assign { } { } + assign { } { } + assign $0\xer_ca$23[1:0]$5200 $1\xer_ca$23[1:0]$5201 + attribute \src "libresoc.v:125105.5-125105.29" + switch \initial + attribute \src "libresoc.v:125105.9-125105.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:55" + switch \sr_op__input_carry attribute \src "libresoc.v:0.0-0.0" - case 5'10100 + case 2'00 assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + assign $1\xer_ca$23[1:0]$5201 2'00 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 2'01 assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + assign $1\xer_ca$23[1:0]$5201 2'11 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 + case 2'10 assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + assign $1\xer_ca$23[1:0]$5201 \xer_ca case - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + assign $1\xer_ca$23[1:0]$5201 2'00 end sync always - update \dec31_dec_sub22_cr_in $0\dec31_dec_sub22_cr_in[2:0] + update \xer_ca$23 $0\xer_ca$23[1:0]$5200 + end + connect \$24 $not$libresoc.v:125091$5197_Y + connect \rc$21 \rc + connect { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$22 \xer_so + connect \rb$20 \b + connect \b \rb + connect \ra$19 \a +end +attribute \src "libresoc.v:125134.1-125431.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.input" +attribute \generator "nMigen" +module \input$50 + attribute \src "libresoc.v:125413.3-125424.6" + wire width 64 $0\b[63:0] + attribute \src "libresoc.v:125135.7-125135.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:125413.3-125424.6" + wire width 64 $1\b[63:0] + attribute \src "libresoc.v:125412.18-125412.100" + wire width 64 $not$libresoc.v:125412$5203_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" + wire width 64 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" + wire width 64 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" + wire width 64 \b + attribute \src "libresoc.v:125135.7-125135.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 39 \logical_op__data_len$18 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 24 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 25 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 33 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 40 \logical_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 23 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 44 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 22 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 41 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 42 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 43 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" + cell $not $not$libresoc.v:125412$5203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \rb + connect \Y $not$libresoc.v:125412$5203_Y end - attribute \src "libresoc.v:30213.3-30267.6" - process $proc$libresoc.v:30213$655 + attribute \src "libresoc.v:125135.7-125135.20" + process $proc$libresoc.v:125135$5205 assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:125413.3-125424.6" + process $proc$libresoc.v:125413$5204 assign { } { } - assign $0\dec31_dec_sub22_cr_out[2:0] $1\dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:30214.5-30214.29" + assign $0\b[63:0] $1\b[63:0] + attribute \src "libresoc.v:125414.5-125414.29" switch \initial - attribute \src "libresoc.v:30214.9-30214.17" + attribute \src "libresoc.v:125414.9-125414.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:42" + switch \logical_op__invert_in attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + assign $1\b[63:0] \$23 attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 case - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + assign { } { } + assign $1\b[63:0] \rb end sync always - update \dec31_dec_sub22_cr_out $0\dec31_dec_sub22_cr_out[2:0] + update \b $0\b[63:0] end - connect \opcode_switch \opcode_in [10:6] + connect \$23 $not$libresoc.v:125412$5203_Y + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$22 \xer_so + connect \rb$21 \b + connect \ra$20 \a + connect \a \ra end -attribute \src "libresoc.v:30273.1-31708.10" +attribute \src "libresoc.v:125435.1-125732.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub23" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.input" attribute \generator "nMigen" -module \dec31_dec_sub23 - attribute \src "libresoc.v:30776.3-30824.6" - wire width 8 $0\dec31_dec_sub23_asmcode[7:0] - attribute \src "libresoc.v:30972.3-31020.6" - wire $0\dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:31609.3-31657.6" - wire width 3 $0\dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:31658.3-31706.6" - wire width 3 $0\dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:30727.3-30775.6" - wire width 2 $0\dec31_dec_sub23_cry_in[1:0] - attribute \src "libresoc.v:30923.3-30971.6" - wire $0\dec31_dec_sub23_cry_out[0:0] - attribute \src "libresoc.v:31364.3-31412.6" - wire width 5 $0\dec31_dec_sub23_form[4:0] - attribute \src "libresoc.v:30531.3-30579.6" - wire width 12 $0\dec31_dec_sub23_function_unit[11:0] - attribute \src "libresoc.v:31413.3-31461.6" - wire width 3 $0\dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:31462.3-31510.6" - wire width 4 $0\dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:31511.3-31559.6" - wire width 2 $0\dec31_dec_sub23_in3_sel[1:0] - attribute \src "libresoc.v:31070.3-31118.6" - wire width 7 $0\dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:30825.3-30873.6" - wire $0\dec31_dec_sub23_inv_a[0:0] - attribute \src "libresoc.v:30874.3-30922.6" - wire $0\dec31_dec_sub23_inv_out[0:0] - attribute \src "libresoc.v:31168.3-31216.6" - wire $0\dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:30580.3-30628.6" - wire width 4 $0\dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:31266.3-31314.6" - wire $0\dec31_dec_sub23_lk[0:0] - attribute \src "libresoc.v:31560.3-31608.6" - wire width 2 $0\dec31_dec_sub23_out_sel[1:0] - attribute \src "libresoc.v:30678.3-30726.6" - wire width 2 $0\dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:31119.3-31167.6" - wire $0\dec31_dec_sub23_rsrv[0:0] - attribute \src "libresoc.v:31315.3-31363.6" - wire $0\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "libresoc.v:31217.3-31265.6" - wire $0\dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:31021.3-31069.6" - wire $0\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:30629.3-30677.6" - wire width 2 $0\dec31_dec_sub23_upd[1:0] - attribute \src "libresoc.v:30274.7-30274.20" +module \input$78 + attribute \src "libresoc.v:125714.3-125725.6" + wire width 64 $0\a[63:0] + attribute \src "libresoc.v:125436.7-125436.20" wire $0\initial[0:0] - attribute \src "libresoc.v:30776.3-30824.6" - wire width 8 $1\dec31_dec_sub23_asmcode[7:0] - attribute \src "libresoc.v:30972.3-31020.6" - wire $1\dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:31609.3-31657.6" - wire width 3 $1\dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:31658.3-31706.6" - wire width 3 $1\dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:30727.3-30775.6" - wire width 2 $1\dec31_dec_sub23_cry_in[1:0] - attribute \src "libresoc.v:30923.3-30971.6" - wire $1\dec31_dec_sub23_cry_out[0:0] - attribute \src "libresoc.v:31364.3-31412.6" - wire width 5 $1\dec31_dec_sub23_form[4:0] - attribute \src "libresoc.v:30531.3-30579.6" - wire width 12 $1\dec31_dec_sub23_function_unit[11:0] - attribute \src "libresoc.v:31413.3-31461.6" - wire width 3 $1\dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:31462.3-31510.6" - wire width 4 $1\dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:31511.3-31559.6" - wire width 2 $1\dec31_dec_sub23_in3_sel[1:0] - attribute \src "libresoc.v:31070.3-31118.6" - wire width 7 $1\dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:30825.3-30873.6" - wire $1\dec31_dec_sub23_inv_a[0:0] - attribute \src "libresoc.v:30874.3-30922.6" - wire $1\dec31_dec_sub23_inv_out[0:0] - attribute \src "libresoc.v:31168.3-31216.6" - wire $1\dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:30580.3-30628.6" - wire width 4 $1\dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:31266.3-31314.6" - wire $1\dec31_dec_sub23_lk[0:0] - attribute \src "libresoc.v:31560.3-31608.6" - wire width 2 $1\dec31_dec_sub23_out_sel[1:0] - attribute \src "libresoc.v:30678.3-30726.6" - wire width 2 $1\dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:31119.3-31167.6" - wire $1\dec31_dec_sub23_rsrv[0:0] - attribute \src "libresoc.v:31315.3-31363.6" - wire $1\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "libresoc.v:31217.3-31265.6" - wire $1\dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:31021.3-31069.6" - wire $1\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:30629.3-30677.6" - wire width 2 $1\dec31_dec_sub23_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub23_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub23_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub23_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub23_cr_out + attribute \src "libresoc.v:125714.3-125725.6" + wire width 64 $1\a[63:0] + attribute \src "libresoc.v:125713.18-125713.100" + wire width 64 $not$libresoc.v:125713$5206_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + wire width 64 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" + wire width 64 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" + wire width 64 \b + attribute \src "libresoc.v:125436.7-125436.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 39 \logical_op__data_len$18 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 24 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 25 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \logical_op__imm_data__ok$5 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub23_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub23_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub23_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 33 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 40 \logical_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 23 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 44 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 22 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 41 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 42 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 43 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + cell $not $not$libresoc.v:125713$5206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \Y $not$libresoc.v:125713$5206_Y + end + attribute \src "libresoc.v:125436.7-125436.20" + process $proc$libresoc.v:125436$5208 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:125714.3-125725.6" + process $proc$libresoc.v:125714$5207 + assign { } { } + assign $0\a[63:0] $1\a[63:0] + attribute \src "libresoc.v:125715.5-125715.29" + switch \initial + attribute \src "libresoc.v:125715.9-125715.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" + switch \logical_op__invert_in + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a[63:0] \$23 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\a[63:0] \ra + end + sync always + update \a $0\a[63:0] + end + connect \$23 $not$libresoc.v:125713$5206_Y + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$22 \xer_so + connect \rb$21 \rb + connect \b \rb + connect \ra$20 \a +end +attribute \src "libresoc.v:125736.1-125986.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.input" +attribute \generator "nMigen" +module \input$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" + wire width 64 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" + wire width 64 \b attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -44609,39 +198118,111 @@ module \dec31_dec_sub23 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub23_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub23_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub23_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub23_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 18 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 19 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 12 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 28 \mul_op__insn$13 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \mul_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -44716,18587 +198297,10303 @@ module \dec31_dec_sub23 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub23_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub23_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub23_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub23_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub23_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub23_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub23_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub23_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub23_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub23_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub23_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub23_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub23_upd - attribute \src "libresoc.v:30274.7-30274.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 17 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 23 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 24 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 22 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 21 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 25 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 32 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 16 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 13 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 29 \ra$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 30 \rb$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 15 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 31 \xer_so$16 + connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$16 \xer_so + connect \rb$15 \rb + connect \b \rb + connect \ra$14 \a + connect \a \ra +end +attribute \src "libresoc.v:125990.1-126209.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.int" +attribute \generator "nMigen" +module \int + attribute \src "libresoc.v:126115.3-126121.6" + wire width 5 $0$memwr$\memory$libresoc.v:126120$5241_ADDR[4:0]$5250 + attribute \src "libresoc.v:126115.3-126121.6" + wire width 64 $0$memwr$\memory$libresoc.v:126120$5241_DATA[63:0]$5251 + attribute \src "libresoc.v:126115.3-126121.6" + wire width 64 $0$memwr$\memory$libresoc.v:126120$5241_EN[63:0]$5252 + attribute \src "libresoc.v:126115.3-126121.6" + wire width 5 $0\_0_[4:0] + attribute \src "libresoc.v:126115.3-126121.6" + wire width 5 $0\_1_[4:0] + attribute \src "libresoc.v:126115.3-126121.6" + wire width 5 $0\_2_[4:0] + attribute \src "libresoc.v:126115.3-126121.6" + wire width 5 $0\_3_[4:0] + attribute \src "libresoc.v:126144.3-126153.6" + wire width 64 $0\dmi__data_o[63:0] + attribute \src "libresoc.v:125991.7-125991.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:126135.3-126143.6" + wire $0\ren_delay$10$next[0:0]$5261 + attribute \src "libresoc.v:126068.3-126069.43" + wire $0\ren_delay$10[0:0]$5243 + attribute \src "libresoc.v:126034.7-126034.28" + wire $0\ren_delay$10[0:0]$5309 + attribute \src "libresoc.v:126164.3-126172.6" + wire $0\ren_delay$8$next[0:0]$5266 + attribute \src "libresoc.v:126072.3-126073.41" + wire $0\ren_delay$8[0:0]$5247 + attribute \src "libresoc.v:126038.7-126038.27" + wire $0\ren_delay$8[0:0]$5311 + attribute \src "libresoc.v:126183.3-126191.6" + wire $0\ren_delay$9$next[0:0]$5270 + attribute \src "libresoc.v:126070.3-126071.41" + wire $0\ren_delay$9[0:0]$5245 + attribute \src "libresoc.v:126042.7-126042.27" + wire $0\ren_delay$9[0:0]$5313 + attribute \src "libresoc.v:126126.3-126134.6" + wire $0\ren_delay$next[0:0]$5258 + attribute \src "libresoc.v:126074.3-126075.35" + wire $0\ren_delay[0:0] + attribute \src "libresoc.v:126154.3-126163.6" + wire width 64 $0\src1__data_o[63:0] + attribute \src "libresoc.v:126173.3-126182.6" + wire width 64 $0\src2__data_o[63:0] + attribute \src "libresoc.v:126192.3-126201.6" + wire width 64 $0\src3__data_o[63:0] + attribute \src "libresoc.v:126144.3-126153.6" + wire width 64 $1\dmi__data_o[63:0] + attribute \src "libresoc.v:126135.3-126143.6" + wire $1\ren_delay$10$next[0:0]$5262 + attribute \src "libresoc.v:126164.3-126172.6" + wire $1\ren_delay$8$next[0:0]$5267 + attribute \src "libresoc.v:126183.3-126191.6" + wire $1\ren_delay$9$next[0:0]$5271 + attribute \src "libresoc.v:126126.3-126134.6" + wire $1\ren_delay$next[0:0]$5259 + attribute \src "libresoc.v:126032.7-126032.23" + wire $1\ren_delay[0:0] + attribute \src "libresoc.v:126154.3-126163.6" + wire width 64 $1\src1__data_o[63:0] + attribute \src "libresoc.v:126173.3-126182.6" + wire width 64 $1\src2__data_o[63:0] + attribute \src "libresoc.v:126192.3-126201.6" + wire width 64 $1\src3__data_o[63:0] + attribute \src "libresoc.v:126122.26-126122.32" + wire width 64 $memrd$\memory$libresoc.v:126122$5253_DATA + attribute \src "libresoc.v:126123.30-126123.36" + wire width 64 $memrd$\memory$libresoc.v:126123$5254_DATA + attribute \src "libresoc.v:126124.30-126124.36" + wire width 64 $memrd$\memory$libresoc.v:126124$5255_DATA + attribute \src "libresoc.v:126125.30-126125.36" + wire width 64 $memrd$\memory$libresoc.v:126125$5256_DATA + attribute \src "libresoc.v:0.0-0.0" + wire width 5 $memwr$\memory$libresoc.v:126120$5241_ADDR + attribute \src "libresoc.v:0.0-0.0" + wire width 64 $memwr$\memory$libresoc.v:126120$5241_DATA + attribute \src "libresoc.v:0.0-0.0" + wire width 64 $memwr$\memory$libresoc.v:126120$5241_EN + attribute \src "libresoc.v:126111.13-126111.16" + wire width 5 \_0_ + attribute \src "libresoc.v:126112.13-126112.16" + wire width 5 \_1_ + attribute \src "libresoc.v:126113.13-126113.16" + wire width 5 \_2_ + attribute \src "libresoc.v:126114.13-126114.16" + wire width 5 \_3_ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 17 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 input 15 \dest1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 14 \dest1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 16 \dest1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 input 2 \dmi__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 4 \dmi__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 3 \dmi__ren + attribute \src "libresoc.v:125991.7-125991.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:30274.7-30274.20" - process $proc$libresoc.v:30274$681 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 5 \memory_r_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 5 \memory_r_addr$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 5 \memory_r_addr$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 5 \memory_r_addr$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 5 \memory_w_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 64 \memory_w_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire \memory_w_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 input 6 \src1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 5 \src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 7 \src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 input 9 \src2__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 8 \src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \src2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 input 12 \src3__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 11 \src3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 13 \src3__ren + attribute \src "libresoc.v:126076.14-126076.20" + memory width 64 size 32 \memory + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5273 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5273 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 0 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5274 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5274 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 1 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5275 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5275 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 2 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5276 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5276 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 3 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5277 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5277 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 4 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5278 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5278 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 5 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5279 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5279 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 6 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5280 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5280 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 7 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5281 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5281 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 8 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5282 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5282 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 9 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5283 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5283 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 10 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5284 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5284 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 11 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5285 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5285 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 12 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5286 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5286 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 13 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5287 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5287 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 14 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5288 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5288 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 15 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5289 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5289 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 16 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5290 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5290 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 17 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5291 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5291 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 18 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5292 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5292 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 19 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5293 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5293 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 20 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5294 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5294 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 21 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5295 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5295 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 22 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5296 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5296 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 23 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5297 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5297 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 24 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5298 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5298 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 25 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5299 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5299 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 26 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5300 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5300 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 27 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5301 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5301 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 28 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5302 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5302 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 29 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5303 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5303 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 30 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5304 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5304 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 31 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:126122.26-126122.32" + cell $memrd $memrd$\memory$libresoc.v:126122$5253 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_0_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:126122$5253_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:126123.30-126123.36" + cell $memrd $memrd$\memory$libresoc.v:126123$5254 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_1_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:126123$5254_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:126124.30-126124.36" + cell $memrd $memrd$\memory$libresoc.v:126124$5255 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_2_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:126124$5255_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:126125.30-126125.36" + cell $memrd $memrd$\memory$libresoc.v:126125$5256 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_3_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:126125$5256_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:0.0-0.0" + cell $memwr $memwr$\memory$libresoc.v:0$5305 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \PRIORITY 5305 + parameter \WIDTH 64 + connect \ADDR $memwr$\memory$libresoc.v:126120$5241_ADDR + connect \CLK 1'x + connect \DATA $memwr$\memory$libresoc.v:126120$5241_DATA + connect \EN $memwr$\memory$libresoc.v:126120$5241_EN + end + attribute \src "libresoc.v:0.0-0.0" + process $proc$libresoc.v:0$5314 + sync always + sync init + end + attribute \src "libresoc.v:125991.7-125991.20" + process $proc$libresoc.v:125991$5306 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:30531.3-30579.6" - process $proc$libresoc.v:30531$657 + attribute \src "libresoc.v:126032.7-126032.23" + process $proc$libresoc.v:126032$5307 assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_function_unit[11:0] $1\dec31_dec_sub23_function_unit[11:0] - attribute \src "libresoc.v:30532.5-30532.29" - switch \initial - attribute \src "libresoc.v:30532.9-30532.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - case - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000000 - end + assign $1\ren_delay[0:0] 1'0 sync always - update \dec31_dec_sub23_function_unit $0\dec31_dec_sub23_function_unit[11:0] + sync init + update \ren_delay $1\ren_delay[0:0] end - attribute \src "libresoc.v:30580.3-30628.6" - process $proc$libresoc.v:30580$658 - assign { } { } + attribute \src "libresoc.v:126034.7-126034.28" + process $proc$libresoc.v:126034$5308 assign { } { } - assign $0\dec31_dec_sub23_ldst_len[3:0] $1\dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:30581.5-30581.29" - switch \initial - attribute \src "libresoc.v:30581.9-30581.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 - case - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0000 - end + assign $0\ren_delay$10[0:0]$5309 1'0 sync always - update \dec31_dec_sub23_ldst_len $0\dec31_dec_sub23_ldst_len[3:0] + sync init + update \ren_delay$10 $0\ren_delay$10[0:0]$5309 end - attribute \src "libresoc.v:30629.3-30677.6" - process $proc$libresoc.v:30629$659 + attribute \src "libresoc.v:126038.7-126038.27" + process $proc$libresoc.v:126038$5310 assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_upd[1:0] $1\dec31_dec_sub23_upd[1:0] - attribute \src "libresoc.v:30630.5-30630.29" - switch \initial - attribute \src "libresoc.v:30630.9-30630.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub23_upd[1:0] 2'00 - end + assign $0\ren_delay$8[0:0]$5311 1'0 sync always - update \dec31_dec_sub23_upd $0\dec31_dec_sub23_upd[1:0] + sync init + update \ren_delay$8 $0\ren_delay$8[0:0]$5311 end - attribute \src "libresoc.v:30678.3-30726.6" - process $proc$libresoc.v:30678$660 - assign { } { } + attribute \src "libresoc.v:126042.7-126042.27" + process $proc$libresoc.v:126042$5312 assign { } { } - assign $0\dec31_dec_sub23_rc_sel[1:0] $1\dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:30679.5-30679.29" - switch \initial - attribute \src "libresoc.v:30679.9-30679.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - end + assign $0\ren_delay$9[0:0]$5313 1'0 sync always - update \dec31_dec_sub23_rc_sel $0\dec31_dec_sub23_rc_sel[1:0] + sync init + update \ren_delay$9 $0\ren_delay$9[0:0]$5313 end - attribute \src "libresoc.v:30727.3-30775.6" - process $proc$libresoc.v:30727$661 + attribute \src "libresoc.v:126068.3-126069.43" + process $proc$libresoc.v:126068$5242 assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_cry_in[1:0] $1\dec31_dec_sub23_cry_in[1:0] - attribute \src "libresoc.v:30728.5-30728.29" - switch \initial - attribute \src "libresoc.v:30728.9-30728.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub23_cry_in $0\dec31_dec_sub23_cry_in[1:0] + assign $0\ren_delay$10[0:0]$5243 \ren_delay$10$next + sync posedge \coresync_clk + update \ren_delay$10 $0\ren_delay$10[0:0]$5243 end - attribute \src "libresoc.v:30776.3-30824.6" - process $proc$libresoc.v:30776$662 + attribute \src "libresoc.v:126070.3-126071.41" + process $proc$libresoc.v:126070$5244 assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_asmcode[7:0] $1\dec31_dec_sub23_asmcode[7:0] - attribute \src "libresoc.v:30777.5-30777.29" - switch \initial - attribute \src "libresoc.v:30777.9-30777.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01010001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01011011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01011100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01100000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01100001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01101010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01101011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'10101010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'10101011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'10110110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'10110111 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111101 - case - assign $1\dec31_dec_sub23_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub23_asmcode $0\dec31_dec_sub23_asmcode[7:0] + assign $0\ren_delay$9[0:0]$5245 \ren_delay$9$next + sync posedge \coresync_clk + update \ren_delay$9 $0\ren_delay$9[0:0]$5245 end - attribute \src "libresoc.v:30825.3-30873.6" - process $proc$libresoc.v:30825$663 + attribute \src "libresoc.v:126072.3-126073.41" + process $proc$libresoc.v:126072$5246 assign { } { } + assign $0\ren_delay$8[0:0]$5247 \ren_delay$8$next + sync posedge \coresync_clk + update \ren_delay$8 $0\ren_delay$8[0:0]$5247 + end + attribute \src "libresoc.v:126074.3-126075.35" + process $proc$libresoc.v:126074$5248 assign { } { } - assign $0\dec31_dec_sub23_inv_a[0:0] $1\dec31_dec_sub23_inv_a[0:0] - attribute \src "libresoc.v:30826.5-30826.29" - switch \initial - attribute \src "libresoc.v:30826.9-30826.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub23_inv_a $0\dec31_dec_sub23_inv_a[0:0] + assign $0\ren_delay[0:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[0:0] end - attribute \src "libresoc.v:30874.3-30922.6" - process $proc$libresoc.v:30874$664 + attribute \src "libresoc.v:126115.3-126121.6" + process $proc$libresoc.v:126115$5249 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_inv_out[0:0] $1\dec31_dec_sub23_inv_out[0:0] - attribute \src "libresoc.v:30875.5-30875.29" - switch \initial - attribute \src "libresoc.v:30875.9-30875.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub23_inv_out $0\dec31_dec_sub23_inv_out[0:0] - end - attribute \src "libresoc.v:30923.3-30971.6" - process $proc$libresoc.v:30923$665 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_cry_out[0:0] $1\dec31_dec_sub23_cry_out[0:0] - attribute \src "libresoc.v:30924.5-30924.29" - switch \initial - attribute \src "libresoc.v:30924.9-30924.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub23_cry_out $0\dec31_dec_sub23_cry_out[0:0] - end - attribute \src "libresoc.v:30972.3-31020.6" - process $proc$libresoc.v:30972$666 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_br[0:0] $1\dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:30973.5-30973.29" - switch \initial - attribute \src "libresoc.v:30973.9-30973.17" + assign { } { } + assign $0$memwr$\memory$libresoc.v:126120$5241_ADDR[4:0]$5250 5'xxxxx + assign $0$memwr$\memory$libresoc.v:126120$5241_DATA[63:0]$5251 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:126120$5241_EN[63:0]$5252 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\_0_[4:0] \src1__addr + assign $0\_1_[4:0] \src2__addr + assign $0\_2_[4:0] \src3__addr + assign $0\_3_[4:0] \dmi__addr + attribute \src "libresoc.v:126120.5-126120.58" + switch \dest1__wen + attribute \src "libresoc.v:126120.9-126120.19" case 1'1 + assign $0$memwr$\memory$libresoc.v:126120$5241_ADDR[4:0]$5250 \dest1__addr + assign $0$memwr$\memory$libresoc.v:126120$5241_DATA[63:0]$5251 \dest1__data_i + assign $0$memwr$\memory$libresoc.v:126120$5241_EN[63:0]$5252 64'1111111111111111111111111111111111111111111111111111111111111111 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - case - assign $1\dec31_dec_sub23_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub23_br $0\dec31_dec_sub23_br[0:0] + sync posedge \coresync_clk + update \_0_ $0\_0_[4:0] + update \_1_ $0\_1_[4:0] + update \_2_ $0\_2_[4:0] + update \_3_ $0\_3_[4:0] + update $memwr$\memory$libresoc.v:126120$5241_ADDR $0$memwr$\memory$libresoc.v:126120$5241_ADDR[4:0]$5250 + update $memwr$\memory$libresoc.v:126120$5241_DATA $0$memwr$\memory$libresoc.v:126120$5241_DATA[63:0]$5251 + update $memwr$\memory$libresoc.v:126120$5241_EN $0$memwr$\memory$libresoc.v:126120$5241_EN[63:0]$5252 end - attribute \src "libresoc.v:31021.3-31069.6" - process $proc$libresoc.v:31021$667 + attribute \src "libresoc.v:126126.3-126134.6" + process $proc$libresoc.v:126126$5257 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_sgn_ext[0:0] $1\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:31022.5-31022.29" + assign $0\ren_delay$next[0:0]$5258 $1\ren_delay$next[0:0]$5259 + attribute \src "libresoc.v:126127.5-126127.29" switch \initial - attribute \src "libresoc.v:31022.9-31022.17" + attribute \src "libresoc.v:126127.9-126127.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + assign $1\ren_delay$next[0:0]$5259 1'0 case - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + assign $1\ren_delay$next[0:0]$5259 \src1__ren end sync always - update \dec31_dec_sub23_sgn_ext $0\dec31_dec_sub23_sgn_ext[0:0] + update \ren_delay$next $0\ren_delay$next[0:0]$5258 end - attribute \src "libresoc.v:31070.3-31118.6" - process $proc$libresoc.v:31070$668 + attribute \src "libresoc.v:126135.3-126143.6" + process $proc$libresoc.v:126135$5260 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_internal_op[6:0] $1\dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:31071.5-31071.29" + assign $0\ren_delay$10$next[0:0]$5261 $1\ren_delay$10$next[0:0]$5262 + attribute \src "libresoc.v:126136.5-126136.29" switch \initial - attribute \src "libresoc.v:31071.9-31071.17" + attribute \src "libresoc.v:126136.9-126136.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + assign $1\ren_delay$10$next[0:0]$5262 1'0 case - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0000000 + assign $1\ren_delay$10$next[0:0]$5262 \dmi__ren end sync always - update \dec31_dec_sub23_internal_op $0\dec31_dec_sub23_internal_op[6:0] + update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5261 end - attribute \src "libresoc.v:31119.3-31167.6" - process $proc$libresoc.v:31119$669 + attribute \src "libresoc.v:126144.3-126153.6" + process $proc$libresoc.v:126144$5263 assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_rsrv[0:0] $1\dec31_dec_sub23_rsrv[0:0] - attribute \src "libresoc.v:31120.5-31120.29" - switch \initial - attribute \src "libresoc.v:31120.9-31120.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + assign { } { } + assign $0\dmi__data_o[63:0] $1\dmi__data_o[63:0] + attribute \src "libresoc.v:126145.5-126145.29" + switch \initial + attribute \src "libresoc.v:126145.9-126145.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay$10 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + assign $1\dmi__data_o[63:0] \memory_r_data$7 case - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + assign $1\dmi__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \dec31_dec_sub23_rsrv $0\dec31_dec_sub23_rsrv[0:0] + update \dmi__data_o $0\dmi__data_o[63:0] end - attribute \src "libresoc.v:31168.3-31216.6" - process $proc$libresoc.v:31168$670 + attribute \src "libresoc.v:126154.3-126163.6" + process $proc$libresoc.v:126154$5264 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_is_32b[0:0] $1\dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:31169.5-31169.29" + assign $0\src1__data_o[63:0] $1\src1__data_o[63:0] + attribute \src "libresoc.v:126155.5-126155.29" switch \initial - attribute \src "libresoc.v:31169.9-31169.17" + attribute \src "libresoc.v:126155.9-126155.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\src1__data_o[63:0] \memory_r_data case - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\src1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \dec31_dec_sub23_is_32b $0\dec31_dec_sub23_is_32b[0:0] + update \src1__data_o $0\src1__data_o[63:0] end - attribute \src "libresoc.v:31217.3-31265.6" - process $proc$libresoc.v:31217$671 + attribute \src "libresoc.v:126164.3-126172.6" + process $proc$libresoc.v:126164$5265 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_sgn[0:0] $1\dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:31218.5-31218.29" + assign $0\ren_delay$8$next[0:0]$5266 $1\ren_delay$8$next[0:0]$5267 + attribute \src "libresoc.v:126165.5-126165.29" switch \initial - attribute \src "libresoc.v:31218.9-31218.17" + attribute \src "libresoc.v:126165.9-126165.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 5'01101 + case 1'1 assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + assign $1\ren_delay$8$next[0:0]$5267 1'0 + case + assign $1\ren_delay$8$next[0:0]$5267 \src2__ren + end + sync always + update \ren_delay$8$next $0\ren_delay$8$next[0:0]$5266 + end + attribute \src "libresoc.v:126173.3-126182.6" + process $proc$libresoc.v:126173$5268 + assign { } { } + assign { } { } + assign $0\src2__data_o[63:0] $1\src2__data_o[63:0] + attribute \src "libresoc.v:126174.5-126174.29" + switch \initial + attribute \src "libresoc.v:126174.9-126174.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay$8 attribute \src "libresoc.v:0.0-0.0" - case 5'01100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + assign $1\src2__data_o[63:0] \memory_r_data$3 + case + assign $1\src2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \src2__data_o $0\src2__data_o[63:0] + end + attribute \src "libresoc.v:126183.3-126191.6" + process $proc$libresoc.v:126183$5269 + assign { } { } + assign { } { } + assign $0\ren_delay$9$next[0:0]$5270 $1\ren_delay$9$next[0:0]$5271 + attribute \src "libresoc.v:126184.5-126184.29" + switch \initial + attribute \src "libresoc.v:126184.9-126184.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 5'00101 + case 1'1 assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + assign $1\ren_delay$9$next[0:0]$5271 1'0 + case + assign $1\ren_delay$9$next[0:0]$5271 \src3__ren + end + sync always + update \ren_delay$9$next $0\ren_delay$9$next[0:0]$5270 + end + attribute \src "libresoc.v:126192.3-126201.6" + process $proc$libresoc.v:126192$5272 + assign { } { } + assign { } { } + assign $0\src3__data_o[63:0] $1\src3__data_o[63:0] + attribute \src "libresoc.v:126193.5-126193.29" + switch \initial + attribute \src "libresoc.v:126193.9-126193.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay$9 attribute \src "libresoc.v:0.0-0.0" - case 5'00100 + case 1'1 assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + assign $1\src3__data_o[63:0] \memory_r_data$5 case - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + assign $1\src3__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \dec31_dec_sub23_sgn $0\dec31_dec_sub23_sgn[0:0] + update \src3__data_o $0\src3__data_o[63:0] + end + connect \memory_r_data $memrd$\memory$libresoc.v:126122$5253_DATA + connect \memory_r_data$3 $memrd$\memory$libresoc.v:126123$5254_DATA + connect \memory_r_data$5 $memrd$\memory$libresoc.v:126124$5255_DATA + connect \memory_r_data$7 $memrd$\memory$libresoc.v:126125$5256_DATA + connect \memory_w_data \dest1__data_i + connect \memory_w_en \dest1__wen + connect \memory_w_addr \dest1__addr + connect \memory_r_addr$6 \dmi__addr + connect \memory_r_addr$4 \src3__addr + connect \memory_r_addr$2 \src2__addr + connect \memory_r_addr \src1__addr +end +attribute \src "libresoc.v:126213.1-128927.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.jtag" +attribute \generator "nMigen" +module \jtag + attribute \src "libresoc.v:128359.3-128385.6" + wire $0\TAP_bus__tdo[0:0] + attribute \src "libresoc.v:128007.3-128022.6" + wire $0\TAP_tdo[0:0] + attribute \src "libresoc.v:128520.3-128552.6" + wire width 4 $0\dmi0__addr_i$next[3:0]$5725 + attribute \src "libresoc.v:127910.3-127911.41" + wire width 4 $0\dmi0__addr_i[3:0] + attribute \src "libresoc.v:128606.3-128632.6" + wire width 64 $0\dmi0__din$next[63:0]$5738 + attribute \src "libresoc.v:127906.3-127907.35" + wire width 64 $0\dmi0__din[63:0] + attribute \src "libresoc.v:128209.3-128225.6" + wire $0\dmi0_addrsr__oe$next[0:0]$5662 + attribute \src "libresoc.v:127938.3-127939.47" + wire $0\dmi0_addrsr__oe[0:0] + attribute \src "libresoc.v:128226.3-128246.6" + wire width 8 $0\dmi0_addrsr_reg$next[7:0]$5666 + attribute \src "libresoc.v:127936.3-127937.47" + wire width 8 $0\dmi0_addrsr_reg[7:0] + attribute \src "libresoc.v:128191.3-128199.6" + wire $0\dmi0_addrsr_update_core$next[0:0]$5656 + attribute \src "libresoc.v:127942.3-127943.63" + wire $0\dmi0_addrsr_update_core[0:0] + attribute \src "libresoc.v:128200.3-128208.6" + wire $0\dmi0_addrsr_update_core_prev$next[0:0]$5659 + attribute \src "libresoc.v:127940.3-127941.73" + wire $0\dmi0_addrsr_update_core_prev[0:0] + attribute \src "libresoc.v:128633.3-128653.6" + wire width 64 $0\dmi0_datasr__i$next[63:0]$5743 + attribute \src "libresoc.v:127904.3-127905.45" + wire width 64 $0\dmi0_datasr__i[63:0] + attribute \src "libresoc.v:128265.3-128281.6" + wire width 2 $0\dmi0_datasr__oe$next[1:0]$5677 + attribute \src "libresoc.v:127930.3-127931.47" + wire width 2 $0\dmi0_datasr__oe[1:0] + attribute \src "libresoc.v:128282.3-128302.6" + wire width 64 $0\dmi0_datasr_reg$next[63:0]$5681 + attribute \src "libresoc.v:127928.3-127929.47" + wire width 64 $0\dmi0_datasr_reg[63:0] + attribute \src "libresoc.v:128247.3-128255.6" + wire $0\dmi0_datasr_update_core$next[0:0]$5671 + attribute \src "libresoc.v:127934.3-127935.63" + wire $0\dmi0_datasr_update_core[0:0] + attribute \src "libresoc.v:128256.3-128264.6" + wire $0\dmi0_datasr_update_core_prev$next[0:0]$5674 + attribute \src "libresoc.v:127932.3-127933.73" + wire $0\dmi0_datasr_update_core_prev[0:0] + attribute \src "libresoc.v:128553.3-128605.6" + wire width 3 $0\fsm_state$503$next[2:0]$5731 + attribute \src "libresoc.v:127908.3-127909.45" + wire width 3 $0\fsm_state$503[2:0]$5577 + attribute \src "libresoc.v:126859.13-126859.35" + wire width 3 $0\fsm_state$503[2:0]$5777 + attribute \src "libresoc.v:128419.3-128471.6" + wire width 3 $0\fsm_state$next[2:0]$5708 + attribute \src "libresoc.v:127916.3-127917.35" + wire width 3 $0\fsm_state[2:0] + attribute \src "libresoc.v:126214.7-126214.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:128701.3-128721.6" + wire width 154 $0\io_bd$next[153:0]$5760 + attribute \src "libresoc.v:127968.3-127969.27" + wire width 154 $0\io_bd[153:0] + attribute \src "libresoc.v:128683.3-128700.6" + wire width 154 $0\io_sr$next[153:0]$5756 + attribute \src "libresoc.v:127970.3-127971.27" + wire width 154 $0\io_sr[153:0] + attribute \src "libresoc.v:128386.3-128418.6" + wire width 29 $0\jtag_wb__adr$next[28:0]$5702 + attribute \src "libresoc.v:127918.3-127919.41" + wire width 29 $0\jtag_wb__adr[28:0] + attribute \src "libresoc.v:128472.3-128498.6" + wire width 64 $0\jtag_wb__dat_w$next[63:0]$5715 + attribute \src "libresoc.v:127914.3-127915.45" + wire width 64 $0\jtag_wb__dat_w[63:0] + attribute \src "libresoc.v:128097.3-128113.6" + wire $0\jtag_wb_addrsr__oe$next[0:0]$5632 + attribute \src "libresoc.v:127954.3-127955.53" + wire $0\jtag_wb_addrsr__oe[0:0] + attribute \src "libresoc.v:128114.3-128134.6" + wire width 29 $0\jtag_wb_addrsr_reg$next[28:0]$5636 + attribute \src "libresoc.v:127952.3-127953.53" + wire width 29 $0\jtag_wb_addrsr_reg[28:0] + attribute \src "libresoc.v:128079.3-128087.6" + wire $0\jtag_wb_addrsr_update_core$next[0:0]$5626 + attribute \src "libresoc.v:127958.3-127959.69" + wire $0\jtag_wb_addrsr_update_core[0:0] + attribute \src "libresoc.v:128088.3-128096.6" + wire $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5629 + attribute \src "libresoc.v:127956.3-127957.79" + wire $0\jtag_wb_addrsr_update_core_prev[0:0] + attribute \src "libresoc.v:128499.3-128519.6" + wire width 64 $0\jtag_wb_datasr__i$next[63:0]$5720 + attribute \src "libresoc.v:127912.3-127913.51" + wire width 64 $0\jtag_wb_datasr__i[63:0] + attribute \src "libresoc.v:128153.3-128169.6" + wire width 2 $0\jtag_wb_datasr__oe$next[1:0]$5647 + attribute \src "libresoc.v:127946.3-127947.53" + wire width 2 $0\jtag_wb_datasr__oe[1:0] + attribute \src "libresoc.v:128170.3-128190.6" + wire width 64 $0\jtag_wb_datasr_reg$next[63:0]$5651 + attribute \src "libresoc.v:127944.3-127945.53" + wire width 64 $0\jtag_wb_datasr_reg[63:0] + attribute \src "libresoc.v:128135.3-128143.6" + wire $0\jtag_wb_datasr_update_core$next[0:0]$5641 + attribute \src "libresoc.v:127950.3-127951.69" + wire $0\jtag_wb_datasr_update_core[0:0] + attribute \src "libresoc.v:128144.3-128152.6" + wire $0\jtag_wb_datasr_update_core_prev$next[0:0]$5644 + attribute \src "libresoc.v:127948.3-127949.79" + wire $0\jtag_wb_datasr_update_core_prev[0:0] + attribute \src "libresoc.v:128041.3-128057.6" + wire $0\sr0__oe$next[0:0]$5617 + attribute \src "libresoc.v:127962.3-127963.31" + wire $0\sr0__oe[0:0] + attribute \src "libresoc.v:128058.3-128078.6" + wire width 3 $0\sr0_reg$next[2:0]$5621 + attribute \src "libresoc.v:127960.3-127961.31" + wire width 3 $0\sr0_reg[2:0] + attribute \src "libresoc.v:128023.3-128031.6" + wire $0\sr0_update_core$next[0:0]$5611 + attribute \src "libresoc.v:127966.3-127967.47" + wire $0\sr0_update_core[0:0] + attribute \src "libresoc.v:128032.3-128040.6" + wire $0\sr0_update_core_prev$next[0:0]$5614 + attribute \src "libresoc.v:127964.3-127965.57" + wire $0\sr0_update_core_prev[0:0] + attribute \src "libresoc.v:128673.3-128682.6" + wire width 2 $0\sr5__i[1:0] + attribute \src "libresoc.v:128321.3-128337.6" + wire $0\sr5__oe$next[0:0]$5692 + attribute \src "libresoc.v:127922.3-127923.31" + wire $0\sr5__oe[0:0] + attribute \src "libresoc.v:128338.3-128358.6" + wire width 2 $0\sr5_reg$next[1:0]$5696 + attribute \src "libresoc.v:127920.3-127921.31" + wire width 2 $0\sr5_reg[1:0] + attribute \src "libresoc.v:128303.3-128311.6" + wire $0\sr5_update_core$next[0:0]$5686 + attribute \src "libresoc.v:127926.3-127927.47" + wire $0\sr5_update_core[0:0] + attribute \src "libresoc.v:128312.3-128320.6" + wire $0\sr5_update_core_prev$next[0:0]$5689 + attribute \src "libresoc.v:127924.3-127925.57" + wire $0\sr5_update_core_prev[0:0] + attribute \src "libresoc.v:128654.3-128672.6" + wire $0\wb_dcache_en$next[0:0]$5748 + attribute \src "libresoc.v:127902.3-127903.41" + wire $0\wb_dcache_en[0:0] + attribute \src "libresoc.v:128654.3-128672.6" + wire $0\wb_icache_en$next[0:0]$5749 + attribute \src "libresoc.v:127900.3-127901.41" + wire $0\wb_icache_en[0:0] + attribute \src "libresoc.v:128359.3-128385.6" + wire $1\TAP_bus__tdo[0:0] + attribute \src "libresoc.v:128007.3-128022.6" + wire $1\TAP_tdo[0:0] + attribute \src "libresoc.v:128520.3-128552.6" + wire width 4 $1\dmi0__addr_i$next[3:0]$5726 + attribute \src "libresoc.v:126772.13-126772.32" + wire width 4 $1\dmi0__addr_i[3:0] + attribute \src "libresoc.v:128606.3-128632.6" + wire width 64 $1\dmi0__din$next[63:0]$5739 + attribute \src "libresoc.v:126777.14-126777.46" + wire width 64 $1\dmi0__din[63:0] + attribute \src "libresoc.v:128209.3-128225.6" + wire $1\dmi0_addrsr__oe$next[0:0]$5663 + attribute \src "libresoc.v:126791.7-126791.29" + wire $1\dmi0_addrsr__oe[0:0] + attribute \src "libresoc.v:128226.3-128246.6" + wire width 8 $1\dmi0_addrsr_reg$next[7:0]$5667 + attribute \src "libresoc.v:126799.13-126799.36" + wire width 8 $1\dmi0_addrsr_reg[7:0] + attribute \src "libresoc.v:128191.3-128199.6" + wire $1\dmi0_addrsr_update_core$next[0:0]$5657 + attribute \src "libresoc.v:126807.7-126807.37" + wire $1\dmi0_addrsr_update_core[0:0] + attribute \src "libresoc.v:128200.3-128208.6" + wire $1\dmi0_addrsr_update_core_prev$next[0:0]$5660 + attribute \src "libresoc.v:126811.7-126811.42" + wire $1\dmi0_addrsr_update_core_prev[0:0] + attribute \src "libresoc.v:128633.3-128653.6" + wire width 64 $1\dmi0_datasr__i$next[63:0]$5744 + attribute \src "libresoc.v:126815.14-126815.51" + wire width 64 $1\dmi0_datasr__i[63:0] + attribute \src "libresoc.v:128265.3-128281.6" + wire width 2 $1\dmi0_datasr__oe$next[1:0]$5678 + attribute \src "libresoc.v:126821.13-126821.35" + wire width 2 $1\dmi0_datasr__oe[1:0] + attribute \src "libresoc.v:128282.3-128302.6" + wire width 64 $1\dmi0_datasr_reg$next[63:0]$5682 + attribute \src "libresoc.v:126829.14-126829.52" + wire width 64 $1\dmi0_datasr_reg[63:0] + attribute \src "libresoc.v:128247.3-128255.6" + wire $1\dmi0_datasr_update_core$next[0:0]$5672 + attribute \src "libresoc.v:126837.7-126837.37" + wire $1\dmi0_datasr_update_core[0:0] + attribute \src "libresoc.v:128256.3-128264.6" + wire $1\dmi0_datasr_update_core_prev$next[0:0]$5675 + attribute \src "libresoc.v:126841.7-126841.42" + wire $1\dmi0_datasr_update_core_prev[0:0] + attribute \src "libresoc.v:128553.3-128605.6" + wire width 3 $1\fsm_state$503$next[2:0]$5732 + attribute \src "libresoc.v:128419.3-128471.6" + wire width 3 $1\fsm_state$next[2:0]$5709 + attribute \src "libresoc.v:126857.13-126857.29" + wire width 3 $1\fsm_state[2:0] + attribute \src "libresoc.v:128701.3-128721.6" + wire width 154 $1\io_bd$next[153:0]$5761 + attribute \src "libresoc.v:127057.15-127057.67" + wire width 154 $1\io_bd[153:0] + attribute \src "libresoc.v:128683.3-128700.6" + wire width 154 $1\io_sr$next[153:0]$5757 + attribute \src "libresoc.v:127069.15-127069.67" + wire width 154 $1\io_sr[153:0] + attribute \src "libresoc.v:128386.3-128418.6" + wire width 29 $1\jtag_wb__adr$next[28:0]$5703 + attribute \src "libresoc.v:127078.14-127078.41" + wire width 29 $1\jtag_wb__adr[28:0] + attribute \src "libresoc.v:128472.3-128498.6" + wire width 64 $1\jtag_wb__dat_w$next[63:0]$5716 + attribute \src "libresoc.v:127087.14-127087.51" + wire width 64 $1\jtag_wb__dat_w[63:0] + attribute \src "libresoc.v:128097.3-128113.6" + wire $1\jtag_wb_addrsr__oe$next[0:0]$5633 + attribute \src "libresoc.v:127101.7-127101.32" + wire $1\jtag_wb_addrsr__oe[0:0] + attribute \src "libresoc.v:128114.3-128134.6" + wire width 29 $1\jtag_wb_addrsr_reg$next[28:0]$5637 + attribute \src "libresoc.v:127109.14-127109.47" + wire width 29 $1\jtag_wb_addrsr_reg[28:0] + attribute \src "libresoc.v:128079.3-128087.6" + wire $1\jtag_wb_addrsr_update_core$next[0:0]$5627 + attribute \src "libresoc.v:127117.7-127117.40" + wire $1\jtag_wb_addrsr_update_core[0:0] + attribute \src "libresoc.v:128088.3-128096.6" + wire $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5630 + attribute \src "libresoc.v:127121.7-127121.45" + wire $1\jtag_wb_addrsr_update_core_prev[0:0] + attribute \src "libresoc.v:128499.3-128519.6" + wire width 64 $1\jtag_wb_datasr__i$next[63:0]$5721 + attribute \src "libresoc.v:127125.14-127125.54" + wire width 64 $1\jtag_wb_datasr__i[63:0] + attribute \src "libresoc.v:128153.3-128169.6" + wire width 2 $1\jtag_wb_datasr__oe$next[1:0]$5648 + attribute \src "libresoc.v:127131.13-127131.38" + wire width 2 $1\jtag_wb_datasr__oe[1:0] + attribute \src "libresoc.v:128170.3-128190.6" + wire width 64 $1\jtag_wb_datasr_reg$next[63:0]$5652 + attribute \src "libresoc.v:127139.14-127139.55" + wire width 64 $1\jtag_wb_datasr_reg[63:0] + attribute \src "libresoc.v:128135.3-128143.6" + wire $1\jtag_wb_datasr_update_core$next[0:0]$5642 + attribute \src "libresoc.v:127147.7-127147.40" + wire $1\jtag_wb_datasr_update_core[0:0] + attribute \src "libresoc.v:128144.3-128152.6" + wire $1\jtag_wb_datasr_update_core_prev$next[0:0]$5645 + attribute \src "libresoc.v:127151.7-127151.45" + wire $1\jtag_wb_datasr_update_core_prev[0:0] + attribute \src "libresoc.v:128041.3-128057.6" + wire $1\sr0__oe$next[0:0]$5618 + attribute \src "libresoc.v:127581.7-127581.21" + wire $1\sr0__oe[0:0] + attribute \src "libresoc.v:128058.3-128078.6" + wire width 3 $1\sr0_reg$next[2:0]$5622 + attribute \src "libresoc.v:127589.13-127589.27" + wire width 3 $1\sr0_reg[2:0] + attribute \src "libresoc.v:128023.3-128031.6" + wire $1\sr0_update_core$next[0:0]$5612 + attribute \src "libresoc.v:127597.7-127597.29" + wire $1\sr0_update_core[0:0] + attribute \src "libresoc.v:128032.3-128040.6" + wire $1\sr0_update_core_prev$next[0:0]$5615 + attribute \src "libresoc.v:127601.7-127601.34" + wire $1\sr0_update_core_prev[0:0] + attribute \src "libresoc.v:128673.3-128682.6" + wire width 2 $1\sr5__i[1:0] + attribute \src "libresoc.v:128321.3-128337.6" + wire $1\sr5__oe$next[0:0]$5693 + attribute \src "libresoc.v:127611.7-127611.21" + wire $1\sr5__oe[0:0] + attribute \src "libresoc.v:128338.3-128358.6" + wire width 2 $1\sr5_reg$next[1:0]$5697 + attribute \src "libresoc.v:127619.13-127619.27" + wire width 2 $1\sr5_reg[1:0] + attribute \src "libresoc.v:128303.3-128311.6" + wire $1\sr5_update_core$next[0:0]$5687 + attribute \src "libresoc.v:127627.7-127627.29" + wire $1\sr5_update_core[0:0] + attribute \src "libresoc.v:128312.3-128320.6" + wire $1\sr5_update_core_prev$next[0:0]$5690 + attribute \src "libresoc.v:127631.7-127631.34" + wire $1\sr5_update_core_prev[0:0] + attribute \src "libresoc.v:128654.3-128672.6" + wire $1\wb_dcache_en$next[0:0]$5750 + attribute \src "libresoc.v:127636.7-127636.26" + wire $1\wb_dcache_en[0:0] + attribute \src "libresoc.v:128654.3-128672.6" + wire $1\wb_icache_en$next[0:0]$5751 + attribute \src "libresoc.v:127641.7-127641.26" + wire $1\wb_icache_en[0:0] + attribute \src "libresoc.v:128520.3-128552.6" + wire width 4 $2\dmi0__addr_i$next[3:0]$5727 + attribute \src "libresoc.v:128606.3-128632.6" + wire width 64 $2\dmi0__din$next[63:0]$5740 + attribute \src "libresoc.v:128209.3-128225.6" + wire $2\dmi0_addrsr__oe$next[0:0]$5664 + attribute \src "libresoc.v:128226.3-128246.6" + wire width 8 $2\dmi0_addrsr_reg$next[7:0]$5668 + attribute \src "libresoc.v:128633.3-128653.6" + wire width 64 $2\dmi0_datasr__i$next[63:0]$5745 + attribute \src "libresoc.v:128265.3-128281.6" + wire width 2 $2\dmi0_datasr__oe$next[1:0]$5679 + attribute \src "libresoc.v:128282.3-128302.6" + wire width 64 $2\dmi0_datasr_reg$next[63:0]$5683 + attribute \src "libresoc.v:128553.3-128605.6" + wire width 3 $2\fsm_state$503$next[2:0]$5733 + attribute \src "libresoc.v:128419.3-128471.6" + wire width 3 $2\fsm_state$next[2:0]$5710 + attribute \src "libresoc.v:128701.3-128721.6" + wire width 154 $2\io_bd$next[153:0]$5762 + attribute \src "libresoc.v:128683.3-128700.6" + wire width 154 $2\io_sr$next[153:0]$5758 + attribute \src "libresoc.v:128386.3-128418.6" + wire width 29 $2\jtag_wb__adr$next[28:0]$5704 + attribute \src "libresoc.v:128472.3-128498.6" + wire width 64 $2\jtag_wb__dat_w$next[63:0]$5717 + attribute \src "libresoc.v:128097.3-128113.6" + wire $2\jtag_wb_addrsr__oe$next[0:0]$5634 + attribute \src "libresoc.v:128114.3-128134.6" + wire width 29 $2\jtag_wb_addrsr_reg$next[28:0]$5638 + attribute \src "libresoc.v:128499.3-128519.6" + wire width 64 $2\jtag_wb_datasr__i$next[63:0]$5722 + attribute \src "libresoc.v:128153.3-128169.6" + wire width 2 $2\jtag_wb_datasr__oe$next[1:0]$5649 + attribute \src "libresoc.v:128170.3-128190.6" + wire width 64 $2\jtag_wb_datasr_reg$next[63:0]$5653 + attribute \src "libresoc.v:128041.3-128057.6" + wire $2\sr0__oe$next[0:0]$5619 + attribute \src "libresoc.v:128058.3-128078.6" + wire width 3 $2\sr0_reg$next[2:0]$5623 + attribute \src "libresoc.v:128321.3-128337.6" + wire $2\sr5__oe$next[0:0]$5694 + attribute \src "libresoc.v:128338.3-128358.6" + wire width 2 $2\sr5_reg$next[1:0]$5698 + attribute \src "libresoc.v:128654.3-128672.6" + wire $2\wb_dcache_en$next[0:0]$5752 + attribute \src "libresoc.v:128654.3-128672.6" + wire $2\wb_icache_en$next[0:0]$5753 + attribute \src "libresoc.v:128520.3-128552.6" + wire width 4 $3\dmi0__addr_i$next[3:0]$5728 + attribute \src "libresoc.v:128606.3-128632.6" + wire width 64 $3\dmi0__din$next[63:0]$5741 + attribute \src "libresoc.v:128226.3-128246.6" + wire width 8 $3\dmi0_addrsr_reg$next[7:0]$5669 + attribute \src "libresoc.v:128633.3-128653.6" + wire width 64 $3\dmi0_datasr__i$next[63:0]$5746 + attribute \src "libresoc.v:128282.3-128302.6" + wire width 64 $3\dmi0_datasr_reg$next[63:0]$5684 + attribute \src "libresoc.v:128553.3-128605.6" + wire width 3 $3\fsm_state$503$next[2:0]$5734 + attribute \src "libresoc.v:128419.3-128471.6" + wire width 3 $3\fsm_state$next[2:0]$5711 + attribute \src "libresoc.v:128386.3-128418.6" + wire width 29 $3\jtag_wb__adr$next[28:0]$5705 + attribute \src "libresoc.v:128472.3-128498.6" + wire width 64 $3\jtag_wb__dat_w$next[63:0]$5718 + attribute \src "libresoc.v:128114.3-128134.6" + wire width 29 $3\jtag_wb_addrsr_reg$next[28:0]$5639 + attribute \src "libresoc.v:128499.3-128519.6" + wire width 64 $3\jtag_wb_datasr__i$next[63:0]$5723 + attribute \src "libresoc.v:128170.3-128190.6" + wire width 64 $3\jtag_wb_datasr_reg$next[63:0]$5654 + attribute \src "libresoc.v:128058.3-128078.6" + wire width 3 $3\sr0_reg$next[2:0]$5624 + attribute \src "libresoc.v:128338.3-128358.6" + wire width 2 $3\sr5_reg$next[1:0]$5699 + attribute \src "libresoc.v:128520.3-128552.6" + wire width 4 $4\dmi0__addr_i$next[3:0]$5729 + attribute \src "libresoc.v:128553.3-128605.6" + wire width 3 $4\fsm_state$503$next[2:0]$5735 + attribute \src "libresoc.v:128419.3-128471.6" + wire width 3 $4\fsm_state$next[2:0]$5712 + attribute \src "libresoc.v:128386.3-128418.6" + wire width 29 $4\jtag_wb__adr$next[28:0]$5706 + attribute \src "libresoc.v:128553.3-128605.6" + wire width 3 $5\fsm_state$503$next[2:0]$5736 + attribute \src "libresoc.v:128419.3-128471.6" + wire width 3 $5\fsm_state$next[2:0]$5713 + attribute \src "libresoc.v:127864.19-127864.112" + wire width 30 $add$libresoc.v:127864$5535_Y + attribute \src "libresoc.v:127866.19-127866.112" + wire width 30 $add$libresoc.v:127866$5537_Y + attribute \src "libresoc.v:127872.19-127872.112" + wire width 5 $add$libresoc.v:127872$5544_Y + attribute \src "libresoc.v:127873.19-127873.112" + wire width 5 $add$libresoc.v:127873$5545_Y + attribute \src "libresoc.v:127688.18-127688.112" + wire $and$libresoc.v:127688$5359_Y + attribute \src "libresoc.v:127755.18-127755.108" + wire $and$libresoc.v:127755$5426_Y + attribute \src "libresoc.v:127766.18-127766.110" + wire $and$libresoc.v:127766$5437_Y + attribute \src "libresoc.v:127794.19-127794.110" + wire $and$libresoc.v:127794$5465_Y + attribute \src "libresoc.v:127797.19-127797.114" + wire $and$libresoc.v:127797$5468_Y + attribute \src "libresoc.v:127800.19-127800.112" + wire $and$libresoc.v:127800$5471_Y + attribute \src "libresoc.v:127802.19-127802.113" + wire $and$libresoc.v:127802$5473_Y + attribute \src "libresoc.v:127804.19-127804.121" + wire $and$libresoc.v:127804$5475_Y + attribute \src "libresoc.v:127807.19-127807.114" + wire $and$libresoc.v:127807$5478_Y + attribute \src "libresoc.v:127809.19-127809.112" + wire $and$libresoc.v:127809$5480_Y + attribute \src "libresoc.v:127813.19-127813.113" + wire $and$libresoc.v:127813$5484_Y + attribute \src "libresoc.v:127815.19-127815.132" + wire $and$libresoc.v:127815$5486_Y + attribute \src "libresoc.v:127819.19-127819.114" + wire $and$libresoc.v:127819$5490_Y + attribute \src "libresoc.v:127821.19-127821.112" + wire $and$libresoc.v:127821$5492_Y + attribute \src "libresoc.v:127824.19-127824.113" + wire $and$libresoc.v:127824$5495_Y + attribute \src "libresoc.v:127826.19-127826.132" + wire $and$libresoc.v:127826$5497_Y + attribute \src "libresoc.v:127829.19-127829.114" + wire $and$libresoc.v:127829$5500_Y + attribute \src "libresoc.v:127831.19-127831.112" + wire $and$libresoc.v:127831$5502_Y + attribute \src "libresoc.v:127833.18-127833.108" + wire $and$libresoc.v:127833$5504_Y + attribute \src "libresoc.v:127834.19-127834.113" + wire $and$libresoc.v:127834$5505_Y + attribute \src "libresoc.v:127836.19-127836.129" + wire $and$libresoc.v:127836$5507_Y + attribute \src "libresoc.v:127840.19-127840.114" + wire $and$libresoc.v:127840$5511_Y + attribute \src "libresoc.v:127842.19-127842.112" + wire $and$libresoc.v:127842$5513_Y + attribute \src "libresoc.v:127844.18-127844.111" + wire $and$libresoc.v:127844$5515_Y + attribute \src "libresoc.v:127845.19-127845.113" + wire $and$libresoc.v:127845$5516_Y + attribute \src "libresoc.v:127847.19-127847.129" + wire $and$libresoc.v:127847$5518_Y + attribute \src "libresoc.v:127850.19-127850.114" + wire $and$libresoc.v:127850$5521_Y + attribute \src "libresoc.v:127852.19-127852.112" + wire $and$libresoc.v:127852$5523_Y + attribute \src "libresoc.v:127854.19-127854.113" + wire $and$libresoc.v:127854$5525_Y + attribute \src "libresoc.v:127857.19-127857.121" + wire $and$libresoc.v:127857$5528_Y + attribute \src "libresoc.v:127889.17-127889.106" + wire $and$libresoc.v:127889$5561_Y + attribute \src "libresoc.v:127644.17-127644.110" + wire $eq$libresoc.v:127644$5315_Y + attribute \src "libresoc.v:127655.18-127655.111" + wire $eq$libresoc.v:127655$5326_Y + attribute \src "libresoc.v:127666.18-127666.111" + wire $eq$libresoc.v:127666$5337_Y + attribute \src "libresoc.v:127699.17-127699.110" + wire $eq$libresoc.v:127699$5370_Y + attribute \src "libresoc.v:127700.18-127700.111" + wire $eq$libresoc.v:127700$5371_Y + attribute \src "libresoc.v:127711.18-127711.111" + wire $eq$libresoc.v:127711$5382_Y + attribute \src "libresoc.v:127733.18-127733.111" + wire $eq$libresoc.v:127733$5404_Y + attribute \src "libresoc.v:127777.18-127777.111" + wire $eq$libresoc.v:127777$5448_Y + attribute \src "libresoc.v:127788.18-127788.111" + wire $eq$libresoc.v:127788$5459_Y + attribute \src "libresoc.v:127789.19-127789.112" + wire $eq$libresoc.v:127789$5460_Y + attribute \src "libresoc.v:127790.19-127790.112" + wire $eq$libresoc.v:127790$5461_Y + attribute \src "libresoc.v:127792.19-127792.112" + wire $eq$libresoc.v:127792$5463_Y + attribute \src "libresoc.v:127795.19-127795.112" + wire $eq$libresoc.v:127795$5466_Y + attribute \src "libresoc.v:127805.19-127805.112" + wire $eq$libresoc.v:127805$5476_Y + attribute \src "libresoc.v:127810.17-127810.110" + wire $eq$libresoc.v:127810$5481_Y + attribute \src "libresoc.v:127811.18-127811.111" + wire $eq$libresoc.v:127811$5482_Y + attribute \src "libresoc.v:127816.19-127816.112" + wire $eq$libresoc.v:127816$5487_Y + attribute \src "libresoc.v:127817.19-127817.112" + wire $eq$libresoc.v:127817$5488_Y + attribute \src "libresoc.v:127827.19-127827.112" + wire $eq$libresoc.v:127827$5498_Y + attribute \src "libresoc.v:127837.19-127837.112" + wire $eq$libresoc.v:127837$5508_Y + attribute \src "libresoc.v:127838.19-127838.112" + wire $eq$libresoc.v:127838$5509_Y + attribute \src "libresoc.v:127848.19-127848.112" + wire $eq$libresoc.v:127848$5519_Y + attribute \src "libresoc.v:127855.18-127855.111" + wire $eq$libresoc.v:127855$5526_Y + attribute \src "libresoc.v:127858.19-127858.110" + wire $eq$libresoc.v:127858$5529_Y + attribute \src "libresoc.v:127860.19-127860.110" + wire $eq$libresoc.v:127860$5531_Y + attribute \src "libresoc.v:127861.19-127861.110" + wire $eq$libresoc.v:127861$5532_Y + attribute \src "libresoc.v:127863.19-127863.110" + wire $eq$libresoc.v:127863$5534_Y + attribute \src "libresoc.v:127865.18-127865.111" + wire $eq$libresoc.v:127865$5536_Y + attribute \src "libresoc.v:127868.19-127868.116" + wire $eq$libresoc.v:127868$5540_Y + attribute \src "libresoc.v:127869.19-127869.116" + wire $eq$libresoc.v:127869$5541_Y + attribute \src "libresoc.v:127871.19-127871.116" + wire $eq$libresoc.v:127871$5543_Y + attribute \src "libresoc.v:127867.19-127867.106" + wire width 8 $extend$libresoc.v:127867$5538_Y + attribute \src "libresoc.v:127796.19-127796.109" + wire $ne$libresoc.v:127796$5467_Y + attribute \src "libresoc.v:127798.19-127798.109" + wire $ne$libresoc.v:127798$5469_Y + attribute \src "libresoc.v:127801.19-127801.109" + wire $ne$libresoc.v:127801$5472_Y + attribute \src "libresoc.v:127806.19-127806.120" + wire $ne$libresoc.v:127806$5477_Y + attribute \src "libresoc.v:127808.19-127808.120" + wire $ne$libresoc.v:127808$5479_Y + attribute \src "libresoc.v:127812.19-127812.120" + wire $ne$libresoc.v:127812$5483_Y + attribute \src "libresoc.v:127818.19-127818.120" + wire $ne$libresoc.v:127818$5489_Y + attribute \src "libresoc.v:127820.19-127820.120" + wire $ne$libresoc.v:127820$5491_Y + attribute \src "libresoc.v:127823.19-127823.120" + wire $ne$libresoc.v:127823$5494_Y + attribute \src "libresoc.v:127828.19-127828.117" + wire $ne$libresoc.v:127828$5499_Y + attribute \src "libresoc.v:127830.19-127830.117" + wire $ne$libresoc.v:127830$5501_Y + attribute \src "libresoc.v:127832.19-127832.117" + wire $ne$libresoc.v:127832$5503_Y + attribute \src "libresoc.v:127839.19-127839.117" + wire $ne$libresoc.v:127839$5510_Y + attribute \src "libresoc.v:127841.19-127841.117" + wire $ne$libresoc.v:127841$5512_Y + attribute \src "libresoc.v:127843.19-127843.117" + wire $ne$libresoc.v:127843$5514_Y + attribute \src "libresoc.v:127849.19-127849.109" + wire $ne$libresoc.v:127849$5520_Y + attribute \src "libresoc.v:127851.19-127851.109" + wire $ne$libresoc.v:127851$5522_Y + attribute \src "libresoc.v:127853.19-127853.109" + wire $ne$libresoc.v:127853$5524_Y + attribute \src "libresoc.v:127803.19-127803.110" + wire $not$libresoc.v:127803$5474_Y + attribute \src "libresoc.v:127814.19-127814.121" + wire $not$libresoc.v:127814$5485_Y + attribute \src "libresoc.v:127825.19-127825.121" + wire $not$libresoc.v:127825$5496_Y + attribute \src "libresoc.v:127835.19-127835.118" + wire $not$libresoc.v:127835$5506_Y + attribute \src "libresoc.v:127846.19-127846.118" + wire $not$libresoc.v:127846$5517_Y + attribute \src "libresoc.v:127856.19-127856.110" + wire $not$libresoc.v:127856$5527_Y + attribute \src "libresoc.v:127859.19-127859.100" + wire $not$libresoc.v:127859$5530_Y + attribute \src "libresoc.v:127677.18-127677.104" + wire $or$libresoc.v:127677$5348_Y + attribute \src "libresoc.v:127722.18-127722.104" + wire $or$libresoc.v:127722$5393_Y + attribute \src "libresoc.v:127744.18-127744.104" + wire $or$libresoc.v:127744$5415_Y + attribute \src "libresoc.v:127791.19-127791.107" + wire $or$libresoc.v:127791$5462_Y + attribute \src "libresoc.v:127793.19-127793.107" + wire $or$libresoc.v:127793$5464_Y + attribute \src "libresoc.v:127799.18-127799.104" + wire $or$libresoc.v:127799$5470_Y + attribute \src "libresoc.v:127822.18-127822.104" + wire $or$libresoc.v:127822$5493_Y + attribute \src "libresoc.v:127862.19-127862.107" + wire $or$libresoc.v:127862$5533_Y + attribute \src "libresoc.v:127870.19-127870.107" + wire $or$libresoc.v:127870$5542_Y + attribute \src "libresoc.v:127878.17-127878.101" + wire $or$libresoc.v:127878$5550_Y + attribute \src "libresoc.v:127867.19-127867.106" + wire width 8 $pos$libresoc.v:127867$5539_Y + attribute \src "libresoc.v:127645.18-127645.133" + wire $ternary$libresoc.v:127645$5316_Y + attribute \src "libresoc.v:127646.19-127646.133" + wire $ternary$libresoc.v:127646$5317_Y + attribute \src "libresoc.v:127647.19-127647.134" + wire $ternary$libresoc.v:127647$5318_Y + attribute \src "libresoc.v:127648.19-127648.133" + wire $ternary$libresoc.v:127648$5319_Y + attribute \src "libresoc.v:127649.19-127649.132" + wire $ternary$libresoc.v:127649$5320_Y + attribute \src "libresoc.v:127650.19-127650.133" + wire $ternary$libresoc.v:127650$5321_Y + attribute \src "libresoc.v:127651.19-127651.133" + wire $ternary$libresoc.v:127651$5322_Y + attribute \src "libresoc.v:127652.19-127652.132" + wire $ternary$libresoc.v:127652$5323_Y + attribute \src "libresoc.v:127653.19-127653.133" + wire $ternary$libresoc.v:127653$5324_Y + attribute \src "libresoc.v:127654.19-127654.133" + wire $ternary$libresoc.v:127654$5325_Y + attribute \src "libresoc.v:127656.19-127656.132" + wire $ternary$libresoc.v:127656$5327_Y + attribute \src "libresoc.v:127657.19-127657.133" + wire $ternary$libresoc.v:127657$5328_Y + attribute \src "libresoc.v:127658.19-127658.133" + wire $ternary$libresoc.v:127658$5329_Y + attribute \src "libresoc.v:127659.19-127659.132" + wire $ternary$libresoc.v:127659$5330_Y + attribute \src "libresoc.v:127660.19-127660.133" + wire $ternary$libresoc.v:127660$5331_Y + attribute \src "libresoc.v:127661.19-127661.133" + wire $ternary$libresoc.v:127661$5332_Y + attribute \src "libresoc.v:127662.19-127662.132" + wire $ternary$libresoc.v:127662$5333_Y + attribute \src "libresoc.v:127663.19-127663.133" + wire $ternary$libresoc.v:127663$5334_Y + attribute \src "libresoc.v:127664.19-127664.133" + wire $ternary$libresoc.v:127664$5335_Y + attribute \src "libresoc.v:127665.19-127665.132" + wire $ternary$libresoc.v:127665$5336_Y + attribute \src "libresoc.v:127667.19-127667.133" + wire $ternary$libresoc.v:127667$5338_Y + attribute \src "libresoc.v:127668.19-127668.133" + wire $ternary$libresoc.v:127668$5339_Y + attribute \src "libresoc.v:127669.19-127669.132" + wire $ternary$libresoc.v:127669$5340_Y + attribute \src "libresoc.v:127670.19-127670.133" + wire $ternary$libresoc.v:127670$5341_Y + attribute \src "libresoc.v:127671.19-127671.133" + wire $ternary$libresoc.v:127671$5342_Y + attribute \src "libresoc.v:127672.19-127672.132" + wire $ternary$libresoc.v:127672$5343_Y + attribute \src "libresoc.v:127673.19-127673.133" + wire $ternary$libresoc.v:127673$5344_Y + attribute \src "libresoc.v:127674.19-127674.134" + wire $ternary$libresoc.v:127674$5345_Y + attribute \src "libresoc.v:127675.19-127675.135" + wire $ternary$libresoc.v:127675$5346_Y + attribute \src "libresoc.v:127676.19-127676.135" + wire $ternary$libresoc.v:127676$5347_Y + attribute \src "libresoc.v:127678.19-127678.136" + wire $ternary$libresoc.v:127678$5349_Y + attribute \src "libresoc.v:127679.19-127679.134" + wire $ternary$libresoc.v:127679$5350_Y + attribute \src "libresoc.v:127680.19-127680.135" + wire $ternary$libresoc.v:127680$5351_Y + attribute \src "libresoc.v:127681.19-127681.135" + wire $ternary$libresoc.v:127681$5352_Y + attribute \src "libresoc.v:127682.19-127682.136" + wire $ternary$libresoc.v:127682$5353_Y + attribute \src "libresoc.v:127683.19-127683.134" + wire $ternary$libresoc.v:127683$5354_Y + attribute \src "libresoc.v:127684.19-127684.133" + wire $ternary$libresoc.v:127684$5355_Y + attribute \src "libresoc.v:127685.19-127685.134" + wire $ternary$libresoc.v:127685$5356_Y + attribute \src "libresoc.v:127686.19-127686.133" + wire $ternary$libresoc.v:127686$5357_Y + attribute \src "libresoc.v:127687.19-127687.130" + wire $ternary$libresoc.v:127687$5358_Y + attribute \src "libresoc.v:127689.19-127689.130" + wire $ternary$libresoc.v:127689$5360_Y + attribute \src "libresoc.v:127690.19-127690.133" + wire $ternary$libresoc.v:127690$5361_Y + attribute \src "libresoc.v:127691.19-127691.132" + wire $ternary$libresoc.v:127691$5362_Y + attribute \src "libresoc.v:127692.19-127692.133" + wire $ternary$libresoc.v:127692$5363_Y + attribute \src "libresoc.v:127693.19-127693.132" + wire $ternary$libresoc.v:127693$5364_Y + attribute \src "libresoc.v:127694.19-127694.135" + wire $ternary$libresoc.v:127694$5365_Y + attribute \src "libresoc.v:127695.19-127695.134" + wire $ternary$libresoc.v:127695$5366_Y + attribute \src "libresoc.v:127696.19-127696.135" + wire $ternary$libresoc.v:127696$5367_Y + attribute \src "libresoc.v:127697.19-127697.135" + wire $ternary$libresoc.v:127697$5368_Y + attribute \src "libresoc.v:127698.19-127698.134" + wire $ternary$libresoc.v:127698$5369_Y + attribute \src "libresoc.v:127701.19-127701.135" + wire $ternary$libresoc.v:127701$5372_Y + attribute \src "libresoc.v:127702.19-127702.135" + wire $ternary$libresoc.v:127702$5373_Y + attribute \src "libresoc.v:127703.19-127703.134" + wire $ternary$libresoc.v:127703$5374_Y + attribute \src "libresoc.v:127704.19-127704.135" + wire $ternary$libresoc.v:127704$5375_Y + attribute \src "libresoc.v:127705.19-127705.135" + wire $ternary$libresoc.v:127705$5376_Y + attribute \src "libresoc.v:127706.19-127706.134" + wire $ternary$libresoc.v:127706$5377_Y + attribute \src "libresoc.v:127707.19-127707.135" + wire $ternary$libresoc.v:127707$5378_Y + attribute \src "libresoc.v:127708.19-127708.133" + wire $ternary$libresoc.v:127708$5379_Y + attribute \src "libresoc.v:127709.19-127709.134" + wire $ternary$libresoc.v:127709$5380_Y + attribute \src "libresoc.v:127710.19-127710.133" + wire $ternary$libresoc.v:127710$5381_Y + attribute \src "libresoc.v:127712.19-127712.134" + wire $ternary$libresoc.v:127712$5383_Y + attribute \src "libresoc.v:127713.19-127713.134" + wire $ternary$libresoc.v:127713$5384_Y + attribute \src "libresoc.v:127714.19-127714.133" + wire $ternary$libresoc.v:127714$5385_Y + attribute \src "libresoc.v:127715.19-127715.134" + wire $ternary$libresoc.v:127715$5386_Y + attribute \src "libresoc.v:127716.19-127716.134" + wire $ternary$libresoc.v:127716$5387_Y + attribute \src "libresoc.v:127717.19-127717.133" + wire $ternary$libresoc.v:127717$5388_Y + attribute \src "libresoc.v:127718.19-127718.134" + wire $ternary$libresoc.v:127718$5389_Y + attribute \src "libresoc.v:127719.19-127719.134" + wire $ternary$libresoc.v:127719$5390_Y + attribute \src "libresoc.v:127720.19-127720.133" + wire $ternary$libresoc.v:127720$5391_Y + attribute \src "libresoc.v:127721.19-127721.134" + wire $ternary$libresoc.v:127721$5392_Y + attribute \src "libresoc.v:127723.19-127723.134" + wire $ternary$libresoc.v:127723$5394_Y + attribute \src "libresoc.v:127724.19-127724.133" + wire $ternary$libresoc.v:127724$5395_Y + attribute \src "libresoc.v:127725.19-127725.134" + wire $ternary$libresoc.v:127725$5396_Y + attribute \src "libresoc.v:127726.19-127726.134" + wire $ternary$libresoc.v:127726$5397_Y + attribute \src "libresoc.v:127727.19-127727.133" + wire $ternary$libresoc.v:127727$5398_Y + attribute \src "libresoc.v:127728.19-127728.134" + wire $ternary$libresoc.v:127728$5399_Y + attribute \src "libresoc.v:127729.19-127729.135" + wire $ternary$libresoc.v:127729$5400_Y + attribute \src "libresoc.v:127730.19-127730.134" + wire $ternary$libresoc.v:127730$5401_Y + attribute \src "libresoc.v:127731.19-127731.135" + wire $ternary$libresoc.v:127731$5402_Y + attribute \src "libresoc.v:127732.19-127732.135" + wire $ternary$libresoc.v:127732$5403_Y + attribute \src "libresoc.v:127734.19-127734.134" + wire $ternary$libresoc.v:127734$5405_Y + attribute \src "libresoc.v:127735.19-127735.135" + wire $ternary$libresoc.v:127735$5406_Y + attribute \src "libresoc.v:127736.19-127736.133" + wire $ternary$libresoc.v:127736$5407_Y + attribute \src "libresoc.v:127737.19-127737.133" + wire $ternary$libresoc.v:127737$5408_Y + attribute \src "libresoc.v:127738.19-127738.133" + wire $ternary$libresoc.v:127738$5409_Y + attribute \src "libresoc.v:127739.19-127739.133" + wire $ternary$libresoc.v:127739$5410_Y + attribute \src "libresoc.v:127740.19-127740.133" + wire $ternary$libresoc.v:127740$5411_Y + attribute \src "libresoc.v:127741.19-127741.133" + wire $ternary$libresoc.v:127741$5412_Y + attribute \src "libresoc.v:127742.19-127742.133" + wire $ternary$libresoc.v:127742$5413_Y + attribute \src "libresoc.v:127743.19-127743.133" + wire $ternary$libresoc.v:127743$5414_Y + attribute \src "libresoc.v:127745.19-127745.133" + wire $ternary$libresoc.v:127745$5416_Y + attribute \src "libresoc.v:127746.19-127746.133" + wire $ternary$libresoc.v:127746$5417_Y + attribute \src "libresoc.v:127747.19-127747.134" + wire $ternary$libresoc.v:127747$5418_Y + attribute \src "libresoc.v:127748.19-127748.134" + wire $ternary$libresoc.v:127748$5419_Y + attribute \src "libresoc.v:127749.19-127749.135" + wire $ternary$libresoc.v:127749$5420_Y + attribute \src "libresoc.v:127750.19-127750.133" + wire $ternary$libresoc.v:127750$5421_Y + attribute \src "libresoc.v:127751.19-127751.135" + wire $ternary$libresoc.v:127751$5422_Y + attribute \src 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"/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$65 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$67 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$69 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$71 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$73 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$75 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$77 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$79 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$81 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$83 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$85 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$87 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$89 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$95 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 328 \TAP_bus__tck + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 164 \TAP_bus__tdi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire output 319 \TAP_bus__tdo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 329 \TAP_bus__tms + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:414" + wire \TAP_tdo + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" + wire \_fsm_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" + wire \_fsm_isdr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" + wire \_fsm_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" + wire \_fsm_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" + wire \_fsm_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:225" + wire \_idblock_TAP_id_tdo + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375" + wire \_idblock_id_bypass + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" + wire \_idblock_select_id + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" + wire width 4 \_irblock_ir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" + wire \_irblock_tdo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 330 \clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire input 6 \dmi0__ack_o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 4 output 2 \dmi0__addr_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 4 \dmi0__addr_i$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 output 5 \dmi0__din + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 \dmi0__din$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 input 7 \dmi0__dout + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire output 3 \dmi0__req_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire output 4 \dmi0__we_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" + wire width 8 \dmi0_addrsr__i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" + wire width 8 \dmi0_addrsr__o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" + wire \dmi0_addrsr__oe + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" + wire \dmi0_addrsr__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" + wire \dmi0_addrsr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" + wire \dmi0_addrsr_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 8 \dmi0_addrsr_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 8 \dmi0_addrsr_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" + wire \dmi0_addrsr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" + wire \dmi0_addrsr_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \dmi0_addrsr_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \dmi0_addrsr_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \dmi0_addrsr_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \dmi0_addrsr_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" + wire width 64 \dmi0_datasr__i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" + wire width 64 \dmi0_datasr__i$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" + wire width 64 \dmi0_datasr__o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" + wire width 2 \dmi0_datasr__oe + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" + wire width 2 \dmi0_datasr__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" + wire \dmi0_datasr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" + wire width 2 \dmi0_datasr_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 64 \dmi0_datasr_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 64 \dmi0_datasr_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" + wire \dmi0_datasr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" + wire \dmi0_datasr_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \dmi0_datasr_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \dmi0_datasr_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \dmi0_datasr_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \dmi0_datasr_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 165 \eint_0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 10 \eint_0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 166 \eint_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 11 \eint_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 167 \eint_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 12 \eint_2__pad__i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + wire width 3 \fsm_state + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire width 3 \fsm_state$503 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire width 3 \fsm_state$503$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + wire width 3 \fsm_state$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 174 \gpio_e10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 20 \gpio_e10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 21 \gpio_e10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 19 \gpio_e10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 175 \gpio_e10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 176 \gpio_e10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 177 \gpio_e11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 23 \gpio_e11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 24 \gpio_e11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 22 \gpio_e11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 178 \gpio_e11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 179 \gpio_e11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 180 \gpio_e12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 26 \gpio_e12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 27 \gpio_e12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 25 \gpio_e12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 181 \gpio_e12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 182 \gpio_e12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 183 \gpio_e13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 29 \gpio_e13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 30 \gpio_e13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 28 \gpio_e13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 184 \gpio_e13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 185 \gpio_e13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 186 \gpio_e14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 32 \gpio_e14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 33 \gpio_e14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 31 \gpio_e14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 187 \gpio_e14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 188 \gpio_e14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 189 \gpio_e15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 35 \gpio_e15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 36 \gpio_e15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 34 \gpio_e15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 190 \gpio_e15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 191 \gpio_e15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 168 \gpio_e8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 14 \gpio_e8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 15 \gpio_e8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 13 \gpio_e8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 169 \gpio_e8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 170 \gpio_e8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 171 \gpio_e9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 17 \gpio_e9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 18 \gpio_e9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 16 \gpio_e9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 172 \gpio_e9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 173 \gpio_e9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 192 \gpio_s0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 38 \gpio_s0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 39 \gpio_s0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 37 \gpio_s0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 193 \gpio_s0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 194 \gpio_s0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 195 \gpio_s1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 41 \gpio_s1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 42 \gpio_s1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 40 \gpio_s1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 196 \gpio_s1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 197 \gpio_s1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 198 \gpio_s2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 44 \gpio_s2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 45 \gpio_s2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 43 \gpio_s2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 199 \gpio_s2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 200 \gpio_s2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 201 \gpio_s3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 47 \gpio_s3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 48 \gpio_s3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 46 \gpio_s3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 202 \gpio_s3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 203 \gpio_s3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 204 \gpio_s4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 50 \gpio_s4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 51 \gpio_s4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 49 \gpio_s4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 205 \gpio_s4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 206 \gpio_s4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 207 \gpio_s5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 53 \gpio_s5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 54 \gpio_s5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 52 \gpio_s5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 208 \gpio_s5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 209 \gpio_s5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 210 \gpio_s6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 56 \gpio_s6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 57 \gpio_s6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 55 \gpio_s6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 211 \gpio_s6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 212 \gpio_s6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 213 \gpio_s7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 59 \gpio_s7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 60 \gpio_s7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 58 \gpio_s7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 214 \gpio_s7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 215 \gpio_s7__pad__oe + attribute \src "libresoc.v:126214.7-126214.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" + wire width 154 \io_bd + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" + wire width 154 \io_bd$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:395" + wire \io_bd2core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:394" + wire \io_bd2io + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:391" + wire \io_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:392" + wire \io_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire width 154 \io_sr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire width 154 \io_sr$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:393" + wire \io_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire input 326 \jtag_wb__ack + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 29 output 320 \jtag_wb__adr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 29 \jtag_wb__adr$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 322 \jtag_wb__cyc + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 input 327 \jtag_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 output 325 \jtag_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 \jtag_wb__dat_w$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 321 \jtag_wb__sel + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 323 \jtag_wb__stb + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 324 \jtag_wb__we + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" + wire width 29 \jtag_wb_addrsr__i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" + wire width 29 \jtag_wb_addrsr__o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" + wire \jtag_wb_addrsr__oe + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" + wire \jtag_wb_addrsr__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" + wire \jtag_wb_addrsr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" + wire \jtag_wb_addrsr_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 29 \jtag_wb_addrsr_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 29 \jtag_wb_addrsr_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" + wire \jtag_wb_addrsr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" + wire \jtag_wb_addrsr_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \jtag_wb_addrsr_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \jtag_wb_addrsr_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \jtag_wb_addrsr_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \jtag_wb_addrsr_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" + wire width 64 \jtag_wb_datasr__i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" + wire width 64 \jtag_wb_datasr__i$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" + wire width 64 \jtag_wb_datasr__o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" + wire width 2 \jtag_wb_datasr__oe + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" + wire width 2 \jtag_wb_datasr__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" + wire \jtag_wb_datasr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" + wire width 2 \jtag_wb_datasr_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 64 \jtag_wb_datasr_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 64 \jtag_wb_datasr_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" + wire \jtag_wb_datasr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" + wire \jtag_wb_datasr_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \jtag_wb_datasr_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \jtag_wb_datasr_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \jtag_wb_datasr_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \jtag_wb_datasr_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 61 \mspi0_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 216 \mspi0_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 62 \mspi0_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 217 \mspi0_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 219 \mspi0_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 64 \mspi0_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 63 \mspi0_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 218 \mspi0_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 65 \mspi1_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 220 \mspi1_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 66 \mspi1_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 221 \mspi1_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 223 \mspi1_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 68 \mspi1_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 67 \mspi1_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 222 \mspi1_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 72 \mtwi_scl__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 227 \mtwi_scl__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 224 \mtwi_sda__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 70 \mtwi_sda__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 71 \mtwi_sda__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 69 \mtwi_sda__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 225 \mtwi_sda__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 226 \mtwi_sda__pad__oe + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire \negjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire \negjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire \posjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire \posjtag_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 73 \pwm_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 228 \pwm_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 74 \pwm_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 229 \pwm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 78 \sd0_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 233 \sd0_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 230 \sd0_cmd__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 76 \sd0_cmd__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 77 \sd0_cmd__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 75 \sd0_cmd__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 231 \sd0_cmd__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 232 \sd0_cmd__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 234 \sd0_data0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 80 \sd0_data0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 81 \sd0_data0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 79 \sd0_data0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 235 \sd0_data0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 236 \sd0_data0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 237 \sd0_data1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 83 \sd0_data1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 84 \sd0_data1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 82 \sd0_data1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 238 \sd0_data1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 239 \sd0_data1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 240 \sd0_data2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 86 \sd0_data2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 87 \sd0_data2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 85 \sd0_data2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 241 \sd0_data2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 242 \sd0_data2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 243 \sd0_data3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 89 \sd0_data3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 90 \sd0_data3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 88 \sd0_data3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 244 \sd0_data3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 245 \sd0_data3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 116 \sdr_a_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 271 \sdr_a_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 134 \sdr_a_10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 289 \sdr_a_10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 135 \sdr_a_11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 290 \sdr_a_11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 136 \sdr_a_12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 291 \sdr_a_12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 117 \sdr_a_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 272 \sdr_a_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 118 \sdr_a_2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 273 \sdr_a_2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 119 \sdr_a_3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 274 \sdr_a_3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 120 \sdr_a_4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 275 \sdr_a_4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 121 \sdr_a_5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 276 \sdr_a_5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 122 \sdr_a_6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 277 \sdr_a_6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 123 \sdr_a_7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 278 \sdr_a_7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 124 \sdr_a_8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 279 \sdr_a_8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 125 \sdr_a_9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 280 \sdr_a_9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 126 \sdr_ba_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 281 \sdr_ba_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 127 \sdr_ba_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 282 \sdr_ba_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 131 \sdr_cas_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 286 \sdr_cas_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 129 \sdr_cke__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 284 \sdr_cke__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 128 \sdr_clock__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 283 \sdr_clock__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 133 \sdr_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 288 \sdr_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 91 \sdr_dm_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 246 \sdr_dm_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 292 \sdr_dm_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 138 \sdr_dm_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 139 \sdr_dm_1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 137 \sdr_dm_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 293 \sdr_dm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 294 \sdr_dm_1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 247 \sdr_dq_0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 93 \sdr_dq_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 94 \sdr_dq_0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 92 \sdr_dq_0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 248 \sdr_dq_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 249 \sdr_dq_0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 301 \sdr_dq_10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 147 \sdr_dq_10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 148 \sdr_dq_10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 146 \sdr_dq_10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 302 \sdr_dq_10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 303 \sdr_dq_10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 304 \sdr_dq_11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 150 \sdr_dq_11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 151 \sdr_dq_11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 149 \sdr_dq_11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 305 \sdr_dq_11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 306 \sdr_dq_11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 307 \sdr_dq_12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 153 \sdr_dq_12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 154 \sdr_dq_12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 152 \sdr_dq_12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 308 \sdr_dq_12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 309 \sdr_dq_12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 310 \sdr_dq_13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 156 \sdr_dq_13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 157 \sdr_dq_13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 155 \sdr_dq_13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 311 \sdr_dq_13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 312 \sdr_dq_13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 313 \sdr_dq_14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 159 \sdr_dq_14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 160 \sdr_dq_14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 158 \sdr_dq_14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 314 \sdr_dq_14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 315 \sdr_dq_14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 316 \sdr_dq_15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 162 \sdr_dq_15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 163 \sdr_dq_15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 161 \sdr_dq_15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 317 \sdr_dq_15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 318 \sdr_dq_15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 250 \sdr_dq_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 96 \sdr_dq_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 97 \sdr_dq_1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 95 \sdr_dq_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 251 \sdr_dq_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 252 \sdr_dq_1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 253 \sdr_dq_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 99 \sdr_dq_2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 100 \sdr_dq_2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 98 \sdr_dq_2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 254 \sdr_dq_2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 255 \sdr_dq_2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 256 \sdr_dq_3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 102 \sdr_dq_3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 103 \sdr_dq_3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 101 \sdr_dq_3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 257 \sdr_dq_3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 258 \sdr_dq_3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 259 \sdr_dq_4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 105 \sdr_dq_4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 106 \sdr_dq_4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 104 \sdr_dq_4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 260 \sdr_dq_4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 261 \sdr_dq_4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 262 \sdr_dq_5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 108 \sdr_dq_5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 109 \sdr_dq_5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 107 \sdr_dq_5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 263 \sdr_dq_5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 264 \sdr_dq_5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 265 \sdr_dq_6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 111 \sdr_dq_6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 112 \sdr_dq_6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 110 \sdr_dq_6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 266 \sdr_dq_6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 267 \sdr_dq_6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 268 \sdr_dq_7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 114 \sdr_dq_7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 115 \sdr_dq_7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 113 \sdr_dq_7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 269 \sdr_dq_7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 270 \sdr_dq_7__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 295 \sdr_dq_8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 141 \sdr_dq_8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 142 \sdr_dq_8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 140 \sdr_dq_8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 296 \sdr_dq_8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 297 \sdr_dq_8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 298 \sdr_dq_9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 144 \sdr_dq_9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 145 \sdr_dq_9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 143 \sdr_dq_9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 299 \sdr_dq_9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 300 \sdr_dq_9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 130 \sdr_ras_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 285 \sdr_ras_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 132 \sdr_we_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 287 \sdr_we_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" + wire width 3 \sr0__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" + wire width 3 \sr0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" + wire \sr0__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" + wire \sr0__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" + wire \sr0_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" + wire \sr0_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 3 \sr0_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 3 \sr0_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" + wire \sr0_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" + wire \sr0_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \sr0_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \sr0_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \sr0_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \sr0_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" + wire width 2 \sr5__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" + wire \sr5__ie + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" + wire width 2 \sr5__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" + wire \sr5__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" + wire \sr5__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" + wire \sr5_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" + wire \sr5_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 2 \sr5_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 2 \sr5_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" + wire \sr5_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" + wire \sr5_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \sr5_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \sr5_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \sr5_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \sr5_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" + wire output 8 \wb_dcache_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" + wire \wb_dcache_en$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" + wire output 9 \wb_icache_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" + wire \wb_icache_en$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" + cell $add $add$libresoc.v:127864$5535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 29 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 30 + connect \A \jtag_wb__adr + connect \B 1'1 + connect \Y $add$libresoc.v:127864$5535_Y end - attribute \src "libresoc.v:31266.3-31314.6" - process $proc$libresoc.v:31266$672 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_lk[0:0] $1\dec31_dec_sub23_lk[0:0] - attribute \src "libresoc.v:31267.5-31267.29" - switch \initial - attribute \src "libresoc.v:31267.9-31267.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub23_lk $0\dec31_dec_sub23_lk[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" + cell $add $add$libresoc.v:127866$5537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 29 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 30 + connect \A \jtag_wb__adr + connect \B 1'1 + connect \Y $add$libresoc.v:127866$5537_Y end - attribute \src "libresoc.v:31315.3-31363.6" - process $proc$libresoc.v:31315$673 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_sgl_pipe[0:0] $1\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "libresoc.v:31316.5-31316.29" - switch \initial - attribute \src "libresoc.v:31316.9-31316.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - case - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub23_sgl_pipe $0\dec31_dec_sub23_sgl_pipe[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" + cell $add $add$libresoc.v:127872$5544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \dmi0__addr_i + connect \B 1'1 + connect \Y $add$libresoc.v:127872$5544_Y end - attribute \src "libresoc.v:31364.3-31412.6" - process $proc$libresoc.v:31364$674 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_form[4:0] $1\dec31_dec_sub23_form[4:0] - attribute \src "libresoc.v:31365.5-31365.29" - switch \initial - attribute \src "libresoc.v:31365.9-31365.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - case - assign $1\dec31_dec_sub23_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub23_form $0\dec31_dec_sub23_form[4:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" + cell $add $add$libresoc.v:127873$5545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \dmi0__addr_i + connect \B 1'1 + connect \Y $add$libresoc.v:127873$5545_Y end - attribute \src "libresoc.v:31413.3-31461.6" - process $proc$libresoc.v:31413$675 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_in1_sel[2:0] $1\dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:31414.5-31414.29" - switch \initial - attribute \src "libresoc.v:31414.9-31414.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - case - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub23_in1_sel $0\dec31_dec_sub23_in1_sel[2:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400" + cell $and $and$libresoc.v:127688$5359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$15 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:127688$5359_Y end - attribute \src "libresoc.v:31462.3-31510.6" - process $proc$libresoc.v:31462$676 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_in2_sel[3:0] $1\dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:31463.5-31463.29" - switch \initial - attribute \src "libresoc.v:31463.9-31463.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub23_in2_sel $0\dec31_dec_sub23_in2_sel[3:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $and $and$libresoc.v:127755$5426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_fsm_isdr + connect \B \$27 + connect \Y $and$libresoc.v:127755$5426_Y end - attribute \src "libresoc.v:31511.3-31559.6" - process $proc$libresoc.v:31511$677 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_in3_sel[1:0] $1\dec31_dec_sub23_in3_sel[1:0] - attribute \src "libresoc.v:31512.5-31512.29" - switch \initial - attribute \src "libresoc.v:31512.9-31512.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub23_in3_sel $0\dec31_dec_sub23_in3_sel[1:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" + cell $and $and$libresoc.v:127766$5437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$29 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:127766$5437_Y end - attribute \src "libresoc.v:31560.3-31608.6" - process $proc$libresoc.v:31560$678 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_out_sel[1:0] $1\dec31_dec_sub23_out_sel[1:0] - attribute \src "libresoc.v:31561.5-31561.29" - switch \initial - attribute \src "libresoc.v:31561.9-31561.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub23_out_sel $0\dec31_dec_sub23_out_sel[1:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $and $and$libresoc.v:127794$5465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_fsm_isdr + connect \B \$367 + connect \Y $and$libresoc.v:127794$5465_Y end - attribute \src "libresoc.v:31609.3-31657.6" - process $proc$libresoc.v:31609$679 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_cr_in[2:0] $1\dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:31610.5-31610.29" - switch \initial - attribute \src "libresoc.v:31610.9-31610.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub23_cr_in $0\dec31_dec_sub23_cr_in[2:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $and $and$libresoc.v:127797$5468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$373 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:127797$5468_Y end - attribute \src "libresoc.v:31658.3-31706.6" - process $proc$libresoc.v:31658$680 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_cr_out[2:0] $1\dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:31659.5-31659.29" - switch \initial - attribute \src "libresoc.v:31659.9-31659.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - case - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub23_cr_out $0\dec31_dec_sub23_cr_out[2:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $and $and$libresoc.v:127800$5471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$377 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:127800$5471_Y end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:31712.1-32427.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub24" -attribute \generator "nMigen" -module \dec31_dec_sub24 - attribute \src "libresoc.v:32065.3-32083.6" - wire width 8 $0\dec31_dec_sub24_asmcode[7:0] - attribute \src "libresoc.v:32141.3-32159.6" - wire $0\dec31_dec_sub24_br[0:0] - attribute \src "libresoc.v:32388.3-32406.6" - wire width 3 $0\dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:32407.3-32425.6" - wire width 3 $0\dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:32046.3-32064.6" - wire width 2 $0\dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:32122.3-32140.6" - wire $0\dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:32293.3-32311.6" - wire width 5 $0\dec31_dec_sub24_form[4:0] - attribute \src "libresoc.v:31970.3-31988.6" - wire width 12 $0\dec31_dec_sub24_function_unit[11:0] - attribute \src "libresoc.v:32312.3-32330.6" - wire width 3 $0\dec31_dec_sub24_in1_sel[2:0] - attribute \src "libresoc.v:32331.3-32349.6" - wire width 4 $0\dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:32350.3-32368.6" - wire width 2 $0\dec31_dec_sub24_in3_sel[1:0] - attribute \src "libresoc.v:32179.3-32197.6" - wire width 7 $0\dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:32084.3-32102.6" - wire $0\dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:32103.3-32121.6" - wire $0\dec31_dec_sub24_inv_out[0:0] - attribute \src "libresoc.v:32217.3-32235.6" - wire $0\dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:31989.3-32007.6" - wire width 4 $0\dec31_dec_sub24_ldst_len[3:0] - attribute \src "libresoc.v:32255.3-32273.6" - wire $0\dec31_dec_sub24_lk[0:0] - attribute \src "libresoc.v:32369.3-32387.6" - wire width 2 $0\dec31_dec_sub24_out_sel[1:0] - attribute \src "libresoc.v:32027.3-32045.6" - wire width 2 $0\dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:32198.3-32216.6" - wire $0\dec31_dec_sub24_rsrv[0:0] - attribute \src "libresoc.v:32274.3-32292.6" - wire $0\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "libresoc.v:32236.3-32254.6" - wire $0\dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:32160.3-32178.6" - wire $0\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "libresoc.v:32008.3-32026.6" - wire width 2 $0\dec31_dec_sub24_upd[1:0] - attribute \src "libresoc.v:31713.7-31713.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:32065.3-32083.6" - wire width 8 $1\dec31_dec_sub24_asmcode[7:0] - attribute \src "libresoc.v:32141.3-32159.6" - wire $1\dec31_dec_sub24_br[0:0] - attribute \src "libresoc.v:32388.3-32406.6" - wire width 3 $1\dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:32407.3-32425.6" - wire width 3 $1\dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:32046.3-32064.6" - wire width 2 $1\dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:32122.3-32140.6" - wire $1\dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:32293.3-32311.6" - wire width 5 $1\dec31_dec_sub24_form[4:0] - attribute \src "libresoc.v:31970.3-31988.6" - wire width 12 $1\dec31_dec_sub24_function_unit[11:0] - attribute \src "libresoc.v:32312.3-32330.6" - wire width 3 $1\dec31_dec_sub24_in1_sel[2:0] - attribute \src "libresoc.v:32331.3-32349.6" - wire width 4 $1\dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:32350.3-32368.6" - wire width 2 $1\dec31_dec_sub24_in3_sel[1:0] - attribute \src "libresoc.v:32179.3-32197.6" - wire width 7 $1\dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:32084.3-32102.6" - wire $1\dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:32103.3-32121.6" - wire $1\dec31_dec_sub24_inv_out[0:0] - attribute \src "libresoc.v:32217.3-32235.6" - wire $1\dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:31989.3-32007.6" - wire width 4 $1\dec31_dec_sub24_ldst_len[3:0] - attribute \src "libresoc.v:32255.3-32273.6" - wire $1\dec31_dec_sub24_lk[0:0] - attribute \src "libresoc.v:32369.3-32387.6" - wire width 2 $1\dec31_dec_sub24_out_sel[1:0] - attribute \src "libresoc.v:32027.3-32045.6" - wire width 2 $1\dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:32198.3-32216.6" - wire $1\dec31_dec_sub24_rsrv[0:0] - attribute \src "libresoc.v:32274.3-32292.6" - wire $1\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "libresoc.v:32236.3-32254.6" - wire $1\dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:32160.3-32178.6" - wire $1\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "libresoc.v:32008.3-32026.6" - wire width 2 $1\dec31_dec_sub24_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub24_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub24_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub24_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub24_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub24_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub24_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub24_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub24_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub24_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub24_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub24_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub24_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub24_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub24_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub24_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub24_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub24_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub24_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub24_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub24_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub24_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub24_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub24_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub24_upd - attribute \src "libresoc.v:31713.7-31713.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:31713.7-31713.20" - process $proc$libresoc.v:31713$706 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:127802$5473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$381 + connect \B \_fsm_update + connect \Y $and$libresoc.v:127802$5473_Y end - attribute \src "libresoc.v:31970.3-31988.6" - process $proc$libresoc.v:31970$682 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_function_unit[11:0] $1\dec31_dec_sub24_function_unit[11:0] - attribute \src "libresoc.v:31971.5-31971.29" - switch \initial - attribute \src "libresoc.v:31971.9-31971.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 - case - assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub24_function_unit $0\dec31_dec_sub24_function_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $and $and$libresoc.v:127804$5475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr0_update_core_prev + connect \B \$385 + connect \Y $and$libresoc.v:127804$5475_Y end - attribute \src "libresoc.v:31989.3-32007.6" - process $proc$libresoc.v:31989$683 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_ldst_len[3:0] $1\dec31_dec_sub24_ldst_len[3:0] - attribute \src "libresoc.v:31990.5-31990.29" - switch \initial - attribute \src "libresoc.v:31990.9-31990.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub24_ldst_len $0\dec31_dec_sub24_ldst_len[3:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $and $and$libresoc.v:127807$5478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$391 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:127807$5478_Y end - attribute \src "libresoc.v:32008.3-32026.6" - process $proc$libresoc.v:32008$684 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_upd[1:0] $1\dec31_dec_sub24_upd[1:0] - attribute \src "libresoc.v:32009.5-32009.29" - switch \initial - attribute \src "libresoc.v:32009.9-32009.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub24_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub24_upd $0\dec31_dec_sub24_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $and $and$libresoc.v:127809$5480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$395 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:127809$5480_Y end - attribute \src "libresoc.v:32027.3-32045.6" - process $proc$libresoc.v:32027$685 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_rc_sel[1:0] $1\dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:32028.5-32028.29" - switch \initial - attribute \src "libresoc.v:32028.9-32028.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub24_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub24_rc_sel $0\dec31_dec_sub24_rc_sel[1:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:127813$5484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$399 + connect \B \_fsm_update + connect \Y $and$libresoc.v:127813$5484_Y end - attribute \src "libresoc.v:32046.3-32064.6" - process $proc$libresoc.v:32046$686 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_cry_in[1:0] $1\dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:32047.5-32047.29" - switch \initial - attribute \src "libresoc.v:32047.9-32047.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub24_cry_in $0\dec31_dec_sub24_cry_in[1:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $and $and$libresoc.v:127815$5486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_addrsr_update_core_prev + connect \B \$403 + connect \Y $and$libresoc.v:127815$5486_Y end - attribute \src "libresoc.v:32065.3-32083.6" - process $proc$libresoc.v:32065$687 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_asmcode[7:0] $1\dec31_dec_sub24_asmcode[7:0] - attribute \src "libresoc.v:32066.5-32066.29" - switch \initial - attribute \src "libresoc.v:32066.9-32066.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_asmcode[7:0] 8'10011111 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100101 - case - assign $1\dec31_dec_sub24_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub24_asmcode $0\dec31_dec_sub24_asmcode[7:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $and $and$libresoc.v:127819$5490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$411 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:127819$5490_Y end - attribute \src "libresoc.v:32084.3-32102.6" - process $proc$libresoc.v:32084$688 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_inv_a[0:0] $1\dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:32085.5-32085.29" - switch \initial - attribute \src "libresoc.v:32085.9-32085.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_inv_a $0\dec31_dec_sub24_inv_a[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $and $and$libresoc.v:127821$5492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$415 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:127821$5492_Y end - attribute \src "libresoc.v:32103.3-32121.6" - process $proc$libresoc.v:32103$689 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_inv_out[0:0] $1\dec31_dec_sub24_inv_out[0:0] - attribute \src "libresoc.v:32104.5-32104.29" - switch \initial - attribute \src "libresoc.v:32104.9-32104.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_inv_out $0\dec31_dec_sub24_inv_out[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:127824$5495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$419 + connect \B \_fsm_update + connect \Y $and$libresoc.v:127824$5495_Y end - attribute \src "libresoc.v:32122.3-32140.6" - process $proc$libresoc.v:32122$690 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_cry_out[0:0] $1\dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:32123.5-32123.29" - switch \initial - attribute \src "libresoc.v:32123.9-32123.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_cry_out $0\dec31_dec_sub24_cry_out[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $and $and$libresoc.v:127826$5497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_datasr_update_core_prev + connect \B \$423 + connect \Y $and$libresoc.v:127826$5497_Y end - attribute \src "libresoc.v:32141.3-32159.6" - process $proc$libresoc.v:32141$691 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_br[0:0] $1\dec31_dec_sub24_br[0:0] - attribute \src "libresoc.v:32142.5-32142.29" - switch \initial - attribute \src "libresoc.v:32142.9-32142.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_br[0:0] 1'0 - case - assign $1\dec31_dec_sub24_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_br $0\dec31_dec_sub24_br[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $and $and$libresoc.v:127829$5500 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$429 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:127829$5500_Y end - attribute \src "libresoc.v:32160.3-32178.6" - process $proc$libresoc.v:32160$692 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_sgn_ext[0:0] $1\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "libresoc.v:32161.5-32161.29" - switch \initial - attribute \src "libresoc.v:32161.9-32161.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_sgn_ext $0\dec31_dec_sub24_sgn_ext[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $and $and$libresoc.v:127831$5502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$433 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:127831$5502_Y end - attribute \src "libresoc.v:32179.3-32197.6" - process $proc$libresoc.v:32179$693 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_internal_op[6:0] $1\dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:32180.5-32180.29" - switch \initial - attribute \src "libresoc.v:32180.9-32180.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 - case - assign $1\dec31_dec_sub24_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub24_internal_op $0\dec31_dec_sub24_internal_op[6:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $and $and$libresoc.v:127833$5504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_fsm_isdr + connect \B \$41 + connect \Y $and$libresoc.v:127833$5504_Y end - attribute \src "libresoc.v:32198.3-32216.6" - process $proc$libresoc.v:32198$694 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_rsrv[0:0] $1\dec31_dec_sub24_rsrv[0:0] - attribute \src "libresoc.v:32199.5-32199.29" - switch \initial - attribute \src "libresoc.v:32199.9-32199.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_rsrv $0\dec31_dec_sub24_rsrv[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:127834$5505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$437 + connect \B \_fsm_update + connect \Y $and$libresoc.v:127834$5505_Y end - attribute \src "libresoc.v:32217.3-32235.6" - process $proc$libresoc.v:32217$695 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_is_32b[0:0] $1\dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:32218.5-32218.29" - switch \initial - attribute \src "libresoc.v:32218.9-32218.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 - case - assign $1\dec31_dec_sub24_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_is_32b $0\dec31_dec_sub24_is_32b[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $and $and$libresoc.v:127836$5507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_addrsr_update_core_prev + connect \B \$441 + connect \Y $and$libresoc.v:127836$5507_Y end - attribute \src "libresoc.v:32236.3-32254.6" - process $proc$libresoc.v:32236$696 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_sgn[0:0] $1\dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:32237.5-32237.29" - switch \initial - attribute \src "libresoc.v:32237.9-32237.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub24_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_sgn $0\dec31_dec_sub24_sgn[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $and $and$libresoc.v:127840$5511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$449 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:127840$5511_Y end - attribute \src "libresoc.v:32255.3-32273.6" - process $proc$libresoc.v:32255$697 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_lk[0:0] $1\dec31_dec_sub24_lk[0:0] - attribute \src "libresoc.v:32256.5-32256.29" - switch \initial - attribute \src "libresoc.v:32256.9-32256.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub24_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_lk $0\dec31_dec_sub24_lk[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $and $and$libresoc.v:127842$5513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$453 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:127842$5513_Y end - attribute \src "libresoc.v:32274.3-32292.6" - process $proc$libresoc.v:32274$698 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_sgl_pipe[0:0] $1\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "libresoc.v:32275.5-32275.29" - switch \initial - attribute \src "libresoc.v:32275.9-32275.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_sgl_pipe $0\dec31_dec_sub24_sgl_pipe[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" + cell $and $and$libresoc.v:127844$5515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$43 + connect \B \_fsm_update + connect \Y $and$libresoc.v:127844$5515_Y end - attribute \src "libresoc.v:32293.3-32311.6" - process $proc$libresoc.v:32293$699 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_form[4:0] $1\dec31_dec_sub24_form[4:0] - attribute \src "libresoc.v:32294.5-32294.29" - switch \initial - attribute \src "libresoc.v:32294.9-32294.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_form[4:0] 5'01000 - case - assign $1\dec31_dec_sub24_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub24_form $0\dec31_dec_sub24_form[4:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:127845$5516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$457 + connect \B \_fsm_update + connect \Y $and$libresoc.v:127845$5516_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $and $and$libresoc.v:127847$5518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_datasr_update_core_prev + connect \B \$461 + connect \Y $and$libresoc.v:127847$5518_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $and $and$libresoc.v:127850$5521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$467 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:127850$5521_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $and $and$libresoc.v:127852$5523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$471 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:127852$5523_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:127854$5525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$475 + connect \B \_fsm_update + connect \Y $and$libresoc.v:127854$5525_Y end - attribute \src "libresoc.v:32312.3-32330.6" - process $proc$libresoc.v:32312$700 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_in1_sel[2:0] $1\dec31_dec_sub24_in1_sel[2:0] - attribute \src "libresoc.v:32313.5-32313.29" - switch \initial - attribute \src "libresoc.v:32313.9-32313.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 - case - assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub24_in1_sel $0\dec31_dec_sub24_in1_sel[2:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $and $and$libresoc.v:127857$5528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr5_update_core_prev + connect \B \$479 + connect \Y $and$libresoc.v:127857$5528_Y end - attribute \src "libresoc.v:32331.3-32349.6" - process $proc$libresoc.v:32331$701 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_in2_sel[3:0] $1\dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:32332.5-32332.29" - switch \initial - attribute \src "libresoc.v:32332.9-32332.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_in2_sel[3:0] 4'1011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub24_in2_sel $0\dec31_dec_sub24_in2_sel[3:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + cell $and $and$libresoc.v:127889$5561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_fsm_isdr + connect \B \$5 + connect \Y $and$libresoc.v:127889$5561_Y end - attribute \src "libresoc.v:32350.3-32368.6" - process $proc$libresoc.v:32350$702 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_in3_sel[1:0] $1\dec31_dec_sub24_in3_sel[1:0] - attribute \src "libresoc.v:32351.5-32351.29" - switch \initial - attribute \src "libresoc.v:32351.9-32351.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub24_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub24_in3_sel $0\dec31_dec_sub24_in3_sel[1:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $eq $eq$libresoc.v:127644$5315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 4'1111 + connect \Y $eq$libresoc.v:127644$5315_Y end - attribute \src "libresoc.v:32369.3-32387.6" - process $proc$libresoc.v:32369$703 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_out_sel[1:0] $1\dec31_dec_sub24_out_sel[1:0] - attribute \src "libresoc.v:32370.5-32370.29" - switch \initial - attribute \src "libresoc.v:32370.9-32370.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub24_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub24_out_sel $0\dec31_dec_sub24_out_sel[1:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $eq $eq$libresoc.v:127655$5326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'0 + connect \Y $eq$libresoc.v:127655$5326_Y end - attribute \src "libresoc.v:32388.3-32406.6" - process $proc$libresoc.v:32388$704 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_cr_in[2:0] $1\dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:32389.5-32389.29" - switch \initial - attribute \src "libresoc.v:32389.9-32389.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub24_cr_in $0\dec31_dec_sub24_cr_in[2:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $eq $eq$libresoc.v:127666$5337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:127666$5337_Y end - attribute \src "libresoc.v:32407.3-32425.6" - process $proc$libresoc.v:32407$705 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_cr_out[2:0] $1\dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:32408.5-32408.29" - switch \initial - attribute \src "libresoc.v:32408.9-32408.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 - case - assign $1\dec31_dec_sub24_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub24_cr_out $0\dec31_dec_sub24_cr_out[2:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + cell $eq $eq$libresoc.v:127699$5370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'1 + connect \Y $eq$libresoc.v:127699$5370_Y end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:32431.1-33938.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub26" -attribute \generator "nMigen" -module \dec31_dec_sub26 - attribute \src "libresoc.v:32949.3-33000.6" - wire width 8 $0\dec31_dec_sub26_asmcode[7:0] - attribute \src "libresoc.v:33157.3-33208.6" - wire $0\dec31_dec_sub26_br[0:0] - attribute \src "libresoc.v:33833.3-33884.6" - wire width 3 $0\dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:33885.3-33936.6" - wire width 3 $0\dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:32897.3-32948.6" - wire width 2 $0\dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:33105.3-33156.6" - wire $0\dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:33573.3-33624.6" - wire width 5 $0\dec31_dec_sub26_form[4:0] - attribute \src "libresoc.v:32689.3-32740.6" - wire width 12 $0\dec31_dec_sub26_function_unit[11:0] - attribute \src "libresoc.v:33625.3-33676.6" - wire width 3 $0\dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:33677.3-33728.6" - wire width 4 $0\dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:33729.3-33780.6" - wire width 2 $0\dec31_dec_sub26_in3_sel[1:0] - attribute \src "libresoc.v:33261.3-33312.6" - wire width 7 $0\dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:33001.3-33052.6" - wire $0\dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:33053.3-33104.6" - wire $0\dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:33365.3-33416.6" - wire $0\dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:32741.3-32792.6" - wire width 4 $0\dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:33469.3-33520.6" - wire $0\dec31_dec_sub26_lk[0:0] - attribute \src "libresoc.v:33781.3-33832.6" - wire width 2 $0\dec31_dec_sub26_out_sel[1:0] - attribute \src "libresoc.v:32845.3-32896.6" - wire width 2 $0\dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:33313.3-33364.6" - wire $0\dec31_dec_sub26_rsrv[0:0] - attribute \src "libresoc.v:33521.3-33572.6" - wire $0\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "libresoc.v:33417.3-33468.6" - wire $0\dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:33209.3-33260.6" - wire $0\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "libresoc.v:32793.3-32844.6" - wire width 2 $0\dec31_dec_sub26_upd[1:0] - attribute \src "libresoc.v:32432.7-32432.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:32949.3-33000.6" - wire width 8 $1\dec31_dec_sub26_asmcode[7:0] - attribute \src "libresoc.v:33157.3-33208.6" - wire $1\dec31_dec_sub26_br[0:0] - attribute \src "libresoc.v:33833.3-33884.6" - wire width 3 $1\dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:33885.3-33936.6" - wire width 3 $1\dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:32897.3-32948.6" - wire width 2 $1\dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:33105.3-33156.6" - wire $1\dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:33573.3-33624.6" - wire width 5 $1\dec31_dec_sub26_form[4:0] - attribute \src "libresoc.v:32689.3-32740.6" - wire width 12 $1\dec31_dec_sub26_function_unit[11:0] - attribute \src "libresoc.v:33625.3-33676.6" - wire width 3 $1\dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:33677.3-33728.6" - wire width 4 $1\dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:33729.3-33780.6" - wire width 2 $1\dec31_dec_sub26_in3_sel[1:0] - attribute \src "libresoc.v:33261.3-33312.6" - wire width 7 $1\dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:33001.3-33052.6" - wire $1\dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:33053.3-33104.6" - wire $1\dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:33365.3-33416.6" - wire $1\dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:32741.3-32792.6" - wire width 4 $1\dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:33469.3-33520.6" - wire $1\dec31_dec_sub26_lk[0:0] - attribute \src "libresoc.v:33781.3-33832.6" - wire width 2 $1\dec31_dec_sub26_out_sel[1:0] - attribute \src "libresoc.v:32845.3-32896.6" - wire width 2 $1\dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:33313.3-33364.6" - wire $1\dec31_dec_sub26_rsrv[0:0] - attribute \src "libresoc.v:33521.3-33572.6" - wire $1\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "libresoc.v:33417.3-33468.6" - wire $1\dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:33209.3-33260.6" - wire $1\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "libresoc.v:32793.3-32844.6" - wire width 2 $1\dec31_dec_sub26_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub26_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub26_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub26_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub26_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub26_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub26_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub26_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub26_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub26_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub26_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub26_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub26_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub26_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub26_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub26_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub26_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub26_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub26_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub26_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub26_upd - attribute \src "libresoc.v:32432.7-32432.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:32432.7-32432.20" - process $proc$libresoc.v:32432$731 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $eq $eq$libresoc.v:127700$5371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'0 + connect \Y $eq$libresoc.v:127700$5371_Y end - attribute \src "libresoc.v:32689.3-32740.6" - process $proc$libresoc.v:32689$707 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_function_unit[11:0] $1\dec31_dec_sub26_function_unit[11:0] - attribute \src "libresoc.v:32690.5-32690.29" - switch \initial - attribute \src "libresoc.v:32690.9-32690.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000 - case - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub26_function_unit $0\dec31_dec_sub26_function_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $eq $eq$libresoc.v:127711$5382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:127711$5382_Y end - attribute \src "libresoc.v:32741.3-32792.6" - process $proc$libresoc.v:32741$708 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_ldst_len[3:0] $1\dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:32742.5-32742.29" - switch \initial - attribute \src "libresoc.v:32742.9-32742.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub26_ldst_len $0\dec31_dec_sub26_ldst_len[3:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" + cell $eq $eq$libresoc.v:127733$5404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:127733$5404_Y end - attribute \src "libresoc.v:32793.3-32844.6" - process $proc$libresoc.v:32793$709 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_upd[1:0] $1\dec31_dec_sub26_upd[1:0] - attribute \src "libresoc.v:32794.5-32794.29" - switch \initial - attribute \src "libresoc.v:32794.9-32794.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub26_upd $0\dec31_dec_sub26_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $eq $eq$libresoc.v:127777$5448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'0 + connect \Y $eq$libresoc.v:127777$5448_Y end - attribute \src "libresoc.v:32845.3-32896.6" - process $proc$libresoc.v:32845$710 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_rc_sel[1:0] $1\dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:32846.5-32846.29" - switch \initial - attribute \src "libresoc.v:32846.9-32846.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub26_rc_sel $0\dec31_dec_sub26_rc_sel[1:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $eq $eq$libresoc.v:127788$5459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:127788$5459_Y end - attribute \src "libresoc.v:32897.3-32948.6" - process $proc$libresoc.v:32897$711 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_cry_in[1:0] $1\dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:32898.5-32898.29" - switch \initial - attribute \src "libresoc.v:32898.9-32898.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub26_cry_in $0\dec31_dec_sub26_cry_in[1:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $eq $eq$libresoc.v:127789$5460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'0 + connect \Y $eq$libresoc.v:127789$5460_Y end - attribute \src "libresoc.v:32949.3-33000.6" - process $proc$libresoc.v:32949$712 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_asmcode[7:0] $1\dec31_dec_sub26_asmcode[7:0] - attribute \src "libresoc.v:32950.5-32950.29" - switch \initial - attribute \src "libresoc.v:32950.9-32950.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000111 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001111 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'10010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'10100000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'10100001 - case - assign $1\dec31_dec_sub26_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub26_asmcode $0\dec31_dec_sub26_asmcode[7:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $eq $eq$libresoc.v:127790$5461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:127790$5461_Y end - attribute \src "libresoc.v:33001.3-33052.6" - process $proc$libresoc.v:33001$713 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_inv_a[0:0] $1\dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:33002.5-33002.29" - switch \initial - attribute \src "libresoc.v:33002.9-33002.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_inv_a $0\dec31_dec_sub26_inv_a[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" + cell $eq $eq$libresoc.v:127792$5463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:127792$5463_Y end - attribute \src "libresoc.v:33053.3-33104.6" - process $proc$libresoc.v:33053$714 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_inv_out[0:0] $1\dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:33054.5-33054.29" - switch \initial - attribute \src "libresoc.v:33054.9-33054.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_inv_out $0\dec31_dec_sub26_inv_out[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + cell $eq $eq$libresoc.v:127795$5466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 3'100 + connect \Y $eq$libresoc.v:127795$5466_Y end - attribute \src "libresoc.v:33105.3-33156.6" - process $proc$libresoc.v:33105$715 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_cry_out[0:0] $1\dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:33106.5-33106.29" - switch \initial - attribute \src "libresoc.v:33106.9-33106.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'1 - case - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_cry_out $0\dec31_dec_sub26_cry_out[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + cell $eq $eq$libresoc.v:127805$5476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 3'101 + connect \Y $eq$libresoc.v:127805$5476_Y end - attribute \src "libresoc.v:33157.3-33208.6" - process $proc$libresoc.v:33157$716 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_br[0:0] $1\dec31_dec_sub26_br[0:0] - attribute \src "libresoc.v:33158.5-33158.29" - switch \initial - attribute \src "libresoc.v:33158.9-33158.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - case - assign $1\dec31_dec_sub26_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_br $0\dec31_dec_sub26_br[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + cell $eq $eq$libresoc.v:127810$5481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 4'1111 + connect \Y $eq$libresoc.v:127810$5481_Y end - attribute \src "libresoc.v:33209.3-33260.6" - process $proc$libresoc.v:33209$717 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_sgn_ext[0:0] $1\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "libresoc.v:33210.5-33210.29" - switch \initial - attribute \src "libresoc.v:33210.9-33210.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_sgn_ext $0\dec31_dec_sub26_sgn_ext[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" + cell $eq $eq$libresoc.v:127811$5482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:127811$5482_Y end - attribute \src "libresoc.v:33261.3-33312.6" - process $proc$libresoc.v:33261$718 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_internal_op[6:0] $1\dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:33262.5-33262.29" - switch \initial - attribute \src "libresoc.v:33262.9-33262.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0100000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 - case - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub26_internal_op $0\dec31_dec_sub26_internal_op[6:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + cell $eq $eq$libresoc.v:127816$5487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 3'110 + connect \Y $eq$libresoc.v:127816$5487_Y end - attribute \src "libresoc.v:33313.3-33364.6" - process $proc$libresoc.v:33313$719 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_rsrv[0:0] $1\dec31_dec_sub26_rsrv[0:0] - attribute \src "libresoc.v:33314.5-33314.29" - switch \initial - attribute \src "libresoc.v:33314.9-33314.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_rsrv $0\dec31_dec_sub26_rsrv[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + cell $eq $eq$libresoc.v:127817$5488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 3'111 + connect \Y $eq$libresoc.v:127817$5488_Y end - attribute \src "libresoc.v:33365.3-33416.6" - process $proc$libresoc.v:33365$720 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_is_32b[0:0] $1\dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:33366.5-33366.29" - switch \initial - attribute \src "libresoc.v:33366.9-33366.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_is_32b $0\dec31_dec_sub26_is_32b[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + cell $eq $eq$libresoc.v:127827$5498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 4'1000 + connect \Y $eq$libresoc.v:127827$5498_Y end - attribute \src "libresoc.v:33417.3-33468.6" - process $proc$libresoc.v:33417$721 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_sgn[0:0] $1\dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:33418.5-33418.29" - switch \initial - attribute \src "libresoc.v:33418.9-33418.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'1 - case - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_sgn $0\dec31_dec_sub26_sgn[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + cell $eq $eq$libresoc.v:127837$5508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 4'1001 + connect \Y $eq$libresoc.v:127837$5508_Y end - attribute \src "libresoc.v:33469.3-33520.6" - process $proc$libresoc.v:33469$722 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_lk[0:0] $1\dec31_dec_sub26_lk[0:0] - attribute \src "libresoc.v:33470.5-33470.29" - switch \initial - attribute \src "libresoc.v:33470.9-33470.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_lk $0\dec31_dec_sub26_lk[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + cell $eq $eq$libresoc.v:127838$5509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 4'1010 + connect \Y $eq$libresoc.v:127838$5509_Y end - attribute \src "libresoc.v:33521.3-33572.6" - process $proc$libresoc.v:33521$723 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_sgl_pipe[0:0] $1\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "libresoc.v:33522.5-33522.29" - switch \initial - attribute \src "libresoc.v:33522.9-33522.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_sgl_pipe $0\dec31_dec_sub26_sgl_pipe[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + cell $eq $eq$libresoc.v:127848$5519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 4'1011 + connect \Y $eq$libresoc.v:127848$5519_Y end - attribute \src "libresoc.v:33573.3-33624.6" - process $proc$libresoc.v:33573$724 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_form[4:0] $1\dec31_dec_sub26_form[4:0] - attribute \src "libresoc.v:33574.5-33574.29" - switch \initial - attribute \src "libresoc.v:33574.9-33574.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'10000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'10000 - case - assign $1\dec31_dec_sub26_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub26_form $0\dec31_dec_sub26_form[4:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" + cell $eq $eq$libresoc.v:127855$5526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'0 + connect \Y $eq$libresoc.v:127855$5526_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" + cell $eq $eq$libresoc.v:127858$5529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 1'0 + connect \Y $eq$libresoc.v:127858$5529_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" + cell $eq $eq$libresoc.v:127860$5531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 1'1 + connect \Y $eq$libresoc.v:127860$5531_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" + cell $eq $eq$libresoc.v:127861$5532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 2'10 + connect \Y $eq$libresoc.v:127861$5532_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:792" + cell $eq $eq$libresoc.v:127863$5534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 2'10 + connect \Y $eq$libresoc.v:127863$5534_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" + cell $eq $eq$libresoc.v:127865$5536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'0 + connect \Y $eq$libresoc.v:127865$5536_Y end - attribute \src "libresoc.v:33625.3-33676.6" - process $proc$libresoc.v:33625$725 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_in1_sel[2:0] $1\dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:33626.5-33626.29" - switch \initial - attribute \src "libresoc.v:33626.9-33626.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 - case - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub26_in1_sel $0\dec31_dec_sub26_in1_sel[2:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" + cell $eq $eq$libresoc.v:127868$5540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fsm_state$503 + connect \B 1'1 + connect \Y $eq$libresoc.v:127868$5540_Y end - attribute \src "libresoc.v:33677.3-33728.6" - process $proc$libresoc.v:33677$726 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_in2_sel[3:0] $1\dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:33678.5-33678.29" - switch \initial - attribute \src "libresoc.v:33678.9-33678.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'1010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'1010 - case - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub26_in2_sel $0\dec31_dec_sub26_in2_sel[3:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" + cell $eq $eq$libresoc.v:127869$5541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \fsm_state$503 + connect \B 2'10 + connect \Y $eq$libresoc.v:127869$5541_Y end - attribute \src "libresoc.v:33729.3-33780.6" - process $proc$libresoc.v:33729$727 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_in3_sel[1:0] $1\dec31_dec_sub26_in3_sel[1:0] - attribute \src "libresoc.v:33730.5-33730.29" - switch \initial - attribute \src "libresoc.v:33730.9-33730.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub26_in3_sel $0\dec31_dec_sub26_in3_sel[1:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" + cell $eq $eq$libresoc.v:127871$5543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \fsm_state$503 + connect \B 2'10 + connect \Y $eq$libresoc.v:127871$5543_Y end - attribute \src "libresoc.v:33781.3-33832.6" - process $proc$libresoc.v:33781$728 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_out_sel[1:0] $1\dec31_dec_sub26_out_sel[1:0] - attribute \src "libresoc.v:33782.5-33782.29" - switch \initial - attribute \src "libresoc.v:33782.9-33782.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub26_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub26_out_sel $0\dec31_dec_sub26_out_sel[1:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + cell $pos $extend$libresoc.v:127867$5538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \dmi0__addr_i + connect \Y $extend$libresoc.v:127867$5538_Y end - attribute \src "libresoc.v:33833.3-33884.6" - process $proc$libresoc.v:33833$729 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_cr_in[2:0] $1\dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:33834.5-33834.29" - switch \initial - attribute \src "libresoc.v:33834.9-33834.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub26_cr_in $0\dec31_dec_sub26_cr_in[2:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $ne $ne$libresoc.v:127796$5467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr0_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:127796$5467_Y end - attribute \src "libresoc.v:33885.3-33936.6" - process $proc$libresoc.v:33885$730 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_cr_out[2:0] $1\dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:33886.5-33886.29" - switch \initial - attribute \src "libresoc.v:33886.9-33886.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - case - assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub26_cr_out $0\dec31_dec_sub26_cr_out[2:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $ne $ne$libresoc.v:127798$5469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr0_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:127798$5469_Y end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:33942.1-34657.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub27" -attribute \generator "nMigen" -module \dec31_dec_sub27 - attribute \src "libresoc.v:34295.3-34313.6" - wire width 8 $0\dec31_dec_sub27_asmcode[7:0] - attribute \src "libresoc.v:34371.3-34389.6" - wire $0\dec31_dec_sub27_br[0:0] - attribute \src "libresoc.v:34618.3-34636.6" - wire width 3 $0\dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:34637.3-34655.6" - wire width 3 $0\dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:34276.3-34294.6" - wire width 2 $0\dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:34352.3-34370.6" - wire $0\dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:34523.3-34541.6" - wire width 5 $0\dec31_dec_sub27_form[4:0] - attribute \src "libresoc.v:34200.3-34218.6" - wire width 12 $0\dec31_dec_sub27_function_unit[11:0] - attribute \src "libresoc.v:34542.3-34560.6" - wire width 3 $0\dec31_dec_sub27_in1_sel[2:0] - attribute \src "libresoc.v:34561.3-34579.6" - wire width 4 $0\dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:34580.3-34598.6" - wire width 2 $0\dec31_dec_sub27_in3_sel[1:0] - attribute \src "libresoc.v:34409.3-34427.6" - wire width 7 $0\dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:34314.3-34332.6" - wire $0\dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:34333.3-34351.6" - wire $0\dec31_dec_sub27_inv_out[0:0] - attribute \src "libresoc.v:34447.3-34465.6" - wire $0\dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:34219.3-34237.6" - wire width 4 $0\dec31_dec_sub27_ldst_len[3:0] - attribute \src "libresoc.v:34485.3-34503.6" - wire $0\dec31_dec_sub27_lk[0:0] - attribute \src "libresoc.v:34599.3-34617.6" - wire width 2 $0\dec31_dec_sub27_out_sel[1:0] - attribute \src "libresoc.v:34257.3-34275.6" - wire width 2 $0\dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:34428.3-34446.6" - wire $0\dec31_dec_sub27_rsrv[0:0] - attribute \src "libresoc.v:34504.3-34522.6" - wire $0\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "libresoc.v:34466.3-34484.6" - wire $0\dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:34390.3-34408.6" - wire $0\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "libresoc.v:34238.3-34256.6" - wire width 2 $0\dec31_dec_sub27_upd[1:0] - attribute \src "libresoc.v:33943.7-33943.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:34295.3-34313.6" - wire width 8 $1\dec31_dec_sub27_asmcode[7:0] - attribute \src "libresoc.v:34371.3-34389.6" - wire $1\dec31_dec_sub27_br[0:0] - attribute \src "libresoc.v:34618.3-34636.6" - wire width 3 $1\dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:34637.3-34655.6" - wire width 3 $1\dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:34276.3-34294.6" - wire width 2 $1\dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:34352.3-34370.6" - wire $1\dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:34523.3-34541.6" - wire width 5 $1\dec31_dec_sub27_form[4:0] - attribute \src "libresoc.v:34200.3-34218.6" - wire width 12 $1\dec31_dec_sub27_function_unit[11:0] - attribute \src "libresoc.v:34542.3-34560.6" - wire width 3 $1\dec31_dec_sub27_in1_sel[2:0] - attribute \src "libresoc.v:34561.3-34579.6" - wire width 4 $1\dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:34580.3-34598.6" - wire width 2 $1\dec31_dec_sub27_in3_sel[1:0] - attribute \src "libresoc.v:34409.3-34427.6" - wire width 7 $1\dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:34314.3-34332.6" - wire $1\dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:34333.3-34351.6" - wire $1\dec31_dec_sub27_inv_out[0:0] - attribute \src "libresoc.v:34447.3-34465.6" - wire $1\dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:34219.3-34237.6" - wire width 4 $1\dec31_dec_sub27_ldst_len[3:0] - attribute \src "libresoc.v:34485.3-34503.6" - wire $1\dec31_dec_sub27_lk[0:0] - attribute \src "libresoc.v:34599.3-34617.6" - wire width 2 $1\dec31_dec_sub27_out_sel[1:0] - attribute \src "libresoc.v:34257.3-34275.6" - wire width 2 $1\dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:34428.3-34446.6" - wire $1\dec31_dec_sub27_rsrv[0:0] - attribute \src "libresoc.v:34504.3-34522.6" - wire $1\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "libresoc.v:34466.3-34484.6" - wire $1\dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:34390.3-34408.6" - wire $1\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "libresoc.v:34238.3-34256.6" - wire width 2 $1\dec31_dec_sub27_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub27_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub27_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub27_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub27_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub27_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub27_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub27_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub27_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub27_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub27_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub27_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub27_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub27_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub27_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub27_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub27_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub27_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub27_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub27_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub27_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub27_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub27_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub27_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub27_upd - attribute \src "libresoc.v:33943.7-33943.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:33943.7-33943.20" - process $proc$libresoc.v:33943$756 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $ne $ne$libresoc.v:127801$5472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr0_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:127801$5472_Y end - attribute \src "libresoc.v:34200.3-34218.6" - process $proc$libresoc.v:34200$732 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_function_unit[11:0] $1\dec31_dec_sub27_function_unit[11:0] - attribute \src "libresoc.v:34201.5-34201.29" - switch \initial - attribute \src "libresoc.v:34201.9-34201.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 - case - assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub27_function_unit $0\dec31_dec_sub27_function_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $ne $ne$libresoc.v:127806$5477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_addrsr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:127806$5477_Y end - attribute \src "libresoc.v:34219.3-34237.6" - process $proc$libresoc.v:34219$733 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_ldst_len[3:0] $1\dec31_dec_sub27_ldst_len[3:0] - attribute \src "libresoc.v:34220.5-34220.29" - switch \initial - attribute \src "libresoc.v:34220.9-34220.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub27_ldst_len $0\dec31_dec_sub27_ldst_len[3:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $ne $ne$libresoc.v:127808$5479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_addrsr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:127808$5479_Y end - attribute \src "libresoc.v:34238.3-34256.6" - process $proc$libresoc.v:34238$734 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_upd[1:0] $1\dec31_dec_sub27_upd[1:0] - attribute \src "libresoc.v:34239.5-34239.29" - switch \initial - attribute \src "libresoc.v:34239.9-34239.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub27_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub27_upd $0\dec31_dec_sub27_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $ne $ne$libresoc.v:127812$5483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_addrsr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:127812$5483_Y end - attribute \src "libresoc.v:34257.3-34275.6" - process $proc$libresoc.v:34257$735 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_rc_sel[1:0] $1\dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:34258.5-34258.29" - switch \initial - attribute \src "libresoc.v:34258.9-34258.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub27_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub27_rc_sel $0\dec31_dec_sub27_rc_sel[1:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $ne $ne$libresoc.v:127818$5489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:127818$5489_Y end - attribute \src "libresoc.v:34276.3-34294.6" - process $proc$libresoc.v:34276$736 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_cry_in[1:0] $1\dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:34277.5-34277.29" - switch \initial - attribute \src "libresoc.v:34277.9-34277.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub27_cry_in $0\dec31_dec_sub27_cry_in[1:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $ne $ne$libresoc.v:127820$5491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:127820$5491_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $ne $ne$libresoc.v:127823$5494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:127823$5494_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $ne $ne$libresoc.v:127828$5499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_addrsr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:127828$5499_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $ne $ne$libresoc.v:127830$5501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_addrsr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:127830$5501_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $ne $ne$libresoc.v:127832$5503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_addrsr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:127832$5503_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $ne $ne$libresoc.v:127839$5510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:127839$5510_Y end - attribute \src "libresoc.v:34295.3-34313.6" - process $proc$libresoc.v:34295$737 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_asmcode[7:0] $1\dec31_dec_sub27_asmcode[7:0] - attribute \src "libresoc.v:34296.5-34296.29" - switch \initial - attribute \src "libresoc.v:34296.9-34296.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_asmcode[7:0] 8'01000111 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_asmcode[7:0] 8'10011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_asmcode[7:0] 8'10100001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_asmcode[7:0] 8'10100100 - case - assign $1\dec31_dec_sub27_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub27_asmcode $0\dec31_dec_sub27_asmcode[7:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $ne $ne$libresoc.v:127841$5512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:127841$5512_Y end - attribute \src "libresoc.v:34314.3-34332.6" - process $proc$libresoc.v:34314$738 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_inv_a[0:0] $1\dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:34315.5-34315.29" - switch \initial - attribute \src "libresoc.v:34315.9-34315.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_inv_a $0\dec31_dec_sub27_inv_a[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $ne $ne$libresoc.v:127843$5514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:127843$5514_Y end - attribute \src "libresoc.v:34333.3-34351.6" - process $proc$libresoc.v:34333$739 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_inv_out[0:0] $1\dec31_dec_sub27_inv_out[0:0] - attribute \src "libresoc.v:34334.5-34334.29" - switch \initial - attribute \src "libresoc.v:34334.9-34334.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_inv_out $0\dec31_dec_sub27_inv_out[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $ne $ne$libresoc.v:127849$5520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr5_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:127849$5520_Y end - attribute \src "libresoc.v:34352.3-34370.6" - process $proc$libresoc.v:34352$740 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_cry_out[0:0] $1\dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:34353.5-34353.29" - switch \initial - attribute \src "libresoc.v:34353.9-34353.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_cry_out $0\dec31_dec_sub27_cry_out[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $ne $ne$libresoc.v:127851$5522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr5_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:127851$5522_Y end - attribute \src "libresoc.v:34371.3-34389.6" - process $proc$libresoc.v:34371$741 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_br[0:0] $1\dec31_dec_sub27_br[0:0] - attribute \src "libresoc.v:34372.5-34372.29" - switch \initial - attribute \src "libresoc.v:34372.9-34372.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_br[0:0] 1'0 - case - assign $1\dec31_dec_sub27_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_br $0\dec31_dec_sub27_br[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $ne $ne$libresoc.v:127853$5524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr5_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:127853$5524_Y end - attribute \src "libresoc.v:34390.3-34408.6" - process $proc$libresoc.v:34390$742 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_sgn_ext[0:0] $1\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "libresoc.v:34391.5-34391.29" - switch \initial - attribute \src "libresoc.v:34391.9-34391.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_sgn_ext $0\dec31_dec_sub27_sgn_ext[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:127803$5474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr0_update_core + connect \Y $not$libresoc.v:127803$5474_Y end - attribute \src "libresoc.v:34409.3-34427.6" - process $proc$libresoc.v:34409$743 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_internal_op[6:0] $1\dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:34410.5-34410.29" - switch \initial - attribute \src "libresoc.v:34410.9-34410.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_internal_op[6:0] 7'0100000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 - case - assign $1\dec31_dec_sub27_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub27_internal_op $0\dec31_dec_sub27_internal_op[6:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:127814$5485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_addrsr_update_core + connect \Y $not$libresoc.v:127814$5485_Y end - attribute \src "libresoc.v:34428.3-34446.6" - process $proc$libresoc.v:34428$744 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_rsrv[0:0] $1\dec31_dec_sub27_rsrv[0:0] - attribute \src "libresoc.v:34429.5-34429.29" - switch \initial - attribute \src "libresoc.v:34429.9-34429.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_rsrv $0\dec31_dec_sub27_rsrv[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:127825$5496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_datasr_update_core + connect \Y $not$libresoc.v:127825$5496_Y end - attribute \src "libresoc.v:34447.3-34465.6" - process $proc$libresoc.v:34447$745 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_is_32b[0:0] $1\dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:34448.5-34448.29" - switch \initial - attribute \src "libresoc.v:34448.9-34448.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_is_32b $0\dec31_dec_sub27_is_32b[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:127835$5506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_addrsr_update_core + connect \Y $not$libresoc.v:127835$5506_Y end - attribute \src "libresoc.v:34466.3-34484.6" - process $proc$libresoc.v:34466$746 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_sgn[0:0] $1\dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:34467.5-34467.29" - switch \initial - attribute \src "libresoc.v:34467.9-34467.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub27_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_sgn $0\dec31_dec_sub27_sgn[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:127846$5517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_datasr_update_core + connect \Y $not$libresoc.v:127846$5517_Y end - attribute \src "libresoc.v:34485.3-34503.6" - process $proc$libresoc.v:34485$747 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_lk[0:0] $1\dec31_dec_sub27_lk[0:0] - attribute \src "libresoc.v:34486.5-34486.29" - switch \initial - attribute \src "libresoc.v:34486.9-34486.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub27_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_lk $0\dec31_dec_sub27_lk[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:127856$5527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr5_update_core + connect \Y $not$libresoc.v:127856$5527_Y end - attribute \src "libresoc.v:34504.3-34522.6" - process $proc$libresoc.v:34504$748 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_sgl_pipe[0:0] $1\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "libresoc.v:34505.5-34505.29" - switch \initial - attribute \src "libresoc.v:34505.9-34505.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_sgl_pipe $0\dec31_dec_sub27_sgl_pipe[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" + cell $not $not$libresoc.v:127859$5530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$484 + connect \Y $not$libresoc.v:127859$5530_Y end - attribute \src "libresoc.v:34523.3-34541.6" - process $proc$libresoc.v:34523$749 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_form[4:0] $1\dec31_dec_sub27_form[4:0] - attribute \src "libresoc.v:34524.5-34524.29" - switch \initial - attribute \src "libresoc.v:34524.9-34524.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_form[4:0] 5'10000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_form[4:0] 5'10000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_form[4:0] 5'01000 - case - assign $1\dec31_dec_sub27_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub27_form $0\dec31_dec_sub27_form[4:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $or $or$libresoc.v:127677$5348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$11 + connect \B \$13 + connect \Y $or$libresoc.v:127677$5348_Y end - attribute \src "libresoc.v:34542.3-34560.6" - process $proc$libresoc.v:34542$750 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_in1_sel[2:0] $1\dec31_dec_sub27_in1_sel[2:0] - attribute \src "libresoc.v:34543.5-34543.29" - switch \initial - attribute \src "libresoc.v:34543.9-34543.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 - case - assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub27_in1_sel $0\dec31_dec_sub27_in1_sel[2:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $or $or$libresoc.v:127722$5393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$19 + connect \B \$21 + connect \Y $or$libresoc.v:127722$5393_Y end - attribute \src "libresoc.v:34561.3-34579.6" - process $proc$libresoc.v:34561$751 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_in2_sel[3:0] $1\dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:34562.5-34562.29" - switch \initial - attribute \src "libresoc.v:34562.9-34562.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_in2_sel[3:0] 4'1010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_in2_sel[3:0] 4'1010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub27_in2_sel $0\dec31_dec_sub27_in2_sel[3:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $or $or$libresoc.v:127744$5415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$23 + connect \B \$25 + connect \Y $or$libresoc.v:127744$5415_Y end - attribute \src "libresoc.v:34580.3-34598.6" - process $proc$libresoc.v:34580$752 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_in3_sel[1:0] $1\dec31_dec_sub27_in3_sel[1:0] - attribute \src "libresoc.v:34581.5-34581.29" - switch \initial - attribute \src "libresoc.v:34581.9-34581.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub27_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub27_in3_sel $0\dec31_dec_sub27_in3_sel[1:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $or $or$libresoc.v:127791$5462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$359 + connect \B \$361 + connect \Y $or$libresoc.v:127791$5462_Y end - attribute \src "libresoc.v:34599.3-34617.6" - process $proc$libresoc.v:34599$753 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_out_sel[1:0] $1\dec31_dec_sub27_out_sel[1:0] - attribute \src "libresoc.v:34600.5-34600.29" - switch \initial - attribute \src "libresoc.v:34600.9-34600.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub27_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub27_out_sel $0\dec31_dec_sub27_out_sel[1:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $or $or$libresoc.v:127793$5464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$363 + connect \B \$365 + connect \Y $or$libresoc.v:127793$5464_Y end - attribute \src "libresoc.v:34618.3-34636.6" - process $proc$libresoc.v:34618$754 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_cr_in[2:0] $1\dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:34619.5-34619.29" - switch \initial - attribute \src "libresoc.v:34619.9-34619.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub27_cr_in $0\dec31_dec_sub27_cr_in[2:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $or $or$libresoc.v:127799$5470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$33 + connect \B \$35 + connect \Y $or$libresoc.v:127799$5470_Y end - attribute \src "libresoc.v:34637.3-34655.6" - process $proc$libresoc.v:34637$755 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_cr_out[2:0] $1\dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:34638.5-34638.29" - switch \initial - attribute \src "libresoc.v:34638.9-34638.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 - case - assign $1\dec31_dec_sub27_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub27_cr_out $0\dec31_dec_sub27_cr_out[2:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $or $or$libresoc.v:127822$5493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$37 + connect \B \$39 + connect \Y $or$libresoc.v:127822$5493_Y end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:34661.1-35808.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub28" -attribute \generator "nMigen" -module \dec31_dec_sub28 - attribute \src "libresoc.v:35104.3-35140.6" - wire width 8 $0\dec31_dec_sub28_asmcode[7:0] - attribute \src "libresoc.v:35252.3-35288.6" - wire $0\dec31_dec_sub28_br[0:0] - attribute \src "libresoc.v:35733.3-35769.6" - wire width 3 $0\dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:35770.3-35806.6" - wire width 3 $0\dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:35067.3-35103.6" - wire width 2 $0\dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:35215.3-35251.6" - wire $0\dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:35548.3-35584.6" - wire width 5 $0\dec31_dec_sub28_form[4:0] - attribute \src "libresoc.v:34919.3-34955.6" - wire width 12 $0\dec31_dec_sub28_function_unit[11:0] - attribute \src "libresoc.v:35585.3-35621.6" - wire width 3 $0\dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:35622.3-35658.6" - wire width 4 $0\dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:35659.3-35695.6" - wire width 2 $0\dec31_dec_sub28_in3_sel[1:0] - attribute \src "libresoc.v:35326.3-35362.6" - wire width 7 $0\dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:35141.3-35177.6" - wire $0\dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:35178.3-35214.6" - wire $0\dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:35400.3-35436.6" - wire $0\dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:34956.3-34992.6" - wire width 4 $0\dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:35474.3-35510.6" - wire $0\dec31_dec_sub28_lk[0:0] - attribute \src "libresoc.v:35696.3-35732.6" - wire width 2 $0\dec31_dec_sub28_out_sel[1:0] - attribute \src "libresoc.v:35030.3-35066.6" - wire width 2 $0\dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:35363.3-35399.6" - wire $0\dec31_dec_sub28_rsrv[0:0] - attribute \src "libresoc.v:35511.3-35547.6" - wire $0\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "libresoc.v:35437.3-35473.6" - wire $0\dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:35289.3-35325.6" - wire $0\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "libresoc.v:34993.3-35029.6" - wire width 2 $0\dec31_dec_sub28_upd[1:0] - attribute \src "libresoc.v:34662.7-34662.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:35104.3-35140.6" - wire width 8 $1\dec31_dec_sub28_asmcode[7:0] - attribute \src "libresoc.v:35252.3-35288.6" - wire $1\dec31_dec_sub28_br[0:0] - attribute \src "libresoc.v:35733.3-35769.6" - wire width 3 $1\dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:35770.3-35806.6" - wire width 3 $1\dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:35067.3-35103.6" - wire width 2 $1\dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:35215.3-35251.6" - wire $1\dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:35548.3-35584.6" - wire width 5 $1\dec31_dec_sub28_form[4:0] - attribute \src "libresoc.v:34919.3-34955.6" - wire width 12 $1\dec31_dec_sub28_function_unit[11:0] - attribute \src "libresoc.v:35585.3-35621.6" - wire width 3 $1\dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:35622.3-35658.6" - wire width 4 $1\dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:35659.3-35695.6" - wire width 2 $1\dec31_dec_sub28_in3_sel[1:0] - attribute \src "libresoc.v:35326.3-35362.6" - wire width 7 $1\dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:35141.3-35177.6" - wire $1\dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:35178.3-35214.6" - wire $1\dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:35400.3-35436.6" - wire $1\dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:34956.3-34992.6" - wire width 4 $1\dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:35474.3-35510.6" - wire $1\dec31_dec_sub28_lk[0:0] - attribute \src "libresoc.v:35696.3-35732.6" - wire width 2 $1\dec31_dec_sub28_out_sel[1:0] - attribute \src "libresoc.v:35030.3-35066.6" - wire width 2 $1\dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:35363.3-35399.6" - wire $1\dec31_dec_sub28_rsrv[0:0] - attribute \src "libresoc.v:35511.3-35547.6" - wire $1\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "libresoc.v:35437.3-35473.6" - wire $1\dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:35289.3-35325.6" - wire $1\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "libresoc.v:34993.3-35029.6" - wire width 2 $1\dec31_dec_sub28_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub28_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub28_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub28_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub28_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub28_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub28_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub28_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub28_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub28_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub28_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub28_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub28_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub28_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub28_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub28_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub28_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub28_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub28_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub28_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub28_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub28_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub28_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub28_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub28_upd - attribute \src "libresoc.v:34662.7-34662.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:34662.7-34662.20" - process $proc$libresoc.v:34662$781 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" + cell $or $or$libresoc.v:127862$5533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$487 + connect \B \$489 + connect \Y $or$libresoc.v:127862$5533_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" + cell $or $or$libresoc.v:127870$5542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$504 + connect \B \$506 + connect \Y $or$libresoc.v:127870$5542_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + cell $or $or$libresoc.v:127878$5550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \$3 + connect \Y $or$libresoc.v:127878$5550_Y end - attribute \src "libresoc.v:34919.3-34955.6" - process $proc$libresoc.v:34919$757 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_function_unit[11:0] $1\dec31_dec_sub28_function_unit[11:0] - attribute \src "libresoc.v:34920.5-34920.29" - switch \initial - attribute \src "libresoc.v:34920.9-34920.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - case - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub28_function_unit $0\dec31_dec_sub28_function_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + cell $pos $pos$libresoc.v:127867$5539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:127867$5538_Y + connect \Y $pos$libresoc.v:127867$5539_Y end - attribute \src "libresoc.v:34956.3-34992.6" - process $proc$libresoc.v:34956$758 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_ldst_len[3:0] $1\dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:34957.5-34957.29" - switch \initial - attribute \src "libresoc.v:34957.9-34957.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub28_ldst_len $0\dec31_dec_sub28_ldst_len[3:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127645$5316 + parameter \WIDTH 1 + connect \A \gpio_e15__pad__i + connect \B \io_bd [24] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127645$5316_Y end - attribute \src "libresoc.v:34993.3-35029.6" - process $proc$libresoc.v:34993$759 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_upd[1:0] $1\dec31_dec_sub28_upd[1:0] - attribute \src "libresoc.v:34994.5-34994.29" - switch \initial - attribute \src "libresoc.v:34994.9-34994.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub28_upd $0\dec31_dec_sub28_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127646$5317 + parameter \WIDTH 1 + connect \A \gpio_e15__core__o + connect \B \io_bd [25] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127646$5317_Y end - attribute \src "libresoc.v:35030.3-35066.6" - process $proc$libresoc.v:35030$760 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_rc_sel[1:0] $1\dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:35031.5-35031.29" - switch \initial - attribute \src "libresoc.v:35031.9-35031.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub28_rc_sel $0\dec31_dec_sub28_rc_sel[1:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127647$5318 + parameter \WIDTH 1 + connect \A \gpio_e15__core__oe + connect \B \io_bd [26] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127647$5318_Y end - attribute \src "libresoc.v:35067.3-35103.6" - process $proc$libresoc.v:35067$761 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_cry_in[1:0] $1\dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:35068.5-35068.29" - switch \initial - attribute \src "libresoc.v:35068.9-35068.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub28_cry_in $0\dec31_dec_sub28_cry_in[1:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127648$5319 + parameter \WIDTH 1 + connect \A \gpio_s0__pad__i + connect \B \io_bd [27] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127648$5319_Y end - attribute \src "libresoc.v:35104.3-35140.6" - process $proc$libresoc.v:35104$762 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_asmcode[7:0] $1\dec31_dec_sub28_asmcode[7:0] - attribute \src "libresoc.v:35105.5-35105.29" - switch \initial - attribute \src "libresoc.v:35105.9-35105.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'00001111 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'00010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'00011001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'00011011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'01000011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'10000011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'10000111 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'10001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'10001001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'11010000 - case - assign $1\dec31_dec_sub28_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub28_asmcode $0\dec31_dec_sub28_asmcode[7:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127649$5320 + parameter \WIDTH 1 + connect \A \gpio_s0__core__o + connect \B \io_bd [28] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127649$5320_Y end - attribute \src "libresoc.v:35141.3-35177.6" - process $proc$libresoc.v:35141$763 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_inv_a[0:0] $1\dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:35142.5-35142.29" - switch \initial - attribute \src "libresoc.v:35142.9-35142.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_inv_a $0\dec31_dec_sub28_inv_a[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127650$5321 + parameter \WIDTH 1 + connect \A \gpio_s0__core__oe + connect \B \io_bd [29] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127650$5321_Y end - attribute \src "libresoc.v:35178.3-35214.6" - process $proc$libresoc.v:35178$764 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_inv_out[0:0] $1\dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:35179.5-35179.29" - switch \initial - attribute \src "libresoc.v:35179.9-35179.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_inv_out $0\dec31_dec_sub28_inv_out[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127651$5322 + parameter \WIDTH 1 + connect \A \gpio_s1__pad__i + connect \B \io_bd [30] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127651$5322_Y end - attribute \src "libresoc.v:35215.3-35251.6" - process $proc$libresoc.v:35215$765 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_cry_out[0:0] $1\dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:35216.5-35216.29" - switch \initial - attribute \src "libresoc.v:35216.9-35216.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_cry_out $0\dec31_dec_sub28_cry_out[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127652$5323 + parameter \WIDTH 1 + connect \A \gpio_s1__core__o + connect \B \io_bd [31] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127652$5323_Y end - attribute \src "libresoc.v:35252.3-35288.6" - process $proc$libresoc.v:35252$766 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_br[0:0] $1\dec31_dec_sub28_br[0:0] - attribute \src "libresoc.v:35253.5-35253.29" - switch \initial - attribute \src "libresoc.v:35253.9-35253.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - case - assign $1\dec31_dec_sub28_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_br $0\dec31_dec_sub28_br[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127653$5324 + parameter \WIDTH 1 + connect \A \gpio_s1__core__oe + connect \B \io_bd [32] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127653$5324_Y end - attribute \src "libresoc.v:35289.3-35325.6" - process $proc$libresoc.v:35289$767 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_sgn_ext[0:0] $1\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "libresoc.v:35290.5-35290.29" - switch \initial - attribute \src "libresoc.v:35290.9-35290.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_sgn_ext $0\dec31_dec_sub28_sgn_ext[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127654$5325 + parameter \WIDTH 1 + connect \A \gpio_s2__pad__i + connect \B \io_bd [33] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127654$5325_Y end - attribute \src "libresoc.v:35326.3-35362.6" - process $proc$libresoc.v:35326$768 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_internal_op[6:0] $1\dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:35327.5-35327.29" - switch \initial - attribute \src "libresoc.v:35327.9-35327.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 - case - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub28_internal_op $0\dec31_dec_sub28_internal_op[6:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127656$5327 + parameter \WIDTH 1 + connect \A \gpio_s2__core__o + connect \B \io_bd [34] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127656$5327_Y end - attribute \src "libresoc.v:35363.3-35399.6" - process $proc$libresoc.v:35363$769 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_rsrv[0:0] $1\dec31_dec_sub28_rsrv[0:0] - attribute \src "libresoc.v:35364.5-35364.29" - switch \initial - attribute \src "libresoc.v:35364.9-35364.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_rsrv $0\dec31_dec_sub28_rsrv[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127657$5328 + parameter \WIDTH 1 + connect \A \gpio_s2__core__oe + connect \B \io_bd [35] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127657$5328_Y end - attribute \src "libresoc.v:35400.3-35436.6" - process $proc$libresoc.v:35400$770 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_is_32b[0:0] $1\dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:35401.5-35401.29" - switch \initial - attribute \src "libresoc.v:35401.9-35401.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_is_32b $0\dec31_dec_sub28_is_32b[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127658$5329 + parameter \WIDTH 1 + connect \A \gpio_s3__pad__i + connect \B \io_bd [36] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127658$5329_Y end - attribute \src "libresoc.v:35437.3-35473.6" - process $proc$libresoc.v:35437$771 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_sgn[0:0] $1\dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:35438.5-35438.29" - switch \initial - attribute \src "libresoc.v:35438.9-35438.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_sgn $0\dec31_dec_sub28_sgn[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127659$5330 + parameter \WIDTH 1 + connect \A \gpio_s3__core__o + connect \B \io_bd [37] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127659$5330_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127660$5331 + parameter \WIDTH 1 + connect \A \gpio_s3__core__oe + connect \B \io_bd [38] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127660$5331_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127661$5332 + parameter \WIDTH 1 + connect \A \gpio_s4__pad__i + connect \B \io_bd [39] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127661$5332_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127662$5333 + parameter \WIDTH 1 + connect \A \gpio_s4__core__o + connect \B \io_bd [40] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127662$5333_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127663$5334 + parameter \WIDTH 1 + connect \A \gpio_s4__core__oe + connect \B \io_bd [41] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127663$5334_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127664$5335 + parameter \WIDTH 1 + connect \A \gpio_s5__pad__i + connect \B \io_bd [42] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127664$5335_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127665$5336 + parameter \WIDTH 1 + connect \A \gpio_s5__core__o + connect \B \io_bd [43] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127665$5336_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127667$5338 + parameter \WIDTH 1 + connect \A \gpio_s5__core__oe + connect \B \io_bd [44] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127667$5338_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127668$5339 + parameter \WIDTH 1 + connect \A \gpio_s6__pad__i + connect \B \io_bd [45] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127668$5339_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127669$5340 + parameter \WIDTH 1 + connect \A \gpio_s6__core__o + connect \B \io_bd [46] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127669$5340_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127670$5341 + parameter \WIDTH 1 + connect \A \gpio_s6__core__oe + connect \B \io_bd [47] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127670$5341_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127671$5342 + parameter \WIDTH 1 + connect \A \gpio_s7__pad__i + connect \B \io_bd [48] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127671$5342_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127672$5343 + parameter \WIDTH 1 + connect \A \gpio_s7__core__o + connect \B \io_bd [49] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127672$5343_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127673$5344 + parameter \WIDTH 1 + connect \A \gpio_s7__core__oe + connect \B \io_bd [50] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127673$5344_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127674$5345 + parameter \WIDTH 1 + connect \A \mspi0_clk__core__o + connect \B \io_bd [51] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127674$5345_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127675$5346 + parameter \WIDTH 1 + connect \A \mspi0_cs_n__core__o + connect \B \io_bd [52] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127675$5346_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127676$5347 + parameter \WIDTH 1 + connect \A \mspi0_mosi__core__o + connect \B \io_bd [53] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127676$5347_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + cell $mux $ternary$libresoc.v:127678$5349 + parameter \WIDTH 1 + connect \A \mspi0_miso__pad__i + connect \B \io_bd [54] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127678$5349_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127679$5350 + parameter \WIDTH 1 + connect \A \mspi1_clk__core__o + connect \B \io_bd [55] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127679$5350_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127680$5351 + parameter \WIDTH 1 + connect \A \mspi1_cs_n__core__o + connect \B \io_bd [56] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127680$5351_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127681$5352 + parameter \WIDTH 1 + connect \A \mspi1_mosi__core__o + connect \B \io_bd [57] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127681$5352_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + cell $mux $ternary$libresoc.v:127682$5353 + parameter \WIDTH 1 + connect \A \mspi1_miso__pad__i + connect \B \io_bd [58] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127682$5353_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127683$5354 + parameter \WIDTH 1 + connect \A \mtwi_sda__pad__i + connect \B \io_bd [59] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127683$5354_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127684$5355 + parameter \WIDTH 1 + connect \A \mtwi_sda__core__o + connect \B \io_bd [60] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127684$5355_Y end - attribute \src "libresoc.v:35474.3-35510.6" - process $proc$libresoc.v:35474$772 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_lk[0:0] $1\dec31_dec_sub28_lk[0:0] - attribute \src "libresoc.v:35475.5-35475.29" - switch \initial - attribute \src "libresoc.v:35475.9-35475.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_lk $0\dec31_dec_sub28_lk[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127685$5356 + parameter \WIDTH 1 + connect \A \mtwi_sda__core__oe + connect \B \io_bd [61] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127685$5356_Y end - attribute \src "libresoc.v:35511.3-35547.6" - process $proc$libresoc.v:35511$773 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_sgl_pipe[0:0] $1\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "libresoc.v:35512.5-35512.29" - switch \initial - attribute \src "libresoc.v:35512.9-35512.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_sgl_pipe $0\dec31_dec_sub28_sgl_pipe[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127686$5357 + parameter \WIDTH 1 + connect \A \mtwi_scl__core__o + connect \B \io_bd [62] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127686$5357_Y end - attribute \src "libresoc.v:35548.3-35584.6" - process $proc$libresoc.v:35548$774 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_form[4:0] $1\dec31_dec_sub28_form[4:0] - attribute \src "libresoc.v:35549.5-35549.29" - switch \initial - attribute \src "libresoc.v:35549.9-35549.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - case - assign $1\dec31_dec_sub28_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub28_form $0\dec31_dec_sub28_form[4:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127687$5358 + parameter \WIDTH 1 + connect \A \pwm_0__core__o + connect \B \io_bd [63] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127687$5358_Y end - attribute \src "libresoc.v:35585.3-35621.6" - process $proc$libresoc.v:35585$775 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_in1_sel[2:0] $1\dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:35586.5-35586.29" - switch \initial - attribute \src "libresoc.v:35586.9-35586.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - case - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub28_in1_sel $0\dec31_dec_sub28_in1_sel[2:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127689$5360 + parameter \WIDTH 1 + connect \A \pwm_1__core__o + connect \B \io_bd [64] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127689$5360_Y end - attribute \src "libresoc.v:35622.3-35658.6" - process $proc$libresoc.v:35622$776 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_in2_sel[3:0] $1\dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:35623.5-35623.29" - switch \initial - attribute \src "libresoc.v:35623.9-35623.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub28_in2_sel $0\dec31_dec_sub28_in2_sel[3:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127690$5361 + parameter \WIDTH 1 + connect \A \sd0_cmd__pad__i + connect \B \io_bd [65] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127690$5361_Y end - attribute \src "libresoc.v:35659.3-35695.6" - process $proc$libresoc.v:35659$777 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_in3_sel[1:0] $1\dec31_dec_sub28_in3_sel[1:0] - attribute \src "libresoc.v:35660.5-35660.29" - switch \initial - attribute \src "libresoc.v:35660.9-35660.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub28_in3_sel $0\dec31_dec_sub28_in3_sel[1:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127691$5362 + parameter \WIDTH 1 + connect \A \sd0_cmd__core__o + connect \B \io_bd [66] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127691$5362_Y end - attribute \src "libresoc.v:35696.3-35732.6" - process $proc$libresoc.v:35696$778 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_out_sel[1:0] $1\dec31_dec_sub28_out_sel[1:0] - attribute \src "libresoc.v:35697.5-35697.29" - switch \initial - attribute \src "libresoc.v:35697.9-35697.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub28_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub28_out_sel $0\dec31_dec_sub28_out_sel[1:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127692$5363 + parameter \WIDTH 1 + connect \A \sd0_cmd__core__oe + connect \B \io_bd [67] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127692$5363_Y end - attribute \src "libresoc.v:35733.3-35769.6" - process $proc$libresoc.v:35733$779 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_cr_in[2:0] $1\dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:35734.5-35734.29" - switch \initial - attribute \src "libresoc.v:35734.9-35734.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub28_cr_in $0\dec31_dec_sub28_cr_in[2:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127693$5364 + parameter \WIDTH 1 + connect \A \sd0_clk__core__o + connect \B \io_bd [68] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127693$5364_Y end - attribute \src "libresoc.v:35770.3-35806.6" - process $proc$libresoc.v:35770$780 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_cr_out[2:0] $1\dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:35771.5-35771.29" - switch \initial - attribute \src "libresoc.v:35771.9-35771.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 - case - assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub28_cr_out $0\dec31_dec_sub28_cr_out[2:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127694$5365 + parameter \WIDTH 1 + connect \A \sd0_data0__pad__i + connect \B \io_bd [69] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127694$5365_Y end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:35812.1-36383.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub4" -attribute \generator "nMigen" -module \dec31_dec_sub4 - attribute \src "libresoc.v:36135.3-36147.6" - wire width 8 $0\dec31_dec_sub4_asmcode[7:0] - attribute \src "libresoc.v:36187.3-36199.6" - wire $0\dec31_dec_sub4_br[0:0] - attribute \src "libresoc.v:36356.3-36368.6" - wire width 3 $0\dec31_dec_sub4_cr_in[2:0] - attribute \src "libresoc.v:36369.3-36381.6" - wire width 3 $0\dec31_dec_sub4_cr_out[2:0] - attribute \src "libresoc.v:36122.3-36134.6" - wire width 2 $0\dec31_dec_sub4_cry_in[1:0] - attribute \src "libresoc.v:36174.3-36186.6" - wire $0\dec31_dec_sub4_cry_out[0:0] - attribute \src "libresoc.v:36291.3-36303.6" - wire width 5 $0\dec31_dec_sub4_form[4:0] - attribute \src "libresoc.v:36070.3-36082.6" - wire width 12 $0\dec31_dec_sub4_function_unit[11:0] - attribute \src "libresoc.v:36304.3-36316.6" - wire width 3 $0\dec31_dec_sub4_in1_sel[2:0] - attribute \src "libresoc.v:36317.3-36329.6" - wire width 4 $0\dec31_dec_sub4_in2_sel[3:0] - attribute \src "libresoc.v:36330.3-36342.6" - wire width 2 $0\dec31_dec_sub4_in3_sel[1:0] - attribute \src "libresoc.v:36213.3-36225.6" - wire width 7 $0\dec31_dec_sub4_internal_op[6:0] - attribute \src "libresoc.v:36148.3-36160.6" - wire $0\dec31_dec_sub4_inv_a[0:0] - attribute \src "libresoc.v:36161.3-36173.6" - wire $0\dec31_dec_sub4_inv_out[0:0] - attribute \src "libresoc.v:36239.3-36251.6" - wire $0\dec31_dec_sub4_is_32b[0:0] - attribute \src "libresoc.v:36083.3-36095.6" - wire width 4 $0\dec31_dec_sub4_ldst_len[3:0] - attribute \src "libresoc.v:36265.3-36277.6" - wire $0\dec31_dec_sub4_lk[0:0] - attribute \src "libresoc.v:36343.3-36355.6" - wire width 2 $0\dec31_dec_sub4_out_sel[1:0] - attribute \src "libresoc.v:36109.3-36121.6" - wire width 2 $0\dec31_dec_sub4_rc_sel[1:0] - attribute \src "libresoc.v:36226.3-36238.6" - wire $0\dec31_dec_sub4_rsrv[0:0] - attribute \src "libresoc.v:36278.3-36290.6" - wire $0\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "libresoc.v:36252.3-36264.6" - wire $0\dec31_dec_sub4_sgn[0:0] - attribute \src "libresoc.v:36200.3-36212.6" - wire $0\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "libresoc.v:36096.3-36108.6" - wire width 2 $0\dec31_dec_sub4_upd[1:0] - attribute \src "libresoc.v:35813.7-35813.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:36135.3-36147.6" - wire width 8 $1\dec31_dec_sub4_asmcode[7:0] - attribute \src "libresoc.v:36187.3-36199.6" - wire $1\dec31_dec_sub4_br[0:0] - attribute \src "libresoc.v:36356.3-36368.6" - wire width 3 $1\dec31_dec_sub4_cr_in[2:0] - attribute \src "libresoc.v:36369.3-36381.6" - wire width 3 $1\dec31_dec_sub4_cr_out[2:0] - attribute \src "libresoc.v:36122.3-36134.6" - wire width 2 $1\dec31_dec_sub4_cry_in[1:0] - attribute \src "libresoc.v:36174.3-36186.6" - wire $1\dec31_dec_sub4_cry_out[0:0] - attribute \src "libresoc.v:36291.3-36303.6" - wire width 5 $1\dec31_dec_sub4_form[4:0] - attribute \src "libresoc.v:36070.3-36082.6" - wire width 12 $1\dec31_dec_sub4_function_unit[11:0] - attribute \src "libresoc.v:36304.3-36316.6" - wire width 3 $1\dec31_dec_sub4_in1_sel[2:0] - attribute \src "libresoc.v:36317.3-36329.6" - wire width 4 $1\dec31_dec_sub4_in2_sel[3:0] - attribute \src "libresoc.v:36330.3-36342.6" - wire width 2 $1\dec31_dec_sub4_in3_sel[1:0] - attribute \src "libresoc.v:36213.3-36225.6" - wire width 7 $1\dec31_dec_sub4_internal_op[6:0] - attribute \src "libresoc.v:36148.3-36160.6" - wire $1\dec31_dec_sub4_inv_a[0:0] - attribute \src "libresoc.v:36161.3-36173.6" - wire $1\dec31_dec_sub4_inv_out[0:0] - attribute \src "libresoc.v:36239.3-36251.6" - wire $1\dec31_dec_sub4_is_32b[0:0] - attribute \src "libresoc.v:36083.3-36095.6" - wire width 4 $1\dec31_dec_sub4_ldst_len[3:0] - attribute \src "libresoc.v:36265.3-36277.6" - wire $1\dec31_dec_sub4_lk[0:0] - attribute \src "libresoc.v:36343.3-36355.6" - wire width 2 $1\dec31_dec_sub4_out_sel[1:0] - attribute \src "libresoc.v:36109.3-36121.6" - wire width 2 $1\dec31_dec_sub4_rc_sel[1:0] - attribute \src "libresoc.v:36226.3-36238.6" - wire $1\dec31_dec_sub4_rsrv[0:0] - attribute \src "libresoc.v:36278.3-36290.6" - wire $1\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "libresoc.v:36252.3-36264.6" - wire $1\dec31_dec_sub4_sgn[0:0] - attribute \src "libresoc.v:36200.3-36212.6" - wire $1\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "libresoc.v:36096.3-36108.6" - wire width 2 $1\dec31_dec_sub4_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub4_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub4_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub4_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub4_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub4_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub4_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub4_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub4_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub4_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub4_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub4_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub4_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub4_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub4_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub4_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub4_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub4_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub4_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub4_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub4_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub4_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub4_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub4_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub4_upd - attribute \src "libresoc.v:35813.7-35813.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:35813.7-35813.20" - process $proc$libresoc.v:35813$806 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127695$5366 + parameter \WIDTH 1 + connect \A \sd0_data0__core__o + connect \B \io_bd [70] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127695$5366_Y end - attribute \src "libresoc.v:36070.3-36082.6" - process $proc$libresoc.v:36070$782 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_function_unit[11:0] $1\dec31_dec_sub4_function_unit[11:0] - attribute \src "libresoc.v:36071.5-36071.29" - switch \initial - attribute \src "libresoc.v:36071.9-36071.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_function_unit[11:0] 12'000010000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_function_unit[11:0] 12'000010000000 - case - assign $1\dec31_dec_sub4_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub4_function_unit $0\dec31_dec_sub4_function_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127696$5367 + parameter \WIDTH 1 + connect \A \sd0_data0__core__oe + connect \B \io_bd [71] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127696$5367_Y end - attribute \src "libresoc.v:36083.3-36095.6" - process $proc$libresoc.v:36083$783 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_ldst_len[3:0] $1\dec31_dec_sub4_ldst_len[3:0] - attribute \src "libresoc.v:36084.5-36084.29" - switch \initial - attribute \src "libresoc.v:36084.9-36084.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub4_ldst_len $0\dec31_dec_sub4_ldst_len[3:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127697$5368 + parameter \WIDTH 1 + connect \A \sd0_data1__pad__i + connect \B \io_bd [72] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127697$5368_Y end - attribute \src "libresoc.v:36096.3-36108.6" - process $proc$libresoc.v:36096$784 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_upd[1:0] $1\dec31_dec_sub4_upd[1:0] - attribute \src "libresoc.v:36097.5-36097.29" - switch \initial - attribute \src "libresoc.v:36097.9-36097.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub4_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub4_upd $0\dec31_dec_sub4_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127698$5369 + parameter \WIDTH 1 + connect \A \sd0_data1__core__o + connect \B \io_bd [73] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127698$5369_Y end - attribute \src "libresoc.v:36109.3-36121.6" - process $proc$libresoc.v:36109$785 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_rc_sel[1:0] $1\dec31_dec_sub4_rc_sel[1:0] - attribute \src "libresoc.v:36110.5-36110.29" - switch \initial - attribute \src "libresoc.v:36110.9-36110.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub4_rc_sel $0\dec31_dec_sub4_rc_sel[1:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127701$5372 + parameter \WIDTH 1 + connect \A \sd0_data1__core__oe + connect \B \io_bd [74] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127701$5372_Y end - attribute \src "libresoc.v:36122.3-36134.6" - process $proc$libresoc.v:36122$786 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_cry_in[1:0] $1\dec31_dec_sub4_cry_in[1:0] - attribute \src "libresoc.v:36123.5-36123.29" - switch \initial - attribute \src "libresoc.v:36123.9-36123.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub4_cry_in $0\dec31_dec_sub4_cry_in[1:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127702$5373 + parameter \WIDTH 1 + connect \A \sd0_data2__pad__i + connect \B \io_bd [75] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127702$5373_Y end - attribute \src "libresoc.v:36135.3-36147.6" - process $proc$libresoc.v:36135$787 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_asmcode[7:0] $1\dec31_dec_sub4_asmcode[7:0] - attribute \src "libresoc.v:36136.5-36136.29" - switch \initial - attribute \src "libresoc.v:36136.9-36136.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_asmcode[7:0] 8'11001010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_asmcode[7:0] 8'11001110 - case - assign $1\dec31_dec_sub4_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub4_asmcode $0\dec31_dec_sub4_asmcode[7:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127703$5374 + parameter \WIDTH 1 + connect \A \sd0_data2__core__o + connect \B \io_bd [76] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127703$5374_Y end - attribute \src "libresoc.v:36148.3-36160.6" - process $proc$libresoc.v:36148$788 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_inv_a[0:0] $1\dec31_dec_sub4_inv_a[0:0] - attribute \src "libresoc.v:36149.5-36149.29" - switch \initial - attribute \src "libresoc.v:36149.9-36149.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_inv_a $0\dec31_dec_sub4_inv_a[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127704$5375 + parameter \WIDTH 1 + connect \A \sd0_data2__core__oe + connect \B \io_bd [77] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127704$5375_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127705$5376 + parameter \WIDTH 1 + connect \A \sd0_data3__pad__i + connect \B \io_bd [78] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127705$5376_Y end - attribute \src "libresoc.v:36161.3-36173.6" - process $proc$libresoc.v:36161$789 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_inv_out[0:0] $1\dec31_dec_sub4_inv_out[0:0] - attribute \src "libresoc.v:36162.5-36162.29" - switch \initial - attribute \src "libresoc.v:36162.9-36162.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_inv_out $0\dec31_dec_sub4_inv_out[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127706$5377 + parameter \WIDTH 1 + connect \A \sd0_data3__core__o + connect \B \io_bd [79] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127706$5377_Y end - attribute \src "libresoc.v:36174.3-36186.6" - process $proc$libresoc.v:36174$790 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_cry_out[0:0] $1\dec31_dec_sub4_cry_out[0:0] - attribute \src "libresoc.v:36175.5-36175.29" - switch \initial - attribute \src "libresoc.v:36175.9-36175.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_cry_out $0\dec31_dec_sub4_cry_out[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127707$5378 + parameter \WIDTH 1 + connect \A \sd0_data3__core__oe + connect \B \io_bd [80] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127707$5378_Y end - attribute \src "libresoc.v:36187.3-36199.6" - process $proc$libresoc.v:36187$791 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_br[0:0] $1\dec31_dec_sub4_br[0:0] - attribute \src "libresoc.v:36188.5-36188.29" - switch \initial - attribute \src "libresoc.v:36188.9-36188.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_br[0:0] 1'0 - case - assign $1\dec31_dec_sub4_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_br $0\dec31_dec_sub4_br[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127708$5379 + parameter \WIDTH 1 + connect \A \sdr_dm_0__core__o + connect \B \io_bd [81] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127708$5379_Y end - attribute \src "libresoc.v:36200.3-36212.6" - process $proc$libresoc.v:36200$792 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_sgn_ext[0:0] $1\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "libresoc.v:36201.5-36201.29" - switch \initial - attribute \src "libresoc.v:36201.9-36201.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_sgn_ext $0\dec31_dec_sub4_sgn_ext[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127709$5380 + parameter \WIDTH 1 + connect \A \sdr_dq_0__pad__i + connect \B \io_bd [82] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127709$5380_Y end - attribute \src "libresoc.v:36213.3-36225.6" - process $proc$libresoc.v:36213$793 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_internal_op[6:0] $1\dec31_dec_sub4_internal_op[6:0] - attribute \src "libresoc.v:36214.5-36214.29" - switch \initial - attribute \src "libresoc.v:36214.9-36214.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 - case - assign $1\dec31_dec_sub4_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub4_internal_op $0\dec31_dec_sub4_internal_op[6:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127710$5381 + parameter \WIDTH 1 + connect \A \sdr_dq_0__core__o + connect \B \io_bd [83] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127710$5381_Y end - attribute \src "libresoc.v:36226.3-36238.6" - process $proc$libresoc.v:36226$794 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_rsrv[0:0] $1\dec31_dec_sub4_rsrv[0:0] - attribute \src "libresoc.v:36227.5-36227.29" - switch \initial - attribute \src "libresoc.v:36227.9-36227.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_rsrv $0\dec31_dec_sub4_rsrv[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127712$5383 + parameter \WIDTH 1 + connect \A \sdr_dq_0__core__oe + connect \B \io_bd [84] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127712$5383_Y end - attribute \src "libresoc.v:36239.3-36251.6" - process $proc$libresoc.v:36239$795 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_is_32b[0:0] $1\dec31_dec_sub4_is_32b[0:0] - attribute \src "libresoc.v:36240.5-36240.29" - switch \initial - attribute \src "libresoc.v:36240.9-36240.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_is_32b[0:0] 1'1 - case - assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_is_32b $0\dec31_dec_sub4_is_32b[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127713$5384 + parameter \WIDTH 1 + connect \A \sdr_dq_1__pad__i + connect \B \io_bd [85] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127713$5384_Y end - attribute \src "libresoc.v:36252.3-36264.6" - process $proc$libresoc.v:36252$796 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_sgn[0:0] $1\dec31_dec_sub4_sgn[0:0] - attribute \src "libresoc.v:36253.5-36253.29" - switch \initial - attribute \src "libresoc.v:36253.9-36253.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub4_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_sgn $0\dec31_dec_sub4_sgn[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127714$5385 + parameter \WIDTH 1 + connect \A \sdr_dq_1__core__o + connect \B \io_bd [86] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127714$5385_Y end - attribute \src "libresoc.v:36265.3-36277.6" - process $proc$libresoc.v:36265$797 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_lk[0:0] $1\dec31_dec_sub4_lk[0:0] - attribute \src "libresoc.v:36266.5-36266.29" - switch \initial - attribute \src "libresoc.v:36266.9-36266.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub4_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_lk $0\dec31_dec_sub4_lk[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127715$5386 + parameter \WIDTH 1 + connect \A \sdr_dq_1__core__oe + connect \B \io_bd [87] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127715$5386_Y end - attribute \src "libresoc.v:36278.3-36290.6" - process $proc$libresoc.v:36278$798 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_sgl_pipe[0:0] $1\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "libresoc.v:36279.5-36279.29" - switch \initial - attribute \src "libresoc.v:36279.9-36279.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'1 - case - assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_sgl_pipe $0\dec31_dec_sub4_sgl_pipe[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127716$5387 + parameter \WIDTH 1 + connect \A \sdr_dq_2__pad__i + connect \B \io_bd [88] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127716$5387_Y end - attribute \src "libresoc.v:36291.3-36303.6" - process $proc$libresoc.v:36291$799 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_form[4:0] $1\dec31_dec_sub4_form[4:0] - attribute \src "libresoc.v:36292.5-36292.29" - switch \initial - attribute \src "libresoc.v:36292.9-36292.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_form[4:0] 5'01000 - case - assign $1\dec31_dec_sub4_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub4_form $0\dec31_dec_sub4_form[4:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127717$5388 + parameter \WIDTH 1 + connect \A \sdr_dq_2__core__o + connect \B \io_bd [89] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127717$5388_Y end - attribute \src "libresoc.v:36304.3-36316.6" - process $proc$libresoc.v:36304$800 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_in1_sel[2:0] $1\dec31_dec_sub4_in1_sel[2:0] - attribute \src "libresoc.v:36305.5-36305.29" - switch \initial - attribute \src "libresoc.v:36305.9-36305.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_in1_sel[2:0] 3'001 - case - assign $1\dec31_dec_sub4_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub4_in1_sel $0\dec31_dec_sub4_in1_sel[2:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127718$5389 + parameter \WIDTH 1 + connect \A \sdr_dq_2__core__oe + connect \B \io_bd [90] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127718$5389_Y end - attribute \src "libresoc.v:36317.3-36329.6" - process $proc$libresoc.v:36317$801 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_in2_sel[3:0] $1\dec31_dec_sub4_in2_sel[3:0] - attribute \src "libresoc.v:36318.5-36318.29" - switch \initial - attribute \src "libresoc.v:36318.9-36318.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub4_in2_sel $0\dec31_dec_sub4_in2_sel[3:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127719$5390 + parameter \WIDTH 1 + connect \A \sdr_dq_3__pad__i + connect \B \io_bd [91] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127719$5390_Y end - attribute \src "libresoc.v:36330.3-36342.6" - process $proc$libresoc.v:36330$802 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_in3_sel[1:0] $1\dec31_dec_sub4_in3_sel[1:0] - attribute \src "libresoc.v:36331.5-36331.29" - switch \initial - attribute \src "libresoc.v:36331.9-36331.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub4_in3_sel $0\dec31_dec_sub4_in3_sel[1:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127720$5391 + parameter \WIDTH 1 + connect \A \sdr_dq_3__core__o + connect \B \io_bd [92] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127720$5391_Y end - attribute \src "libresoc.v:36343.3-36355.6" - process $proc$libresoc.v:36343$803 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_out_sel[1:0] $1\dec31_dec_sub4_out_sel[1:0] - attribute \src "libresoc.v:36344.5-36344.29" - switch \initial - attribute \src "libresoc.v:36344.9-36344.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub4_out_sel $0\dec31_dec_sub4_out_sel[1:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127721$5392 + parameter \WIDTH 1 + connect \A \sdr_dq_3__core__oe + connect \B \io_bd [93] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127721$5392_Y end - attribute \src "libresoc.v:36356.3-36368.6" - process $proc$libresoc.v:36356$804 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_cr_in[2:0] $1\dec31_dec_sub4_cr_in[2:0] - attribute \src "libresoc.v:36357.5-36357.29" - switch \initial - attribute \src "libresoc.v:36357.9-36357.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub4_cr_in $0\dec31_dec_sub4_cr_in[2:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127723$5394 + parameter \WIDTH 1 + connect \A \sdr_dq_4__pad__i + connect \B \io_bd [94] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127723$5394_Y end - attribute \src "libresoc.v:36369.3-36381.6" - process $proc$libresoc.v:36369$805 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_cr_out[2:0] $1\dec31_dec_sub4_cr_out[2:0] - attribute \src "libresoc.v:36370.5-36370.29" - switch \initial - attribute \src "libresoc.v:36370.9-36370.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 - case - assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub4_cr_out $0\dec31_dec_sub4_cr_out[2:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127724$5395 + parameter \WIDTH 1 + connect \A \sdr_dq_4__core__o + connect \B \io_bd [95] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127724$5395_Y end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:36387.1-37678.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub8" -attribute \generator "nMigen" -module \dec31_dec_sub8 - attribute \src "libresoc.v:36860.3-36902.6" - wire width 8 $0\dec31_dec_sub8_asmcode[7:0] - attribute \src "libresoc.v:37032.3-37074.6" - wire $0\dec31_dec_sub8_br[0:0] - attribute \src "libresoc.v:37591.3-37633.6" - wire width 3 $0\dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:37634.3-37676.6" - wire width 3 $0\dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:36817.3-36859.6" - wire width 2 $0\dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:36989.3-37031.6" - wire $0\dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:37376.3-37418.6" - wire width 5 $0\dec31_dec_sub8_form[4:0] - attribute \src "libresoc.v:36645.3-36687.6" - wire width 12 $0\dec31_dec_sub8_function_unit[11:0] - attribute \src "libresoc.v:37419.3-37461.6" - wire width 3 $0\dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:37462.3-37504.6" - wire width 4 $0\dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:37505.3-37547.6" - wire width 2 $0\dec31_dec_sub8_in3_sel[1:0] - attribute \src "libresoc.v:37118.3-37160.6" - wire width 7 $0\dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:36903.3-36945.6" - wire $0\dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:36946.3-36988.6" - wire $0\dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:37204.3-37246.6" - wire $0\dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:36688.3-36730.6" - wire width 4 $0\dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:37290.3-37332.6" - wire $0\dec31_dec_sub8_lk[0:0] - attribute \src "libresoc.v:37548.3-37590.6" - wire width 2 $0\dec31_dec_sub8_out_sel[1:0] - attribute \src "libresoc.v:36774.3-36816.6" - wire width 2 $0\dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:37161.3-37203.6" - wire $0\dec31_dec_sub8_rsrv[0:0] - attribute \src "libresoc.v:37333.3-37375.6" - wire $0\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "libresoc.v:37247.3-37289.6" - wire $0\dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:37075.3-37117.6" - wire $0\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "libresoc.v:36731.3-36773.6" - wire width 2 $0\dec31_dec_sub8_upd[1:0] - attribute \src "libresoc.v:36388.7-36388.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:36860.3-36902.6" - wire width 8 $1\dec31_dec_sub8_asmcode[7:0] - attribute \src "libresoc.v:37032.3-37074.6" - wire $1\dec31_dec_sub8_br[0:0] - attribute \src "libresoc.v:37591.3-37633.6" - wire width 3 $1\dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:37634.3-37676.6" - wire width 3 $1\dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:36817.3-36859.6" - wire width 2 $1\dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:36989.3-37031.6" - wire $1\dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:37376.3-37418.6" - wire width 5 $1\dec31_dec_sub8_form[4:0] - attribute \src "libresoc.v:36645.3-36687.6" - wire width 12 $1\dec31_dec_sub8_function_unit[11:0] - attribute \src "libresoc.v:37419.3-37461.6" - wire width 3 $1\dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:37462.3-37504.6" - wire width 4 $1\dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:37505.3-37547.6" - wire width 2 $1\dec31_dec_sub8_in3_sel[1:0] - attribute \src "libresoc.v:37118.3-37160.6" - wire width 7 $1\dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:36903.3-36945.6" - wire $1\dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:36946.3-36988.6" - wire $1\dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:37204.3-37246.6" - wire $1\dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:36688.3-36730.6" - wire width 4 $1\dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:37290.3-37332.6" - wire $1\dec31_dec_sub8_lk[0:0] - attribute \src "libresoc.v:37548.3-37590.6" - wire width 2 $1\dec31_dec_sub8_out_sel[1:0] - attribute \src "libresoc.v:36774.3-36816.6" - wire width 2 $1\dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:37161.3-37203.6" - wire $1\dec31_dec_sub8_rsrv[0:0] - attribute \src "libresoc.v:37333.3-37375.6" - wire $1\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "libresoc.v:37247.3-37289.6" - wire $1\dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:37075.3-37117.6" - wire $1\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "libresoc.v:36731.3-36773.6" - wire width 2 $1\dec31_dec_sub8_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub8_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub8_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub8_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub8_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub8_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub8_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub8_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub8_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub8_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub8_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub8_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub8_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub8_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub8_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub8_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub8_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub8_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub8_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub8_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub8_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub8_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub8_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub8_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub8_upd - attribute \src "libresoc.v:36388.7-36388.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:36388.7-36388.20" - process $proc$libresoc.v:36388$831 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127725$5396 + parameter \WIDTH 1 + connect \A \sdr_dq_4__core__oe + connect \B \io_bd [96] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127725$5396_Y end - attribute \src "libresoc.v:36645.3-36687.6" - process $proc$libresoc.v:36645$807 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_function_unit[11:0] $1\dec31_dec_sub8_function_unit[11:0] - attribute \src "libresoc.v:36646.5-36646.29" - switch \initial - attribute \src "libresoc.v:36646.9-36646.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - case - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub8_function_unit $0\dec31_dec_sub8_function_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127726$5397 + parameter \WIDTH 1 + connect \A \sdr_dq_5__pad__i + connect \B \io_bd [97] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127726$5397_Y end - attribute \src "libresoc.v:36688.3-36730.6" - process $proc$libresoc.v:36688$808 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_ldst_len[3:0] $1\dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:36689.5-36689.29" - switch \initial - attribute \src "libresoc.v:36689.9-36689.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub8_ldst_len $0\dec31_dec_sub8_ldst_len[3:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127727$5398 + parameter \WIDTH 1 + connect \A \sdr_dq_5__core__o + connect \B \io_bd [98] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127727$5398_Y end - attribute \src "libresoc.v:36731.3-36773.6" - process $proc$libresoc.v:36731$809 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_upd[1:0] $1\dec31_dec_sub8_upd[1:0] - attribute \src "libresoc.v:36732.5-36732.29" - switch \initial - attribute \src "libresoc.v:36732.9-36732.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub8_upd $0\dec31_dec_sub8_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127728$5399 + parameter \WIDTH 1 + connect \A \sdr_dq_5__core__oe + connect \B \io_bd [99] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127728$5399_Y end - attribute \src "libresoc.v:36774.3-36816.6" - process $proc$libresoc.v:36774$810 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_rc_sel[1:0] $1\dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:36775.5-36775.29" - switch \initial - attribute \src "libresoc.v:36775.9-36775.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub8_rc_sel $0\dec31_dec_sub8_rc_sel[1:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127729$5400 + parameter \WIDTH 1 + connect \A \sdr_dq_6__pad__i + connect \B \io_bd [100] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127729$5400_Y end - attribute \src "libresoc.v:36817.3-36859.6" - process $proc$libresoc.v:36817$811 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_cry_in[1:0] $1\dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:36818.5-36818.29" - switch \initial - attribute \src "libresoc.v:36818.9-36818.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 - case - assign $1\dec31_dec_sub8_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub8_cry_in $0\dec31_dec_sub8_cry_in[1:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127730$5401 + parameter \WIDTH 1 + connect \A \sdr_dq_6__core__o + connect \B \io_bd [101] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127730$5401_Y end - attribute \src "libresoc.v:36860.3-36902.6" - process $proc$libresoc.v:36860$812 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_asmcode[7:0] $1\dec31_dec_sub8_asmcode[7:0] - attribute \src "libresoc.v:36861.5-36861.29" - switch \initial - attribute \src "libresoc.v:36861.9-36861.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'10000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'10000101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'10111110 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'10111111 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000111 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11001000 - case - assign $1\dec31_dec_sub8_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub8_asmcode $0\dec31_dec_sub8_asmcode[7:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127731$5402 + parameter \WIDTH 1 + connect \A \sdr_dq_6__core__oe + connect \B \io_bd [102] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127731$5402_Y end - attribute \src "libresoc.v:36903.3-36945.6" - process $proc$libresoc.v:36903$813 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_inv_a[0:0] $1\dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:36904.5-36904.29" - switch \initial - attribute \src "libresoc.v:36904.9-36904.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - case - assign $1\dec31_dec_sub8_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_inv_a $0\dec31_dec_sub8_inv_a[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127732$5403 + parameter \WIDTH 1 + connect \A \sdr_dq_7__pad__i + connect \B \io_bd [103] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127732$5403_Y end - attribute \src "libresoc.v:36946.3-36988.6" - process $proc$libresoc.v:36946$814 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_inv_out[0:0] $1\dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:36947.5-36947.29" - switch \initial - attribute \src "libresoc.v:36947.9-36947.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_inv_out $0\dec31_dec_sub8_inv_out[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127734$5405 + parameter \WIDTH 1 + connect \A \sdr_dq_7__core__o + connect \B \io_bd [104] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127734$5405_Y end - attribute \src "libresoc.v:36989.3-37031.6" - process $proc$libresoc.v:36989$815 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_cry_out[0:0] $1\dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:36990.5-36990.29" - switch \initial - attribute \src "libresoc.v:36990.9-36990.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 - case - assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_cry_out $0\dec31_dec_sub8_cry_out[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127735$5406 + parameter \WIDTH 1 + connect \A \sdr_dq_7__core__oe + connect \B \io_bd [105] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127735$5406_Y end - attribute \src "libresoc.v:37032.3-37074.6" - process $proc$libresoc.v:37032$816 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_br[0:0] $1\dec31_dec_sub8_br[0:0] - attribute \src "libresoc.v:37033.5-37033.29" - switch \initial - attribute \src "libresoc.v:37033.9-37033.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - case - assign $1\dec31_dec_sub8_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_br $0\dec31_dec_sub8_br[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127736$5407 + parameter \WIDTH 1 + connect \A \sdr_a_0__core__o + connect \B \io_bd [106] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127736$5407_Y end - attribute \src "libresoc.v:37075.3-37117.6" - process $proc$libresoc.v:37075$817 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_sgn_ext[0:0] $1\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "libresoc.v:37076.5-37076.29" - switch \initial - attribute \src "libresoc.v:37076.9-37076.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_sgn_ext $0\dec31_dec_sub8_sgn_ext[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127737$5408 + parameter \WIDTH 1 + connect \A \sdr_a_1__core__o + connect \B \io_bd [107] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127737$5408_Y end - attribute \src "libresoc.v:37118.3-37160.6" - process $proc$libresoc.v:37118$818 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_internal_op[6:0] $1\dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:37119.5-37119.29" - switch \initial - attribute \src "libresoc.v:37119.9-37119.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - case - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub8_internal_op $0\dec31_dec_sub8_internal_op[6:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127738$5409 + parameter \WIDTH 1 + connect \A \sdr_a_2__core__o + connect \B \io_bd [108] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127738$5409_Y end - attribute \src "libresoc.v:37161.3-37203.6" - process $proc$libresoc.v:37161$819 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_rsrv[0:0] $1\dec31_dec_sub8_rsrv[0:0] - attribute \src "libresoc.v:37162.5-37162.29" - switch \initial - attribute \src "libresoc.v:37162.9-37162.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_rsrv $0\dec31_dec_sub8_rsrv[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127739$5410 + parameter \WIDTH 1 + connect \A \sdr_a_3__core__o + connect \B \io_bd [109] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127739$5410_Y end - attribute \src "libresoc.v:37204.3-37246.6" - process $proc$libresoc.v:37204$820 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_is_32b[0:0] $1\dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:37205.5-37205.29" - switch \initial - attribute \src "libresoc.v:37205.9-37205.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_is_32b $0\dec31_dec_sub8_is_32b[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127740$5411 + parameter \WIDTH 1 + connect \A \sdr_a_4__core__o + connect \B \io_bd [110] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127740$5411_Y end - attribute \src "libresoc.v:37247.3-37289.6" - process $proc$libresoc.v:37247$821 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_sgn[0:0] $1\dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:37248.5-37248.29" - switch \initial - attribute \src "libresoc.v:37248.9-37248.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_sgn $0\dec31_dec_sub8_sgn[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127741$5412 + parameter \WIDTH 1 + connect \A \sdr_a_5__core__o + connect \B \io_bd [111] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127741$5412_Y end - attribute \src "libresoc.v:37290.3-37332.6" - process $proc$libresoc.v:37290$822 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_lk[0:0] $1\dec31_dec_sub8_lk[0:0] - attribute \src "libresoc.v:37291.5-37291.29" - switch \initial - attribute \src "libresoc.v:37291.9-37291.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_lk $0\dec31_dec_sub8_lk[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127742$5413 + parameter \WIDTH 1 + connect \A \sdr_a_6__core__o + connect \B \io_bd [112] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127742$5413_Y end - attribute \src "libresoc.v:37333.3-37375.6" - process $proc$libresoc.v:37333$823 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_sgl_pipe[0:0] $1\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "libresoc.v:37334.5-37334.29" - switch \initial - attribute \src "libresoc.v:37334.9-37334.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_sgl_pipe $0\dec31_dec_sub8_sgl_pipe[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127743$5414 + parameter \WIDTH 1 + connect \A \sdr_a_7__core__o + connect \B \io_bd [113] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127743$5414_Y end - attribute \src "libresoc.v:37376.3-37418.6" - process $proc$libresoc.v:37376$824 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_form[4:0] $1\dec31_dec_sub8_form[4:0] - attribute \src "libresoc.v:37377.5-37377.29" - switch \initial - attribute \src "libresoc.v:37377.9-37377.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - case - assign $1\dec31_dec_sub8_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub8_form $0\dec31_dec_sub8_form[4:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127745$5416 + parameter \WIDTH 1 + connect \A \sdr_a_8__core__o + connect \B \io_bd [114] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127745$5416_Y end - attribute \src "libresoc.v:37419.3-37461.6" - process $proc$libresoc.v:37419$825 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_in1_sel[2:0] $1\dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:37420.5-37420.29" - switch \initial - attribute \src "libresoc.v:37420.9-37420.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - case - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub8_in1_sel $0\dec31_dec_sub8_in1_sel[2:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127746$5417 + parameter \WIDTH 1 + connect \A \sdr_a_9__core__o + connect \B \io_bd [115] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127746$5417_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127747$5418 + parameter \WIDTH 1 + connect \A \sdr_ba_0__core__o + connect \B \io_bd [116] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127747$5418_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127748$5419 + parameter \WIDTH 1 + connect \A \sdr_ba_1__core__o + connect \B \io_bd [117] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127748$5419_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127749$5420 + parameter \WIDTH 1 + connect \A \sdr_clock__core__o + connect \B \io_bd [118] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127749$5420_Y end - attribute \src "libresoc.v:37462.3-37504.6" - process $proc$libresoc.v:37462$826 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_in2_sel[3:0] $1\dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:37463.5-37463.29" - switch \initial - attribute \src "libresoc.v:37463.9-37463.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'1001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'1001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 - case - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub8_in2_sel $0\dec31_dec_sub8_in2_sel[3:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127750$5421 + parameter \WIDTH 1 + connect \A \sdr_cke__core__o + connect \B \io_bd [119] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127750$5421_Y end - attribute \src "libresoc.v:37505.3-37547.6" - process $proc$libresoc.v:37505$827 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_in3_sel[1:0] $1\dec31_dec_sub8_in3_sel[1:0] - attribute \src "libresoc.v:37506.5-37506.29" - switch \initial - attribute \src "libresoc.v:37506.9-37506.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub8_in3_sel $0\dec31_dec_sub8_in3_sel[1:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127751$5422 + parameter \WIDTH 1 + connect \A \sdr_ras_n__core__o + connect \B \io_bd [120] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127751$5422_Y end - attribute \src "libresoc.v:37548.3-37590.6" - process $proc$libresoc.v:37548$828 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_out_sel[1:0] $1\dec31_dec_sub8_out_sel[1:0] - attribute \src "libresoc.v:37549.5-37549.29" - switch \initial - attribute \src "libresoc.v:37549.9-37549.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub8_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub8_out_sel $0\dec31_dec_sub8_out_sel[1:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127752$5423 + parameter \WIDTH 1 + connect \A \sdr_cas_n__core__o + connect \B \io_bd [121] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127752$5423_Y end - attribute \src "libresoc.v:37591.3-37633.6" - process $proc$libresoc.v:37591$829 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_cr_in[2:0] $1\dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:37592.5-37592.29" - switch \initial - attribute \src "libresoc.v:37592.9-37592.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub8_cr_in $0\dec31_dec_sub8_cr_in[2:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127753$5424 + parameter \WIDTH 1 + connect \A \sdr_we_n__core__o + connect \B \io_bd [122] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127753$5424_Y end - attribute \src "libresoc.v:37634.3-37676.6" - process $proc$libresoc.v:37634$830 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_cr_out[2:0] $1\dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:37635.5-37635.29" - switch \initial - attribute \src "libresoc.v:37635.9-37635.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - case - assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub8_cr_out $0\dec31_dec_sub8_cr_out[2:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127754$5425 + parameter \WIDTH 1 + connect \A \sdr_cs_n__core__o + connect \B \io_bd [123] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127754$5425_Y end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:37682.1-39261.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub9" -attribute \generator "nMigen" -module \dec31_dec_sub9 - attribute \src "libresoc.v:38215.3-38269.6" - wire width 8 $0\dec31_dec_sub9_asmcode[7:0] - attribute \src "libresoc.v:38435.3-38489.6" - wire $0\dec31_dec_sub9_br[0:0] - attribute \src "libresoc.v:39150.3-39204.6" - wire width 3 $0\dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:39205.3-39259.6" - wire width 3 $0\dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:38160.3-38214.6" - wire width 2 $0\dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:38380.3-38434.6" - wire $0\dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:38875.3-38929.6" - wire width 5 $0\dec31_dec_sub9_form[4:0] - attribute \src "libresoc.v:37940.3-37994.6" - wire width 12 $0\dec31_dec_sub9_function_unit[11:0] - attribute \src "libresoc.v:38930.3-38984.6" - wire width 3 $0\dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:38985.3-39039.6" - wire width 4 $0\dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:39040.3-39094.6" - wire width 2 $0\dec31_dec_sub9_in3_sel[1:0] - attribute \src "libresoc.v:38545.3-38599.6" - wire width 7 $0\dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:38270.3-38324.6" - wire $0\dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:38325.3-38379.6" - wire $0\dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:38655.3-38709.6" - wire $0\dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:37995.3-38049.6" - wire width 4 $0\dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:38765.3-38819.6" - wire $0\dec31_dec_sub9_lk[0:0] - attribute \src "libresoc.v:39095.3-39149.6" - wire width 2 $0\dec31_dec_sub9_out_sel[1:0] - attribute \src "libresoc.v:38105.3-38159.6" - wire width 2 $0\dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:38600.3-38654.6" - wire $0\dec31_dec_sub9_rsrv[0:0] - attribute \src "libresoc.v:38820.3-38874.6" - wire $0\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "libresoc.v:38710.3-38764.6" - wire $0\dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:38490.3-38544.6" - wire $0\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "libresoc.v:38050.3-38104.6" - wire width 2 $0\dec31_dec_sub9_upd[1:0] - attribute \src "libresoc.v:37683.7-37683.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:38215.3-38269.6" - wire width 8 $1\dec31_dec_sub9_asmcode[7:0] - attribute \src "libresoc.v:38435.3-38489.6" - wire $1\dec31_dec_sub9_br[0:0] - attribute \src "libresoc.v:39150.3-39204.6" - wire width 3 $1\dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:39205.3-39259.6" - wire width 3 $1\dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:38160.3-38214.6" - wire width 2 $1\dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:38380.3-38434.6" - wire $1\dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:38875.3-38929.6" - wire width 5 $1\dec31_dec_sub9_form[4:0] - attribute \src "libresoc.v:37940.3-37994.6" - wire width 12 $1\dec31_dec_sub9_function_unit[11:0] - attribute \src "libresoc.v:38930.3-38984.6" - wire width 3 $1\dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:38985.3-39039.6" - wire width 4 $1\dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:39040.3-39094.6" - wire width 2 $1\dec31_dec_sub9_in3_sel[1:0] - attribute \src "libresoc.v:38545.3-38599.6" - wire width 7 $1\dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:38270.3-38324.6" - wire $1\dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:38325.3-38379.6" - wire $1\dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:38655.3-38709.6" - wire $1\dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:37995.3-38049.6" - wire width 4 $1\dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:38765.3-38819.6" - wire $1\dec31_dec_sub9_lk[0:0] - attribute \src "libresoc.v:39095.3-39149.6" - wire width 2 $1\dec31_dec_sub9_out_sel[1:0] - attribute \src "libresoc.v:38105.3-38159.6" - wire width 2 $1\dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:38600.3-38654.6" - wire $1\dec31_dec_sub9_rsrv[0:0] - attribute \src "libresoc.v:38820.3-38874.6" - wire $1\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "libresoc.v:38710.3-38764.6" - wire $1\dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:38490.3-38544.6" - wire $1\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "libresoc.v:38050.3-38104.6" - wire width 2 $1\dec31_dec_sub9_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub9_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub9_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub9_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub9_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub9_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub9_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub9_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub9_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub9_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub9_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub9_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub9_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub9_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub9_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub9_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub9_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub9_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub9_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub9_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub9_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub9_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub9_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub9_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub9_upd - attribute \src "libresoc.v:37683.7-37683.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:37683.7-37683.20" - process $proc$libresoc.v:37683$856 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127756$5427 + parameter \WIDTH 1 + connect \A \sdr_a_10__core__o + connect \B \io_bd [124] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127756$5427_Y end - attribute \src "libresoc.v:37940.3-37994.6" - process $proc$libresoc.v:37940$832 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_function_unit[11:0] $1\dec31_dec_sub9_function_unit[11:0] - attribute \src "libresoc.v:37941.5-37941.29" - switch \initial - attribute \src "libresoc.v:37941.9-37941.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 - case - assign $1\dec31_dec_sub9_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub9_function_unit $0\dec31_dec_sub9_function_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127757$5428 + parameter \WIDTH 1 + connect \A \sdr_a_11__core__o + connect \B \io_bd [125] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127757$5428_Y end - attribute \src "libresoc.v:37995.3-38049.6" - process $proc$libresoc.v:37995$833 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_ldst_len[3:0] $1\dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:37996.5-37996.29" - switch \initial - attribute \src "libresoc.v:37996.9-37996.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub9_ldst_len $0\dec31_dec_sub9_ldst_len[3:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127758$5429 + parameter \WIDTH 1 + connect \A \sdr_a_12__core__o + connect \B \io_bd [126] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127758$5429_Y end - attribute \src "libresoc.v:38050.3-38104.6" - process $proc$libresoc.v:38050$834 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_upd[1:0] $1\dec31_dec_sub9_upd[1:0] - attribute \src "libresoc.v:38051.5-38051.29" - switch \initial - attribute \src "libresoc.v:38051.9-38051.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub9_upd $0\dec31_dec_sub9_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127759$5430 + parameter \WIDTH 1 + connect \A \sdr_dm_1__pad__i + connect \B \io_bd [127] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127759$5430_Y end - attribute \src "libresoc.v:38105.3-38159.6" - process $proc$libresoc.v:38105$835 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_rc_sel[1:0] $1\dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:38106.5-38106.29" - switch \initial - attribute \src "libresoc.v:38106.9-38106.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub9_rc_sel $0\dec31_dec_sub9_rc_sel[1:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127760$5431 + parameter \WIDTH 1 + connect \A \sdr_dm_1__core__o + connect \B \io_bd [128] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127760$5431_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127761$5432 + parameter \WIDTH 1 + connect \A \sdr_dm_1__core__oe + connect \B \io_bd [129] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127761$5432_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127762$5433 + parameter \WIDTH 1 + connect \A \sdr_dq_8__pad__i + connect \B \io_bd [130] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127762$5433_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127763$5434 + parameter \WIDTH 1 + connect \A \sdr_dq_8__core__o + connect \B \io_bd [131] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127763$5434_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127764$5435 + parameter \WIDTH 1 + connect \A \sdr_dq_8__core__oe + connect \B \io_bd [132] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127764$5435_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127765$5436 + parameter \WIDTH 1 + connect \A \sdr_dq_9__pad__i + connect \B \io_bd [133] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127765$5436_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127767$5438 + parameter \WIDTH 1 + connect \A \sdr_dq_9__core__o + connect \B \io_bd [134] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127767$5438_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127768$5439 + parameter \WIDTH 1 + connect \A \sdr_dq_9__core__oe + connect \B \io_bd [135] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127768$5439_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127769$5440 + parameter \WIDTH 1 + connect \A \sdr_dq_10__pad__i + connect \B \io_bd [136] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127769$5440_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127770$5441 + parameter \WIDTH 1 + connect \A \sdr_dq_10__core__o + connect \B \io_bd [137] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127770$5441_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127771$5442 + parameter \WIDTH 1 + connect \A \sdr_dq_10__core__oe + connect \B \io_bd [138] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127771$5442_Y end - attribute \src "libresoc.v:38160.3-38214.6" - process $proc$libresoc.v:38160$836 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_cry_in[1:0] $1\dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:38161.5-38161.29" - switch \initial - attribute \src "libresoc.v:38161.9-38161.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub9_cry_in $0\dec31_dec_sub9_cry_in[1:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127772$5443 + parameter \WIDTH 1 + connect \A \sdr_dq_11__pad__i + connect \B \io_bd [139] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127772$5443_Y end - attribute \src "libresoc.v:38215.3-38269.6" - process $proc$libresoc.v:38215$837 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_asmcode[7:0] $1\dec31_dec_sub9_asmcode[7:0] - attribute \src "libresoc.v:38216.5-38216.29" - switch \initial - attribute \src "libresoc.v:38216.9-38216.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110111 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01110100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01110010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111110 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111111 - case - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub9_asmcode $0\dec31_dec_sub9_asmcode[7:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127773$5444 + parameter \WIDTH 1 + connect \A \sdr_dq_11__core__o + connect \B \io_bd [140] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127773$5444_Y end - attribute \src "libresoc.v:38270.3-38324.6" - process $proc$libresoc.v:38270$838 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_inv_a[0:0] $1\dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:38271.5-38271.29" - switch \initial - attribute \src "libresoc.v:38271.9-38271.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_inv_a $0\dec31_dec_sub9_inv_a[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127774$5445 + parameter \WIDTH 1 + connect \A \sdr_dq_11__core__oe + connect \B \io_bd [141] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127774$5445_Y end - attribute \src "libresoc.v:38325.3-38379.6" - process $proc$libresoc.v:38325$839 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_inv_out[0:0] $1\dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:38326.5-38326.29" - switch \initial - attribute \src "libresoc.v:38326.9-38326.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_inv_out $0\dec31_dec_sub9_inv_out[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127775$5446 + parameter \WIDTH 1 + connect \A \sdr_dq_12__pad__i + connect \B \io_bd [142] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127775$5446_Y end - attribute \src "libresoc.v:38380.3-38434.6" - process $proc$libresoc.v:38380$840 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_cry_out[0:0] $1\dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:38381.5-38381.29" - switch \initial - attribute \src "libresoc.v:38381.9-38381.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_cry_out $0\dec31_dec_sub9_cry_out[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127776$5447 + parameter \WIDTH 1 + connect \A \sdr_dq_12__core__o + connect \B \io_bd [143] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127776$5447_Y end - attribute \src "libresoc.v:38435.3-38489.6" - process $proc$libresoc.v:38435$841 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_br[0:0] $1\dec31_dec_sub9_br[0:0] - attribute \src "libresoc.v:38436.5-38436.29" - switch \initial - attribute \src "libresoc.v:38436.9-38436.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - case - assign $1\dec31_dec_sub9_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_br $0\dec31_dec_sub9_br[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127778$5449 + parameter \WIDTH 1 + connect \A \sdr_dq_12__core__oe + connect \B \io_bd [144] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127778$5449_Y end - attribute \src "libresoc.v:38490.3-38544.6" - process $proc$libresoc.v:38490$842 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_sgn_ext[0:0] $1\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "libresoc.v:38491.5-38491.29" - switch \initial - attribute \src "libresoc.v:38491.9-38491.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_sgn_ext $0\dec31_dec_sub9_sgn_ext[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127779$5450 + parameter \WIDTH 1 + connect \A \sdr_dq_13__pad__i + connect \B \io_bd [145] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127779$5450_Y end - attribute \src "libresoc.v:38545.3-38599.6" - process $proc$libresoc.v:38545$843 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_internal_op[6:0] $1\dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:38546.5-38546.29" - switch \initial - attribute \src "libresoc.v:38546.9-38546.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 - case - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub9_internal_op $0\dec31_dec_sub9_internal_op[6:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127780$5451 + parameter \WIDTH 1 + connect \A \sdr_dq_13__core__o + connect \B \io_bd [146] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127780$5451_Y end - attribute \src "libresoc.v:38600.3-38654.6" - process $proc$libresoc.v:38600$844 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_rsrv[0:0] $1\dec31_dec_sub9_rsrv[0:0] - attribute \src "libresoc.v:38601.5-38601.29" - switch \initial - attribute \src "libresoc.v:38601.9-38601.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_rsrv $0\dec31_dec_sub9_rsrv[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127781$5452 + parameter \WIDTH 1 + connect \A \sdr_dq_13__core__oe + connect \B \io_bd [147] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127781$5452_Y end - attribute \src "libresoc.v:38655.3-38709.6" - process $proc$libresoc.v:38655$845 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_is_32b[0:0] $1\dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:38656.5-38656.29" - switch \initial - attribute \src "libresoc.v:38656.9-38656.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_is_32b $0\dec31_dec_sub9_is_32b[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127782$5453 + parameter \WIDTH 1 + connect \A \sdr_dq_14__pad__i + connect \B \io_bd [148] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127782$5453_Y end - attribute \src "libresoc.v:38710.3-38764.6" - process $proc$libresoc.v:38710$846 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_sgn[0:0] $1\dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:38711.5-38711.29" - switch \initial - attribute \src "libresoc.v:38711.9-38711.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - case - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_sgn $0\dec31_dec_sub9_sgn[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127783$5454 + parameter \WIDTH 1 + connect \A \sdr_dq_14__core__o + connect \B \io_bd [149] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127783$5454_Y end - attribute \src "libresoc.v:38765.3-38819.6" - process $proc$libresoc.v:38765$847 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_lk[0:0] $1\dec31_dec_sub9_lk[0:0] - attribute \src "libresoc.v:38766.5-38766.29" - switch \initial - attribute \src "libresoc.v:38766.9-38766.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_lk $0\dec31_dec_sub9_lk[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127784$5455 + parameter \WIDTH 1 + connect \A \sdr_dq_14__core__oe + connect \B \io_bd [150] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127784$5455_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127785$5456 + parameter \WIDTH 1 + connect \A \sdr_dq_15__pad__i + connect \B \io_bd [151] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127785$5456_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127786$5457 + parameter \WIDTH 1 + connect \A \sdr_dq_15__core__o + connect \B \io_bd [152] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127786$5457_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127787$5458 + parameter \WIDTH 1 + connect \A \sdr_dq_15__core__oe + connect \B \io_bd [153] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127787$5458_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + cell $mux $ternary$libresoc.v:127874$5546 + parameter \WIDTH 1 + connect \A \eint_0__pad__i + connect \B \io_bd [0] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127874$5546_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + cell $mux $ternary$libresoc.v:127875$5547 + parameter \WIDTH 1 + connect \A \eint_1__pad__i + connect \B \io_bd [1] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127875$5547_Y end - attribute \src "libresoc.v:38820.3-38874.6" - process $proc$libresoc.v:38820$848 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_sgl_pipe[0:0] $1\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "libresoc.v:38821.5-38821.29" - switch \initial - attribute \src "libresoc.v:38821.9-38821.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_sgl_pipe $0\dec31_dec_sub9_sgl_pipe[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + cell $mux $ternary$libresoc.v:127876$5548 + parameter \WIDTH 1 + connect \A \eint_2__pad__i + connect \B \io_bd [2] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127876$5548_Y end - attribute \src "libresoc.v:38875.3-38929.6" - process $proc$libresoc.v:38875$849 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_form[4:0] $1\dec31_dec_sub9_form[4:0] - attribute \src "libresoc.v:38876.5-38876.29" - switch \initial - attribute \src "libresoc.v:38876.9-38876.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - case - assign $1\dec31_dec_sub9_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub9_form $0\dec31_dec_sub9_form[4:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127877$5549 + parameter \WIDTH 1 + connect \A \gpio_e8__pad__i + connect \B \io_bd [3] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127877$5549_Y end - attribute \src "libresoc.v:38930.3-38984.6" - process $proc$libresoc.v:38930$850 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_in1_sel[2:0] $1\dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:38931.5-38931.29" - switch \initial - attribute \src "libresoc.v:38931.9-38931.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - case - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub9_in1_sel $0\dec31_dec_sub9_in1_sel[2:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127879$5551 + parameter \WIDTH 1 + connect \A \gpio_e8__core__o + connect \B \io_bd [4] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127879$5551_Y end - attribute \src "libresoc.v:38985.3-39039.6" - process $proc$libresoc.v:38985$851 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_in2_sel[3:0] $1\dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:38986.5-38986.29" - switch \initial - attribute \src "libresoc.v:38986.9-38986.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub9_in2_sel $0\dec31_dec_sub9_in2_sel[3:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127880$5552 + parameter \WIDTH 1 + connect \A \gpio_e8__core__oe + connect \B \io_bd [5] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127880$5552_Y end - attribute \src "libresoc.v:39040.3-39094.6" - process $proc$libresoc.v:39040$852 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_in3_sel[1:0] $1\dec31_dec_sub9_in3_sel[1:0] - attribute \src "libresoc.v:39041.5-39041.29" - switch \initial - attribute \src "libresoc.v:39041.9-39041.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub9_in3_sel $0\dec31_dec_sub9_in3_sel[1:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127881$5553 + parameter \WIDTH 1 + connect \A \gpio_e9__pad__i + connect \B \io_bd [6] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127881$5553_Y end - attribute \src "libresoc.v:39095.3-39149.6" - process $proc$libresoc.v:39095$853 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_out_sel[1:0] $1\dec31_dec_sub9_out_sel[1:0] - attribute \src "libresoc.v:39096.5-39096.29" - switch \initial - attribute \src "libresoc.v:39096.9-39096.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub9_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub9_out_sel $0\dec31_dec_sub9_out_sel[1:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127882$5554 + parameter \WIDTH 1 + connect \A \gpio_e9__core__o + connect \B \io_bd [7] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127882$5554_Y end - attribute \src "libresoc.v:39150.3-39204.6" - process $proc$libresoc.v:39150$854 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_cr_in[2:0] $1\dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:39151.5-39151.29" - switch \initial - attribute \src "libresoc.v:39151.9-39151.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub9_cr_in $0\dec31_dec_sub9_cr_in[2:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127883$5555 + parameter \WIDTH 1 + connect \A \gpio_e9__core__oe + connect \B \io_bd [8] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127883$5555_Y end - attribute \src "libresoc.v:39205.3-39259.6" - process $proc$libresoc.v:39205$855 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_cr_out[2:0] $1\dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:39206.5-39206.29" - switch \initial - attribute \src "libresoc.v:39206.9-39206.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - case - assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub9_cr_out $0\dec31_dec_sub9_cr_out[2:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127884$5556 + parameter \WIDTH 1 + connect \A \gpio_e10__pad__i + connect \B \io_bd [9] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127884$5556_Y end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:39265.1-39908.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec58" -attribute \generator "nMigen" -module \dec58 - attribute \src "libresoc.v:39603.3-39618.6" - wire width 8 $0\dec58_asmcode[7:0] - attribute \src "libresoc.v:39667.3-39682.6" - wire $0\dec58_br[0:0] - attribute \src "libresoc.v:39875.3-39890.6" - wire width 3 $0\dec58_cr_in[2:0] - attribute \src "libresoc.v:39891.3-39906.6" - wire width 3 $0\dec58_cr_out[2:0] - attribute \src "libresoc.v:39587.3-39602.6" - wire width 2 $0\dec58_cry_in[1:0] - attribute \src "libresoc.v:39651.3-39666.6" - wire $0\dec58_cry_out[0:0] - attribute \src "libresoc.v:39795.3-39810.6" - wire width 5 $0\dec58_form[4:0] - attribute \src "libresoc.v:39523.3-39538.6" - wire width 12 $0\dec58_function_unit[11:0] - attribute \src "libresoc.v:39811.3-39826.6" - wire width 3 $0\dec58_in1_sel[2:0] - attribute \src "libresoc.v:39827.3-39842.6" - wire width 4 $0\dec58_in2_sel[3:0] - attribute \src "libresoc.v:39843.3-39858.6" - wire width 2 $0\dec58_in3_sel[1:0] - attribute \src "libresoc.v:39699.3-39714.6" - wire width 7 $0\dec58_internal_op[6:0] - attribute \src "libresoc.v:39619.3-39634.6" - wire $0\dec58_inv_a[0:0] - attribute \src "libresoc.v:39635.3-39650.6" - wire $0\dec58_inv_out[0:0] - attribute \src "libresoc.v:39731.3-39746.6" - wire $0\dec58_is_32b[0:0] - attribute \src "libresoc.v:39539.3-39554.6" - wire width 4 $0\dec58_ldst_len[3:0] - attribute \src "libresoc.v:39763.3-39778.6" - wire $0\dec58_lk[0:0] - attribute \src "libresoc.v:39859.3-39874.6" - wire width 2 $0\dec58_out_sel[1:0] - attribute \src "libresoc.v:39571.3-39586.6" - wire width 2 $0\dec58_rc_sel[1:0] - attribute \src "libresoc.v:39715.3-39730.6" - wire $0\dec58_rsrv[0:0] - attribute \src "libresoc.v:39779.3-39794.6" - wire $0\dec58_sgl_pipe[0:0] - attribute \src "libresoc.v:39747.3-39762.6" - wire $0\dec58_sgn[0:0] - attribute \src "libresoc.v:39683.3-39698.6" - wire $0\dec58_sgn_ext[0:0] - attribute \src "libresoc.v:39555.3-39570.6" - wire width 2 $0\dec58_upd[1:0] - attribute \src "libresoc.v:39266.7-39266.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:39603.3-39618.6" - wire width 8 $1\dec58_asmcode[7:0] - attribute \src "libresoc.v:39667.3-39682.6" - wire $1\dec58_br[0:0] - attribute \src "libresoc.v:39875.3-39890.6" - wire width 3 $1\dec58_cr_in[2:0] - attribute \src "libresoc.v:39891.3-39906.6" - wire width 3 $1\dec58_cr_out[2:0] - attribute \src "libresoc.v:39587.3-39602.6" - wire width 2 $1\dec58_cry_in[1:0] - attribute \src "libresoc.v:39651.3-39666.6" - wire $1\dec58_cry_out[0:0] - attribute \src "libresoc.v:39795.3-39810.6" - wire width 5 $1\dec58_form[4:0] - attribute \src "libresoc.v:39523.3-39538.6" - wire width 12 $1\dec58_function_unit[11:0] - attribute \src "libresoc.v:39811.3-39826.6" - wire width 3 $1\dec58_in1_sel[2:0] - attribute \src "libresoc.v:39827.3-39842.6" - wire width 4 $1\dec58_in2_sel[3:0] - attribute \src "libresoc.v:39843.3-39858.6" - wire width 2 $1\dec58_in3_sel[1:0] - attribute \src "libresoc.v:39699.3-39714.6" - wire width 7 $1\dec58_internal_op[6:0] - attribute \src "libresoc.v:39619.3-39634.6" - wire $1\dec58_inv_a[0:0] - attribute \src "libresoc.v:39635.3-39650.6" - wire $1\dec58_inv_out[0:0] - attribute \src "libresoc.v:39731.3-39746.6" - wire $1\dec58_is_32b[0:0] - attribute \src "libresoc.v:39539.3-39554.6" - wire width 4 $1\dec58_ldst_len[3:0] - attribute \src "libresoc.v:39763.3-39778.6" - wire $1\dec58_lk[0:0] - attribute \src "libresoc.v:39859.3-39874.6" - wire width 2 $1\dec58_out_sel[1:0] - attribute \src "libresoc.v:39571.3-39586.6" - wire width 2 $1\dec58_rc_sel[1:0] - attribute \src "libresoc.v:39715.3-39730.6" - wire $1\dec58_rsrv[0:0] - attribute \src "libresoc.v:39779.3-39794.6" - wire $1\dec58_sgl_pipe[0:0] - attribute \src "libresoc.v:39747.3-39762.6" - wire $1\dec58_sgn[0:0] - attribute \src "libresoc.v:39683.3-39698.6" - wire $1\dec58_sgn_ext[0:0] - attribute \src "libresoc.v:39555.3-39570.6" - wire width 2 $1\dec58_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec58_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec58_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec58_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec58_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec58_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec58_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec58_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec58_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec58_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec58_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec58_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec58_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec58_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec58_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec58_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec58_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec58_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec58_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec58_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec58_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec58_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec58_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec58_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec58_upd - attribute \src "libresoc.v:39266.7-39266.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 2 \opcode_switch - attribute \src "libresoc.v:39266.7-39266.20" - process $proc$libresoc.v:39266$881 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127885$5557 + parameter \WIDTH 1 + connect \A \gpio_e10__core__o + connect \B \io_bd [10] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127885$5557_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127886$5558 + parameter \WIDTH 1 + connect \A \gpio_e10__core__oe + connect \B \io_bd [11] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127886$5558_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127887$5559 + parameter \WIDTH 1 + connect \A \gpio_e11__pad__i + connect \B \io_bd [12] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127887$5559_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127888$5560 + parameter \WIDTH 1 + connect \A \gpio_e11__core__o + connect \B \io_bd [13] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127888$5560_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127890$5562 + parameter \WIDTH 1 + connect \A \gpio_e11__core__oe + connect \B \io_bd [14] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127890$5562_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127891$5563 + parameter \WIDTH 1 + connect \A \gpio_e12__pad__i + connect \B \io_bd [15] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127891$5563_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127892$5564 + parameter \WIDTH 1 + connect \A \gpio_e12__core__o + connect \B \io_bd [16] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127892$5564_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127893$5565 + parameter \WIDTH 1 + connect \A \gpio_e12__core__oe + connect \B \io_bd [17] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127893$5565_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127894$5566 + parameter \WIDTH 1 + connect \A \gpio_e13__pad__i + connect \B \io_bd [18] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127894$5566_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127895$5567 + parameter \WIDTH 1 + connect \A \gpio_e13__core__o + connect \B \io_bd [19] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127895$5567_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127896$5568 + parameter \WIDTH 1 + connect \A \gpio_e13__core__oe + connect \B \io_bd [20] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127896$5568_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127897$5569 + parameter \WIDTH 1 + connect \A \gpio_e14__pad__i + connect \B \io_bd [21] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127897$5569_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127898$5570 + parameter \WIDTH 1 + connect \A \gpio_e14__core__o + connect \B \io_bd [22] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127898$5570_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127899$5571 + parameter \WIDTH 1 + connect \A \gpio_e14__core__oe + connect \B \io_bd [23] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127899$5571_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:127972.8-127984.4" + cell \_fsm \_fsm + connect \TAP_bus__tck \TAP_bus__tck + connect \TAP_bus__tms \TAP_bus__tms + connect \capture \_fsm_capture + connect \isdr \_fsm_isdr + connect \isir \_fsm_isir + connect \negjtag_clk \negjtag_clk + connect \negjtag_rst \negjtag_rst + connect \posjtag_clk \posjtag_clk + connect \posjtag_rst \posjtag_rst + connect \shift \_fsm_shift + connect \update \_fsm_update + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:127985.12-127995.4" + cell \_idblock \_idblock + connect \TAP_bus__tdi \TAP_bus__tdi + connect \TAP_id_tdo \_idblock_TAP_id_tdo + connect \capture \_fsm_capture + connect \id_bypass \_idblock_id_bypass + connect \posjtag_clk \posjtag_clk + connect \posjtag_rst \posjtag_rst + connect \select_id \_idblock_select_id + connect \shift \_fsm_shift + connect \update \_fsm_update + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:127996.12-128006.4" + cell \_irblock \_irblock + connect \TAP_bus__tdi \TAP_bus__tdi + connect \capture \_fsm_capture + connect \ir \_irblock_ir + connect \isir \_fsm_isir + connect \posjtag_clk \posjtag_clk + connect \posjtag_rst \posjtag_rst + connect \shift \_fsm_shift + connect \tdo \_irblock_tdo + connect \update \_fsm_update + end + attribute \src "libresoc.v:126214.7-126214.20" + process $proc$libresoc.v:126214$5763 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:39523.3-39538.6" - process $proc$libresoc.v:39523$857 - assign { } { } + attribute \src "libresoc.v:126772.13-126772.32" + process $proc$libresoc.v:126772$5764 assign { } { } - assign $0\dec58_function_unit[11:0] $1\dec58_function_unit[11:0] - attribute \src "libresoc.v:39524.5-39524.29" - switch \initial - attribute \src "libresoc.v:39524.9-39524.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_function_unit[11:0] 12'000000000100 - case - assign $1\dec58_function_unit[11:0] 12'000000000000 - end + assign $1\dmi0__addr_i[3:0] 4'0000 sync always - update \dec58_function_unit $0\dec58_function_unit[11:0] + sync init + update \dmi0__addr_i $1\dmi0__addr_i[3:0] end - attribute \src "libresoc.v:39539.3-39554.6" - process $proc$libresoc.v:39539$858 + attribute \src "libresoc.v:126777.14-126777.46" + process $proc$libresoc.v:126777$5765 assign { } { } - assign { } { } - assign $0\dec58_ldst_len[3:0] $1\dec58_ldst_len[3:0] - attribute \src "libresoc.v:39540.5-39540.29" - switch \initial - attribute \src "libresoc.v:39540.9-39540.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_ldst_len[3:0] 4'0100 - case - assign $1\dec58_ldst_len[3:0] 4'0000 - end + assign $1\dmi0__din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always - update \dec58_ldst_len $0\dec58_ldst_len[3:0] + sync init + update \dmi0__din $1\dmi0__din[63:0] end - attribute \src "libresoc.v:39555.3-39570.6" - process $proc$libresoc.v:39555$859 - assign { } { } + attribute \src "libresoc.v:126791.7-126791.29" + process $proc$libresoc.v:126791$5766 assign { } { } - assign $0\dec58_upd[1:0] $1\dec58_upd[1:0] - attribute \src "libresoc.v:39556.5-39556.29" - switch \initial - attribute \src "libresoc.v:39556.9-39556.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_upd[1:0] 2'00 - case - assign $1\dec58_upd[1:0] 2'00 - end + assign $1\dmi0_addrsr__oe[0:0] 1'0 sync always - update \dec58_upd $0\dec58_upd[1:0] + sync init + update \dmi0_addrsr__oe $1\dmi0_addrsr__oe[0:0] end - attribute \src "libresoc.v:39571.3-39586.6" - process $proc$libresoc.v:39571$860 + attribute \src "libresoc.v:126799.13-126799.36" + process $proc$libresoc.v:126799$5767 assign { } { } - assign { } { } - assign $0\dec58_rc_sel[1:0] $1\dec58_rc_sel[1:0] - attribute \src "libresoc.v:39572.5-39572.29" - switch \initial - attribute \src "libresoc.v:39572.9-39572.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_rc_sel[1:0] 2'00 - case - assign $1\dec58_rc_sel[1:0] 2'00 - end + assign $1\dmi0_addrsr_reg[7:0] 8'00000000 sync always - update \dec58_rc_sel $0\dec58_rc_sel[1:0] + sync init + update \dmi0_addrsr_reg $1\dmi0_addrsr_reg[7:0] end - attribute \src "libresoc.v:39587.3-39602.6" - process $proc$libresoc.v:39587$861 - assign { } { } + attribute \src "libresoc.v:126807.7-126807.37" + process $proc$libresoc.v:126807$5768 assign { } { } - assign $0\dec58_cry_in[1:0] $1\dec58_cry_in[1:0] - attribute \src "libresoc.v:39588.5-39588.29" - switch \initial - attribute \src "libresoc.v:39588.9-39588.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_cry_in[1:0] 2'00 - case - assign $1\dec58_cry_in[1:0] 2'00 - end + assign $1\dmi0_addrsr_update_core[0:0] 1'0 sync always - update \dec58_cry_in $0\dec58_cry_in[1:0] + sync init + update \dmi0_addrsr_update_core $1\dmi0_addrsr_update_core[0:0] end - attribute \src "libresoc.v:39603.3-39618.6" - process $proc$libresoc.v:39603$862 + attribute \src "libresoc.v:126811.7-126811.42" + process $proc$libresoc.v:126811$5769 assign { } { } - assign { } { } - assign $0\dec58_asmcode[7:0] $1\dec58_asmcode[7:0] - attribute \src "libresoc.v:39604.5-39604.29" - switch \initial - attribute \src "libresoc.v:39604.9-39604.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_asmcode[7:0] 8'01010010 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_asmcode[7:0] 8'01010101 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_asmcode[7:0] 8'01100010 - case - assign $1\dec58_asmcode[7:0] 8'00000000 - end + assign $1\dmi0_addrsr_update_core_prev[0:0] 1'0 sync always - update \dec58_asmcode $0\dec58_asmcode[7:0] + sync init + update \dmi0_addrsr_update_core_prev $1\dmi0_addrsr_update_core_prev[0:0] end - attribute \src "libresoc.v:39619.3-39634.6" - process $proc$libresoc.v:39619$863 - assign { } { } + attribute \src "libresoc.v:126815.14-126815.51" + process $proc$libresoc.v:126815$5770 assign { } { } - assign $0\dec58_inv_a[0:0] $1\dec58_inv_a[0:0] - attribute \src "libresoc.v:39620.5-39620.29" - switch \initial - attribute \src "libresoc.v:39620.9-39620.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_inv_a[0:0] 1'0 - case - assign $1\dec58_inv_a[0:0] 1'0 - end + assign $1\dmi0_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always - update \dec58_inv_a $0\dec58_inv_a[0:0] + sync init + update \dmi0_datasr__i $1\dmi0_datasr__i[63:0] end - attribute \src "libresoc.v:39635.3-39650.6" - process $proc$libresoc.v:39635$864 + attribute \src "libresoc.v:126821.13-126821.35" + process $proc$libresoc.v:126821$5771 assign { } { } - assign { } { } - assign $0\dec58_inv_out[0:0] $1\dec58_inv_out[0:0] - attribute \src "libresoc.v:39636.5-39636.29" - switch \initial - attribute \src "libresoc.v:39636.9-39636.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_inv_out[0:0] 1'0 - case - assign $1\dec58_inv_out[0:0] 1'0 - end + assign $1\dmi0_datasr__oe[1:0] 2'00 sync always - update \dec58_inv_out $0\dec58_inv_out[0:0] + sync init + update \dmi0_datasr__oe $1\dmi0_datasr__oe[1:0] end - attribute \src "libresoc.v:39651.3-39666.6" - process $proc$libresoc.v:39651$865 - assign { } { } + attribute \src "libresoc.v:126829.14-126829.52" + process $proc$libresoc.v:126829$5772 assign { } { } - assign $0\dec58_cry_out[0:0] $1\dec58_cry_out[0:0] - attribute \src "libresoc.v:39652.5-39652.29" - switch \initial - attribute \src "libresoc.v:39652.9-39652.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_cry_out[0:0] 1'0 - case - assign $1\dec58_cry_out[0:0] 1'0 - end + assign $1\dmi0_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always - update \dec58_cry_out $0\dec58_cry_out[0:0] + sync init + update \dmi0_datasr_reg $1\dmi0_datasr_reg[63:0] end - attribute \src "libresoc.v:39667.3-39682.6" - process $proc$libresoc.v:39667$866 + attribute \src "libresoc.v:126837.7-126837.37" + process $proc$libresoc.v:126837$5773 assign { } { } - assign { } { } - assign $0\dec58_br[0:0] $1\dec58_br[0:0] - attribute \src "libresoc.v:39668.5-39668.29" - switch \initial - attribute \src "libresoc.v:39668.9-39668.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_br[0:0] 1'0 - case - assign $1\dec58_br[0:0] 1'0 - end + assign $1\dmi0_datasr_update_core[0:0] 1'0 sync always - update \dec58_br $0\dec58_br[0:0] + sync init + update \dmi0_datasr_update_core $1\dmi0_datasr_update_core[0:0] end - attribute \src "libresoc.v:39683.3-39698.6" - process $proc$libresoc.v:39683$867 - assign { } { } + attribute \src "libresoc.v:126841.7-126841.42" + process $proc$libresoc.v:126841$5774 assign { } { } - assign $0\dec58_sgn_ext[0:0] $1\dec58_sgn_ext[0:0] - attribute \src "libresoc.v:39684.5-39684.29" - switch \initial - attribute \src "libresoc.v:39684.9-39684.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_sgn_ext[0:0] 1'1 - case - assign $1\dec58_sgn_ext[0:0] 1'0 - end + assign $1\dmi0_datasr_update_core_prev[0:0] 1'0 sync always - update \dec58_sgn_ext $0\dec58_sgn_ext[0:0] + sync init + update \dmi0_datasr_update_core_prev $1\dmi0_datasr_update_core_prev[0:0] end - attribute \src "libresoc.v:39699.3-39714.6" - process $proc$libresoc.v:39699$868 + attribute \src "libresoc.v:126857.13-126857.29" + process $proc$libresoc.v:126857$5775 assign { } { } - assign { } { } - assign $0\dec58_internal_op[6:0] $1\dec58_internal_op[6:0] - attribute \src "libresoc.v:39700.5-39700.29" - switch \initial - attribute \src "libresoc.v:39700.9-39700.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_internal_op[6:0] 7'0100101 - case - assign $1\dec58_internal_op[6:0] 7'0000000 - end + assign $1\fsm_state[2:0] 3'000 sync always - update \dec58_internal_op $0\dec58_internal_op[6:0] + sync init + update \fsm_state $1\fsm_state[2:0] end - attribute \src "libresoc.v:39715.3-39730.6" - process $proc$libresoc.v:39715$869 - assign { } { } + attribute \src "libresoc.v:126859.13-126859.35" + process $proc$libresoc.v:126859$5776 assign { } { } - assign $0\dec58_rsrv[0:0] $1\dec58_rsrv[0:0] - attribute \src "libresoc.v:39716.5-39716.29" - switch \initial - attribute \src "libresoc.v:39716.9-39716.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_rsrv[0:0] 1'0 - case - assign $1\dec58_rsrv[0:0] 1'0 - end + assign $0\fsm_state$503[2:0]$5777 3'000 sync always - update \dec58_rsrv $0\dec58_rsrv[0:0] + sync init + update \fsm_state$503 $0\fsm_state$503[2:0]$5777 end - attribute \src "libresoc.v:39731.3-39746.6" - process $proc$libresoc.v:39731$870 + attribute \src "libresoc.v:127057.15-127057.67" + process $proc$libresoc.v:127057$5778 assign { } { } - assign { } { } - assign $0\dec58_is_32b[0:0] $1\dec58_is_32b[0:0] - attribute \src "libresoc.v:39732.5-39732.29" - switch \initial - attribute \src "libresoc.v:39732.9-39732.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_is_32b[0:0] 1'0 - case - assign $1\dec58_is_32b[0:0] 1'0 - end + assign $1\io_bd[153:0] 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always - update \dec58_is_32b $0\dec58_is_32b[0:0] + sync init + update \io_bd $1\io_bd[153:0] end - attribute \src "libresoc.v:39747.3-39762.6" - process $proc$libresoc.v:39747$871 - assign { } { } + attribute \src "libresoc.v:127069.15-127069.67" + process $proc$libresoc.v:127069$5779 assign { } { } - assign $0\dec58_sgn[0:0] $1\dec58_sgn[0:0] - attribute \src "libresoc.v:39748.5-39748.29" - switch \initial - attribute \src "libresoc.v:39748.9-39748.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_sgn[0:0] 1'0 - case - assign $1\dec58_sgn[0:0] 1'0 - end + assign $1\io_sr[153:0] 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always - update \dec58_sgn $0\dec58_sgn[0:0] + sync init + update \io_sr $1\io_sr[153:0] end - attribute \src "libresoc.v:39763.3-39778.6" - process $proc$libresoc.v:39763$872 + attribute \src "libresoc.v:127078.14-127078.41" + process $proc$libresoc.v:127078$5780 assign { } { } - assign { } { } - assign $0\dec58_lk[0:0] $1\dec58_lk[0:0] - attribute \src "libresoc.v:39764.5-39764.29" - switch \initial - attribute \src "libresoc.v:39764.9-39764.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_lk[0:0] 1'0 - case - assign $1\dec58_lk[0:0] 1'0 - end + assign $1\jtag_wb__adr[28:0] 29'00000000000000000000000000000 sync always - update \dec58_lk $0\dec58_lk[0:0] + sync init + update \jtag_wb__adr $1\jtag_wb__adr[28:0] end - attribute \src "libresoc.v:39779.3-39794.6" - process $proc$libresoc.v:39779$873 - assign { } { } + attribute \src "libresoc.v:127087.14-127087.51" + process $proc$libresoc.v:127087$5781 assign { } { } - assign $0\dec58_sgl_pipe[0:0] $1\dec58_sgl_pipe[0:0] - attribute \src "libresoc.v:39780.5-39780.29" - switch \initial - attribute \src "libresoc.v:39780.9-39780.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_sgl_pipe[0:0] 1'1 - case - assign $1\dec58_sgl_pipe[0:0] 1'0 - end + assign $1\jtag_wb__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always - update \dec58_sgl_pipe $0\dec58_sgl_pipe[0:0] + sync init + update \jtag_wb__dat_w $1\jtag_wb__dat_w[63:0] end - attribute \src "libresoc.v:39795.3-39810.6" - process $proc$libresoc.v:39795$874 + attribute \src "libresoc.v:127101.7-127101.32" + process $proc$libresoc.v:127101$5782 assign { } { } - assign { } { } - assign $0\dec58_form[4:0] $1\dec58_form[4:0] - attribute \src "libresoc.v:39796.5-39796.29" - switch \initial - attribute \src "libresoc.v:39796.9-39796.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_form[4:0] 5'00101 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_form[4:0] 5'00101 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_form[4:0] 5'00101 - case - assign $1\dec58_form[4:0] 5'00000 - end + assign $1\jtag_wb_addrsr__oe[0:0] 1'0 sync always - update \dec58_form $0\dec58_form[4:0] + sync init + update \jtag_wb_addrsr__oe $1\jtag_wb_addrsr__oe[0:0] end - attribute \src "libresoc.v:39811.3-39826.6" - process $proc$libresoc.v:39811$875 - assign { } { } + attribute \src "libresoc.v:127109.14-127109.47" + process $proc$libresoc.v:127109$5783 assign { } { } - assign $0\dec58_in1_sel[2:0] $1\dec58_in1_sel[2:0] - attribute \src "libresoc.v:39812.5-39812.29" - switch \initial - attribute \src "libresoc.v:39812.9-39812.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_in1_sel[2:0] 3'010 - case - assign $1\dec58_in1_sel[2:0] 3'000 - end + assign $1\jtag_wb_addrsr_reg[28:0] 29'00000000000000000000000000000 sync always - update \dec58_in1_sel $0\dec58_in1_sel[2:0] + sync init + update \jtag_wb_addrsr_reg $1\jtag_wb_addrsr_reg[28:0] end - attribute \src "libresoc.v:39827.3-39842.6" - process $proc$libresoc.v:39827$876 + attribute \src "libresoc.v:127117.7-127117.40" + process $proc$libresoc.v:127117$5784 assign { } { } - assign { } { } - assign $0\dec58_in2_sel[3:0] $1\dec58_in2_sel[3:0] - attribute \src "libresoc.v:39828.5-39828.29" - switch \initial - attribute \src "libresoc.v:39828.9-39828.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_in2_sel[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_in2_sel[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_in2_sel[3:0] 4'1000 - case - assign $1\dec58_in2_sel[3:0] 4'0000 - end + assign $1\jtag_wb_addrsr_update_core[0:0] 1'0 sync always - update \dec58_in2_sel $0\dec58_in2_sel[3:0] + sync init + update \jtag_wb_addrsr_update_core $1\jtag_wb_addrsr_update_core[0:0] end - attribute \src "libresoc.v:39843.3-39858.6" - process $proc$libresoc.v:39843$877 - assign { } { } + attribute \src "libresoc.v:127121.7-127121.45" + process $proc$libresoc.v:127121$5785 assign { } { } - assign $0\dec58_in3_sel[1:0] $1\dec58_in3_sel[1:0] - attribute \src "libresoc.v:39844.5-39844.29" - switch \initial - attribute \src "libresoc.v:39844.9-39844.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_in3_sel[1:0] 2'00 - case - assign $1\dec58_in3_sel[1:0] 2'00 - end + assign $1\jtag_wb_addrsr_update_core_prev[0:0] 1'0 sync always - update \dec58_in3_sel $0\dec58_in3_sel[1:0] + sync init + update \jtag_wb_addrsr_update_core_prev $1\jtag_wb_addrsr_update_core_prev[0:0] end - attribute \src "libresoc.v:39859.3-39874.6" - process $proc$libresoc.v:39859$878 + attribute \src "libresoc.v:127125.14-127125.54" + process $proc$libresoc.v:127125$5786 assign { } { } - assign { } { } - assign $0\dec58_out_sel[1:0] $1\dec58_out_sel[1:0] - attribute \src "libresoc.v:39860.5-39860.29" - switch \initial - attribute \src "libresoc.v:39860.9-39860.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_out_sel[1:0] 2'01 - case - assign $1\dec58_out_sel[1:0] 2'00 - end + assign $1\jtag_wb_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always - update \dec58_out_sel $0\dec58_out_sel[1:0] + sync init + update \jtag_wb_datasr__i $1\jtag_wb_datasr__i[63:0] end - attribute \src "libresoc.v:39875.3-39890.6" - process $proc$libresoc.v:39875$879 - assign { } { } + attribute \src "libresoc.v:127131.13-127131.38" + process $proc$libresoc.v:127131$5787 assign { } { } - assign $0\dec58_cr_in[2:0] $1\dec58_cr_in[2:0] - attribute \src "libresoc.v:39876.5-39876.29" - switch \initial - attribute \src "libresoc.v:39876.9-39876.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_cr_in[2:0] 3'000 - case - assign $1\dec58_cr_in[2:0] 3'000 - end + assign $1\jtag_wb_datasr__oe[1:0] 2'00 sync always - update \dec58_cr_in $0\dec58_cr_in[2:0] + sync init + update \jtag_wb_datasr__oe $1\jtag_wb_datasr__oe[1:0] end - attribute \src "libresoc.v:39891.3-39906.6" - process $proc$libresoc.v:39891$880 + attribute \src "libresoc.v:127139.14-127139.55" + process $proc$libresoc.v:127139$5788 assign { } { } + assign $1\jtag_wb_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \jtag_wb_datasr_reg $1\jtag_wb_datasr_reg[63:0] + end + attribute \src "libresoc.v:127147.7-127147.40" + process $proc$libresoc.v:127147$5789 assign { } { } - assign $0\dec58_cr_out[2:0] $1\dec58_cr_out[2:0] - attribute \src "libresoc.v:39892.5-39892.29" - switch \initial - attribute \src "libresoc.v:39892.9-39892.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_cr_out[2:0] 3'000 - case - assign $1\dec58_cr_out[2:0] 3'000 - end + assign $1\jtag_wb_datasr_update_core[0:0] 1'0 sync always - update \dec58_cr_out $0\dec58_cr_out[2:0] + sync init + update \jtag_wb_datasr_update_core $1\jtag_wb_datasr_update_core[0:0] end - connect \opcode_switch \opcode_in [1:0] -end -attribute \src "libresoc.v:39912.1-40483.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec62" -attribute \generator "nMigen" -module \dec62 - attribute \src "libresoc.v:40235.3-40247.6" - wire width 8 $0\dec62_asmcode[7:0] - attribute \src "libresoc.v:40287.3-40299.6" - wire $0\dec62_br[0:0] - attribute \src "libresoc.v:40456.3-40468.6" - wire width 3 $0\dec62_cr_in[2:0] - attribute \src "libresoc.v:40469.3-40481.6" - wire width 3 $0\dec62_cr_out[2:0] - attribute \src "libresoc.v:40222.3-40234.6" - wire width 2 $0\dec62_cry_in[1:0] - attribute \src "libresoc.v:40274.3-40286.6" - wire $0\dec62_cry_out[0:0] - attribute \src "libresoc.v:40391.3-40403.6" - wire width 5 $0\dec62_form[4:0] - attribute \src "libresoc.v:40170.3-40182.6" - wire width 12 $0\dec62_function_unit[11:0] - attribute \src "libresoc.v:40404.3-40416.6" - wire width 3 $0\dec62_in1_sel[2:0] - attribute \src "libresoc.v:40417.3-40429.6" - wire width 4 $0\dec62_in2_sel[3:0] - attribute \src "libresoc.v:40430.3-40442.6" - wire width 2 $0\dec62_in3_sel[1:0] - attribute \src "libresoc.v:40313.3-40325.6" - wire width 7 $0\dec62_internal_op[6:0] - attribute \src "libresoc.v:40248.3-40260.6" - wire $0\dec62_inv_a[0:0] - attribute \src "libresoc.v:40261.3-40273.6" - wire $0\dec62_inv_out[0:0] - attribute \src "libresoc.v:40339.3-40351.6" - wire $0\dec62_is_32b[0:0] - attribute \src "libresoc.v:40183.3-40195.6" - wire width 4 $0\dec62_ldst_len[3:0] - attribute \src "libresoc.v:40365.3-40377.6" - wire $0\dec62_lk[0:0] - attribute \src "libresoc.v:40443.3-40455.6" - wire width 2 $0\dec62_out_sel[1:0] - attribute \src "libresoc.v:40209.3-40221.6" - wire width 2 $0\dec62_rc_sel[1:0] - attribute \src "libresoc.v:40326.3-40338.6" - wire $0\dec62_rsrv[0:0] - attribute \src "libresoc.v:40378.3-40390.6" - wire $0\dec62_sgl_pipe[0:0] - attribute \src "libresoc.v:40352.3-40364.6" - wire $0\dec62_sgn[0:0] - attribute \src "libresoc.v:40300.3-40312.6" - wire $0\dec62_sgn_ext[0:0] - attribute \src "libresoc.v:40196.3-40208.6" - wire width 2 $0\dec62_upd[1:0] - attribute \src "libresoc.v:39913.7-39913.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:40235.3-40247.6" - wire width 8 $1\dec62_asmcode[7:0] - attribute \src "libresoc.v:40287.3-40299.6" - wire $1\dec62_br[0:0] - attribute \src "libresoc.v:40456.3-40468.6" - wire width 3 $1\dec62_cr_in[2:0] - attribute \src "libresoc.v:40469.3-40481.6" - wire width 3 $1\dec62_cr_out[2:0] - attribute \src "libresoc.v:40222.3-40234.6" - wire width 2 $1\dec62_cry_in[1:0] - attribute \src "libresoc.v:40274.3-40286.6" - wire $1\dec62_cry_out[0:0] - attribute \src "libresoc.v:40391.3-40403.6" - wire width 5 $1\dec62_form[4:0] - attribute \src "libresoc.v:40170.3-40182.6" - wire width 12 $1\dec62_function_unit[11:0] - attribute \src "libresoc.v:40404.3-40416.6" - wire width 3 $1\dec62_in1_sel[2:0] - attribute \src "libresoc.v:40417.3-40429.6" - wire width 4 $1\dec62_in2_sel[3:0] - attribute \src "libresoc.v:40430.3-40442.6" - wire width 2 $1\dec62_in3_sel[1:0] - attribute \src "libresoc.v:40313.3-40325.6" - wire width 7 $1\dec62_internal_op[6:0] - attribute \src "libresoc.v:40248.3-40260.6" - wire $1\dec62_inv_a[0:0] - attribute \src "libresoc.v:40261.3-40273.6" - wire $1\dec62_inv_out[0:0] - attribute \src "libresoc.v:40339.3-40351.6" - wire $1\dec62_is_32b[0:0] - attribute \src "libresoc.v:40183.3-40195.6" - wire width 4 $1\dec62_ldst_len[3:0] - attribute \src "libresoc.v:40365.3-40377.6" - wire $1\dec62_lk[0:0] - attribute \src "libresoc.v:40443.3-40455.6" - wire width 2 $1\dec62_out_sel[1:0] - attribute \src "libresoc.v:40209.3-40221.6" - wire width 2 $1\dec62_rc_sel[1:0] - attribute \src "libresoc.v:40326.3-40338.6" - wire $1\dec62_rsrv[0:0] - attribute \src "libresoc.v:40378.3-40390.6" - wire $1\dec62_sgl_pipe[0:0] - attribute \src "libresoc.v:40352.3-40364.6" - wire $1\dec62_sgn[0:0] - attribute \src "libresoc.v:40300.3-40312.6" - wire $1\dec62_sgn_ext[0:0] - attribute \src "libresoc.v:40196.3-40208.6" - wire width 2 $1\dec62_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec62_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec62_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec62_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec62_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec62_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec62_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec62_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec62_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec62_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec62_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec62_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec62_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec62_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec62_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec62_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec62_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec62_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec62_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec62_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec62_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec62_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec62_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec62_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec62_upd - attribute \src "libresoc.v:39913.7-39913.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 2 \opcode_switch - attribute \src "libresoc.v:39913.7-39913.20" - process $proc$libresoc.v:39913$906 + attribute \src "libresoc.v:127151.7-127151.45" + process $proc$libresoc.v:127151$5790 assign { } { } - assign $0\initial[0:0] 1'0 + assign $1\jtag_wb_datasr_update_core_prev[0:0] 1'0 sync always - update \initial $0\initial[0:0] sync init + update \jtag_wb_datasr_update_core_prev $1\jtag_wb_datasr_update_core_prev[0:0] end - attribute \src "libresoc.v:40170.3-40182.6" - process $proc$libresoc.v:40170$882 + attribute \src "libresoc.v:127581.7-127581.21" + process $proc$libresoc.v:127581$5791 assign { } { } + assign $1\sr0__oe[0:0] 1'0 + sync always + sync init + update \sr0__oe $1\sr0__oe[0:0] + end + attribute \src "libresoc.v:127589.13-127589.27" + process $proc$libresoc.v:127589$5792 assign { } { } - assign $0\dec62_function_unit[11:0] $1\dec62_function_unit[11:0] - attribute \src "libresoc.v:40171.5-40171.29" - switch \initial - attribute \src "libresoc.v:40171.9-40171.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_function_unit[11:0] 12'000000000100 - case - assign $1\dec62_function_unit[11:0] 12'000000000000 - end + assign $1\sr0_reg[2:0] 3'000 sync always - update \dec62_function_unit $0\dec62_function_unit[11:0] + sync init + update \sr0_reg $1\sr0_reg[2:0] end - attribute \src "libresoc.v:40183.3-40195.6" - process $proc$libresoc.v:40183$883 + attribute \src "libresoc.v:127597.7-127597.29" + process $proc$libresoc.v:127597$5793 assign { } { } + assign $1\sr0_update_core[0:0] 1'0 + sync always + sync init + update \sr0_update_core $1\sr0_update_core[0:0] + end + attribute \src "libresoc.v:127601.7-127601.34" + process $proc$libresoc.v:127601$5794 assign { } { } - assign $0\dec62_ldst_len[3:0] $1\dec62_ldst_len[3:0] - attribute \src "libresoc.v:40184.5-40184.29" - switch \initial - attribute \src "libresoc.v:40184.9-40184.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_ldst_len[3:0] 4'1000 - case - assign $1\dec62_ldst_len[3:0] 4'0000 - end + assign $1\sr0_update_core_prev[0:0] 1'0 sync always - update \dec62_ldst_len $0\dec62_ldst_len[3:0] + sync init + update \sr0_update_core_prev $1\sr0_update_core_prev[0:0] end - attribute \src "libresoc.v:40196.3-40208.6" - process $proc$libresoc.v:40196$884 + attribute \src "libresoc.v:127611.7-127611.21" + process $proc$libresoc.v:127611$5795 assign { } { } + assign $1\sr5__oe[0:0] 1'0 + sync always + sync init + update \sr5__oe $1\sr5__oe[0:0] + end + attribute \src "libresoc.v:127619.13-127619.27" + process $proc$libresoc.v:127619$5796 assign { } { } - assign $0\dec62_upd[1:0] $1\dec62_upd[1:0] - attribute \src "libresoc.v:40197.5-40197.29" - switch \initial - attribute \src "libresoc.v:40197.9-40197.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_upd[1:0] 2'01 - case - assign $1\dec62_upd[1:0] 2'00 - end + assign $1\sr5_reg[1:0] 2'00 sync always - update \dec62_upd $0\dec62_upd[1:0] + sync init + update \sr5_reg $1\sr5_reg[1:0] end - attribute \src "libresoc.v:40209.3-40221.6" - process $proc$libresoc.v:40209$885 + attribute \src "libresoc.v:127627.7-127627.29" + process $proc$libresoc.v:127627$5797 assign { } { } + assign $1\sr5_update_core[0:0] 1'0 + sync always + sync init + update \sr5_update_core $1\sr5_update_core[0:0] + end + attribute \src "libresoc.v:127631.7-127631.34" + process $proc$libresoc.v:127631$5798 assign { } { } - assign $0\dec62_rc_sel[1:0] $1\dec62_rc_sel[1:0] - attribute \src "libresoc.v:40210.5-40210.29" - switch \initial - attribute \src "libresoc.v:40210.9-40210.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_rc_sel[1:0] 2'00 - case - assign $1\dec62_rc_sel[1:0] 2'00 - end + assign $1\sr5_update_core_prev[0:0] 1'0 sync always - update \dec62_rc_sel $0\dec62_rc_sel[1:0] + sync init + update \sr5_update_core_prev $1\sr5_update_core_prev[0:0] end - attribute \src "libresoc.v:40222.3-40234.6" - process $proc$libresoc.v:40222$886 + attribute \src "libresoc.v:127636.7-127636.26" + process $proc$libresoc.v:127636$5799 assign { } { } + assign $1\wb_dcache_en[0:0] 1'1 + sync always + sync init + update \wb_dcache_en $1\wb_dcache_en[0:0] + end + attribute \src "libresoc.v:127641.7-127641.26" + process $proc$libresoc.v:127641$5800 assign { } { } - assign $0\dec62_cry_in[1:0] $1\dec62_cry_in[1:0] - attribute \src "libresoc.v:40223.5-40223.29" - switch \initial - attribute \src "libresoc.v:40223.9-40223.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_cry_in[1:0] 2'00 - case - assign $1\dec62_cry_in[1:0] 2'00 - end + assign $1\wb_icache_en[0:0] 1'1 sync always - update \dec62_cry_in $0\dec62_cry_in[1:0] + sync init + update \wb_icache_en $1\wb_icache_en[0:0] end - attribute \src "libresoc.v:40235.3-40247.6" - process $proc$libresoc.v:40235$887 + attribute \src "libresoc.v:127900.3-127901.41" + process $proc$libresoc.v:127900$5572 assign { } { } + assign $0\wb_icache_en[0:0] \wb_icache_en$next + sync posedge \clk + update \wb_icache_en $0\wb_icache_en[0:0] + end + attribute \src "libresoc.v:127902.3-127903.41" + process $proc$libresoc.v:127902$5573 assign { } { } - assign $0\dec62_asmcode[7:0] $1\dec62_asmcode[7:0] - attribute \src "libresoc.v:40236.5-40236.29" - switch \initial - attribute \src "libresoc.v:40236.9-40236.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_asmcode[7:0] 8'10101100 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_asmcode[7:0] 8'10101111 - case - assign $1\dec62_asmcode[7:0] 8'00000000 - end - sync always - update \dec62_asmcode $0\dec62_asmcode[7:0] + assign $0\wb_dcache_en[0:0] \wb_dcache_en$next + sync posedge \clk + update \wb_dcache_en $0\wb_dcache_en[0:0] end - attribute \src "libresoc.v:40248.3-40260.6" - process $proc$libresoc.v:40248$888 + attribute \src "libresoc.v:127904.3-127905.45" + process $proc$libresoc.v:127904$5574 assign { } { } + assign $0\dmi0_datasr__i[63:0] \dmi0_datasr__i$next + sync posedge \clk + update \dmi0_datasr__i $0\dmi0_datasr__i[63:0] + end + attribute \src "libresoc.v:127906.3-127907.35" + process $proc$libresoc.v:127906$5575 assign { } { } - assign $0\dec62_inv_a[0:0] $1\dec62_inv_a[0:0] - attribute \src "libresoc.v:40249.5-40249.29" - switch \initial - attribute \src "libresoc.v:40249.9-40249.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_inv_a[0:0] 1'0 - case - assign $1\dec62_inv_a[0:0] 1'0 - end - sync always - update \dec62_inv_a $0\dec62_inv_a[0:0] + assign $0\dmi0__din[63:0] \dmi0__din$next + sync posedge \clk + update \dmi0__din $0\dmi0__din[63:0] end - attribute \src "libresoc.v:40261.3-40273.6" - process $proc$libresoc.v:40261$889 + attribute \src "libresoc.v:127908.3-127909.45" + process $proc$libresoc.v:127908$5576 assign { } { } + assign $0\fsm_state$503[2:0]$5577 \fsm_state$503$next + sync posedge \clk + update \fsm_state$503 $0\fsm_state$503[2:0]$5577 + end + attribute \src "libresoc.v:127910.3-127911.41" + process $proc$libresoc.v:127910$5578 assign { } { } - assign $0\dec62_inv_out[0:0] $1\dec62_inv_out[0:0] - attribute \src "libresoc.v:40262.5-40262.29" - switch \initial - attribute \src "libresoc.v:40262.9-40262.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_inv_out[0:0] 1'0 - case - assign $1\dec62_inv_out[0:0] 1'0 - end - sync always - update \dec62_inv_out $0\dec62_inv_out[0:0] + assign $0\dmi0__addr_i[3:0] \dmi0__addr_i$next + sync posedge \clk + update \dmi0__addr_i $0\dmi0__addr_i[3:0] end - attribute \src "libresoc.v:40274.3-40286.6" - process $proc$libresoc.v:40274$890 + attribute \src "libresoc.v:127912.3-127913.51" + process $proc$libresoc.v:127912$5579 assign { } { } + assign $0\jtag_wb_datasr__i[63:0] \jtag_wb_datasr__i$next + sync posedge \clk + update \jtag_wb_datasr__i $0\jtag_wb_datasr__i[63:0] + end + attribute \src "libresoc.v:127914.3-127915.45" + process $proc$libresoc.v:127914$5580 assign { } { } - assign $0\dec62_cry_out[0:0] $1\dec62_cry_out[0:0] - attribute \src "libresoc.v:40275.5-40275.29" - switch \initial - attribute \src "libresoc.v:40275.9-40275.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_cry_out[0:0] 1'0 - case - assign $1\dec62_cry_out[0:0] 1'0 - end - sync always - update \dec62_cry_out $0\dec62_cry_out[0:0] + assign $0\jtag_wb__dat_w[63:0] \jtag_wb__dat_w$next + sync posedge \clk + update \jtag_wb__dat_w $0\jtag_wb__dat_w[63:0] end - attribute \src "libresoc.v:40287.3-40299.6" - process $proc$libresoc.v:40287$891 + attribute \src "libresoc.v:127916.3-127917.35" + process $proc$libresoc.v:127916$5581 assign { } { } + assign $0\fsm_state[2:0] \fsm_state$next + sync posedge \clk + update \fsm_state $0\fsm_state[2:0] + end + attribute \src "libresoc.v:127918.3-127919.41" + process $proc$libresoc.v:127918$5582 assign { } { } - assign $0\dec62_br[0:0] $1\dec62_br[0:0] - attribute \src "libresoc.v:40288.5-40288.29" - switch \initial - attribute \src "libresoc.v:40288.9-40288.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_br[0:0] 1'0 - case - assign $1\dec62_br[0:0] 1'0 - end - sync always - update \dec62_br $0\dec62_br[0:0] + assign $0\jtag_wb__adr[28:0] \jtag_wb__adr$next + sync posedge \clk + update \jtag_wb__adr $0\jtag_wb__adr[28:0] end - attribute \src "libresoc.v:40300.3-40312.6" - process $proc$libresoc.v:40300$892 + attribute \src "libresoc.v:127920.3-127921.31" + process $proc$libresoc.v:127920$5583 assign { } { } + assign $0\sr5_reg[1:0] \sr5_reg$next + sync posedge \posjtag_clk + update \sr5_reg $0\sr5_reg[1:0] + end + attribute \src "libresoc.v:127922.3-127923.31" + process $proc$libresoc.v:127922$5584 assign { } { } - assign $0\dec62_sgn_ext[0:0] $1\dec62_sgn_ext[0:0] - attribute \src "libresoc.v:40301.5-40301.29" - switch \initial - attribute \src "libresoc.v:40301.9-40301.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_sgn_ext[0:0] 1'0 - case - assign $1\dec62_sgn_ext[0:0] 1'0 - end - sync always - update \dec62_sgn_ext $0\dec62_sgn_ext[0:0] + assign $0\sr5__oe[0:0] \sr5__oe$next + sync posedge \clk + update \sr5__oe $0\sr5__oe[0:0] end - attribute \src "libresoc.v:40313.3-40325.6" - process $proc$libresoc.v:40313$893 + attribute \src "libresoc.v:127924.3-127925.57" + process $proc$libresoc.v:127924$5585 assign { } { } + assign $0\sr5_update_core_prev[0:0] \sr5_update_core_prev$next + sync posedge \clk + update \sr5_update_core_prev $0\sr5_update_core_prev[0:0] + end + attribute \src "libresoc.v:127926.3-127927.47" + process $proc$libresoc.v:127926$5586 assign { } { } - assign $0\dec62_internal_op[6:0] $1\dec62_internal_op[6:0] - attribute \src "libresoc.v:40314.5-40314.29" - switch \initial - attribute \src "libresoc.v:40314.9-40314.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_internal_op[6:0] 7'0100110 - case - assign $1\dec62_internal_op[6:0] 7'0000000 - end - sync always - update \dec62_internal_op $0\dec62_internal_op[6:0] + assign $0\sr5_update_core[0:0] \sr5_update_core$next + sync posedge \clk + update \sr5_update_core $0\sr5_update_core[0:0] end - attribute \src "libresoc.v:40326.3-40338.6" - process $proc$libresoc.v:40326$894 + attribute \src "libresoc.v:127928.3-127929.47" + process $proc$libresoc.v:127928$5587 assign { } { } + assign $0\dmi0_datasr_reg[63:0] \dmi0_datasr_reg$next + sync posedge \posjtag_clk + update \dmi0_datasr_reg $0\dmi0_datasr_reg[63:0] + end + attribute \src "libresoc.v:127930.3-127931.47" + process $proc$libresoc.v:127930$5588 assign { } { } - assign $0\dec62_rsrv[0:0] $1\dec62_rsrv[0:0] - attribute \src "libresoc.v:40327.5-40327.29" - switch \initial - attribute \src "libresoc.v:40327.9-40327.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_rsrv[0:0] 1'0 - case - assign $1\dec62_rsrv[0:0] 1'0 - end - sync always - update \dec62_rsrv $0\dec62_rsrv[0:0] + assign $0\dmi0_datasr__oe[1:0] \dmi0_datasr__oe$next + sync posedge \clk + update \dmi0_datasr__oe $0\dmi0_datasr__oe[1:0] end - attribute \src "libresoc.v:40339.3-40351.6" - process $proc$libresoc.v:40339$895 + attribute \src "libresoc.v:127932.3-127933.73" + process $proc$libresoc.v:127932$5589 assign { } { } + assign $0\dmi0_datasr_update_core_prev[0:0] \dmi0_datasr_update_core_prev$next + sync posedge \clk + update \dmi0_datasr_update_core_prev $0\dmi0_datasr_update_core_prev[0:0] + end + attribute \src "libresoc.v:127934.3-127935.63" + process $proc$libresoc.v:127934$5590 assign { } { } - assign $0\dec62_is_32b[0:0] $1\dec62_is_32b[0:0] - attribute \src "libresoc.v:40340.5-40340.29" - switch \initial - attribute \src "libresoc.v:40340.9-40340.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_is_32b[0:0] 1'0 - case - assign $1\dec62_is_32b[0:0] 1'0 - end - sync always - update \dec62_is_32b $0\dec62_is_32b[0:0] + assign $0\dmi0_datasr_update_core[0:0] \dmi0_datasr_update_core$next + sync posedge \clk + update \dmi0_datasr_update_core $0\dmi0_datasr_update_core[0:0] end - attribute \src "libresoc.v:40352.3-40364.6" - process $proc$libresoc.v:40352$896 + attribute \src "libresoc.v:127936.3-127937.47" + process $proc$libresoc.v:127936$5591 assign { } { } + assign $0\dmi0_addrsr_reg[7:0] \dmi0_addrsr_reg$next + sync posedge \posjtag_clk + update \dmi0_addrsr_reg $0\dmi0_addrsr_reg[7:0] + end + attribute \src "libresoc.v:127938.3-127939.47" + process $proc$libresoc.v:127938$5592 assign { } { } - assign $0\dec62_sgn[0:0] $1\dec62_sgn[0:0] - attribute \src "libresoc.v:40353.5-40353.29" - switch \initial - attribute \src "libresoc.v:40353.9-40353.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_sgn[0:0] 1'0 - case - assign $1\dec62_sgn[0:0] 1'0 - end - sync always - update \dec62_sgn $0\dec62_sgn[0:0] + assign $0\dmi0_addrsr__oe[0:0] \dmi0_addrsr__oe$next + sync posedge \clk + update \dmi0_addrsr__oe $0\dmi0_addrsr__oe[0:0] end - attribute \src "libresoc.v:40365.3-40377.6" - process $proc$libresoc.v:40365$897 + attribute \src "libresoc.v:127940.3-127941.73" + process $proc$libresoc.v:127940$5593 assign { } { } + assign $0\dmi0_addrsr_update_core_prev[0:0] \dmi0_addrsr_update_core_prev$next + sync posedge \clk + update \dmi0_addrsr_update_core_prev $0\dmi0_addrsr_update_core_prev[0:0] + end + attribute \src "libresoc.v:127942.3-127943.63" + process $proc$libresoc.v:127942$5594 assign { } { } - assign $0\dec62_lk[0:0] $1\dec62_lk[0:0] - attribute \src "libresoc.v:40366.5-40366.29" - switch \initial - attribute \src "libresoc.v:40366.9-40366.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_lk[0:0] 1'0 - case - assign $1\dec62_lk[0:0] 1'0 - end - sync always - update \dec62_lk $0\dec62_lk[0:0] + assign $0\dmi0_addrsr_update_core[0:0] \dmi0_addrsr_update_core$next + sync posedge \clk + update \dmi0_addrsr_update_core $0\dmi0_addrsr_update_core[0:0] end - attribute \src "libresoc.v:40378.3-40390.6" - process $proc$libresoc.v:40378$898 + attribute \src "libresoc.v:127944.3-127945.53" + process $proc$libresoc.v:127944$5595 assign { } { } + assign $0\jtag_wb_datasr_reg[63:0] \jtag_wb_datasr_reg$next + sync posedge \posjtag_clk + update \jtag_wb_datasr_reg $0\jtag_wb_datasr_reg[63:0] + end + attribute \src "libresoc.v:127946.3-127947.53" + process $proc$libresoc.v:127946$5596 assign { } { } - assign $0\dec62_sgl_pipe[0:0] $1\dec62_sgl_pipe[0:0] - attribute \src "libresoc.v:40379.5-40379.29" - switch \initial - attribute \src "libresoc.v:40379.9-40379.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_sgl_pipe[0:0] 1'1 - case - assign $1\dec62_sgl_pipe[0:0] 1'0 - end - sync always - update \dec62_sgl_pipe $0\dec62_sgl_pipe[0:0] + assign $0\jtag_wb_datasr__oe[1:0] \jtag_wb_datasr__oe$next + sync posedge \clk + update \jtag_wb_datasr__oe $0\jtag_wb_datasr__oe[1:0] end - attribute \src "libresoc.v:40391.3-40403.6" - process $proc$libresoc.v:40391$899 + attribute \src "libresoc.v:127948.3-127949.79" + process $proc$libresoc.v:127948$5597 assign { } { } + assign $0\jtag_wb_datasr_update_core_prev[0:0] \jtag_wb_datasr_update_core_prev$next + sync posedge \clk + update \jtag_wb_datasr_update_core_prev $0\jtag_wb_datasr_update_core_prev[0:0] + end + attribute \src "libresoc.v:127950.3-127951.69" + process $proc$libresoc.v:127950$5598 assign { } { } - assign $0\dec62_form[4:0] $1\dec62_form[4:0] - attribute \src "libresoc.v:40392.5-40392.29" - switch \initial - attribute \src "libresoc.v:40392.9-40392.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_form[4:0] 5'00101 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_form[4:0] 5'00101 - case - assign $1\dec62_form[4:0] 5'00000 - end - sync always - update \dec62_form $0\dec62_form[4:0] + assign $0\jtag_wb_datasr_update_core[0:0] \jtag_wb_datasr_update_core$next + sync posedge \clk + update \jtag_wb_datasr_update_core $0\jtag_wb_datasr_update_core[0:0] end - attribute \src "libresoc.v:40404.3-40416.6" - process $proc$libresoc.v:40404$900 + attribute \src "libresoc.v:127952.3-127953.53" + process $proc$libresoc.v:127952$5599 assign { } { } + assign $0\jtag_wb_addrsr_reg[28:0] \jtag_wb_addrsr_reg$next + sync posedge \posjtag_clk + update \jtag_wb_addrsr_reg $0\jtag_wb_addrsr_reg[28:0] + end + attribute \src "libresoc.v:127954.3-127955.53" + process $proc$libresoc.v:127954$5600 assign { } { } - assign $0\dec62_in1_sel[2:0] $1\dec62_in1_sel[2:0] - attribute \src "libresoc.v:40405.5-40405.29" - switch \initial - attribute \src "libresoc.v:40405.9-40405.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_in1_sel[2:0] 3'010 - case - assign $1\dec62_in1_sel[2:0] 3'000 - end - sync always - update \dec62_in1_sel $0\dec62_in1_sel[2:0] + assign $0\jtag_wb_addrsr__oe[0:0] \jtag_wb_addrsr__oe$next + sync posedge \clk + update \jtag_wb_addrsr__oe $0\jtag_wb_addrsr__oe[0:0] end - attribute \src "libresoc.v:40417.3-40429.6" - process $proc$libresoc.v:40417$901 + attribute \src "libresoc.v:127956.3-127957.79" + process $proc$libresoc.v:127956$5601 assign { } { } + assign $0\jtag_wb_addrsr_update_core_prev[0:0] \jtag_wb_addrsr_update_core_prev$next + sync posedge \clk + update \jtag_wb_addrsr_update_core_prev $0\jtag_wb_addrsr_update_core_prev[0:0] + end + attribute \src "libresoc.v:127958.3-127959.69" + process $proc$libresoc.v:127958$5602 assign { } { } - assign $0\dec62_in2_sel[3:0] $1\dec62_in2_sel[3:0] - attribute \src "libresoc.v:40418.5-40418.29" - switch \initial - attribute \src "libresoc.v:40418.9-40418.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_in2_sel[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_in2_sel[3:0] 4'1000 - case - assign $1\dec62_in2_sel[3:0] 4'0000 - end - sync always - update \dec62_in2_sel $0\dec62_in2_sel[3:0] + assign $0\jtag_wb_addrsr_update_core[0:0] \jtag_wb_addrsr_update_core$next + sync posedge \clk + update \jtag_wb_addrsr_update_core $0\jtag_wb_addrsr_update_core[0:0] + end + attribute \src "libresoc.v:127960.3-127961.31" + process $proc$libresoc.v:127960$5603 + assign { } { } + assign $0\sr0_reg[2:0] \sr0_reg$next + sync posedge \posjtag_clk + update \sr0_reg $0\sr0_reg[2:0] end - attribute \src "libresoc.v:40430.3-40442.6" - process $proc$libresoc.v:40430$902 + attribute \src "libresoc.v:127962.3-127963.31" + process $proc$libresoc.v:127962$5604 assign { } { } + assign $0\sr0__oe[0:0] \sr0__oe$next + sync posedge \clk + update \sr0__oe $0\sr0__oe[0:0] + end + attribute \src "libresoc.v:127964.3-127965.57" + process $proc$libresoc.v:127964$5605 assign { } { } - assign $0\dec62_in3_sel[1:0] $1\dec62_in3_sel[1:0] - attribute \src "libresoc.v:40431.5-40431.29" - switch \initial - attribute \src "libresoc.v:40431.9-40431.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_in3_sel[1:0] 2'01 - case - assign $1\dec62_in3_sel[1:0] 2'00 - end - sync always - update \dec62_in3_sel $0\dec62_in3_sel[1:0] + assign $0\sr0_update_core_prev[0:0] \sr0_update_core_prev$next + sync posedge \clk + update \sr0_update_core_prev $0\sr0_update_core_prev[0:0] + end + attribute \src "libresoc.v:127966.3-127967.47" + process $proc$libresoc.v:127966$5606 + assign { } { } + assign $0\sr0_update_core[0:0] \sr0_update_core$next + sync posedge \clk + update \sr0_update_core $0\sr0_update_core[0:0] end - attribute \src "libresoc.v:40443.3-40455.6" - process $proc$libresoc.v:40443$903 + attribute \src "libresoc.v:127968.3-127969.27" + process $proc$libresoc.v:127968$5607 assign { } { } + assign $0\io_bd[153:0] \io_bd$next + sync negedge \negjtag_clk + update \io_bd $0\io_bd[153:0] + end + attribute \src "libresoc.v:127970.3-127971.27" + process $proc$libresoc.v:127970$5608 assign { } { } - assign $0\dec62_out_sel[1:0] $1\dec62_out_sel[1:0] - attribute \src "libresoc.v:40444.5-40444.29" - switch \initial - attribute \src "libresoc.v:40444.9-40444.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_out_sel[1:0] 2'00 - case - assign $1\dec62_out_sel[1:0] 2'00 - end - sync always - update \dec62_out_sel $0\dec62_out_sel[1:0] + assign $0\io_sr[153:0] \io_sr$next + sync posedge \posjtag_clk + update \io_sr $0\io_sr[153:0] end - attribute \src "libresoc.v:40456.3-40468.6" - process $proc$libresoc.v:40456$904 + attribute \src "libresoc.v:128007.3-128022.6" + process $proc$libresoc.v:128007$5609 assign { } { } assign { } { } - assign $0\dec62_cr_in[2:0] $1\dec62_cr_in[2:0] - attribute \src "libresoc.v:40457.5-40457.29" + assign $0\TAP_tdo[0:0] $1\TAP_tdo[0:0] + attribute \src "libresoc.v:128008.5-128008.29" switch \initial - attribute \src "libresoc.v:40457.9-40457.17" + attribute \src "libresoc.v:128008.9-128008.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:415" + switch { \$369 \_idblock_select_id \_fsm_isir } attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 3'--1 assign { } { } - assign $1\dec62_cr_in[2:0] 3'000 + assign $1\TAP_tdo[0:0] \_irblock_tdo attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 3'-1- assign { } { } - assign $1\dec62_cr_in[2:0] 3'000 + assign $1\TAP_tdo[0:0] \_idblock_TAP_id_tdo + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $1\TAP_tdo[0:0] \io_sr [153] case - assign $1\dec62_cr_in[2:0] 3'000 + assign $1\TAP_tdo[0:0] 1'0 end sync always - update \dec62_cr_in $0\dec62_cr_in[2:0] + update \TAP_tdo $0\TAP_tdo[0:0] end - attribute \src "libresoc.v:40469.3-40481.6" - process $proc$libresoc.v:40469$905 + attribute \src "libresoc.v:128023.3-128031.6" + process $proc$libresoc.v:128023$5610 assign { } { } assign { } { } - assign $0\dec62_cr_out[2:0] $1\dec62_cr_out[2:0] - attribute \src "libresoc.v:40470.5-40470.29" + assign $0\sr0_update_core$next[0:0]$5611 $1\sr0_update_core$next[0:0]$5612 + attribute \src "libresoc.v:128024.5-128024.29" switch \initial - attribute \src "libresoc.v:40470.9-40470.17" + attribute \src "libresoc.v:128024.9-128024.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_cr_out[2:0] 3'000 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 1'1 assign { } { } - assign $1\dec62_cr_out[2:0] 3'000 + assign $1\sr0_update_core$next[0:0]$5612 1'0 case - assign $1\dec62_cr_out[2:0] 3'000 - end - sync always - update \dec62_cr_out $0\dec62_cr_out[2:0] - end - connect \opcode_switch \opcode_in [1:0] -end -attribute \src "libresoc.v:40487.1-40992.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a" -attribute \generator "nMigen" -module \dec_a - attribute \src "libresoc.v:40921.3-40956.6" - wire width 3 $0\fast_a[2:0] - attribute \src "libresoc.v:40921.3-40956.6" - wire $0\fast_a_ok[0:0] - attribute \src "libresoc.v:40488.7-40488.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:40889.3-40904.6" - wire width 5 $0\reg_a[4:0] - attribute \src "libresoc.v:40905.3-40920.6" - wire $0\reg_a_ok[0:0] - attribute \src "libresoc.v:40957.3-40967.6" - wire width 10 $0\spr[9:0] - attribute \src "libresoc.v:40979.3-40990.6" - wire width 10 $0\spr_a[9:0] - attribute \src "libresoc.v:40979.3-40990.6" - wire $0\spr_a_ok[0:0] - attribute \src "libresoc.v:40968.3-40978.6" - wire width 10 $0\sprmap_spr_i[9:0] - attribute \src "libresoc.v:40921.3-40956.6" - wire width 3 $1\fast_a[2:0] - attribute \src "libresoc.v:40921.3-40956.6" - wire $1\fast_a_ok[0:0] - attribute \src "libresoc.v:40889.3-40904.6" - wire width 5 $1\reg_a[4:0] - attribute \src "libresoc.v:40905.3-40920.6" - wire $1\reg_a_ok[0:0] - attribute \src "libresoc.v:40957.3-40967.6" - wire width 10 $1\spr[9:0] - attribute \src "libresoc.v:40979.3-40990.6" - wire width 10 $1\spr_a[9:0] - attribute \src "libresoc.v:40979.3-40990.6" - wire $1\spr_a_ok[0:0] - attribute \src "libresoc.v:40968.3-40978.6" - wire width 10 $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:40921.3-40956.6" - wire width 3 $2\fast_a[2:0] - attribute \src "libresoc.v:40921.3-40956.6" - wire $2\fast_a_ok[0:0] - attribute \src "libresoc.v:40889.3-40904.6" - wire width 5 $2\reg_a[4:0] - attribute \src "libresoc.v:40905.3-40920.6" - wire $2\reg_a_ok[0:0] - attribute \src "libresoc.v:40921.3-40956.6" - wire width 3 $3\fast_a[2:0] - attribute \src "libresoc.v:40921.3-40956.6" - wire $3\fast_a_ok[0:0] - attribute \src "libresoc.v:40873.18-40873.110" - wire $and$libresoc.v:40873$913_Y - attribute \src "libresoc.v:40878.18-40878.113" - wire $and$libresoc.v:40878$918_Y - attribute \src "libresoc.v:40881.17-40881.107" - wire $and$libresoc.v:40881$921_Y - attribute \src "libresoc.v:40868.18-40868.112" - wire $eq$libresoc.v:40868$908_Y - attribute \src "libresoc.v:40869.18-40869.112" - wire $eq$libresoc.v:40869$909_Y - attribute \src "libresoc.v:40870.18-40870.112" - wire $eq$libresoc.v:40870$910_Y - attribute \src "libresoc.v:40872.17-40872.111" - wire $eq$libresoc.v:40872$912_Y - attribute \src "libresoc.v:40875.18-40875.112" - wire $eq$libresoc.v:40875$915_Y - attribute \src "libresoc.v:40879.17-40879.111" - wire $eq$libresoc.v:40879$919_Y - attribute \src "libresoc.v:40871.18-40871.109" - wire $ne$libresoc.v:40871$911_Y - attribute \src "libresoc.v:40880.17-40880.108" - wire $ne$libresoc.v:40880$920_Y - attribute \src "libresoc.v:40876.18-40876.105" - wire $not$libresoc.v:40876$916_Y - attribute \src "libresoc.v:40877.18-40877.108" - wire $not$libresoc.v:40877$917_Y - attribute \src "libresoc.v:40867.17-40867.107" - wire $or$libresoc.v:40867$907_Y - attribute \src "libresoc.v:40874.18-40874.110" - wire $or$libresoc.v:40874$914_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" - wire \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" - wire \$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:119" - wire \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" - wire \$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 10 \BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 9 \RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 8 \RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 10 input 11 \SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 input 12 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 output 6 \fast_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 7 \fast_a_ok - attribute \src "libresoc.v:40488.7-40488.15" - wire \initial - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 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attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 13 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parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \XL_XO [9] - connect \B \$27 - connect \Y $and$libresoc.v:40878$918_Y + attribute \src "libresoc.v:128032.3-128040.6" + process $proc$libresoc.v:128032$5613 + assign { } { } + assign { } { } + assign $0\sr0_update_core_prev$next[0:0]$5614 $1\sr0_update_core_prev$next[0:0]$5615 + attribute \src "libresoc.v:128033.5-128033.29" + switch \initial + attribute \src "libresoc.v:128033.9-128033.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr0_update_core_prev$next[0:0]$5615 1'0 + case + assign $1\sr0_update_core_prev$next[0:0]$5615 \sr0_update_core + end + sync always + update \sr0_update_core_prev$next $0\sr0_update_core_prev$next[0:0]$5614 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" - cell $and $and$libresoc.v:40881$921 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \$5 - connect \Y $and$libresoc.v:40881$921_Y + attribute \src "libresoc.v:128041.3-128057.6" + process $proc$libresoc.v:128041$5616 + assign { } { } + assign { } { } + assign $0\sr0__oe$next[0:0]$5617 $2\sr0__oe$next[0:0]$5619 + attribute \src "libresoc.v:128042.5-128042.29" + switch \initial + attribute \src "libresoc.v:128042.9-128042.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$387 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr0__oe$next[0:0]$5618 \sr0_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\sr0__oe$next[0:0]$5618 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sr0__oe$next[0:0]$5619 1'0 + case + assign $2\sr0__oe$next[0:0]$5619 $1\sr0__oe$next[0:0]$5618 + end + sync always + update \sr0__oe$next $0\sr0__oe$next[0:0]$5617 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109" - cell $eq $eq$libresoc.v:40868$908 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'100 - connect \Y $eq$libresoc.v:40868$908_Y + attribute \src "libresoc.v:128058.3-128078.6" + process $proc$libresoc.v:128058$5620 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sr0_reg$next[2:0]$5621 $3\sr0_reg$next[2:0]$5624 + attribute \src "libresoc.v:128059.5-128059.29" + switch \initial + attribute \src "libresoc.v:128059.9-128059.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \sr0_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr0_reg$next[2:0]$5622 { \TAP_bus__tdi \sr0_reg [2:1] } + case + assign $1\sr0_reg$next[2:0]$5622 \sr0_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \sr0_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sr0_reg$next[2:0]$5623 \sr0__i + case + assign $2\sr0_reg$next[2:0]$5623 $1\sr0_reg$next[2:0]$5622 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\sr0_reg$next[2:0]$5624 3'000 + case + assign $3\sr0_reg$next[2:0]$5624 $2\sr0_reg$next[2:0]$5623 + end + sync always + update \sr0_reg$next $0\sr0_reg$next[2:0]$5621 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102" - cell $eq $eq$libresoc.v:40869$909 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'001 - connect \Y $eq$libresoc.v:40869$909_Y + attribute \src "libresoc.v:128079.3-128087.6" + process $proc$libresoc.v:128079$5625 + assign { } { } + assign { } { } + assign $0\jtag_wb_addrsr_update_core$next[0:0]$5626 $1\jtag_wb_addrsr_update_core$next[0:0]$5627 + attribute \src "libresoc.v:128080.5-128080.29" + switch \initial + attribute \src "libresoc.v:128080.9-128080.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_addrsr_update_core$next[0:0]$5627 1'0 + case + assign $1\jtag_wb_addrsr_update_core$next[0:0]$5627 \jtag_wb_addrsr_update + end + sync always + update \jtag_wb_addrsr_update_core$next $0\jtag_wb_addrsr_update_core$next[0:0]$5626 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103" - cell $eq $eq$libresoc.v:40870$910 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'010 - connect \Y $eq$libresoc.v:40870$910_Y + attribute \src "libresoc.v:128088.3-128096.6" + process $proc$libresoc.v:128088$5628 + assign { } { } + assign { } { } + assign $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5629 $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5630 + attribute \src "libresoc.v:128089.5-128089.29" + switch \initial + attribute \src "libresoc.v:128089.9-128089.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5630 1'0 + case + assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5630 \jtag_wb_addrsr_update_core + end + sync always + update \jtag_wb_addrsr_update_core_prev$next $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5629 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102" - cell $eq $eq$libresoc.v:40872$912 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'001 - connect \Y $eq$libresoc.v:40872$912_Y + attribute \src "libresoc.v:128097.3-128113.6" + process $proc$libresoc.v:128097$5631 + assign { } { } + assign { } { } + assign $0\jtag_wb_addrsr__oe$next[0:0]$5632 $2\jtag_wb_addrsr__oe$next[0:0]$5634 + attribute \src "libresoc.v:128098.5-128098.29" + switch \initial + attribute \src "libresoc.v:128098.9-128098.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$405 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_addrsr__oe$next[0:0]$5633 \jtag_wb_addrsr_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\jtag_wb_addrsr__oe$next[0:0]$5633 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_addrsr__oe$next[0:0]$5634 1'0 + case + assign $2\jtag_wb_addrsr__oe$next[0:0]$5634 $1\jtag_wb_addrsr__oe$next[0:0]$5633 + end + sync always + update \jtag_wb_addrsr__oe$next $0\jtag_wb_addrsr__oe$next[0:0]$5632 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109" - cell $eq $eq$libresoc.v:40875$915 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'100 - connect \Y $eq$libresoc.v:40875$915_Y + attribute \src "libresoc.v:128114.3-128134.6" + process $proc$libresoc.v:128114$5635 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb_addrsr_reg$next[28:0]$5636 $3\jtag_wb_addrsr_reg$next[28:0]$5639 + attribute \src "libresoc.v:128115.5-128115.29" + switch \initial + attribute \src "libresoc.v:128115.9-128115.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \jtag_wb_addrsr_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_addrsr_reg$next[28:0]$5637 { \TAP_bus__tdi \jtag_wb_addrsr_reg [28:1] } + case + assign $1\jtag_wb_addrsr_reg$next[28:0]$5637 \jtag_wb_addrsr_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \jtag_wb_addrsr_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_addrsr_reg$next[28:0]$5638 \jtag_wb_addrsr__i + case + assign $2\jtag_wb_addrsr_reg$next[28:0]$5638 $1\jtag_wb_addrsr_reg$next[28:0]$5637 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb_addrsr_reg$next[28:0]$5639 29'00000000000000000000000000000 + case + assign $3\jtag_wb_addrsr_reg$next[28:0]$5639 $2\jtag_wb_addrsr_reg$next[28:0]$5638 + end + sync always + update \jtag_wb_addrsr_reg$next $0\jtag_wb_addrsr_reg$next[28:0]$5636 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103" - cell $eq $eq$libresoc.v:40879$919 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'010 - connect \Y $eq$libresoc.v:40879$919_Y + attribute \src "libresoc.v:128135.3-128143.6" + process $proc$libresoc.v:128135$5640 + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr_update_core$next[0:0]$5641 $1\jtag_wb_datasr_update_core$next[0:0]$5642 + attribute \src "libresoc.v:128136.5-128136.29" + switch \initial + attribute \src "libresoc.v:128136.9-128136.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_datasr_update_core$next[0:0]$5642 1'0 + case + assign $1\jtag_wb_datasr_update_core$next[0:0]$5642 \jtag_wb_datasr_update + end + sync always + update \jtag_wb_datasr_update_core$next $0\jtag_wb_datasr_update_core$next[0:0]$5641 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" - cell $ne $ne$libresoc.v:40871$911 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \ra - connect \B 5'00000 - connect \Y $ne$libresoc.v:40871$911_Y + attribute \src "libresoc.v:128144.3-128152.6" + process $proc$libresoc.v:128144$5643 + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr_update_core_prev$next[0:0]$5644 $1\jtag_wb_datasr_update_core_prev$next[0:0]$5645 + attribute \src "libresoc.v:128145.5-128145.29" + switch \initial + attribute \src "libresoc.v:128145.9-128145.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5645 1'0 + case + assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5645 \jtag_wb_datasr_update_core + end + sync always + update \jtag_wb_datasr_update_core_prev$next $0\jtag_wb_datasr_update_core_prev$next[0:0]$5644 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" - cell $ne $ne$libresoc.v:40880$920 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \ra - connect \B 5'00000 - connect \Y $ne$libresoc.v:40880$920_Y + attribute \src "libresoc.v:128153.3-128169.6" + process $proc$libresoc.v:128153$5646 + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr__oe$next[1:0]$5647 $2\jtag_wb_datasr__oe$next[1:0]$5649 + attribute \src "libresoc.v:128154.5-128154.29" + switch \initial + attribute \src "libresoc.v:128154.9-128154.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$425 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_datasr__oe$next[1:0]$5648 \jtag_wb_datasr_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\jtag_wb_datasr__oe$next[1:0]$5648 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_datasr__oe$next[1:0]$5649 2'00 + case + assign $2\jtag_wb_datasr__oe$next[1:0]$5649 $1\jtag_wb_datasr__oe$next[1:0]$5648 + end + sync always + update \jtag_wb_datasr__oe$next $0\jtag_wb_datasr__oe$next[1:0]$5647 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:119" - cell $not $not$libresoc.v:40876$916 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \BO [2] - connect \Y $not$libresoc.v:40876$916_Y + attribute \src "libresoc.v:128170.3-128190.6" + process $proc$libresoc.v:128170$5650 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr_reg$next[63:0]$5651 $3\jtag_wb_datasr_reg$next[63:0]$5654 + attribute \src "libresoc.v:128171.5-128171.29" + switch \initial + attribute \src "libresoc.v:128171.9-128171.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \jtag_wb_datasr_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_datasr_reg$next[63:0]$5652 { \TAP_bus__tdi \jtag_wb_datasr_reg [63:1] } + case + assign $1\jtag_wb_datasr_reg$next[63:0]$5652 \jtag_wb_datasr_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \jtag_wb_datasr_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_datasr_reg$next[63:0]$5653 \jtag_wb_datasr__i + case + assign $2\jtag_wb_datasr_reg$next[63:0]$5653 $1\jtag_wb_datasr_reg$next[63:0]$5652 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb_datasr_reg$next[63:0]$5654 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\jtag_wb_datasr_reg$next[63:0]$5654 $2\jtag_wb_datasr_reg$next[63:0]$5653 + end + sync always + update \jtag_wb_datasr_reg$next $0\jtag_wb_datasr_reg$next[63:0]$5651 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" - cell $not $not$libresoc.v:40877$917 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \XL_XO [5] - connect \Y $not$libresoc.v:40877$917_Y + attribute \src "libresoc.v:128191.3-128199.6" + process $proc$libresoc.v:128191$5655 + assign { } { } + assign { } { } + assign $0\dmi0_addrsr_update_core$next[0:0]$5656 $1\dmi0_addrsr_update_core$next[0:0]$5657 + attribute \src "libresoc.v:128192.5-128192.29" + switch \initial + attribute \src "libresoc.v:128192.9-128192.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_addrsr_update_core$next[0:0]$5657 1'0 + case + assign $1\dmi0_addrsr_update_core$next[0:0]$5657 \dmi0_addrsr_update + end + sync always + update \dmi0_addrsr_update_core$next $0\dmi0_addrsr_update_core$next[0:0]$5656 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" - cell $or $or$libresoc.v:40867$907 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \$7 - connect \Y $or$libresoc.v:40867$907_Y + attribute \src "libresoc.v:128200.3-128208.6" + process $proc$libresoc.v:128200$5658 + assign { } { } + assign { } { } + assign $0\dmi0_addrsr_update_core_prev$next[0:0]$5659 $1\dmi0_addrsr_update_core_prev$next[0:0]$5660 + attribute \src "libresoc.v:128201.5-128201.29" + switch \initial + attribute \src "libresoc.v:128201.9-128201.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_addrsr_update_core_prev$next[0:0]$5660 1'0 + case + assign $1\dmi0_addrsr_update_core_prev$next[0:0]$5660 \dmi0_addrsr_update_core + end + sync always + update \dmi0_addrsr_update_core_prev$next $0\dmi0_addrsr_update_core_prev$next[0:0]$5659 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" - cell $or $or$libresoc.v:40874$914 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$13 - connect \B \$19 - connect \Y $or$libresoc.v:40874$914_Y + attribute \src "libresoc.v:128209.3-128225.6" + process $proc$libresoc.v:128209$5661 + assign { } { } + assign { } { } + assign $0\dmi0_addrsr__oe$next[0:0]$5662 $2\dmi0_addrsr__oe$next[0:0]$5664 + attribute \src "libresoc.v:128210.5-128210.29" + switch \initial + attribute \src "libresoc.v:128210.9-128210.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$443 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_addrsr__oe$next[0:0]$5663 \dmi0_addrsr_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\dmi0_addrsr__oe$next[0:0]$5663 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_addrsr__oe$next[0:0]$5664 1'0 + case + assign $2\dmi0_addrsr__oe$next[0:0]$5664 $1\dmi0_addrsr__oe$next[0:0]$5663 + end + sync always + update \dmi0_addrsr__oe$next $0\dmi0_addrsr__oe$next[0:0]$5662 end - attribute \module_not_derived 1 - attribute \src "libresoc.v:40882.10-40888.4" - cell \sprmap \sprmap - connect \fast_o \sprmap_fast_o - connect \fast_o_ok \sprmap_fast_o_ok - connect \spr_i \sprmap_spr_i - connect \spr_o \sprmap_spr_o - connect \spr_o_ok \sprmap_spr_o_ok + attribute \src "libresoc.v:128226.3-128246.6" + process $proc$libresoc.v:128226$5665 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0_addrsr_reg$next[7:0]$5666 $3\dmi0_addrsr_reg$next[7:0]$5669 + attribute \src "libresoc.v:128227.5-128227.29" + switch \initial + attribute \src "libresoc.v:128227.9-128227.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \dmi0_addrsr_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_addrsr_reg$next[7:0]$5667 { \TAP_bus__tdi \dmi0_addrsr_reg [7:1] } + case + assign $1\dmi0_addrsr_reg$next[7:0]$5667 \dmi0_addrsr_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \dmi0_addrsr_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_addrsr_reg$next[7:0]$5668 \dmi0_addrsr__i + case + assign $2\dmi0_addrsr_reg$next[7:0]$5668 $1\dmi0_addrsr_reg$next[7:0]$5667 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0_addrsr_reg$next[7:0]$5669 8'00000000 + case + assign $3\dmi0_addrsr_reg$next[7:0]$5669 $2\dmi0_addrsr_reg$next[7:0]$5668 + end + sync always + update \dmi0_addrsr_reg$next $0\dmi0_addrsr_reg$next[7:0]$5666 end - attribute \src "libresoc.v:40488.7-40488.20" - process $proc$libresoc.v:40488$928 + attribute \src "libresoc.v:128247.3-128255.6" + process $proc$libresoc.v:128247$5670 assign { } { } - assign $0\initial[0:0] 1'0 + assign { } { } + assign $0\dmi0_datasr_update_core$next[0:0]$5671 $1\dmi0_datasr_update_core$next[0:0]$5672 + attribute \src "libresoc.v:128248.5-128248.29" + switch \initial + attribute \src "libresoc.v:128248.9-128248.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_datasr_update_core$next[0:0]$5672 1'0 + case + assign $1\dmi0_datasr_update_core$next[0:0]$5672 \dmi0_datasr_update + end sync always - update \initial $0\initial[0:0] - sync init + update \dmi0_datasr_update_core$next $0\dmi0_datasr_update_core$next[0:0]$5671 end - attribute \src "libresoc.v:40889.3-40904.6" - process $proc$libresoc.v:40889$922 + attribute \src "libresoc.v:128256.3-128264.6" + process $proc$libresoc.v:128256$5673 assign { } { } + assign { } { } + assign $0\dmi0_datasr_update_core_prev$next[0:0]$5674 $1\dmi0_datasr_update_core_prev$next[0:0]$5675 + attribute \src "libresoc.v:128257.5-128257.29" + switch \initial + attribute \src "libresoc.v:128257.9-128257.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_datasr_update_core_prev$next[0:0]$5675 1'0 + case + assign $1\dmi0_datasr_update_core_prev$next[0:0]$5675 \dmi0_datasr_update_core + end + sync always + update \dmi0_datasr_update_core_prev$next $0\dmi0_datasr_update_core_prev$next[0:0]$5674 + end + attribute \src "libresoc.v:128265.3-128281.6" + process $proc$libresoc.v:128265$5676 assign { } { } assign { } { } - assign $0\reg_a[4:0] $2\reg_a[4:0] - attribute \src "libresoc.v:40890.5-40890.29" + assign $0\dmi0_datasr__oe$next[1:0]$5677 $2\dmi0_datasr__oe$next[1:0]$5679 + attribute \src "libresoc.v:128266.5-128266.29" switch \initial - attribute \src "libresoc.v:40890.9-40890.17" + attribute \src "libresoc.v:128266.9-128266.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" - switch \$9 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$463 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg_a[4:0] \ra + assign $1\dmi0_datasr__oe$next[1:0]$5678 \dmi0_datasr_isir + attribute \src "libresoc.v:0.0-0.0" case - assign $1\reg_a[4:0] 5'00000 + assign { } { } + assign $1\dmi0_datasr__oe$next[1:0]$5678 2'00 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109" - switch \$11 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg_a[4:0] \RS + assign $2\dmi0_datasr__oe$next[1:0]$5679 2'00 case - assign $2\reg_a[4:0] $1\reg_a[4:0] + assign $2\dmi0_datasr__oe$next[1:0]$5679 $1\dmi0_datasr__oe$next[1:0]$5678 end sync always - update \reg_a $0\reg_a[4:0] + update \dmi0_datasr__oe$next $0\dmi0_datasr__oe$next[1:0]$5677 end - attribute \src "libresoc.v:40905.3-40920.6" - process $proc$libresoc.v:40905$923 + attribute \src "libresoc.v:128282.3-128302.6" + process $proc$libresoc.v:128282$5680 assign { } { } assign { } { } assign { } { } - assign $0\reg_a_ok[0:0] $2\reg_a_ok[0:0] - attribute \src "libresoc.v:40906.5-40906.29" + assign { } { } + assign $0\dmi0_datasr_reg$next[63:0]$5681 $3\dmi0_datasr_reg$next[63:0]$5684 + attribute \src "libresoc.v:128283.5-128283.29" switch \initial - attribute \src "libresoc.v:40906.9-40906.17" + attribute \src "libresoc.v:128283.9-128283.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" - switch \$21 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \dmi0_datasr_shift attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg_a_ok[0:0] 1'1 + assign $1\dmi0_datasr_reg$next[63:0]$5682 { \TAP_bus__tdi \dmi0_datasr_reg [63:1] } case - assign $1\reg_a_ok[0:0] 1'0 + assign $1\dmi0_datasr_reg$next[63:0]$5682 \dmi0_datasr_reg end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109" - switch \$23 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \dmi0_datasr_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg_a_ok[0:0] 1'1 + assign $2\dmi0_datasr_reg$next[63:0]$5683 \dmi0_datasr__i case - assign $2\reg_a_ok[0:0] $1\reg_a_ok[0:0] + assign $2\dmi0_datasr_reg$next[63:0]$5683 $1\dmi0_datasr_reg$next[63:0]$5682 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0_datasr_reg$next[63:0]$5684 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dmi0_datasr_reg$next[63:0]$5684 $2\dmi0_datasr_reg$next[63:0]$5683 end sync always - update \reg_a_ok $0\reg_a_ok[0:0] + update \dmi0_datasr_reg$next $0\dmi0_datasr_reg$next[63:0]$5681 end - attribute \src "libresoc.v:40921.3-40956.6" - process $proc$libresoc.v:40921$924 + attribute \src "libresoc.v:128303.3-128311.6" + process $proc$libresoc.v:128303$5685 assign { } { } assign { } { } + assign $0\sr5_update_core$next[0:0]$5686 $1\sr5_update_core$next[0:0]$5687 + attribute \src "libresoc.v:128304.5-128304.29" + switch \initial + attribute \src "libresoc.v:128304.9-128304.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr5_update_core$next[0:0]$5687 1'0 + case + assign $1\sr5_update_core$next[0:0]$5687 \sr5_update + end + sync always + update \sr5_update_core$next $0\sr5_update_core$next[0:0]$5686 + end + attribute \src "libresoc.v:128312.3-128320.6" + process $proc$libresoc.v:128312$5688 assign { } { } assign { } { } - assign $0\fast_a[2:0] $1\fast_a[2:0] - assign $0\fast_a_ok[0:0] $1\fast_a_ok[0:0] - attribute \src "libresoc.v:40922.5-40922.29" + assign $0\sr5_update_core_prev$next[0:0]$5689 $1\sr5_update_core_prev$next[0:0]$5690 + attribute \src "libresoc.v:128313.5-128313.29" switch \initial - attribute \src "libresoc.v:40922.9-40922.17" + attribute \src "libresoc.v:128313.9-128313.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115" - switch \internal_op + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" - case 7'0000111 + case 1'1 assign { } { } + assign $1\sr5_update_core_prev$next[0:0]$5690 1'0 + case + assign $1\sr5_update_core_prev$next[0:0]$5690 \sr5_update_core + end + sync always + update \sr5_update_core_prev$next $0\sr5_update_core_prev$next[0:0]$5689 + end + attribute \src "libresoc.v:128321.3-128337.6" + process $proc$libresoc.v:128321$5691 + assign { } { } + assign { } { } + assign $0\sr5__oe$next[0:0]$5692 $2\sr5__oe$next[0:0]$5694 + attribute \src "libresoc.v:128322.5-128322.29" + switch \initial + attribute \src "libresoc.v:128322.9-128322.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$481 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $1\fast_a[2:0] $2\fast_a[2:0] - assign $1\fast_a_ok[0:0] $2\fast_a_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:119" - switch \$25 + assign $1\sr5__oe$next[0:0]$5693 \sr5_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\sr5__oe$next[0:0]$5693 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sr5__oe$next[0:0]$5694 1'0 + case + assign $2\sr5__oe$next[0:0]$5694 $1\sr5__oe$next[0:0]$5693 + end + sync always + update \sr5__oe$next $0\sr5__oe$next[0:0]$5692 + end + attribute \src "libresoc.v:128338.3-128358.6" + process $proc$libresoc.v:128338$5695 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sr5_reg$next[1:0]$5696 $3\sr5_reg$next[1:0]$5699 + attribute \src "libresoc.v:128339.5-128339.29" + switch \initial + attribute \src "libresoc.v:128339.9-128339.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \sr5_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr5_reg$next[1:0]$5697 { \TAP_bus__tdi \sr5_reg [1] } + case + assign $1\sr5_reg$next[1:0]$5697 \sr5_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \sr5_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sr5_reg$next[1:0]$5698 \sr5__i + case + assign $2\sr5_reg$next[1:0]$5698 $1\sr5_reg$next[1:0]$5697 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\sr5_reg$next[1:0]$5699 2'00 + case + assign $3\sr5_reg$next[1:0]$5699 $2\sr5_reg$next[1:0]$5698 + end + sync always + update \sr5_reg$next $0\sr5_reg$next[1:0]$5696 + end + attribute \src "libresoc.v:128359.3-128385.6" + process $proc$libresoc.v:128359$5700 + assign { } { } + assign $0\TAP_bus__tdo[0:0] $1\TAP_bus__tdo[0:0] + attribute \src "libresoc.v:128360.5-128360.29" + switch \initial + attribute \src "libresoc.v:128360.9-128360.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:685" + switch { \sr5_shift \dmi0_datasr_shift \dmi0_addrsr_shift \jtag_wb_datasr_shift \jtag_wb_addrsr_shift \sr0_shift } + attribute \src "libresoc.v:0.0-0.0" + case 6'-----1 + assign { } { } + assign $1\TAP_bus__tdo[0:0] \sr0_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 6'----1- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \jtag_wb_addrsr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 6'---1-- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \jtag_wb_datasr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 6'--1--- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \dmi0_addrsr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 6'-1---- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \dmi0_datasr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 6'1----- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \sr5_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\TAP_bus__tdo[0:0] \TAP_tdo + end + sync always + update \TAP_bus__tdo $0\TAP_bus__tdo[0:0] + end + attribute \src "libresoc.v:128386.3-128418.6" + process $proc$libresoc.v:128386$5701 + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb__adr$next[28:0]$5702 $4\jtag_wb__adr$next[28:0]$5706 + attribute \src "libresoc.v:128387.5-128387.29" + switch \initial + attribute \src "libresoc.v:128387.9-128387.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\jtag_wb__adr$next[28:0]$5703 $2\jtag_wb__adr$next[28:0]$5704 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" + switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\jtag_wb__adr$next[28:0]$5704 \jtag_wb_addrsr__o + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\jtag_wb__adr$next[28:0]$5704 \$495 [28:0] + case + assign $2\jtag_wb__adr$next[28:0]$5704 \jtag_wb__adr + end + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\jtag_wb__adr$next[28:0]$5703 $3\jtag_wb__adr$next[28:0]$5705 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" + switch \jtag_wb__ack attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } + assign $3\jtag_wb__adr$next[28:0]$5705 \$498 [28:0] + case + assign $3\jtag_wb__adr$next[28:0]$5705 \jtag_wb__adr + end + case + assign $1\jtag_wb__adr$next[28:0]$5703 \jtag_wb__adr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\jtag_wb__adr$next[28:0]$5706 29'00000000000000000000000000000 + case + assign $4\jtag_wb__adr$next[28:0]$5706 $1\jtag_wb__adr$next[28:0]$5703 + end + sync always + update \jtag_wb__adr$next $0\jtag_wb__adr$next[28:0]$5702 + end + attribute \src "libresoc.v:128419.3-128471.6" + process $proc$libresoc.v:128419$5707 + assign { } { } + assign { } { } + assign { } { } + assign $0\fsm_state$next[2:0]$5708 $5\fsm_state$next[2:0]$5713 + attribute \src "libresoc.v:128420.5-128420.29" + switch \initial + attribute \src "libresoc.v:128420.9-128420.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\fsm_state$next[2:0]$5709 $2\fsm_state$next[2:0]$5710 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" + switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 assign { } { } - assign $2\fast_a[2:0] 3'000 - assign $2\fast_a_ok[0:0] 1'1 + assign $2\fsm_state$next[2:0]$5710 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\fsm_state$next[2:0]$5710 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\fsm_state$next[2:0]$5710 3'010 case - assign $2\fast_a[2:0] 3'000 - assign $2\fast_a_ok[0:0] 1'0 + assign $2\fsm_state$next[2:0]$5710 \fsm_state end attribute \src "libresoc.v:0.0-0.0" - case 7'0001000 + case 3'001 assign { } { } + assign $1\fsm_state$next[2:0]$5709 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 assign { } { } - assign $1\fast_a[2:0] $3\fast_a[2:0] - assign $1\fast_a_ok[0:0] $3\fast_a_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" - switch \$29 + assign $1\fsm_state$next[2:0]$5709 $3\fsm_state$next[2:0]$5711 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" + switch \jtag_wb__ack attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign { } { } - assign $3\fast_a[2:0] 3'000 - assign $3\fast_a_ok[0:0] 1'1 + assign $3\fsm_state$next[2:0]$5711 3'000 case - assign $3\fast_a[2:0] 3'000 - assign $3\fast_a_ok[0:0] 1'0 + assign $3\fsm_state$next[2:0]$5711 \fsm_state end attribute \src "libresoc.v:0.0-0.0" - case 7'0101110 + case 3'010 assign { } { } + assign $1\fsm_state$next[2:0]$5709 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 assign { } { } - assign { $1\fast_a_ok[0:0] $1\fast_a[2:0] } { \sprmap_fast_o_ok \sprmap_fast_o } + assign $1\fsm_state$next[2:0]$5709 $4\fsm_state$next[2:0]$5712 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$next[2:0]$5712 3'001 + case + assign $4\fsm_state$next[2:0]$5712 \fsm_state + end case - assign $1\fast_a[2:0] 3'000 - assign $1\fast_a_ok[0:0] 1'0 + assign $1\fsm_state$next[2:0]$5709 \fsm_state + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fsm_state$next[2:0]$5713 3'000 + case + assign $5\fsm_state$next[2:0]$5713 $1\fsm_state$next[2:0]$5709 end sync always - update \fast_a $0\fast_a[2:0] - update \fast_a_ok $0\fast_a_ok[0:0] + update \fsm_state$next $0\fsm_state$next[2:0]$5708 end - attribute \src "libresoc.v:40957.3-40967.6" - process $proc$libresoc.v:40957$925 + attribute \src "libresoc.v:128472.3-128498.6" + process $proc$libresoc.v:128472$5714 assign { } { } assign { } { } - assign $0\spr[9:0] $1\spr[9:0] - attribute \src "libresoc.v:40958.5-40958.29" + assign { } { } + assign $0\jtag_wb__dat_w$next[63:0]$5715 $3\jtag_wb__dat_w$next[63:0]$5718 + attribute \src "libresoc.v:128473.5-128473.29" switch \initial - attribute \src "libresoc.v:40958.9-40958.17" + attribute \src "libresoc.v:128473.9-128473.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115" - switch \internal_op + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + switch \fsm_state attribute \src "libresoc.v:0.0-0.0" - case 7'0101110 + case 3'000 assign { } { } - assign $1\spr[9:0] { \SPR [4:0] \SPR [9:5] } + assign $1\jtag_wb__dat_w$next[63:0]$5716 $2\jtag_wb__dat_w$next[63:0]$5717 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" + switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $2\jtag_wb__dat_w$next[63:0]$5717 \jtag_wb__dat_w + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $2\jtag_wb__dat_w$next[63:0]$5717 \jtag_wb__dat_w + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\jtag_wb__dat_w$next[63:0]$5717 \jtag_wb_datasr__o + case + assign $2\jtag_wb__dat_w$next[63:0]$5717 \jtag_wb__dat_w + end case - assign $1\spr[9:0] 10'0000000000 + assign $1\jtag_wb__dat_w$next[63:0]$5716 \jtag_wb__dat_w + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb__dat_w$next[63:0]$5718 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\jtag_wb__dat_w$next[63:0]$5718 $1\jtag_wb__dat_w$next[63:0]$5716 end sync always - update \spr $0\spr[9:0] + update \jtag_wb__dat_w$next $0\jtag_wb__dat_w$next[63:0]$5715 end - attribute \src "libresoc.v:40968.3-40978.6" - process $proc$libresoc.v:40968$926 + attribute \src "libresoc.v:128499.3-128519.6" + process $proc$libresoc.v:128499$5719 assign { } { } assign { } { } - assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:40969.5-40969.29" + assign { } { } + assign $0\jtag_wb_datasr__i$next[63:0]$5720 $3\jtag_wb_datasr__i$next[63:0]$5723 + attribute \src "libresoc.v:128500.5-128500.29" switch \initial - attribute \src "libresoc.v:40969.9-40969.17" + attribute \src "libresoc.v:128500.9-128500.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115" - switch \internal_op + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + switch \fsm_state attribute \src "libresoc.v:0.0-0.0" - case 7'0101110 + case 3'011 assign { } { } - assign $1\sprmap_spr_i[9:0] \spr + assign $1\jtag_wb_datasr__i$next[63:0]$5721 $2\jtag_wb_datasr__i$next[63:0]$5722 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_datasr__i$next[63:0]$5722 \jtag_wb__dat_r + case + assign $2\jtag_wb_datasr__i$next[63:0]$5722 \jtag_wb_datasr__i + end case - assign $1\sprmap_spr_i[9:0] 10'0000000000 + assign $1\jtag_wb_datasr__i$next[63:0]$5721 \jtag_wb_datasr__i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb_datasr__i$next[63:0]$5723 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\jtag_wb_datasr__i$next[63:0]$5723 $1\jtag_wb_datasr__i$next[63:0]$5721 end sync always - update \sprmap_spr_i $0\sprmap_spr_i[9:0] + update \jtag_wb_datasr__i$next $0\jtag_wb_datasr__i$next[63:0]$5720 end - attribute \src "libresoc.v:40979.3-40990.6" - process $proc$libresoc.v:40979$927 - assign { } { } + attribute \src "libresoc.v:128520.3-128552.6" + process $proc$libresoc.v:128520$5724 assign { } { } assign { } { } assign { } { } - assign $0\spr_a[9:0] $1\spr_a[9:0] - assign $0\spr_a_ok[0:0] $1\spr_a_ok[0:0] - attribute \src "libresoc.v:40980.5-40980.29" + assign $0\dmi0__addr_i$next[3:0]$5725 $4\dmi0__addr_i$next[3:0]$5729 + attribute \src "libresoc.v:128521.5-128521.29" switch \initial - attribute \src "libresoc.v:40980.9-40980.17" + attribute \src "libresoc.v:128521.9-128521.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115" - switch \internal_op + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + switch \fsm_state$503 attribute \src "libresoc.v:0.0-0.0" - case 7'0101110 + case 3'000 assign { } { } + assign $1\dmi0__addr_i$next[3:0]$5726 $2\dmi0__addr_i$next[3:0]$5727 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" + switch { \dmi0_datasr__oe \dmi0_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\dmi0__addr_i$next[3:0]$5727 \dmi0_addrsr__o [3:0] + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\dmi0__addr_i$next[3:0]$5727 \$512 [3:0] + case + assign $2\dmi0__addr_i$next[3:0]$5727 \dmi0__addr_i + end + attribute \src "libresoc.v:0.0-0.0" + case 3'100 assign { } { } - assign { $1\spr_a_ok[0:0] $1\spr_a[9:0] } { \sprmap_spr_o_ok \sprmap_spr_o } + assign $1\dmi0__addr_i$next[3:0]$5726 $3\dmi0__addr_i$next[3:0]$5728 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" + switch \dmi0__ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0__addr_i$next[3:0]$5728 \$515 [3:0] + case + assign $3\dmi0__addr_i$next[3:0]$5728 \dmi0__addr_i + end case - assign $1\spr_a[9:0] 10'0000000000 - assign $1\spr_a_ok[0:0] 1'0 + assign $1\dmi0__addr_i$next[3:0]$5726 \dmi0__addr_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\dmi0__addr_i$next[3:0]$5729 4'0000 + case + assign $4\dmi0__addr_i$next[3:0]$5729 $1\dmi0__addr_i$next[3:0]$5726 end sync always - update \spr_a $0\spr_a[9:0] - update \spr_a_ok $0\spr_a_ok[0:0] - end - connect \$9 $or$libresoc.v:40867$907_Y - connect \$11 $eq$libresoc.v:40868$908_Y - connect \$13 $eq$libresoc.v:40869$909_Y - connect \$15 $eq$libresoc.v:40870$910_Y - connect \$17 $ne$libresoc.v:40871$911_Y - connect \$1 $eq$libresoc.v:40872$912_Y - connect \$19 $and$libresoc.v:40873$913_Y - connect \$21 $or$libresoc.v:40874$914_Y - connect \$23 $eq$libresoc.v:40875$915_Y - connect \$25 $not$libresoc.v:40876$916_Y - connect \$27 $not$libresoc.v:40877$917_Y - connect \$29 $and$libresoc.v:40878$918_Y - connect \$3 $eq$libresoc.v:40879$919_Y - connect \$5 $ne$libresoc.v:40880$920_Y - connect \$7 $and$libresoc.v:40881$921_Y - connect \ra \RA -end -attribute \src "libresoc.v:40996.1-41187.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_b" -attribute \generator "nMigen" -module \dec_b - attribute \src "libresoc.v:41151.3-41168.6" - wire width 3 $0\fast_b[2:0] - attribute \src "libresoc.v:41169.3-41186.6" - wire $0\fast_b_ok[0:0] - attribute \src "libresoc.v:40997.7-40997.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:41121.3-41135.6" - wire width 5 $0\reg_b[4:0] - attribute \src "libresoc.v:41136.3-41150.6" - wire $0\reg_b_ok[0:0] - attribute \src "libresoc.v:41151.3-41168.6" - wire width 3 $1\fast_b[2:0] - attribute \src "libresoc.v:41169.3-41186.6" - wire $1\fast_b_ok[0:0] - attribute \src "libresoc.v:41121.3-41135.6" - wire width 5 $1\reg_b[4:0] - attribute \src "libresoc.v:41136.3-41150.6" - wire $1\reg_b_ok[0:0] - attribute \src "libresoc.v:41151.3-41168.6" - wire width 3 $2\fast_b[2:0] - attribute \src "libresoc.v:41169.3-41186.6" - wire $2\fast_b_ok[0:0] - attribute \src "libresoc.v:41117.17-41117.117" - wire $eq$libresoc.v:41117$929_Y - attribute \src "libresoc.v:41119.17-41119.117" - wire $eq$libresoc.v:41119$931_Y - attribute \src "libresoc.v:41118.17-41118.107" - wire $not$libresoc.v:41118$930_Y - attribute \src "libresoc.v:41120.17-41120.107" - wire $not$libresoc.v:41120$932_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 7 \RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 6 \RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 input 8 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 output 4 \fast_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 5 \fast_b_ok - attribute \src "libresoc.v:40997.7-40997.15" - wire \initial - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 9 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 output 2 \reg_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 3 \reg_b_ok - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:178" - wire width 4 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" - cell $eq $eq$libresoc.v:41117$929 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0001000 - connect \Y $eq$libresoc.v:41117$929_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" - cell $eq $eq$libresoc.v:41119$931 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0001000 - connect \Y $eq$libresoc.v:41119$931_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204" - cell $not $not$libresoc.v:41118$930 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \XL_XO [9] - connect \Y $not$libresoc.v:41118$930_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204" - cell $not $not$libresoc.v:41120$932 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \XL_XO [9] - connect \Y $not$libresoc.v:41120$932_Y + update \dmi0__addr_i$next $0\dmi0__addr_i$next[3:0]$5725 end - attribute \src "libresoc.v:40997.7-40997.20" - process $proc$libresoc.v:40997$937 + attribute \src "libresoc.v:128553.3-128605.6" + process $proc$libresoc.v:128553$5730 assign { } { } - assign $0\initial[0:0] 1'0 + assign { } { } + assign { } { } + assign $0\fsm_state$503$next[2:0]$5731 $5\fsm_state$503$next[2:0]$5736 + attribute \src "libresoc.v:128554.5-128554.29" + switch \initial + attribute \src "libresoc.v:128554.9-128554.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + switch \fsm_state$503 + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\fsm_state$503$next[2:0]$5732 $2\fsm_state$503$next[2:0]$5733 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" + switch { \dmi0_datasr__oe \dmi0_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\fsm_state$503$next[2:0]$5733 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\fsm_state$503$next[2:0]$5733 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\fsm_state$503$next[2:0]$5733 3'010 + case + assign $2\fsm_state$503$next[2:0]$5733 \fsm_state$503 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\fsm_state$503$next[2:0]$5732 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\fsm_state$503$next[2:0]$5732 $3\fsm_state$503$next[2:0]$5734 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" + switch \dmi0__ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fsm_state$503$next[2:0]$5734 3'000 + case + assign $3\fsm_state$503$next[2:0]$5734 \fsm_state$503 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\fsm_state$503$next[2:0]$5732 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\fsm_state$503$next[2:0]$5732 $4\fsm_state$503$next[2:0]$5735 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" + switch \dmi0__ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$503$next[2:0]$5735 3'001 + case + assign $4\fsm_state$503$next[2:0]$5735 \fsm_state$503 + end + case + assign $1\fsm_state$503$next[2:0]$5732 \fsm_state$503 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fsm_state$503$next[2:0]$5736 3'000 + case + assign $5\fsm_state$503$next[2:0]$5736 $1\fsm_state$503$next[2:0]$5732 + end sync always - update \initial $0\initial[0:0] - sync init + update \fsm_state$503$next $0\fsm_state$503$next[2:0]$5731 end - attribute \src "libresoc.v:41121.3-41135.6" - process $proc$libresoc.v:41121$933 + attribute \src "libresoc.v:128606.3-128632.6" + process $proc$libresoc.v:128606$5737 assign { } { } assign { } { } - assign $0\reg_b[4:0] $1\reg_b[4:0] - attribute \src "libresoc.v:41122.5-41122.29" + assign { } { } + assign $0\dmi0__din$next[63:0]$5738 $3\dmi0__din$next[63:0]$5741 + attribute \src "libresoc.v:128607.5-128607.29" switch \initial - attribute \src "libresoc.v:41122.9-41122.17" + attribute \src "libresoc.v:128607.9-128607.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + switch \fsm_state$503 attribute \src "libresoc.v:0.0-0.0" - case 4'0001 + case 3'000 assign { } { } - assign $1\reg_b[4:0] \RB + assign $1\dmi0__din$next[63:0]$5739 $2\dmi0__din$next[63:0]$5740 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" + switch { \dmi0_datasr__oe \dmi0_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $2\dmi0__din$next[63:0]$5740 \dmi0__din + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $2\dmi0__din$next[63:0]$5740 \dmi0__din + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\dmi0__din$next[63:0]$5740 \dmi0_datasr__o + case + assign $2\dmi0__din$next[63:0]$5740 \dmi0__din + end + case + assign $1\dmi0__din$next[63:0]$5739 \dmi0__din + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" - case 4'1101 + case 1'1 assign { } { } - assign $1\reg_b[4:0] \RS + assign $3\dmi0__din$next[63:0]$5741 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $1\reg_b[4:0] 5'00000 + assign $3\dmi0__din$next[63:0]$5741 $1\dmi0__din$next[63:0]$5739 end sync always - update \reg_b $0\reg_b[4:0] + update \dmi0__din$next $0\dmi0__din$next[63:0]$5738 end - attribute \src "libresoc.v:41136.3-41150.6" - process $proc$libresoc.v:41136$934 + attribute \src "libresoc.v:128633.3-128653.6" + process $proc$libresoc.v:128633$5742 assign { } { } assign { } { } - assign $0\reg_b_ok[0:0] $1\reg_b_ok[0:0] - attribute \src "libresoc.v:41137.5-41137.29" + assign { } { } + assign $0\dmi0_datasr__i$next[63:0]$5743 $3\dmi0_datasr__i$next[63:0]$5746 + attribute \src "libresoc.v:128634.5-128634.29" switch \initial - attribute \src "libresoc.v:41137.9-41137.17" + attribute \src "libresoc.v:128634.9-128634.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + switch \fsm_state$503 attribute \src "libresoc.v:0.0-0.0" - case 4'0001 + case 3'011 assign { } { } - assign $1\reg_b_ok[0:0] 1'1 + assign $1\dmi0_datasr__i$next[63:0]$5744 $2\dmi0_datasr__i$next[63:0]$5745 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" + switch \dmi0__ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_datasr__i$next[63:0]$5745 \dmi0__dout + case + assign $2\dmi0_datasr__i$next[63:0]$5745 \dmi0_datasr__i + end + case + assign $1\dmi0_datasr__i$next[63:0]$5744 \dmi0_datasr__i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" - case 4'1101 + case 1'1 assign { } { } - assign $1\reg_b_ok[0:0] 1'1 + assign $3\dmi0_datasr__i$next[63:0]$5746 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $1\reg_b_ok[0:0] 1'0 + assign $3\dmi0_datasr__i$next[63:0]$5746 $1\dmi0_datasr__i$next[63:0]$5744 end sync always - update \reg_b_ok $0\reg_b_ok[0:0] + update \dmi0_datasr__i$next $0\dmi0_datasr__i$next[63:0]$5743 end - attribute \src "libresoc.v:41151.3-41168.6" - process $proc$libresoc.v:41151$935 + attribute \src "libresoc.v:128654.3-128672.6" + process $proc$libresoc.v:128654$5747 assign { } { } assign { } { } - assign $0\fast_b[2:0] $1\fast_b[2:0] - attribute \src "libresoc.v:41152.5-41152.29" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\wb_dcache_en$next[0:0]$5748 $2\wb_dcache_en$next[0:0]$5752 + assign $0\wb_icache_en$next[0:0]$5749 $2\wb_icache_en$next[0:0]$5753 + attribute \src "libresoc.v:128655.5-128655.29" switch \initial - attribute \src "libresoc.v:41152.9-41152.17" + attribute \src "libresoc.v:128655.9-128655.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" - switch \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:102" + switch \sr5__oe attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fast_b[2:0] $2\fast_b[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204" - switch { \XL_XO [5] \$3 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\fast_b[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\fast_b[2:0] 3'010 - case - assign $2\fast_b[2:0] 3'000 - end + assign { } { } + assign { $1\wb_dcache_en$next[0:0]$5750 $1\wb_icache_en$next[0:0]$5751 } \sr5__o case - assign $1\fast_b[2:0] 3'000 + assign $1\wb_dcache_en$next[0:0]$5750 \wb_dcache_en + assign $1\wb_icache_en$next[0:0]$5751 \wb_icache_en + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $2\wb_icache_en$next[0:0]$5753 1'1 + assign $2\wb_dcache_en$next[0:0]$5752 1'1 + case + assign $2\wb_dcache_en$next[0:0]$5752 $1\wb_dcache_en$next[0:0]$5750 + assign $2\wb_icache_en$next[0:0]$5753 $1\wb_icache_en$next[0:0]$5751 end sync always - update \fast_b $0\fast_b[2:0] + update \wb_dcache_en$next $0\wb_dcache_en$next[0:0]$5748 + update \wb_icache_en$next $0\wb_icache_en$next[0:0]$5749 end - attribute \src "libresoc.v:41169.3-41186.6" - process $proc$libresoc.v:41169$936 + attribute \src "libresoc.v:128673.3-128682.6" + process $proc$libresoc.v:128673$5754 assign { } { } assign { } { } - assign $0\fast_b_ok[0:0] $1\fast_b_ok[0:0] - attribute \src "libresoc.v:41170.5-41170.29" + assign $0\sr5__i[1:0] $1\sr5__i[1:0] + attribute \src "libresoc.v:128674.5-128674.29" switch \initial - attribute \src "libresoc.v:41170.9-41170.17" + attribute \src "libresoc.v:128674.9-128674.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" - switch \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:105" + switch \sr5__ie attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fast_b_ok[0:0] $2\fast_b_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204" - switch { \XL_XO [5] \$7 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\fast_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\fast_b_ok[0:0] 1'1 - case - assign $2\fast_b_ok[0:0] 1'0 - end + assign $1\sr5__i[1:0] { \wb_dcache_en \wb_icache_en } case - assign $1\fast_b_ok[0:0] 1'0 + assign $1\sr5__i[1:0] 2'00 end sync always - update \fast_b_ok $0\fast_b_ok[0:0] + update \sr5__i $0\sr5__i[1:0] end - connect \$1 $eq$libresoc.v:41117$929_Y - connect \$3 $not$libresoc.v:41118$930_Y - connect \$5 $eq$libresoc.v:41119$931_Y - connect \$7 $not$libresoc.v:41120$932_Y -end -attribute \src "libresoc.v:41191.1-41239.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_c" -attribute \generator "nMigen" -module \dec_c - attribute \src "libresoc.v:41192.7-41192.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:41209.3-41223.6" - wire width 5 $0\reg_c[4:0] - attribute \src "libresoc.v:41224.3-41238.6" - wire $0\reg_c_ok[0:0] - attribute \src "libresoc.v:41209.3-41223.6" - wire width 5 $1\reg_c[4:0] - attribute \src "libresoc.v:41224.3-41238.6" - wire $1\reg_c_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 4 \RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 3 \RS - attribute \src "libresoc.v:41192.7-41192.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 output 1 \reg_c - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \reg_c_ok - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:282" - wire width 2 input 5 \sel_in - attribute \src "libresoc.v:41192.7-41192.20" - process $proc$libresoc.v:41192$940 + attribute \src "libresoc.v:128683.3-128700.6" + process $proc$libresoc.v:128683$5755 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:41209.3-41223.6" - process $proc$libresoc.v:41209$938 assign { } { } assign { } { } - assign $0\reg_c[4:0] $1\reg_c[4:0] - attribute \src "libresoc.v:41210.5-41210.29" + assign $0\io_sr$next[153:0]$5756 $2\io_sr$next[153:0]$5758 + attribute \src "libresoc.v:128684.5-128684.29" switch \initial - attribute \src "libresoc.v:41210.9-41210.17" + attribute \src "libresoc.v:128684.9-128684.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:552" + switch { \io_update \io_shift \io_capture } attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 3'--1 assign { } { } - assign $1\reg_c[4:0] \RB + assign $1\io_sr$next[153:0]$5757 { \sdr_dq_15__core__oe \sdr_dq_15__core__o \sdr_dq_15__pad__i \sdr_dq_14__core__oe \sdr_dq_14__core__o \sdr_dq_14__pad__i \sdr_dq_13__core__oe \sdr_dq_13__core__o \sdr_dq_13__pad__i \sdr_dq_12__core__oe \sdr_dq_12__core__o \sdr_dq_12__pad__i \sdr_dq_11__core__oe \sdr_dq_11__core__o \sdr_dq_11__pad__i \sdr_dq_10__core__oe \sdr_dq_10__core__o \sdr_dq_10__pad__i \sdr_dq_9__core__oe \sdr_dq_9__core__o \sdr_dq_9__pad__i \sdr_dq_8__core__oe \sdr_dq_8__core__o \sdr_dq_8__pad__i \sdr_dm_1__core__oe \sdr_dm_1__core__o \sdr_dm_1__pad__i \sdr_a_12__core__o \sdr_a_11__core__o \sdr_a_10__core__o \sdr_cs_n__core__o \sdr_we_n__core__o \sdr_cas_n__core__o \sdr_ras_n__core__o \sdr_cke__core__o \sdr_clock__core__o \sdr_ba_1__core__o \sdr_ba_0__core__o \sdr_a_9__core__o \sdr_a_8__core__o \sdr_a_7__core__o \sdr_a_6__core__o \sdr_a_5__core__o \sdr_a_4__core__o \sdr_a_3__core__o \sdr_a_2__core__o \sdr_a_1__core__o \sdr_a_0__core__o \sdr_dq_7__core__oe \sdr_dq_7__core__o \sdr_dq_7__pad__i \sdr_dq_6__core__oe \sdr_dq_6__core__o \sdr_dq_6__pad__i \sdr_dq_5__core__oe \sdr_dq_5__core__o \sdr_dq_5__pad__i \sdr_dq_4__core__oe \sdr_dq_4__core__o \sdr_dq_4__pad__i \sdr_dq_3__core__oe \sdr_dq_3__core__o \sdr_dq_3__pad__i \sdr_dq_2__core__oe \sdr_dq_2__core__o \sdr_dq_2__pad__i \sdr_dq_1__core__oe \sdr_dq_1__core__o \sdr_dq_1__pad__i \sdr_dq_0__core__oe \sdr_dq_0__core__o \sdr_dq_0__pad__i \sdr_dm_0__core__o \sd0_data3__core__oe \sd0_data3__core__o \sd0_data3__pad__i \sd0_data2__core__oe \sd0_data2__core__o \sd0_data2__pad__i \sd0_data1__core__oe \sd0_data1__core__o \sd0_data1__pad__i \sd0_data0__core__oe \sd0_data0__core__o \sd0_data0__pad__i \sd0_clk__core__o \sd0_cmd__core__oe \sd0_cmd__core__o \sd0_cmd__pad__i \pwm_1__core__o \pwm_0__core__o \mtwi_scl__core__o \mtwi_sda__core__oe \mtwi_sda__core__o \mtwi_sda__pad__i \mspi1_miso__pad__i \mspi1_mosi__core__o \mspi1_cs_n__core__o \mspi1_clk__core__o \mspi0_miso__pad__i \mspi0_mosi__core__o \mspi0_cs_n__core__o \mspi0_clk__core__o \gpio_s7__core__oe \gpio_s7__core__o \gpio_s7__pad__i \gpio_s6__core__oe \gpio_s6__core__o \gpio_s6__pad__i \gpio_s5__core__oe \gpio_s5__core__o \gpio_s5__pad__i \gpio_s4__core__oe \gpio_s4__core__o \gpio_s4__pad__i \gpio_s3__core__oe \gpio_s3__core__o \gpio_s3__pad__i \gpio_s2__core__oe \gpio_s2__core__o \gpio_s2__pad__i \gpio_s1__core__oe \gpio_s1__core__o \gpio_s1__pad__i \gpio_s0__core__oe \gpio_s0__core__o \gpio_s0__pad__i \gpio_e15__core__oe \gpio_e15__core__o \gpio_e15__pad__i \gpio_e14__core__oe \gpio_e14__core__o \gpio_e14__pad__i \gpio_e13__core__oe \gpio_e13__core__o \gpio_e13__pad__i \gpio_e12__core__oe \gpio_e12__core__o \gpio_e12__pad__i \gpio_e11__core__oe \gpio_e11__core__o \gpio_e11__pad__i \gpio_e10__core__oe \gpio_e10__core__o \gpio_e10__pad__i \gpio_e9__core__oe \gpio_e9__core__o \gpio_e9__pad__i \gpio_e8__core__oe \gpio_e8__core__o \gpio_e8__pad__i \eint_2__pad__i \eint_1__pad__i \eint_0__pad__i } attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 3'-1- assign { } { } - assign $1\reg_c[4:0] \RS + assign $1\io_sr$next[153:0]$5757 { \io_sr [152:0] \TAP_bus__tdi } case - assign $1\reg_c[4:0] 5'00000 + assign $1\io_sr$next[153:0]$5757 \io_sr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\io_sr$next[153:0]$5758 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\io_sr$next[153:0]$5758 $1\io_sr$next[153:0]$5757 end sync always - update \reg_c $0\reg_c[4:0] + update \io_sr$next $0\io_sr$next[153:0]$5756 end - attribute \src "libresoc.v:41224.3-41238.6" - process $proc$libresoc.v:41224$939 + attribute \src "libresoc.v:128701.3-128721.6" + process $proc$libresoc.v:128701$5759 assign { } { } assign { } { } - assign $0\reg_c_ok[0:0] $1\reg_c_ok[0:0] - attribute \src "libresoc.v:41225.5-41225.29" + assign { } { } + assign $0\io_bd$next[153:0]$5760 $2\io_bd$next[153:0]$5762 + attribute \src "libresoc.v:128702.5-128702.29" switch \initial - attribute \src "libresoc.v:41225.9-41225.17" + attribute \src "libresoc.v:128702.9-128702.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:552" + switch { \io_update \io_shift \io_capture } attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\reg_c_ok[0:0] 1'1 + case 3'--1 + assign $1\io_bd$next[153:0]$5761 \io_bd attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 3'-1- + assign $1\io_bd$next[153:0]$5761 \io_bd + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- assign { } { } - assign $1\reg_c_ok[0:0] 1'1 + assign $1\io_bd$next[153:0]$5761 \io_sr case - assign $1\reg_c_ok[0:0] 1'0 + assign $1\io_bd$next[153:0]$5761 \io_bd end - sync always - update \reg_c_ok $0\reg_c_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \negjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\io_bd$next[153:0]$5762 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\io_bd$next[153:0]$5762 $1\io_bd$next[153:0]$5761 + end + sync always + update \io_bd$next $0\io_bd$next[153:0]$5760 + end + connect \$9 $eq$libresoc.v:127644$5315_Y + connect \$99 $ternary$libresoc.v:127645$5316_Y + connect \$101 $ternary$libresoc.v:127646$5317_Y + connect \$103 $ternary$libresoc.v:127647$5318_Y + connect \$105 $ternary$libresoc.v:127648$5319_Y + connect \$107 $ternary$libresoc.v:127649$5320_Y + connect \$109 $ternary$libresoc.v:127650$5321_Y + connect \$111 $ternary$libresoc.v:127651$5322_Y + connect \$113 $ternary$libresoc.v:127652$5323_Y + connect \$115 $ternary$libresoc.v:127653$5324_Y + connect \$117 $ternary$libresoc.v:127654$5325_Y + connect \$11 $eq$libresoc.v:127655$5326_Y + connect \$119 $ternary$libresoc.v:127656$5327_Y + connect \$121 $ternary$libresoc.v:127657$5328_Y + connect \$123 $ternary$libresoc.v:127658$5329_Y + connect \$125 $ternary$libresoc.v:127659$5330_Y + connect \$127 $ternary$libresoc.v:127660$5331_Y + connect \$129 $ternary$libresoc.v:127661$5332_Y + connect \$131 $ternary$libresoc.v:127662$5333_Y + connect \$133 $ternary$libresoc.v:127663$5334_Y + connect \$135 $ternary$libresoc.v:127664$5335_Y + connect \$137 $ternary$libresoc.v:127665$5336_Y + connect \$13 $eq$libresoc.v:127666$5337_Y + connect \$139 $ternary$libresoc.v:127667$5338_Y + connect \$141 $ternary$libresoc.v:127668$5339_Y + connect \$143 $ternary$libresoc.v:127669$5340_Y + connect \$145 $ternary$libresoc.v:127670$5341_Y + connect \$147 $ternary$libresoc.v:127671$5342_Y + connect \$149 $ternary$libresoc.v:127672$5343_Y + connect \$151 $ternary$libresoc.v:127673$5344_Y + connect \$153 $ternary$libresoc.v:127674$5345_Y + connect \$155 $ternary$libresoc.v:127675$5346_Y + connect \$157 $ternary$libresoc.v:127676$5347_Y + connect \$15 $or$libresoc.v:127677$5348_Y + connect \$159 $ternary$libresoc.v:127678$5349_Y + connect \$161 $ternary$libresoc.v:127679$5350_Y + connect \$163 $ternary$libresoc.v:127680$5351_Y + connect \$165 $ternary$libresoc.v:127681$5352_Y + connect \$167 $ternary$libresoc.v:127682$5353_Y + connect \$169 $ternary$libresoc.v:127683$5354_Y + connect \$171 $ternary$libresoc.v:127684$5355_Y + connect \$173 $ternary$libresoc.v:127685$5356_Y + connect \$175 $ternary$libresoc.v:127686$5357_Y + connect \$177 $ternary$libresoc.v:127687$5358_Y + connect \$17 $and$libresoc.v:127688$5359_Y + connect \$179 $ternary$libresoc.v:127689$5360_Y + connect \$181 $ternary$libresoc.v:127690$5361_Y + connect \$183 $ternary$libresoc.v:127691$5362_Y + connect \$185 $ternary$libresoc.v:127692$5363_Y + connect \$187 $ternary$libresoc.v:127693$5364_Y + connect \$189 $ternary$libresoc.v:127694$5365_Y + connect \$191 $ternary$libresoc.v:127695$5366_Y + connect \$193 $ternary$libresoc.v:127696$5367_Y + connect \$195 $ternary$libresoc.v:127697$5368_Y + connect \$197 $ternary$libresoc.v:127698$5369_Y + connect \$1 $eq$libresoc.v:127699$5370_Y + connect \$19 $eq$libresoc.v:127700$5371_Y + connect \$199 $ternary$libresoc.v:127701$5372_Y + connect \$201 $ternary$libresoc.v:127702$5373_Y + connect \$203 $ternary$libresoc.v:127703$5374_Y + connect \$205 $ternary$libresoc.v:127704$5375_Y + connect \$207 $ternary$libresoc.v:127705$5376_Y + connect \$209 $ternary$libresoc.v:127706$5377_Y + connect \$211 $ternary$libresoc.v:127707$5378_Y + connect \$213 $ternary$libresoc.v:127708$5379_Y + connect \$215 $ternary$libresoc.v:127709$5380_Y + connect \$217 $ternary$libresoc.v:127710$5381_Y + connect \$21 $eq$libresoc.v:127711$5382_Y + connect \$219 $ternary$libresoc.v:127712$5383_Y + connect \$221 $ternary$libresoc.v:127713$5384_Y + connect \$223 $ternary$libresoc.v:127714$5385_Y + connect \$225 $ternary$libresoc.v:127715$5386_Y + connect \$227 $ternary$libresoc.v:127716$5387_Y + connect \$229 $ternary$libresoc.v:127717$5388_Y + connect \$231 $ternary$libresoc.v:127718$5389_Y + connect \$233 $ternary$libresoc.v:127719$5390_Y + connect \$235 $ternary$libresoc.v:127720$5391_Y + connect \$237 $ternary$libresoc.v:127721$5392_Y + connect \$23 $or$libresoc.v:127722$5393_Y + connect \$239 $ternary$libresoc.v:127723$5394_Y + connect \$241 $ternary$libresoc.v:127724$5395_Y + connect \$243 $ternary$libresoc.v:127725$5396_Y + connect \$245 $ternary$libresoc.v:127726$5397_Y + connect \$247 $ternary$libresoc.v:127727$5398_Y + connect \$249 $ternary$libresoc.v:127728$5399_Y + connect \$251 $ternary$libresoc.v:127729$5400_Y + connect \$253 $ternary$libresoc.v:127730$5401_Y + connect \$255 $ternary$libresoc.v:127731$5402_Y + connect \$257 $ternary$libresoc.v:127732$5403_Y + connect \$25 $eq$libresoc.v:127733$5404_Y + connect \$259 $ternary$libresoc.v:127734$5405_Y + connect \$261 $ternary$libresoc.v:127735$5406_Y + connect \$263 $ternary$libresoc.v:127736$5407_Y + connect \$265 $ternary$libresoc.v:127737$5408_Y + connect \$267 $ternary$libresoc.v:127738$5409_Y + connect \$269 $ternary$libresoc.v:127739$5410_Y + connect \$271 $ternary$libresoc.v:127740$5411_Y + connect \$273 $ternary$libresoc.v:127741$5412_Y + connect \$275 $ternary$libresoc.v:127742$5413_Y + connect \$277 $ternary$libresoc.v:127743$5414_Y + connect \$27 $or$libresoc.v:127744$5415_Y + connect \$279 $ternary$libresoc.v:127745$5416_Y + connect \$281 $ternary$libresoc.v:127746$5417_Y + connect \$283 $ternary$libresoc.v:127747$5418_Y + connect \$285 $ternary$libresoc.v:127748$5419_Y + connect \$287 $ternary$libresoc.v:127749$5420_Y + connect \$289 $ternary$libresoc.v:127750$5421_Y + connect \$291 $ternary$libresoc.v:127751$5422_Y + connect \$293 $ternary$libresoc.v:127752$5423_Y + connect \$295 $ternary$libresoc.v:127753$5424_Y + connect \$297 $ternary$libresoc.v:127754$5425_Y + connect \$29 $and$libresoc.v:127755$5426_Y + connect \$299 $ternary$libresoc.v:127756$5427_Y + connect \$301 $ternary$libresoc.v:127757$5428_Y + connect \$303 $ternary$libresoc.v:127758$5429_Y + connect \$305 $ternary$libresoc.v:127759$5430_Y + connect \$307 $ternary$libresoc.v:127760$5431_Y + connect \$309 $ternary$libresoc.v:127761$5432_Y + connect \$311 $ternary$libresoc.v:127762$5433_Y + connect \$313 $ternary$libresoc.v:127763$5434_Y + connect \$315 $ternary$libresoc.v:127764$5435_Y + connect \$317 $ternary$libresoc.v:127765$5436_Y + connect \$31 $and$libresoc.v:127766$5437_Y + connect \$319 $ternary$libresoc.v:127767$5438_Y + connect \$321 $ternary$libresoc.v:127768$5439_Y + connect \$323 $ternary$libresoc.v:127769$5440_Y + connect \$325 $ternary$libresoc.v:127770$5441_Y + connect \$327 $ternary$libresoc.v:127771$5442_Y + connect \$329 $ternary$libresoc.v:127772$5443_Y + connect \$331 $ternary$libresoc.v:127773$5444_Y + connect \$333 $ternary$libresoc.v:127774$5445_Y + connect \$335 $ternary$libresoc.v:127775$5446_Y + connect \$337 $ternary$libresoc.v:127776$5447_Y + connect \$33 $eq$libresoc.v:127777$5448_Y + connect \$339 $ternary$libresoc.v:127778$5449_Y + connect \$341 $ternary$libresoc.v:127779$5450_Y + connect \$343 $ternary$libresoc.v:127780$5451_Y + connect \$345 $ternary$libresoc.v:127781$5452_Y + connect \$347 $ternary$libresoc.v:127782$5453_Y + connect \$349 $ternary$libresoc.v:127783$5454_Y + connect \$351 $ternary$libresoc.v:127784$5455_Y + connect \$353 $ternary$libresoc.v:127785$5456_Y + connect \$355 $ternary$libresoc.v:127786$5457_Y + connect \$357 $ternary$libresoc.v:127787$5458_Y + connect \$35 $eq$libresoc.v:127788$5459_Y + connect \$359 $eq$libresoc.v:127789$5460_Y + connect \$361 $eq$libresoc.v:127790$5461_Y + connect \$363 $or$libresoc.v:127791$5462_Y + connect \$365 $eq$libresoc.v:127792$5463_Y + connect \$367 $or$libresoc.v:127793$5464_Y + connect \$369 $and$libresoc.v:127794$5465_Y + connect \$371 $eq$libresoc.v:127795$5466_Y + connect \$373 $ne$libresoc.v:127796$5467_Y + connect \$375 $and$libresoc.v:127797$5468_Y + connect \$377 $ne$libresoc.v:127798$5469_Y + connect \$37 $or$libresoc.v:127799$5470_Y + connect \$379 $and$libresoc.v:127800$5471_Y + connect \$381 $ne$libresoc.v:127801$5472_Y + connect \$383 $and$libresoc.v:127802$5473_Y + connect \$385 $not$libresoc.v:127803$5474_Y + connect \$387 $and$libresoc.v:127804$5475_Y + connect \$389 $eq$libresoc.v:127805$5476_Y + connect \$391 $ne$libresoc.v:127806$5477_Y + connect \$393 $and$libresoc.v:127807$5478_Y + connect \$395 $ne$libresoc.v:127808$5479_Y + connect \$397 $and$libresoc.v:127809$5480_Y + connect \$3 $eq$libresoc.v:127810$5481_Y + connect \$39 $eq$libresoc.v:127811$5482_Y + connect \$399 $ne$libresoc.v:127812$5483_Y + connect \$401 $and$libresoc.v:127813$5484_Y + connect \$403 $not$libresoc.v:127814$5485_Y + connect \$405 $and$libresoc.v:127815$5486_Y + connect \$407 $eq$libresoc.v:127816$5487_Y + connect \$409 $eq$libresoc.v:127817$5488_Y + connect \$411 $ne$libresoc.v:127818$5489_Y + connect \$413 $and$libresoc.v:127819$5490_Y + connect \$415 $ne$libresoc.v:127820$5491_Y + connect \$417 $and$libresoc.v:127821$5492_Y + connect \$41 $or$libresoc.v:127822$5493_Y + connect \$419 $ne$libresoc.v:127823$5494_Y + connect \$421 $and$libresoc.v:127824$5495_Y + connect \$423 $not$libresoc.v:127825$5496_Y + connect \$425 $and$libresoc.v:127826$5497_Y + connect \$427 $eq$libresoc.v:127827$5498_Y + connect \$429 $ne$libresoc.v:127828$5499_Y + connect \$431 $and$libresoc.v:127829$5500_Y + connect \$433 $ne$libresoc.v:127830$5501_Y + connect \$435 $and$libresoc.v:127831$5502_Y + connect \$437 $ne$libresoc.v:127832$5503_Y + connect \$43 $and$libresoc.v:127833$5504_Y + connect \$439 $and$libresoc.v:127834$5505_Y + connect \$441 $not$libresoc.v:127835$5506_Y + connect \$443 $and$libresoc.v:127836$5507_Y + connect \$445 $eq$libresoc.v:127837$5508_Y + connect \$447 $eq$libresoc.v:127838$5509_Y + connect \$449 $ne$libresoc.v:127839$5510_Y + connect \$451 $and$libresoc.v:127840$5511_Y + connect \$453 $ne$libresoc.v:127841$5512_Y + connect \$455 $and$libresoc.v:127842$5513_Y + connect \$457 $ne$libresoc.v:127843$5514_Y + connect \$45 $and$libresoc.v:127844$5515_Y + connect \$459 $and$libresoc.v:127845$5516_Y + connect \$461 $not$libresoc.v:127846$5517_Y + connect \$463 $and$libresoc.v:127847$5518_Y + connect \$465 $eq$libresoc.v:127848$5519_Y + connect \$467 $ne$libresoc.v:127849$5520_Y + connect \$469 $and$libresoc.v:127850$5521_Y + connect \$471 $ne$libresoc.v:127851$5522_Y + connect \$473 $and$libresoc.v:127852$5523_Y + connect \$475 $ne$libresoc.v:127853$5524_Y + connect \$477 $and$libresoc.v:127854$5525_Y + connect \$47 $eq$libresoc.v:127855$5526_Y + connect \$479 $not$libresoc.v:127856$5527_Y + connect \$481 $and$libresoc.v:127857$5528_Y + connect \$484 $eq$libresoc.v:127858$5529_Y + connect \$483 $not$libresoc.v:127859$5530_Y + connect \$487 $eq$libresoc.v:127860$5531_Y + connect \$489 $eq$libresoc.v:127861$5532_Y + connect \$491 $or$libresoc.v:127862$5533_Y + connect \$493 $eq$libresoc.v:127863$5534_Y + connect \$496 $add$libresoc.v:127864$5535_Y + connect \$49 $eq$libresoc.v:127865$5536_Y + connect \$499 $add$libresoc.v:127866$5537_Y + connect \$501 $pos$libresoc.v:127867$5539_Y + connect \$504 $eq$libresoc.v:127868$5540_Y + connect \$506 $eq$libresoc.v:127869$5541_Y + connect \$508 $or$libresoc.v:127870$5542_Y + connect \$510 $eq$libresoc.v:127871$5543_Y + connect \$513 $add$libresoc.v:127872$5544_Y + connect \$516 $add$libresoc.v:127873$5545_Y + connect \$51 $ternary$libresoc.v:127874$5546_Y + connect \$53 $ternary$libresoc.v:127875$5547_Y + connect \$55 $ternary$libresoc.v:127876$5548_Y + connect \$57 $ternary$libresoc.v:127877$5549_Y + connect \$5 $or$libresoc.v:127878$5550_Y + connect \$59 $ternary$libresoc.v:127879$5551_Y + connect \$61 $ternary$libresoc.v:127880$5552_Y + connect \$63 $ternary$libresoc.v:127881$5553_Y + connect \$65 $ternary$libresoc.v:127882$5554_Y + connect \$67 $ternary$libresoc.v:127883$5555_Y + connect \$69 $ternary$libresoc.v:127884$5556_Y + connect \$71 $ternary$libresoc.v:127885$5557_Y + connect \$73 $ternary$libresoc.v:127886$5558_Y + connect \$75 $ternary$libresoc.v:127887$5559_Y + connect \$77 $ternary$libresoc.v:127888$5560_Y + connect \$7 $and$libresoc.v:127889$5561_Y + connect \$79 $ternary$libresoc.v:127890$5562_Y + connect \$81 $ternary$libresoc.v:127891$5563_Y + connect \$83 $ternary$libresoc.v:127892$5564_Y + connect \$85 $ternary$libresoc.v:127893$5565_Y + connect \$87 $ternary$libresoc.v:127894$5566_Y + connect \$89 $ternary$libresoc.v:127895$5567_Y + connect \$91 $ternary$libresoc.v:127896$5568_Y + connect \$93 $ternary$libresoc.v:127897$5569_Y + connect \$95 $ternary$libresoc.v:127898$5570_Y + connect \$97 $ternary$libresoc.v:127899$5571_Y + connect \$495 \$496 + connect \$498 \$499 + connect \$512 \$513 + connect \$515 \$516 + connect \sr5__ie 1'0 + connect \sr0__i \sr0__o + connect \dmi0__we_i \$510 + connect \dmi0__req_i \$508 + connect \dmi0_addrsr__i \$501 + connect \jtag_wb__we \$493 + connect \jtag_wb__stb \$491 + connect \jtag_wb__cyc \$483 + connect \jtag_wb__sel 1'1 + connect \jtag_wb_addrsr__i \jtag_wb__adr + connect \sr5_update \$477 + connect \sr5_shift \$473 + connect \sr5_capture \$469 + connect \sr5_isir \$465 + connect \sr5__o \sr5_reg + connect \dmi0_datasr_update \$459 + connect \dmi0_datasr_shift \$455 + connect \dmi0_datasr_capture \$451 + connect \dmi0_datasr_isir { \$447 \$445 } + connect \dmi0_datasr__o \dmi0_datasr_reg + connect \dmi0_addrsr_update \$439 + connect \dmi0_addrsr_shift \$435 + connect \dmi0_addrsr_capture \$431 + connect \dmi0_addrsr_isir \$427 + connect \dmi0_addrsr__o \dmi0_addrsr_reg + connect \jtag_wb_datasr_update \$421 + connect \jtag_wb_datasr_shift \$417 + connect \jtag_wb_datasr_capture \$413 + connect \jtag_wb_datasr_isir { \$409 \$407 } + connect \jtag_wb_datasr__o \jtag_wb_datasr_reg + connect \jtag_wb_addrsr_update \$401 + connect \jtag_wb_addrsr_shift \$397 + connect \jtag_wb_addrsr_capture \$393 + connect \jtag_wb_addrsr_isir \$389 + connect \jtag_wb_addrsr__o \jtag_wb_addrsr_reg + connect \sr0_update \$383 + connect \sr0_shift \$379 + connect \sr0_capture \$375 + connect \sr0_isir \$371 + connect \sr0__o \sr0_reg + connect \sdr_dq_15__pad__oe \$357 + connect \sdr_dq_15__pad__o \$355 + connect \sdr_dq_15__core__i \$353 + connect \sdr_dq_14__pad__oe \$351 + connect \sdr_dq_14__pad__o \$349 + connect \sdr_dq_14__core__i \$347 + connect \sdr_dq_13__pad__oe \$345 + connect \sdr_dq_13__pad__o \$343 + connect \sdr_dq_13__core__i \$341 + connect \sdr_dq_12__pad__oe \$339 + connect \sdr_dq_12__pad__o \$337 + connect \sdr_dq_12__core__i \$335 + connect \sdr_dq_11__pad__oe \$333 + connect \sdr_dq_11__pad__o \$331 + connect \sdr_dq_11__core__i \$329 + connect \sdr_dq_10__pad__oe \$327 + connect \sdr_dq_10__pad__o \$325 + connect \sdr_dq_10__core__i \$323 + connect \sdr_dq_9__pad__oe \$321 + connect \sdr_dq_9__pad__o \$319 + connect \sdr_dq_9__core__i \$317 + connect \sdr_dq_8__pad__oe \$315 + connect \sdr_dq_8__pad__o \$313 + connect \sdr_dq_8__core__i \$311 + connect \sdr_dm_1__pad__oe \$309 + connect \sdr_dm_1__pad__o \$307 + connect \sdr_dm_1__core__i \$305 + connect \sdr_a_12__pad__o \$303 + connect \sdr_a_11__pad__o \$301 + connect \sdr_a_10__pad__o \$299 + connect \sdr_cs_n__pad__o \$297 + connect \sdr_we_n__pad__o \$295 + connect \sdr_cas_n__pad__o \$293 + connect \sdr_ras_n__pad__o \$291 + connect \sdr_cke__pad__o \$289 + connect \sdr_clock__pad__o \$287 + connect \sdr_ba_1__pad__o \$285 + connect \sdr_ba_0__pad__o \$283 + connect \sdr_a_9__pad__o \$281 + connect \sdr_a_8__pad__o \$279 + connect \sdr_a_7__pad__o \$277 + connect \sdr_a_6__pad__o \$275 + connect \sdr_a_5__pad__o \$273 + connect \sdr_a_4__pad__o \$271 + connect \sdr_a_3__pad__o \$269 + connect \sdr_a_2__pad__o \$267 + connect \sdr_a_1__pad__o \$265 + connect \sdr_a_0__pad__o \$263 + connect \sdr_dq_7__pad__oe \$261 + connect \sdr_dq_7__pad__o \$259 + connect \sdr_dq_7__core__i \$257 + connect \sdr_dq_6__pad__oe \$255 + connect \sdr_dq_6__pad__o \$253 + connect \sdr_dq_6__core__i \$251 + connect \sdr_dq_5__pad__oe \$249 + connect \sdr_dq_5__pad__o \$247 + connect \sdr_dq_5__core__i \$245 + connect \sdr_dq_4__pad__oe \$243 + connect \sdr_dq_4__pad__o \$241 + connect \sdr_dq_4__core__i \$239 + connect \sdr_dq_3__pad__oe \$237 + connect \sdr_dq_3__pad__o \$235 + connect \sdr_dq_3__core__i \$233 + connect \sdr_dq_2__pad__oe \$231 + connect \sdr_dq_2__pad__o \$229 + connect \sdr_dq_2__core__i \$227 + connect \sdr_dq_1__pad__oe \$225 + connect \sdr_dq_1__pad__o \$223 + connect \sdr_dq_1__core__i \$221 + connect \sdr_dq_0__pad__oe \$219 + connect \sdr_dq_0__pad__o \$217 + connect \sdr_dq_0__core__i \$215 + connect \sdr_dm_0__pad__o \$213 + connect \sd0_data3__pad__oe \$211 + connect \sd0_data3__pad__o \$209 + connect \sd0_data3__core__i \$207 + connect \sd0_data2__pad__oe \$205 + connect \sd0_data2__pad__o \$203 + connect \sd0_data2__core__i \$201 + connect \sd0_data1__pad__oe \$199 + connect \sd0_data1__pad__o \$197 + connect \sd0_data1__core__i \$195 + connect \sd0_data0__pad__oe \$193 + connect \sd0_data0__pad__o \$191 + connect \sd0_data0__core__i \$189 + connect \sd0_clk__pad__o \$187 + connect \sd0_cmd__pad__oe \$185 + connect \sd0_cmd__pad__o \$183 + connect \sd0_cmd__core__i \$181 + connect \pwm_1__pad__o \$179 + connect \pwm_0__pad__o \$177 + connect \mtwi_scl__pad__o \$175 + connect \mtwi_sda__pad__oe \$173 + connect \mtwi_sda__pad__o \$171 + connect \mtwi_sda__core__i \$169 + connect \mspi1_miso__core__i \$167 + connect \mspi1_mosi__pad__o \$165 + connect \mspi1_cs_n__pad__o \$163 + connect \mspi1_clk__pad__o \$161 + connect \mspi0_miso__core__i \$159 + connect \mspi0_mosi__pad__o \$157 + connect \mspi0_cs_n__pad__o \$155 + connect \mspi0_clk__pad__o \$153 + connect \gpio_s7__pad__oe \$151 + connect \gpio_s7__pad__o \$149 + connect \gpio_s7__core__i \$147 + connect \gpio_s6__pad__oe \$145 + connect \gpio_s6__pad__o \$143 + connect \gpio_s6__core__i \$141 + connect \gpio_s5__pad__oe \$139 + connect \gpio_s5__pad__o \$137 + connect \gpio_s5__core__i \$135 + connect \gpio_s4__pad__oe \$133 + connect \gpio_s4__pad__o \$131 + connect \gpio_s4__core__i \$129 + connect \gpio_s3__pad__oe \$127 + connect \gpio_s3__pad__o \$125 + connect \gpio_s3__core__i \$123 + connect \gpio_s2__pad__oe \$121 + connect \gpio_s2__pad__o \$119 + connect \gpio_s2__core__i \$117 + connect \gpio_s1__pad__oe \$115 + connect \gpio_s1__pad__o \$113 + connect \gpio_s1__core__i \$111 + connect \gpio_s0__pad__oe \$109 + connect \gpio_s0__pad__o \$107 + connect \gpio_s0__core__i \$105 + connect \gpio_e15__pad__oe \$103 + connect \gpio_e15__pad__o \$101 + connect \gpio_e15__core__i \$99 + connect \gpio_e14__pad__oe \$97 + connect \gpio_e14__pad__o \$95 + connect \gpio_e14__core__i \$93 + connect \gpio_e13__pad__oe \$91 + connect \gpio_e13__pad__o \$89 + connect \gpio_e13__core__i \$87 + connect \gpio_e12__pad__oe \$85 + connect \gpio_e12__pad__o \$83 + connect \gpio_e12__core__i \$81 + connect \gpio_e11__pad__oe \$79 + connect \gpio_e11__pad__o \$77 + connect \gpio_e11__core__i \$75 + connect \gpio_e10__pad__oe \$73 + connect \gpio_e10__pad__o \$71 + connect \gpio_e10__core__i \$69 + connect \gpio_e9__pad__oe \$67 + connect \gpio_e9__pad__o \$65 + connect \gpio_e9__core__i \$63 + connect \gpio_e8__pad__oe \$61 + connect \gpio_e8__pad__o \$59 + connect \gpio_e8__core__i \$57 + connect \eint_2__core__i \$55 + connect \eint_1__core__i \$53 + connect \eint_0__core__i \$51 + connect \io_bd2core \$49 + connect \io_bd2io \$47 + connect \io_update \$45 + connect \io_shift \$31 + connect \io_capture \$17 + connect \_idblock_id_bypass \$9 + connect \_idblock_select_id \$7 +end +attribute \src "libresoc.v:128931.1-129120.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0" +attribute \generator "nMigen" +module \l0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 31 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 23 \dbus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 45 output 28 \dbus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 22 \dbus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 input 27 \dbus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 output 30 \dbus__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 24 \dbus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 8 output 26 \dbus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 25 \dbus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 29 \dbus__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 96 input 6 \ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 7 \ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire output 16 \ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire output 2 \ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 input 5 \ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 8 \ldst_port0_exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 9 \ldst_port0_exc_$signal$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 10 \ldst_port0_exc_$signal$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 11 \ldst_port0_exc_$signal$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 12 \ldst_port0_exc_$signal$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 13 \ldst_port0_exc_$signal$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 14 \ldst_port0_exc_$signal$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 15 \ldst_port0_exc_$signal$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire input 3 \ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire input 4 \ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 17 \ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 18 \ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 19 \ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 20 \ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 48 \pimem_ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pimem_ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire \pimem_ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire \pimem_ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 \pimem_ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \pimem_ldst_port0_exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire \pimem_ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire \pimem_ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pimem_ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pimem_ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pimem_ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pimem_ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:69" + wire width 64 \pimem_m_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:61" + wire \pimem_m_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" + wire width 48 \pimem_x_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:66" + wire \pimem_x_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52" + wire \pimem_x_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51" + wire width 8 \pimem_x_mask_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:54" + wire width 64 \pimem_x_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53" + wire \pimem_x_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" + wire \pimem_x_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" + wire input 21 \wb_dcache_en + attribute \module_not_derived 1 + attribute \src "libresoc.v:129036.12-129070.4" + cell \l0$130 \l0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \ldst_port0_addr_i \ldst_port0_addr_i + connect \ldst_port0_addr_i$12 \pimem_ldst_port0_addr_i + connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok + connect \ldst_port0_addr_i_ok$13 \pimem_ldst_port0_addr_i_ok + connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o + connect \ldst_port0_addr_ok_o$14 \pimem_ldst_port0_addr_ok_o + connect \ldst_port0_busy_o \ldst_port0_busy_o + connect \ldst_port0_busy_o$10 \pimem_ldst_port0_busy_o + connect \ldst_port0_data_len \ldst_port0_data_len + connect \ldst_port0_data_len$11 \pimem_ldst_port0_data_len + connect \ldst_port0_exc_$signal \ldst_port0_exc_$signal + connect \ldst_port0_exc_$signal$1 \ldst_port0_exc_$signal$1 + connect \ldst_port0_exc_$signal$19 \pimem_ldst_port0_exc_$signal + connect \ldst_port0_exc_$signal$2 \ldst_port0_exc_$signal$2 + connect \ldst_port0_exc_$signal$3 \ldst_port0_exc_$signal$3 + connect \ldst_port0_exc_$signal$4 \ldst_port0_exc_$signal$4 + connect \ldst_port0_exc_$signal$5 \ldst_port0_exc_$signal$5 + connect \ldst_port0_exc_$signal$6 \ldst_port0_exc_$signal$6 + connect \ldst_port0_exc_$signal$7 \ldst_port0_exc_$signal$7 + connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i + connect \ldst_port0_is_ld_i$8 \pimem_ldst_port0_is_ld_i + connect \ldst_port0_is_st_i \ldst_port0_is_st_i + connect \ldst_port0_is_st_i$9 \pimem_ldst_port0_is_st_i + connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o$15 \pimem_ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok + connect \ldst_port0_ld_data_o_ok$16 \pimem_ldst_port0_ld_data_o_ok + connect \ldst_port0_st_data_i \ldst_port0_st_data_i + connect \ldst_port0_st_data_i$18 \pimem_ldst_port0_st_data_i + connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok + connect \ldst_port0_st_data_i_ok$17 \pimem_ldst_port0_st_data_i_ok end + attribute \module_not_derived 1 + attribute \src "libresoc.v:129071.9-129093.4" + cell \lsmem \lsmem + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dbus__ack \dbus__ack + connect \dbus__adr \dbus__adr + connect \dbus__cyc \dbus__cyc + connect \dbus__dat_r \dbus__dat_r + connect \dbus__dat_w \dbus__dat_w + connect \dbus__err \dbus__err + connect \dbus__sel \dbus__sel + connect \dbus__stb \dbus__stb + connect \dbus__we \dbus__we + connect \m_ld_data_o \pimem_m_ld_data_o + connect \m_valid_i \pimem_m_valid_i + connect \wb_dcache_en \wb_dcache_en + connect \x_addr_i \pimem_x_addr_i + connect \x_busy_o \pimem_x_busy_o + connect \x_ld_i \pimem_x_ld_i + connect \x_mask_i \pimem_x_mask_i + connect \x_st_data_i \pimem_x_st_data_i + connect \x_st_i \pimem_x_st_i + connect \x_valid_i \pimem_x_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:129094.9-129118.4" + cell \pimem \pimem + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \ldst_port0_addr_i \pimem_ldst_port0_addr_i + connect \ldst_port0_addr_i_ok \pimem_ldst_port0_addr_i_ok + connect \ldst_port0_addr_ok_o \pimem_ldst_port0_addr_ok_o + connect \ldst_port0_busy_o \pimem_ldst_port0_busy_o + connect \ldst_port0_data_len \pimem_ldst_port0_data_len + connect \ldst_port0_exc_$signal \pimem_ldst_port0_exc_$signal + connect \ldst_port0_is_ld_i \pimem_ldst_port0_is_ld_i + connect \ldst_port0_is_st_i \pimem_ldst_port0_is_st_i + connect \ldst_port0_ld_data_o \pimem_ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o_ok \pimem_ldst_port0_ld_data_o_ok + connect \ldst_port0_st_data_i \pimem_ldst_port0_st_data_i + connect \ldst_port0_st_data_i_ok \pimem_ldst_port0_st_data_i_ok + connect \m_ld_data_o \pimem_m_ld_data_o + connect \m_valid_i \pimem_m_valid_i + connect \x_addr_i \pimem_x_addr_i + connect \x_busy_o \pimem_x_busy_o + connect \x_ld_i \pimem_x_ld_i + connect \x_mask_i \pimem_x_mask_i + connect \x_st_data_i \pimem_x_st_data_i + connect \x_st_i \pimem_x_st_i + connect \x_valid_i \pimem_x_valid_i + end + connect \pimem_ldst_port0_exc_$signal 1'0 end -attribute \src "libresoc.v:41243.1-41548.10" +attribute \src "libresoc.v:129124.1-129532.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in" +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0" attribute \generator "nMigen" -module \dec_cr_in - attribute \src "libresoc.v:41442.3-41468.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:41469.3-41479.6" - wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:41420.3-41430.6" - wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:41480.3-41490.6" - wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:41491.3-41501.6" - wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:41393.3-41419.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:41529.3-41547.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:41431.3-41441.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:41244.7-41244.20" +module \l0$130 + attribute \src "libresoc.v:129387.3-129401.6" + wire $0\idx_l$23$next[0:0]$5840 + attribute \src "libresoc.v:129287.3-129288.35" + wire $0\idx_l$23[0:0]$5807 + attribute \src "libresoc.v:129145.7-129145.24" + wire $0\idx_l$23[0:0]$5862 + attribute \src "libresoc.v:129442.3-129451.6" + wire $0\idx_l_r_idx_l[0:0] + attribute \src "libresoc.v:129432.3-129441.6" + wire $0\idx_l_s_idx_l[0:0] + attribute \src "libresoc.v:129125.7-129125.20" wire $0\initial[0:0] - attribute \src "libresoc.v:41502.3-41512.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:41513.3-41528.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:41442.3-41468.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:41469.3-41479.6" - wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:41420.3-41430.6" - wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:41480.3-41490.6" - wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:41491.3-41501.6" - wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:41393.3-41419.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:41529.3-41547.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:41431.3-41441.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:41502.3-41512.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:41513.3-41528.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:41529.3-41547.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:41513.3-41528.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:41386.17-41386.112" - wire $and$libresoc.v:41386$942_Y - attribute \src "libresoc.v:41388.17-41388.112" - wire $and$libresoc.v:41388$944_Y - attribute \src "libresoc.v:41385.17-41385.117" - wire $eq$libresoc.v:41385$941_Y - attribute \src "libresoc.v:41387.17-41387.117" - wire $eq$libresoc.v:41387$943_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 12 \BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 11 \BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 16 \BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 15 \BI - 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$1\ldst_port0_st_data_i_ok$17[0:0]$5818 + attribute \src "libresoc.v:129272.7-129272.25" + wire $1\reset_delay[0:0] + attribute \src "libresoc.v:129467.3-129476.6" + wire $1\reset_l_r_reset[0:0] + attribute \src "libresoc.v:129452.3-129466.6" + wire $1\reset_l_s_reset[0:0] + attribute \src "libresoc.v:129387.3-129401.6" + wire $2\idx_l$23$next[0:0]$5842 + attribute \src "libresoc.v:129452.3-129466.6" + wire $2\reset_l_s_reset[0:0] + attribute \src "libresoc.v:129283.18-129283.103" + wire $not$libresoc.v:129283$5803_Y + attribute \src "libresoc.v:129284.18-129284.118" + wire $not$libresoc.v:129284$5804_Y + attribute \src "libresoc.v:129281.18-129281.134" + wire $or$libresoc.v:129281$5801_Y + attribute \src "libresoc.v:129282.18-129282.120" + wire $ternary$libresoc.v:129282$5802_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire \$22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:136" + wire width 96 \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:136" + wire width 96 \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 33 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire \idx_l$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire \idx_l$23$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \idx_l_q_idx_l + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \ldst_port0_exc_$signal$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \ldst_port0_exc_$signal$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \ldst_port0_exc_$signal$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 12 \ldst_port0_exc_$signal$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 13 \ldst_port0_exc_$signal$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 14 \ldst_port0_exc_$signal$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 15 \ldst_port0_exc_$signal$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" + wire \ldst_port0_go_die_i + attribute \src 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attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $and $and$libresoc.v:41386$942 + wire input 29 \ldst_port0_ld_data_o_ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:126" + wire \ldst_port0_ldst_error + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:126" + wire \ldst_port0_ldst_error$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:123" + wire \ldst_port0_mmu_done + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:123" + wire \ldst_port0_mmu_done$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 19 \ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 31 \ldst_port0_st_data_i$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 20 \ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 30 \ldst_port0_st_data_i_ok$17 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire \pick_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire \pick_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire \pick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:292" + wire \reset_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:292" + wire \reset_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \reset_l_q_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \reset_l_r_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \reset_l_s_reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" + cell $not $not$libresoc.v:129283$5803 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \move_one - connect \Y $and$libresoc.v:41386$942_Y + connect \A \pick_n + connect \Y $not$libresoc.v:129283$5803_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $and $and$libresoc.v:41388$944 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" + cell $not $not$libresoc.v:129284$5804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \move_one - connect \Y $and$libresoc.v:41388$944_Y + connect \A \ldst_port0_busy_o$10 + connect \Y $not$libresoc.v:129284$5804_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $eq $eq$libresoc.v:41385$941 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" + cell $or $or$libresoc.v:129281$5801 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:41385$941_Y + connect \A \ldst_port0_is_ld_i + connect \B \ldst_port0_is_st_i + connect \Y $or$libresoc.v:129281$5801_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $eq $eq$libresoc.v:41387$943 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:41387$943_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:129282$5802 + parameter \WIDTH 1 + connect \A \idx_l$23 + connect \B \pick_o + connect \S \idx_l_q_idx_l + connect \Y $ternary$libresoc.v:129282$5802_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:41389.9-41392.4" - cell \ppick \ppick - connect \i \ppick_i - connect \o \ppick_o + attribute \src "libresoc.v:129289.9-129295.4" + cell \idx_l \idx_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_idx_l \idx_l_q_idx_l + connect \r_idx_l \idx_l_r_idx_l + connect \s_idx_l \idx_l_s_idx_l + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:129296.8-129300.4" + cell \pick \pick + connect \i \pick_i + connect \n \pick_n + connect \o \pick_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:129301.17-129307.4" + cell \reset_l$131 \reset_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_reset \reset_l_q_reset + connect \r_reset \reset_l_r_reset + connect \s_reset \reset_l_s_reset end - attribute \src "libresoc.v:41244.7-41244.20" - process $proc$libresoc.v:41244$955 + attribute \src "libresoc.v:129125.7-129125.20" + process $proc$libresoc.v:129125$5860 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:41393.3-41419.6" - process $proc$libresoc.v:41393$945 + attribute \src "libresoc.v:129145.7-129145.24" + process $proc$libresoc.v:129145$5861 assign { } { } + assign $0\idx_l$23[0:0]$5862 1'0 + sync always + sync init + update \idx_l$23 $0\idx_l$23[0:0]$5862 + end + attribute \src "libresoc.v:129272.7-129272.25" + process $proc$libresoc.v:129272$5863 assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:41394.5-41394.29" - switch \initial - attribute \src "libresoc.v:41394.9-41394.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end + assign $1\reset_delay[0:0] 1'0 sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + sync init + update \reset_delay $1\reset_delay[0:0] + end + attribute \src "libresoc.v:129285.3-129286.36" + process $proc$libresoc.v:129285$5805 + assign { } { } + assign $0\reset_delay[0:0] \reset_l_q_reset + sync posedge \coresync_clk + update \reset_delay $0\reset_delay[0:0] + end + attribute \src "libresoc.v:129287.3-129288.35" + process $proc$libresoc.v:129287$5806 + assign { } { } + assign $0\idx_l$23[0:0]$5807 \idx_l$23$next + sync posedge \coresync_clk + update \idx_l$23 $0\idx_l$23[0:0]$5807 end - attribute \src "libresoc.v:41420.3-41430.6" - process $proc$libresoc.v:41420$946 + attribute \src "libresoc.v:129308.3-129317.6" + process $proc$libresoc.v:129308$5808 assign { } { } assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:41421.5-41421.29" + assign $0\ldst_port0_addr_i$12[47:0]$5809 $1\ldst_port0_addr_i$12[47:0]$5810 + attribute \src "libresoc.v:129309.5-129309.29" switch \initial - attribute \src "libresoc.v:41421.9-41421.17" + attribute \src "libresoc.v:129309.9-129309.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 1'1 assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 + assign $1\ldst_port0_addr_i$12[47:0]$5810 \$32 [47:0] case - assign $1\cr_bitfield_b_ok[0:0] 1'0 + assign $1\ldst_port0_addr_i$12[47:0]$5810 48'000000000000000000000000000000000000000000000000 end sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + update \ldst_port0_addr_i$12 $0\ldst_port0_addr_i$12[47:0]$5809 end - attribute \src "libresoc.v:41431.3-41441.6" - process $proc$libresoc.v:41431$947 + attribute \src "libresoc.v:129318.3-129327.6" + process $proc$libresoc.v:129318$5811 assign { } { } assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:41432.5-41432.29" + assign $0\ldst_port0_addr_i_ok$13[0:0]$5812 $1\ldst_port0_addr_i_ok$13[0:0]$5813 + attribute \src "libresoc.v:129319.5-129319.29" switch \initial - attribute \src "libresoc.v:41432.9-41432.17" + attribute \src "libresoc.v:129319.9-129319.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 1'1 assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 + assign $1\ldst_port0_addr_i_ok$13[0:0]$5813 \ldst_port0_addr_i_ok case - assign $1\cr_fxm_ok[0:0] 1'0 + assign $1\ldst_port0_addr_i_ok$13[0:0]$5813 1'0 end sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] + update \ldst_port0_addr_i_ok$13 $0\ldst_port0_addr_i_ok$13[0:0]$5812 end - attribute \src "libresoc.v:41442.3-41468.6" - process $proc$libresoc.v:41442$948 + attribute \src "libresoc.v:129328.3-129338.6" + process $proc$libresoc.v:129328$5814 assign { } { } assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:41443.5-41443.29" + assign { } { } + assign { } { } + assign $0\ldst_port0_st_data_i$18[63:0]$5815 $1\ldst_port0_st_data_i$18[63:0]$5817 + assign $0\ldst_port0_st_data_i_ok$17[0:0]$5816 $1\ldst_port0_st_data_i_ok$17[0:0]$5818 + attribute \src "libresoc.v:129329.5-129329.29" switch \initial - attribute \src "libresoc.v:41443.9-41443.17" + attribute \src "libresoc.v:129329.9-129329.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \BI [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 1'1 assign { } { } - assign $1\cr_bitfield[2:0] \BA [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'101 assign { } { } - assign $1\cr_bitfield[2:0] \BC [4:2] + assign { $1\ldst_port0_st_data_i_ok$17[0:0]$5818 $1\ldst_port0_st_data_i$18[63:0]$5817 } { \ldst_port0_st_data_i_ok \ldst_port0_st_data_i } case - assign $1\cr_bitfield[2:0] 3'000 + assign $1\ldst_port0_st_data_i$18[63:0]$5817 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\ldst_port0_st_data_i_ok$17[0:0]$5818 1'0 end sync always - update \cr_bitfield $0\cr_bitfield[2:0] + update \ldst_port0_st_data_i$18 $0\ldst_port0_st_data_i$18[63:0]$5815 + update \ldst_port0_st_data_i_ok$17 $0\ldst_port0_st_data_i_ok$17[0:0]$5816 end - attribute \src "libresoc.v:41469.3-41479.6" - process $proc$libresoc.v:41469$949 + attribute \src "libresoc.v:129339.3-129349.6" + process $proc$libresoc.v:129339$5819 assign { } { } assign { } { } - assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:41470.5-41470.29" + assign { } { } + assign { } { } + assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] + assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] + attribute \src "libresoc.v:129340.5-129340.29" switch \initial - attribute \src "libresoc.v:41470.9-41470.17" + attribute \src "libresoc.v:129340.9-129340.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 1'1 assign { } { } - assign $1\cr_bitfield_b[2:0] \BB [4:2] + assign { } { } + assign { $1\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o[63:0] } { \ldst_port0_ld_data_o_ok$16 \ldst_port0_ld_data_o$15 } case - assign $1\cr_bitfield_b[2:0] 3'000 + assign $1\ldst_port0_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\ldst_port0_ld_data_o_ok[0:0] 1'0 end sync always - update \cr_bitfield_b $0\cr_bitfield_b[2:0] + update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] + update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] end - attribute \src "libresoc.v:41480.3-41490.6" - process $proc$libresoc.v:41480$950 + attribute \src "libresoc.v:129350.3-129359.6" + process $proc$libresoc.v:129350$5820 assign { } { } assign { } { } - assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:41481.5-41481.29" + assign $0\ldst_port0_busy_o[0:0] $1\ldst_port0_busy_o[0:0] + attribute \src "libresoc.v:129351.5-129351.29" switch \initial - attribute \src "libresoc.v:41481.9-41481.17" + attribute \src "libresoc.v:129351.9-129351.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 1'1 assign { } { } - assign $1\cr_bitfield_o[2:0] \BT [4:2] + assign $1\ldst_port0_busy_o[0:0] \ldst_port0_busy_o$10 case - assign $1\cr_bitfield_o[2:0] 3'000 + assign $1\ldst_port0_busy_o[0:0] 1'0 end sync always - update \cr_bitfield_o $0\cr_bitfield_o[2:0] + update \ldst_port0_busy_o $0\ldst_port0_busy_o[0:0] end - attribute \src "libresoc.v:41491.3-41501.6" - process $proc$libresoc.v:41491$951 + attribute \src "libresoc.v:129360.3-129369.6" + process $proc$libresoc.v:129360$5821 assign { } { } assign { } { } - assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:41492.5-41492.29" + assign $0\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] + attribute \src "libresoc.v:129361.5-129361.29" switch \initial - attribute \src "libresoc.v:41492.9-41492.17" + attribute \src "libresoc.v:129361.9-129361.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 1'1 assign { } { } - assign $1\cr_bitfield_o_ok[0:0] 1'1 + assign $1\ldst_port0_addr_ok_o[0:0] \ldst_port0_addr_ok_o$14 case - assign $1\cr_bitfield_o_ok[0:0] 1'0 + assign $1\ldst_port0_addr_ok_o[0:0] 1'0 end sync always - update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] end - attribute \src "libresoc.v:41502.3-41512.6" - process $proc$libresoc.v:41502$952 + attribute \src "libresoc.v:129370.3-129386.6" + process $proc$libresoc.v:129370$5822 assign { } { } assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:41503.5-41503.29" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\ldst_port0_exc_$signal[0:0]$5823 $1\ldst_port0_exc_$signal[0:0]$5831 + assign $0\ldst_port0_exc_$signal$1[0:0]$5824 $1\ldst_port0_exc_$signal$1[0:0]$5832 + assign $0\ldst_port0_exc_$signal$2[0:0]$5825 $1\ldst_port0_exc_$signal$2[0:0]$5833 + assign $0\ldst_port0_exc_$signal$3[0:0]$5826 $1\ldst_port0_exc_$signal$3[0:0]$5834 + assign $0\ldst_port0_exc_$signal$4[0:0]$5827 $1\ldst_port0_exc_$signal$4[0:0]$5835 + assign $0\ldst_port0_exc_$signal$5[0:0]$5828 $1\ldst_port0_exc_$signal$5[0:0]$5836 + assign $0\ldst_port0_exc_$signal$6[0:0]$5829 $1\ldst_port0_exc_$signal$6[0:0]$5837 + assign $0\ldst_port0_exc_$signal$7[0:0]$5830 $1\ldst_port0_exc_$signal$7[0:0]$5838 + attribute \src "libresoc.v:129371.5-129371.29" switch \initial - attribute \src "libresoc.v:41503.9-41503.17" + attribute \src "libresoc.v:129371.9-129371.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 1'1 assign { } { } - assign $1\move_one[0:0] \insn_in [20] + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\ldst_port0_exc_$signal$7[0:0]$5838 $1\ldst_port0_exc_$signal$6[0:0]$5837 $1\ldst_port0_exc_$signal$5[0:0]$5836 $1\ldst_port0_exc_$signal$4[0:0]$5835 $1\ldst_port0_exc_$signal$3[0:0]$5834 $1\ldst_port0_exc_$signal$2[0:0]$5833 $1\ldst_port0_exc_$signal$1[0:0]$5832 $1\ldst_port0_exc_$signal[0:0]$5831 } { \ldst_port0_exc_$signal$39 \ldst_port0_exc_$signal$38 \ldst_port0_exc_$signal$37 \ldst_port0_exc_$signal$36 \ldst_port0_exc_$signal$35 \ldst_port0_exc_$signal$34 \ldst_port0_exc_$signal$33 \ldst_port0_exc_$signal$19 } case - assign $1\move_one[0:0] 1'0 + assign $1\ldst_port0_exc_$signal[0:0]$5831 1'0 + assign $1\ldst_port0_exc_$signal$1[0:0]$5832 1'0 + assign $1\ldst_port0_exc_$signal$2[0:0]$5833 1'0 + assign $1\ldst_port0_exc_$signal$3[0:0]$5834 1'0 + assign $1\ldst_port0_exc_$signal$4[0:0]$5835 1'0 + assign $1\ldst_port0_exc_$signal$5[0:0]$5836 1'0 + assign $1\ldst_port0_exc_$signal$6[0:0]$5837 1'0 + assign $1\ldst_port0_exc_$signal$7[0:0]$5838 1'0 end sync always - update \move_one $0\move_one[0:0] + update \ldst_port0_exc_$signal $0\ldst_port0_exc_$signal[0:0]$5823 + update \ldst_port0_exc_$signal$1 $0\ldst_port0_exc_$signal$1[0:0]$5824 + update \ldst_port0_exc_$signal$2 $0\ldst_port0_exc_$signal$2[0:0]$5825 + update \ldst_port0_exc_$signal$3 $0\ldst_port0_exc_$signal$3[0:0]$5826 + update \ldst_port0_exc_$signal$4 $0\ldst_port0_exc_$signal$4[0:0]$5827 + update \ldst_port0_exc_$signal$5 $0\ldst_port0_exc_$signal$5[0:0]$5828 + update \ldst_port0_exc_$signal$6 $0\ldst_port0_exc_$signal$6[0:0]$5829 + update \ldst_port0_exc_$signal$7 $0\ldst_port0_exc_$signal$7[0:0]$5830 end - attribute \src "libresoc.v:41513.3-41528.6" - process $proc$libresoc.v:41513$953 + attribute \src "libresoc.v:129387.3-129401.6" + process $proc$libresoc.v:129387$5839 assign { } { } assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:41514.5-41514.29" + assign { } { } + assign $0\idx_l$23$next[0:0]$5840 $2\idx_l$23$next[0:0]$5842 + attribute \src "libresoc.v:129388.5-129388.29" switch \initial - attribute \src "libresoc.v:41514.9-41514.17" + attribute \src "libresoc.v:129388.9-129388.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] \FXM - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "libresoc.v:41529.3-41547.6" - process $proc$libresoc.v:41529$954 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:41530.5-41530.29" - switch \initial - attribute \src "libresoc.v:41530.9-41530.17" case 1'1 + assign { } { } + assign $1\idx_l$23$next[0:0]$5841 \pick_o case + assign $1\idx_l$23$next[0:0]$5841 \idx_l$23 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 1'1 assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - switch \$7 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end + assign $2\idx_l$23$next[0:0]$5842 1'0 case - assign $1\cr_fxm[7:0] 8'00000000 + assign $2\idx_l$23$next[0:0]$5842 $1\idx_l$23$next[0:0]$5841 end sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$libresoc.v:41385$941_Y - connect \$3 $and$libresoc.v:41386$942_Y - connect \$5 $eq$libresoc.v:41387$943_Y - connect \$7 $and$libresoc.v:41388$944_Y -end -attribute \src "libresoc.v:41552.1-41795.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out" -attribute \generator "nMigen" -module \dec_cr_out - attribute \src "libresoc.v:41709.3-41727.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:41679.3-41697.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:41760.3-41794.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:41698.3-41708.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:41553.7-41553.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:41728.3-41738.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:41739.3-41759.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:41709.3-41727.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:41679.3-41697.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:41760.3-41794.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:41698.3-41708.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:41728.3-41738.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:41739.3-41759.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:41760.3-41794.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:41739.3-41759.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:41760.3-41794.6" - wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:41739.3-41759.6" - wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:41760.3-41794.6" - wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:41672.17-41672.117" - wire $eq$libresoc.v:41672$956_Y - attribute \src "libresoc.v:41673.17-41673.117" - wire $eq$libresoc.v:41673$957_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 input 8 \FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 input 10 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 input 9 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 output 6 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 7 \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 output 4 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 5 \cr_fxm_ok - attribute \src "libresoc.v:41553.7-41553.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" - wire width 32 input 11 \insn_in - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 3 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" - wire input 2 \rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - cell $eq $eq$libresoc.v:41672$956 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:41672$956_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - cell $eq $eq$libresoc.v:41673$957 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:41673$957_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:41674.13-41678.4" - cell \ppick$1 \ppick - connect \en_o \ppick_en_o - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "libresoc.v:41553.7-41553.20" - process $proc$libresoc.v:41553$964 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + update \idx_l$23$next $0\idx_l$23$next[0:0]$5840 end - attribute \src "libresoc.v:41679.3-41697.6" - process $proc$libresoc.v:41679$958 + attribute \src "libresoc.v:129402.3-129411.6" + process $proc$libresoc.v:129402$5843 assign { } { } assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:41680.5-41680.29" + assign $0\ldst_port0_mmu_done[0:0] $1\ldst_port0_mmu_done[0:0] + attribute \src "libresoc.v:129403.5-129403.29" switch \initial - attribute \src "libresoc.v:41680.9-41680.17" + attribute \src "libresoc.v:129403.9-129403.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 1'1 assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 + assign $1\ldst_port0_mmu_done[0:0] \ldst_port0_mmu_done$40 case - assign $1\cr_bitfield_ok[0:0] 1'0 + assign $1\ldst_port0_mmu_done[0:0] 1'0 end sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + update \ldst_port0_mmu_done $0\ldst_port0_mmu_done[0:0] end - attribute \src "libresoc.v:41698.3-41708.6" - process $proc$libresoc.v:41698$959 + attribute \src "libresoc.v:129412.3-129421.6" + process $proc$libresoc.v:129412$5844 assign { } { } assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:41699.5-41699.29" + assign $0\ldst_port0_ldst_error[0:0] $1\ldst_port0_ldst_error[0:0] + attribute \src "libresoc.v:129413.5-129413.29" switch \initial - attribute \src "libresoc.v:41699.9-41699.17" + attribute \src "libresoc.v:129413.9-129413.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 1'1 assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 + assign $1\ldst_port0_ldst_error[0:0] \ldst_port0_ldst_error$41 case - assign $1\cr_fxm_ok[0:0] 1'0 + assign $1\ldst_port0_ldst_error[0:0] 1'0 end sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] + update \ldst_port0_ldst_error $0\ldst_port0_ldst_error[0:0] end - attribute \src "libresoc.v:41709.3-41727.6" - process $proc$libresoc.v:41709$960 + attribute \src "libresoc.v:129422.3-129431.6" + process $proc$libresoc.v:129422$5845 assign { } { } assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:41710.5-41710.29" + assign $0\ldst_port0_cache_paradox[0:0] $1\ldst_port0_cache_paradox[0:0] + attribute \src "libresoc.v:129423.5-129423.29" switch \initial - attribute \src "libresoc.v:41710.9-41710.17" + attribute \src "libresoc.v:129423.9-129423.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 1'1 assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] + assign $1\ldst_port0_cache_paradox[0:0] \ldst_port0_cache_paradox$42 case - assign $1\cr_bitfield[2:0] 3'000 + assign $1\ldst_port0_cache_paradox[0:0] 1'0 end sync always - update \cr_bitfield $0\cr_bitfield[2:0] + update \ldst_port0_cache_paradox $0\ldst_port0_cache_paradox[0:0] end - attribute \src "libresoc.v:41728.3-41738.6" - process $proc$libresoc.v:41728$961 + attribute \src "libresoc.v:129432.3-129441.6" + process $proc$libresoc.v:129432$5846 assign { } { } assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:41729.5-41729.29" + assign $0\idx_l_s_idx_l[0:0] $1\idx_l_s_idx_l[0:0] + attribute \src "libresoc.v:129433.5-129433.29" switch \initial - attribute \src "libresoc.v:41729.9-41729.17" + attribute \src "libresoc.v:129433.9-129433.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" + switch \$26 attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 1'1 assign { } { } - assign $1\move_one[0:0] \insn_in [20] + assign $1\idx_l_s_idx_l[0:0] 1'1 case - assign $1\move_one[0:0] 1'0 + assign $1\idx_l_s_idx_l[0:0] 1'0 end sync always - update \move_one $0\move_one[0:0] + update \idx_l_s_idx_l $0\idx_l_s_idx_l[0:0] end - attribute \src "libresoc.v:41739.3-41759.6" - process $proc$libresoc.v:41739$962 + attribute \src "libresoc.v:129442.3-129451.6" + process $proc$libresoc.v:129442$5847 assign { } { } assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:41740.5-41740.29" + assign $0\idx_l_r_idx_l[0:0] $1\idx_l_r_idx_l[0:0] + attribute \src "libresoc.v:129443.5-129443.29" switch \initial - attribute \src "libresoc.v:41740.9-41740.17" + attribute \src "libresoc.v:129443.9-129443.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:296" + switch \reset_l_q_reset attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 1'1 assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ppick_i[7:0] \FXM - case - assign $3\ppick_i[7:0] 8'00000000 - end - case - assign $2\ppick_i[7:0] 8'00000000 - end + assign $1\idx_l_r_idx_l[0:0] 1'1 case - assign $1\ppick_i[7:0] 8'00000000 + assign $1\idx_l_r_idx_l[0:0] 1'1 end sync always - update \ppick_i $0\ppick_i[7:0] + update \idx_l_r_idx_l $0\idx_l_r_idx_l[0:0] end - attribute \src "libresoc.v:41760.3-41794.6" - process $proc$libresoc.v:41760$963 + attribute \src "libresoc.v:129452.3-129466.6" + process $proc$libresoc.v:129452$5848 assign { } { } assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:41761.5-41761.29" + assign $0\reset_l_s_reset[0:0] $1\reset_l_s_reset[0:0] + attribute \src "libresoc.v:129453.5-129453.29" switch \initial - attribute \src "libresoc.v:41761.9-41761.17" + attribute \src "libresoc.v:129453.9-129453.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 1'1 assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \$3 + assign $1\reset_l_s_reset[0:0] $2\reset_l_s_reset[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" + switch \$28 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" - switch \ppick_en_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cr_fxm[7:0] \ppick_o - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 10 output 4 \spr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 5 \spr_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \sprmap_fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \sprmap_fast_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62" - wire width 10 \sprmap_spr_i - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" - attribute \enum_value_0000010010 "DSISR" - attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" - attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" - attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" - attribute \enum_value_0100010000 "SPRG0_priv" - attribute \enum_value_0100010001 "SPRG1_priv" - attribute \enum_value_0100010010 "SPRG2_priv" - attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 10 \sprmap_spr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \sprmap_spr_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" - cell $eq $eq$libresoc.v:42152$965 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0110001 - connect \Y $eq$libresoc.v:42152$965_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" - cell $eq $eq$libresoc.v:42153$966 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0110001 - connect \Y $eq$libresoc.v:42153$966_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" - cell $eq $eq$libresoc.v:42154$967 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0110001 - connect \Y $eq$libresoc.v:42154$967_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" - cell $not $not$libresoc.v:42155$968 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \BO [2] - connect \Y $not$libresoc.v:42155$968_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:42156.14-42162.4" - cell \sprmap$2 \sprmap - connect \fast_o \sprmap_fast_o - connect \fast_o_ok \sprmap_fast_o_ok - connect \spr_i \sprmap_spr_i - connect \spr_o \sprmap_spr_o - connect \spr_o_ok \sprmap_spr_o_ok - end - attribute \src "libresoc.v:41800.7-41800.20" - process $proc$libresoc.v:41800$975 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + update \reset_l_s_reset $0\reset_l_s_reset[0:0] end - attribute \src "libresoc.v:42163.3-42177.6" - process $proc$libresoc.v:42163$969 + attribute \src "libresoc.v:129467.3-129476.6" + process $proc$libresoc.v:129467$5849 assign { } { } assign { } { } - assign $0\reg_o[4:0] $1\reg_o[4:0] - attribute \src "libresoc.v:42164.5-42164.29" + assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] + attribute \src "libresoc.v:129468.5-129468.29" switch \initial - attribute \src "libresoc.v:42164.9-42164.17" + attribute \src "libresoc.v:129468.9-129468.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\reg_o[4:0] \RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:296" + switch \reset_l_q_reset attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 1'1 assign { } { } - assign $1\reg_o[4:0] \RA + assign $1\reset_l_r_reset[0:0] 1'1 case - assign $1\reg_o[4:0] 5'00000 + assign $1\reset_l_r_reset[0:0] 1'0 end sync always - update \reg_o $0\reg_o[4:0] + update \reset_l_r_reset $0\reset_l_r_reset[0:0] end - attribute \src "libresoc.v:42178.3-42192.6" - process $proc$libresoc.v:42178$970 + attribute \src "libresoc.v:129477.3-129486.6" + process $proc$libresoc.v:129477$5850 assign { } { } assign { } { } - assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0] - attribute \src "libresoc.v:42179.5-42179.29" + assign $0\ldst_port0_is_ld_i$8[0:0]$5851 $1\ldst_port0_is_ld_i$8[0:0]$5852 + attribute \src "libresoc.v:129478.5-129478.29" switch \initial - attribute \src "libresoc.v:42179.9-42179.17" + attribute \src "libresoc.v:129478.9-129478.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\reg_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 1'1 assign { } { } - assign $1\reg_o_ok[0:0] 1'1 + assign $1\ldst_port0_is_ld_i$8[0:0]$5852 \ldst_port0_is_ld_i case - assign $1\reg_o_ok[0:0] 1'0 + assign $1\ldst_port0_is_ld_i$8[0:0]$5852 1'0 end sync always - update \reg_o_ok $0\reg_o_ok[0:0] + update \ldst_port0_is_ld_i$8 $0\ldst_port0_is_ld_i$8[0:0]$5851 end - attribute \src "libresoc.v:42193.3-42203.6" - process $proc$libresoc.v:42193$971 + attribute \src "libresoc.v:129487.3-129496.6" + process $proc$libresoc.v:129487$5853 assign { } { } assign { } { } - assign $0\spr[9:0] $1\spr[9:0] - attribute \src "libresoc.v:42194.5-42194.29" + assign $0\ldst_port0_is_st_i$9[0:0]$5854 $1\ldst_port0_is_st_i$9[0:0]$5855 + attribute \src "libresoc.v:129488.5-129488.29" switch \initial - attribute \src "libresoc.v:42194.9-42194.17" + attribute \src "libresoc.v:129488.9-129488.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 1'1 assign { } { } - assign $1\spr[9:0] { \SPR [4:0] \SPR [9:5] } + assign $1\ldst_port0_is_st_i$9[0:0]$5855 \ldst_port0_is_st_i case - assign $1\spr[9:0] 10'0000000000 + assign $1\ldst_port0_is_st_i$9[0:0]$5855 1'0 end sync always - update \spr $0\spr[9:0] + update \ldst_port0_is_st_i$9 $0\ldst_port0_is_st_i$9[0:0]$5854 end - attribute \src "libresoc.v:42204.3-42219.6" - process $proc$libresoc.v:42204$972 + attribute \src "libresoc.v:129497.3-129506.6" + process $proc$libresoc.v:129497$5856 assign { } { } assign { } { } - assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:42205.5-42205.29" + assign $0\ldst_port0_data_len$11[3:0]$5857 $1\ldst_port0_data_len$11[3:0]$5858 + attribute \src "libresoc.v:129498.5-129498.29" switch \initial - attribute \src "libresoc.v:42205.9-42205.17" + attribute \src "libresoc.v:129498.9-129498.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 1'1 assign { } { } - assign $1\sprmap_spr_i[9:0] $2\sprmap_spr_i[9:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\sprmap_spr_i[9:0] \spr - case - assign $2\sprmap_spr_i[9:0] 10'0000000000 - end + assign $1\ldst_port0_data_len$11[3:0]$5858 \ldst_port0_data_len case - assign $1\sprmap_spr_i[9:0] 10'0000000000 + assign $1\ldst_port0_data_len$11[3:0]$5858 4'0000 end sync always - update \sprmap_spr_i $0\sprmap_spr_i[9:0] + update \ldst_port0_data_len$11 $0\ldst_port0_data_len$11[3:0]$5857 end - attribute \src "libresoc.v:42220.3-42236.6" - process $proc$libresoc.v:42220$973 - assign { } { } - assign { } { } + attribute \src "libresoc.v:129507.3-129516.6" + process $proc$libresoc.v:129507$5859 assign { } { } assign { } { } - assign $0\spr_o[9:0] $1\spr_o[9:0] - assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "libresoc.v:42221.5-42221.29" + assign $0\ldst_port0_go_die_i[0:0] $1\ldst_port0_go_die_i[0:0] + attribute \src "libresoc.v:129508.5-129508.29" switch \initial - attribute \src "libresoc.v:42221.9-42221.17" + attribute \src "libresoc.v:129508.9-129508.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" - case 2'11 - assign { } { } + case 1'1 assign { } { } - assign $1\spr_o[9:0] $2\spr_o[9:0] - assign $1\spr_o_ok[0:0] $2\spr_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\spr_o_ok[0:0] $2\spr_o[9:0] } { \sprmap_spr_o_ok \sprmap_spr_o } - case - assign $2\spr_o[9:0] 10'0000000000 - assign $2\spr_o_ok[0:0] 1'0 - end + assign $1\ldst_port0_go_die_i[0:0] \ldst_port0_go_die_i$30 case - assign $1\spr_o[9:0] 10'0000000000 - assign $1\spr_o_ok[0:0] 1'0 + assign $1\ldst_port0_go_die_i[0:0] 1'0 end sync always - update \spr_o $0\spr_o[9:0] - update \spr_o_ok $0\spr_o_ok[0:0] + update \ldst_port0_go_die_i $0\ldst_port0_go_die_i[0:0] end - attribute \src "libresoc.v:42237.3-42275.6" - process $proc$libresoc.v:42237$974 - assign { } { } + connect \$20 $or$libresoc.v:129281$5801_Y + connect \$24 $ternary$libresoc.v:129282$5802_Y + connect \$26 $not$libresoc.v:129283$5803_Y + connect \$28 $not$libresoc.v:129284$5804_Y + connect \$22 \$24 + connect \$32 \ldst_port0_addr_i + connect \ldst_port0_go_die_i$30 1'0 + connect \ldst_port0_exc_$signal$33 1'0 + connect \ldst_port0_exc_$signal$34 1'0 + connect \ldst_port0_exc_$signal$35 1'0 + connect \ldst_port0_exc_$signal$36 1'0 + connect \ldst_port0_exc_$signal$37 1'0 + connect \ldst_port0_exc_$signal$38 1'0 + connect \ldst_port0_exc_$signal$39 1'0 + connect \ldst_port0_mmu_done$40 1'0 + connect \ldst_port0_ldst_error$41 1'0 + connect \ldst_port0_cache_paradox$42 1'0 + connect \reset_delay$next \reset_l_q_reset + connect \pick_i \$20 +end +attribute \src "libresoc.v:129536.1-129594.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.ld_active" +attribute \generator "nMigen" +module \ld_active + attribute \src "libresoc.v:129537.7-129537.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:129582.3-129590.6" + wire $0\q_int$next[0:0]$5874 + attribute \src "libresoc.v:129580.3-129581.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:129582.3-129590.6" + wire $1\q_int$next[0:0]$5875 + attribute \src "libresoc.v:129559.7-129559.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:129572.17-129572.96" + wire $and$libresoc.v:129572$5864_Y + attribute \src "libresoc.v:129577.17-129577.96" + wire $and$libresoc.v:129577$5869_Y + attribute \src "libresoc.v:129574.18-129574.99" + wire $not$libresoc.v:129574$5866_Y + attribute \src "libresoc.v:129576.17-129576.98" + wire $not$libresoc.v:129576$5868_Y + attribute \src "libresoc.v:129579.17-129579.98" + wire $not$libresoc.v:129579$5871_Y + attribute \src "libresoc.v:129573.18-129573.104" + wire $or$libresoc.v:129573$5865_Y + attribute \src "libresoc.v:129575.18-129575.105" + wire $or$libresoc.v:129575$5867_Y + attribute \src "libresoc.v:129578.17-129578.103" + wire $or$libresoc.v:129578$5870_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:129537.7-129537.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 2 \r_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 3 \s_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:129572$5864 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:129572$5864_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:129577$5869 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:129577$5869_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:129574$5866 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_ld_active + connect \Y $not$libresoc.v:129574$5866_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:129576$5868 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_ld_active + connect \Y $not$libresoc.v:129576$5868_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:129579$5871 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_ld_active + connect \Y $not$libresoc.v:129579$5871_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:129573$5865 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_ld_active + connect \Y $or$libresoc.v:129573$5865_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:129575$5867 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_ld_active + connect \B \q_int + connect \Y $or$libresoc.v:129575$5867_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:129578$5870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_ld_active + connect \Y $or$libresoc.v:129578$5870_Y + end + attribute \src "libresoc.v:129537.7-129537.20" + process $proc$libresoc.v:129537$5876 assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:129559.7-129559.19" + process $proc$libresoc.v:129559$5877 assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:129580.3-129581.27" + process $proc$libresoc.v:129580$5872 assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:129582.3-129590.6" + process $proc$libresoc.v:129582$5873 assign { } { } assign { } { } - assign $0\fast_o[2:0] $3\fast_o[2:0] - assign $0\fast_o_ok[0:0] $3\fast_o_ok[0:0] - attribute \src "libresoc.v:42238.5-42238.29" + assign $0\q_int$next[0:0]$5874 $1\q_int$next[0:0]$5875 + attribute \src "libresoc.v:129583.5-129583.29" switch \initial - attribute \src "libresoc.v:42238.9-42238.17" + attribute \src "libresoc.v:129583.9-129583.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'11 - assign { } { } - assign { } { } - assign $1\fast_o[2:0] $2\fast_o[2:0] - assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" - switch \$5 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\fast_o_ok[0:0] $2\fast_o[2:0] } { \sprmap_fast_o_ok \sprmap_fast_o } - case - assign $2\fast_o[2:0] 3'000 - assign $2\fast_o_ok[0:0] 1'0 - end - case - assign $1\fast_o[2:0] 3'000 - assign $1\fast_o_ok[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:340" - switch \internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0000111 , 7'0001000 - assign { } { } - assign { } { } - assign $3\fast_o[2:0] $4\fast_o[2:0] - assign $3\fast_o_ok[0:0] $4\fast_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" - switch \$7 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $4\fast_o[2:0] 3'000 - assign $4\fast_o_ok[0:0] 1'1 - case - assign $4\fast_o[2:0] $1\fast_o[2:0] - assign $4\fast_o_ok[0:0] $1\fast_o_ok[0:0] - end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 7'1000110 - assign { } { } + case 1'1 assign { } { } - assign $3\fast_o[2:0] 3'011 - assign $3\fast_o_ok[0:0] 1'1 + assign $1\q_int$next[0:0]$5875 1'0 case - assign $3\fast_o[2:0] $1\fast_o[2:0] - assign $3\fast_o_ok[0:0] $1\fast_o_ok[0:0] + assign $1\q_int$next[0:0]$5875 \$5 end sync always - update \fast_o $0\fast_o[2:0] - update \fast_o_ok $0\fast_o_ok[0:0] + update \q_int$next $0\q_int$next[0:0]$5874 end - connect \$1 $eq$libresoc.v:42152$965_Y - connect \$3 $eq$libresoc.v:42153$966_Y - connect \$5 $eq$libresoc.v:42154$967_Y - connect \$7 $not$libresoc.v:42155$968_Y + connect \$9 $and$libresoc.v:129572$5864_Y + connect \$11 $or$libresoc.v:129573$5865_Y + connect \$13 $not$libresoc.v:129574$5866_Y + connect \$15 $or$libresoc.v:129575$5867_Y + connect \$1 $not$libresoc.v:129576$5868_Y + connect \$3 $and$libresoc.v:129577$5869_Y + connect \$5 $or$libresoc.v:129578$5870_Y + connect \$7 $not$libresoc.v:129579$5871_Y + connect \qlq_ld_active \$15 + connect \qn_ld_active \$13 + connect \q_ld_active \$11 end -attribute \src "libresoc.v:42280.1-42441.10" +attribute \src "libresoc.v:129598.1-130955.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o2" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0" attribute \generator "nMigen" -module \dec_o2 - attribute \src "libresoc.v:42401.3-42420.6" - wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:42421.3-42440.6" - wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:42281.7-42281.20" +module \ldst0 + attribute \src "libresoc.v:130610.3-130618.6" + wire $0\adr_l_r_adr$next[0:0]$6020 + attribute \src "libresoc.v:130492.3-130493.39" + wire $0\adr_l_r_adr[0:0] + attribute \src "libresoc.v:130438.3-130439.21" + wire $0\alu_ok[0:0] + attribute \src "libresoc.v:130775.3-130784.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:130785.3-130794.6" + wire width 64 $0\dest2_o[63:0] + attribute \src "libresoc.v:130765.3-130774.6" + wire width 64 $0\ea_r$next[63:0]$6108 + attribute \src "libresoc.v:130440.3-130441.25" + wire width 64 $0\ea_r[63:0] + attribute \src "libresoc.v:129599.7-129599.20" wire $0\initial[0:0] - attribute \src "libresoc.v:42387.3-42400.6" - wire width 5 $0\reg_o[4:0] - attribute \src "libresoc.v:42387.3-42400.6" - wire $0\reg_o_ok[0:0] - attribute \src "libresoc.v:42401.3-42420.6" - wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:42421.3-42440.6" - wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:42387.3-42400.6" - wire width 5 $1\reg_o[4:0] - attribute \src "libresoc.v:42387.3-42400.6" - wire $1\reg_o_ok[0:0] - attribute \src "libresoc.v:42401.3-42420.6" - wire width 3 $2\fast_o[2:0] - attribute \src "libresoc.v:42421.3-42440.6" - wire $2\fast_o_ok[0:0] - attribute \src "libresoc.v:42385.17-42385.108" - wire $eq$libresoc.v:42385$976_Y - attribute \src "libresoc.v:42386.17-42386.100" - wire width 6 $extend$libresoc.v:42386$977_Y - attribute \src "libresoc.v:42386.17-42386.100" - wire width 6 $pos$libresoc.v:42386$978_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:377" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 6 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 7 \RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 output 4 \fast_o + attribute \src "libresoc.v:130840.3-130859.6" + wire width 64 $0\ldd_o[63:0] + attribute \src "libresoc.v:130804.3-130827.6" + wire width 64 $0\lddata_r[63:0] + attribute \src "libresoc.v:130707.3-130716.6" + wire width 64 $0\ldo_r$next[63:0]$6093 + attribute \src "libresoc.v:130448.3-130449.27" + wire width 64 $0\ldo_r[63:0] + attribute \src "libresoc.v:130436.3-130437.33" + wire width 96 $0\ldst_port0_addr_i[95:0] + attribute \src "libresoc.v:130795.3-130803.6" + wire $0\ldst_port0_addr_i_ok$next[0:0]$6113 + attribute \src "libresoc.v:130434.3-130435.57" + wire $0\ldst_port0_addr_i_ok[0:0] + attribute \src "libresoc.v:130884.3-130895.6" + wire width 64 $0\ldst_port0_st_data_i[63:0] + attribute \src "libresoc.v:130655.3-130663.6" + wire $0\lsd_l_r_lsd$next[0:0]$6035 + attribute \src "libresoc.v:130482.3-130483.39" + wire $0\lsd_l_r_lsd[0:0] + attribute \src "libresoc.v:130583.3-130591.6" + wire $0\opc_l_r_opc$next[0:0]$6011 + attribute \src "libresoc.v:130498.3-130499.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:130574.3-130582.6" + wire $0\opc_l_s_opc$next[0:0]$6008 + attribute \src "libresoc.v:130500.3-130501.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:130664.3-130706.6" + wire $0\oper_r__byte_reverse$next[0:0]$6038 + attribute \src "libresoc.v:130474.3-130475.57" + wire $0\oper_r__byte_reverse[0:0] + attribute \src "libresoc.v:130664.3-130706.6" + wire width 4 $0\oper_r__data_len$next[3:0]$6039 + attribute \src "libresoc.v:130472.3-130473.49" + wire width 4 $0\oper_r__data_len[3:0] + attribute \src "libresoc.v:130664.3-130706.6" + wire width 12 $0\oper_r__fn_unit$next[11:0]$6040 + attribute \src "libresoc.v:130452.3-130453.47" + wire width 12 $0\oper_r__fn_unit[11:0] + attribute \src "libresoc.v:130664.3-130706.6" + wire width 64 $0\oper_r__imm_data__data$next[63:0]$6041 + attribute \src "libresoc.v:130454.3-130455.61" + wire width 64 $0\oper_r__imm_data__data[63:0] + attribute \src "libresoc.v:130664.3-130706.6" + wire $0\oper_r__imm_data__ok$next[0:0]$6042 + attribute \src "libresoc.v:130456.3-130457.57" + wire $0\oper_r__imm_data__ok[0:0] + attribute \src "libresoc.v:130664.3-130706.6" + wire width 32 $0\oper_r__insn$next[31:0]$6043 + attribute \src "libresoc.v:130480.3-130481.41" + wire width 32 $0\oper_r__insn[31:0] + attribute \src "libresoc.v:130664.3-130706.6" + wire width 7 $0\oper_r__insn_type$next[6:0]$6044 + attribute \src "libresoc.v:130450.3-130451.51" + wire width 7 $0\oper_r__insn_type[6:0] + attribute \src "libresoc.v:130664.3-130706.6" + wire $0\oper_r__is_32bit$next[0:0]$6045 + attribute \src "libresoc.v:130468.3-130469.49" + wire $0\oper_r__is_32bit[0:0] + attribute \src "libresoc.v:130664.3-130706.6" + wire $0\oper_r__is_signed$next[0:0]$6046 + attribute \src "libresoc.v:130470.3-130471.51" + wire $0\oper_r__is_signed[0:0] + attribute \src "libresoc.v:130664.3-130706.6" + wire width 2 $0\oper_r__ldst_mode$next[1:0]$6047 + attribute \src "libresoc.v:130478.3-130479.51" + wire width 2 $0\oper_r__ldst_mode[1:0] + attribute \src "libresoc.v:130664.3-130706.6" + wire $0\oper_r__oe__oe$next[0:0]$6048 + attribute \src "libresoc.v:130464.3-130465.45" + wire $0\oper_r__oe__oe[0:0] + attribute \src "libresoc.v:130664.3-130706.6" + wire $0\oper_r__oe__ok$next[0:0]$6049 + attribute \src "libresoc.v:130466.3-130467.45" + wire $0\oper_r__oe__ok[0:0] + attribute \src "libresoc.v:130664.3-130706.6" + wire $0\oper_r__rc__ok$next[0:0]$6050 + attribute \src "libresoc.v:130462.3-130463.45" + wire $0\oper_r__rc__ok[0:0] + attribute \src "libresoc.v:130664.3-130706.6" + wire $0\oper_r__rc__rc$next[0:0]$6051 + attribute \src "libresoc.v:130460.3-130461.45" + wire $0\oper_r__rc__rc[0:0] + attribute \src "libresoc.v:130664.3-130706.6" + wire $0\oper_r__sign_extend$next[0:0]$6052 + attribute \src "libresoc.v:130476.3-130477.55" + wire $0\oper_r__sign_extend[0:0] + attribute \src "libresoc.v:130664.3-130706.6" + wire $0\oper_r__zero_a$next[0:0]$6053 + attribute \src "libresoc.v:130458.3-130459.45" + wire $0\oper_r__zero_a[0:0] + attribute \src "libresoc.v:130502.3-130503.28" + wire $0\p_st_go[0:0] + attribute \src "libresoc.v:130828.3-130839.6" + wire width 64 $0\revnorev[63:0] + attribute \src "libresoc.v:130601.3-130609.6" + wire width 3 $0\src_l_r_src$next[2:0]$6017 + attribute \src "libresoc.v:130494.3-130495.39" + wire width 3 $0\src_l_r_src[2:0] + attribute \src "libresoc.v:130592.3-130600.6" + wire width 3 $0\src_l_s_src$next[2:0]$6014 + attribute \src "libresoc.v:130496.3-130497.39" + wire width 3 $0\src_l_s_src[2:0] + attribute \src "libresoc.v:130717.3-130732.6" + wire width 64 $0\src_r0$next[63:0]$6096 + attribute \src "libresoc.v:130446.3-130447.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:130733.3-130748.6" + wire width 64 $0\src_r1$next[63:0]$6100 + attribute \src "libresoc.v:130444.3-130445.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:130749.3-130764.6" + wire width 64 $0\src_r2$next[63:0]$6104 + attribute \src "libresoc.v:130442.3-130443.29" + wire width 64 $0\src_r2[63:0] + attribute \src "libresoc.v:130860.3-130883.6" + wire width 64 $0\stdata_r[63:0] + attribute \src "libresoc.v:130646.3-130654.6" + wire $0\sto_l_r_sto$next[0:0]$6032 + attribute \src "libresoc.v:130484.3-130485.39" + wire $0\sto_l_r_sto[0:0] + attribute \src "libresoc.v:130637.3-130645.6" + wire $0\upd_l_r_upd$next[0:0]$6029 + attribute \src "libresoc.v:130486.3-130487.39" + wire $0\upd_l_r_upd[0:0] + attribute \src "libresoc.v:130628.3-130636.6" + wire $0\upd_l_s_upd$next[0:0]$6026 + attribute \src "libresoc.v:130488.3-130489.39" + wire $0\upd_l_s_upd[0:0] + attribute \src "libresoc.v:130619.3-130627.6" + wire $0\wri_l_r_wri$next[0:0]$6023 + attribute \src "libresoc.v:130490.3-130491.39" + wire $0\wri_l_r_wri[0:0] + attribute \src "libresoc.v:130610.3-130618.6" + wire $1\adr_l_r_adr$next[0:0]$6021 + attribute \src "libresoc.v:129795.7-129795.25" + wire $1\adr_l_r_adr[0:0] + attribute \src "libresoc.v:129809.7-129809.20" + wire $1\alu_ok[0:0] + attribute \src "libresoc.v:130775.3-130784.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "libresoc.v:130785.3-130794.6" + wire width 64 $1\dest2_o[63:0] + attribute \src "libresoc.v:130765.3-130774.6" + wire width 64 $1\ea_r$next[63:0]$6109 + attribute \src "libresoc.v:129855.14-129855.41" + wire width 64 $1\ea_r[63:0] + attribute \src "libresoc.v:130840.3-130859.6" + wire width 64 $1\ldd_o[63:0] + attribute \src "libresoc.v:130804.3-130827.6" + wire width 64 $1\lddata_r[63:0] + attribute \src "libresoc.v:130707.3-130716.6" + wire width 64 $1\ldo_r$next[63:0]$6094 + attribute \src "libresoc.v:129885.14-129885.42" + wire width 64 $1\ldo_r[63:0] + attribute \src "libresoc.v:129890.14-129890.62" + wire width 96 $1\ldst_port0_addr_i[95:0] + attribute \src "libresoc.v:130795.3-130803.6" + wire $1\ldst_port0_addr_i_ok$next[0:0]$6114 + attribute \src "libresoc.v:129895.7-129895.34" + wire $1\ldst_port0_addr_i_ok[0:0] + attribute \src "libresoc.v:130884.3-130895.6" + wire width 64 $1\ldst_port0_st_data_i[63:0] + attribute \src "libresoc.v:130655.3-130663.6" + wire $1\lsd_l_r_lsd$next[0:0]$6036 + attribute \src "libresoc.v:129944.7-129944.25" + wire $1\lsd_l_r_lsd[0:0] + attribute \src "libresoc.v:130583.3-130591.6" + wire $1\opc_l_r_opc$next[0:0]$6012 + attribute \src "libresoc.v:129958.7-129958.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "libresoc.v:130574.3-130582.6" + wire $1\opc_l_s_opc$next[0:0]$6009 + attribute \src "libresoc.v:129962.7-129962.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "libresoc.v:130664.3-130706.6" + wire $1\oper_r__byte_reverse$next[0:0]$6054 + attribute \src "libresoc.v:130090.7-130090.34" + wire $1\oper_r__byte_reverse[0:0] + attribute \src "libresoc.v:130664.3-130706.6" + wire width 4 $1\oper_r__data_len$next[3:0]$6055 + attribute \src "libresoc.v:130094.13-130094.36" + wire width 4 $1\oper_r__data_len[3:0] + attribute \src "libresoc.v:130664.3-130706.6" + wire width 12 $1\oper_r__fn_unit$next[11:0]$6056 + attribute \src "libresoc.v:130111.14-130111.39" + wire width 12 $1\oper_r__fn_unit[11:0] + attribute \src "libresoc.v:130664.3-130706.6" + wire width 64 $1\oper_r__imm_data__data$next[63:0]$6057 + attribute \src "libresoc.v:130115.14-130115.59" + wire width 64 $1\oper_r__imm_data__data[63:0] + attribute \src "libresoc.v:130664.3-130706.6" + wire $1\oper_r__imm_data__ok$next[0:0]$6058 + attribute \src "libresoc.v:130119.7-130119.34" + wire $1\oper_r__imm_data__ok[0:0] + attribute \src "libresoc.v:130664.3-130706.6" + wire width 32 $1\oper_r__insn$next[31:0]$6059 + attribute \src "libresoc.v:130123.14-130123.34" + wire width 32 $1\oper_r__insn[31:0] + attribute \src "libresoc.v:130664.3-130706.6" + wire width 7 $1\oper_r__insn_type$next[6:0]$6060 + attribute \src "libresoc.v:130201.13-130201.38" + wire width 7 $1\oper_r__insn_type[6:0] + attribute \src "libresoc.v:130664.3-130706.6" + wire $1\oper_r__is_32bit$next[0:0]$6061 + attribute \src "libresoc.v:130205.7-130205.30" + wire $1\oper_r__is_32bit[0:0] + attribute \src "libresoc.v:130664.3-130706.6" + wire $1\oper_r__is_signed$next[0:0]$6062 + attribute \src "libresoc.v:130209.7-130209.31" + wire $1\oper_r__is_signed[0:0] + attribute \src "libresoc.v:130664.3-130706.6" + wire width 2 $1\oper_r__ldst_mode$next[1:0]$6063 + attribute \src "libresoc.v:130218.13-130218.37" + wire width 2 $1\oper_r__ldst_mode[1:0] + attribute \src "libresoc.v:130664.3-130706.6" + wire $1\oper_r__oe__oe$next[0:0]$6064 + attribute \src "libresoc.v:130222.7-130222.28" + wire $1\oper_r__oe__oe[0:0] + attribute \src "libresoc.v:130664.3-130706.6" + wire $1\oper_r__oe__ok$next[0:0]$6065 + attribute \src "libresoc.v:130226.7-130226.28" + wire $1\oper_r__oe__ok[0:0] + attribute \src "libresoc.v:130664.3-130706.6" + wire $1\oper_r__rc__ok$next[0:0]$6066 + attribute \src "libresoc.v:130230.7-130230.28" + wire $1\oper_r__rc__ok[0:0] + attribute \src "libresoc.v:130664.3-130706.6" + wire $1\oper_r__rc__rc$next[0:0]$6067 + attribute \src "libresoc.v:130234.7-130234.28" + wire $1\oper_r__rc__rc[0:0] + attribute \src "libresoc.v:130664.3-130706.6" + wire $1\oper_r__sign_extend$next[0:0]$6068 + attribute \src "libresoc.v:130238.7-130238.33" + wire $1\oper_r__sign_extend[0:0] + attribute \src "libresoc.v:130664.3-130706.6" + wire $1\oper_r__zero_a$next[0:0]$6069 + attribute \src "libresoc.v:130242.7-130242.28" + wire $1\oper_r__zero_a[0:0] + attribute \src "libresoc.v:130246.7-130246.21" + wire $1\p_st_go[0:0] + attribute \src "libresoc.v:130828.3-130839.6" + wire width 64 $1\revnorev[63:0] + attribute \src "libresoc.v:130601.3-130609.6" + wire width 3 $1\src_l_r_src$next[2:0]$6018 + attribute \src "libresoc.v:130288.13-130288.31" + wire width 3 $1\src_l_r_src[2:0] + attribute \src "libresoc.v:130592.3-130600.6" + wire width 3 $1\src_l_s_src$next[2:0]$6015 + attribute \src "libresoc.v:130292.13-130292.31" + wire width 3 $1\src_l_s_src[2:0] + attribute \src "libresoc.v:130717.3-130732.6" + wire width 64 $1\src_r0$next[63:0]$6097 + attribute \src "libresoc.v:130296.14-130296.43" + wire width 64 $1\src_r0[63:0] + attribute \src "libresoc.v:130733.3-130748.6" + wire width 64 $1\src_r1$next[63:0]$6101 + attribute \src "libresoc.v:130300.14-130300.43" + wire width 64 $1\src_r1[63:0] + attribute \src "libresoc.v:130749.3-130764.6" + wire width 64 $1\src_r2$next[63:0]$6105 + attribute \src "libresoc.v:130304.14-130304.43" + wire width 64 $1\src_r2[63:0] + attribute \src "libresoc.v:130860.3-130883.6" + wire width 64 $1\stdata_r[63:0] + attribute \src "libresoc.v:130646.3-130654.6" + wire $1\sto_l_r_sto$next[0:0]$6033 + attribute \src "libresoc.v:130314.7-130314.25" + wire $1\sto_l_r_sto[0:0] + attribute \src "libresoc.v:130637.3-130645.6" + wire $1\upd_l_r_upd$next[0:0]$6030 + attribute \src "libresoc.v:130324.7-130324.25" + wire $1\upd_l_r_upd[0:0] + attribute \src "libresoc.v:130628.3-130636.6" + wire $1\upd_l_s_upd$next[0:0]$6027 + attribute \src "libresoc.v:130328.7-130328.25" + wire $1\upd_l_s_upd[0:0] + attribute \src "libresoc.v:130619.3-130627.6" + wire $1\wri_l_r_wri$next[0:0]$6024 + attribute \src "libresoc.v:130338.7-130338.25" + wire $1\wri_l_r_wri[0:0] + attribute \src "libresoc.v:130840.3-130859.6" + wire width 64 $2\ldd_o[63:0] + attribute \src "libresoc.v:130804.3-130827.6" + wire width 64 $2\lddata_r[63:0] + attribute \src "libresoc.v:130664.3-130706.6" + wire $2\oper_r__byte_reverse$next[0:0]$6070 + attribute \src "libresoc.v:130664.3-130706.6" + wire width 4 $2\oper_r__data_len$next[3:0]$6071 + attribute \src "libresoc.v:130664.3-130706.6" + wire width 12 $2\oper_r__fn_unit$next[11:0]$6072 + attribute \src "libresoc.v:130664.3-130706.6" + wire width 64 $2\oper_r__imm_data__data$next[63:0]$6073 + attribute \src "libresoc.v:130664.3-130706.6" + wire $2\oper_r__imm_data__ok$next[0:0]$6074 + attribute \src "libresoc.v:130664.3-130706.6" + wire width 32 $2\oper_r__insn$next[31:0]$6075 + attribute \src "libresoc.v:130664.3-130706.6" + wire width 7 $2\oper_r__insn_type$next[6:0]$6076 + attribute \src "libresoc.v:130664.3-130706.6" + wire $2\oper_r__is_32bit$next[0:0]$6077 + attribute \src "libresoc.v:130664.3-130706.6" + wire $2\oper_r__is_signed$next[0:0]$6078 + attribute \src "libresoc.v:130664.3-130706.6" + wire width 2 $2\oper_r__ldst_mode$next[1:0]$6079 + attribute \src "libresoc.v:130664.3-130706.6" + wire $2\oper_r__oe__oe$next[0:0]$6080 + attribute \src "libresoc.v:130664.3-130706.6" + wire $2\oper_r__oe__ok$next[0:0]$6081 + attribute \src "libresoc.v:130664.3-130706.6" + wire $2\oper_r__rc__ok$next[0:0]$6082 + attribute \src "libresoc.v:130664.3-130706.6" + wire $2\oper_r__rc__rc$next[0:0]$6083 + attribute \src "libresoc.v:130664.3-130706.6" + wire $2\oper_r__sign_extend$next[0:0]$6084 + attribute \src "libresoc.v:130664.3-130706.6" + wire $2\oper_r__zero_a$next[0:0]$6085 + attribute \src "libresoc.v:130717.3-130732.6" + wire width 64 $2\src_r0$next[63:0]$6098 + attribute \src "libresoc.v:130733.3-130748.6" + wire width 64 $2\src_r1$next[63:0]$6102 + attribute \src "libresoc.v:130749.3-130764.6" + wire width 64 $2\src_r2$next[63:0]$6106 + attribute \src "libresoc.v:130860.3-130883.6" + wire width 64 $2\stdata_r[63:0] + attribute \src "libresoc.v:130664.3-130706.6" + wire width 64 $3\oper_r__imm_data__data$next[63:0]$6086 + attribute \src "libresoc.v:130664.3-130706.6" + wire $3\oper_r__imm_data__ok$next[0:0]$6087 + attribute \src "libresoc.v:130664.3-130706.6" + wire $3\oper_r__oe__oe$next[0:0]$6088 + attribute \src "libresoc.v:130664.3-130706.6" + wire $3\oper_r__oe__ok$next[0:0]$6089 + attribute \src "libresoc.v:130664.3-130706.6" + wire $3\oper_r__rc__ok$next[0:0]$6090 + attribute \src "libresoc.v:130664.3-130706.6" + wire $3\oper_r__rc__rc$next[0:0]$6091 + attribute \src "libresoc.v:130420.18-130420.124" + wire width 65 $add$libresoc.v:130420$5958_Y + attribute \src "libresoc.v:130343.19-130343.118" + wire $and$libresoc.v:130343$5878_Y + attribute \src "libresoc.v:130344.19-130344.125" + wire $and$libresoc.v:130344$5879_Y + attribute \src "libresoc.v:130345.19-130345.120" + wire $and$libresoc.v:130345$5880_Y + attribute \src "libresoc.v:130346.19-130346.125" + wire $and$libresoc.v:130346$5881_Y + attribute \src "libresoc.v:130347.19-130347.118" + wire $and$libresoc.v:130347$5882_Y + attribute \src "libresoc.v:130349.19-130349.119" + wire $and$libresoc.v:130349$5884_Y + attribute \src "libresoc.v:130350.19-130350.123" + wire $and$libresoc.v:130350$5885_Y + attribute \src "libresoc.v:130351.19-130351.123" + wire $and$libresoc.v:130351$5886_Y + attribute \src "libresoc.v:130352.19-130352.120" + wire $and$libresoc.v:130352$5887_Y + attribute \src "libresoc.v:130353.19-130353.123" + wire $and$libresoc.v:130353$5888_Y + attribute \src "libresoc.v:130354.19-130354.119" + wire $and$libresoc.v:130354$5889_Y + attribute \src "libresoc.v:130355.19-130355.123" + wire $and$libresoc.v:130355$5890_Y + attribute \src "libresoc.v:130356.19-130356.125" + wire $and$libresoc.v:130356$5891_Y + attribute \src "libresoc.v:130358.19-130358.116" + wire $and$libresoc.v:130358$5893_Y + attribute \src "libresoc.v:130360.19-130360.120" + wire $and$libresoc.v:130360$5895_Y + attribute \src "libresoc.v:130361.19-130361.123" + wire $and$libresoc.v:130361$5896_Y + attribute \src "libresoc.v:130365.19-130365.125" + wire $and$libresoc.v:130365$5900_Y + attribute \src "libresoc.v:130366.19-130366.123" + wire $and$libresoc.v:130366$5901_Y + attribute \src "libresoc.v:130371.19-130371.116" + wire $and$libresoc.v:130371$5906_Y + attribute \src "libresoc.v:130373.19-130373.116" + wire $and$libresoc.v:130373$5908_Y + attribute \src "libresoc.v:130376.19-130376.118" + wire $and$libresoc.v:130376$5911_Y + attribute \src "libresoc.v:130378.19-130378.125" + wire $and$libresoc.v:130378$5913_Y + attribute \src "libresoc.v:130381.19-130381.160" + wire width 3 $and$libresoc.v:130381$5916_Y + attribute \src "libresoc.v:130382.19-130382.122" + wire $and$libresoc.v:130382$5917_Y + attribute \src "libresoc.v:130383.19-130383.122" + wire $and$libresoc.v:130383$5918_Y + attribute \src "libresoc.v:130385.19-130385.122" + wire $and$libresoc.v:130385$5921_Y + attribute \src "libresoc.v:130397.18-130397.123" + wire $and$libresoc.v:130397$5935_Y + attribute \src "libresoc.v:130398.18-130398.123" + wire $and$libresoc.v:130398$5936_Y + attribute \src "libresoc.v:130400.18-130400.114" + wire $and$libresoc.v:130400$5938_Y + attribute \src "libresoc.v:130402.18-130402.113" + wire $and$libresoc.v:130402$5940_Y + attribute \src "libresoc.v:130405.18-130405.113" + wire $and$libresoc.v:130405$5943_Y + attribute \src "libresoc.v:130409.18-130409.113" + wire $and$libresoc.v:130409$5947_Y + attribute \src "libresoc.v:130412.18-130412.119" + wire $and$libresoc.v:130412$5950_Y + attribute \src "libresoc.v:130421.18-130421.150" + wire width 3 $and$libresoc.v:130421$5959_Y + attribute \src "libresoc.v:130423.18-130423.113" + wire width 3 $and$libresoc.v:130423$5961_Y + attribute \src "libresoc.v:130425.18-130425.113" + wire width 3 $and$libresoc.v:130425$5963_Y + attribute \src "libresoc.v:130426.18-130426.127" + wire $and$libresoc.v:130426$5964_Y + attribute \src "libresoc.v:130427.18-130427.117" + wire $and$libresoc.v:130427$5965_Y + attribute \src "libresoc.v:130432.18-130432.117" + wire $and$libresoc.v:130432$5970_Y + attribute \src "libresoc.v:130357.19-130357.127" + wire $eq$libresoc.v:130357$5892_Y + attribute \src "libresoc.v:130377.19-130377.127" + wire $eq$libresoc.v:130377$5912_Y + attribute \src "libresoc.v:130379.19-130379.127" + wire $eq$libresoc.v:130379$5914_Y + attribute \src "libresoc.v:130390.19-130390.126" + wire $eq$libresoc.v:130390$5927_Y + attribute \src "libresoc.v:130395.18-130395.127" + wire $eq$libresoc.v:130395$5933_Y + attribute \src "libresoc.v:130396.18-130396.127" + wire $eq$libresoc.v:130396$5934_Y + attribute \src "libresoc.v:130404.18-130404.126" + wire $eq$libresoc.v:130404$5942_Y + attribute \src "libresoc.v:130408.18-130408.126" + wire $eq$libresoc.v:130408$5946_Y + attribute \src "libresoc.v:130384.19-130384.110" + wire width 96 $extend$libresoc.v:130384$5919_Y + attribute \src "libresoc.v:130386.19-130386.116" + wire width 64 $extend$libresoc.v:130386$5922_Y + attribute \src "libresoc.v:130391.19-130391.102" + wire width 64 $extend$libresoc.v:130391$5928_Y + attribute \src "libresoc.v:130369.19-130369.109" + wire $not$libresoc.v:130369$5904_Y + attribute \src "libresoc.v:130374.19-130374.121" + wire $not$libresoc.v:130374$5909_Y + attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire input 3 \cu_ad__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire output 4 \cu_ad__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 23 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 22 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 26 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 25 \cu_rd__rel_o + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 5 \fast_o_ok - attribute \src "libresoc.v:42281.7-42281.15" + wire width 64 output 33 \ea + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \ea_r + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \ea_r$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \exc_$signal$179 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \exc_$signal$180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \exc_$signal$181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \exc_$signal$182 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \exc_$signal$183 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \exc_$signal$184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \exc_$signal$185 + attribute \src "libresoc.v:129599.7-129599.15" wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:110" + wire \ld_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:273" + wire \ld_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:281" + wire width 64 \ldd_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:385" + wire width 64 \ldd_r + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:11" + wire width 64 \lddata_r + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \ldo_r + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \ldo_r$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 96 output 38 \ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 96 \ldst_port0_addr_i$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 39 \ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \ldst_port0_addr_i_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire input 48 \ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire input 34 \ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 output 37 \ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 40 \ldst_port0_exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 41 \ldst_port0_exc_$signal$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 42 \ldst_port0_exc_$signal$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 43 \ldst_port0_exc_$signal$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 44 \ldst_port0_exc_$signal$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 45 \ldst_port0_exc_$signal$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 46 \ldst_port0_exc_$signal$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 47 \ldst_port0_exc_$signal$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire output 35 \ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire output 36 \ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 49 \ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 50 \ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 51 \ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 52 \ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:114" + wire \load_mem_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \lod_l_qn_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \lod_l_r_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \lod_l_s_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \lsd_l_q_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \lsd_l_r_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \lsd_l_r_lsd$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \lsd_l_s_lsd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 32 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:266" + wire \op_is_ld + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:267" + wire \op_is_st + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \opc_l_q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \oper_i_ldst_ldst0__byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \oper_i_ldst_ldst0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 7 \oper_i_ldst_ldst0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 8 \oper_i_ldst_ldst0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \oper_i_ldst_ldst0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 21 \oper_i_ldst_ldst0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -63321,234 +208618,118 @@ module \dec_o2 attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 8 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:366" - wire input 1 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 output 2 \reg_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 3 \reg_o_ok - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 input 6 \upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:377" - cell $eq $eq$libresoc.v:42385$976 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \upd - connect \B 2'01 - connect \Y $eq$libresoc.v:42385$976_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $extend$libresoc.v:42386$977 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 6 - connect \A \RA - connect \Y $extend$libresoc.v:42386$977_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $pos$libresoc.v:42386$978 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A $extend$libresoc.v:42386$977_Y - connect \Y $pos$libresoc.v:42386$978_Y - end - attribute \src "libresoc.v:42281.7-42281.20" - process $proc$libresoc.v:42281$982 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:42387.3-42400.6" - process $proc$libresoc.v:42387$979 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\reg_o[4:0] $1\reg_o[4:0] - assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0] - attribute \src "libresoc.v:42388.5-42388.29" - switch \initial - attribute \src "libresoc.v:42388.9-42388.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:377" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $1\reg_o[4:0] \$3 [4:0] - assign $1\reg_o_ok[0:0] 1'1 - case - assign $1\reg_o[4:0] 5'00000 - assign $1\reg_o_ok[0:0] 1'0 - end - sync always - update \reg_o $0\reg_o[4:0] - update \reg_o_ok $0\reg_o_ok[0:0] - end - attribute \src "libresoc.v:42401.3-42420.6" - process $proc$libresoc.v:42401$980 - assign { } { } - assign { } { } - assign $0\fast_o[2:0] $1\fast_o[2:0] - attribute \src "libresoc.v:42402.5-42402.29" - switch \initial - attribute \src "libresoc.v:42402.9-42402.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" - switch \internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0000111 , 7'0000110 , 7'0001000 - assign { } { } - assign $1\fast_o[2:0] $2\fast_o[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:388" - switch \lk - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fast_o[2:0] 3'001 - case - assign $2\fast_o[2:0] 3'000 - end - attribute \src "libresoc.v:0.0-0.0" - case 7'1000110 - assign { } { } - assign $1\fast_o[2:0] 3'100 - case - assign $1\fast_o[2:0] 3'000 - end - sync always - update \fast_o $0\fast_o[2:0] - end - attribute \src "libresoc.v:42421.3-42440.6" - process $proc$libresoc.v:42421$981 - assign { } { } - assign { } { } - assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] - attribute \src "libresoc.v:42422.5-42422.29" - switch \initial - attribute \src "libresoc.v:42422.9-42422.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" - switch \internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0000111 , 7'0000110 , 7'0001000 - assign { } { } - assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:388" - switch \lk - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fast_o_ok[0:0] 1'1 - case - assign $2\fast_o_ok[0:0] 1'0 - end - attribute \src "libresoc.v:0.0-0.0" - case 7'1000110 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - case - assign $1\fast_o_ok[0:0] 1'0 - end - sync always - update \fast_o_ok $0\fast_o_ok[0:0] - end - connect \$1 $eq$libresoc.v:42385$976_Y - connect \$3 $pos$libresoc.v:42386$978_Y -end -attribute \src "libresoc.v:42445.1-42579.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_oe" -attribute \generator "nMigen" -module \dec_oe - attribute \src "libresoc.v:42446.7-42446.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:42537.3-42557.6" - wire $0\oe[0:0] - attribute \src "libresoc.v:42558.3-42578.6" - wire $0\oe_ok[0:0] - attribute \src "libresoc.v:42537.3-42557.6" - wire $1\oe[0:0] - attribute \src "libresoc.v:42558.3-42578.6" - wire $1\oe_ok[0:0] - attribute \src "libresoc.v:42537.3-42557.6" - wire $2\oe[0:0] - attribute \src "libresoc.v:42558.3-42578.6" - wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire input 4 \OE - attribute \src "libresoc.v:42446.7-42446.15" - wire \initial + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 6 \oper_i_ldst_ldst0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \oper_i_ldst_ldst0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \oper_i_ldst_ldst0__is_signed + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 20 \oper_i_ldst_ldst0__ldst_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \oper_i_ldst_ldst0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \oper_i_ldst_ldst0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \oper_i_ldst_ldst0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \oper_i_ldst_ldst0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \oper_i_ldst_ldst0__sign_extend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \oper_i_ldst_ldst0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__byte_reverse$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \oper_r__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \oper_r__data_len$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \oper_r__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \oper_r__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \oper_r__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \oper_r__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__imm_data__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \oper_r__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \oper_r__insn$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -63623,8446 +208804,11911 @@ module \dec_oe attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 1 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 3 \oe_ok - attribute \enum_base_type "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \oper_r__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \oper_r__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__is_signed$next + attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" - wire width 2 input 5 \sel_in - attribute \src "libresoc.v:42446.7-42446.20" - process $proc$libresoc.v:42446$985 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \oper_r__ldst_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \oper_r__ldst_mode$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__sign_extend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__sign_extend$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__zero_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:303" + wire \p_st_go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:303" + wire \p_st_go$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:276" + wire \rd_done + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:275" + wire \rda_any + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:290" + wire \reset_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:291" + wire \reset_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:287" + wire \reset_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:292" + wire width 3 \reset_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:293" + wire \reset_s + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:289" + wire \reset_u + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:288" + wire \reset_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:499" + wire width 64 \revnorev + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \rst_l_q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rst_l_r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 27 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:405" + wire width 64 \src1_or_z + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 28 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410" + wire width 64 \src2_or_imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 29 \src3_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 \src_l_q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \src_l_r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \src_l_r_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \src_l_s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \src_l_s_src$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" + wire width 64 \src_r0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" + wire width 64 \src_r0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" + wire width 64 \src_r1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" + wire width 64 \src_r1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" + wire width 64 \src_r2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" + wire width 64 \src_r2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:111" + wire \st_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:11" + wire width 64 \stdata_r + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \sto_l_q_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \sto_l_r_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \sto_l_r_sto$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \sto_l_s_sto + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:115" + wire \stwd_mem_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \upd_l_q_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \upd_l_r_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \upd_l_r_upd$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \upd_l_s_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \upd_l_s_upd$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:274" + wire \wr_any + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:277" + wire \wr_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \wri_l_q_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \wri_l_r_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \wri_l_r_wri$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \wri_l_s_wri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:414" + cell $add $add$libresoc.v:130420$5958 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \src1_or_z + connect \B \src2_or_imm + connect \Y $add$libresoc.v:130420$5958_Y end - attribute \src "libresoc.v:42537.3-42557.6" - process $proc$libresoc.v:42537$983 - assign { } { } - assign { } { } - assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:42538.5-42538.29" - switch \initial - attribute \src "libresoc.v:42538.9-42538.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" - switch \internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe[0:0] \OE - case - assign $2\oe[0:0] 1'0 - end - end - sync always - update \oe $0\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" + cell $and $and$libresoc.v:130343$5878 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_valid + connect \B \$98 + connect \Y $and$libresoc.v:130343$5878_Y end - attribute \src "libresoc.v:42558.3-42578.6" - process $proc$libresoc.v:42558$984 - assign { } { } - assign { } { } - assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:42559.5-42559.29" - switch \initial - attribute \src "libresoc.v:42559.9-42559.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" - switch \internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe_ok[0:0] 1'1 - case - assign $2\oe_ok[0:0] 1'0 - end - end - sync always - update \oe_ok $0\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" + cell $and $and$libresoc.v:130344$5879 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_valid + connect \B \adr_l_q_adr + connect \Y $and$libresoc.v:130344$5879_Y end -end -attribute \src "libresoc.v:42583.1-42637.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_rc" -attribute \generator "nMigen" -module \dec_rc - attribute \src "libresoc.v:42584.7-42584.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:42599.3-42617.6" - wire $0\rc[0:0] - attribute \src "libresoc.v:42618.3-42636.6" - wire $0\rc_ok[0:0] - attribute \src "libresoc.v:42599.3-42617.6" - wire $1\rc[0:0] - attribute \src "libresoc.v:42618.3-42636.6" - wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire input 3 \Rc - attribute \src "libresoc.v:42584.7-42584.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" - wire width 2 input 4 \sel_in - attribute \src "libresoc.v:42584.7-42584.20" - process $proc$libresoc.v:42584$988 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" + cell $and $and$libresoc.v:130345$5880 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$102 + connect \B \cu_busy_o + connect \Y $and$libresoc.v:130345$5880_Y end - attribute \src "libresoc.v:42599.3-42617.6" - process $proc$libresoc.v:42599$986 - assign { } { } - assign { } { } - assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:42600.5-42600.29" - switch \initial - attribute \src "libresoc.v:42600.9-42600.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc[0:0] \Rc - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc[0:0] 1'0 - case - assign $1\rc[0:0] 1'0 - end - sync always - update \rc $0\rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" + cell $and $and$libresoc.v:130346$5881 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sto_l_q_sto + connect \B \cu_busy_o + connect \Y $and$libresoc.v:130346$5881_Y end - attribute \src "libresoc.v:42618.3-42636.6" - process $proc$libresoc.v:42618$987 - assign { } { } - assign { } { } - assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:42619.5-42619.29" - switch \initial - attribute \src "libresoc.v:42619.9-42619.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - case - assign $1\rc_ok[0:0] 1'0 - end - sync always - update \rc_ok $0\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" + cell $and $and$libresoc.v:130347$5882 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$106 + connect \B \rd_done + connect \Y $and$libresoc.v:130347$5882_Y end -end -attribute \src "libresoc.v:42641.1-43020.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.imem" -attribute \generator "nMigen" -module \imem - attribute \src "libresoc.v:42972.3-42981.6" - wire $0\a_busy_o[0:0] - attribute \src "libresoc.v:42952.3-42971.6" - wire width 45 $0\f_badaddr_o$next[44:0]$1057 - attribute \src "libresoc.v:42783.3-42784.39" - wire width 45 $0\f_badaddr_o[44:0] - attribute \src "libresoc.v:42982.3-42999.6" - wire $0\f_busy_o[0:0] - attribute \src "libresoc.v:42929.3-42951.6" - wire $0\f_fetch_err_o$next[0:0]$1052 - attribute \src "libresoc.v:42785.3-42786.43" - wire $0\f_fetch_err_o[0:0] - attribute \src "libresoc.v:43000.3-43017.6" - wire width 64 $0\f_instr_o[63:0] - attribute \src "libresoc.v:42906.3-42928.6" - wire width 45 $0\ibus__adr$next[44:0]$1047 - attribute \src "libresoc.v:42787.3-42788.35" - wire width 45 $0\ibus__adr[44:0] - attribute \src "libresoc.v:42797.3-42824.6" - wire $0\ibus__cyc$next[0:0]$1023 - attribute \src "libresoc.v:42795.3-42796.35" - wire $0\ibus__cyc[0:0] - attribute \src "libresoc.v:42853.3-42880.6" - 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"/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" - wire width 45 \f_badaddr_o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" - wire output 5 \f_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34" - wire \f_fetch_err_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34" - wire \f_fetch_err_o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33" - wire width 64 output 6 \f_instr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:27" - wire \f_stall_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" - wire input 4 \f_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 9 \ibus__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 45 output 14 \ibus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 45 \ibus__adr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire output 8 \ibus__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire \ibus__cyc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 64 input 13 \ibus__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 10 \ibus__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 8 output 12 \ibus__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 8 \ibus__sel$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire output 11 \ibus__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire \ibus__stb$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:69" - wire width 64 \ibus_rdata - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:69" - wire width 64 \ibus_rdata$next - attribute \src "libresoc.v:42642.7-42642.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" - wire input 7 \wb_icache_en - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:42759$991 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" + cell $and $and$libresoc.v:130349$5884 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \a_valid_i - connect \B \$11 - connect \Y $and$libresoc.v:42759$991_Y + connect \A \$108 + connect \B \op_is_st + connect \Y $and$libresoc.v:130349$5884_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:42765$997 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447" + cell $and $and$libresoc.v:130350$5885 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \a_valid_i - connect \B \$21 - connect \Y $and$libresoc.v:42765$997_Y + connect \A \$110 + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:130350$5885_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:42770$1002 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" + cell $and $and$libresoc.v:130351$5886 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \a_valid_i - connect \B \$31 - connect \Y $and$libresoc.v:42770$1002_Y + connect \A \rd_done + connect \B \wri_l_q_wri + connect \Y $and$libresoc.v:130351$5886_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:42773$1005 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" + cell $and $and$libresoc.v:130352$5887 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \a_valid_i - connect \B \$1 - connect \Y $and$libresoc.v:42773$1005_Y + connect \A \$114 + connect \B \cu_busy_o + connect \Y $and$libresoc.v:130352$5887_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:42776$1008 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" + cell $and $and$libresoc.v:130353$5888 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \a_valid_i + connect \A \$116 + connect \B \lod_l_qn_lod + connect \Y $and$libresoc.v:130353$5888_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" + cell $and $and$libresoc.v:130354$5889 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$118 + connect \B \op_is_ld + connect \Y $and$libresoc.v:130354$5889_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" + cell $and $and$libresoc.v:130355$5890 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$120 + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:130355$5890_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" + cell $and $and$libresoc.v:130356$5891 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 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+ connect \A \$130 + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:130361$5896_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" + cell $and $and$libresoc.v:130365$5900 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rst_l_q_rst + connect \B \cu_busy_o + connect \Y $and$libresoc.v:130365$5900_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" + cell $and $and$libresoc.v:130366$5901 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$140 + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:130366$5901_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" + cell $and $and$libresoc.v:130371$5906 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 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+ parameter \Y_WIDTH 1 + connect \A \$162 + connect \B \cu_wr__go_i [1] + connect \Y $and$libresoc.v:130378$5913_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:482" + cell $and $and$libresoc.v:130381$5916 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { \cu_busy_o \cu_busy_o \cu_busy_o } + connect \B { 1'0 \$167 \op_is_ld } + connect \Y $and$libresoc.v:130381$5916_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489" + cell $and $and$libresoc.v:130382$5917 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \op_is_ld + connect \B \cu_busy_o + connect \Y $and$libresoc.v:130382$5917_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:490" + cell $and $and$libresoc.v:130383$5918 + parameter \A_SIGNED 0 + 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$and$libresoc.v:130405$5943 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$39 connect \B \$41 - connect \Y $and$libresoc.v:42776$1008_Y + connect \Y $and$libresoc.v:130405$5943_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - cell $and $and$libresoc.v:42777$1009 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" + cell $and $and$libresoc.v:130409$5947 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ibus__cyc - connect \B \ibus__err - connect \Y $and$libresoc.v:42777$1009_Y + connect \A \$47 + connect \B \$49 + connect \Y $and$libresoc.v:130409$5947_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - cell $and $and$libresoc.v:42779$1011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:367" + cell $and $and$libresoc.v:130412$5950 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ibus__cyc - connect \B \ibus__err - connect \Y $and$libresoc.v:42779$1011_Y + connect \A \addr_ok + connect \B \op_is_st + connect \Y $and$libresoc.v:130412$5950_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:42758$990 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" + cell $and $and$libresoc.v:130421$5959 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \src_l_q_src + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$libresoc.v:130421$5959_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" + cell $and $and$libresoc.v:130423$5961 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A \$76 + connect \B \$78 + connect \Y $and$libresoc.v:130423$5961_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" + cell $and $and$libresoc.v:130425$5963 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$80 + connect \B \$82 + connect \Y $and$libresoc.v:130425$5963_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" + cell $and $and$libresoc.v:130426$5964 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \a_stall_i - connect \Y $not$libresoc.v:42758$990_Y + connect \A \src_l_q_src [2] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:130426$5964_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:42761$993 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" + cell $and $and$libresoc.v:130427$5965 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \f_valid_i - connect \Y $not$libresoc.v:42761$993_Y + connect \A \$86 + connect \B \op_is_st + connect \Y $and$libresoc.v:130427$5965_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:42762$994 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" + cell $and $and$libresoc.v:130432$5970 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \a_stall_i - connect \Y $not$libresoc.v:42762$994_Y + connect \A \cu_busy_o + connect \B \$92 + connect \Y $and$libresoc.v:130432$5970_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:42764$996 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" + cell $eq $eq$libresoc.v:130357$5892 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \oper_r__ldst_mode + connect \B 2'01 + connect \Y $eq$libresoc.v:130357$5892_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" + cell $eq $eq$libresoc.v:130377$5912 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \oper_r__ldst_mode + connect \B 2'01 + connect \Y $eq$libresoc.v:130377$5912_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" + cell $eq $eq$libresoc.v:130379$5914 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \oper_r__ldst_mode + connect \B 2'01 + connect \Y $eq$libresoc.v:130379$5914_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" + cell $eq $eq$libresoc.v:130390$5927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \oper_r__data_len + connect \B 2'10 + connect \Y $eq$libresoc.v:130390$5927_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:308" + cell $eq $eq$libresoc.v:130395$5933 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \oper_r__insn_type + connect \B 7'0100110 + connect \Y $eq$libresoc.v:130395$5933_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" + cell $eq $eq$libresoc.v:130396$5934 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \oper_r__insn_type + connect \B 7'0100101 + connect \Y $eq$libresoc.v:130396$5934_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" + cell $eq $eq$libresoc.v:130404$5942 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \oper_r__ldst_mode + connect \B 2'01 + connect \Y $eq$libresoc.v:130404$5942_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" + cell $eq $eq$libresoc.v:130408$5946 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \oper_r__ldst_mode + connect \B 2'01 + connect \Y $eq$libresoc.v:130408$5946_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" + cell $pos $extend$libresoc.v:130384$5919 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 96 + connect \A \addr_r + connect \Y $extend$libresoc.v:130384$5919_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + cell $pos $extend$libresoc.v:130386$5922 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 64 + connect \A \ldst_port0_ld_data_o [7:0] + connect \Y $extend$libresoc.v:130386$5922_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + cell $pos $extend$libresoc.v:130391$5928 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 64 + connect \A \src_r2 [7:0] + connect \Y $extend$libresoc.v:130391$5928_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" + cell $not $not$libresoc.v:130369$5904 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \a_stall_i - connect \Y $not$libresoc.v:42764$996_Y + connect \A \$147 + connect \Y $not$libresoc.v:130369$5904_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:42767$999 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" + cell $not $not$libresoc.v:130374$5909 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \f_valid_i - connect \Y $not$libresoc.v:42767$999_Y + connect \A \ldst_port0_busy_o + connect \Y $not$libresoc.v:130374$5909_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:42769$1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" + cell $not $not$libresoc.v:130399$5937 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \a_stall_i - connect \Y $not$libresoc.v:42769$1001_Y + connect \A \alu_valid + connect \Y $not$libresoc.v:130399$5937_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:42772$1004 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" + cell $not $not$libresoc.v:130401$5939 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \f_valid_i - connect \Y $not$libresoc.v:42772$1004_Y + connect \A \rda_any + connect \Y $not$libresoc.v:130401$5939_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:42775$1007 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" + cell $not $not$libresoc.v:130403$5941 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \a_stall_i - connect \Y $not$libresoc.v:42775$1007_Y + connect \A \ldst_port0_busy_o + connect \Y $not$libresoc.v:130403$5941_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" - cell $not $not$libresoc.v:42778$1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" + cell $not $not$libresoc.v:130407$5945 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \f_stall_i - connect \Y $not$libresoc.v:42778$1010_Y + connect \A \ldst_port0_busy_o + connect \Y $not$libresoc.v:130407$5945_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" - cell $not $not$libresoc.v:42780$1012 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" + cell $not $not$libresoc.v:130422$5960 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A { \oper_r__imm_data__ok \oper_r__zero_a } + connect \Y $not$libresoc.v:130422$5960_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" + cell $not $not$libresoc.v:130424$5962 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rdmaskn_i + connect \Y $not$libresoc.v:130424$5962_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" + cell $not $not$libresoc.v:130431$5969 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \f_stall_i - connect \Y $not$libresoc.v:42780$1012_Y + connect \A \$93 + connect \Y $not$libresoc.v:130431$5969_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:42782$1014 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" + cell $not $not$libresoc.v:130433$5971 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \f_valid_i - connect \Y $not$libresoc.v:42782$1014_Y + connect \A \cu_rd__rel_o [2] + connect \Y $not$libresoc.v:130433$5971_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:42757$989 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" + cell $or $or$libresoc.v:130348$5883 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \$7 - connect \Y $or$libresoc.v:42757$989_Y + connect \A \cu_done_o + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:130348$5883_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:42760$992 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297" + cell $or $or$libresoc.v:130359$5894 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ibus__ack - connect \B \ibus__err - connect \Y $or$libresoc.v:42760$992_Y + connect \A \cu_wr__go_i [0] + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:130359$5894_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:42763$995 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" + cell $or $or$libresoc.v:130362$5897 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$15 - connect \B \$17 - connect \Y $or$libresoc.v:42763$995_Y + connect \A \cu_st__go_i + connect \B \p_st_go + connect \Y $or$libresoc.v:130362$5897_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:42766$998 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" + cell $or $or$libresoc.v:130363$5898 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ibus__ack - connect \B \ibus__err - connect \Y $or$libresoc.v:42766$998_Y + connect \A \$134 + connect \B \cu_wr__go_i [0] + connect \Y $or$libresoc.v:130363$5898_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:42768$1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" + cell $or $or$libresoc.v:130364$5899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$25 - connect \B \$27 - connect \Y $or$libresoc.v:42768$1000_Y + connect \A \$136 + connect \B \cu_wr__go_i [1] + connect \Y $or$libresoc.v:130364$5899_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:42771$1003 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" + cell $or $or$libresoc.v:130367$5902 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ibus__ack - connect \B \ibus__err - connect \Y $or$libresoc.v:42771$1003_Y + connect \A \cu_st__rel_o + connect \B \cu_wr__rel_o [0] + connect \Y $or$libresoc.v:130367$5902_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:42774$1006 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" + cell $or $or$libresoc.v:130368$5903 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$35 - connect \B \$37 - connect \Y $or$libresoc.v:42774$1006_Y + connect \A \$145 + connect \B \cu_wr__rel_o [1] + connect \Y $or$libresoc.v:130368$5903_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298" + cell $or $or$libresoc.v:130370$5905 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [1] + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:130370$5905_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" + cell $or $or$libresoc.v:130372$5907 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lod_l_qn_lod + connect \B \op_is_st + connect \Y $or$libresoc.v:130372$5907_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" + cell $or $or$libresoc.v:130375$5910 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$156 + connect \B \op_is_ld + connect \Y $or$libresoc.v:130375$5910_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299" + cell $or $or$libresoc.v:130380$5915 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_st__go_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:130380$5915_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:300" + cell $or $or$libresoc.v:130388$5925 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:130388$5925_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301" + cell $or $or$libresoc.v:130394$5932 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_ad__go_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:130394$5932_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" + cell $or $or$libresoc.v:130406$5944 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_reset + connect \B \$43 + connect \Y $or$libresoc.v:130406$5944_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" + cell $or $or$libresoc.v:130410$5948 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_reset + connect \B \$51 + connect \Y $or$libresoc.v:130410$5948_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:360" + cell $or $or$libresoc.v:130411$5949 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reset_w + connect \B { \$45 \$53 } + connect \Y $or$libresoc.v:130411$5949_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:368" + cell $or $or$libresoc.v:130413$5951 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \reset_s + connect \B \p_st_go + connect \Y $or$libresoc.v:130413$5951_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" + cell $or $or$libresoc.v:130414$5952 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \reset_s + connect \B \p_st_go + connect \Y $or$libresoc.v:130414$5952_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" + cell $or $or$libresoc.v:130415$5953 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$61 + connect \B \ld_ok + connect \Y $or$libresoc.v:130415$5953_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295" + cell $or $or$libresoc.v:130428$5966 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:130428$5966_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431" + cell $or $or$libresoc.v:130429$5967 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_rd__go_i [0] + connect \B \cu_rd__go_i [1] + connect \Y $or$libresoc.v:130429$5967_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" + cell $or $or$libresoc.v:130430$5968 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_rd__rel_o [0] + connect \B \cu_rd__rel_o [1] + connect \Y $or$libresoc.v:130430$5968_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" + cell $pos $pos$libresoc.v:130384$5920 + parameter \A_SIGNED 0 + parameter \A_WIDTH 96 + parameter \Y_WIDTH 96 + connect \A $extend$libresoc.v:130384$5919_Y + connect \Y $pos$libresoc.v:130384$5920_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + cell $pos $pos$libresoc.v:130386$5923 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:130386$5922_Y + connect \Y $pos$libresoc.v:130386$5923_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + cell $pos $pos$libresoc.v:130387$5924 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 48'000000000000000000000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] } + connect \Y $pos$libresoc.v:130387$5924_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + cell $pos $pos$libresoc.v:130389$5926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] \ldst_port0_ld_data_o [23:16] \ldst_port0_ld_data_o [31:24] } + connect \Y $pos$libresoc.v:130389$5926_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + cell $pos $pos$libresoc.v:130391$5929 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:130391$5928_Y + connect \Y $pos$libresoc.v:130391$5929_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + cell $pos $pos$libresoc.v:130392$5930 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 48'000000000000000000000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] } + connect \Y $pos$libresoc.v:130392$5930_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + cell $pos $pos$libresoc.v:130393$5931 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] \src_r2 [23:16] \src_r2 [31:24] } + connect \Y $pos$libresoc.v:130393$5931_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:130416$5954 + parameter \WIDTH 64 + connect \A \ldo_r + connect \B \ldd_o + connect \S \ld_ok + connect \Y $ternary$libresoc.v:130416$5954_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:130417$5955 + parameter \WIDTH 64 + connect \A \ea_r + connect \B \alu_o + connect \S \alu_l_q_alu + connect \Y $ternary$libresoc.v:130417$5955_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:406" + cell $mux $ternary$libresoc.v:130418$5956 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \S \oper_r__zero_a + connect \Y $ternary$libresoc.v:130418$5956_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411" + cell $mux $ternary$libresoc.v:130419$5957 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \oper_r__imm_data__data + connect \S \oper_r__imm_data__ok + connect \Y $ternary$libresoc.v:130419$5957_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:130504.9-130510.4" + cell \adr_l \adr_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_adr \adr_l_q_adr + connect \r_adr \adr_l_r_adr + connect \s_adr \adr_l_s_adr + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:130511.15-130517.4" + cell \alu_l$128 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:130518.9-130524.4" + cell \lod_l \lod_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \qn_lod \lod_l_qn_lod + connect \r_lod \lod_l_r_lod + connect \s_lod \lod_l_s_lod + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:130525.9-130531.4" + cell \lsd_l \lsd_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_lsd \lsd_l_q_lsd + connect \r_lsd \lsd_l_r_lsd + connect \s_lsd \lsd_l_s_lsd + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:130532.15-130538.4" + cell \opc_l$126 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:130539.15-130545.4" + cell \rst_l$129 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rst \rst_l_q_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:130546.15-130552.4" + cell \src_l$127 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:130553.9-130559.4" + cell \sto_l \sto_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_sto \sto_l_q_sto + connect \r_sto \sto_l_r_sto + connect \s_sto \sto_l_s_sto + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:130560.9-130566.4" + cell \upd_l \upd_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_upd \upd_l_q_upd + connect \r_upd \upd_l_r_upd + connect \s_upd \upd_l_s_upd + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:130567.9-130573.4" + cell \wri_l \wri_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_wri \wri_l_q_wri + connect \r_wri \wri_l_r_wri + connect \s_wri \wri_l_s_wri + end + attribute \src "libresoc.v:129599.7-129599.20" + process $proc$libresoc.v:129599$6120 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:129795.7-129795.25" + process $proc$libresoc.v:129795$6121 + assign { } { } + assign $1\adr_l_r_adr[0:0] 1'1 + sync always + sync init + update \adr_l_r_adr $1\adr_l_r_adr[0:0] + end + attribute \src "libresoc.v:129809.7-129809.20" + process $proc$libresoc.v:129809$6122 + assign { } { } + assign $1\alu_ok[0:0] 1'0 + sync always + sync init + update \alu_ok $1\alu_ok[0:0] + end + attribute \src "libresoc.v:129855.14-129855.41" + process $proc$libresoc.v:129855$6123 + assign { } { } + assign $1\ea_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ea_r $1\ea_r[63:0] + end + attribute \src "libresoc.v:129885.14-129885.42" + process $proc$libresoc.v:129885$6124 + assign { } { } + assign $1\ldo_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ldo_r $1\ldo_r[63:0] + end + attribute \src "libresoc.v:129890.14-129890.62" + process $proc$libresoc.v:129890$6125 + assign { } { } + assign $1\ldst_port0_addr_i[95:0] 96'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ldst_port0_addr_i $1\ldst_port0_addr_i[95:0] + end + attribute \src "libresoc.v:129895.7-129895.34" + process $proc$libresoc.v:129895$6126 + assign { } { } + assign $1\ldst_port0_addr_i_ok[0:0] 1'0 + sync always + sync init + update \ldst_port0_addr_i_ok $1\ldst_port0_addr_i_ok[0:0] + end + attribute \src "libresoc.v:129944.7-129944.25" + process $proc$libresoc.v:129944$6127 + assign { } { } + assign $1\lsd_l_r_lsd[0:0] 1'1 + sync always + sync init + update \lsd_l_r_lsd $1\lsd_l_r_lsd[0:0] + end + attribute \src "libresoc.v:129958.7-129958.25" + process $proc$libresoc.v:129958$6128 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:129962.7-129962.25" + process $proc$libresoc.v:129962$6129 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:130090.7-130090.34" + process $proc$libresoc.v:130090$6130 + assign { } { } + assign $1\oper_r__byte_reverse[0:0] 1'0 + sync always + sync init + update \oper_r__byte_reverse $1\oper_r__byte_reverse[0:0] + end + attribute \src "libresoc.v:130094.13-130094.36" + process $proc$libresoc.v:130094$6131 + assign { } { } + assign $1\oper_r__data_len[3:0] 4'0000 + sync always + sync init + update \oper_r__data_len $1\oper_r__data_len[3:0] + end + attribute \src "libresoc.v:130111.14-130111.39" + process $proc$libresoc.v:130111$6132 + assign { } { } + assign $1\oper_r__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \oper_r__fn_unit $1\oper_r__fn_unit[11:0] + end + attribute \src "libresoc.v:130115.14-130115.59" + process $proc$libresoc.v:130115$6133 + assign { } { } + assign $1\oper_r__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \oper_r__imm_data__data $1\oper_r__imm_data__data[63:0] + end + attribute \src "libresoc.v:130119.7-130119.34" + process $proc$libresoc.v:130119$6134 + assign { } { } + assign $1\oper_r__imm_data__ok[0:0] 1'0 + sync always + sync init + update \oper_r__imm_data__ok $1\oper_r__imm_data__ok[0:0] + end + attribute \src "libresoc.v:130123.14-130123.34" + process $proc$libresoc.v:130123$6135 + assign { } { } + assign $1\oper_r__insn[31:0] 0 + sync always + sync init + update \oper_r__insn $1\oper_r__insn[31:0] + end + attribute \src "libresoc.v:130201.13-130201.38" + process $proc$libresoc.v:130201$6136 + assign { } { } + assign $1\oper_r__insn_type[6:0] 7'0000000 + sync always + sync init + update \oper_r__insn_type $1\oper_r__insn_type[6:0] + end + attribute \src "libresoc.v:130205.7-130205.30" + process $proc$libresoc.v:130205$6137 + assign { } { } + assign $1\oper_r__is_32bit[0:0] 1'0 + sync always + sync init + update \oper_r__is_32bit $1\oper_r__is_32bit[0:0] + end + attribute \src "libresoc.v:130209.7-130209.31" + process $proc$libresoc.v:130209$6138 + assign { } { } + assign $1\oper_r__is_signed[0:0] 1'0 + sync always + sync init + update \oper_r__is_signed $1\oper_r__is_signed[0:0] + end + attribute \src "libresoc.v:130218.13-130218.37" + process $proc$libresoc.v:130218$6139 + assign { } { } + assign $1\oper_r__ldst_mode[1:0] 2'00 + sync always + sync init + update \oper_r__ldst_mode $1\oper_r__ldst_mode[1:0] + end + attribute \src "libresoc.v:130222.7-130222.28" + process $proc$libresoc.v:130222$6140 + assign { } { } + assign $1\oper_r__oe__oe[0:0] 1'0 + sync always + sync init + update \oper_r__oe__oe $1\oper_r__oe__oe[0:0] + end + attribute \src "libresoc.v:130226.7-130226.28" + process $proc$libresoc.v:130226$6141 + assign { } { } + assign $1\oper_r__oe__ok[0:0] 1'0 + sync always + sync init + update \oper_r__oe__ok $1\oper_r__oe__ok[0:0] + end + attribute \src "libresoc.v:130230.7-130230.28" + process $proc$libresoc.v:130230$6142 + assign { } { } + assign $1\oper_r__rc__ok[0:0] 1'0 + sync always + sync init + update \oper_r__rc__ok $1\oper_r__rc__ok[0:0] + end + attribute \src "libresoc.v:130234.7-130234.28" + process $proc$libresoc.v:130234$6143 + assign { } { } + assign $1\oper_r__rc__rc[0:0] 1'0 + sync always + sync init + update \oper_r__rc__rc $1\oper_r__rc__rc[0:0] + end + attribute \src "libresoc.v:130238.7-130238.33" + process $proc$libresoc.v:130238$6144 + assign { } { } + assign $1\oper_r__sign_extend[0:0] 1'0 + sync always + sync init + update \oper_r__sign_extend $1\oper_r__sign_extend[0:0] + end + attribute \src "libresoc.v:130242.7-130242.28" + process $proc$libresoc.v:130242$6145 + assign { } { } + assign $1\oper_r__zero_a[0:0] 1'0 + sync always + sync init + update \oper_r__zero_a $1\oper_r__zero_a[0:0] + end + attribute \src "libresoc.v:130246.7-130246.21" + process $proc$libresoc.v:130246$6146 + assign { } { } + assign $1\p_st_go[0:0] 1'0 + sync always + sync init + update \p_st_go $1\p_st_go[0:0] + end + attribute \src "libresoc.v:130288.13-130288.31" + process $proc$libresoc.v:130288$6147 + assign { } { } + assign $1\src_l_r_src[2:0] 3'111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[2:0] + end + attribute \src "libresoc.v:130292.13-130292.31" + process $proc$libresoc.v:130292$6148 + assign { } { } + assign $1\src_l_s_src[2:0] 3'000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[2:0] + end + attribute \src "libresoc.v:130296.14-130296.43" + process $proc$libresoc.v:130296$6149 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:130300.14-130300.43" + process $proc$libresoc.v:130300$6150 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:130304.14-130304.43" + process $proc$libresoc.v:130304$6151 + assign { } { } + assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r2 $1\src_r2[63:0] + end + attribute \src "libresoc.v:130314.7-130314.25" + process $proc$libresoc.v:130314$6152 + assign { } { } + assign $1\sto_l_r_sto[0:0] 1'1 + sync always + sync init + update \sto_l_r_sto $1\sto_l_r_sto[0:0] + end + attribute \src "libresoc.v:130324.7-130324.25" + process $proc$libresoc.v:130324$6153 + assign { } { } + assign $1\upd_l_r_upd[0:0] 1'1 + sync always + sync init + update \upd_l_r_upd $1\upd_l_r_upd[0:0] + end + attribute \src "libresoc.v:130328.7-130328.25" + process $proc$libresoc.v:130328$6154 + assign { } { } + assign $1\upd_l_s_upd[0:0] 1'0 + sync always + sync init + update \upd_l_s_upd $1\upd_l_s_upd[0:0] + end + attribute \src "libresoc.v:130338.7-130338.25" + process $proc$libresoc.v:130338$6155 + assign { } { } + assign $1\wri_l_r_wri[0:0] 1'1 + sync always + sync init + update \wri_l_r_wri $1\wri_l_r_wri[0:0] + end + attribute \src "libresoc.v:130434.3-130435.57" + process $proc$libresoc.v:130434$5972 + assign { } { } + assign $0\ldst_port0_addr_i_ok[0:0] \ldst_port0_addr_i_ok$next + sync posedge \coresync_clk + update \ldst_port0_addr_i_ok $0\ldst_port0_addr_i_ok[0:0] + end + attribute \src "libresoc.v:130436.3-130437.33" + process $proc$libresoc.v:130436$5973 + assign { } { } + assign $0\ldst_port0_addr_i[95:0] \$175 + sync posedge \coresync_clk + update \ldst_port0_addr_i $0\ldst_port0_addr_i[95:0] + end + attribute \src "libresoc.v:130438.3-130439.21" + process $proc$libresoc.v:130438$5974 + assign { } { } + assign $0\alu_ok[0:0] \$96 + sync posedge \coresync_clk + update \alu_ok $0\alu_ok[0:0] + end + attribute \src "libresoc.v:130440.3-130441.25" + process $proc$libresoc.v:130440$5975 + assign { } { } + assign $0\ea_r[63:0] \ea_r$next + sync posedge \coresync_clk + update \ea_r $0\ea_r[63:0] + end + attribute \src "libresoc.v:130442.3-130443.29" + process $proc$libresoc.v:130442$5976 + assign { } { } + assign $0\src_r2[63:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[63:0] + end + attribute \src "libresoc.v:130444.3-130445.29" + process $proc$libresoc.v:130444$5977 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:130446.3-130447.29" + process $proc$libresoc.v:130446$5978 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:130448.3-130449.27" + process $proc$libresoc.v:130448$5979 + assign { } { } + assign $0\ldo_r[63:0] \ldo_r$next + sync posedge \coresync_clk + update \ldo_r $0\ldo_r[63:0] + end + attribute \src "libresoc.v:130450.3-130451.51" + process $proc$libresoc.v:130450$5980 + assign { } { } + assign $0\oper_r__insn_type[6:0] \oper_r__insn_type$next + sync posedge \coresync_clk + update \oper_r__insn_type $0\oper_r__insn_type[6:0] + end + attribute \src "libresoc.v:130452.3-130453.47" + process $proc$libresoc.v:130452$5981 + assign { } { } + assign $0\oper_r__fn_unit[11:0] \oper_r__fn_unit$next + sync posedge \coresync_clk + update \oper_r__fn_unit $0\oper_r__fn_unit[11:0] + end + attribute \src "libresoc.v:130454.3-130455.61" + process $proc$libresoc.v:130454$5982 + assign { } { } + assign $0\oper_r__imm_data__data[63:0] \oper_r__imm_data__data$next + sync posedge \coresync_clk + update \oper_r__imm_data__data $0\oper_r__imm_data__data[63:0] + end + attribute \src "libresoc.v:130456.3-130457.57" + process $proc$libresoc.v:130456$5983 + assign { } { } + assign $0\oper_r__imm_data__ok[0:0] \oper_r__imm_data__ok$next + sync posedge \coresync_clk + update \oper_r__imm_data__ok $0\oper_r__imm_data__ok[0:0] + end + attribute \src "libresoc.v:130458.3-130459.45" + process $proc$libresoc.v:130458$5984 + assign { } { } + assign $0\oper_r__zero_a[0:0] \oper_r__zero_a$next + sync posedge \coresync_clk + update \oper_r__zero_a $0\oper_r__zero_a[0:0] + end + attribute \src "libresoc.v:130460.3-130461.45" + process $proc$libresoc.v:130460$5985 + assign { } { } + assign $0\oper_r__rc__rc[0:0] \oper_r__rc__rc$next + sync posedge \coresync_clk + update \oper_r__rc__rc $0\oper_r__rc__rc[0:0] + end + attribute \src "libresoc.v:130462.3-130463.45" + process $proc$libresoc.v:130462$5986 + assign { } { } + assign $0\oper_r__rc__ok[0:0] \oper_r__rc__ok$next + sync posedge \coresync_clk + update \oper_r__rc__ok $0\oper_r__rc__ok[0:0] + end + attribute \src "libresoc.v:130464.3-130465.45" + process $proc$libresoc.v:130464$5987 + assign { } { } + assign $0\oper_r__oe__oe[0:0] \oper_r__oe__oe$next + sync posedge \coresync_clk + update \oper_r__oe__oe $0\oper_r__oe__oe[0:0] + end + attribute \src "libresoc.v:130466.3-130467.45" + process $proc$libresoc.v:130466$5988 + assign { } { } + assign $0\oper_r__oe__ok[0:0] \oper_r__oe__ok$next + sync posedge \coresync_clk + update \oper_r__oe__ok $0\oper_r__oe__ok[0:0] + end + attribute \src "libresoc.v:130468.3-130469.49" + process $proc$libresoc.v:130468$5989 + assign { } { } + assign $0\oper_r__is_32bit[0:0] \oper_r__is_32bit$next + sync posedge \coresync_clk + update \oper_r__is_32bit $0\oper_r__is_32bit[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:42781$1013 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ibus__ack - connect \B \ibus__err - connect \Y $or$libresoc.v:42781$1013_Y + attribute \src "libresoc.v:130470.3-130471.51" + process $proc$libresoc.v:130470$5990 + assign { } { } + assign $0\oper_r__is_signed[0:0] \oper_r__is_signed$next + sync posedge \coresync_clk + update \oper_r__is_signed $0\oper_r__is_signed[0:0] end - attribute \src "libresoc.v:42642.7-42642.20" - process $proc$libresoc.v:42642$1064 + attribute \src "libresoc.v:130472.3-130473.49" + process $proc$libresoc.v:130472$5991 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + assign $0\oper_r__data_len[3:0] \oper_r__data_len$next + sync posedge \coresync_clk + update \oper_r__data_len $0\oper_r__data_len[3:0] end - attribute \src "libresoc.v:42706.14-42706.44" - process $proc$libresoc.v:42706$1065 + attribute \src "libresoc.v:130474.3-130475.57" + process $proc$libresoc.v:130474$5992 assign { } { } - assign $1\f_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 - sync always - sync init - update \f_badaddr_o $1\f_badaddr_o[44:0] + assign $0\oper_r__byte_reverse[0:0] \oper_r__byte_reverse$next + sync posedge \coresync_clk + update \oper_r__byte_reverse $0\oper_r__byte_reverse[0:0] end - attribute \src "libresoc.v:42713.7-42713.27" - process $proc$libresoc.v:42713$1066 + attribute \src "libresoc.v:130476.3-130477.55" + process $proc$libresoc.v:130476$5993 assign { } { } - assign $1\f_fetch_err_o[0:0] 1'0 - sync always - sync init - update \f_fetch_err_o $1\f_fetch_err_o[0:0] + assign $0\oper_r__sign_extend[0:0] \oper_r__sign_extend$next + sync posedge \coresync_clk + update \oper_r__sign_extend $0\oper_r__sign_extend[0:0] end - attribute \src "libresoc.v:42727.14-42727.42" - process $proc$libresoc.v:42727$1067 + attribute \src "libresoc.v:130478.3-130479.51" + process $proc$libresoc.v:130478$5994 assign { } { } - assign $1\ibus__adr[44:0] 45'000000000000000000000000000000000000000000000 - sync always - sync init - update \ibus__adr $1\ibus__adr[44:0] + assign $0\oper_r__ldst_mode[1:0] \oper_r__ldst_mode$next + sync posedge \coresync_clk + update \oper_r__ldst_mode $0\oper_r__ldst_mode[1:0] end - attribute \src "libresoc.v:42732.7-42732.23" - process $proc$libresoc.v:42732$1068 + attribute \src "libresoc.v:130480.3-130481.41" + process $proc$libresoc.v:130480$5995 assign { } { } - assign $1\ibus__cyc[0:0] 1'0 - sync always - sync init - update \ibus__cyc $1\ibus__cyc[0:0] + assign $0\oper_r__insn[31:0] \oper_r__insn$next + sync posedge \coresync_clk + update \oper_r__insn $0\oper_r__insn[31:0] end - attribute \src "libresoc.v:42741.13-42741.30" - process $proc$libresoc.v:42741$1069 + attribute \src "libresoc.v:130482.3-130483.39" + process $proc$libresoc.v:130482$5996 assign { } { } - assign $1\ibus__sel[7:0] 8'00000000 - sync always - sync init - update \ibus__sel $1\ibus__sel[7:0] + assign $0\lsd_l_r_lsd[0:0] \lsd_l_r_lsd$next + sync posedge \coresync_clk + update \lsd_l_r_lsd $0\lsd_l_r_lsd[0:0] end - attribute \src "libresoc.v:42746.7-42746.23" - process $proc$libresoc.v:42746$1070 + attribute \src "libresoc.v:130484.3-130485.39" + process $proc$libresoc.v:130484$5997 assign { } { } - assign $1\ibus__stb[0:0] 1'0 - sync always - sync init - update \ibus__stb $1\ibus__stb[0:0] + assign $0\sto_l_r_sto[0:0] \sto_l_r_sto$next + sync posedge \coresync_clk + update \sto_l_r_sto $0\sto_l_r_sto[0:0] end - attribute \src "libresoc.v:42750.14-42750.47" - process $proc$libresoc.v:42750$1071 + attribute \src "libresoc.v:130486.3-130487.39" + process $proc$libresoc.v:130486$5998 assign { } { } - assign $1\ibus_rdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \ibus_rdata $1\ibus_rdata[63:0] + assign $0\upd_l_r_upd[0:0] \upd_l_r_upd$next + sync posedge \coresync_clk + update \upd_l_r_upd $0\upd_l_r_upd[0:0] end - attribute \src "libresoc.v:42783.3-42784.39" - process $proc$libresoc.v:42783$1015 + attribute \src "libresoc.v:130488.3-130489.39" + process $proc$libresoc.v:130488$5999 assign { } { } - assign $0\f_badaddr_o[44:0] \f_badaddr_o$next - sync posedge \clk - update \f_badaddr_o $0\f_badaddr_o[44:0] + assign $0\upd_l_s_upd[0:0] \upd_l_s_upd$next + sync posedge \coresync_clk + update \upd_l_s_upd $0\upd_l_s_upd[0:0] end - attribute \src "libresoc.v:42785.3-42786.43" - process $proc$libresoc.v:42785$1016 + attribute \src "libresoc.v:130490.3-130491.39" + process $proc$libresoc.v:130490$6000 assign { } { } - assign $0\f_fetch_err_o[0:0] \f_fetch_err_o$next - sync posedge \clk - update \f_fetch_err_o $0\f_fetch_err_o[0:0] + assign $0\wri_l_r_wri[0:0] \wri_l_r_wri$next + sync posedge \coresync_clk + update \wri_l_r_wri $0\wri_l_r_wri[0:0] end - attribute \src "libresoc.v:42787.3-42788.35" - process $proc$libresoc.v:42787$1017 + attribute \src "libresoc.v:130492.3-130493.39" + process $proc$libresoc.v:130492$6001 assign { } { } - assign $0\ibus__adr[44:0] \ibus__adr$next - sync posedge \clk - update \ibus__adr $0\ibus__adr[44:0] + assign $0\adr_l_r_adr[0:0] \adr_l_r_adr$next + sync posedge \coresync_clk + update \adr_l_r_adr $0\adr_l_r_adr[0:0] end - attribute \src "libresoc.v:42789.3-42790.37" - process $proc$libresoc.v:42789$1018 + attribute \src "libresoc.v:130494.3-130495.39" + process $proc$libresoc.v:130494$6002 assign { } { } - assign $0\ibus_rdata[63:0] \ibus_rdata$next - sync posedge \clk - update \ibus_rdata $0\ibus_rdata[63:0] + assign $0\src_l_r_src[2:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:42791.3-42792.35" - process $proc$libresoc.v:42791$1019 + attribute \src "libresoc.v:130496.3-130497.39" + process $proc$libresoc.v:130496$6003 assign { } { } - assign $0\ibus__sel[7:0] \ibus__sel$next - sync posedge \clk - update \ibus__sel $0\ibus__sel[7:0] + assign $0\src_l_s_src[2:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:42793.3-42794.35" - process $proc$libresoc.v:42793$1020 + attribute \src "libresoc.v:130498.3-130499.39" + process $proc$libresoc.v:130498$6004 assign { } { } - assign $0\ibus__stb[0:0] \ibus__stb$next - sync posedge \clk - update \ibus__stb $0\ibus__stb[0:0] + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:42795.3-42796.35" - process $proc$libresoc.v:42795$1021 + attribute \src "libresoc.v:130500.3-130501.39" + process $proc$libresoc.v:130500$6005 assign { } { } - assign $0\ibus__cyc[0:0] \ibus__cyc$next - sync posedge \clk - update \ibus__cyc $0\ibus__cyc[0:0] + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:42797.3-42824.6" - process $proc$libresoc.v:42797$1022 + attribute \src "libresoc.v:130502.3-130503.28" + process $proc$libresoc.v:130502$6006 assign { } { } + assign $0\p_st_go[0:0] \cu_st__go_i + sync posedge \coresync_clk + update \p_st_go $0\p_st_go[0:0] + end + attribute \src "libresoc.v:130574.3-130582.6" + process $proc$libresoc.v:130574$6007 assign { } { } assign { } { } - assign $0\ibus__cyc$next[0:0]$1023 $4\ibus__cyc$next[0:0]$1027 - attribute \src "libresoc.v:42798.5-42798.29" + assign $0\opc_l_s_opc$next[0:0]$6008 $1\opc_l_s_opc$next[0:0]$6009 + attribute \src "libresoc.v:130575.5-130575.29" switch \initial - attribute \src "libresoc.v:42798.9-42798.17" + attribute \src "libresoc.v:130575.9-130575.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" - switch \wb_icache_en + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ibus__cyc$next[0:0]$1024 $2\ibus__cyc$next[0:0]$1025 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" - switch { \$3 \ibus__cyc } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\ibus__cyc$next[0:0]$1025 $3\ibus__cyc$next[0:0]$1026 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - switch \$9 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ibus__cyc$next[0:0]$1026 1'0 - case - assign $3\ibus__cyc$next[0:0]$1026 \ibus__cyc - end - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\ibus__cyc$next[0:0]$1025 1'1 - case - assign $2\ibus__cyc$next[0:0]$1025 \ibus__cyc - end + assign $1\opc_l_s_opc$next[0:0]$6009 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$6009 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6008 + end + attribute \src "libresoc.v:130583.3-130591.6" + process $proc$libresoc.v:130583$6010 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$6011 $1\opc_l_r_opc$next[0:0]$6012 + attribute \src "libresoc.v:130584.5-130584.29" + switch \initial + attribute \src "libresoc.v:130584.9-130584.17" + case 1'1 case - assign $1\ibus__cyc$next[0:0]$1024 \ibus__cyc end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\ibus__cyc$next[0:0]$1027 1'0 + assign $1\opc_l_r_opc$next[0:0]$6012 1'1 case - assign $4\ibus__cyc$next[0:0]$1027 $1\ibus__cyc$next[0:0]$1024 + assign $1\opc_l_r_opc$next[0:0]$6012 \reset_o end sync always - update \ibus__cyc$next $0\ibus__cyc$next[0:0]$1023 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6011 end - attribute \src "libresoc.v:42825.3-42852.6" - process $proc$libresoc.v:42825$1028 + attribute \src "libresoc.v:130592.3-130600.6" + process $proc$libresoc.v:130592$6013 assign { } { } assign { } { } - assign { } { } - assign $0\ibus__stb$next[0:0]$1029 $4\ibus__stb$next[0:0]$1033 - attribute \src "libresoc.v:42826.5-42826.29" + assign $0\src_l_s_src$next[2:0]$6014 $1\src_l_s_src$next[2:0]$6015 + attribute \src "libresoc.v:130593.5-130593.29" switch \initial - attribute \src "libresoc.v:42826.9-42826.17" + attribute \src "libresoc.v:130593.9-130593.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" - switch \wb_icache_en + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ibus__stb$next[0:0]$1030 $2\ibus__stb$next[0:0]$1031 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" - switch { \$13 \ibus__cyc } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\ibus__stb$next[0:0]$1031 $3\ibus__stb$next[0:0]$1032 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - switch \$19 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ibus__stb$next[0:0]$1032 1'0 - case - assign $3\ibus__stb$next[0:0]$1032 \ibus__stb - end - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\ibus__stb$next[0:0]$1031 1'1 - case - assign $2\ibus__stb$next[0:0]$1031 \ibus__stb - end + assign $1\src_l_s_src$next[2:0]$6015 3'000 + case + assign $1\src_l_s_src$next[2:0]$6015 { \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6014 + end + attribute \src "libresoc.v:130601.3-130609.6" + process $proc$libresoc.v:130601$6016 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[2:0]$6017 $1\src_l_r_src$next[2:0]$6018 + attribute \src "libresoc.v:130602.5-130602.29" + switch \initial + attribute \src "libresoc.v:130602.9-130602.17" + case 1'1 case - assign $1\ibus__stb$next[0:0]$1030 \ibus__stb end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\ibus__stb$next[0:0]$1033 1'0 + assign $1\src_l_r_src$next[2:0]$6018 3'111 case - assign $4\ibus__stb$next[0:0]$1033 $1\ibus__stb$next[0:0]$1030 + assign $1\src_l_r_src$next[2:0]$6018 \reset_r end sync always - update \ibus__stb$next $0\ibus__stb$next[0:0]$1029 + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6017 end - attribute \src "libresoc.v:42853.3-42880.6" - process $proc$libresoc.v:42853$1034 + attribute \src "libresoc.v:130610.3-130618.6" + process $proc$libresoc.v:130610$6019 assign { } { } + assign { } { } + assign $0\adr_l_r_adr$next[0:0]$6020 $1\adr_l_r_adr$next[0:0]$6021 + attribute \src "libresoc.v:130611.5-130611.29" + switch \initial + attribute \src "libresoc.v:130611.9-130611.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\adr_l_r_adr$next[0:0]$6021 1'1 + case + assign $1\adr_l_r_adr$next[0:0]$6021 \reset_a + end + sync always + update \adr_l_r_adr$next $0\adr_l_r_adr$next[0:0]$6020 + end + attribute \src "libresoc.v:130619.3-130627.6" + process $proc$libresoc.v:130619$6022 assign { } { } assign { } { } - assign $0\ibus__sel$next[7:0]$1035 $4\ibus__sel$next[7:0]$1039 - attribute \src "libresoc.v:42854.5-42854.29" + assign $0\wri_l_r_wri$next[0:0]$6023 $1\wri_l_r_wri$next[0:0]$6024 + attribute \src "libresoc.v:130620.5-130620.29" switch \initial - attribute \src "libresoc.v:42854.9-42854.17" + attribute \src "libresoc.v:130620.9-130620.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" - switch \wb_icache_en + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ibus__sel$next[7:0]$1036 $2\ibus__sel$next[7:0]$1037 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" - switch { \$23 \ibus__cyc } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\ibus__sel$next[7:0]$1037 $3\ibus__sel$next[7:0]$1038 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - switch \$29 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ibus__sel$next[7:0]$1038 8'00000000 - case - assign $3\ibus__sel$next[7:0]$1038 \ibus__sel - end - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\ibus__sel$next[7:0]$1037 8'11111111 - case - assign $2\ibus__sel$next[7:0]$1037 \ibus__sel - end + assign $1\wri_l_r_wri$next[0:0]$6024 1'1 + case + assign $1\wri_l_r_wri$next[0:0]$6024 \$38 [0] + end + sync always + update \wri_l_r_wri$next $0\wri_l_r_wri$next[0:0]$6023 + end + attribute \src "libresoc.v:130628.3-130636.6" + process $proc$libresoc.v:130628$6025 + assign { } { } + assign { } { } + assign $0\upd_l_s_upd$next[0:0]$6026 $1\upd_l_s_upd$next[0:0]$6027 + attribute \src "libresoc.v:130629.5-130629.29" + switch \initial + attribute \src "libresoc.v:130629.9-130629.17" + case 1'1 case - assign $1\ibus__sel$next[7:0]$1036 \ibus__sel end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\ibus__sel$next[7:0]$1039 8'00000000 + assign $1\upd_l_s_upd$next[0:0]$6027 1'0 case - assign $4\ibus__sel$next[7:0]$1039 $1\ibus__sel$next[7:0]$1036 + assign $1\upd_l_s_upd$next[0:0]$6027 \reset_i end sync always - update \ibus__sel$next $0\ibus__sel$next[7:0]$1035 + update \upd_l_s_upd$next $0\upd_l_s_upd$next[0:0]$6026 end - attribute \src "libresoc.v:42881.3-42905.6" - process $proc$libresoc.v:42881$1040 + attribute \src "libresoc.v:130637.3-130645.6" + process $proc$libresoc.v:130637$6028 + assign { } { } assign { } { } + assign $0\upd_l_r_upd$next[0:0]$6029 $1\upd_l_r_upd$next[0:0]$6030 + attribute \src "libresoc.v:130638.5-130638.29" + switch \initial + attribute \src "libresoc.v:130638.9-130638.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\upd_l_r_upd$next[0:0]$6030 1'1 + case + assign $1\upd_l_r_upd$next[0:0]$6030 \reset_u + end + sync always + update \upd_l_r_upd$next $0\upd_l_r_upd$next[0:0]$6029 + end + attribute \src "libresoc.v:130646.3-130654.6" + process $proc$libresoc.v:130646$6031 assign { } { } assign { } { } - assign $0\ibus_rdata$next[63:0]$1041 $4\ibus_rdata$next[63:0]$1045 - attribute \src "libresoc.v:42882.5-42882.29" + assign $0\sto_l_r_sto$next[0:0]$6032 $1\sto_l_r_sto$next[0:0]$6033 + attribute \src "libresoc.v:130647.5-130647.29" switch \initial - attribute \src "libresoc.v:42882.9-42882.17" + attribute \src "libresoc.v:130647.9-130647.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" - switch \wb_icache_en + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ibus_rdata$next[63:0]$1042 $2\ibus_rdata$next[63:0]$1043 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" - switch { \$33 \ibus__cyc } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\ibus_rdata$next[63:0]$1043 $3\ibus_rdata$next[63:0]$1044 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - switch \$39 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ibus_rdata$next[63:0]$1044 \ibus__dat_r - case - assign $3\ibus_rdata$next[63:0]$1044 \ibus_rdata - end - case - assign $2\ibus_rdata$next[63:0]$1043 \ibus_rdata - end + assign $1\sto_l_r_sto$next[0:0]$6033 1'1 + case + assign $1\sto_l_r_sto$next[0:0]$6033 \$59 + end + sync always + update \sto_l_r_sto$next $0\sto_l_r_sto$next[0:0]$6032 + end + attribute \src "libresoc.v:130655.3-130663.6" + process $proc$libresoc.v:130655$6034 + assign { } { } + assign { } { } + assign $0\lsd_l_r_lsd$next[0:0]$6035 $1\lsd_l_r_lsd$next[0:0]$6036 + attribute \src "libresoc.v:130656.5-130656.29" + switch \initial + attribute \src "libresoc.v:130656.9-130656.17" + case 1'1 case - assign $1\ibus_rdata$next[63:0]$1042 \ibus_rdata end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\ibus_rdata$next[63:0]$1045 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\lsd_l_r_lsd$next[0:0]$6036 1'1 case - assign $4\ibus_rdata$next[63:0]$1045 $1\ibus_rdata$next[63:0]$1042 + assign $1\lsd_l_r_lsd$next[0:0]$6036 \$63 end sync always - update \ibus_rdata$next $0\ibus_rdata$next[63:0]$1041 + update \lsd_l_r_lsd$next $0\lsd_l_r_lsd$next[0:0]$6035 end - attribute \src "libresoc.v:42906.3-42928.6" - process $proc$libresoc.v:42906$1046 + attribute \src "libresoc.v:130664.3-130706.6" + process $proc$libresoc.v:130664$6037 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\ibus__adr$next[44:0]$1047 $3\ibus__adr$next[44:0]$1050 - attribute \src "libresoc.v:42907.5-42907.29" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\oper_r__byte_reverse$next[0:0]$6038 $2\oper_r__byte_reverse$next[0:0]$6070 + assign $0\oper_r__data_len$next[3:0]$6039 $2\oper_r__data_len$next[3:0]$6071 + assign $0\oper_r__fn_unit$next[11:0]$6040 $2\oper_r__fn_unit$next[11:0]$6072 + assign { } { } + assign { } { } + assign $0\oper_r__insn$next[31:0]$6043 $2\oper_r__insn$next[31:0]$6075 + assign $0\oper_r__insn_type$next[6:0]$6044 $2\oper_r__insn_type$next[6:0]$6076 + assign $0\oper_r__is_32bit$next[0:0]$6045 $2\oper_r__is_32bit$next[0:0]$6077 + assign $0\oper_r__is_signed$next[0:0]$6046 $2\oper_r__is_signed$next[0:0]$6078 + assign $0\oper_r__ldst_mode$next[1:0]$6047 $2\oper_r__ldst_mode$next[1:0]$6079 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\oper_r__sign_extend$next[0:0]$6052 $2\oper_r__sign_extend$next[0:0]$6084 + assign $0\oper_r__zero_a$next[0:0]$6053 $2\oper_r__zero_a$next[0:0]$6085 + assign $0\oper_r__imm_data__data$next[63:0]$6041 $3\oper_r__imm_data__data$next[63:0]$6086 + assign $0\oper_r__imm_data__ok$next[0:0]$6042 $3\oper_r__imm_data__ok$next[0:0]$6087 + assign $0\oper_r__oe__oe$next[0:0]$6048 $3\oper_r__oe__oe$next[0:0]$6088 + assign $0\oper_r__oe__ok$next[0:0]$6049 $3\oper_r__oe__ok$next[0:0]$6089 + assign $0\oper_r__rc__ok$next[0:0]$6050 $3\oper_r__rc__ok$next[0:0]$6090 + assign $0\oper_r__rc__rc$next[0:0]$6051 $3\oper_r__rc__rc$next[0:0]$6091 + attribute \src "libresoc.v:130665.5-130665.29" switch \initial - attribute \src "libresoc.v:42907.9-42907.17" + attribute \src "libresoc.v:130665.9-130665.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" - switch \wb_icache_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:379" + switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ibus__adr$next[44:0]$1048 $2\ibus__adr$next[44:0]$1049 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" - switch { \$43 \ibus__cyc } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign $2\ibus__adr$next[44:0]$1049 \ibus__adr - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\ibus__adr$next[44:0]$1049 \a_pc_i [47:3] - case - assign $2\ibus__adr$next[44:0]$1049 \ibus__adr - end + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\oper_r__insn$next[31:0]$6059 $1\oper_r__ldst_mode$next[1:0]$6063 $1\oper_r__sign_extend$next[0:0]$6068 $1\oper_r__byte_reverse$next[0:0]$6054 $1\oper_r__data_len$next[3:0]$6055 $1\oper_r__is_signed$next[0:0]$6062 $1\oper_r__is_32bit$next[0:0]$6061 $1\oper_r__oe__ok$next[0:0]$6065 $1\oper_r__oe__oe$next[0:0]$6064 $1\oper_r__rc__ok$next[0:0]$6066 $1\oper_r__rc__rc$next[0:0]$6067 $1\oper_r__zero_a$next[0:0]$6069 $1\oper_r__imm_data__ok$next[0:0]$6058 $1\oper_r__imm_data__data$next[63:0]$6057 $1\oper_r__fn_unit$next[11:0]$6056 $1\oper_r__insn_type$next[6:0]$6060 } { \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__insn_type } + case + assign $1\oper_r__byte_reverse$next[0:0]$6054 \oper_r__byte_reverse + assign $1\oper_r__data_len$next[3:0]$6055 \oper_r__data_len + assign $1\oper_r__fn_unit$next[11:0]$6056 \oper_r__fn_unit + assign $1\oper_r__imm_data__data$next[63:0]$6057 \oper_r__imm_data__data + assign $1\oper_r__imm_data__ok$next[0:0]$6058 \oper_r__imm_data__ok + assign $1\oper_r__insn$next[31:0]$6059 \oper_r__insn + assign $1\oper_r__insn_type$next[6:0]$6060 \oper_r__insn_type + assign $1\oper_r__is_32bit$next[0:0]$6061 \oper_r__is_32bit + assign $1\oper_r__is_signed$next[0:0]$6062 \oper_r__is_signed + assign $1\oper_r__ldst_mode$next[1:0]$6063 \oper_r__ldst_mode + assign $1\oper_r__oe__oe$next[0:0]$6064 \oper_r__oe__oe + assign $1\oper_r__oe__ok$next[0:0]$6065 \oper_r__oe__ok + assign $1\oper_r__rc__ok$next[0:0]$6066 \oper_r__rc__ok + assign $1\oper_r__rc__rc$next[0:0]$6067 \oper_r__rc__rc + assign $1\oper_r__sign_extend$next[0:0]$6068 \oper_r__sign_extend + assign $1\oper_r__zero_a$next[0:0]$6069 \oper_r__zero_a + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:381" + switch \cu_done_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\oper_r__insn$next[31:0]$6075 $2\oper_r__ldst_mode$next[1:0]$6079 $2\oper_r__sign_extend$next[0:0]$6084 $2\oper_r__byte_reverse$next[0:0]$6070 $2\oper_r__data_len$next[3:0]$6071 $2\oper_r__is_signed$next[0:0]$6078 $2\oper_r__is_32bit$next[0:0]$6077 $2\oper_r__oe__ok$next[0:0]$6081 $2\oper_r__oe__oe$next[0:0]$6080 $2\oper_r__rc__ok$next[0:0]$6082 $2\oper_r__rc__rc$next[0:0]$6083 $2\oper_r__zero_a$next[0:0]$6085 $2\oper_r__imm_data__ok$next[0:0]$6074 $2\oper_r__imm_data__data$next[63:0]$6073 $2\oper_r__fn_unit$next[11:0]$6072 $2\oper_r__insn_type$next[6:0]$6076 } 131'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 case - assign $1\ibus__adr$next[44:0]$1048 \ibus__adr + assign $2\oper_r__byte_reverse$next[0:0]$6070 $1\oper_r__byte_reverse$next[0:0]$6054 + assign $2\oper_r__data_len$next[3:0]$6071 $1\oper_r__data_len$next[3:0]$6055 + assign $2\oper_r__fn_unit$next[11:0]$6072 $1\oper_r__fn_unit$next[11:0]$6056 + assign $2\oper_r__imm_data__data$next[63:0]$6073 $1\oper_r__imm_data__data$next[63:0]$6057 + assign $2\oper_r__imm_data__ok$next[0:0]$6074 $1\oper_r__imm_data__ok$next[0:0]$6058 + assign $2\oper_r__insn$next[31:0]$6075 $1\oper_r__insn$next[31:0]$6059 + assign $2\oper_r__insn_type$next[6:0]$6076 $1\oper_r__insn_type$next[6:0]$6060 + assign $2\oper_r__is_32bit$next[0:0]$6077 $1\oper_r__is_32bit$next[0:0]$6061 + assign $2\oper_r__is_signed$next[0:0]$6078 $1\oper_r__is_signed$next[0:0]$6062 + assign $2\oper_r__ldst_mode$next[1:0]$6079 $1\oper_r__ldst_mode$next[1:0]$6063 + assign $2\oper_r__oe__oe$next[0:0]$6080 $1\oper_r__oe__oe$next[0:0]$6064 + assign $2\oper_r__oe__ok$next[0:0]$6081 $1\oper_r__oe__ok$next[0:0]$6065 + assign $2\oper_r__rc__ok$next[0:0]$6082 $1\oper_r__rc__ok$next[0:0]$6066 + assign $2\oper_r__rc__rc$next[0:0]$6083 $1\oper_r__rc__rc$next[0:0]$6067 + assign $2\oper_r__sign_extend$next[0:0]$6084 $1\oper_r__sign_extend$next[0:0]$6068 + assign $2\oper_r__zero_a$next[0:0]$6085 $1\oper_r__zero_a$next[0:0]$6069 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $3\oper_r__imm_data__data$next[63:0]$6086 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\oper_r__imm_data__ok$next[0:0]$6087 1'0 + assign $3\oper_r__rc__rc$next[0:0]$6091 1'0 + assign $3\oper_r__rc__ok$next[0:0]$6090 1'0 + assign $3\oper_r__oe__oe$next[0:0]$6088 1'0 + assign $3\oper_r__oe__ok$next[0:0]$6089 1'0 + case + assign $3\oper_r__imm_data__data$next[63:0]$6086 $2\oper_r__imm_data__data$next[63:0]$6073 + assign $3\oper_r__imm_data__ok$next[0:0]$6087 $2\oper_r__imm_data__ok$next[0:0]$6074 + assign $3\oper_r__oe__oe$next[0:0]$6088 $2\oper_r__oe__oe$next[0:0]$6080 + assign $3\oper_r__oe__ok$next[0:0]$6089 $2\oper_r__oe__ok$next[0:0]$6081 + assign $3\oper_r__rc__ok$next[0:0]$6090 $2\oper_r__rc__ok$next[0:0]$6082 + assign $3\oper_r__rc__rc$next[0:0]$6091 $2\oper_r__rc__rc$next[0:0]$6083 + end + sync always + update \oper_r__byte_reverse$next $0\oper_r__byte_reverse$next[0:0]$6038 + update \oper_r__data_len$next $0\oper_r__data_len$next[3:0]$6039 + update \oper_r__fn_unit$next $0\oper_r__fn_unit$next[11:0]$6040 + update \oper_r__imm_data__data$next $0\oper_r__imm_data__data$next[63:0]$6041 + update \oper_r__imm_data__ok$next $0\oper_r__imm_data__ok$next[0:0]$6042 + update \oper_r__insn$next $0\oper_r__insn$next[31:0]$6043 + update \oper_r__insn_type$next $0\oper_r__insn_type$next[6:0]$6044 + update \oper_r__is_32bit$next $0\oper_r__is_32bit$next[0:0]$6045 + update \oper_r__is_signed$next $0\oper_r__is_signed$next[0:0]$6046 + update \oper_r__ldst_mode$next $0\oper_r__ldst_mode$next[1:0]$6047 + update \oper_r__oe__oe$next $0\oper_r__oe__oe$next[0:0]$6048 + update \oper_r__oe__ok$next $0\oper_r__oe__ok$next[0:0]$6049 + update \oper_r__rc__ok$next $0\oper_r__rc__ok$next[0:0]$6050 + update \oper_r__rc__rc$next $0\oper_r__rc__rc$next[0:0]$6051 + update \oper_r__sign_extend$next $0\oper_r__sign_extend$next[0:0]$6052 + update \oper_r__zero_a$next $0\oper_r__zero_a$next[0:0]$6053 + end + attribute \src "libresoc.v:130707.3-130716.6" + process $proc$libresoc.v:130707$6092 + assign { } { } + assign { } { } + assign $0\ldo_r$next[63:0]$6093 $1\ldo_r$next[63:0]$6094 + attribute \src "libresoc.v:130708.5-130708.29" + switch \initial + attribute \src "libresoc.v:130708.9-130708.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \ld_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ibus__adr$next[44:0]$1050 45'000000000000000000000000000000000000000000000 + assign $1\ldo_r$next[63:0]$6094 \ldd_o case - assign $3\ibus__adr$next[44:0]$1050 $1\ibus__adr$next[44:0]$1048 + assign $1\ldo_r$next[63:0]$6094 \ldo_r end sync always - update \ibus__adr$next $0\ibus__adr$next[44:0]$1047 + update \ldo_r$next $0\ldo_r$next[63:0]$6093 end - attribute \src "libresoc.v:42929.3-42951.6" - process $proc$libresoc.v:42929$1051 + attribute \src "libresoc.v:130717.3-130732.6" + process $proc$libresoc.v:130717$6095 assign { } { } assign { } { } assign { } { } - assign $0\f_fetch_err_o$next[0:0]$1052 $3\f_fetch_err_o$next[0:0]$1055 - attribute \src "libresoc.v:42930.5-42930.29" + assign $0\src_r0$next[63:0]$6096 $2\src_r0$next[63:0]$6098 + attribute \src "libresoc.v:130718.5-130718.29" switch \initial - attribute \src "libresoc.v:42930.9-42930.17" + attribute \src "libresoc.v:130718.9-130718.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" - switch \wb_icache_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" + switch \cu_rd__go_i [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\f_fetch_err_o$next[0:0]$1053 $2\f_fetch_err_o$next[0:0]$1054 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - switch { \$47 \$45 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\f_fetch_err_o$next[0:0]$1054 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\f_fetch_err_o$next[0:0]$1054 1'0 - case - assign $2\f_fetch_err_o$next[0:0]$1054 \f_fetch_err_o - end + assign $1\src_r0$next[63:0]$6097 \src1_i case - assign $1\f_fetch_err_o$next[0:0]$1053 \f_fetch_err_o + assign $1\src_r0$next[63:0]$6097 \src_r0 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" + switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\f_fetch_err_o$next[0:0]$1055 1'0 + assign $2\src_r0$next[63:0]$6098 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\f_fetch_err_o$next[0:0]$1055 $1\f_fetch_err_o$next[0:0]$1053 + assign $2\src_r0$next[63:0]$6098 $1\src_r0$next[63:0]$6097 end sync always - update \f_fetch_err_o$next $0\f_fetch_err_o$next[0:0]$1052 + update \src_r0$next $0\src_r0$next[63:0]$6096 end - attribute \src "libresoc.v:42952.3-42971.6" - process $proc$libresoc.v:42952$1056 + attribute \src "libresoc.v:130733.3-130748.6" + process $proc$libresoc.v:130733$6099 assign { } { } assign { } { } assign { } { } - assign $0\f_badaddr_o$next[44:0]$1057 $3\f_badaddr_o$next[44:0]$1060 - attribute \src "libresoc.v:42953.5-42953.29" + assign $0\src_r1$next[63:0]$6100 $2\src_r1$next[63:0]$6102 + attribute \src "libresoc.v:130734.5-130734.29" switch \initial - attribute \src "libresoc.v:42953.9-42953.17" + attribute \src "libresoc.v:130734.9-130734.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" - switch \wb_icache_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" + switch \cu_rd__go_i [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\f_badaddr_o$next[44:0]$1058 $2\f_badaddr_o$next[44:0]$1059 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - switch { \$51 \$49 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\f_badaddr_o$next[44:0]$1059 \ibus__adr - case - assign $2\f_badaddr_o$next[44:0]$1059 \f_badaddr_o - end + assign $1\src_r1$next[63:0]$6101 \src2_i + case + assign $1\src_r1$next[63:0]$6101 \src_r1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src_r1$next[63:0]$6102 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\src_r1$next[63:0]$6102 $1\src_r1$next[63:0]$6101 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$6100 + end + attribute \src "libresoc.v:130749.3-130764.6" + process $proc$libresoc.v:130749$6103 + assign { } { } + assign { } { } + assign { } { } + assign $0\src_r2$next[63:0]$6104 $2\src_r2$next[63:0]$6106 + attribute \src "libresoc.v:130750.5-130750.29" + switch \initial + attribute \src "libresoc.v:130750.9-130750.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" + switch \cu_rd__go_i [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[63:0]$6105 \src3_i + case + assign $1\src_r2$next[63:0]$6105 \src_r2 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src_r2$next[63:0]$6106 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\src_r2$next[63:0]$6106 $1\src_r2$next[63:0]$6105 + end + sync always + update \src_r2$next $0\src_r2$next[63:0]$6104 + end + attribute \src "libresoc.v:130765.3-130774.6" + process $proc$libresoc.v:130765$6107 + assign { } { } + assign { } { } + assign $0\ea_r$next[63:0]$6108 $1\ea_r$next[63:0]$6109 + attribute \src "libresoc.v:130766.5-130766.29" + switch \initial + attribute \src "libresoc.v:130766.9-130766.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \alu_l_q_alu + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ea_r$next[63:0]$6109 \alu_o + case + assign $1\ea_r$next[63:0]$6109 \ea_r + end + sync always + update \ea_r$next $0\ea_r$next[63:0]$6108 + end + attribute \src "libresoc.v:130775.3-130784.6" + process $proc$libresoc.v:130775$6110 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:130776.5-130776.29" + switch \initial + attribute \src "libresoc.v:130776.9-130776.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" + switch \cu_wr__go_i [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \ldd_r + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "libresoc.v:130785.3-130794.6" + process $proc$libresoc.v:130785$6111 + assign { } { } + assign { } { } + assign $0\dest2_o[63:0] $1\dest2_o[63:0] + attribute \src "libresoc.v:130786.5-130786.29" + switch \initial + attribute \src "libresoc.v:130786.9-130786.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477" + switch \$164 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[63:0] \addr_r + case + assign $1\dest2_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest2_o $0\dest2_o[63:0] + end + attribute \src "libresoc.v:130795.3-130803.6" + process $proc$libresoc.v:130795$6112 + assign { } { } + assign { } { } + assign $0\ldst_port0_addr_i_ok$next[0:0]$6113 $1\ldst_port0_addr_i_ok$next[0:0]$6114 + attribute \src "libresoc.v:130796.5-130796.29" + switch \initial + attribute \src "libresoc.v:130796.9-130796.17" + case 1'1 case - assign $1\f_badaddr_o$next[44:0]$1058 \f_badaddr_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\f_badaddr_o$next[44:0]$1060 45'000000000000000000000000000000000000000000000 + assign $1\ldst_port0_addr_i_ok$next[0:0]$6114 1'0 case - assign $3\f_badaddr_o$next[44:0]$1060 $1\f_badaddr_o$next[44:0]$1058 + assign $1\ldst_port0_addr_i_ok$next[0:0]$6114 \$177 end sync always - update \f_badaddr_o$next $0\f_badaddr_o$next[44:0]$1057 + update \ldst_port0_addr_i_ok$next $0\ldst_port0_addr_i_ok$next[0:0]$6113 end - attribute \src "libresoc.v:42972.3-42981.6" - process $proc$libresoc.v:42972$1061 + attribute \src "libresoc.v:130804.3-130827.6" + process $proc$libresoc.v:130804$6115 assign { } { } assign { } { } - assign $0\a_busy_o[0:0] $1\a_busy_o[0:0] - attribute \src "libresoc.v:42973.5-42973.29" + assign $0\lddata_r[63:0] $1\lddata_r[63:0] + attribute \src "libresoc.v:130805.5-130805.29" switch \initial - attribute \src "libresoc.v:42973.9-42973.17" + attribute \src "libresoc.v:130805.9-130805.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" - switch \wb_icache_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:500" + switch \oper_r__byte_reverse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\a_busy_o[0:0] \ibus__cyc + assign $1\lddata_r[63:0] $2\lddata_r[63:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:22" + switch \oper_r__data_len + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $2\lddata_r[63:0] \$186 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $2\lddata_r[63:0] \$188 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $2\lddata_r[63:0] \$190 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $2\lddata_r[63:0] { \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] \ldst_port0_ld_data_o [23:16] \ldst_port0_ld_data_o [31:24] \ldst_port0_ld_data_o [39:32] \ldst_port0_ld_data_o [47:40] \ldst_port0_ld_data_o [55:48] \ldst_port0_ld_data_o [63:56] } + case + assign $2\lddata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end case - assign $1\a_busy_o[0:0] 1'0 + assign $1\lddata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \a_busy_o $0\a_busy_o[0:0] + update \lddata_r $0\lddata_r[63:0] end - attribute \src "libresoc.v:42982.3-42999.6" - process $proc$libresoc.v:42982$1062 + attribute \src "libresoc.v:130828.3-130839.6" + process $proc$libresoc.v:130828$6116 assign { } { } + assign $0\revnorev[63:0] $1\revnorev[63:0] + attribute \src "libresoc.v:130829.5-130829.29" + switch \initial + attribute \src "libresoc.v:130829.9-130829.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:500" + switch \oper_r__byte_reverse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\revnorev[63:0] \lddata_r + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\revnorev[63:0] \ldst_port0_ld_data_o + end + sync always + update \revnorev $0\revnorev[63:0] + end + attribute \src "libresoc.v:130840.3-130859.6" + process $proc$libresoc.v:130840$6117 assign { } { } - assign $0\f_busy_o[0:0] $1\f_busy_o[0:0] - attribute \src "libresoc.v:42983.5-42983.29" + assign $0\ldd_o[63:0] $1\ldd_o[63:0] + attribute \src "libresoc.v:130841.5-130841.29" switch \initial - attribute \src "libresoc.v:42983.9-42983.17" + attribute \src "libresoc.v:130841.9-130841.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" - switch \wb_icache_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:509" + switch \oper_r__sign_extend attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\f_busy_o[0:0] $2\f_busy_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:96" - switch \f_fetch_err_o + assign $1\ldd_o[63:0] $2\ldd_o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" + switch \$192 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\f_busy_o[0:0] 1'0 + assign $2\ldd_o[63:0] { \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15:0] } attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\f_busy_o[0:0] \ibus__cyc + assign $2\ldd_o[63:0] { \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31:0] } end + attribute \src "libresoc.v:0.0-0.0" case - assign $1\f_busy_o[0:0] 1'0 + assign { } { } + assign $1\ldd_o[63:0] \revnorev end sync always - update \f_busy_o $0\f_busy_o[0:0] + update \ldd_o $0\ldd_o[63:0] end - attribute \src "libresoc.v:43000.3-43017.6" - process $proc$libresoc.v:43000$1063 + attribute \src "libresoc.v:130860.3-130883.6" + process $proc$libresoc.v:130860$6118 assign { } { } assign { } { } - assign $0\f_instr_o[63:0] $1\f_instr_o[63:0] - attribute \src "libresoc.v:43001.5-43001.29" + assign $0\stdata_r[63:0] $1\stdata_r[63:0] + attribute \src "libresoc.v:130861.5-130861.29" switch \initial - attribute \src "libresoc.v:43001.9-43001.17" + attribute \src "libresoc.v:130861.9-130861.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" - switch \wb_icache_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" + switch \oper_r__byte_reverse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\f_instr_o[63:0] $2\f_instr_o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:96" - switch \f_fetch_err_o + assign $1\stdata_r[63:0] $2\stdata_r[63:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:22" + switch \oper_r__data_len attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\f_instr_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + case 4'0001 + assign { } { } + assign $2\stdata_r[63:0] \$194 attribute \src "libresoc.v:0.0-0.0" - case + case 4'0010 assign { } { } - assign $2\f_instr_o[63:0] \ibus_rdata + assign $2\stdata_r[63:0] \$196 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $2\stdata_r[63:0] \$198 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $2\stdata_r[63:0] { \src_r2 [7:0] \src_r2 [15:8] \src_r2 [23:16] \src_r2 [31:24] \src_r2 [39:32] \src_r2 [47:40] \src_r2 [55:48] \src_r2 [63:56] } + case + assign $2\stdata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end case - assign $1\f_instr_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\stdata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \f_instr_o $0\f_instr_o[63:0] + update \stdata_r $0\stdata_r[63:0] end - connect \$9 $or$libresoc.v:42757$989_Y - connect \$11 $not$libresoc.v:42758$990_Y - connect \$13 $and$libresoc.v:42759$991_Y - connect \$15 $or$libresoc.v:42760$992_Y - connect \$17 $not$libresoc.v:42761$993_Y - connect \$1 $not$libresoc.v:42762$994_Y - connect \$19 $or$libresoc.v:42763$995_Y - connect \$21 $not$libresoc.v:42764$996_Y - connect \$23 $and$libresoc.v:42765$997_Y - connect \$25 $or$libresoc.v:42766$998_Y - connect \$27 $not$libresoc.v:42767$999_Y - connect \$29 $or$libresoc.v:42768$1000_Y - connect \$31 $not$libresoc.v:42769$1001_Y - connect \$33 $and$libresoc.v:42770$1002_Y - connect \$35 $or$libresoc.v:42771$1003_Y - connect \$37 $not$libresoc.v:42772$1004_Y - connect \$3 $and$libresoc.v:42773$1005_Y - connect \$39 $or$libresoc.v:42774$1006_Y - connect \$41 $not$libresoc.v:42775$1007_Y - connect \$43 $and$libresoc.v:42776$1008_Y - connect \$45 $and$libresoc.v:42777$1009_Y - connect \$47 $not$libresoc.v:42778$1010_Y - connect \$49 $and$libresoc.v:42779$1011_Y - connect \$51 $not$libresoc.v:42780$1012_Y - connect \$5 $or$libresoc.v:42781$1013_Y - connect \$7 $not$libresoc.v:42782$1014_Y - connect \a_stall_i 1'0 - connect \f_stall_i 1'0 + attribute \src "libresoc.v:130884.3-130895.6" + process $proc$libresoc.v:130884$6119 + assign { } { } + assign $0\ldst_port0_st_data_i[63:0] $1\ldst_port0_st_data_i[63:0] + attribute \src "libresoc.v:130885.5-130885.29" + switch \initial + attribute \src "libresoc.v:130885.9-130885.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" + switch \oper_r__byte_reverse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_st_data_i[63:0] \stdata_r + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\ldst_port0_st_data_i[63:0] \src_r2 + end + sync always + update \ldst_port0_st_data_i $0\ldst_port0_st_data_i[63:0] + end + connect \$100 $and$libresoc.v:130343$5878_Y + connect \$102 $and$libresoc.v:130344$5879_Y + connect \$104 $and$libresoc.v:130345$5880_Y + connect \$106 $and$libresoc.v:130346$5881_Y + connect \$108 $and$libresoc.v:130347$5882_Y + connect \$10 $or$libresoc.v:130348$5883_Y + connect \$110 $and$libresoc.v:130349$5884_Y + connect \$112 $and$libresoc.v:130350$5885_Y + connect \$114 $and$libresoc.v:130351$5886_Y + connect \$116 $and$libresoc.v:130352$5887_Y + connect \$118 $and$libresoc.v:130353$5888_Y + connect \$120 $and$libresoc.v:130354$5889_Y + connect \$122 $and$libresoc.v:130355$5890_Y + connect \$124 $and$libresoc.v:130356$5891_Y + connect \$126 $eq$libresoc.v:130357$5892_Y + connect \$128 $and$libresoc.v:130358$5893_Y + connect \$12 $or$libresoc.v:130359$5894_Y + connect \$130 $and$libresoc.v:130360$5895_Y + connect \$132 $and$libresoc.v:130361$5896_Y + connect \$134 $or$libresoc.v:130362$5897_Y + connect \$136 $or$libresoc.v:130363$5898_Y + connect \$138 $or$libresoc.v:130364$5899_Y + connect \$140 $and$libresoc.v:130365$5900_Y + connect \$142 $and$libresoc.v:130366$5901_Y + connect \$145 $or$libresoc.v:130367$5902_Y + connect \$147 $or$libresoc.v:130368$5903_Y + connect \$144 $not$libresoc.v:130369$5904_Y + connect \$14 $or$libresoc.v:130370$5905_Y + connect \$150 $and$libresoc.v:130371$5906_Y + connect \$152 $or$libresoc.v:130372$5907_Y + connect \$154 $and$libresoc.v:130373$5908_Y + connect \$156 $not$libresoc.v:130374$5909_Y + connect \$158 $or$libresoc.v:130375$5910_Y + connect \$160 $and$libresoc.v:130376$5911_Y + connect \$162 $eq$libresoc.v:130377$5912_Y + connect \$164 $and$libresoc.v:130378$5913_Y + connect \$167 $eq$libresoc.v:130379$5914_Y + connect \$16 $or$libresoc.v:130380$5915_Y + connect \$169 $and$libresoc.v:130381$5916_Y + connect \$171 $and$libresoc.v:130382$5917_Y + connect \$173 $and$libresoc.v:130383$5918_Y + connect \$175 $pos$libresoc.v:130384$5920_Y + connect \$177 $and$libresoc.v:130385$5921_Y + connect \$186 $pos$libresoc.v:130386$5923_Y + connect \$188 $pos$libresoc.v:130387$5924_Y + connect \$18 $or$libresoc.v:130388$5925_Y + connect \$190 $pos$libresoc.v:130389$5926_Y + connect \$192 $eq$libresoc.v:130390$5927_Y + connect \$194 $pos$libresoc.v:130391$5929_Y + connect \$196 $pos$libresoc.v:130392$5930_Y + connect \$198 $pos$libresoc.v:130393$5931_Y + connect \$20 $or$libresoc.v:130394$5932_Y + connect \$22 $eq$libresoc.v:130395$5933_Y + connect \$24 $eq$libresoc.v:130396$5934_Y + connect \$26 $and$libresoc.v:130397$5935_Y + connect \$28 $and$libresoc.v:130398$5936_Y + connect \$30 $not$libresoc.v:130399$5937_Y + connect \$32 $and$libresoc.v:130400$5938_Y + connect \$34 $not$libresoc.v:130401$5939_Y + connect \$36 $and$libresoc.v:130402$5940_Y + connect \$39 $not$libresoc.v:130403$5941_Y + connect \$41 $eq$libresoc.v:130404$5942_Y + connect \$43 $and$libresoc.v:130405$5943_Y + connect \$45 $or$libresoc.v:130406$5944_Y + connect \$47 $not$libresoc.v:130407$5945_Y + connect \$49 $eq$libresoc.v:130408$5946_Y + connect \$51 $and$libresoc.v:130409$5947_Y + connect \$53 $or$libresoc.v:130410$5948_Y + connect \$55 $or$libresoc.v:130411$5949_Y + connect \$57 $and$libresoc.v:130412$5950_Y + connect \$59 $or$libresoc.v:130413$5951_Y + connect \$61 $or$libresoc.v:130414$5952_Y + connect \$63 $or$libresoc.v:130415$5953_Y + connect \$65 $ternary$libresoc.v:130416$5954_Y + connect \$67 $ternary$libresoc.v:130417$5955_Y + connect \$69 $ternary$libresoc.v:130418$5956_Y + connect \$71 $ternary$libresoc.v:130419$5957_Y + connect \$74 $add$libresoc.v:130420$5958_Y + connect \$76 $and$libresoc.v:130421$5959_Y + connect \$78 $not$libresoc.v:130422$5960_Y + connect \$80 $and$libresoc.v:130423$5961_Y + connect \$82 $not$libresoc.v:130424$5962_Y + connect \$84 $and$libresoc.v:130425$5963_Y + connect \$86 $and$libresoc.v:130426$5964_Y + connect \$88 $and$libresoc.v:130427$5965_Y + connect \$8 $or$libresoc.v:130428$5966_Y + connect \$90 $or$libresoc.v:130429$5967_Y + connect \$93 $or$libresoc.v:130430$5968_Y + connect \$92 $not$libresoc.v:130431$5969_Y + connect \$96 $and$libresoc.v:130432$5970_Y + connect \$98 $not$libresoc.v:130433$5971_Y + connect \$38 \$55 + connect \$73 \$74 + connect \$166 \$169 + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \ldst_port0_st_data_i_ok \cu_st__go_i + connect \ld_ok \ldst_port0_ld_data_o_ok + connect \addr_ok \ldst_port0_addr_ok_o + connect { \exc_$signal$185 \exc_$signal$184 \exc_$signal$183 \exc_$signal$182 \exc_$signal$181 \exc_$signal$180 \exc_$signal$179 \exc_$signal } { \ldst_port0_exc_$signal$7 \ldst_port0_exc_$signal$6 \ldst_port0_exc_$signal$5 \ldst_port0_exc_$signal$4 \ldst_port0_exc_$signal$3 \ldst_port0_exc_$signal$2 \ldst_port0_exc_$signal$1 \ldst_port0_exc_$signal } + connect \ldst_port0_addr_i$next \$175 + connect \ldst_port0_data_len \oper_r__data_len + connect \ldst_port0_is_st_i \$173 + connect \ldst_port0_is_ld_i \$171 + connect \cu_wrmask_o \$169 [1:0] + connect \ea \dest2_o + connect \o \dest1_o + connect \cu_done_o \$160 + connect \wr_reset \$154 + connect \wr_any \$138 + connect \cu_wr__rel_o [1] \$132 + connect \cu_wr__rel_o [0] \$122 + connect \cu_st__rel_o \$112 + connect \cu_ad__rel_o \$104 + connect \rd_done \$100 + connect \alu_valid \$96 + connect \rda_any \$90 + connect \cu_rd__rel_o [2] \$88 + connect \cu_rd__rel_o [1:0] \$84 [1:0] + connect \cu_busy_o \opc_l_q_opc + connect \alu_ok$next \alu_valid + connect \alu_o \$74 [63:0] + connect \src2_or_imm \$71 + connect \src1_or_z \$69 + connect \addr_r \$67 + connect \ldd_r \$65 + connect \rst_l_r_rst \cu_issue_i + connect \rst_l_s_rst \addr_ok + connect \lsd_l_s_lsd \cu_issue_i + connect \sto_l_s_sto \$57 + connect \wri_l_s_wri \cu_issue_i + connect \lod_l_r_lod \ld_ok + connect \lod_l_s_lod \reset_i + connect \adr_l_s_adr \reset_i + connect \alu_l_r_alu \$36 + connect \alu_l_s_alu \reset_i + connect \st_o \op_is_st + connect \ld_o \op_is_ld + connect \stwd_mem_o \$28 + connect \load_mem_o \$26 + connect \op_is_ld \$24 + connect \op_is_st \$22 + connect \p_st_go$next \cu_st__go_i + connect \reset_a \$20 + connect \reset_r \$18 + connect \reset_s \$16 + connect \reset_u \$14 + connect \reset_w \$12 + connect \reset_o \$10 + connect \reset_i \$8 end -attribute \src "libresoc.v:43024.1-45737.10" +attribute \src "libresoc.v:130959.1-131546.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.jtag" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.left_mask" attribute \generator "nMigen" -module \jtag - attribute \src "libresoc.v:45169.3-45195.6" - wire $0\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:44817.3-44832.6" - wire $0\TAP_tdo[0:0] - attribute \src "libresoc.v:45330.3-45362.6" - wire width 4 $0\dmi0__addr_i$next[3:0]$1482 - attribute \src "libresoc.v:44720.3-44721.41" - wire width 4 $0\dmi0__addr_i[3:0] - attribute \src "libresoc.v:45416.3-45442.6" - wire width 64 $0\dmi0__din$next[63:0]$1495 - attribute \src "libresoc.v:44716.3-44717.35" - wire width 64 $0\dmi0__din[63:0] - attribute \src "libresoc.v:45019.3-45035.6" - wire $0\dmi0_addrsr__oe$next[0:0]$1419 - attribute \src "libresoc.v:44748.3-44749.47" - wire $0\dmi0_addrsr__oe[0:0] - attribute \src "libresoc.v:45036.3-45056.6" - wire width 8 $0\dmi0_addrsr_reg$next[7:0]$1423 - attribute \src "libresoc.v:44746.3-44747.47" - wire width 8 $0\dmi0_addrsr_reg[7:0] - attribute \src "libresoc.v:45001.3-45009.6" - wire $0\dmi0_addrsr_update_core$next[0:0]$1413 - attribute \src "libresoc.v:44752.3-44753.63" - wire $0\dmi0_addrsr_update_core[0:0] - attribute \src "libresoc.v:45010.3-45018.6" - wire $0\dmi0_addrsr_update_core_prev$next[0:0]$1416 - attribute \src "libresoc.v:44750.3-44751.73" - wire $0\dmi0_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:45443.3-45463.6" - wire width 64 $0\dmi0_datasr__i$next[63:0]$1500 - attribute \src "libresoc.v:44714.3-44715.45" - wire width 64 $0\dmi0_datasr__i[63:0] - attribute \src "libresoc.v:45075.3-45091.6" - wire width 2 $0\dmi0_datasr__oe$next[1:0]$1434 - attribute \src "libresoc.v:44740.3-44741.47" - wire width 2 $0\dmi0_datasr__oe[1:0] - attribute \src "libresoc.v:45092.3-45112.6" - wire width 64 $0\dmi0_datasr_reg$next[63:0]$1438 - attribute \src "libresoc.v:44738.3-44739.47" - wire width 64 $0\dmi0_datasr_reg[63:0] - attribute \src "libresoc.v:45057.3-45065.6" - wire $0\dmi0_datasr_update_core$next[0:0]$1428 - attribute \src "libresoc.v:44744.3-44745.63" - wire $0\dmi0_datasr_update_core[0:0] - attribute \src "libresoc.v:45066.3-45074.6" - wire $0\dmi0_datasr_update_core_prev$next[0:0]$1431 - attribute \src "libresoc.v:44742.3-44743.73" - wire $0\dmi0_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:45363.3-45415.6" - wire width 3 $0\fsm_state$503$next[2:0]$1488 - attribute \src "libresoc.v:44718.3-44719.45" - wire width 3 $0\fsm_state$503[2:0]$1334 - attribute \src "libresoc.v:43670.13-43670.35" - wire width 3 $0\fsm_state$503[2:0]$1534 - attribute \src "libresoc.v:45229.3-45281.6" - wire width 3 $0\fsm_state$next[2:0]$1465 - attribute \src "libresoc.v:44726.3-44727.35" - wire width 3 $0\fsm_state[2:0] - attribute \src "libresoc.v:43025.7-43025.20" +module \left_mask + attribute \src "libresoc.v:130960.7-130960.20" wire $0\initial[0:0] - attribute \src "libresoc.v:45511.3-45531.6" - wire width 154 $0\io_bd$next[153:0]$1517 - attribute \src "libresoc.v:44778.3-44779.27" - wire width 154 $0\io_bd[153:0] - attribute \src "libresoc.v:45493.3-45510.6" - wire width 154 $0\io_sr$next[153:0]$1513 - attribute \src "libresoc.v:44780.3-44781.27" - wire width 154 $0\io_sr[153:0] - attribute \src "libresoc.v:45196.3-45228.6" - wire width 29 $0\jtag_wb__adr$next[28:0]$1459 - attribute \src "libresoc.v:44728.3-44729.41" - wire width 29 $0\jtag_wb__adr[28:0] - attribute \src "libresoc.v:45282.3-45308.6" - wire width 64 $0\jtag_wb__dat_w$next[63:0]$1472 - attribute \src "libresoc.v:44724.3-44725.45" - wire width 64 $0\jtag_wb__dat_w[63:0] - attribute \src "libresoc.v:44907.3-44923.6" - wire $0\jtag_wb_addrsr__oe$next[0:0]$1389 - attribute \src "libresoc.v:44764.3-44765.53" - wire $0\jtag_wb_addrsr__oe[0:0] - attribute \src "libresoc.v:44924.3-44944.6" - wire width 29 $0\jtag_wb_addrsr_reg$next[28:0]$1393 - attribute \src "libresoc.v:44762.3-44763.53" - wire width 29 $0\jtag_wb_addrsr_reg[28:0] - attribute \src "libresoc.v:44889.3-44897.6" - wire $0\jtag_wb_addrsr_update_core$next[0:0]$1383 - attribute \src "libresoc.v:44768.3-44769.69" - wire $0\jtag_wb_addrsr_update_core[0:0] - attribute \src "libresoc.v:44898.3-44906.6" - wire $0\jtag_wb_addrsr_update_core_prev$next[0:0]$1386 - attribute \src "libresoc.v:44766.3-44767.79" - wire $0\jtag_wb_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:45309.3-45329.6" - wire width 64 $0\jtag_wb_datasr__i$next[63:0]$1477 - attribute \src "libresoc.v:44722.3-44723.51" - wire width 64 $0\jtag_wb_datasr__i[63:0] - attribute \src "libresoc.v:44963.3-44979.6" - wire width 2 $0\jtag_wb_datasr__oe$next[1:0]$1404 - attribute \src "libresoc.v:44756.3-44757.53" - wire width 2 $0\jtag_wb_datasr__oe[1:0] - attribute \src "libresoc.v:44980.3-45000.6" - wire width 64 $0\jtag_wb_datasr_reg$next[63:0]$1408 - attribute \src "libresoc.v:44754.3-44755.53" - wire width 64 $0\jtag_wb_datasr_reg[63:0] - attribute \src "libresoc.v:44945.3-44953.6" - wire $0\jtag_wb_datasr_update_core$next[0:0]$1398 - attribute \src "libresoc.v:44760.3-44761.69" - wire $0\jtag_wb_datasr_update_core[0:0] - attribute \src "libresoc.v:44954.3-44962.6" - wire $0\jtag_wb_datasr_update_core_prev$next[0:0]$1401 - attribute \src "libresoc.v:44758.3-44759.79" - wire $0\jtag_wb_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:44851.3-44867.6" - wire $0\sr0__oe$next[0:0]$1374 - attribute \src "libresoc.v:44772.3-44773.31" - wire $0\sr0__oe[0:0] - attribute \src "libresoc.v:44868.3-44888.6" - wire width 3 $0\sr0_reg$next[2:0]$1378 - attribute \src "libresoc.v:44770.3-44771.31" - wire width 3 $0\sr0_reg[2:0] - attribute \src "libresoc.v:44833.3-44841.6" - wire $0\sr0_update_core$next[0:0]$1368 - attribute \src "libresoc.v:44776.3-44777.47" - wire $0\sr0_update_core[0:0] - attribute \src "libresoc.v:44842.3-44850.6" - wire $0\sr0_update_core_prev$next[0:0]$1371 - attribute \src "libresoc.v:44774.3-44775.57" - wire $0\sr0_update_core_prev[0:0] - attribute \src "libresoc.v:45483.3-45492.6" - wire width 2 $0\sr5__i[1:0] - attribute \src "libresoc.v:45131.3-45147.6" - wire $0\sr5__oe$next[0:0]$1449 - attribute \src "libresoc.v:44732.3-44733.31" - wire $0\sr5__oe[0:0] - attribute \src "libresoc.v:45148.3-45168.6" - wire width 2 $0\sr5_reg$next[1:0]$1453 - attribute \src "libresoc.v:44730.3-44731.31" - wire width 2 $0\sr5_reg[1:0] - attribute \src "libresoc.v:45113.3-45121.6" - wire $0\sr5_update_core$next[0:0]$1443 - attribute \src "libresoc.v:44736.3-44737.47" - wire $0\sr5_update_core[0:0] - attribute \src "libresoc.v:45122.3-45130.6" - wire $0\sr5_update_core_prev$next[0:0]$1446 - attribute \src "libresoc.v:44734.3-44735.57" - wire $0\sr5_update_core_prev[0:0] - attribute \src "libresoc.v:45464.3-45482.6" - wire $0\wb_dcache_en$next[0:0]$1505 - attribute \src "libresoc.v:44712.3-44713.41" - wire $0\wb_dcache_en[0:0] - attribute \src "libresoc.v:45464.3-45482.6" - wire $0\wb_icache_en$next[0:0]$1506 - attribute \src "libresoc.v:44710.3-44711.41" - wire $0\wb_icache_en[0:0] - attribute \src "libresoc.v:45169.3-45195.6" - wire $1\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:44817.3-44832.6" - wire $1\TAP_tdo[0:0] - attribute \src "libresoc.v:45330.3-45362.6" - wire width 4 $1\dmi0__addr_i$next[3:0]$1483 - attribute \src "libresoc.v:43583.13-43583.32" - wire width 4 $1\dmi0__addr_i[3:0] - attribute \src "libresoc.v:45416.3-45442.6" - wire width 64 $1\dmi0__din$next[63:0]$1496 - attribute \src "libresoc.v:43588.14-43588.46" - wire width 64 $1\dmi0__din[63:0] - attribute \src "libresoc.v:45019.3-45035.6" - wire $1\dmi0_addrsr__oe$next[0:0]$1420 - attribute \src "libresoc.v:43602.7-43602.29" - wire $1\dmi0_addrsr__oe[0:0] - attribute \src "libresoc.v:45036.3-45056.6" - wire width 8 $1\dmi0_addrsr_reg$next[7:0]$1424 - attribute \src "libresoc.v:43610.13-43610.36" - wire width 8 $1\dmi0_addrsr_reg[7:0] - attribute \src "libresoc.v:45001.3-45009.6" - wire $1\dmi0_addrsr_update_core$next[0:0]$1414 - attribute \src "libresoc.v:43618.7-43618.37" - wire $1\dmi0_addrsr_update_core[0:0] - attribute \src "libresoc.v:45010.3-45018.6" - wire $1\dmi0_addrsr_update_core_prev$next[0:0]$1417 - attribute \src "libresoc.v:43622.7-43622.42" - wire $1\dmi0_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:45443.3-45463.6" - wire width 64 $1\dmi0_datasr__i$next[63:0]$1501 - attribute \src "libresoc.v:43626.14-43626.51" - wire width 64 $1\dmi0_datasr__i[63:0] - attribute \src "libresoc.v:45075.3-45091.6" - wire width 2 $1\dmi0_datasr__oe$next[1:0]$1435 - attribute \src "libresoc.v:43632.13-43632.35" - wire width 2 $1\dmi0_datasr__oe[1:0] - attribute \src "libresoc.v:45092.3-45112.6" - wire width 64 $1\dmi0_datasr_reg$next[63:0]$1439 - attribute \src "libresoc.v:43640.14-43640.52" - wire width 64 $1\dmi0_datasr_reg[63:0] - attribute \src "libresoc.v:45057.3-45065.6" - wire $1\dmi0_datasr_update_core$next[0:0]$1429 - attribute \src "libresoc.v:43648.7-43648.37" - wire $1\dmi0_datasr_update_core[0:0] - attribute \src "libresoc.v:45066.3-45074.6" - wire $1\dmi0_datasr_update_core_prev$next[0:0]$1432 - attribute \src "libresoc.v:43652.7-43652.42" - wire $1\dmi0_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:45363.3-45415.6" - wire width 3 $1\fsm_state$503$next[2:0]$1489 - attribute \src "libresoc.v:45229.3-45281.6" - wire width 3 $1\fsm_state$next[2:0]$1466 - attribute \src "libresoc.v:43668.13-43668.29" - wire width 3 $1\fsm_state[2:0] - attribute \src "libresoc.v:45511.3-45531.6" - wire width 154 $1\io_bd$next[153:0]$1518 - attribute \src "libresoc.v:43868.15-43868.67" - wire width 154 $1\io_bd[153:0] - attribute \src "libresoc.v:45493.3-45510.6" - wire width 154 $1\io_sr$next[153:0]$1514 - attribute \src "libresoc.v:43880.15-43880.67" - wire width 154 $1\io_sr[153:0] - attribute \src "libresoc.v:45196.3-45228.6" - wire width 29 $1\jtag_wb__adr$next[28:0]$1460 - attribute \src "libresoc.v:43889.14-43889.41" - wire width 29 $1\jtag_wb__adr[28:0] - attribute \src "libresoc.v:45282.3-45308.6" - wire width 64 $1\jtag_wb__dat_w$next[63:0]$1473 - attribute \src "libresoc.v:43898.14-43898.51" - wire width 64 $1\jtag_wb__dat_w[63:0] - attribute \src "libresoc.v:44907.3-44923.6" - wire $1\jtag_wb_addrsr__oe$next[0:0]$1390 - attribute \src "libresoc.v:43912.7-43912.32" - wire $1\jtag_wb_addrsr__oe[0:0] - attribute \src "libresoc.v:44924.3-44944.6" - wire width 29 $1\jtag_wb_addrsr_reg$next[28:0]$1394 - attribute \src "libresoc.v:43920.14-43920.47" - wire width 29 $1\jtag_wb_addrsr_reg[28:0] - attribute \src "libresoc.v:44889.3-44897.6" - wire $1\jtag_wb_addrsr_update_core$next[0:0]$1384 - attribute \src "libresoc.v:43928.7-43928.40" - wire $1\jtag_wb_addrsr_update_core[0:0] - attribute \src "libresoc.v:44898.3-44906.6" - wire $1\jtag_wb_addrsr_update_core_prev$next[0:0]$1387 - attribute \src "libresoc.v:43932.7-43932.45" - wire $1\jtag_wb_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:45309.3-45329.6" - wire width 64 $1\jtag_wb_datasr__i$next[63:0]$1478 - attribute \src "libresoc.v:43936.14-43936.54" - wire width 64 $1\jtag_wb_datasr__i[63:0] - attribute \src "libresoc.v:44963.3-44979.6" - wire width 2 $1\jtag_wb_datasr__oe$next[1:0]$1405 - attribute \src "libresoc.v:43942.13-43942.38" - wire width 2 $1\jtag_wb_datasr__oe[1:0] - attribute \src "libresoc.v:44980.3-45000.6" - wire width 64 $1\jtag_wb_datasr_reg$next[63:0]$1409 - attribute \src "libresoc.v:43950.14-43950.55" - wire width 64 $1\jtag_wb_datasr_reg[63:0] - attribute \src "libresoc.v:44945.3-44953.6" - wire $1\jtag_wb_datasr_update_core$next[0:0]$1399 - attribute \src "libresoc.v:43958.7-43958.40" - wire $1\jtag_wb_datasr_update_core[0:0] - attribute \src "libresoc.v:44954.3-44962.6" - wire $1\jtag_wb_datasr_update_core_prev$next[0:0]$1402 - attribute \src "libresoc.v:43962.7-43962.45" - wire $1\jtag_wb_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:44851.3-44867.6" - wire $1\sr0__oe$next[0:0]$1375 - attribute \src "libresoc.v:44392.7-44392.21" - wire $1\sr0__oe[0:0] - attribute \src "libresoc.v:44868.3-44888.6" - wire width 3 $1\sr0_reg$next[2:0]$1379 - attribute \src "libresoc.v:44400.13-44400.27" - wire width 3 $1\sr0_reg[2:0] - attribute \src "libresoc.v:44833.3-44841.6" - wire $1\sr0_update_core$next[0:0]$1369 - attribute \src "libresoc.v:44408.7-44408.29" - wire $1\sr0_update_core[0:0] - attribute \src "libresoc.v:44842.3-44850.6" - wire $1\sr0_update_core_prev$next[0:0]$1372 - attribute \src "libresoc.v:44412.7-44412.34" - wire $1\sr0_update_core_prev[0:0] - attribute \src "libresoc.v:45483.3-45492.6" - wire width 2 $1\sr5__i[1:0] - attribute \src "libresoc.v:45131.3-45147.6" - wire $1\sr5__oe$next[0:0]$1450 - attribute \src "libresoc.v:44422.7-44422.21" - wire $1\sr5__oe[0:0] - attribute \src "libresoc.v:45148.3-45168.6" - wire width 2 $1\sr5_reg$next[1:0]$1454 - attribute \src "libresoc.v:44430.13-44430.27" - wire width 2 $1\sr5_reg[1:0] - attribute \src "libresoc.v:45113.3-45121.6" - wire $1\sr5_update_core$next[0:0]$1444 - attribute \src "libresoc.v:44438.7-44438.29" - wire $1\sr5_update_core[0:0] - attribute \src "libresoc.v:45122.3-45130.6" - wire $1\sr5_update_core_prev$next[0:0]$1447 - attribute \src "libresoc.v:44442.7-44442.34" - wire $1\sr5_update_core_prev[0:0] - attribute \src "libresoc.v:45464.3-45482.6" - wire $1\wb_dcache_en$next[0:0]$1507 - attribute \src "libresoc.v:44446.7-44446.26" - wire $1\wb_dcache_en[0:0] - attribute \src "libresoc.v:45464.3-45482.6" - wire $1\wb_icache_en$next[0:0]$1508 - attribute \src "libresoc.v:44451.7-44451.26" - wire $1\wb_icache_en[0:0] - attribute \src "libresoc.v:45330.3-45362.6" - wire width 4 $2\dmi0__addr_i$next[3:0]$1484 - attribute \src "libresoc.v:45416.3-45442.6" - wire width 64 $2\dmi0__din$next[63:0]$1497 - attribute \src "libresoc.v:45019.3-45035.6" - wire $2\dmi0_addrsr__oe$next[0:0]$1421 - attribute \src "libresoc.v:45036.3-45056.6" - wire width 8 $2\dmi0_addrsr_reg$next[7:0]$1425 - attribute \src "libresoc.v:45443.3-45463.6" - wire width 64 $2\dmi0_datasr__i$next[63:0]$1502 - attribute \src "libresoc.v:45075.3-45091.6" - wire width 2 $2\dmi0_datasr__oe$next[1:0]$1436 - attribute \src "libresoc.v:45092.3-45112.6" - wire width 64 $2\dmi0_datasr_reg$next[63:0]$1440 - attribute \src "libresoc.v:45363.3-45415.6" - wire width 3 $2\fsm_state$503$next[2:0]$1490 - attribute \src "libresoc.v:45229.3-45281.6" - wire width 3 $2\fsm_state$next[2:0]$1467 - attribute \src "libresoc.v:45511.3-45531.6" - wire width 154 $2\io_bd$next[153:0]$1519 - attribute \src "libresoc.v:45493.3-45510.6" - wire width 154 $2\io_sr$next[153:0]$1515 - attribute \src "libresoc.v:45196.3-45228.6" - wire width 29 $2\jtag_wb__adr$next[28:0]$1461 - attribute \src "libresoc.v:45282.3-45308.6" - wire width 64 $2\jtag_wb__dat_w$next[63:0]$1474 - attribute \src "libresoc.v:44907.3-44923.6" - wire $2\jtag_wb_addrsr__oe$next[0:0]$1391 - attribute \src "libresoc.v:44924.3-44944.6" - wire width 29 $2\jtag_wb_addrsr_reg$next[28:0]$1395 - attribute \src "libresoc.v:45309.3-45329.6" - wire width 64 $2\jtag_wb_datasr__i$next[63:0]$1479 - attribute \src "libresoc.v:44963.3-44979.6" - wire width 2 $2\jtag_wb_datasr__oe$next[1:0]$1406 - attribute \src "libresoc.v:44980.3-45000.6" - wire width 64 $2\jtag_wb_datasr_reg$next[63:0]$1410 - attribute \src "libresoc.v:44851.3-44867.6" - wire $2\sr0__oe$next[0:0]$1376 - attribute \src "libresoc.v:44868.3-44888.6" - wire width 3 $2\sr0_reg$next[2:0]$1380 - attribute \src "libresoc.v:45131.3-45147.6" - wire $2\sr5__oe$next[0:0]$1451 - attribute \src "libresoc.v:45148.3-45168.6" - wire width 2 $2\sr5_reg$next[1:0]$1455 - attribute \src "libresoc.v:45464.3-45482.6" - wire $2\wb_dcache_en$next[0:0]$1509 - attribute \src "libresoc.v:45464.3-45482.6" - wire $2\wb_icache_en$next[0:0]$1510 - attribute \src "libresoc.v:45330.3-45362.6" - wire width 4 $3\dmi0__addr_i$next[3:0]$1485 - attribute \src "libresoc.v:45416.3-45442.6" - wire width 64 $3\dmi0__din$next[63:0]$1498 - attribute \src "libresoc.v:45036.3-45056.6" - wire width 8 $3\dmi0_addrsr_reg$next[7:0]$1426 - attribute \src "libresoc.v:45443.3-45463.6" - wire width 64 $3\dmi0_datasr__i$next[63:0]$1503 - attribute \src "libresoc.v:45092.3-45112.6" - wire width 64 $3\dmi0_datasr_reg$next[63:0]$1441 - attribute \src "libresoc.v:45363.3-45415.6" - wire width 3 $3\fsm_state$503$next[2:0]$1491 - attribute \src "libresoc.v:45229.3-45281.6" - wire width 3 $3\fsm_state$next[2:0]$1468 - attribute \src "libresoc.v:45196.3-45228.6" - wire width 29 $3\jtag_wb__adr$next[28:0]$1462 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"libresoc.v:44564.19-44564.134" - wire $ternary$libresoc.v:44564$1182_Y - attribute \src "libresoc.v:44566.19-44566.134" - wire $ternary$libresoc.v:44566$1184_Y - attribute \src "libresoc.v:44567.19-44567.134" - wire $ternary$libresoc.v:44567$1185_Y - attribute \src "libresoc.v:44568.19-44568.134" - wire $ternary$libresoc.v:44568$1186_Y - attribute \src "libresoc.v:44569.19-44569.135" - wire $ternary$libresoc.v:44569$1187_Y - attribute \src "libresoc.v:44570.19-44570.134" - wire $ternary$libresoc.v:44570$1188_Y - attribute \src "libresoc.v:44571.19-44571.135" - wire $ternary$libresoc.v:44571$1189_Y - attribute \src "libresoc.v:44572.19-44572.135" - wire $ternary$libresoc.v:44572$1190_Y - attribute \src "libresoc.v:44573.19-44573.134" - wire $ternary$libresoc.v:44573$1191_Y - attribute \src "libresoc.v:44574.19-44574.135" - wire $ternary$libresoc.v:44574$1192_Y - attribute \src "libresoc.v:44575.19-44575.135" - wire $ternary$libresoc.v:44575$1193_Y - attribute \src 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"libresoc.v:44686.18-44686.130" - wire $ternary$libresoc.v:44686$1305_Y - attribute \src "libresoc.v:44687.18-44687.131" - wire $ternary$libresoc.v:44687$1306_Y - attribute \src "libresoc.v:44689.18-44689.130" - wire $ternary$libresoc.v:44689$1308_Y - attribute \src "libresoc.v:44690.18-44690.131" - wire $ternary$libresoc.v:44690$1309_Y - attribute \src "libresoc.v:44691.18-44691.131" - wire $ternary$libresoc.v:44691$1310_Y - attribute \src "libresoc.v:44692.18-44692.130" - wire $ternary$libresoc.v:44692$1311_Y - attribute \src "libresoc.v:44693.18-44693.131" - wire $ternary$libresoc.v:44693$1312_Y - attribute \src "libresoc.v:44694.18-44694.132" - wire $ternary$libresoc.v:44694$1313_Y - attribute \src "libresoc.v:44695.18-44695.132" - wire $ternary$libresoc.v:44695$1314_Y - attribute \src "libresoc.v:44696.18-44696.133" - wire $ternary$libresoc.v:44696$1315_Y - attribute \src "libresoc.v:44697.18-44697.133" - wire $ternary$libresoc.v:44697$1316_Y - attribute \src "libresoc.v:44698.18-44698.132" - wire $ternary$libresoc.v:44698$1317_Y - attribute \src "libresoc.v:44700.18-44700.133" - wire $ternary$libresoc.v:44700$1319_Y - attribute \src "libresoc.v:44701.18-44701.133" - wire $ternary$libresoc.v:44701$1320_Y - attribute \src "libresoc.v:44702.18-44702.132" - wire $ternary$libresoc.v:44702$1321_Y - attribute \src "libresoc.v:44703.18-44703.133" - wire $ternary$libresoc.v:44703$1322_Y - attribute \src "libresoc.v:44704.18-44704.133" - wire $ternary$libresoc.v:44704$1323_Y - attribute \src "libresoc.v:44705.18-44705.132" - wire $ternary$libresoc.v:44705$1324_Y - attribute \src "libresoc.v:44706.18-44706.133" - wire $ternary$libresoc.v:44706$1325_Y - attribute \src "libresoc.v:44707.18-44707.133" - wire $ternary$libresoc.v:44707$1326_Y - attribute \src "libresoc.v:44708.18-44708.132" - wire $ternary$libresoc.v:44708$1327_Y - attribute \src "libresoc.v:44709.18-44709.133" - wire $ternary$libresoc.v:44709$1328_Y - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + attribute \src "libresoc.v:131158.3-131545.6" + wire width 64 $0\mask[63:0] + attribute \src "libresoc.v:131158.3-131545.6" + wire $10\mask[9:9] + attribute \src "libresoc.v:131158.3-131545.6" + wire $11\mask[10:10] + attribute \src "libresoc.v:131158.3-131545.6" + wire $12\mask[11:11] + attribute \src "libresoc.v:131158.3-131545.6" + wire $13\mask[12:12] + attribute \src "libresoc.v:131158.3-131545.6" + wire $14\mask[13:13] + attribute \src "libresoc.v:131158.3-131545.6" + wire $15\mask[14:14] + attribute \src "libresoc.v:131158.3-131545.6" + wire $16\mask[15:15] + attribute \src "libresoc.v:131158.3-131545.6" + wire $17\mask[16:16] + attribute \src "libresoc.v:131158.3-131545.6" + wire $18\mask[17:17] + attribute \src "libresoc.v:131158.3-131545.6" + wire $19\mask[18:18] + attribute \src "libresoc.v:131158.3-131545.6" + wire $1\mask[0:0] + attribute \src "libresoc.v:131158.3-131545.6" + wire $20\mask[19:19] + attribute \src "libresoc.v:131158.3-131545.6" + wire $21\mask[20:20] + attribute \src "libresoc.v:131158.3-131545.6" + wire $22\mask[21:21] + attribute \src "libresoc.v:131158.3-131545.6" + wire $23\mask[22:22] + attribute \src "libresoc.v:131158.3-131545.6" + wire $24\mask[23:23] + attribute \src "libresoc.v:131158.3-131545.6" + wire $25\mask[24:24] + attribute \src "libresoc.v:131158.3-131545.6" + wire $26\mask[25:25] + attribute \src "libresoc.v:131158.3-131545.6" + wire $27\mask[26:26] + attribute \src "libresoc.v:131158.3-131545.6" + wire $28\mask[27:27] + attribute \src "libresoc.v:131158.3-131545.6" + wire $29\mask[28:28] + attribute \src "libresoc.v:131158.3-131545.6" + wire $2\mask[1:1] + attribute \src "libresoc.v:131158.3-131545.6" + wire $30\mask[29:29] + attribute \src "libresoc.v:131158.3-131545.6" + wire $31\mask[30:30] + attribute \src "libresoc.v:131158.3-131545.6" + wire $32\mask[31:31] + attribute \src "libresoc.v:131158.3-131545.6" + wire $33\mask[32:32] + attribute \src "libresoc.v:131158.3-131545.6" + wire $34\mask[33:33] + attribute \src "libresoc.v:131158.3-131545.6" + wire $35\mask[34:34] + attribute \src "libresoc.v:131158.3-131545.6" + wire $36\mask[35:35] + attribute \src "libresoc.v:131158.3-131545.6" + wire $37\mask[36:36] + attribute \src "libresoc.v:131158.3-131545.6" + wire $38\mask[37:37] + attribute \src "libresoc.v:131158.3-131545.6" + wire $39\mask[38:38] + attribute \src "libresoc.v:131158.3-131545.6" + wire $3\mask[2:2] + attribute \src "libresoc.v:131158.3-131545.6" + wire $40\mask[39:39] + attribute \src "libresoc.v:131158.3-131545.6" + wire $41\mask[40:40] + attribute \src "libresoc.v:131158.3-131545.6" + wire $42\mask[41:41] + attribute \src "libresoc.v:131158.3-131545.6" + wire $43\mask[42:42] + attribute \src "libresoc.v:131158.3-131545.6" + wire $44\mask[43:43] + attribute \src "libresoc.v:131158.3-131545.6" + wire $45\mask[44:44] + attribute \src "libresoc.v:131158.3-131545.6" + wire $46\mask[45:45] + attribute \src "libresoc.v:131158.3-131545.6" + wire $47\mask[46:46] + attribute \src "libresoc.v:131158.3-131545.6" + wire $48\mask[47:47] + attribute \src "libresoc.v:131158.3-131545.6" + wire $49\mask[48:48] + attribute \src "libresoc.v:131158.3-131545.6" + wire $4\mask[3:3] + attribute \src "libresoc.v:131158.3-131545.6" + wire $50\mask[49:49] + attribute \src "libresoc.v:131158.3-131545.6" + wire $51\mask[50:50] + attribute \src "libresoc.v:131158.3-131545.6" + wire $52\mask[51:51] + attribute \src "libresoc.v:131158.3-131545.6" + wire $53\mask[52:52] + attribute \src "libresoc.v:131158.3-131545.6" + wire $54\mask[53:53] + attribute \src "libresoc.v:131158.3-131545.6" + wire $55\mask[54:54] + attribute \src "libresoc.v:131158.3-131545.6" + wire $56\mask[55:55] + attribute \src "libresoc.v:131158.3-131545.6" + wire $57\mask[56:56] + attribute \src "libresoc.v:131158.3-131545.6" + wire $58\mask[57:57] + attribute \src "libresoc.v:131158.3-131545.6" + wire $59\mask[58:58] + attribute \src "libresoc.v:131158.3-131545.6" + wire $5\mask[4:4] + attribute \src "libresoc.v:131158.3-131545.6" + wire $60\mask[59:59] + attribute \src "libresoc.v:131158.3-131545.6" + wire $61\mask[60:60] + attribute \src "libresoc.v:131158.3-131545.6" + wire $62\mask[61:61] + attribute \src "libresoc.v:131158.3-131545.6" + wire $63\mask[62:62] + attribute \src "libresoc.v:131158.3-131545.6" + wire $64\mask[63:63] + attribute \src "libresoc.v:131158.3-131545.6" + wire $6\mask[5:5] + attribute \src "libresoc.v:131158.3-131545.6" + wire $7\mask[6:6] + attribute \src "libresoc.v:131158.3-131545.6" + wire $8\mask[7:7] + attribute \src "libresoc.v:131158.3-131545.6" + wire $9\mask[8:8] + attribute \src "libresoc.v:131094.17-131094.96" + wire $gt$libresoc.v:131094$6156_Y + attribute \src "libresoc.v:131095.18-131095.98" + wire $gt$libresoc.v:131095$6157_Y + attribute \src "libresoc.v:131096.19-131096.99" + wire $gt$libresoc.v:131096$6158_Y + attribute \src "libresoc.v:131097.19-131097.99" + wire $gt$libresoc.v:131097$6159_Y + attribute \src "libresoc.v:131098.19-131098.99" + wire $gt$libresoc.v:131098$6160_Y + attribute \src "libresoc.v:131099.19-131099.99" + wire $gt$libresoc.v:131099$6161_Y + attribute \src "libresoc.v:131100.19-131100.99" + wire $gt$libresoc.v:131100$6162_Y + attribute \src "libresoc.v:131101.19-131101.99" + wire $gt$libresoc.v:131101$6163_Y + attribute \src "libresoc.v:131102.19-131102.99" + wire $gt$libresoc.v:131102$6164_Y + attribute \src "libresoc.v:131103.19-131103.99" + wire $gt$libresoc.v:131103$6165_Y + attribute \src "libresoc.v:131104.19-131104.99" + wire $gt$libresoc.v:131104$6166_Y + attribute \src "libresoc.v:131105.18-131105.97" + wire $gt$libresoc.v:131105$6167_Y + attribute \src "libresoc.v:131106.19-131106.99" + wire $gt$libresoc.v:131106$6168_Y + attribute \src "libresoc.v:131107.19-131107.99" + wire $gt$libresoc.v:131107$6169_Y + attribute \src "libresoc.v:131108.19-131108.99" + wire $gt$libresoc.v:131108$6170_Y + attribute \src "libresoc.v:131109.19-131109.99" + wire $gt$libresoc.v:131109$6171_Y + attribute \src "libresoc.v:131110.19-131110.99" + wire $gt$libresoc.v:131110$6172_Y + attribute \src "libresoc.v:131111.18-131111.97" + wire $gt$libresoc.v:131111$6173_Y + attribute \src "libresoc.v:131112.18-131112.97" + wire $gt$libresoc.v:131112$6174_Y + attribute \src "libresoc.v:131113.18-131113.97" + wire $gt$libresoc.v:131113$6175_Y + attribute \src "libresoc.v:131114.17-131114.96" + wire $gt$libresoc.v:131114$6176_Y + attribute \src "libresoc.v:131115.18-131115.97" + wire $gt$libresoc.v:131115$6177_Y + attribute \src "libresoc.v:131116.18-131116.97" + wire $gt$libresoc.v:131116$6178_Y + attribute \src "libresoc.v:131117.18-131117.97" + wire $gt$libresoc.v:131117$6179_Y + attribute \src "libresoc.v:131118.18-131118.97" + wire $gt$libresoc.v:131118$6180_Y + attribute \src "libresoc.v:131119.18-131119.97" + wire $gt$libresoc.v:131119$6181_Y + attribute \src "libresoc.v:131120.18-131120.97" + wire $gt$libresoc.v:131120$6182_Y + attribute \src "libresoc.v:131121.18-131121.97" + wire $gt$libresoc.v:131121$6183_Y + attribute \src "libresoc.v:131122.18-131122.98" + wire $gt$libresoc.v:131122$6184_Y + attribute \src "libresoc.v:131123.18-131123.98" + wire $gt$libresoc.v:131123$6185_Y + attribute \src "libresoc.v:131124.18-131124.98" + wire $gt$libresoc.v:131124$6186_Y + attribute \src "libresoc.v:131125.17-131125.96" + wire $gt$libresoc.v:131125$6187_Y + attribute \src "libresoc.v:131126.18-131126.98" + wire $gt$libresoc.v:131126$6188_Y + attribute \src "libresoc.v:131127.18-131127.98" + wire $gt$libresoc.v:131127$6189_Y + attribute \src "libresoc.v:131128.18-131128.98" + wire $gt$libresoc.v:131128$6190_Y + attribute \src "libresoc.v:131129.18-131129.98" + wire $gt$libresoc.v:131129$6191_Y + attribute \src "libresoc.v:131130.18-131130.98" + wire $gt$libresoc.v:131130$6192_Y + attribute \src "libresoc.v:131131.18-131131.98" + wire $gt$libresoc.v:131131$6193_Y + attribute \src "libresoc.v:131132.18-131132.98" + wire $gt$libresoc.v:131132$6194_Y + attribute \src "libresoc.v:131133.18-131133.98" + wire $gt$libresoc.v:131133$6195_Y + attribute \src "libresoc.v:131134.18-131134.98" + wire $gt$libresoc.v:131134$6196_Y + attribute \src "libresoc.v:131135.18-131135.98" + wire $gt$libresoc.v:131135$6197_Y + attribute \src "libresoc.v:131136.17-131136.96" + wire $gt$libresoc.v:131136$6198_Y + attribute \src "libresoc.v:131137.18-131137.98" + wire $gt$libresoc.v:131137$6199_Y + attribute \src "libresoc.v:131138.18-131138.98" + wire $gt$libresoc.v:131138$6200_Y + attribute \src "libresoc.v:131139.18-131139.98" + wire $gt$libresoc.v:131139$6201_Y + attribute \src "libresoc.v:131140.18-131140.98" + wire $gt$libresoc.v:131140$6202_Y + attribute \src "libresoc.v:131141.18-131141.98" + wire $gt$libresoc.v:131141$6203_Y + attribute \src "libresoc.v:131142.18-131142.98" + wire $gt$libresoc.v:131142$6204_Y + attribute \src "libresoc.v:131143.18-131143.98" + wire $gt$libresoc.v:131143$6205_Y + attribute \src "libresoc.v:131144.18-131144.98" + wire $gt$libresoc.v:131144$6206_Y + attribute \src "libresoc.v:131145.18-131145.98" + wire $gt$libresoc.v:131145$6207_Y + attribute \src "libresoc.v:131146.18-131146.98" + wire $gt$libresoc.v:131146$6208_Y + attribute \src "libresoc.v:131147.17-131147.96" + wire $gt$libresoc.v:131147$6209_Y + attribute \src "libresoc.v:131148.18-131148.98" + wire $gt$libresoc.v:131148$6210_Y + attribute \src "libresoc.v:131149.18-131149.98" + wire $gt$libresoc.v:131149$6211_Y + attribute \src "libresoc.v:131150.18-131150.98" + wire $gt$libresoc.v:131150$6212_Y + attribute \src "libresoc.v:131151.18-131151.98" + wire $gt$libresoc.v:131151$6213_Y + attribute \src "libresoc.v:131152.18-131152.98" + wire $gt$libresoc.v:131152$6214_Y + attribute \src "libresoc.v:131153.18-131153.98" + wire $gt$libresoc.v:131153$6215_Y + attribute \src "libresoc.v:131154.18-131154.98" + wire $gt$libresoc.v:131154$6216_Y + attribute \src "libresoc.v:131155.18-131155.98" + wire $gt$libresoc.v:131155$6217_Y + attribute \src "libresoc.v:131156.18-131156.98" + wire $gt$libresoc.v:131156$6218_Y + attribute \src "libresoc.v:131157.18-131157.98" + wire $gt$libresoc.v:131157$6219_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$1 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$101 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$103 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$105 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$107 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$109 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$11 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$111 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$113 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$115 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$117 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$119 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$121 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$123 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$125 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$127 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$129 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$13 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$131 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$133 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$135 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$137 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$139 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$141 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$143 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$145 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$147 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$149 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$15 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$151 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$153 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$155 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$157 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - wire \$159 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$161 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$163 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$165 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - wire \$167 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$169 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$17 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$171 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$173 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$175 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$177 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$179 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$181 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$183 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$185 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$187 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$189 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$19 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$191 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$193 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$195 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$197 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$199 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$201 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$203 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$205 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$207 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$209 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$21 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$211 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$213 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$215 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$217 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$219 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$221 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$223 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$225 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$227 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$229 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$23 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$231 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$233 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$235 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$237 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$239 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$241 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$243 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$245 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$247 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$249 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$25 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$251 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$253 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$255 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$257 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$259 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$261 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$263 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$265 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$267 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$269 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$27 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$271 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$273 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$275 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$277 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$279 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$281 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$283 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$285 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$287 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$289 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$29 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$291 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$293 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$295 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$297 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$299 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$3 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$301 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$303 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$305 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$307 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$309 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$31 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$311 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$313 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$315 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$317 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$319 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$321 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$323 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$325 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$327 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$329 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$33 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$331 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$333 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$335 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$337 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$339 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$341 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$343 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$345 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$347 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$349 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$35 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$351 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$353 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$355 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$357 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - wire \$359 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - wire \$361 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - wire \$363 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - wire \$365 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - wire \$367 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - wire \$369 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$37 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$371 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$373 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$375 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$377 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$379 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$381 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$383 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$385 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$387 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$389 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$39 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$391 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$393 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$395 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$397 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$399 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$401 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$403 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$405 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$407 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$409 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$41 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$411 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$413 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$415 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$417 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$419 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$421 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$423 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$425 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$427 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$429 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$43 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$431 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$433 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$435 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$437 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$439 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$441 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$443 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$445 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$447 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$449 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$45 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$451 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$453 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$455 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$457 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$459 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$461 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$463 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$465 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$467 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$469 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$47 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$471 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$473 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$475 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$477 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$479 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$481 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" - wire \$483 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" - wire \$484 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - wire \$487 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - wire \$489 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$49 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - wire \$491 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:792" - wire \$493 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" - wire width 30 \$495 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" - wire width 30 \$496 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" - wire width 30 \$498 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" - wire width 30 \$499 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$5 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire width 8 \$501 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - wire \$504 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - wire \$506 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - wire \$508 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$51 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" - wire \$510 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" - wire width 5 \$512 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" - wire width 5 \$513 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" - wire width 5 \$515 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" - wire width 5 \$516 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$53 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$55 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$57 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$59 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$61 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$63 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$65 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$67 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$69 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$7 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$71 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$73 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$75 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$77 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$79 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$81 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$83 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$85 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$87 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$89 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$9 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$91 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$93 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$95 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$97 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 327 \TAP_bus__tck - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 163 \TAP_bus__tdi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire output 318 \TAP_bus__tdo - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 328 \TAP_bus__tms - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:414" - wire \TAP_tdo - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" - wire \_fsm_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" - wire \_fsm_isdr - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" - wire \_fsm_isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" - wire \_fsm_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" - wire \_fsm_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:225" - wire \_idblock_TAP_id_tdo - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375" - wire \_idblock_id_bypass - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" - wire \_idblock_select_id - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" - wire width 4 \_irblock_ir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" - wire \_irblock_tdo - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 329 \clk - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire input 6 \dmi0__ack_o - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire width 4 output 2 \dmi0__addr_i - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire width 4 \dmi0__addr_i$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire width 64 output 5 \dmi0__din - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire width 64 \dmi0__din$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire width 64 input 7 \dmi0__dout - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire output 3 \dmi0__req_i - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire output 4 \dmi0__we_i - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" - wire width 8 \dmi0_addrsr__i - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" - wire width 8 \dmi0_addrsr__o - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" - wire \dmi0_addrsr__oe - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" - wire \dmi0_addrsr__oe$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" - wire \dmi0_addrsr_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" - wire \dmi0_addrsr_isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 8 \dmi0_addrsr_reg - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 8 \dmi0_addrsr_reg$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" - wire \dmi0_addrsr_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" - wire \dmi0_addrsr_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" - wire \dmi0_addrsr_update_core - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" - wire \dmi0_addrsr_update_core$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" - wire \dmi0_addrsr_update_core_prev - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" - wire \dmi0_addrsr_update_core_prev$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" - wire width 64 \dmi0_datasr__i - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" - wire width 64 \dmi0_datasr__i$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" - wire width 64 \dmi0_datasr__o - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" - wire width 2 \dmi0_datasr__oe - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" - wire width 2 \dmi0_datasr__oe$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" - wire \dmi0_datasr_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" - wire width 2 \dmi0_datasr_isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 64 \dmi0_datasr_reg - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 64 \dmi0_datasr_reg$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" - wire \dmi0_datasr_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" - wire \dmi0_datasr_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" - wire \dmi0_datasr_update_core - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" - wire \dmi0_datasr_update_core$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" - wire \dmi0_datasr_update_core_prev - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" - wire \dmi0_datasr_update_core_prev$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 164 \eint_0__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 9 \eint_0__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 165 \eint_1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 10 \eint_1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 166 \eint_2__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 11 \eint_2__pad__i - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" - wire width 3 \fsm_state - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - wire width 3 \fsm_state$503 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - wire width 3 \fsm_state$503$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" - wire width 3 \fsm_state$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 173 \gpio_e10__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 19 \gpio_e10__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 20 \gpio_e10__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 18 \gpio_e10__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 174 \gpio_e10__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 175 \gpio_e10__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 176 \gpio_e11__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 22 \gpio_e11__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 23 \gpio_e11__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 21 \gpio_e11__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 177 \gpio_e11__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 178 \gpio_e11__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 179 \gpio_e12__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 25 \gpio_e12__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 26 \gpio_e12__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 24 \gpio_e12__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 180 \gpio_e12__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 181 \gpio_e12__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 182 \gpio_e13__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 28 \gpio_e13__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 29 \gpio_e13__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 27 \gpio_e13__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 183 \gpio_e13__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 184 \gpio_e13__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 185 \gpio_e14__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 31 \gpio_e14__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 32 \gpio_e14__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 30 \gpio_e14__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 186 \gpio_e14__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 187 \gpio_e14__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 188 \gpio_e15__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 34 \gpio_e15__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 35 \gpio_e15__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 33 \gpio_e15__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 189 \gpio_e15__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 190 \gpio_e15__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 167 \gpio_e8__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 13 \gpio_e8__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 14 \gpio_e8__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 12 \gpio_e8__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 168 \gpio_e8__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 169 \gpio_e8__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 170 \gpio_e9__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 16 \gpio_e9__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 17 \gpio_e9__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 15 \gpio_e9__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 171 \gpio_e9__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 172 \gpio_e9__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 191 \gpio_s0__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 37 \gpio_s0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 38 \gpio_s0__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 36 \gpio_s0__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 192 \gpio_s0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 193 \gpio_s0__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 194 \gpio_s1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 40 \gpio_s1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 41 \gpio_s1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 39 \gpio_s1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 195 \gpio_s1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 196 \gpio_s1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 197 \gpio_s2__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 43 \gpio_s2__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 44 \gpio_s2__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 42 \gpio_s2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 198 \gpio_s2__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 199 \gpio_s2__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 200 \gpio_s3__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 46 \gpio_s3__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 47 \gpio_s3__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 45 \gpio_s3__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 201 \gpio_s3__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 202 \gpio_s3__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 203 \gpio_s4__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 49 \gpio_s4__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 50 \gpio_s4__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 48 \gpio_s4__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 204 \gpio_s4__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 205 \gpio_s4__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 206 \gpio_s5__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 52 \gpio_s5__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 53 \gpio_s5__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 51 \gpio_s5__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 207 \gpio_s5__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 208 \gpio_s5__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 209 \gpio_s6__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 55 \gpio_s6__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 56 \gpio_s6__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 54 \gpio_s6__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 210 \gpio_s6__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 211 \gpio_s6__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 212 \gpio_s7__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 58 \gpio_s7__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 59 \gpio_s7__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 57 \gpio_s7__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 213 \gpio_s7__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 214 \gpio_s7__pad__oe - attribute \src "libresoc.v:43025.7-43025.15" + attribute \src "libresoc.v:130960.7-130960.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" - wire width 154 \io_bd - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" - wire width 154 \io_bd$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:395" - wire \io_bd2core - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:394" - wire \io_bd2io - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:391" - wire \io_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:392" - wire \io_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" - wire width 154 \io_sr - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" - wire width 154 \io_sr$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:393" - wire \io_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire input 325 \jtag_wb__ack - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 29 output 319 \jtag_wb__adr - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 29 \jtag_wb__adr$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 321 \jtag_wb__cyc - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 input 326 \jtag_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 output 324 \jtag_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 \jtag_wb__dat_w$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 320 \jtag_wb__sel - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 322 \jtag_wb__stb - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 323 \jtag_wb__we - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" - wire width 29 \jtag_wb_addrsr__i - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" - wire width 29 \jtag_wb_addrsr__o - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" - wire \jtag_wb_addrsr__oe - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" - wire \jtag_wb_addrsr__oe$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" - wire \jtag_wb_addrsr_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" - wire \jtag_wb_addrsr_isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 29 \jtag_wb_addrsr_reg - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 29 \jtag_wb_addrsr_reg$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" - wire \jtag_wb_addrsr_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" - wire \jtag_wb_addrsr_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" - wire \jtag_wb_addrsr_update_core - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" - wire \jtag_wb_addrsr_update_core$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" - wire \jtag_wb_addrsr_update_core_prev - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" - wire \jtag_wb_addrsr_update_core_prev$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" - wire width 64 \jtag_wb_datasr__i - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" - wire width 64 \jtag_wb_datasr__i$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" - wire width 64 \jtag_wb_datasr__o - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" - wire width 2 \jtag_wb_datasr__oe - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" - wire width 2 \jtag_wb_datasr__oe$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" - wire \jtag_wb_datasr_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" - wire width 2 \jtag_wb_datasr_isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 64 \jtag_wb_datasr_reg - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 64 \jtag_wb_datasr_reg$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" - wire \jtag_wb_datasr_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" - wire \jtag_wb_datasr_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" - wire \jtag_wb_datasr_update_core - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" - wire \jtag_wb_datasr_update_core$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" - wire \jtag_wb_datasr_update_core_prev - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" - wire \jtag_wb_datasr_update_core_prev$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 60 \mspi0_clk__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 215 \mspi0_clk__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 61 \mspi0_cs_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 216 \mspi0_cs_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 218 \mspi0_miso__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 63 \mspi0_miso__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 62 \mspi0_mosi__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 217 \mspi0_mosi__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 64 \mspi1_clk__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 219 \mspi1_clk__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 65 \mspi1_cs_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 220 \mspi1_cs_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 222 \mspi1_miso__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 67 \mspi1_miso__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 66 \mspi1_mosi__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 221 \mspi1_mosi__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 71 \mtwi_scl__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 226 \mtwi_scl__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 223 \mtwi_sda__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 69 \mtwi_sda__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 70 \mtwi_sda__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 68 \mtwi_sda__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 224 \mtwi_sda__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 225 \mtwi_sda__pad__oe - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" - wire \negjtag_clk - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" - wire \negjtag_rst - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" - wire \posjtag_clk - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" - wire \posjtag_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 72 \pwm_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 227 \pwm_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 73 \pwm_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 228 \pwm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 77 \sd0_clk__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 232 \sd0_clk__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 229 \sd0_cmd__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 75 \sd0_cmd__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 76 \sd0_cmd__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 74 \sd0_cmd__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 230 \sd0_cmd__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 231 \sd0_cmd__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 233 \sd0_data0__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 79 \sd0_data0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 80 \sd0_data0__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 78 \sd0_data0__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 234 \sd0_data0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 235 \sd0_data0__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 236 \sd0_data1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 82 \sd0_data1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 83 \sd0_data1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 81 \sd0_data1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 237 \sd0_data1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 238 \sd0_data1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 239 \sd0_data2__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 85 \sd0_data2__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 86 \sd0_data2__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 84 \sd0_data2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 240 \sd0_data2__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 241 \sd0_data2__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 242 \sd0_data3__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 88 \sd0_data3__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 89 \sd0_data3__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 87 \sd0_data3__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 243 \sd0_data3__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 244 \sd0_data3__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 115 \sdr_a_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 270 \sdr_a_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 133 \sdr_a_10__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 288 \sdr_a_10__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 134 \sdr_a_11__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 289 \sdr_a_11__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 135 \sdr_a_12__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 290 \sdr_a_12__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 116 \sdr_a_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 271 \sdr_a_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 117 \sdr_a_2__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 272 \sdr_a_2__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 118 \sdr_a_3__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 273 \sdr_a_3__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 119 \sdr_a_4__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 274 \sdr_a_4__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 120 \sdr_a_5__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 275 \sdr_a_5__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 121 \sdr_a_6__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 276 \sdr_a_6__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 122 \sdr_a_7__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 277 \sdr_a_7__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 123 \sdr_a_8__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 278 \sdr_a_8__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 124 \sdr_a_9__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 279 \sdr_a_9__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 125 \sdr_ba_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 280 \sdr_ba_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 126 \sdr_ba_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 281 \sdr_ba_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 130 \sdr_cas_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 285 \sdr_cas_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 128 \sdr_cke__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 283 \sdr_cke__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 127 \sdr_clock__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 282 \sdr_clock__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 132 \sdr_cs_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 287 \sdr_cs_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 90 \sdr_dm_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 245 \sdr_dm_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 291 \sdr_dm_1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 137 \sdr_dm_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 138 \sdr_dm_1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 136 \sdr_dm_1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 292 \sdr_dm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 293 \sdr_dm_1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 246 \sdr_dq_0__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 92 \sdr_dq_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 93 \sdr_dq_0__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 91 \sdr_dq_0__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 247 \sdr_dq_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 248 \sdr_dq_0__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 300 \sdr_dq_10__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 146 \sdr_dq_10__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 147 \sdr_dq_10__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 145 \sdr_dq_10__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 301 \sdr_dq_10__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 302 \sdr_dq_10__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 303 \sdr_dq_11__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 149 \sdr_dq_11__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 150 \sdr_dq_11__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 148 \sdr_dq_11__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 304 \sdr_dq_11__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 305 \sdr_dq_11__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 306 \sdr_dq_12__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 152 \sdr_dq_12__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 153 \sdr_dq_12__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 151 \sdr_dq_12__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 307 \sdr_dq_12__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 308 \sdr_dq_12__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 309 \sdr_dq_13__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 155 \sdr_dq_13__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 156 \sdr_dq_13__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 154 \sdr_dq_13__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 310 \sdr_dq_13__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 311 \sdr_dq_13__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 312 \sdr_dq_14__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 158 \sdr_dq_14__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 159 \sdr_dq_14__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 157 \sdr_dq_14__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 313 \sdr_dq_14__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 314 \sdr_dq_14__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 315 \sdr_dq_15__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 161 \sdr_dq_15__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 162 \sdr_dq_15__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 160 \sdr_dq_15__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 316 \sdr_dq_15__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 317 \sdr_dq_15__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 249 \sdr_dq_1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 95 \sdr_dq_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 96 \sdr_dq_1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 94 \sdr_dq_1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 250 \sdr_dq_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 251 \sdr_dq_1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 252 \sdr_dq_2__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 98 \sdr_dq_2__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 99 \sdr_dq_2__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 97 \sdr_dq_2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 253 \sdr_dq_2__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 254 \sdr_dq_2__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 255 \sdr_dq_3__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 101 \sdr_dq_3__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 102 \sdr_dq_3__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 100 \sdr_dq_3__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 256 \sdr_dq_3__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 257 \sdr_dq_3__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 258 \sdr_dq_4__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 104 \sdr_dq_4__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 105 \sdr_dq_4__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 103 \sdr_dq_4__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 259 \sdr_dq_4__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 260 \sdr_dq_4__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 261 \sdr_dq_5__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 107 \sdr_dq_5__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 108 \sdr_dq_5__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 106 \sdr_dq_5__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 262 \sdr_dq_5__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 263 \sdr_dq_5__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 264 \sdr_dq_6__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 110 \sdr_dq_6__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 111 \sdr_dq_6__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 109 \sdr_dq_6__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 265 \sdr_dq_6__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 266 \sdr_dq_6__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 267 \sdr_dq_7__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 113 \sdr_dq_7__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 114 \sdr_dq_7__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 112 \sdr_dq_7__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 268 \sdr_dq_7__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 269 \sdr_dq_7__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 294 \sdr_dq_8__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 140 \sdr_dq_8__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 141 \sdr_dq_8__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 139 \sdr_dq_8__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 295 \sdr_dq_8__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 296 \sdr_dq_8__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 297 \sdr_dq_9__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 143 \sdr_dq_9__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 144 \sdr_dq_9__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 142 \sdr_dq_9__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 298 \sdr_dq_9__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 299 \sdr_dq_9__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 129 \sdr_ras_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 284 \sdr_ras_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 131 \sdr_we_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 286 \sdr_we_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" - wire width 3 \sr0__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" - wire width 3 \sr0__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" - wire \sr0__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" - wire \sr0__oe$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" - wire \sr0_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" - wire \sr0_isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 3 \sr0_reg - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 3 \sr0_reg$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" - wire \sr0_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" - wire \sr0_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" - wire \sr0_update_core - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" - wire \sr0_update_core$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" - wire \sr0_update_core_prev - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" - wire \sr0_update_core_prev$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" - wire width 2 \sr5__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" - wire \sr5__ie - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" - wire width 2 \sr5__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" - wire \sr5__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" - wire \sr5__oe$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" - wire \sr5_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" - wire \sr5_isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 2 \sr5_reg - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 2 \sr5_reg$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" - wire \sr5_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" - wire \sr5_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" - wire \sr5_update_core - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" - wire \sr5_update_core$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" - wire \sr5_update_core_prev - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" - wire \sr5_update_core_prev$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" - wire \wb_dcache_en - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" - wire \wb_dcache_en$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" - wire output 8 \wb_icache_en - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" - wire \wb_icache_en$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" - cell $add $add$libresoc.v:44674$1292 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:12" + wire width 64 output 1 \mask + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:11" + wire width 7 input 2 \shift + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131094$6156 parameter \A_SIGNED 0 - parameter \A_WIDTH 29 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 30 - connect \A \jtag_wb__adr - connect \B 1'1 - connect \Y $add$libresoc.v:44674$1292_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" - cell $add $add$libresoc.v:44676$1294 - parameter \A_SIGNED 0 - parameter \A_WIDTH 29 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 30 - connect \A \jtag_wb__adr - connect \B 1'1 - connect \Y $add$libresoc.v:44676$1294_Y + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'100 + connect \Y $gt$libresoc.v:131094$6156_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" - cell $add $add$libresoc.v:44682$1301 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131095$6157 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \dmi0__addr_i - connect \B 1'1 - connect \Y $add$libresoc.v:44682$1301_Y + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110001 + connect \Y $gt$libresoc.v:131095$6157_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" - cell $add $add$libresoc.v:44683$1302 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131096$6158 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \dmi0__addr_i - connect \B 1'1 - connect \Y $add$libresoc.v:44683$1302_Y + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110010 + connect \Y $gt$libresoc.v:131096$6158_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400" - cell $and $and$libresoc.v:44498$1116 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131097$6159 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 6 parameter \Y_WIDTH 1 - connect \A \$15 - connect \B \_fsm_capture - connect \Y $and$libresoc.v:44498$1116_Y + connect \A \shift + connect \B 6'110011 + connect \Y $gt$libresoc.v:131097$6159_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $and $and$libresoc.v:44565$1183 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131098$6160 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 6 parameter \Y_WIDTH 1 - connect \A \_fsm_isdr - connect \B \$27 - connect \Y $and$libresoc.v:44565$1183_Y + connect \A \shift + connect \B 6'110100 + connect \Y $gt$libresoc.v:131098$6160_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" - cell $and $and$libresoc.v:44576$1194 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131099$6161 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 6 parameter \Y_WIDTH 1 - connect \A \$29 - connect \B \_fsm_shift - connect \Y $and$libresoc.v:44576$1194_Y + connect \A \shift + connect \B 6'110101 + connect \Y $gt$libresoc.v:131099$6161_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $and $and$libresoc.v:44604$1222 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131100$6162 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 6 parameter \Y_WIDTH 1 - connect \A \_fsm_isdr - connect \B \$367 - connect \Y $and$libresoc.v:44604$1222_Y + connect \A \shift + connect \B 6'110110 + connect \Y $gt$libresoc.v:131100$6162_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:44607$1225 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131101$6163 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 6 parameter \Y_WIDTH 1 - connect \A \$373 - connect \B \_fsm_capture - connect \Y $and$libresoc.v:44607$1225_Y + connect \A \shift + connect \B 6'110111 + connect \Y $gt$libresoc.v:131101$6163_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:44610$1228 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131102$6164 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 6 parameter \Y_WIDTH 1 - connect \A \$377 - connect \B \_fsm_shift - connect \Y $and$libresoc.v:44610$1228_Y + connect \A \shift + connect \B 6'111000 + connect \Y $gt$libresoc.v:131102$6164_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:44612$1230 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131103$6165 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 6 parameter \Y_WIDTH 1 - connect \A \$381 - connect \B \_fsm_update - connect \Y $and$libresoc.v:44612$1230_Y + connect \A \shift + connect \B 6'111001 + connect \Y $gt$libresoc.v:131103$6165_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:44614$1232 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131104$6166 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 6 parameter \Y_WIDTH 1 - connect \A \sr0_update_core_prev - connect \B \$385 - connect \Y $and$libresoc.v:44614$1232_Y + connect \A \shift + connect \B 6'111010 + connect \Y $gt$libresoc.v:131104$6166_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:44617$1235 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131105$6167 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \$391 - connect \B \_fsm_capture - connect \Y $and$libresoc.v:44617$1235_Y + connect \A \shift + connect \B 3'101 + connect \Y $gt$libresoc.v:131105$6167_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:44619$1237 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131106$6168 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 6 parameter \Y_WIDTH 1 - connect \A \$395 - connect \B \_fsm_shift - connect \Y $and$libresoc.v:44619$1237_Y + connect \A \shift + connect \B 6'111011 + connect \Y $gt$libresoc.v:131106$6168_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:44623$1241 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131107$6169 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 6 parameter \Y_WIDTH 1 - connect \A \$399 - connect \B \_fsm_update - connect \Y $and$libresoc.v:44623$1241_Y + connect \A \shift + connect \B 6'111100 + connect \Y $gt$libresoc.v:131107$6169_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:44625$1243 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131108$6170 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 6 parameter \Y_WIDTH 1 - connect \A \jtag_wb_addrsr_update_core_prev - connect \B \$403 - connect \Y $and$libresoc.v:44625$1243_Y + connect \A \shift + connect \B 6'111101 + connect \Y $gt$libresoc.v:131108$6170_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:44629$1247 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131109$6171 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 6 parameter \Y_WIDTH 1 - connect \A \$411 - connect \B \_fsm_capture - connect \Y $and$libresoc.v:44629$1247_Y + connect \A \shift + connect \B 6'111110 + connect \Y $gt$libresoc.v:131109$6171_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:44631$1249 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131110$6172 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 6 parameter \Y_WIDTH 1 - connect \A \$415 - connect \B \_fsm_shift - connect \Y $and$libresoc.v:44631$1249_Y + connect \A \shift + connect \B 6'111111 + connect \Y $gt$libresoc.v:131110$6172_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:44634$1252 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131111$6173 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \$419 - connect \B \_fsm_update - connect \Y $and$libresoc.v:44634$1252_Y + connect \A \shift + connect \B 3'110 + connect \Y $gt$libresoc.v:131111$6173_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:44636$1254 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131112$6174 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \jtag_wb_datasr_update_core_prev - connect \B \$423 - connect \Y $and$libresoc.v:44636$1254_Y + connect \A \shift + connect \B 3'111 + connect \Y $gt$libresoc.v:131112$6174_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:44639$1257 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131113$6175 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \$429 - connect \B \_fsm_capture - connect \Y $and$libresoc.v:44639$1257_Y + connect \A \shift + connect \B 4'1000 + connect \Y $gt$libresoc.v:131113$6175_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:44641$1259 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131114$6176 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$433 - connect \B \_fsm_shift - connect \Y $and$libresoc.v:44641$1259_Y + connect \A \shift + connect \B 1'0 + connect \Y $gt$libresoc.v:131114$6176_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $and $and$libresoc.v:44643$1261 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131115$6177 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \_fsm_isdr - connect \B \$41 - connect \Y $and$libresoc.v:44643$1261_Y + connect \A \shift + connect \B 4'1001 + connect \Y $gt$libresoc.v:131115$6177_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:44644$1262 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131116$6178 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \$437 - connect \B \_fsm_update - connect \Y $and$libresoc.v:44644$1262_Y + connect \A \shift + connect \B 4'1010 + connect \Y $gt$libresoc.v:131116$6178_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:44646$1264 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131117$6179 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \dmi0_addrsr_update_core_prev - connect \B \$441 - connect \Y $and$libresoc.v:44646$1264_Y + connect \A \shift + connect \B 4'1011 + connect \Y $gt$libresoc.v:131117$6179_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:44650$1268 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131118$6180 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \$449 - connect \B \_fsm_capture - connect \Y $and$libresoc.v:44650$1268_Y + connect \A \shift + connect \B 4'1100 + connect \Y $gt$libresoc.v:131118$6180_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:44652$1270 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131119$6181 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \$453 - connect \B \_fsm_shift - connect \Y $and$libresoc.v:44652$1270_Y + connect \A \shift + connect \B 4'1101 + connect \Y $gt$libresoc.v:131119$6181_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" - cell $and $and$libresoc.v:44654$1272 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131120$6182 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \$43 - connect \B \_fsm_update - connect \Y $and$libresoc.v:44654$1272_Y + connect \A \shift + connect \B 4'1110 + connect \Y $gt$libresoc.v:131120$6182_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:44655$1273 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131121$6183 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \$457 - connect \B \_fsm_update - connect \Y $and$libresoc.v:44655$1273_Y + connect \A \shift + connect \B 4'1111 + connect \Y $gt$libresoc.v:131121$6183_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:44657$1275 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131122$6184 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \dmi0_datasr_update_core_prev - connect \B \$461 - connect \Y $and$libresoc.v:44657$1275_Y + connect \A \shift + connect \B 5'10000 + connect \Y $gt$libresoc.v:131122$6184_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:44660$1278 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131123$6185 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \$467 - connect \B \_fsm_capture - connect \Y $and$libresoc.v:44660$1278_Y + connect \A \shift + connect \B 5'10001 + connect \Y $gt$libresoc.v:131123$6185_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:44662$1280 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131124$6186 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \$471 - connect \B \_fsm_shift - connect \Y $and$libresoc.v:44662$1280_Y + connect \A \shift + connect \B 5'10010 + connect \Y $gt$libresoc.v:131124$6186_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:44664$1282 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131125$6187 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$475 - connect \B \_fsm_update - connect \Y $and$libresoc.v:44664$1282_Y + connect \A \shift + connect \B 1'1 + connect \Y $gt$libresoc.v:131125$6187_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:44667$1285 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131126$6188 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \sr5_update_core_prev - connect \B \$479 - connect \Y $and$libresoc.v:44667$1285_Y + connect \A \shift + connect \B 5'10011 + connect \Y $gt$libresoc.v:131126$6188_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $and $and$libresoc.v:44699$1318 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131127$6189 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \_fsm_isdr - connect \B \$5 - connect \Y $and$libresoc.v:44699$1318_Y + connect \A \shift + connect \B 5'10100 + connect \Y $gt$libresoc.v:131127$6189_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - cell $eq $eq$libresoc.v:44454$1072 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131128$6190 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 + parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 4'1111 - connect \Y $eq$libresoc.v:44454$1072_Y + connect \A \shift + connect \B 5'10101 + connect \Y $gt$libresoc.v:131128$6190_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:44465$1083 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131129$6191 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 1'0 - connect \Y $eq$libresoc.v:44465$1083_Y + connect \A \shift + connect \B 5'10110 + connect \Y $gt$libresoc.v:131129$6191_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:44476$1094 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131130$6192 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 2'10 - connect \Y $eq$libresoc.v:44476$1094_Y + connect \A \shift + connect \B 5'10111 + connect \Y $gt$libresoc.v:131130$6192_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $eq $eq$libresoc.v:44509$1127 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131131$6193 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 1'1 - connect \Y $eq$libresoc.v:44509$1127_Y + connect \A \shift + connect \B 5'11000 + connect \Y $gt$libresoc.v:131131$6193_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:44510$1128 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131132$6194 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 1'0 - connect \Y $eq$libresoc.v:44510$1128_Y + connect \A \shift + connect \B 5'11001 + connect \Y $gt$libresoc.v:131132$6194_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:44521$1139 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131133$6195 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 2'10 - connect \Y $eq$libresoc.v:44521$1139_Y + connect \A \shift + connect \B 5'11010 + connect \Y $gt$libresoc.v:131133$6195_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - cell $eq $eq$libresoc.v:44543$1161 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131134$6196 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 2'10 - connect \Y $eq$libresoc.v:44543$1161_Y + connect \A \shift + connect \B 5'11011 + connect \Y $gt$libresoc.v:131134$6196_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:44587$1205 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131135$6197 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 1'0 - connect \Y $eq$libresoc.v:44587$1205_Y + connect \A \shift + connect \B 5'11100 + connect \Y $gt$libresoc.v:131135$6197_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:44598$1216 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131136$6198 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \_irblock_ir + connect \A \shift connect \B 2'10 - connect \Y $eq$libresoc.v:44598$1216_Y + connect \Y $gt$libresoc.v:131136$6198_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:44599$1217 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131137$6199 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 1'0 - connect \Y $eq$libresoc.v:44599$1217_Y + connect \A \shift + connect \B 5'11101 + connect \Y $gt$libresoc.v:131137$6199_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:44600$1218 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131138$6200 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 2'10 - connect \Y $eq$libresoc.v:44600$1218_Y + connect \A \shift + connect \B 5'11110 + connect \Y $gt$libresoc.v:131138$6200_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - cell $eq $eq$libresoc.v:44602$1220 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131139$6201 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 2'10 - connect \Y $eq$libresoc.v:44602$1220_Y + connect \A \shift + connect \B 5'11111 + connect \Y $gt$libresoc.v:131139$6201_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:44605$1223 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131140$6202 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \B_WIDTH 6 parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 3'100 - connect \Y $eq$libresoc.v:44605$1223_Y + connect \A \shift + connect \B 6'100000 + connect \Y $gt$libresoc.v:131140$6202_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:44615$1233 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131141$6203 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \B_WIDTH 6 parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 3'101 - connect \Y $eq$libresoc.v:44615$1233_Y + connect \A \shift + connect \B 6'100001 + connect \Y $gt$libresoc.v:131141$6203_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $eq $eq$libresoc.v:44620$1238 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131142$6204 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 + parameter \B_WIDTH 6 parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 4'1111 - connect \Y $eq$libresoc.v:44620$1238_Y + connect \A \shift + connect \B 6'100010 + connect \Y $gt$libresoc.v:131142$6204_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - cell $eq $eq$libresoc.v:44621$1239 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131143$6205 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 6 parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 2'10 - connect \Y $eq$libresoc.v:44621$1239_Y + connect \A \shift + connect \B 6'100011 + connect \Y $gt$libresoc.v:131143$6205_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:44626$1244 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131144$6206 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \B_WIDTH 6 parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 3'110 - connect \Y $eq$libresoc.v:44626$1244_Y + connect \A \shift + connect \B 6'100100 + connect \Y $gt$libresoc.v:131144$6206_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:44627$1245 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131145$6207 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \B_WIDTH 6 parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 3'111 - connect \Y $eq$libresoc.v:44627$1245_Y + connect \A \shift + connect \B 6'100101 + connect \Y $gt$libresoc.v:131145$6207_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:44637$1255 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131146$6208 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 + parameter \B_WIDTH 6 parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 4'1000 - connect \Y $eq$libresoc.v:44637$1255_Y + connect \A \shift + connect \B 6'100110 + connect \Y $gt$libresoc.v:131146$6208_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:44647$1265 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131147$6209 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 4'1001 - connect \Y $eq$libresoc.v:44647$1265_Y + connect \A \shift + connect \B 2'11 + connect \Y $gt$libresoc.v:131147$6209_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:44648$1266 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131148$6210 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 + parameter \B_WIDTH 6 parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 4'1010 - connect \Y $eq$libresoc.v:44648$1266_Y + connect \A \shift + connect \B 6'100111 + connect \Y $gt$libresoc.v:131148$6210_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:44658$1276 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131149$6211 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 + parameter \B_WIDTH 6 parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 4'1011 - connect \Y $eq$libresoc.v:44658$1276_Y + connect \A \shift + connect \B 6'101000 + connect \Y $gt$libresoc.v:131149$6211_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" - cell $eq $eq$libresoc.v:44665$1283 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131150$6212 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 6 parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 1'0 - connect \Y $eq$libresoc.v:44665$1283_Y + connect \A \shift + connect \B 6'101001 + connect \Y $gt$libresoc.v:131150$6212_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" - cell $eq $eq$libresoc.v:44668$1286 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131151$6213 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 6 parameter \Y_WIDTH 1 - connect \A \fsm_state - connect \B 1'0 - connect \Y $eq$libresoc.v:44668$1286_Y + connect \A \shift + connect \B 6'101010 + connect \Y $gt$libresoc.v:131151$6213_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - cell $eq $eq$libresoc.v:44670$1288 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131152$6214 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 6 parameter \Y_WIDTH 1 - connect \A \fsm_state - connect \B 1'1 - connect \Y $eq$libresoc.v:44670$1288_Y + connect \A \shift + connect \B 6'101011 + connect \Y $gt$libresoc.v:131152$6214_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - cell $eq $eq$libresoc.v:44671$1289 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131153$6215 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 6 parameter \Y_WIDTH 1 - connect \A \fsm_state - connect \B 2'10 - connect \Y $eq$libresoc.v:44671$1289_Y + connect \A \shift + connect \B 6'101100 + connect \Y $gt$libresoc.v:131153$6215_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:792" - cell $eq $eq$libresoc.v:44673$1291 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131154$6216 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 6 parameter \Y_WIDTH 1 - connect \A \fsm_state - connect \B 2'10 - connect \Y $eq$libresoc.v:44673$1291_Y + connect \A \shift + connect \B 6'101101 + connect \Y $gt$libresoc.v:131154$6216_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" - cell $eq $eq$libresoc.v:44675$1293 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131155$6217 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 6 parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 1'0 - connect \Y $eq$libresoc.v:44675$1293_Y + connect \A \shift + connect \B 6'101110 + connect \Y $gt$libresoc.v:131155$6217_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - cell $eq $eq$libresoc.v:44678$1297 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131156$6218 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 6 parameter \Y_WIDTH 1 - connect \A \fsm_state$503 - connect \B 1'1 - connect \Y $eq$libresoc.v:44678$1297_Y + connect \A \shift + connect \B 6'101111 + connect \Y $gt$libresoc.v:131156$6218_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - cell $eq $eq$libresoc.v:44679$1298 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:131157$6219 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 6 parameter \Y_WIDTH 1 - connect \A \fsm_state$503 - connect \B 2'10 - connect \Y $eq$libresoc.v:44679$1298_Y + connect \A \shift + connect \B 6'110000 + connect \Y $gt$libresoc.v:131157$6219_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" - cell $eq $eq$libresoc.v:44681$1300 + attribute \src "libresoc.v:130960.7-130960.20" + process $proc$libresoc.v:130960$6221 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:131158.3-131545.6" + process $proc$libresoc.v:131158$6220 + assign { } { } + assign { } { } + assign $0\mask[63:0] [0] $1\mask[0:0] + assign $0\mask[63:0] [1] $2\mask[1:1] + assign $0\mask[63:0] [2] $3\mask[2:2] + assign $0\mask[63:0] [3] $4\mask[3:3] + assign $0\mask[63:0] [4] $5\mask[4:4] + assign $0\mask[63:0] [5] $6\mask[5:5] + assign $0\mask[63:0] [6] $7\mask[6:6] + assign $0\mask[63:0] [7] $8\mask[7:7] + assign $0\mask[63:0] [8] $9\mask[8:8] + assign $0\mask[63:0] [9] $10\mask[9:9] + assign $0\mask[63:0] [10] $11\mask[10:10] + assign $0\mask[63:0] [11] $12\mask[11:11] + assign $0\mask[63:0] [12] $13\mask[12:12] + assign $0\mask[63:0] [13] $14\mask[13:13] + assign $0\mask[63:0] [14] $15\mask[14:14] + assign $0\mask[63:0] [15] $16\mask[15:15] + assign $0\mask[63:0] [16] $17\mask[16:16] + assign $0\mask[63:0] [17] $18\mask[17:17] + assign $0\mask[63:0] [18] $19\mask[18:18] + assign $0\mask[63:0] [19] $20\mask[19:19] + assign $0\mask[63:0] [20] $21\mask[20:20] + assign $0\mask[63:0] [21] $22\mask[21:21] + assign $0\mask[63:0] [22] $23\mask[22:22] + assign $0\mask[63:0] [23] $24\mask[23:23] + assign $0\mask[63:0] [24] $25\mask[24:24] + assign $0\mask[63:0] [25] $26\mask[25:25] + assign $0\mask[63:0] [26] $27\mask[26:26] + assign $0\mask[63:0] [27] $28\mask[27:27] + assign $0\mask[63:0] [28] $29\mask[28:28] + assign $0\mask[63:0] [29] $30\mask[29:29] + assign $0\mask[63:0] [30] $31\mask[30:30] + assign $0\mask[63:0] [31] $32\mask[31:31] + assign $0\mask[63:0] [32] $33\mask[32:32] + assign $0\mask[63:0] [33] $34\mask[33:33] + assign $0\mask[63:0] [34] $35\mask[34:34] + assign $0\mask[63:0] [35] $36\mask[35:35] + assign $0\mask[63:0] [36] $37\mask[36:36] + assign $0\mask[63:0] [37] $38\mask[37:37] + assign $0\mask[63:0] [38] $39\mask[38:38] + assign $0\mask[63:0] [39] $40\mask[39:39] + assign $0\mask[63:0] [40] $41\mask[40:40] + assign $0\mask[63:0] [41] $42\mask[41:41] + assign $0\mask[63:0] [42] $43\mask[42:42] + assign $0\mask[63:0] [43] $44\mask[43:43] + assign $0\mask[63:0] [44] $45\mask[44:44] + assign $0\mask[63:0] [45] $46\mask[45:45] + assign $0\mask[63:0] [46] $47\mask[46:46] + assign $0\mask[63:0] [47] $48\mask[47:47] + assign $0\mask[63:0] [48] $49\mask[48:48] + assign $0\mask[63:0] [49] $50\mask[49:49] + assign $0\mask[63:0] [50] $51\mask[50:50] + assign $0\mask[63:0] [51] $52\mask[51:51] + assign $0\mask[63:0] [52] $53\mask[52:52] + assign $0\mask[63:0] [53] $54\mask[53:53] + assign $0\mask[63:0] [54] $55\mask[54:54] + assign $0\mask[63:0] [55] $56\mask[55:55] + assign $0\mask[63:0] [56] $57\mask[56:56] + assign $0\mask[63:0] [57] $58\mask[57:57] + assign $0\mask[63:0] [58] $59\mask[58:58] + assign $0\mask[63:0] [59] $60\mask[59:59] + assign $0\mask[63:0] [60] $61\mask[60:60] + assign $0\mask[63:0] [61] $62\mask[61:61] + assign $0\mask[63:0] [62] $63\mask[62:62] + assign $0\mask[63:0] [63] $64\mask[63:63] + attribute \src "libresoc.v:131159.5-131159.29" + switch \initial + attribute \src "libresoc.v:131159.9-131159.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\mask[0:0] 1'1 + case + assign $1\mask[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\mask[1:1] 1'1 + case + assign $2\mask[1:1] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\mask[2:2] 1'1 + case + assign $3\mask[2:2] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\mask[3:3] 1'1 + case + assign $4\mask[3:3] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\mask[4:4] 1'1 + case + assign $5\mask[4:4] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$11 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\mask[5:5] 1'1 + case + assign $6\mask[5:5] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\mask[6:6] 1'1 + case + assign $7\mask[6:6] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\mask[7:7] 1'1 + case + assign $8\mask[7:7] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$17 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\mask[8:8] 1'1 + case + assign $9\mask[8:8] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $10\mask[9:9] 1'1 + case + assign $10\mask[9:9] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$21 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $11\mask[10:10] 1'1 + case + assign $11\mask[10:10] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$23 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $12\mask[11:11] 1'1 + case + assign $12\mask[11:11] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $13\mask[12:12] 1'1 + case + assign $13\mask[12:12] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $14\mask[13:13] 1'1 + case + assign $14\mask[13:13] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $15\mask[14:14] 1'1 + case + assign $15\mask[14:14] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$31 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $16\mask[15:15] 1'1 + case + assign $16\mask[15:15] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$33 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $17\mask[16:16] 1'1 + case + assign $17\mask[16:16] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$35 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $18\mask[17:17] 1'1 + case + assign $18\mask[17:17] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$37 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $19\mask[18:18] 1'1 + case + assign $19\mask[18:18] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$39 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $20\mask[19:19] 1'1 + case + assign $20\mask[19:19] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$41 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $21\mask[20:20] 1'1 + case + assign $21\mask[20:20] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$43 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $22\mask[21:21] 1'1 + case + assign $22\mask[21:21] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$45 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $23\mask[22:22] 1'1 + case + assign $23\mask[22:22] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$47 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $24\mask[23:23] 1'1 + case + assign $24\mask[23:23] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$49 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $25\mask[24:24] 1'1 + case + assign $25\mask[24:24] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$51 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $26\mask[25:25] 1'1 + case + assign $26\mask[25:25] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$53 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $27\mask[26:26] 1'1 + case + assign $27\mask[26:26] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$55 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $28\mask[27:27] 1'1 + case + assign $28\mask[27:27] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$57 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $29\mask[28:28] 1'1 + case + assign $29\mask[28:28] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$59 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $30\mask[29:29] 1'1 + case + assign $30\mask[29:29] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$61 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $31\mask[30:30] 1'1 + case + assign $31\mask[30:30] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$63 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $32\mask[31:31] 1'1 + case + assign $32\mask[31:31] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$65 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $33\mask[32:32] 1'1 + case + assign $33\mask[32:32] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$67 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $34\mask[33:33] 1'1 + case + assign $34\mask[33:33] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$69 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $35\mask[34:34] 1'1 + case + assign $35\mask[34:34] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$71 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $36\mask[35:35] 1'1 + case + assign $36\mask[35:35] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$73 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $37\mask[36:36] 1'1 + case + assign $37\mask[36:36] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$75 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $38\mask[37:37] 1'1 + case + assign $38\mask[37:37] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$77 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $39\mask[38:38] 1'1 + case + assign $39\mask[38:38] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$79 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $40\mask[39:39] 1'1 + case + assign $40\mask[39:39] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$81 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $41\mask[40:40] 1'1 + case + assign $41\mask[40:40] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$83 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $42\mask[41:41] 1'1 + case + assign $42\mask[41:41] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$85 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $43\mask[42:42] 1'1 + case + assign $43\mask[42:42] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$87 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $44\mask[43:43] 1'1 + case + assign $44\mask[43:43] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$89 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $45\mask[44:44] 1'1 + case + assign $45\mask[44:44] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$91 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $46\mask[45:45] 1'1 + case + assign $46\mask[45:45] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$93 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $47\mask[46:46] 1'1 + case + assign $47\mask[46:46] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$95 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $48\mask[47:47] 1'1 + case + assign $48\mask[47:47] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$97 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $49\mask[48:48] 1'1 + case + assign $49\mask[48:48] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$99 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $50\mask[49:49] 1'1 + case + assign $50\mask[49:49] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$101 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $51\mask[50:50] 1'1 + case + assign $51\mask[50:50] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$103 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $52\mask[51:51] 1'1 + case + assign $52\mask[51:51] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$105 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $53\mask[52:52] 1'1 + case + assign $53\mask[52:52] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$107 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $54\mask[53:53] 1'1 + case + assign $54\mask[53:53] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$109 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $55\mask[54:54] 1'1 + case + assign $55\mask[54:54] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$111 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $56\mask[55:55] 1'1 + case + assign $56\mask[55:55] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$113 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $57\mask[56:56] 1'1 + case + assign $57\mask[56:56] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$115 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $58\mask[57:57] 1'1 + case + assign $58\mask[57:57] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$117 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $59\mask[58:58] 1'1 + case + assign $59\mask[58:58] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$119 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $60\mask[59:59] 1'1 + case + assign $60\mask[59:59] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$121 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $61\mask[60:60] 1'1 + case + assign $61\mask[60:60] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$123 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $62\mask[61:61] 1'1 + case + assign $62\mask[61:61] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$125 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $63\mask[62:62] 1'1 + case + assign $63\mask[62:62] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$127 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $64\mask[63:63] 1'1 + case + assign $64\mask[63:63] 1'0 + end + sync always + update \mask $0\mask[63:0] + end + connect \$9 $gt$libresoc.v:131094$6156_Y + connect \$99 $gt$libresoc.v:131095$6157_Y + connect \$101 $gt$libresoc.v:131096$6158_Y + connect \$103 $gt$libresoc.v:131097$6159_Y + connect \$105 $gt$libresoc.v:131098$6160_Y + connect \$107 $gt$libresoc.v:131099$6161_Y + connect \$109 $gt$libresoc.v:131100$6162_Y + connect \$111 $gt$libresoc.v:131101$6163_Y + connect \$113 $gt$libresoc.v:131102$6164_Y + connect \$115 $gt$libresoc.v:131103$6165_Y + connect \$117 $gt$libresoc.v:131104$6166_Y + connect \$11 $gt$libresoc.v:131105$6167_Y + connect \$119 $gt$libresoc.v:131106$6168_Y + connect \$121 $gt$libresoc.v:131107$6169_Y + connect \$123 $gt$libresoc.v:131108$6170_Y + connect \$125 $gt$libresoc.v:131109$6171_Y + connect \$127 $gt$libresoc.v:131110$6172_Y + connect \$13 $gt$libresoc.v:131111$6173_Y + connect \$15 $gt$libresoc.v:131112$6174_Y + connect \$17 $gt$libresoc.v:131113$6175_Y + connect \$1 $gt$libresoc.v:131114$6176_Y + connect \$19 $gt$libresoc.v:131115$6177_Y + connect \$21 $gt$libresoc.v:131116$6178_Y + connect \$23 $gt$libresoc.v:131117$6179_Y + connect \$25 $gt$libresoc.v:131118$6180_Y + connect \$27 $gt$libresoc.v:131119$6181_Y + connect \$29 $gt$libresoc.v:131120$6182_Y + connect \$31 $gt$libresoc.v:131121$6183_Y + connect \$33 $gt$libresoc.v:131122$6184_Y + connect \$35 $gt$libresoc.v:131123$6185_Y + connect \$37 $gt$libresoc.v:131124$6186_Y + connect \$3 $gt$libresoc.v:131125$6187_Y + connect \$39 $gt$libresoc.v:131126$6188_Y + connect \$41 $gt$libresoc.v:131127$6189_Y + connect \$43 $gt$libresoc.v:131128$6190_Y + connect \$45 $gt$libresoc.v:131129$6191_Y + connect \$47 $gt$libresoc.v:131130$6192_Y + connect \$49 $gt$libresoc.v:131131$6193_Y + connect \$51 $gt$libresoc.v:131132$6194_Y + connect \$53 $gt$libresoc.v:131133$6195_Y + connect \$55 $gt$libresoc.v:131134$6196_Y + connect \$57 $gt$libresoc.v:131135$6197_Y + connect \$5 $gt$libresoc.v:131136$6198_Y + connect \$59 $gt$libresoc.v:131137$6199_Y + connect \$61 $gt$libresoc.v:131138$6200_Y + connect \$63 $gt$libresoc.v:131139$6201_Y + connect \$65 $gt$libresoc.v:131140$6202_Y + connect \$67 $gt$libresoc.v:131141$6203_Y + connect \$69 $gt$libresoc.v:131142$6204_Y + connect \$71 $gt$libresoc.v:131143$6205_Y + connect \$73 $gt$libresoc.v:131144$6206_Y + connect \$75 $gt$libresoc.v:131145$6207_Y + connect \$77 $gt$libresoc.v:131146$6208_Y + connect \$7 $gt$libresoc.v:131147$6209_Y + connect \$79 $gt$libresoc.v:131148$6210_Y + connect \$81 $gt$libresoc.v:131149$6211_Y + connect \$83 $gt$libresoc.v:131150$6212_Y + connect \$85 $gt$libresoc.v:131151$6213_Y + connect \$87 $gt$libresoc.v:131152$6214_Y + connect \$89 $gt$libresoc.v:131153$6215_Y + connect \$91 $gt$libresoc.v:131154$6216_Y + connect \$93 $gt$libresoc.v:131155$6217_Y + connect \$95 $gt$libresoc.v:131156$6218_Y + connect \$97 $gt$libresoc.v:131157$6219_Y +end +attribute \src "libresoc.v:131550.1-131579.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.lenexp" +attribute \generator "nMigen" +module \lenexp + attribute \src "libresoc.v:131574.17-131574.101" + wire width 64 $extend$libresoc.v:131574$6225_Y + attribute \src "libresoc.v:131574.17-131574.101" + wire width 64 $pos$libresoc.v:131574$6226_Y + attribute \src "libresoc.v:131571.17-131571.111" + wire width 20 $sshl$libresoc.v:131571$6222_Y + attribute \src "libresoc.v:131573.17-131573.113" + wire width 32 $sshl$libresoc.v:131573$6224_Y + attribute \src "libresoc.v:131572.17-131572.107" + wire width 21 $sub$libresoc.v:131572$6223_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" + wire width 21 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" + wire width 20 \$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" + wire width 21 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" + wire width 64 \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" + wire width 32 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131" + wire width 4 input 1 \addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:148" + wire width 17 \binlen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:130" + wire width 4 input 4 \len_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:132" + wire width 64 output 2 \lexp_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134" + wire width 176 output 3 \rexp_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" + cell $pos $extend$libresoc.v:131574$6225 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \$7 + connect \Y $extend$libresoc.v:131574$6225_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" + cell $pos $pos$libresoc.v:131574$6226 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:131574$6225_Y + connect \Y $pos$libresoc.v:131574$6226_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" + cell $sshl $sshl$libresoc.v:131571$6222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \fsm_state$503 - connect \B 2'10 - connect \Y $eq$libresoc.v:44681$1300_Y + parameter \B_WIDTH 4 + parameter \Y_WIDTH 20 + connect \A 5'00001 + connect \B \len_i + connect \Y $sshl$libresoc.v:131571$6222_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - cell $pos $extend$libresoc.v:44677$1295 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" + cell $sshl $sshl$libresoc.v:131573$6224 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \dmi0__addr_i - connect \Y $extend$libresoc.v:44677$1295_Y + parameter \A_WIDTH 17 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 32 + connect \A \binlen + connect \B \addr_i + connect \Y $sshl$libresoc.v:131573$6224_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:44606$1224 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" + cell $sub $sub$libresoc.v:131572$6223 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 20 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sr0_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:44606$1224_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:44608$1226 + parameter \Y_WIDTH 21 + connect \A \$2 + connect \B 1'1 + connect \Y $sub$libresoc.v:131572$6223_Y + end + connect \$2 $sshl$libresoc.v:131571$6222_Y + connect \$4 $sub$libresoc.v:131572$6223_Y + connect \$7 $sshl$libresoc.v:131573$6224_Y + connect \$6 $pos$libresoc.v:131574$6226_Y + connect \$1 \$4 + connect \rexp_o { \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21:20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20:19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19:18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18:17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17:16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16:15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15:14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14:13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13:12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12:11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11:10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10:9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9:8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8:7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7:6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6:5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5:4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4:3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3:2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2:1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1:0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] } + connect \lexp_o \$6 + connect \binlen \$4 [16:0] +end +attribute \src "libresoc.v:131583.1-131641.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.lod_l" +attribute \generator "nMigen" +module \lod_l + attribute \src "libresoc.v:131584.7-131584.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:131629.3-131637.6" + wire $0\q_int$next[0:0]$6237 + attribute \src "libresoc.v:131627.3-131628.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:131629.3-131637.6" + wire $1\q_int$next[0:0]$6238 + attribute \src "libresoc.v:131606.7-131606.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:131619.17-131619.96" + wire $and$libresoc.v:131619$6227_Y + attribute \src "libresoc.v:131624.17-131624.96" + wire $and$libresoc.v:131624$6232_Y + attribute \src "libresoc.v:131621.18-131621.93" + wire $not$libresoc.v:131621$6229_Y + attribute \src "libresoc.v:131623.17-131623.92" + wire $not$libresoc.v:131623$6231_Y + attribute \src "libresoc.v:131626.17-131626.92" + wire $not$libresoc.v:131626$6234_Y + attribute \src "libresoc.v:131620.18-131620.98" + wire $or$libresoc.v:131620$6228_Y + attribute \src "libresoc.v:131622.18-131622.99" + wire $or$libresoc.v:131622$6230_Y + attribute \src "libresoc.v:131625.17-131625.97" + wire $or$libresoc.v:131625$6233_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:131584.7-131584.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \q_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire output 4 \qn_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:131619$6227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \sr0_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:44608$1226_Y + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:131619$6227_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:44611$1229 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:131624$6232 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \sr0_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:44611$1229_Y + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:131624$6232_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:44616$1234 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:131621$6229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \jtag_wb_addrsr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:44616$1234_Y + connect \A \q_lod + connect \Y $not$libresoc.v:131621$6229_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:44618$1236 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:131623$6231 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \jtag_wb_addrsr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:44618$1236_Y + connect \A \r_lod + connect \Y $not$libresoc.v:131623$6231_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:44622$1240 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:131626$6234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \jtag_wb_addrsr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:44622$1240_Y + connect \A \r_lod + connect \Y $not$libresoc.v:131626$6234_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:44628$1246 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:131620$6228 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \jtag_wb_datasr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:44628$1246_Y + connect \A \$9 + connect \B \s_lod + connect \Y $or$libresoc.v:131620$6228_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:44630$1248 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:131622$6230 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \jtag_wb_datasr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:44630$1248_Y + connect \A \q_lod + connect \B \q_int + connect \Y $or$libresoc.v:131622$6230_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:44633$1251 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:131625$6233 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \jtag_wb_datasr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:44633$1251_Y + connect \A \$3 + connect \B \s_lod + connect \Y $or$libresoc.v:131625$6233_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:44638$1256 + attribute \src "libresoc.v:131584.7-131584.20" + process $proc$libresoc.v:131584$6239 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:131606.7-131606.19" + process $proc$libresoc.v:131606$6240 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:131627.3-131628.27" + process $proc$libresoc.v:131627$6235 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:131629.3-131637.6" + process $proc$libresoc.v:131629$6236 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$6237 $1\q_int$next[0:0]$6238 + attribute \src "libresoc.v:131630.5-131630.29" + switch \initial + attribute \src "libresoc.v:131630.9-131630.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$6238 1'0 + case + assign $1\q_int$next[0:0]$6238 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$6237 + end + connect \$9 $and$libresoc.v:131619$6227_Y + connect \$11 $or$libresoc.v:131620$6228_Y + connect \$13 $not$libresoc.v:131621$6229_Y + connect \$15 $or$libresoc.v:131622$6230_Y + connect \$1 $not$libresoc.v:131623$6231_Y + connect \$3 $and$libresoc.v:131624$6232_Y + connect \$5 $or$libresoc.v:131625$6233_Y + connect \$7 $not$libresoc.v:131626$6234_Y + connect \qlq_lod \$15 + connect \qn_lod \$13 + connect \q_lod \$11 +end +attribute \src "libresoc.v:131645.1-132759.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0" +attribute \generator "nMigen" +module \logical0 + attribute \src "libresoc.v:132384.3-132385.24" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:132382.3-132383.44" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:132689.3-132697.6" + wire $0\alu_l_r_alu$next[0:0]$6441 + attribute \src "libresoc.v:132306.3-132307.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:132567.3-132605.6" + wire width 4 $0\alu_logical0_logical_op__data_len$next[3:0]$6370 + attribute \src "libresoc.v:132356.3-132357.83" + wire width 4 $0\alu_logical0_logical_op__data_len[3:0] + attribute \src "libresoc.v:132567.3-132605.6" + wire width 12 $0\alu_logical0_logical_op__fn_unit$next[11:0]$6371 + attribute \src "libresoc.v:132326.3-132327.81" + wire width 12 $0\alu_logical0_logical_op__fn_unit[11:0] + attribute \src "libresoc.v:132567.3-132605.6" + wire width 64 $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6372 + attribute \src "libresoc.v:132328.3-132329.95" + wire width 64 $0\alu_logical0_logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:132567.3-132605.6" + wire $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6373 + attribute \src "libresoc.v:132330.3-132331.91" + wire $0\alu_logical0_logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:132567.3-132605.6" + wire width 2 $0\alu_logical0_logical_op__input_carry$next[1:0]$6374 + attribute \src "libresoc.v:132344.3-132345.89" + wire width 2 $0\alu_logical0_logical_op__input_carry[1:0] + attribute \src "libresoc.v:132567.3-132605.6" + wire width 32 $0\alu_logical0_logical_op__insn$next[31:0]$6375 + attribute \src "libresoc.v:132358.3-132359.75" + wire width 32 $0\alu_logical0_logical_op__insn[31:0] + attribute \src "libresoc.v:132567.3-132605.6" + wire width 7 $0\alu_logical0_logical_op__insn_type$next[6:0]$6376 + attribute \src "libresoc.v:132324.3-132325.85" + wire width 7 $0\alu_logical0_logical_op__insn_type[6:0] + attribute \src "libresoc.v:132567.3-132605.6" + wire $0\alu_logical0_logical_op__invert_in$next[0:0]$6377 + attribute \src "libresoc.v:132340.3-132341.85" + wire $0\alu_logical0_logical_op__invert_in[0:0] + attribute \src "libresoc.v:132567.3-132605.6" + wire $0\alu_logical0_logical_op__invert_out$next[0:0]$6378 + attribute \src "libresoc.v:132346.3-132347.87" + wire $0\alu_logical0_logical_op__invert_out[0:0] + attribute \src "libresoc.v:132567.3-132605.6" + wire $0\alu_logical0_logical_op__is_32bit$next[0:0]$6379 + attribute \src "libresoc.v:132352.3-132353.83" + wire $0\alu_logical0_logical_op__is_32bit[0:0] + attribute \src "libresoc.v:132567.3-132605.6" + wire $0\alu_logical0_logical_op__is_signed$next[0:0]$6380 + attribute \src "libresoc.v:132354.3-132355.85" + wire $0\alu_logical0_logical_op__is_signed[0:0] + attribute \src "libresoc.v:132567.3-132605.6" + wire $0\alu_logical0_logical_op__oe__oe$next[0:0]$6381 + attribute \src "libresoc.v:132336.3-132337.79" + wire $0\alu_logical0_logical_op__oe__oe[0:0] + attribute \src "libresoc.v:132567.3-132605.6" + wire $0\alu_logical0_logical_op__oe__ok$next[0:0]$6382 + attribute \src "libresoc.v:132338.3-132339.79" + wire $0\alu_logical0_logical_op__oe__ok[0:0] + attribute \src "libresoc.v:132567.3-132605.6" + wire $0\alu_logical0_logical_op__output_carry$next[0:0]$6383 + attribute \src "libresoc.v:132350.3-132351.91" + wire $0\alu_logical0_logical_op__output_carry[0:0] + attribute \src "libresoc.v:132567.3-132605.6" + wire $0\alu_logical0_logical_op__rc__ok$next[0:0]$6384 + attribute \src "libresoc.v:132334.3-132335.79" + wire $0\alu_logical0_logical_op__rc__ok[0:0] + attribute \src "libresoc.v:132567.3-132605.6" + wire $0\alu_logical0_logical_op__rc__rc$next[0:0]$6385 + attribute \src "libresoc.v:132332.3-132333.79" + wire $0\alu_logical0_logical_op__rc__rc[0:0] + attribute \src "libresoc.v:132567.3-132605.6" + wire $0\alu_logical0_logical_op__write_cr0$next[0:0]$6386 + attribute \src "libresoc.v:132348.3-132349.85" + wire $0\alu_logical0_logical_op__write_cr0[0:0] + attribute \src "libresoc.v:132567.3-132605.6" + wire $0\alu_logical0_logical_op__zero_a$next[0:0]$6387 + attribute \src "libresoc.v:132342.3-132343.79" + wire $0\alu_logical0_logical_op__zero_a[0:0] + attribute \src "libresoc.v:132680.3-132688.6" + wire $0\alui_l_r_alui$next[0:0]$6438 + attribute \src "libresoc.v:132308.3-132309.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:132606.3-132627.6" + wire width 64 $0\data_r0__o$next[63:0]$6413 + attribute \src "libresoc.v:132320.3-132321.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "libresoc.v:132606.3-132627.6" + wire $0\data_r0__o_ok$next[0:0]$6414 + attribute \src "libresoc.v:132322.3-132323.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "libresoc.v:132628.3-132649.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$6421 + attribute \src "libresoc.v:132316.3-132317.43" + wire width 4 $0\data_r1__cr_a[3:0] + attribute \src "libresoc.v:132628.3-132649.6" + wire $0\data_r1__cr_a_ok$next[0:0]$6422 + attribute \src "libresoc.v:132318.3-132319.49" + wire $0\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:132698.3-132707.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:132708.3-132717.6" + wire width 4 $0\dest2_o[3:0] + attribute \src "libresoc.v:131646.7-131646.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:132522.3-132530.6" + wire $0\opc_l_r_opc$next[0:0]$6355 + attribute \src "libresoc.v:132368.3-132369.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:132513.3-132521.6" + wire $0\opc_l_s_opc$next[0:0]$6352 + attribute \src "libresoc.v:132370.3-132371.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:132718.3-132726.6" + wire width 2 $0\prev_wr_go$next[1:0]$6446 + attribute \src "libresoc.v:132380.3-132381.37" + wire width 2 $0\prev_wr_go[1:0] + attribute \src "libresoc.v:132467.3-132476.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:132558.3-132566.6" + wire width 2 $0\req_l_r_req$next[1:0]$6367 + attribute \src "libresoc.v:132360.3-132361.39" + wire width 2 $0\req_l_r_req[1:0] + attribute \src "libresoc.v:132549.3-132557.6" + wire width 2 $0\req_l_s_req$next[1:0]$6364 + attribute \src "libresoc.v:132362.3-132363.39" + wire width 2 $0\req_l_s_req[1:0] + attribute \src "libresoc.v:132486.3-132494.6" + wire $0\rok_l_r_rdok$next[0:0]$6343 + attribute \src "libresoc.v:132376.3-132377.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:132477.3-132485.6" + wire $0\rok_l_s_rdok$next[0:0]$6340 + attribute \src "libresoc.v:132378.3-132379.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:132504.3-132512.6" + wire $0\rst_l_r_rst$next[0:0]$6349 + attribute \src "libresoc.v:132372.3-132373.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:132495.3-132503.6" + wire $0\rst_l_s_rst$next[0:0]$6346 + attribute \src "libresoc.v:132374.3-132375.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:132540.3-132548.6" + wire width 3 $0\src_l_r_src$next[2:0]$6361 + attribute \src "libresoc.v:132364.3-132365.39" + wire width 3 $0\src_l_r_src[2:0] + attribute \src "libresoc.v:132531.3-132539.6" + wire width 3 $0\src_l_s_src$next[2:0]$6358 + attribute \src "libresoc.v:132366.3-132367.39" + wire width 3 $0\src_l_s_src[2:0] + attribute \src "libresoc.v:132650.3-132659.6" + wire width 64 $0\src_r0$next[63:0]$6429 + attribute \src "libresoc.v:132314.3-132315.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:132660.3-132669.6" + wire width 64 $0\src_r1$next[63:0]$6432 + attribute \src "libresoc.v:132312.3-132313.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:132670.3-132679.6" + wire $0\src_r2$next[0:0]$6435 + attribute \src "libresoc.v:132310.3-132311.29" + wire $0\src_r2[0:0] + attribute \src "libresoc.v:131764.7-131764.24" + wire $1\all_rd_dly[0:0] + attribute \src "libresoc.v:131774.7-131774.26" + wire $1\alu_done_dly[0:0] + attribute \src "libresoc.v:132689.3-132697.6" + wire $1\alu_l_r_alu$next[0:0]$6442 + attribute \src "libresoc.v:131782.7-131782.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "libresoc.v:132567.3-132605.6" + wire width 4 $1\alu_logical0_logical_op__data_len$next[3:0]$6388 + attribute \src "libresoc.v:131790.13-131790.53" + wire width 4 $1\alu_logical0_logical_op__data_len[3:0] + attribute \src "libresoc.v:132567.3-132605.6" + wire width 12 $1\alu_logical0_logical_op__fn_unit$next[11:0]$6389 + attribute \src "libresoc.v:131807.14-131807.56" + wire width 12 $1\alu_logical0_logical_op__fn_unit[11:0] + attribute \src "libresoc.v:132567.3-132605.6" + wire width 64 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6390 + attribute \src "libresoc.v:131811.14-131811.76" + wire width 64 $1\alu_logical0_logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:132567.3-132605.6" + wire $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6391 + attribute \src "libresoc.v:131815.7-131815.51" + wire $1\alu_logical0_logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:132567.3-132605.6" + wire width 2 $1\alu_logical0_logical_op__input_carry$next[1:0]$6392 + attribute \src "libresoc.v:131823.13-131823.56" + wire width 2 $1\alu_logical0_logical_op__input_carry[1:0] + attribute \src "libresoc.v:132567.3-132605.6" + wire width 32 $1\alu_logical0_logical_op__insn$next[31:0]$6393 + attribute \src "libresoc.v:131827.14-131827.51" + wire width 32 $1\alu_logical0_logical_op__insn[31:0] + attribute \src "libresoc.v:132567.3-132605.6" + wire width 7 $1\alu_logical0_logical_op__insn_type$next[6:0]$6394 + attribute \src "libresoc.v:131905.13-131905.55" + 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 18 \oper_i_alu_logical0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src 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\oper_i_alu_logical0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \oper_i_alu_logical0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \oper_i_alu_logical0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \oper_i_alu_logical0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \oper_i_alu_logical0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 2 \prev_wr_go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 2 \prev_wr_go$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" + wire \req_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 2 \req_l_q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 2 \req_l_r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 2 \req_l_r_req$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 2 \req_l_s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 2 \req_l_s_req$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + wire \reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" + wire width 3 \reset_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" + wire width 2 \reset_w + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \rok_l_q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rok_l_r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rok_l_r_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rok_l_s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rok_l_s_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rst_l_r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rst_l_r_rst$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rst_l_s_rst$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + wire \rst_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 25 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 26 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 27 \src3_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 \src_l_q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \src_l_r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \src_l_r_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \src_l_s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \src_l_s_src$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" + wire width 64 \src_or_imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" + wire width 64 \src_or_imm$80 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire \src_r2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire \src_r2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" + wire \src_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" + wire \src_sel$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + wire \wr_any + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $and $and$libresoc.v:132249$6241 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dmi0_addrsr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:44638$1256_Y + connect \A \$1 + connect \B \$3 + connect \Y $and$libresoc.v:132249$6241_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:44640$1258 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:132250$6242 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi0_addrsr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:44640$1258_Y + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$93 + connect \B { 1'1 \$97 \$95 } + connect \Y $and$libresoc.v:132250$6242_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:44642$1260 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:132252$6244 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$99 + connect \B \$101 + connect \Y $and$libresoc.v:132252$6244_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:132253$6245 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dmi0_addrsr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:44642$1260_Y + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:132253$6245_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:44649$1267 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:132254$6246 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dmi0_datasr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:44649$1267_Y + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:132254$6246_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:44651$1269 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $and$libresoc.v:132255$6247 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi0_datasr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:44651$1269_Y + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \req_l_q_req + connect \B { \$105 \$107 } + connect \Y $and$libresoc.v:132255$6247_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:44653$1271 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $and$libresoc.v:132256$6248 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi0_datasr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:44653$1271_Y + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \$109 + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:132256$6248_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:44659$1277 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:132257$6249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \sr5_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:44659$1277_Y + connect \A \cu_wr__go_i [0] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:132257$6249_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:44661$1279 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:132258$6250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \sr5_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:44661$1279_Y + connect \A \cu_wr__go_i [1] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:132258$6250_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:44663$1281 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:132260$6252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \sr5_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:44663$1281_Y + connect \A \all_rd + connect \B \$11 + connect \Y $and$libresoc.v:132260$6252_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:44613$1231 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:132262$6254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \sr0_update_core - connect \Y $not$libresoc.v:44613$1231_Y + connect \A \alu_done + connect \B \$15 + connect \Y $and$libresoc.v:132262$6254_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:44624$1242 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + cell $and $and$libresoc.v:132263$6255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \jtag_wb_addrsr_update_core - connect \Y $not$libresoc.v:44624$1242_Y + connect \A \cu_busy_o + connect \B \rok_l_q_rdok + connect \Y $and$libresoc.v:132263$6255_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:44635$1253 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + cell $and $and$libresoc.v:132264$6256 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \jtag_wb_datasr_update_core - connect \Y $not$libresoc.v:44635$1253_Y + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \cu_wr__go_i + connect \B { \cu_busy_o \cu_busy_o } + connect \Y $and$libresoc.v:132264$6256_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:44645$1263 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $and$libresoc.v:132266$6258 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi0_addrsr_update_core - connect \Y $not$libresoc.v:44645$1263_Y + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \cu_wr__rel_o + connect \B \$23 + connect \Y $and$libresoc.v:132266$6258_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:44656$1274 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $and$libresoc.v:132269$6261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dmi0_datasr_update_core - connect \Y $not$libresoc.v:44656$1274_Y + connect \A \cu_busy_o + connect \B \$21 + connect \Y $and$libresoc.v:132269$6261_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:44666$1284 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $and $and$libresoc.v:132274$6266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \sr5_update_core - connect \Y $not$libresoc.v:44666$1284_Y + connect \A \wr_any + connect \B \$37 + connect \Y $and$libresoc.v:132274$6266_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" - cell $not $not$libresoc.v:44669$1287 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$libresoc.v:132275$6267 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$484 - connect \Y $not$libresoc.v:44669$1287_Y + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \req_l_q_req + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:132275$6267_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:44487$1105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$libresoc.v:132277$6269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$11 - connect \B \$13 - connect \Y $or$libresoc.v:44487$1105_Y + connect \A \$39 + connect \B \$43 + connect \Y $and$libresoc.v:132277$6269_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:44532$1150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:132280$6272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$19 - connect \B \$21 - connect \Y $or$libresoc.v:44532$1150_Y + connect \A \$47 + connect \B \alu_logical0_n_ready_i + connect \Y $and$libresoc.v:132280$6272_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $or $or$libresoc.v:44554$1172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:132281$6273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$23 - connect \B \$25 - connect \Y $or$libresoc.v:44554$1172_Y + connect \A \$49 + connect \B \alu_logical0_n_valid_o + connect \Y $and$libresoc.v:132281$6273_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:44601$1219 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:132282$6274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$359 - connect \B \$361 - connect \Y $or$libresoc.v:44601$1219_Y + connect \A \$51 + connect \B \cu_busy_o + connect \Y $and$libresoc.v:132282$6274_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $or $or$libresoc.v:44603$1221 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + cell $and $and$libresoc.v:132287$6279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$363 - connect \B \$365 - connect \Y $or$libresoc.v:44603$1221_Y + connect \A \alu_logical0_n_valid_o + connect \B \cu_busy_o + connect \Y $and$libresoc.v:132287$6279_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:44609$1227 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + cell $and $and$libresoc.v:132288$6280 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$33 - connect \B \$35 - connect \Y $or$libresoc.v:44609$1227_Y + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \alu_pulsem + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:132288$6280_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $or $or$libresoc.v:44632$1250 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:132291$6283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$37 - connect \B \$39 - connect \Y $or$libresoc.v:44632$1250_Y + connect \A \o_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:132291$6283_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - cell $or $or$libresoc.v:44672$1290 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:132292$6284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$487 - connect \B \$489 - connect \Y $or$libresoc.v:44672$1290_Y + connect \A \cr_a_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:132292$6284_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - cell $or $or$libresoc.v:44680$1299 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + cell $and $and$libresoc.v:132301$6293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$504 - connect \B \$506 - connect \Y $or$libresoc.v:44680$1299_Y + connect \A \alu_logical0_p_ready_o + connect \B \alui_l_q_alui + connect \Y $and$libresoc.v:132301$6293_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $or $or$libresoc.v:44688$1307 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + cell $and $and$libresoc.v:132302$6294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \$3 - connect \Y $or$libresoc.v:44688$1307_Y + connect \A \alu_logical0_n_valid_o + connect \B \alu_l_q_alu + connect \Y $and$libresoc.v:132302$6294_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - cell $pos $pos$libresoc.v:44677$1296 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:132303$6295 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:44677$1295_Y - connect \Y $pos$libresoc.v:44677$1296_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44455$1073 - parameter \WIDTH 1 - connect \A \gpio_e15__pad__i - connect \B \io_bd [24] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44455$1073_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44456$1074 - parameter \WIDTH 1 - connect \A \gpio_e15__core__o - connect \B \io_bd [25] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44456$1074_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44457$1075 - parameter \WIDTH 1 - connect \A \gpio_e15__core__oe - connect \B \io_bd [26] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44457$1075_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44458$1076 - parameter \WIDTH 1 - connect \A \gpio_s0__pad__i - connect \B \io_bd [27] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44458$1076_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44459$1077 - parameter \WIDTH 1 - connect \A \gpio_s0__core__o - connect \B \io_bd [28] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44459$1077_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44460$1078 - parameter \WIDTH 1 - connect \A \gpio_s0__core__oe - connect \B \io_bd [29] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44460$1078_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44461$1079 - parameter \WIDTH 1 - connect \A \gpio_s1__pad__i - connect \B \io_bd [30] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44461$1079_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44462$1080 - parameter \WIDTH 1 - connect \A \gpio_s1__core__o - connect \B \io_bd [31] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44462$1080_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44463$1081 - parameter \WIDTH 1 - connect \A \gpio_s1__core__oe - connect \B \io_bd [32] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44463$1081_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44464$1082 - parameter \WIDTH 1 - connect \A \gpio_s2__pad__i - connect \B \io_bd [33] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44464$1082_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44466$1084 - parameter \WIDTH 1 - connect \A \gpio_s2__core__o - connect \B \io_bd [34] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44466$1084_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44467$1085 - parameter \WIDTH 1 - connect \A \gpio_s2__core__oe - connect \B \io_bd [35] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44467$1085_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44468$1086 - parameter \WIDTH 1 - connect \A \gpio_s3__pad__i - connect \B \io_bd [36] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44468$1086_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44469$1087 - parameter \WIDTH 1 - connect \A \gpio_s3__core__o - connect \B \io_bd [37] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44469$1087_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44470$1088 - parameter \WIDTH 1 - connect \A \gpio_s3__core__oe - connect \B \io_bd [38] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44470$1088_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44471$1089 - parameter \WIDTH 1 - connect \A \gpio_s4__pad__i - connect \B \io_bd [39] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44471$1089_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44472$1090 - parameter \WIDTH 1 - connect \A \gpio_s4__core__o - connect \B \io_bd [40] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44472$1090_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \src_l_q_src + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$libresoc.v:132303$6295_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44473$1091 - parameter \WIDTH 1 - connect \A \gpio_s4__core__oe - connect \B \io_bd [41] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44473$1091_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $eq$libresoc.v:132276$6268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$41 + connect \B 1'0 + connect \Y $eq$libresoc.v:132276$6268_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44474$1092 - parameter \WIDTH 1 - connect \A \gpio_s5__pad__i - connect \B \io_bd [42] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44474$1092_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $eq$libresoc.v:132278$6270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $eq$libresoc.v:132278$6270_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44475$1093 - parameter \WIDTH 1 - connect \A \gpio_s5__core__o - connect \B \io_bd [43] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44475$1093_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$libresoc.v:132251$6243 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rdmaskn_i + connect \Y $not$libresoc.v:132251$6243_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44477$1095 - parameter \WIDTH 1 - connect \A \gpio_s5__core__oe - connect \B \io_bd [44] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44477$1095_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:132259$6251 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $not$libresoc.v:132259$6251_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44478$1096 - parameter \WIDTH 1 - connect \A \gpio_s6__pad__i - connect \B \io_bd [45] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44478$1096_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:132261$6253 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $not$libresoc.v:132261$6253_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44479$1097 - parameter \WIDTH 1 - connect \A \gpio_s6__core__o - connect \B \io_bd [46] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44479$1097_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:132265$6257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \cu_wrmask_o + connect \Y $not$libresoc.v:132265$6257_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44480$1098 - parameter \WIDTH 1 - connect \A \gpio_s6__core__oe - connect \B \io_bd [47] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44480$1098_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:132268$6260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$22 + connect \Y $not$libresoc.v:132268$6260_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44481$1099 - parameter \WIDTH 1 - connect \A \gpio_s7__pad__i - connect \B \io_bd [48] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44481$1099_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$libresoc.v:132273$6265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_logical0_n_ready_i + connect \Y $not$libresoc.v:132273$6265_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44482$1100 - parameter \WIDTH 1 - connect \A \gpio_s7__core__o - connect \B \io_bd [49] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44482$1100_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$libresoc.v:132279$6271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__rel_o + connect \Y $not$libresoc.v:132279$6271_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44483$1101 - parameter \WIDTH 1 - connect \A \gpio_s7__core__oe - connect \B \io_bd [50] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44483$1101_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$libresoc.v:132304$6296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_logical0_logical_op__zero_a + connect \Y $not$libresoc.v:132304$6296_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:44484$1102 - parameter \WIDTH 1 - connect \A \mspi0_clk__core__o - connect \B \io_bd [51] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44484$1102_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$libresoc.v:132305$6297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_logical0_logical_op__imm_data__ok + connect \Y $not$libresoc.v:132305$6297_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:44485$1103 - parameter \WIDTH 1 - connect \A \mspi0_cs_n__core__o - connect \B \io_bd [52] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44485$1103_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$libresoc.v:132272$6264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$31 + connect \B \$33 + connect \Y $or$libresoc.v:132272$6264_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:44486$1104 - parameter \WIDTH 1 - connect \A \mspi0_mosi__core__o - connect \B \io_bd [53] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44486$1104_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$libresoc.v:132283$6275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:132283$6275_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:44488$1106 - parameter \WIDTH 1 - connect \A \mspi0_miso__pad__i - connect \B \io_bd [54] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44488$1106_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$libresoc.v:132284$6276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:132284$6276_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:44489$1107 - parameter \WIDTH 1 - connect \A \mspi1_clk__core__o - connect \B \io_bd [55] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44489$1107_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$libresoc.v:132285$6277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:132285$6277_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:44490$1108 - parameter \WIDTH 1 - connect \A \mspi1_cs_n__core__o - connect \B \io_bd [56] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44490$1108_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$libresoc.v:132286$6278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:132286$6278_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:44491$1109 - parameter \WIDTH 1 - connect \A \mspi1_mosi__core__o - connect \B \io_bd [57] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44491$1109_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:132289$6281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$libresoc.v:132289$6281_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:44492$1110 - parameter \WIDTH 1 - connect \A \mspi1_miso__pad__i - connect \B \io_bd [58] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44492$1110_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:132290$6282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$4 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:132290$6282_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44493$1111 - parameter \WIDTH 1 - connect \A \mtwi_sda__pad__i - connect \B \io_bd [59] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44493$1111_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:132296$6288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$6 + connect \Y $reduce_and$libresoc.v:132296$6288_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44494$1112 - parameter \WIDTH 1 - connect \A \mtwi_sda__core__o - connect \B \io_bd [60] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44494$1112_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:132267$6259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \$25 + connect \Y $reduce_or$libresoc.v:132267$6259_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44495$1113 - parameter \WIDTH 1 - connect \A \mtwi_sda__core__oe - connect \B \io_bd [61] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44495$1113_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:132270$6262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:132270$6262_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:44496$1114 - parameter \WIDTH 1 - connect \A \mtwi_scl__core__o - connect \B \io_bd [62] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44496$1114_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:132271$6263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:132271$6263_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:44497$1115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:132293$6285 parameter \WIDTH 1 - connect \A \pwm_0__core__o - connect \B \io_bd [63] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44497$1115_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:44499$1117 + connect \A \src_l_q_src [0] + connect \B \opc_l_q_opc + connect \S \alu_logical0_logical_op__zero_a + connect \Y $ternary$libresoc.v:132293$6285_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:132294$6286 + parameter \WIDTH 64 + connect \A \src1_i + connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \S \alu_logical0_logical_op__zero_a + connect \Y $ternary$libresoc.v:132294$6286_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:132295$6287 parameter \WIDTH 1 - connect \A \pwm_1__core__o - connect \B \io_bd [64] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44499$1117_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44500$1118 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_logical0_logical_op__imm_data__ok + connect \Y $ternary$libresoc.v:132295$6287_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:132297$6289 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_logical0_logical_op__imm_data__data + connect \S \alu_logical0_logical_op__imm_data__ok + connect \Y $ternary$libresoc.v:132297$6289_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:132298$6290 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $ternary$libresoc.v:132298$6290_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:132299$6291 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm$80 + connect \S \src_sel$77 + connect \Y $ternary$libresoc.v:132299$6291_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:132300$6292 parameter \WIDTH 1 - connect \A \sd0_cmd__pad__i - connect \B \io_bd [65] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44500$1118_Y + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:132300$6292_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44501$1119 - parameter \WIDTH 1 - connect \A \sd0_cmd__core__o - connect \B \io_bd [66] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44501$1119_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:132386.14-132392.4" + cell \alu_l$61 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44502$1120 - parameter \WIDTH 1 - connect \A \sd0_cmd__core__oe - connect \B \io_bd [67] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44502$1120_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:132393.16-132425.4" + cell \alu_logical0 \alu_logical0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \alu_logical0_cr_a + connect \cr_a_ok \cr_a_ok + connect \logical_op__data_len \alu_logical0_logical_op__data_len + connect \logical_op__fn_unit \alu_logical0_logical_op__fn_unit + connect \logical_op__imm_data__data \alu_logical0_logical_op__imm_data__data + connect \logical_op__imm_data__ok \alu_logical0_logical_op__imm_data__ok + connect \logical_op__input_carry \alu_logical0_logical_op__input_carry + connect \logical_op__insn \alu_logical0_logical_op__insn + connect \logical_op__insn_type \alu_logical0_logical_op__insn_type + connect \logical_op__invert_in \alu_logical0_logical_op__invert_in + connect \logical_op__invert_out \alu_logical0_logical_op__invert_out + connect \logical_op__is_32bit \alu_logical0_logical_op__is_32bit + connect \logical_op__is_signed \alu_logical0_logical_op__is_signed + connect \logical_op__oe__oe \alu_logical0_logical_op__oe__oe + connect \logical_op__oe__ok \alu_logical0_logical_op__oe__ok + connect \logical_op__output_carry \alu_logical0_logical_op__output_carry + connect \logical_op__rc__ok \alu_logical0_logical_op__rc__ok + connect \logical_op__rc__rc \alu_logical0_logical_op__rc__rc + connect \logical_op__write_cr0 \alu_logical0_logical_op__write_cr0 + connect \logical_op__zero_a \alu_logical0_logical_op__zero_a + connect \n_ready_i \alu_logical0_n_ready_i + connect \n_valid_o \alu_logical0_n_valid_o + connect \o \alu_logical0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_logical0_p_ready_o + connect \p_valid_i \alu_logical0_p_valid_i + connect \ra \alu_logical0_ra + connect \rb \alu_logical0_rb + connect \xer_so \alu_logical0_xer_so end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:44503$1121 - parameter \WIDTH 1 - connect \A \sd0_clk__core__o - connect \B \io_bd [68] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44503$1121_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:132426.15-132432.4" + cell \alui_l$60 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44504$1122 - parameter \WIDTH 1 - connect \A \sd0_data0__pad__i - connect \B \io_bd [69] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44504$1122_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:132433.14-132439.4" + cell \opc_l$56 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44505$1123 - parameter \WIDTH 1 - connect \A \sd0_data0__core__o - connect \B \io_bd [70] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44505$1123_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:132440.14-132446.4" + cell \req_l$57 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44506$1124 - parameter \WIDTH 1 - connect \A \sd0_data0__core__oe - connect \B \io_bd [71] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44506$1124_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:132447.14-132453.4" + cell \rok_l$59 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44507$1125 - parameter \WIDTH 1 - connect \A \sd0_data1__pad__i - connect \B \io_bd [72] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44507$1125_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:132454.14-132459.4" + cell \rst_l$58 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44508$1126 - parameter \WIDTH 1 - connect \A \sd0_data1__core__o - connect \B \io_bd [73] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44508$1126_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:132460.14-132466.4" + cell \src_l$55 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44511$1129 - parameter \WIDTH 1 - connect \A \sd0_data1__core__oe - connect \B \io_bd [74] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44511$1129_Y + attribute \src "libresoc.v:131646.7-131646.20" + process $proc$libresoc.v:131646$6448 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44512$1130 - parameter \WIDTH 1 - connect \A \sd0_data2__pad__i - connect \B \io_bd [75] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44512$1130_Y + attribute \src "libresoc.v:131764.7-131764.24" + process $proc$libresoc.v:131764$6449 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44513$1131 - parameter \WIDTH 1 - connect \A \sd0_data2__core__o - connect \B \io_bd [76] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44513$1131_Y + attribute \src "libresoc.v:131774.7-131774.26" + process $proc$libresoc.v:131774$6450 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44514$1132 - parameter \WIDTH 1 - connect \A \sd0_data2__core__oe - connect \B \io_bd [77] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44514$1132_Y + attribute \src "libresoc.v:131782.7-131782.25" + process $proc$libresoc.v:131782$6451 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44515$1133 - parameter \WIDTH 1 - connect \A \sd0_data3__pad__i - connect \B \io_bd [78] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44515$1133_Y + attribute \src "libresoc.v:131790.13-131790.53" + process $proc$libresoc.v:131790$6452 + assign { } { } + assign $1\alu_logical0_logical_op__data_len[3:0] 4'0000 + sync always + sync init + update \alu_logical0_logical_op__data_len $1\alu_logical0_logical_op__data_len[3:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44516$1134 - parameter \WIDTH 1 - connect \A \sd0_data3__core__o - connect \B \io_bd [79] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44516$1134_Y + attribute \src "libresoc.v:131807.14-131807.56" + process $proc$libresoc.v:131807$6453 + assign { } { } + assign $1\alu_logical0_logical_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \alu_logical0_logical_op__fn_unit $1\alu_logical0_logical_op__fn_unit[11:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44517$1135 - parameter \WIDTH 1 - connect \A \sd0_data3__core__oe - connect \B \io_bd [80] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44517$1135_Y + attribute \src "libresoc.v:131811.14-131811.76" + process $proc$libresoc.v:131811$6454 + assign { } { } + assign $1\alu_logical0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_logical0_logical_op__imm_data__data $1\alu_logical0_logical_op__imm_data__data[63:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:44518$1136 - parameter \WIDTH 1 - connect \A \sdr_dm_0__core__o - connect \B \io_bd [81] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44518$1136_Y + attribute \src "libresoc.v:131815.7-131815.51" + process $proc$libresoc.v:131815$6455 + assign { } { } + assign $1\alu_logical0_logical_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__imm_data__ok $1\alu_logical0_logical_op__imm_data__ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44519$1137 - parameter \WIDTH 1 - connect \A \sdr_dq_0__pad__i - connect \B \io_bd [82] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44519$1137_Y + attribute \src "libresoc.v:131823.13-131823.56" + process $proc$libresoc.v:131823$6456 + assign { } { } + assign $1\alu_logical0_logical_op__input_carry[1:0] 2'00 + sync always + sync init + update \alu_logical0_logical_op__input_carry $1\alu_logical0_logical_op__input_carry[1:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44520$1138 - parameter \WIDTH 1 - connect \A \sdr_dq_0__core__o - connect \B \io_bd [83] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44520$1138_Y + attribute \src "libresoc.v:131827.14-131827.51" + process $proc$libresoc.v:131827$6457 + assign { } { } + assign $1\alu_logical0_logical_op__insn[31:0] 0 + sync always + sync init + update \alu_logical0_logical_op__insn $1\alu_logical0_logical_op__insn[31:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44522$1140 - parameter \WIDTH 1 - connect \A \sdr_dq_0__core__oe - connect \B \io_bd [84] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44522$1140_Y + attribute \src "libresoc.v:131905.13-131905.55" + process $proc$libresoc.v:131905$6458 + assign { } { } + assign $1\alu_logical0_logical_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_logical0_logical_op__insn_type $1\alu_logical0_logical_op__insn_type[6:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44523$1141 - parameter \WIDTH 1 - connect \A \sdr_dq_1__pad__i - connect \B \io_bd [85] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44523$1141_Y + attribute \src "libresoc.v:131909.7-131909.48" + process $proc$libresoc.v:131909$6459 + assign { } { } + assign $1\alu_logical0_logical_op__invert_in[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__invert_in $1\alu_logical0_logical_op__invert_in[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44524$1142 - parameter \WIDTH 1 - connect \A \sdr_dq_1__core__o - connect \B \io_bd [86] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44524$1142_Y + attribute \src "libresoc.v:131913.7-131913.49" + process $proc$libresoc.v:131913$6460 + assign { } { } + assign $1\alu_logical0_logical_op__invert_out[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__invert_out $1\alu_logical0_logical_op__invert_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44525$1143 - parameter \WIDTH 1 - connect \A \sdr_dq_1__core__oe - connect \B \io_bd [87] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44525$1143_Y + attribute \src "libresoc.v:131917.7-131917.47" + process $proc$libresoc.v:131917$6461 + assign { } { } + assign $1\alu_logical0_logical_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__is_32bit $1\alu_logical0_logical_op__is_32bit[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44526$1144 - parameter \WIDTH 1 - connect \A \sdr_dq_2__pad__i - connect \B \io_bd [88] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44526$1144_Y + attribute \src "libresoc.v:131921.7-131921.48" + process $proc$libresoc.v:131921$6462 + assign { } { } + assign $1\alu_logical0_logical_op__is_signed[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__is_signed $1\alu_logical0_logical_op__is_signed[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44527$1145 - parameter \WIDTH 1 - connect \A \sdr_dq_2__core__o - connect \B \io_bd [89] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44527$1145_Y + attribute \src "libresoc.v:131925.7-131925.45" + process $proc$libresoc.v:131925$6463 + assign { } { } + assign $1\alu_logical0_logical_op__oe__oe[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__oe__oe $1\alu_logical0_logical_op__oe__oe[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44528$1146 - parameter \WIDTH 1 - connect \A \sdr_dq_2__core__oe - connect \B \io_bd [90] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44528$1146_Y + attribute \src "libresoc.v:131929.7-131929.45" + process $proc$libresoc.v:131929$6464 + assign { } { } + assign $1\alu_logical0_logical_op__oe__ok[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__oe__ok $1\alu_logical0_logical_op__oe__ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44529$1147 - parameter \WIDTH 1 - connect \A \sdr_dq_3__pad__i - connect \B \io_bd [91] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44529$1147_Y + attribute \src "libresoc.v:131933.7-131933.51" + process $proc$libresoc.v:131933$6465 + assign { } { } + assign $1\alu_logical0_logical_op__output_carry[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__output_carry $1\alu_logical0_logical_op__output_carry[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44530$1148 - parameter \WIDTH 1 - connect \A \sdr_dq_3__core__o - connect \B \io_bd [92] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44530$1148_Y + attribute \src "libresoc.v:131937.7-131937.45" + process $proc$libresoc.v:131937$6466 + assign { } { } + assign $1\alu_logical0_logical_op__rc__ok[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__rc__ok $1\alu_logical0_logical_op__rc__ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44531$1149 - parameter \WIDTH 1 - connect \A \sdr_dq_3__core__oe - connect \B \io_bd [93] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44531$1149_Y + attribute \src "libresoc.v:131941.7-131941.45" + process $proc$libresoc.v:131941$6467 + assign { } { } + assign $1\alu_logical0_logical_op__rc__rc[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__rc__rc $1\alu_logical0_logical_op__rc__rc[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44533$1151 - parameter \WIDTH 1 - connect \A \sdr_dq_4__pad__i - connect \B \io_bd [94] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44533$1151_Y + attribute \src "libresoc.v:131945.7-131945.48" + process $proc$libresoc.v:131945$6468 + assign { } { } + assign $1\alu_logical0_logical_op__write_cr0[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__write_cr0 $1\alu_logical0_logical_op__write_cr0[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44534$1152 - parameter \WIDTH 1 - connect \A \sdr_dq_4__core__o - connect \B \io_bd [95] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44534$1152_Y + attribute \src "libresoc.v:131949.7-131949.45" + process $proc$libresoc.v:131949$6469 + assign { } { } + assign $1\alu_logical0_logical_op__zero_a[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__zero_a $1\alu_logical0_logical_op__zero_a[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44535$1153 - parameter \WIDTH 1 - connect \A \sdr_dq_4__core__oe - connect \B \io_bd [96] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44535$1153_Y + attribute \src "libresoc.v:131975.7-131975.27" + process $proc$libresoc.v:131975$6470 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44536$1154 - parameter \WIDTH 1 - connect \A \sdr_dq_5__pad__i - connect \B \io_bd [97] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44536$1154_Y + attribute \src "libresoc.v:132009.14-132009.47" + process $proc$libresoc.v:132009$6471 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44537$1155 - parameter \WIDTH 1 - connect \A \sdr_dq_5__core__o - connect \B \io_bd [98] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44537$1155_Y + attribute \src "libresoc.v:132013.7-132013.27" + process $proc$libresoc.v:132013$6472 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44538$1156 - parameter \WIDTH 1 - connect \A \sdr_dq_5__core__oe - connect \B \io_bd [99] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44538$1156_Y + attribute \src "libresoc.v:132017.13-132017.33" + process $proc$libresoc.v:132017$6473 + assign { } { } + assign $1\data_r1__cr_a[3:0] 4'0000 + sync always + sync init + update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44539$1157 - parameter \WIDTH 1 - connect \A \sdr_dq_6__pad__i - connect \B \io_bd [100] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44539$1157_Y + attribute \src "libresoc.v:132021.7-132021.30" + process $proc$libresoc.v:132021$6474 + assign { } { } + assign $1\data_r1__cr_a_ok[0:0] 1'0 + sync always + sync init + update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44540$1158 - parameter \WIDTH 1 - connect \A \sdr_dq_6__core__o - connect \B \io_bd [101] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44540$1158_Y + attribute \src "libresoc.v:132035.7-132035.25" + process $proc$libresoc.v:132035$6475 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44541$1159 - parameter \WIDTH 1 - connect \A \sdr_dq_6__core__oe - connect \B \io_bd [102] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44541$1159_Y + attribute \src "libresoc.v:132039.7-132039.25" + process $proc$libresoc.v:132039$6476 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44542$1160 - parameter \WIDTH 1 - connect \A \sdr_dq_7__pad__i - connect \B \io_bd [103] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44542$1160_Y + attribute \src "libresoc.v:132170.13-132170.30" + process $proc$libresoc.v:132170$6477 + assign { } { } + assign $1\prev_wr_go[1:0] 2'00 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[1:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44544$1162 - parameter \WIDTH 1 - connect \A \sdr_dq_7__core__o - connect \B \io_bd [104] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44544$1162_Y + attribute \src "libresoc.v:132178.13-132178.31" + process $proc$libresoc.v:132178$6478 + assign { } { } + assign $1\req_l_r_req[1:0] 2'11 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[1:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44545$1163 - parameter \WIDTH 1 - connect \A \sdr_dq_7__core__oe - connect \B \io_bd [105] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44545$1163_Y + attribute \src "libresoc.v:132182.13-132182.31" + process $proc$libresoc.v:132182$6479 + assign { } { } + assign $1\req_l_s_req[1:0] 2'00 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[1:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:44546$1164 - parameter \WIDTH 1 - connect \A \sdr_a_0__core__o - connect \B \io_bd [106] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44546$1164_Y + attribute \src "libresoc.v:132194.7-132194.26" + process $proc$libresoc.v:132194$6480 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:44547$1165 - parameter \WIDTH 1 - connect \A \sdr_a_1__core__o - connect \B \io_bd [107] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44547$1165_Y + attribute \src "libresoc.v:132198.7-132198.26" + process $proc$libresoc.v:132198$6481 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:44548$1166 - parameter \WIDTH 1 - connect \A \sdr_a_2__core__o - connect \B \io_bd [108] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44548$1166_Y + attribute \src "libresoc.v:132202.7-132202.25" + process $proc$libresoc.v:132202$6482 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:44549$1167 - parameter \WIDTH 1 - connect \A \sdr_a_3__core__o - connect \B \io_bd [109] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44549$1167_Y + attribute \src "libresoc.v:132206.7-132206.25" + process $proc$libresoc.v:132206$6483 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:44550$1168 - parameter \WIDTH 1 - connect \A \sdr_a_4__core__o - connect \B \io_bd [110] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44550$1168_Y + attribute \src "libresoc.v:132220.13-132220.31" + process $proc$libresoc.v:132220$6484 + assign { } { } + assign $1\src_l_r_src[2:0] 3'111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:44551$1169 - parameter \WIDTH 1 - connect \A \sdr_a_5__core__o - connect \B \io_bd [111] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44551$1169_Y + attribute \src "libresoc.v:132224.13-132224.31" + process $proc$libresoc.v:132224$6485 + assign { } { } + assign $1\src_l_s_src[2:0] 3'000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:44552$1170 - parameter \WIDTH 1 - connect \A \sdr_a_6__core__o - connect \B \io_bd [112] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44552$1170_Y + attribute \src "libresoc.v:132232.14-132232.43" + process $proc$libresoc.v:132232$6486 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:44553$1171 - parameter \WIDTH 1 - connect \A \sdr_a_7__core__o - connect \B \io_bd [113] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44553$1171_Y + attribute \src "libresoc.v:132236.14-132236.43" + process $proc$libresoc.v:132236$6487 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:44555$1173 - parameter \WIDTH 1 - connect \A \sdr_a_8__core__o - connect \B \io_bd [114] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44555$1173_Y + attribute \src "libresoc.v:132240.7-132240.20" + process $proc$libresoc.v:132240$6488 + assign { } { } + assign $1\src_r2[0:0] 1'0 + sync always + sync init + update \src_r2 $1\src_r2[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:44556$1174 - parameter \WIDTH 1 - connect \A \sdr_a_9__core__o - connect \B \io_bd [115] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44556$1174_Y + attribute \src "libresoc.v:132306.3-132307.39" + process $proc$libresoc.v:132306$6298 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:44557$1175 - parameter \WIDTH 1 - connect \A \sdr_ba_0__core__o - connect \B \io_bd [116] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44557$1175_Y + attribute \src "libresoc.v:132308.3-132309.43" + process $proc$libresoc.v:132308$6299 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:44558$1176 - parameter \WIDTH 1 - connect \A \sdr_ba_1__core__o - connect \B \io_bd [117] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44558$1176_Y + attribute \src "libresoc.v:132310.3-132311.29" + process $proc$libresoc.v:132310$6300 + assign { } { } + assign $0\src_r2[0:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:44559$1177 - parameter \WIDTH 1 - connect \A \sdr_clock__core__o - connect \B \io_bd [118] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44559$1177_Y + attribute \src "libresoc.v:132312.3-132313.29" + process $proc$libresoc.v:132312$6301 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:44560$1178 - parameter \WIDTH 1 - connect \A \sdr_cke__core__o - connect \B \io_bd [119] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44560$1178_Y + attribute \src "libresoc.v:132314.3-132315.29" + process $proc$libresoc.v:132314$6302 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:44561$1179 - parameter \WIDTH 1 - connect \A \sdr_ras_n__core__o - connect \B \io_bd [120] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44561$1179_Y + attribute \src "libresoc.v:132316.3-132317.43" + process $proc$libresoc.v:132316$6303 + assign { } { } + assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next + sync posedge \coresync_clk + update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:44562$1180 - parameter \WIDTH 1 - connect \A \sdr_cas_n__core__o - connect \B \io_bd [121] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44562$1180_Y + attribute \src "libresoc.v:132318.3-132319.49" + process $proc$libresoc.v:132318$6304 + assign { } { } + assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next + sync posedge \coresync_clk + update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:44563$1181 - parameter \WIDTH 1 - connect \A \sdr_we_n__core__o - connect \B \io_bd [122] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44563$1181_Y + attribute \src "libresoc.v:132320.3-132321.37" + process $proc$libresoc.v:132320$6305 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:44564$1182 - parameter \WIDTH 1 - connect \A \sdr_cs_n__core__o - connect \B \io_bd [123] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44564$1182_Y + attribute \src "libresoc.v:132322.3-132323.43" + process $proc$libresoc.v:132322$6306 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:44566$1184 - parameter \WIDTH 1 - connect \A \sdr_a_10__core__o - connect \B \io_bd [124] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44566$1184_Y + attribute \src "libresoc.v:132324.3-132325.85" + process $proc$libresoc.v:132324$6307 + assign { } { } + assign $0\alu_logical0_logical_op__insn_type[6:0] \alu_logical0_logical_op__insn_type$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__insn_type $0\alu_logical0_logical_op__insn_type[6:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:44567$1185 - parameter \WIDTH 1 - connect \A \sdr_a_11__core__o - connect \B \io_bd [125] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44567$1185_Y + attribute \src "libresoc.v:132326.3-132327.81" + process $proc$libresoc.v:132326$6308 + assign { } { } + assign $0\alu_logical0_logical_op__fn_unit[11:0] \alu_logical0_logical_op__fn_unit$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__fn_unit $0\alu_logical0_logical_op__fn_unit[11:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:44568$1186 - parameter \WIDTH 1 - connect \A \sdr_a_12__core__o - connect \B \io_bd [126] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44568$1186_Y + attribute \src "libresoc.v:132328.3-132329.95" + process $proc$libresoc.v:132328$6309 + assign { } { } + assign $0\alu_logical0_logical_op__imm_data__data[63:0] \alu_logical0_logical_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__imm_data__data $0\alu_logical0_logical_op__imm_data__data[63:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44569$1187 - parameter \WIDTH 1 - connect \A \sdr_dm_1__pad__i - connect \B \io_bd [127] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44569$1187_Y + attribute \src "libresoc.v:132330.3-132331.91" + process $proc$libresoc.v:132330$6310 + assign { } { } + assign $0\alu_logical0_logical_op__imm_data__ok[0:0] \alu_logical0_logical_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__imm_data__ok $0\alu_logical0_logical_op__imm_data__ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44570$1188 - parameter \WIDTH 1 - connect \A \sdr_dm_1__core__o - connect \B \io_bd [128] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44570$1188_Y + attribute \src "libresoc.v:132332.3-132333.79" + process $proc$libresoc.v:132332$6311 + assign { } { } + assign $0\alu_logical0_logical_op__rc__rc[0:0] \alu_logical0_logical_op__rc__rc$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__rc__rc $0\alu_logical0_logical_op__rc__rc[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44571$1189 - parameter \WIDTH 1 - connect \A \sdr_dm_1__core__oe - connect \B \io_bd [129] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44571$1189_Y + attribute \src "libresoc.v:132334.3-132335.79" + process $proc$libresoc.v:132334$6312 + assign { } { } + assign $0\alu_logical0_logical_op__rc__ok[0:0] \alu_logical0_logical_op__rc__ok$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__rc__ok $0\alu_logical0_logical_op__rc__ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44572$1190 - parameter \WIDTH 1 - connect \A \sdr_dq_8__pad__i - connect \B \io_bd [130] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44572$1190_Y + attribute \src "libresoc.v:132336.3-132337.79" + process $proc$libresoc.v:132336$6313 + assign { } { } + assign $0\alu_logical0_logical_op__oe__oe[0:0] \alu_logical0_logical_op__oe__oe$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__oe__oe $0\alu_logical0_logical_op__oe__oe[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44573$1191 - parameter \WIDTH 1 - connect \A \sdr_dq_8__core__o - connect \B \io_bd [131] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44573$1191_Y + attribute \src "libresoc.v:132338.3-132339.79" + process $proc$libresoc.v:132338$6314 + assign { } { } + assign $0\alu_logical0_logical_op__oe__ok[0:0] \alu_logical0_logical_op__oe__ok$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__oe__ok $0\alu_logical0_logical_op__oe__ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44574$1192 - parameter \WIDTH 1 - connect \A \sdr_dq_8__core__oe - connect \B \io_bd [132] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44574$1192_Y + attribute \src "libresoc.v:132340.3-132341.85" + process $proc$libresoc.v:132340$6315 + assign { } { } + assign $0\alu_logical0_logical_op__invert_in[0:0] \alu_logical0_logical_op__invert_in$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__invert_in $0\alu_logical0_logical_op__invert_in[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44575$1193 - parameter \WIDTH 1 - connect \A \sdr_dq_9__pad__i - connect \B \io_bd [133] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44575$1193_Y + attribute \src "libresoc.v:132342.3-132343.79" + process $proc$libresoc.v:132342$6316 + assign { } { } + assign $0\alu_logical0_logical_op__zero_a[0:0] \alu_logical0_logical_op__zero_a$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__zero_a $0\alu_logical0_logical_op__zero_a[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44577$1195 - parameter \WIDTH 1 - connect \A \sdr_dq_9__core__o - connect \B \io_bd [134] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44577$1195_Y + attribute \src "libresoc.v:132344.3-132345.89" + process $proc$libresoc.v:132344$6317 + assign { } { } + assign $0\alu_logical0_logical_op__input_carry[1:0] \alu_logical0_logical_op__input_carry$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__input_carry $0\alu_logical0_logical_op__input_carry[1:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44578$1196 - parameter \WIDTH 1 - connect \A \sdr_dq_9__core__oe - connect \B \io_bd [135] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44578$1196_Y + attribute \src "libresoc.v:132346.3-132347.87" + process $proc$libresoc.v:132346$6318 + assign { } { } + assign $0\alu_logical0_logical_op__invert_out[0:0] \alu_logical0_logical_op__invert_out$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__invert_out $0\alu_logical0_logical_op__invert_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44579$1197 - parameter \WIDTH 1 - connect \A \sdr_dq_10__pad__i - connect \B \io_bd [136] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44579$1197_Y + attribute \src "libresoc.v:132348.3-132349.85" + process $proc$libresoc.v:132348$6319 + assign { } { } + assign $0\alu_logical0_logical_op__write_cr0[0:0] \alu_logical0_logical_op__write_cr0$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__write_cr0 $0\alu_logical0_logical_op__write_cr0[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44580$1198 - parameter \WIDTH 1 - connect \A \sdr_dq_10__core__o - connect \B \io_bd [137] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44580$1198_Y + attribute \src "libresoc.v:132350.3-132351.91" + process $proc$libresoc.v:132350$6320 + assign { } { } + assign $0\alu_logical0_logical_op__output_carry[0:0] \alu_logical0_logical_op__output_carry$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__output_carry $0\alu_logical0_logical_op__output_carry[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44581$1199 - parameter \WIDTH 1 - connect \A \sdr_dq_10__core__oe - connect \B \io_bd [138] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44581$1199_Y + attribute \src "libresoc.v:132352.3-132353.83" + process $proc$libresoc.v:132352$6321 + assign { } { } + assign $0\alu_logical0_logical_op__is_32bit[0:0] \alu_logical0_logical_op__is_32bit$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__is_32bit $0\alu_logical0_logical_op__is_32bit[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44582$1200 - parameter \WIDTH 1 - connect \A \sdr_dq_11__pad__i - connect \B \io_bd [139] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44582$1200_Y + attribute \src "libresoc.v:132354.3-132355.85" + process $proc$libresoc.v:132354$6322 + assign { } { } + assign $0\alu_logical0_logical_op__is_signed[0:0] \alu_logical0_logical_op__is_signed$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__is_signed $0\alu_logical0_logical_op__is_signed[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44583$1201 - parameter \WIDTH 1 - connect \A \sdr_dq_11__core__o - connect \B \io_bd [140] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44583$1201_Y + attribute \src "libresoc.v:132356.3-132357.83" + process $proc$libresoc.v:132356$6323 + assign { } { } + assign $0\alu_logical0_logical_op__data_len[3:0] \alu_logical0_logical_op__data_len$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__data_len $0\alu_logical0_logical_op__data_len[3:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44584$1202 - parameter \WIDTH 1 - connect \A \sdr_dq_11__core__oe - connect \B \io_bd [141] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44584$1202_Y + attribute \src "libresoc.v:132358.3-132359.75" + process $proc$libresoc.v:132358$6324 + assign { } { } + assign $0\alu_logical0_logical_op__insn[31:0] \alu_logical0_logical_op__insn$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__insn $0\alu_logical0_logical_op__insn[31:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44585$1203 - parameter \WIDTH 1 - connect \A \sdr_dq_12__pad__i - connect \B \io_bd [142] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44585$1203_Y + attribute \src "libresoc.v:132360.3-132361.39" + process $proc$libresoc.v:132360$6325 + assign { } { } + assign $0\req_l_r_req[1:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[1:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44586$1204 - parameter \WIDTH 1 - connect \A \sdr_dq_12__core__o - connect \B \io_bd [143] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44586$1204_Y + attribute \src "libresoc.v:132362.3-132363.39" + process $proc$libresoc.v:132362$6326 + assign { } { } + assign $0\req_l_s_req[1:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[1:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44588$1206 - parameter \WIDTH 1 - connect \A \sdr_dq_12__core__oe - connect \B \io_bd [144] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44588$1206_Y + attribute \src "libresoc.v:132364.3-132365.39" + process $proc$libresoc.v:132364$6327 + assign { } { } + assign $0\src_l_r_src[2:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44589$1207 - parameter \WIDTH 1 - connect \A \sdr_dq_13__pad__i - connect \B \io_bd [145] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44589$1207_Y + attribute \src "libresoc.v:132366.3-132367.39" + process $proc$libresoc.v:132366$6328 + assign { } { } + assign $0\src_l_s_src[2:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44590$1208 - parameter \WIDTH 1 - connect \A \sdr_dq_13__core__o - connect \B \io_bd [146] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44590$1208_Y + attribute \src "libresoc.v:132368.3-132369.39" + process $proc$libresoc.v:132368$6329 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44591$1209 - parameter \WIDTH 1 - connect \A \sdr_dq_13__core__oe - connect \B \io_bd [147] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44591$1209_Y + attribute \src "libresoc.v:132370.3-132371.39" + process $proc$libresoc.v:132370$6330 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44592$1210 - parameter \WIDTH 1 - connect \A \sdr_dq_14__pad__i - connect \B \io_bd [148] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44592$1210_Y + attribute \src "libresoc.v:132372.3-132373.39" + process $proc$libresoc.v:132372$6331 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44593$1211 - parameter \WIDTH 1 - connect \A \sdr_dq_14__core__o - connect \B \io_bd [149] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44593$1211_Y + attribute \src "libresoc.v:132374.3-132375.39" + process $proc$libresoc.v:132374$6332 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44594$1212 - parameter \WIDTH 1 - connect \A \sdr_dq_14__core__oe - connect \B \io_bd [150] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44594$1212_Y + attribute \src "libresoc.v:132376.3-132377.41" + process $proc$libresoc.v:132376$6333 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44595$1213 - parameter \WIDTH 1 - connect \A \sdr_dq_15__pad__i - connect \B \io_bd [151] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44595$1213_Y + attribute \src "libresoc.v:132378.3-132379.41" + process $proc$libresoc.v:132378$6334 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44596$1214 - parameter \WIDTH 1 - connect \A \sdr_dq_15__core__o - connect \B \io_bd [152] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44596$1214_Y + attribute \src "libresoc.v:132380.3-132381.37" + process $proc$libresoc.v:132380$6335 + assign { } { } + assign $0\prev_wr_go[1:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[1:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44597$1215 - parameter \WIDTH 1 - connect \A \sdr_dq_15__core__oe - connect \B \io_bd [153] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44597$1215_Y + attribute \src "libresoc.v:132382.3-132383.44" + process $proc$libresoc.v:132382$6336 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_logical0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:44684$1303 - parameter \WIDTH 1 - connect \A \eint_0__pad__i - connect \B \io_bd [0] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44684$1303_Y + attribute \src "libresoc.v:132384.3-132385.24" + process $proc$libresoc.v:132384$6337 + assign { } { } + assign $0\all_rd_dly[0:0] \$9 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:44685$1304 - parameter \WIDTH 1 - connect \A \eint_1__pad__i - connect \B \io_bd [1] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44685$1304_Y + attribute \src "libresoc.v:132467.3-132476.6" + process $proc$libresoc.v:132467$6338 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:132468.5-132468.29" + switch \initial + attribute \src "libresoc.v:132468.9-132468.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$53 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$45 + end + sync always + update \req_done $0\req_done[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:44686$1305 - parameter \WIDTH 1 - connect \A \eint_2__pad__i - connect \B \io_bd [2] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44686$1305_Y + attribute \src "libresoc.v:132477.3-132485.6" + process $proc$libresoc.v:132477$6339 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$6340 $1\rok_l_s_rdok$next[0:0]$6341 + attribute \src "libresoc.v:132478.5-132478.29" + switch \initial + attribute \src "libresoc.v:132478.9-132478.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$6341 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$6341 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$6340 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44687$1306 - parameter \WIDTH 1 - connect \A \gpio_e8__pad__i - connect \B \io_bd [3] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44687$1306_Y + attribute \src "libresoc.v:132486.3-132494.6" + process $proc$libresoc.v:132486$6342 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$6343 $1\rok_l_r_rdok$next[0:0]$6344 + attribute \src "libresoc.v:132487.5-132487.29" + switch \initial + attribute \src "libresoc.v:132487.9-132487.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$6344 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$6344 \$63 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$6343 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44689$1308 - parameter \WIDTH 1 - connect \A \gpio_e8__core__o - connect \B \io_bd [4] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44689$1308_Y + attribute \src "libresoc.v:132495.3-132503.6" + process $proc$libresoc.v:132495$6345 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$6346 $1\rst_l_s_rst$next[0:0]$6347 + attribute \src "libresoc.v:132496.5-132496.29" + switch \initial + attribute \src "libresoc.v:132496.9-132496.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$6347 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$6347 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$6346 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44690$1309 - parameter \WIDTH 1 - connect \A \gpio_e8__core__oe - connect \B \io_bd [5] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44690$1309_Y + attribute \src "libresoc.v:132504.3-132512.6" + process $proc$libresoc.v:132504$6348 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$6349 $1\rst_l_r_rst$next[0:0]$6350 + attribute \src "libresoc.v:132505.5-132505.29" + switch \initial + attribute \src "libresoc.v:132505.9-132505.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$6350 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$6350 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$6349 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44691$1310 - parameter \WIDTH 1 - connect \A \gpio_e9__pad__i - connect \B \io_bd [6] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44691$1310_Y + attribute \src "libresoc.v:132513.3-132521.6" + process $proc$libresoc.v:132513$6351 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$6352 $1\opc_l_s_opc$next[0:0]$6353 + attribute \src "libresoc.v:132514.5-132514.29" + switch \initial + attribute \src "libresoc.v:132514.9-132514.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$6353 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$6353 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6352 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44692$1311 - parameter \WIDTH 1 - connect \A \gpio_e9__core__o - connect \B \io_bd [7] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44692$1311_Y + attribute \src "libresoc.v:132522.3-132530.6" + process $proc$libresoc.v:132522$6354 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$6355 $1\opc_l_r_opc$next[0:0]$6356 + attribute \src "libresoc.v:132523.5-132523.29" + switch \initial + attribute \src "libresoc.v:132523.9-132523.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$6356 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$6356 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6355 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44693$1312 - parameter \WIDTH 1 - connect \A \gpio_e9__core__oe - connect \B \io_bd [8] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44693$1312_Y + attribute \src "libresoc.v:132531.3-132539.6" + process $proc$libresoc.v:132531$6357 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[2:0]$6358 $1\src_l_s_src$next[2:0]$6359 + attribute \src "libresoc.v:132532.5-132532.29" + switch \initial + attribute \src "libresoc.v:132532.9-132532.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[2:0]$6359 3'000 + case + assign $1\src_l_s_src$next[2:0]$6359 { \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6358 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44694$1313 - parameter \WIDTH 1 - connect \A \gpio_e10__pad__i - connect \B \io_bd [9] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44694$1313_Y + attribute \src "libresoc.v:132540.3-132548.6" + process $proc$libresoc.v:132540$6360 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[2:0]$6361 $1\src_l_r_src$next[2:0]$6362 + attribute \src "libresoc.v:132541.5-132541.29" + switch \initial + attribute \src "libresoc.v:132541.9-132541.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[2:0]$6362 3'111 + case + assign $1\src_l_r_src$next[2:0]$6362 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6361 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44695$1314 - parameter \WIDTH 1 - connect \A \gpio_e10__core__o - connect \B \io_bd [10] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44695$1314_Y + attribute \src "libresoc.v:132549.3-132557.6" + process $proc$libresoc.v:132549$6363 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[1:0]$6364 $1\req_l_s_req$next[1:0]$6365 + attribute \src "libresoc.v:132550.5-132550.29" + switch \initial + attribute \src "libresoc.v:132550.9-132550.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[1:0]$6365 2'00 + case + assign $1\req_l_s_req$next[1:0]$6365 \$65 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[1:0]$6364 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44696$1315 - parameter \WIDTH 1 - connect \A \gpio_e10__core__oe - connect \B \io_bd [11] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44696$1315_Y + attribute \src "libresoc.v:132558.3-132566.6" + process $proc$libresoc.v:132558$6366 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[1:0]$6367 $1\req_l_r_req$next[1:0]$6368 + attribute \src "libresoc.v:132559.5-132559.29" + switch \initial + attribute \src "libresoc.v:132559.9-132559.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[1:0]$6368 2'11 + case + assign $1\req_l_r_req$next[1:0]$6368 \$67 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[1:0]$6367 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44697$1316 - parameter \WIDTH 1 - connect \A \gpio_e11__pad__i - connect \B \io_bd [12] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44697$1316_Y + attribute \src "libresoc.v:132567.3-132605.6" + process $proc$libresoc.v:132567$6369 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_logical0_logical_op__data_len$next[3:0]$6370 $1\alu_logical0_logical_op__data_len$next[3:0]$6388 + assign $0\alu_logical0_logical_op__fn_unit$next[11:0]$6371 $1\alu_logical0_logical_op__fn_unit$next[11:0]$6389 + assign { } { } + assign { } { } + assign $0\alu_logical0_logical_op__input_carry$next[1:0]$6374 $1\alu_logical0_logical_op__input_carry$next[1:0]$6392 + assign $0\alu_logical0_logical_op__insn$next[31:0]$6375 $1\alu_logical0_logical_op__insn$next[31:0]$6393 + assign $0\alu_logical0_logical_op__insn_type$next[6:0]$6376 $1\alu_logical0_logical_op__insn_type$next[6:0]$6394 + assign $0\alu_logical0_logical_op__invert_in$next[0:0]$6377 $1\alu_logical0_logical_op__invert_in$next[0:0]$6395 + assign $0\alu_logical0_logical_op__invert_out$next[0:0]$6378 $1\alu_logical0_logical_op__invert_out$next[0:0]$6396 + assign $0\alu_logical0_logical_op__is_32bit$next[0:0]$6379 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6397 + assign $0\alu_logical0_logical_op__is_signed$next[0:0]$6380 $1\alu_logical0_logical_op__is_signed$next[0:0]$6398 + assign { } { } + assign { } { } + assign $0\alu_logical0_logical_op__output_carry$next[0:0]$6383 $1\alu_logical0_logical_op__output_carry$next[0:0]$6401 + assign { } { } + assign { } { } + assign $0\alu_logical0_logical_op__write_cr0$next[0:0]$6386 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6404 + assign $0\alu_logical0_logical_op__zero_a$next[0:0]$6387 $1\alu_logical0_logical_op__zero_a$next[0:0]$6405 + assign $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6372 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6406 + assign $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6373 $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6407 + assign $0\alu_logical0_logical_op__oe__oe$next[0:0]$6381 $2\alu_logical0_logical_op__oe__oe$next[0:0]$6408 + assign $0\alu_logical0_logical_op__oe__ok$next[0:0]$6382 $2\alu_logical0_logical_op__oe__ok$next[0:0]$6409 + assign $0\alu_logical0_logical_op__rc__ok$next[0:0]$6384 $2\alu_logical0_logical_op__rc__ok$next[0:0]$6410 + assign $0\alu_logical0_logical_op__rc__rc$next[0:0]$6385 $2\alu_logical0_logical_op__rc__rc$next[0:0]$6411 + attribute \src "libresoc.v:132568.5-132568.29" + switch \initial + attribute \src "libresoc.v:132568.9-132568.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_logical0_logical_op__insn$next[31:0]$6393 $1\alu_logical0_logical_op__data_len$next[3:0]$6388 $1\alu_logical0_logical_op__is_signed$next[0:0]$6398 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6397 $1\alu_logical0_logical_op__output_carry$next[0:0]$6401 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6404 $1\alu_logical0_logical_op__invert_out$next[0:0]$6396 $1\alu_logical0_logical_op__input_carry$next[1:0]$6392 $1\alu_logical0_logical_op__zero_a$next[0:0]$6405 $1\alu_logical0_logical_op__invert_in$next[0:0]$6395 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6400 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6399 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6402 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6403 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6391 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6390 $1\alu_logical0_logical_op__fn_unit$next[11:0]$6389 $1\alu_logical0_logical_op__insn_type$next[6:0]$6394 } { \oper_i_alu_logical0__insn \oper_i_alu_logical0__data_len \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__insn_type } + case + assign $1\alu_logical0_logical_op__data_len$next[3:0]$6388 \alu_logical0_logical_op__data_len + assign $1\alu_logical0_logical_op__fn_unit$next[11:0]$6389 \alu_logical0_logical_op__fn_unit + assign $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6390 \alu_logical0_logical_op__imm_data__data + assign $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6391 \alu_logical0_logical_op__imm_data__ok + assign $1\alu_logical0_logical_op__input_carry$next[1:0]$6392 \alu_logical0_logical_op__input_carry + assign $1\alu_logical0_logical_op__insn$next[31:0]$6393 \alu_logical0_logical_op__insn + assign $1\alu_logical0_logical_op__insn_type$next[6:0]$6394 \alu_logical0_logical_op__insn_type + assign $1\alu_logical0_logical_op__invert_in$next[0:0]$6395 \alu_logical0_logical_op__invert_in + assign $1\alu_logical0_logical_op__invert_out$next[0:0]$6396 \alu_logical0_logical_op__invert_out + assign $1\alu_logical0_logical_op__is_32bit$next[0:0]$6397 \alu_logical0_logical_op__is_32bit + assign $1\alu_logical0_logical_op__is_signed$next[0:0]$6398 \alu_logical0_logical_op__is_signed + assign $1\alu_logical0_logical_op__oe__oe$next[0:0]$6399 \alu_logical0_logical_op__oe__oe + assign $1\alu_logical0_logical_op__oe__ok$next[0:0]$6400 \alu_logical0_logical_op__oe__ok + assign $1\alu_logical0_logical_op__output_carry$next[0:0]$6401 \alu_logical0_logical_op__output_carry + assign $1\alu_logical0_logical_op__rc__ok$next[0:0]$6402 \alu_logical0_logical_op__rc__ok + assign $1\alu_logical0_logical_op__rc__rc$next[0:0]$6403 \alu_logical0_logical_op__rc__rc + assign $1\alu_logical0_logical_op__write_cr0$next[0:0]$6404 \alu_logical0_logical_op__write_cr0 + assign $1\alu_logical0_logical_op__zero_a$next[0:0]$6405 \alu_logical0_logical_op__zero_a + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6406 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6407 1'0 + assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6411 1'0 + assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6410 1'0 + assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6408 1'0 + assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6409 1'0 + case + assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6406 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6390 + assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6407 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6391 + assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6408 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6399 + assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6409 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6400 + assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6410 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6402 + assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6411 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6403 + end + sync always + update \alu_logical0_logical_op__data_len$next $0\alu_logical0_logical_op__data_len$next[3:0]$6370 + update \alu_logical0_logical_op__fn_unit$next $0\alu_logical0_logical_op__fn_unit$next[11:0]$6371 + update \alu_logical0_logical_op__imm_data__data$next $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6372 + update \alu_logical0_logical_op__imm_data__ok$next $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6373 + update \alu_logical0_logical_op__input_carry$next $0\alu_logical0_logical_op__input_carry$next[1:0]$6374 + update \alu_logical0_logical_op__insn$next $0\alu_logical0_logical_op__insn$next[31:0]$6375 + update \alu_logical0_logical_op__insn_type$next $0\alu_logical0_logical_op__insn_type$next[6:0]$6376 + update \alu_logical0_logical_op__invert_in$next $0\alu_logical0_logical_op__invert_in$next[0:0]$6377 + update \alu_logical0_logical_op__invert_out$next $0\alu_logical0_logical_op__invert_out$next[0:0]$6378 + update \alu_logical0_logical_op__is_32bit$next $0\alu_logical0_logical_op__is_32bit$next[0:0]$6379 + update \alu_logical0_logical_op__is_signed$next $0\alu_logical0_logical_op__is_signed$next[0:0]$6380 + update \alu_logical0_logical_op__oe__oe$next $0\alu_logical0_logical_op__oe__oe$next[0:0]$6381 + update \alu_logical0_logical_op__oe__ok$next $0\alu_logical0_logical_op__oe__ok$next[0:0]$6382 + update \alu_logical0_logical_op__output_carry$next $0\alu_logical0_logical_op__output_carry$next[0:0]$6383 + update \alu_logical0_logical_op__rc__ok$next $0\alu_logical0_logical_op__rc__ok$next[0:0]$6384 + update \alu_logical0_logical_op__rc__rc$next $0\alu_logical0_logical_op__rc__rc$next[0:0]$6385 + update \alu_logical0_logical_op__write_cr0$next $0\alu_logical0_logical_op__write_cr0$next[0:0]$6386 + update \alu_logical0_logical_op__zero_a$next $0\alu_logical0_logical_op__zero_a$next[0:0]$6387 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44698$1317 - parameter \WIDTH 1 - connect \A \gpio_e11__core__o - connect \B \io_bd [13] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44698$1317_Y + attribute \src "libresoc.v:132606.3-132627.6" + process $proc$libresoc.v:132606$6412 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$6413 $2\data_r0__o$next[63:0]$6417 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$6414 $3\data_r0__o_ok$next[0:0]$6419 + attribute \src "libresoc.v:132607.5-132607.29" + switch \initial + attribute \src "libresoc.v:132607.9-132607.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$6416 $1\data_r0__o$next[63:0]$6415 } { \o_ok \alu_logical0_o } + case + assign $1\data_r0__o$next[63:0]$6415 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$6416 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$6418 $2\data_r0__o$next[63:0]$6417 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$6417 $1\data_r0__o$next[63:0]$6415 + assign $2\data_r0__o_ok$next[0:0]$6418 $1\data_r0__o_ok$next[0:0]$6416 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$6419 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$6419 $2\data_r0__o_ok$next[0:0]$6418 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$6413 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$6414 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44700$1319 - parameter \WIDTH 1 - connect \A \gpio_e11__core__oe - connect \B \io_bd [14] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44700$1319_Y + attribute \src "libresoc.v:132628.3-132649.6" + process $proc$libresoc.v:132628$6420 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__cr_a$next[3:0]$6421 $2\data_r1__cr_a$next[3:0]$6425 + assign { } { } + assign $0\data_r1__cr_a_ok$next[0:0]$6422 $3\data_r1__cr_a_ok$next[0:0]$6427 + attribute \src "libresoc.v:132629.5-132629.29" + switch \initial + attribute \src "libresoc.v:132629.9-132629.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__cr_a_ok$next[0:0]$6424 $1\data_r1__cr_a$next[3:0]$6423 } { \cr_a_ok \alu_logical0_cr_a } + case + assign $1\data_r1__cr_a$next[3:0]$6423 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$6424 \data_r1__cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__cr_a_ok$next[0:0]$6426 $2\data_r1__cr_a$next[3:0]$6425 } 5'00000 + case + assign $2\data_r1__cr_a$next[3:0]$6425 $1\data_r1__cr_a$next[3:0]$6423 + assign $2\data_r1__cr_a_ok$next[0:0]$6426 $1\data_r1__cr_a_ok$next[0:0]$6424 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__cr_a_ok$next[0:0]$6427 1'0 + case + assign $3\data_r1__cr_a_ok$next[0:0]$6427 $2\data_r1__cr_a_ok$next[0:0]$6426 + end + sync always + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$6421 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$6422 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44701$1320 - parameter \WIDTH 1 - connect \A \gpio_e12__pad__i - connect \B \io_bd [15] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44701$1320_Y + attribute \src "libresoc.v:132650.3-132659.6" + process $proc$libresoc.v:132650$6428 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$6429 $1\src_r0$next[63:0]$6430 + attribute \src "libresoc.v:132651.5-132651.29" + switch \initial + attribute \src "libresoc.v:132651.9-132651.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_sel + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$6430 \src_or_imm + case + assign $1\src_r0$next[63:0]$6430 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$6429 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44702$1321 - parameter \WIDTH 1 - connect \A \gpio_e12__core__o - connect \B \io_bd [16] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44702$1321_Y + attribute \src "libresoc.v:132660.3-132669.6" + process $proc$libresoc.v:132660$6431 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$6432 $1\src_r1$next[63:0]$6433 + attribute \src "libresoc.v:132661.5-132661.29" + switch \initial + attribute \src "libresoc.v:132661.9-132661.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_sel$77 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$6433 \src_or_imm$80 + case + assign $1\src_r1$next[63:0]$6433 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$6432 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44703$1322 - parameter \WIDTH 1 - connect \A \gpio_e12__core__oe - connect \B \io_bd [17] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44703$1322_Y + attribute \src "libresoc.v:132670.3-132679.6" + process $proc$libresoc.v:132670$6434 + assign { } { } + assign { } { } + assign $0\src_r2$next[0:0]$6435 $1\src_r2$next[0:0]$6436 + attribute \src "libresoc.v:132671.5-132671.29" + switch \initial + attribute \src "libresoc.v:132671.9-132671.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[0:0]$6436 \src3_i + case + assign $1\src_r2$next[0:0]$6436 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[0:0]$6435 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44704$1323 - parameter \WIDTH 1 - connect \A \gpio_e13__pad__i - connect \B \io_bd [18] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44704$1323_Y + attribute \src "libresoc.v:132680.3-132688.6" + process $proc$libresoc.v:132680$6437 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$6438 $1\alui_l_r_alui$next[0:0]$6439 + attribute \src "libresoc.v:132681.5-132681.29" + switch \initial + attribute \src "libresoc.v:132681.9-132681.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$6439 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$6439 \$89 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$6438 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44705$1324 - parameter \WIDTH 1 - connect \A \gpio_e13__core__o - connect \B \io_bd [19] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44705$1324_Y + attribute \src "libresoc.v:132689.3-132697.6" + process $proc$libresoc.v:132689$6440 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$6441 $1\alu_l_r_alu$next[0:0]$6442 + attribute \src "libresoc.v:132690.5-132690.29" + switch \initial + attribute \src "libresoc.v:132690.9-132690.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$6442 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$6442 \$91 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$6441 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44706$1325 - parameter \WIDTH 1 - connect \A \gpio_e13__core__oe - connect \B \io_bd [20] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44706$1325_Y + attribute \src "libresoc.v:132698.3-132707.6" + process $proc$libresoc.v:132698$6443 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:132699.5-132699.29" + switch \initial + attribute \src "libresoc.v:132699.9-132699.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$113 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__o + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:44707$1326 - parameter \WIDTH 1 - connect \A \gpio_e14__pad__i - connect \B \io_bd [21] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:44707$1326_Y + attribute \src "libresoc.v:132708.3-132717.6" + process $proc$libresoc.v:132708$6444 + assign { } { } + assign { } { } + assign $0\dest2_o[3:0] $1\dest2_o[3:0] + attribute \src "libresoc.v:132709.5-132709.29" + switch \initial + attribute \src "libresoc.v:132709.9-132709.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$115 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[3:0] \data_r1__cr_a + case + assign $1\dest2_o[3:0] 4'0000 + end + sync always + update \dest2_o $0\dest2_o[3:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:44708$1327 - parameter \WIDTH 1 - connect \A \gpio_e14__core__o - connect \B \io_bd [22] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44708$1327_Y + attribute \src "libresoc.v:132718.3-132726.6" + process $proc$libresoc.v:132718$6445 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[1:0]$6446 $1\prev_wr_go$next[1:0]$6447 + attribute \src "libresoc.v:132719.5-132719.29" + switch \initial + attribute \src "libresoc.v:132719.9-132719.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[1:0]$6447 2'00 + case + assign $1\prev_wr_go$next[1:0]$6447 \$19 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[1:0]$6446 + end + connect \$9 $and$libresoc.v:132249$6241_Y + connect \$99 $and$libresoc.v:132250$6242_Y + connect \$101 $not$libresoc.v:132251$6243_Y + connect \$103 $and$libresoc.v:132252$6244_Y + connect \$105 $and$libresoc.v:132253$6245_Y + connect \$107 $and$libresoc.v:132254$6246_Y + connect \$109 $and$libresoc.v:132255$6247_Y + connect \$111 $and$libresoc.v:132256$6248_Y + connect \$113 $and$libresoc.v:132257$6249_Y + connect \$115 $and$libresoc.v:132258$6250_Y + connect \$11 $not$libresoc.v:132259$6251_Y + connect \$13 $and$libresoc.v:132260$6252_Y + connect \$15 $not$libresoc.v:132261$6253_Y + connect \$17 $and$libresoc.v:132262$6254_Y + connect \$1 $and$libresoc.v:132263$6255_Y + connect \$19 $and$libresoc.v:132264$6256_Y + connect \$23 $not$libresoc.v:132265$6257_Y + connect \$25 $and$libresoc.v:132266$6258_Y + connect \$22 $reduce_or$libresoc.v:132267$6259_Y + connect \$21 $not$libresoc.v:132268$6260_Y + connect \$29 $and$libresoc.v:132269$6261_Y + connect \$31 $reduce_or$libresoc.v:132270$6262_Y + connect \$33 $reduce_or$libresoc.v:132271$6263_Y + connect \$35 $or$libresoc.v:132272$6264_Y + connect \$37 $not$libresoc.v:132273$6265_Y + connect \$39 $and$libresoc.v:132274$6266_Y + connect \$41 $and$libresoc.v:132275$6267_Y + connect \$43 $eq$libresoc.v:132276$6268_Y + connect \$45 $and$libresoc.v:132277$6269_Y + connect \$47 $eq$libresoc.v:132278$6270_Y + connect \$4 $not$libresoc.v:132279$6271_Y + connect \$49 $and$libresoc.v:132280$6272_Y + connect \$51 $and$libresoc.v:132281$6273_Y + connect \$53 $and$libresoc.v:132282$6274_Y + connect \$55 $or$libresoc.v:132283$6275_Y + connect \$57 $or$libresoc.v:132284$6276_Y + connect \$59 $or$libresoc.v:132285$6277_Y + connect \$61 $or$libresoc.v:132286$6278_Y + connect \$63 $and$libresoc.v:132287$6279_Y + connect \$65 $and$libresoc.v:132288$6280_Y + connect \$67 $or$libresoc.v:132289$6281_Y + connect \$6 $or$libresoc.v:132290$6282_Y + connect \$69 $and$libresoc.v:132291$6283_Y + connect \$71 $and$libresoc.v:132292$6284_Y + connect \$73 $ternary$libresoc.v:132293$6285_Y + connect \$75 $ternary$libresoc.v:132294$6286_Y + connect \$78 $ternary$libresoc.v:132295$6287_Y + connect \$3 $reduce_and$libresoc.v:132296$6288_Y + connect \$81 $ternary$libresoc.v:132297$6289_Y + connect \$83 $ternary$libresoc.v:132298$6290_Y + connect \$85 $ternary$libresoc.v:132299$6291_Y + connect \$87 $ternary$libresoc.v:132300$6292_Y + connect \$89 $and$libresoc.v:132301$6293_Y + connect \$91 $and$libresoc.v:132302$6294_Y + connect \$93 $and$libresoc.v:132303$6295_Y + connect \$95 $not$libresoc.v:132304$6296_Y + connect \$97 $not$libresoc.v:132305$6297_Y + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \cu_wr__rel_o \$111 + connect \cu_rd__rel_o \$103 + connect \cu_busy_o \opc_l_q_opc + connect \alu_l_s_alu \all_rd_pulse + connect \alu_logical0_n_ready_i \alu_l_q_alu + connect \alui_l_s_alui \all_rd_pulse + connect \alu_logical0_p_valid_i \alui_l_q_alui + connect \alu_logical0_xer_so \$87 + connect \alu_logical0_rb \$85 + connect \alu_logical0_ra \$83 + connect \src_or_imm$80 \$81 + connect \src_sel$77 \$78 + connect \src_or_imm \$75 + connect \src_sel \$73 + connect \cu_wrmask_o { \$71 \$69 } + connect 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\enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_logical_op__insn_type$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_in$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_out$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_32bit$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_signed$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__oe$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__output_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__ok$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__rc$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__write_cr0$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__zero_a$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 48 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 6 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 33 \logical_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_op__fn_unit$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 34 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 35 \logical_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 15 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 42 \logical_op__input_carry$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 49 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 5 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 32 \logical_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 40 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 43 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 46 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 47 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 38 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 39 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 45 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 37 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 36 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 44 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 41 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \main_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \main_logical_op__data_len$60 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \main_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \main_logical_op__fn_unit$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_logical_op__imm_data__data$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__imm_data__ok$47 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_logical_op__input_carry$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_logical_op__insn$61 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_logical_op__insn_type$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__invert_in$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__invert_out$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__is_32bit$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__is_signed$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__oe__oe$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__oe__ok$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__output_carry$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__rc__ok$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__rc__rc$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__write_cr0$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__zero_a$53 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \main_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_xer_so$62 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 31 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$66 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 23 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 24 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 30 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 29 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$63 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 50 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 51 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 27 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 52 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 28 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$libresoc.v:133827$6489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$63 + connect \B \p_ready_o + connect \Y $and$libresoc.v:133827$6489_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:44709$1328 - parameter \WIDTH 1 - connect \A \gpio_e14__core__oe - connect \B \io_bd [23] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:44709$1328_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:133880.14-133925.4" + cell \input$50 \input + connect \logical_op__data_len \input_logical_op__data_len + connect \logical_op__data_len$18 \input_logical_op__data_len$38 + connect \logical_op__fn_unit \input_logical_op__fn_unit + connect \logical_op__fn_unit$3 \input_logical_op__fn_unit$23 + connect \logical_op__imm_data__data \input_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \input_logical_op__imm_data__data$24 + connect \logical_op__imm_data__ok \input_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \input_logical_op__imm_data__ok$25 + connect \logical_op__input_carry \input_logical_op__input_carry + connect \logical_op__input_carry$12 \input_logical_op__input_carry$32 + connect \logical_op__insn \input_logical_op__insn + connect \logical_op__insn$19 \input_logical_op__insn$39 + connect \logical_op__insn_type \input_logical_op__insn_type + connect \logical_op__insn_type$2 \input_logical_op__insn_type$22 + connect \logical_op__invert_in \input_logical_op__invert_in + connect \logical_op__invert_in$10 \input_logical_op__invert_in$30 + connect \logical_op__invert_out \input_logical_op__invert_out + connect \logical_op__invert_out$13 \input_logical_op__invert_out$33 + connect \logical_op__is_32bit \input_logical_op__is_32bit + connect \logical_op__is_32bit$16 \input_logical_op__is_32bit$36 + connect \logical_op__is_signed \input_logical_op__is_signed + connect \logical_op__is_signed$17 \input_logical_op__is_signed$37 + connect \logical_op__oe__oe \input_logical_op__oe__oe + connect \logical_op__oe__oe$8 \input_logical_op__oe__oe$28 + connect \logical_op__oe__ok \input_logical_op__oe__ok + connect \logical_op__oe__ok$9 \input_logical_op__oe__ok$29 + connect \logical_op__output_carry \input_logical_op__output_carry + connect \logical_op__output_carry$15 \input_logical_op__output_carry$35 + connect \logical_op__rc__ok \input_logical_op__rc__ok + connect \logical_op__rc__ok$7 \input_logical_op__rc__ok$27 + connect \logical_op__rc__rc \input_logical_op__rc__rc + connect \logical_op__rc__rc$6 \input_logical_op__rc__rc$26 + connect \logical_op__write_cr0 \input_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \input_logical_op__write_cr0$34 + connect \logical_op__zero_a \input_logical_op__zero_a + connect \logical_op__zero_a$11 \input_logical_op__zero_a$31 + connect \muxid \input_muxid + connect \muxid$1 \input_muxid$21 + connect \ra \input_ra + connect \ra$20 \input_ra$40 + connect \rb \input_rb + connect \rb$21 \input_rb$41 + connect \xer_so \input_xer_so + connect \xer_so$22 \input_xer_so$42 end attribute \module_not_derived 1 - attribute \src "libresoc.v:44782.8-44794.4" - cell \_fsm \_fsm - connect \TAP_bus__tck \TAP_bus__tck - connect \TAP_bus__tms \TAP_bus__tms - connect \capture \_fsm_capture - connect \isdr \_fsm_isdr - connect \isir \_fsm_isir - connect \negjtag_clk \negjtag_clk - connect \negjtag_rst \negjtag_rst - connect \posjtag_clk \posjtag_clk - connect \posjtag_rst \posjtag_rst - connect \shift \_fsm_shift - connect \update \_fsm_update + attribute \src "libresoc.v:133926.13-133971.4" + cell \main$51 \main + connect \logical_op__data_len \main_logical_op__data_len + connect \logical_op__data_len$18 \main_logical_op__data_len$60 + connect \logical_op__fn_unit \main_logical_op__fn_unit + connect \logical_op__fn_unit$3 \main_logical_op__fn_unit$45 + connect \logical_op__imm_data__data \main_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \main_logical_op__imm_data__data$46 + connect \logical_op__imm_data__ok \main_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \main_logical_op__imm_data__ok$47 + connect \logical_op__input_carry \main_logical_op__input_carry + connect \logical_op__input_carry$12 \main_logical_op__input_carry$54 + connect \logical_op__insn \main_logical_op__insn + connect \logical_op__insn$19 \main_logical_op__insn$61 + connect \logical_op__insn_type \main_logical_op__insn_type + connect \logical_op__insn_type$2 \main_logical_op__insn_type$44 + connect \logical_op__invert_in \main_logical_op__invert_in + connect \logical_op__invert_in$10 \main_logical_op__invert_in$52 + connect \logical_op__invert_out \main_logical_op__invert_out + connect \logical_op__invert_out$13 \main_logical_op__invert_out$55 + connect \logical_op__is_32bit \main_logical_op__is_32bit + connect \logical_op__is_32bit$16 \main_logical_op__is_32bit$58 + connect \logical_op__is_signed \main_logical_op__is_signed + connect \logical_op__is_signed$17 \main_logical_op__is_signed$59 + connect \logical_op__oe__oe \main_logical_op__oe__oe + connect \logical_op__oe__oe$8 \main_logical_op__oe__oe$50 + connect \logical_op__oe__ok \main_logical_op__oe__ok + connect \logical_op__oe__ok$9 \main_logical_op__oe__ok$51 + connect \logical_op__output_carry \main_logical_op__output_carry + connect \logical_op__output_carry$15 \main_logical_op__output_carry$57 + connect \logical_op__rc__ok \main_logical_op__rc__ok + connect \logical_op__rc__ok$7 \main_logical_op__rc__ok$49 + connect \logical_op__rc__rc \main_logical_op__rc__rc + connect \logical_op__rc__rc$6 \main_logical_op__rc__rc$48 + connect \logical_op__write_cr0 \main_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \main_logical_op__write_cr0$56 + connect \logical_op__zero_a \main_logical_op__zero_a + connect \logical_op__zero_a$11 \main_logical_op__zero_a$53 + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$43 + connect \o \main_o + connect \o_ok \main_o_ok + connect \ra \main_ra + connect \rb \main_rb + connect \xer_so \main_xer_so + connect \xer_so$20 \main_xer_so$62 end attribute \module_not_derived 1 - attribute \src "libresoc.v:44795.12-44805.4" - cell \_idblock \_idblock - connect \TAP_bus__tdi \TAP_bus__tdi - connect \TAP_id_tdo \_idblock_TAP_id_tdo - connect \capture \_fsm_capture - connect \id_bypass \_idblock_id_bypass - connect \posjtag_clk \posjtag_clk - connect \posjtag_rst \posjtag_rst - connect \select_id \_idblock_select_id - connect \shift \_fsm_shift - connect \update \_fsm_update + attribute \src "libresoc.v:133972.10-133975.4" + cell \n$49 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:44806.12-44816.4" - cell \_irblock \_irblock - connect \TAP_bus__tdi \TAP_bus__tdi - connect \capture \_fsm_capture - connect \ir \_irblock_ir - connect \isir \_fsm_isir - connect \posjtag_clk \posjtag_clk - connect \posjtag_rst \posjtag_rst - connect \shift \_fsm_shift - connect \tdo \_irblock_tdo - connect \update \_fsm_update + attribute \src "libresoc.v:133976.10-133979.4" + cell \p$48 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:43025.7-43025.20" - process $proc$libresoc.v:43025$1520 + attribute \src "libresoc.v:132764.7-132764.20" + process $proc$libresoc.v:132764$6584 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:43583.13-43583.32" - process $proc$libresoc.v:43583$1521 - assign { } { } - assign $1\dmi0__addr_i[3:0] 4'0000 - sync always - sync init - update \dmi0__addr_i $1\dmi0__addr_i[3:0] - end - attribute \src "libresoc.v:43588.14-43588.46" - process $proc$libresoc.v:43588$1522 - assign { } { } - assign $1\dmi0__din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \dmi0__din $1\dmi0__din[63:0] - end - attribute \src "libresoc.v:43602.7-43602.29" - process $proc$libresoc.v:43602$1523 - assign { } { } - assign $1\dmi0_addrsr__oe[0:0] 1'0 - sync always - sync init - update \dmi0_addrsr__oe $1\dmi0_addrsr__oe[0:0] - end - attribute \src "libresoc.v:43610.13-43610.36" - process $proc$libresoc.v:43610$1524 - assign { } { } - assign $1\dmi0_addrsr_reg[7:0] 8'00000000 - sync always - sync init - update \dmi0_addrsr_reg $1\dmi0_addrsr_reg[7:0] - end - attribute \src "libresoc.v:43618.7-43618.37" - process $proc$libresoc.v:43618$1525 - assign { } { } - assign $1\dmi0_addrsr_update_core[0:0] 1'0 - sync always - sync init - update \dmi0_addrsr_update_core $1\dmi0_addrsr_update_core[0:0] - end - attribute \src "libresoc.v:43622.7-43622.42" - process $proc$libresoc.v:43622$1526 - assign { } { } - assign $1\dmi0_addrsr_update_core_prev[0:0] 1'0 - sync always - sync init - update \dmi0_addrsr_update_core_prev $1\dmi0_addrsr_update_core_prev[0:0] - end - attribute \src "libresoc.v:43626.14-43626.51" - process $proc$libresoc.v:43626$1527 - assign { } { } - assign $1\dmi0_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \dmi0_datasr__i $1\dmi0_datasr__i[63:0] - end - attribute \src "libresoc.v:43632.13-43632.35" - process $proc$libresoc.v:43632$1528 - assign { } { } - assign $1\dmi0_datasr__oe[1:0] 2'00 - sync always - sync init - update \dmi0_datasr__oe $1\dmi0_datasr__oe[1:0] - end - attribute \src "libresoc.v:43640.14-43640.52" - process $proc$libresoc.v:43640$1529 - assign { } { } - assign $1\dmi0_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \dmi0_datasr_reg $1\dmi0_datasr_reg[63:0] - end - attribute \src "libresoc.v:43648.7-43648.37" - process $proc$libresoc.v:43648$1530 - assign { } { } - assign $1\dmi0_datasr_update_core[0:0] 1'0 - sync always - sync init - update \dmi0_datasr_update_core $1\dmi0_datasr_update_core[0:0] - end - attribute \src "libresoc.v:43652.7-43652.42" - process $proc$libresoc.v:43652$1531 + attribute \src "libresoc.v:132773.13-132773.24" + process $proc$libresoc.v:132773$6585 assign { } { } - assign $1\dmi0_datasr_update_core_prev[0:0] 1'0 + assign $1\cr_a[3:0] 4'0000 sync always sync init - update \dmi0_datasr_update_core_prev $1\dmi0_datasr_update_core_prev[0:0] + update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:43668.13-43668.29" - process $proc$libresoc.v:43668$1532 + attribute \src "libresoc.v:132782.7-132782.21" + process $proc$libresoc.v:132782$6586 assign { } { } - assign $1\fsm_state[2:0] 3'000 + assign $1\cr_a_ok[0:0] 1'0 sync always sync init - update \fsm_state $1\fsm_state[2:0] + update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:43670.13-43670.35" - process $proc$libresoc.v:43670$1533 + attribute \src "libresoc.v:133061.13-133061.40" + process $proc$libresoc.v:133061$6587 assign { } { } - assign $0\fsm_state$503[2:0]$1534 3'000 + assign $1\logical_op__data_len[3:0] 4'0000 sync always sync init - update \fsm_state$503 $0\fsm_state$503[2:0]$1534 + update \logical_op__data_len $1\logical_op__data_len[3:0] end - attribute \src "libresoc.v:43868.15-43868.67" - process $proc$libresoc.v:43868$1535 + attribute \src "libresoc.v:133083.14-133083.43" + process $proc$libresoc.v:133083$6588 assign { } { } - assign $1\io_bd[153:0] 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\logical_op__fn_unit[11:0] 12'000000000000 sync always sync init - update \io_bd $1\io_bd[153:0] + update \logical_op__fn_unit $1\logical_op__fn_unit[11:0] end - attribute \src "libresoc.v:43880.15-43880.67" - process $proc$libresoc.v:43880$1536 + attribute \src "libresoc.v:133118.14-133118.63" + process $proc$libresoc.v:133118$6589 assign { } { } - assign $1\io_sr[153:0] 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \io_sr $1\io_sr[153:0] + update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:43889.14-43889.41" - process $proc$libresoc.v:43889$1537 + attribute \src "libresoc.v:133127.7-133127.38" + process $proc$libresoc.v:133127$6590 assign { } { } - assign $1\jtag_wb__adr[28:0] 29'00000000000000000000000000000 + assign $1\logical_op__imm_data__ok[0:0] 1'0 sync always sync init - update \jtag_wb__adr $1\jtag_wb__adr[28:0] + update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:43898.14-43898.51" - process $proc$libresoc.v:43898$1538 + attribute \src "libresoc.v:133140.13-133140.43" + process $proc$libresoc.v:133140$6591 assign { } { } - assign $1\jtag_wb__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\logical_op__input_carry[1:0] 2'00 sync always sync init - update \jtag_wb__dat_w $1\jtag_wb__dat_w[63:0] + update \logical_op__input_carry $1\logical_op__input_carry[1:0] end - attribute \src "libresoc.v:43912.7-43912.32" - process $proc$libresoc.v:43912$1539 + attribute \src "libresoc.v:133157.14-133157.38" + process $proc$libresoc.v:133157$6592 assign { } { } - assign $1\jtag_wb_addrsr__oe[0:0] 1'0 + assign $1\logical_op__insn[31:0] 0 sync always sync init - update \jtag_wb_addrsr__oe $1\jtag_wb_addrsr__oe[0:0] + update \logical_op__insn $1\logical_op__insn[31:0] end - attribute \src "libresoc.v:43920.14-43920.47" - process $proc$libresoc.v:43920$1540 + attribute \src "libresoc.v:133240.13-133240.42" + process $proc$libresoc.v:133240$6593 assign { } { } - assign $1\jtag_wb_addrsr_reg[28:0] 29'00000000000000000000000000000 + assign $1\logical_op__insn_type[6:0] 7'0000000 sync always sync init - update \jtag_wb_addrsr_reg $1\jtag_wb_addrsr_reg[28:0] + update \logical_op__insn_type $1\logical_op__insn_type[6:0] end - attribute \src "libresoc.v:43928.7-43928.40" - process $proc$libresoc.v:43928$1541 + attribute \src "libresoc.v:133397.7-133397.35" + process $proc$libresoc.v:133397$6594 assign { } { } - assign $1\jtag_wb_addrsr_update_core[0:0] 1'0 + assign $1\logical_op__invert_in[0:0] 1'0 sync always sync init - update \jtag_wb_addrsr_update_core $1\jtag_wb_addrsr_update_core[0:0] + update \logical_op__invert_in $1\logical_op__invert_in[0:0] end - attribute \src "libresoc.v:43932.7-43932.45" - process $proc$libresoc.v:43932$1542 + attribute \src "libresoc.v:133406.7-133406.36" + process $proc$libresoc.v:133406$6595 assign { } { } - assign $1\jtag_wb_addrsr_update_core_prev[0:0] 1'0 + assign $1\logical_op__invert_out[0:0] 1'0 sync always sync init - update \jtag_wb_addrsr_update_core_prev $1\jtag_wb_addrsr_update_core_prev[0:0] + update \logical_op__invert_out $1\logical_op__invert_out[0:0] end - attribute \src "libresoc.v:43936.14-43936.54" - process $proc$libresoc.v:43936$1543 + attribute \src "libresoc.v:133415.7-133415.34" + process $proc$libresoc.v:133415$6596 assign { } { } - assign $1\jtag_wb_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\logical_op__is_32bit[0:0] 1'0 sync always sync init - update \jtag_wb_datasr__i $1\jtag_wb_datasr__i[63:0] + update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:43942.13-43942.38" - process $proc$libresoc.v:43942$1544 + attribute \src "libresoc.v:133424.7-133424.35" + process $proc$libresoc.v:133424$6597 assign { } { } - assign $1\jtag_wb_datasr__oe[1:0] 2'00 + assign $1\logical_op__is_signed[0:0] 1'0 sync always sync init - update \jtag_wb_datasr__oe $1\jtag_wb_datasr__oe[1:0] + update \logical_op__is_signed $1\logical_op__is_signed[0:0] end - attribute \src "libresoc.v:43950.14-43950.55" - process $proc$libresoc.v:43950$1545 + attribute \src "libresoc.v:133433.7-133433.32" + process $proc$libresoc.v:133433$6598 assign { } { } - assign $1\jtag_wb_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\logical_op__oe__oe[0:0] 1'0 sync always sync init - update \jtag_wb_datasr_reg $1\jtag_wb_datasr_reg[63:0] + update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:43958.7-43958.40" - process $proc$libresoc.v:43958$1546 + attribute \src "libresoc.v:133442.7-133442.32" + process $proc$libresoc.v:133442$6599 assign { } { } - assign $1\jtag_wb_datasr_update_core[0:0] 1'0 + assign $1\logical_op__oe__ok[0:0] 1'0 sync always sync init - update \jtag_wb_datasr_update_core $1\jtag_wb_datasr_update_core[0:0] + update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:43962.7-43962.45" - process $proc$libresoc.v:43962$1547 + attribute \src "libresoc.v:133451.7-133451.38" + process $proc$libresoc.v:133451$6600 assign { } { } - assign $1\jtag_wb_datasr_update_core_prev[0:0] 1'0 + assign $1\logical_op__output_carry[0:0] 1'0 sync always sync init - update \jtag_wb_datasr_update_core_prev $1\jtag_wb_datasr_update_core_prev[0:0] + update \logical_op__output_carry $1\logical_op__output_carry[0:0] end - attribute \src "libresoc.v:44392.7-44392.21" - process $proc$libresoc.v:44392$1548 + attribute \src "libresoc.v:133460.7-133460.32" + process $proc$libresoc.v:133460$6601 assign { } { } - assign $1\sr0__oe[0:0] 1'0 + assign $1\logical_op__rc__ok[0:0] 1'0 sync always sync init - update \sr0__oe $1\sr0__oe[0:0] + update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:44400.13-44400.27" - process $proc$libresoc.v:44400$1549 + attribute \src "libresoc.v:133469.7-133469.32" + process $proc$libresoc.v:133469$6602 assign { } { } - assign $1\sr0_reg[2:0] 3'000 + assign $1\logical_op__rc__rc[0:0] 1'0 sync always sync init - update \sr0_reg $1\sr0_reg[2:0] + update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:44408.7-44408.29" - process $proc$libresoc.v:44408$1550 + attribute \src "libresoc.v:133478.7-133478.35" + process $proc$libresoc.v:133478$6603 assign { } { } - assign $1\sr0_update_core[0:0] 1'0 + assign $1\logical_op__write_cr0[0:0] 1'0 sync always sync init - update \sr0_update_core $1\sr0_update_core[0:0] + update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:44412.7-44412.34" - process $proc$libresoc.v:44412$1551 + attribute \src "libresoc.v:133487.7-133487.32" + process $proc$libresoc.v:133487$6604 assign { } { } - assign $1\sr0_update_core_prev[0:0] 1'0 + assign $1\logical_op__zero_a[0:0] 1'0 sync always sync init - update \sr0_update_core_prev $1\sr0_update_core_prev[0:0] + update \logical_op__zero_a $1\logical_op__zero_a[0:0] end - attribute \src "libresoc.v:44422.7-44422.21" - process $proc$libresoc.v:44422$1552 + attribute \src "libresoc.v:133766.13-133766.25" + process $proc$libresoc.v:133766$6605 assign { } { } - assign $1\sr5__oe[0:0] 1'0 + assign $1\muxid[1:0] 2'00 sync always sync init - update \sr5__oe $1\sr5__oe[0:0] + update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:44430.13-44430.27" - process $proc$libresoc.v:44430$1553 + attribute \src "libresoc.v:133781.14-133781.38" + process $proc$libresoc.v:133781$6606 assign { } { } - assign $1\sr5_reg[1:0] 2'00 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \sr5_reg $1\sr5_reg[1:0] + update \o $1\o[63:0] end - attribute \src "libresoc.v:44438.7-44438.29" - process $proc$libresoc.v:44438$1554 + attribute \src "libresoc.v:133788.7-133788.18" + process $proc$libresoc.v:133788$6607 assign { } { } - assign $1\sr5_update_core[0:0] 1'0 + assign $1\o_ok[0:0] 1'0 sync always sync init - update \sr5_update_core $1\sr5_update_core[0:0] + update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:44442.7-44442.34" - process $proc$libresoc.v:44442$1555 + attribute \src "libresoc.v:133802.7-133802.20" + process $proc$libresoc.v:133802$6608 assign { } { } - assign $1\sr5_update_core_prev[0:0] 1'0 + assign $1\r_busy[0:0] 1'0 sync always sync init - update \sr5_update_core_prev $1\sr5_update_core_prev[0:0] + update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:44446.7-44446.26" - process $proc$libresoc.v:44446$1556 + attribute \src "libresoc.v:133811.7-133811.20" + process $proc$libresoc.v:133811$6609 assign { } { } - assign $1\wb_dcache_en[0:0] 1'1 + assign $1\xer_so[0:0] 1'0 sync always sync init - update \wb_dcache_en $1\wb_dcache_en[0:0] + update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:44451.7-44451.26" - process $proc$libresoc.v:44451$1557 + attribute \src "libresoc.v:133820.7-133820.23" + process $proc$libresoc.v:133820$6610 assign { } { } - assign $1\wb_icache_en[0:0] 1'1 + assign $1\xer_so_ok[0:0] 1'0 sync always sync init - update \wb_icache_en $1\wb_icache_en[0:0] - end - attribute \src "libresoc.v:44710.3-44711.41" - process $proc$libresoc.v:44710$1329 - assign { } { } - assign $0\wb_icache_en[0:0] \wb_icache_en$next - sync posedge \clk - update \wb_icache_en $0\wb_icache_en[0:0] - end - attribute \src "libresoc.v:44712.3-44713.41" - process $proc$libresoc.v:44712$1330 - assign { } { } - assign $0\wb_dcache_en[0:0] \wb_dcache_en$next - sync posedge \clk - update \wb_dcache_en $0\wb_dcache_en[0:0] - end - attribute \src "libresoc.v:44714.3-44715.45" - process $proc$libresoc.v:44714$1331 - assign { } { } - assign $0\dmi0_datasr__i[63:0] \dmi0_datasr__i$next - sync posedge \clk - update \dmi0_datasr__i $0\dmi0_datasr__i[63:0] - end - attribute \src "libresoc.v:44716.3-44717.35" - process $proc$libresoc.v:44716$1332 - assign { } { } - assign $0\dmi0__din[63:0] \dmi0__din$next - sync posedge \clk - update \dmi0__din $0\dmi0__din[63:0] - end - attribute \src "libresoc.v:44718.3-44719.45" - process $proc$libresoc.v:44718$1333 - assign { } { } - assign $0\fsm_state$503[2:0]$1334 \fsm_state$503$next - sync posedge \clk - update \fsm_state$503 $0\fsm_state$503[2:0]$1334 - end - attribute \src "libresoc.v:44720.3-44721.41" - process $proc$libresoc.v:44720$1335 - assign { } { } - assign $0\dmi0__addr_i[3:0] \dmi0__addr_i$next - sync posedge \clk - update \dmi0__addr_i $0\dmi0__addr_i[3:0] - end - attribute \src "libresoc.v:44722.3-44723.51" - process $proc$libresoc.v:44722$1336 - assign { } { } - assign $0\jtag_wb_datasr__i[63:0] \jtag_wb_datasr__i$next - sync posedge \clk - update \jtag_wb_datasr__i $0\jtag_wb_datasr__i[63:0] - end - attribute \src "libresoc.v:44724.3-44725.45" - process $proc$libresoc.v:44724$1337 - assign { } { } - assign $0\jtag_wb__dat_w[63:0] \jtag_wb__dat_w$next - sync posedge \clk - update \jtag_wb__dat_w $0\jtag_wb__dat_w[63:0] + update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:44726.3-44727.35" - process $proc$libresoc.v:44726$1338 + attribute \src "libresoc.v:133828.3-133829.29" + process $proc$libresoc.v:133828$6490 assign { } { } - assign $0\fsm_state[2:0] \fsm_state$next - sync posedge \clk - update \fsm_state $0\fsm_state[2:0] - end - attribute \src "libresoc.v:44728.3-44729.41" - process $proc$libresoc.v:44728$1339 - assign { } { } - assign $0\jtag_wb__adr[28:0] \jtag_wb__adr$next - sync posedge \clk - update \jtag_wb__adr $0\jtag_wb__adr[28:0] + assign $0\xer_so[0:0] \xer_so$next + sync posedge \coresync_clk + update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:44730.3-44731.31" - process $proc$libresoc.v:44730$1340 + attribute \src "libresoc.v:133830.3-133831.35" + process $proc$libresoc.v:133830$6491 assign { } { } - assign $0\sr5_reg[1:0] \sr5_reg$next - sync posedge \posjtag_clk - update \sr5_reg $0\sr5_reg[1:0] + assign $0\xer_so_ok[0:0] \xer_so_ok$next + sync posedge \coresync_clk + update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:44732.3-44733.31" - process $proc$libresoc.v:44732$1341 + attribute \src "libresoc.v:133832.3-133833.25" + process $proc$libresoc.v:133832$6492 assign { } { } - assign $0\sr5__oe[0:0] \sr5__oe$next - sync posedge \clk - update \sr5__oe $0\sr5__oe[0:0] + assign $0\cr_a[3:0] \cr_a$next + sync posedge \coresync_clk + update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:44734.3-44735.57" - process $proc$libresoc.v:44734$1342 + attribute \src "libresoc.v:133834.3-133835.31" + process $proc$libresoc.v:133834$6493 assign { } { } - assign $0\sr5_update_core_prev[0:0] \sr5_update_core_prev$next - sync posedge \clk - update \sr5_update_core_prev $0\sr5_update_core_prev[0:0] + assign $0\cr_a_ok[0:0] \cr_a_ok$next + sync posedge \coresync_clk + update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:44736.3-44737.47" - process $proc$libresoc.v:44736$1343 + attribute \src "libresoc.v:133836.3-133837.19" + process $proc$libresoc.v:133836$6494 assign { } { } - assign $0\sr5_update_core[0:0] \sr5_update_core$next - sync posedge \clk - update \sr5_update_core $0\sr5_update_core[0:0] + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] end - attribute \src "libresoc.v:44738.3-44739.47" - process $proc$libresoc.v:44738$1344 + attribute \src "libresoc.v:133838.3-133839.25" + process $proc$libresoc.v:133838$6495 assign { } { } - assign $0\dmi0_datasr_reg[63:0] \dmi0_datasr_reg$next - sync posedge \posjtag_clk - update \dmi0_datasr_reg $0\dmi0_datasr_reg[63:0] + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:44740.3-44741.47" - process $proc$libresoc.v:44740$1345 + attribute \src "libresoc.v:133840.3-133841.59" + process $proc$libresoc.v:133840$6496 assign { } { } - assign $0\dmi0_datasr__oe[1:0] \dmi0_datasr__oe$next - sync posedge \clk - update \dmi0_datasr__oe $0\dmi0_datasr__oe[1:0] + assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next + sync posedge \coresync_clk + update \logical_op__insn_type $0\logical_op__insn_type[6:0] end - attribute \src "libresoc.v:44742.3-44743.73" - process $proc$libresoc.v:44742$1346 + attribute \src "libresoc.v:133842.3-133843.55" + process $proc$libresoc.v:133842$6497 assign { } { } - assign $0\dmi0_datasr_update_core_prev[0:0] \dmi0_datasr_update_core_prev$next - sync posedge \clk - update \dmi0_datasr_update_core_prev $0\dmi0_datasr_update_core_prev[0:0] + assign $0\logical_op__fn_unit[11:0] \logical_op__fn_unit$next + sync posedge \coresync_clk + update \logical_op__fn_unit $0\logical_op__fn_unit[11:0] end - attribute \src "libresoc.v:44744.3-44745.63" - process $proc$libresoc.v:44744$1347 + attribute \src "libresoc.v:133844.3-133845.69" + process $proc$libresoc.v:133844$6498 assign { } { } - assign $0\dmi0_datasr_update_core[0:0] \dmi0_datasr_update_core$next - sync posedge \clk - update \dmi0_datasr_update_core $0\dmi0_datasr_update_core[0:0] + assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next + sync posedge \coresync_clk + update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:44746.3-44747.47" - process $proc$libresoc.v:44746$1348 + attribute \src "libresoc.v:133846.3-133847.65" + process $proc$libresoc.v:133846$6499 assign { } { } - assign $0\dmi0_addrsr_reg[7:0] \dmi0_addrsr_reg$next - sync posedge \posjtag_clk - update \dmi0_addrsr_reg $0\dmi0_addrsr_reg[7:0] + assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next + sync posedge \coresync_clk + update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:44748.3-44749.47" - process $proc$libresoc.v:44748$1349 + attribute \src "libresoc.v:133848.3-133849.53" + process $proc$libresoc.v:133848$6500 assign { } { } - assign $0\dmi0_addrsr__oe[0:0] \dmi0_addrsr__oe$next - sync posedge \clk - update \dmi0_addrsr__oe $0\dmi0_addrsr__oe[0:0] + assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next + sync posedge \coresync_clk + update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:44750.3-44751.73" - process $proc$libresoc.v:44750$1350 + attribute \src "libresoc.v:133850.3-133851.53" + process $proc$libresoc.v:133850$6501 assign { } { } - assign $0\dmi0_addrsr_update_core_prev[0:0] \dmi0_addrsr_update_core_prev$next - sync posedge \clk - update \dmi0_addrsr_update_core_prev $0\dmi0_addrsr_update_core_prev[0:0] + assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next + sync posedge \coresync_clk + update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:44752.3-44753.63" - process $proc$libresoc.v:44752$1351 + attribute \src "libresoc.v:133852.3-133853.53" + process $proc$libresoc.v:133852$6502 assign { } { } - assign $0\dmi0_addrsr_update_core[0:0] \dmi0_addrsr_update_core$next - sync posedge \clk - update \dmi0_addrsr_update_core $0\dmi0_addrsr_update_core[0:0] + assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next + sync posedge \coresync_clk + update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:44754.3-44755.53" - process $proc$libresoc.v:44754$1352 + attribute \src "libresoc.v:133854.3-133855.53" + process $proc$libresoc.v:133854$6503 assign { } { } - assign $0\jtag_wb_datasr_reg[63:0] \jtag_wb_datasr_reg$next - sync posedge \posjtag_clk - update \jtag_wb_datasr_reg $0\jtag_wb_datasr_reg[63:0] + assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next + sync posedge \coresync_clk + update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:44756.3-44757.53" - process $proc$libresoc.v:44756$1353 + attribute \src "libresoc.v:133856.3-133857.59" + process $proc$libresoc.v:133856$6504 assign { } { } - assign $0\jtag_wb_datasr__oe[1:0] \jtag_wb_datasr__oe$next - sync posedge \clk - update \jtag_wb_datasr__oe $0\jtag_wb_datasr__oe[1:0] + assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next + sync posedge \coresync_clk + update \logical_op__invert_in $0\logical_op__invert_in[0:0] end - attribute \src "libresoc.v:44758.3-44759.79" - process $proc$libresoc.v:44758$1354 + attribute \src "libresoc.v:133858.3-133859.53" + process $proc$libresoc.v:133858$6505 assign { } { } - assign $0\jtag_wb_datasr_update_core_prev[0:0] \jtag_wb_datasr_update_core_prev$next - sync posedge \clk - update \jtag_wb_datasr_update_core_prev $0\jtag_wb_datasr_update_core_prev[0:0] + assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next + sync posedge \coresync_clk + update \logical_op__zero_a $0\logical_op__zero_a[0:0] end - attribute \src "libresoc.v:44760.3-44761.69" - process $proc$libresoc.v:44760$1355 + attribute \src "libresoc.v:133860.3-133861.63" + process $proc$libresoc.v:133860$6506 assign { } { } - assign $0\jtag_wb_datasr_update_core[0:0] \jtag_wb_datasr_update_core$next - sync posedge \clk - update \jtag_wb_datasr_update_core $0\jtag_wb_datasr_update_core[0:0] + assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next + sync posedge \coresync_clk + update \logical_op__input_carry $0\logical_op__input_carry[1:0] end - attribute \src "libresoc.v:44762.3-44763.53" - process $proc$libresoc.v:44762$1356 + attribute \src "libresoc.v:133862.3-133863.61" + process $proc$libresoc.v:133862$6507 assign { } { } - assign $0\jtag_wb_addrsr_reg[28:0] \jtag_wb_addrsr_reg$next - sync posedge \posjtag_clk - update \jtag_wb_addrsr_reg $0\jtag_wb_addrsr_reg[28:0] + assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next + sync posedge \coresync_clk + update \logical_op__invert_out $0\logical_op__invert_out[0:0] end - attribute \src "libresoc.v:44764.3-44765.53" - process $proc$libresoc.v:44764$1357 + attribute \src "libresoc.v:133864.3-133865.59" + process $proc$libresoc.v:133864$6508 assign { } { } - assign $0\jtag_wb_addrsr__oe[0:0] \jtag_wb_addrsr__oe$next - sync posedge \clk - update \jtag_wb_addrsr__oe $0\jtag_wb_addrsr__oe[0:0] + assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next + sync posedge \coresync_clk + update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:44766.3-44767.79" - process $proc$libresoc.v:44766$1358 + attribute \src "libresoc.v:133866.3-133867.65" + process $proc$libresoc.v:133866$6509 assign { } { } - assign $0\jtag_wb_addrsr_update_core_prev[0:0] \jtag_wb_addrsr_update_core_prev$next - sync posedge \clk - update \jtag_wb_addrsr_update_core_prev $0\jtag_wb_addrsr_update_core_prev[0:0] + assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next + sync posedge \coresync_clk + update \logical_op__output_carry $0\logical_op__output_carry[0:0] end - attribute \src "libresoc.v:44768.3-44769.69" - process $proc$libresoc.v:44768$1359 + attribute \src "libresoc.v:133868.3-133869.57" + process $proc$libresoc.v:133868$6510 assign { } { } - assign $0\jtag_wb_addrsr_update_core[0:0] \jtag_wb_addrsr_update_core$next - sync posedge \clk - update \jtag_wb_addrsr_update_core $0\jtag_wb_addrsr_update_core[0:0] + assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next + sync posedge \coresync_clk + update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:44770.3-44771.31" - process $proc$libresoc.v:44770$1360 + attribute \src "libresoc.v:133870.3-133871.59" + process $proc$libresoc.v:133870$6511 assign { } { } - assign $0\sr0_reg[2:0] \sr0_reg$next - sync posedge \posjtag_clk - update \sr0_reg $0\sr0_reg[2:0] + assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next + sync posedge \coresync_clk + update \logical_op__is_signed $0\logical_op__is_signed[0:0] end - attribute \src "libresoc.v:44772.3-44773.31" - process $proc$libresoc.v:44772$1361 + attribute \src "libresoc.v:133872.3-133873.57" + process $proc$libresoc.v:133872$6512 assign { } { } - assign $0\sr0__oe[0:0] \sr0__oe$next - sync posedge \clk - update \sr0__oe $0\sr0__oe[0:0] + assign $0\logical_op__data_len[3:0] \logical_op__data_len$next + sync posedge \coresync_clk + update \logical_op__data_len $0\logical_op__data_len[3:0] end - attribute \src "libresoc.v:44774.3-44775.57" - process $proc$libresoc.v:44774$1362 + attribute \src "libresoc.v:133874.3-133875.49" + process $proc$libresoc.v:133874$6513 assign { } { } - assign $0\sr0_update_core_prev[0:0] \sr0_update_core_prev$next - sync posedge \clk - update \sr0_update_core_prev $0\sr0_update_core_prev[0:0] + assign $0\logical_op__insn[31:0] \logical_op__insn$next + sync posedge \coresync_clk + update \logical_op__insn $0\logical_op__insn[31:0] end - attribute \src "libresoc.v:44776.3-44777.47" - process $proc$libresoc.v:44776$1363 + attribute \src "libresoc.v:133876.3-133877.27" + process $proc$libresoc.v:133876$6514 assign { } { } - assign $0\sr0_update_core[0:0] \sr0_update_core$next - sync posedge \clk - update \sr0_update_core $0\sr0_update_core[0:0] + assign $0\muxid[1:0] \muxid$next + sync posedge \coresync_clk + update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:44778.3-44779.27" - process $proc$libresoc.v:44778$1364 + attribute \src "libresoc.v:133878.3-133879.29" + process $proc$libresoc.v:133878$6515 assign { } { } - assign $0\io_bd[153:0] \io_bd$next - sync negedge \negjtag_clk - update \io_bd $0\io_bd[153:0] + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:44780.3-44781.27" - process $proc$libresoc.v:44780$1365 + attribute \src "libresoc.v:133980.3-133997.6" + process $proc$libresoc.v:133980$6516 assign { } { } - assign $0\io_sr[153:0] \io_sr$next - sync posedge \posjtag_clk - update \io_sr $0\io_sr[153:0] - end - attribute \src "libresoc.v:44817.3-44832.6" - process $proc$libresoc.v:44817$1366 assign { } { } assign { } { } - assign $0\TAP_tdo[0:0] $1\TAP_tdo[0:0] - attribute \src "libresoc.v:44818.5-44818.29" + assign $0\r_busy$next[0:0]$6517 $2\r_busy$next[0:0]$6519 + attribute \src "libresoc.v:133981.5-133981.29" switch \initial - attribute \src "libresoc.v:44818.9-44818.17" + attribute \src "libresoc.v:133981.9-133981.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:415" - switch { \$369 \_idblock_select_id \_fsm_isir } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $1\TAP_tdo[0:0] \_irblock_tdo + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" - case 3'-1- + case 2'-1 assign { } { } - assign $1\TAP_tdo[0:0] \_idblock_TAP_id_tdo + assign $1\r_busy$next[0:0]$6518 1'1 attribute \src "libresoc.v:0.0-0.0" - case 3'1-- + case 2'1- assign { } { } - assign $1\TAP_tdo[0:0] \io_sr [153] - case - assign $1\TAP_tdo[0:0] 1'0 - end - sync always - update \TAP_tdo $0\TAP_tdo[0:0] - end - attribute \src "libresoc.v:44833.3-44841.6" - process $proc$libresoc.v:44833$1367 - assign { } { } - assign { } { } - assign $0\sr0_update_core$next[0:0]$1368 $1\sr0_update_core$next[0:0]$1369 - attribute \src "libresoc.v:44834.5-44834.29" - switch \initial - attribute \src "libresoc.v:44834.9-44834.17" - case 1'1 + assign $1\r_busy$next[0:0]$6518 1'0 case + assign $1\r_busy$next[0:0]$6518 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr0_update_core$next[0:0]$1369 1'0 + assign $2\r_busy$next[0:0]$6519 1'0 case - assign $1\sr0_update_core$next[0:0]$1369 \sr0_update + assign $2\r_busy$next[0:0]$6519 $1\r_busy$next[0:0]$6518 end sync always - update \sr0_update_core$next $0\sr0_update_core$next[0:0]$1368 + update \r_busy$next $0\r_busy$next[0:0]$6517 end - attribute \src "libresoc.v:44842.3-44850.6" - process $proc$libresoc.v:44842$1370 + attribute \src "libresoc.v:133998.3-134010.6" + process $proc$libresoc.v:133998$6520 assign { } { } assign { } { } - assign $0\sr0_update_core_prev$next[0:0]$1371 $1\sr0_update_core_prev$next[0:0]$1372 - attribute \src "libresoc.v:44843.5-44843.29" + assign $0\muxid$next[1:0]$6521 $1\muxid$next[1:0]$6522 + attribute \src "libresoc.v:133999.5-133999.29" switch \initial - attribute \src "libresoc.v:44843.9-44843.17" + attribute \src "libresoc.v:133999.9-133999.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 + assign { } { } + assign $1\muxid$next[1:0]$6522 \muxid$66 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- assign { } { } - assign $1\sr0_update_core_prev$next[0:0]$1372 1'0 + assign $1\muxid$next[1:0]$6522 \muxid$66 case - assign $1\sr0_update_core_prev$next[0:0]$1372 \sr0_update_core + assign $1\muxid$next[1:0]$6522 \muxid end sync always - update \sr0_update_core_prev$next $0\sr0_update_core_prev$next[0:0]$1371 + update \muxid$next $0\muxid$next[1:0]$6521 end - attribute \src "libresoc.v:44851.3-44867.6" - process $proc$libresoc.v:44851$1373 + attribute \src "libresoc.v:134011.3-134052.6" + process $proc$libresoc.v:134011$6523 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\logical_op__data_len$next[3:0]$6524 $1\logical_op__data_len$next[3:0]$6542 + assign $0\logical_op__fn_unit$next[11:0]$6525 $1\logical_op__fn_unit$next[11:0]$6543 + assign { } { } + assign { } { } + assign $0\logical_op__input_carry$next[1:0]$6528 $1\logical_op__input_carry$next[1:0]$6546 + assign $0\logical_op__insn$next[31:0]$6529 $1\logical_op__insn$next[31:0]$6547 + assign $0\logical_op__insn_type$next[6:0]$6530 $1\logical_op__insn_type$next[6:0]$6548 + assign $0\logical_op__invert_in$next[0:0]$6531 $1\logical_op__invert_in$next[0:0]$6549 + assign $0\logical_op__invert_out$next[0:0]$6532 $1\logical_op__invert_out$next[0:0]$6550 + assign $0\logical_op__is_32bit$next[0:0]$6533 $1\logical_op__is_32bit$next[0:0]$6551 + assign $0\logical_op__is_signed$next[0:0]$6534 $1\logical_op__is_signed$next[0:0]$6552 + assign { } { } assign { } { } + assign $0\logical_op__output_carry$next[0:0]$6537 $1\logical_op__output_carry$next[0:0]$6555 assign { } { } - assign $0\sr0__oe$next[0:0]$1374 $2\sr0__oe$next[0:0]$1376 - attribute \src "libresoc.v:44852.5-44852.29" + assign { } { } + assign $0\logical_op__write_cr0$next[0:0]$6540 $1\logical_op__write_cr0$next[0:0]$6558 + assign $0\logical_op__zero_a$next[0:0]$6541 $1\logical_op__zero_a$next[0:0]$6559 + assign $0\logical_op__imm_data__data$next[63:0]$6526 $2\logical_op__imm_data__data$next[63:0]$6560 + assign $0\logical_op__imm_data__ok$next[0:0]$6527 $2\logical_op__imm_data__ok$next[0:0]$6561 + assign $0\logical_op__oe__oe$next[0:0]$6535 $2\logical_op__oe__oe$next[0:0]$6562 + assign $0\logical_op__oe__ok$next[0:0]$6536 $2\logical_op__oe__ok$next[0:0]$6563 + assign $0\logical_op__rc__ok$next[0:0]$6538 $2\logical_op__rc__ok$next[0:0]$6564 + assign $0\logical_op__rc__rc$next[0:0]$6539 $2\logical_op__rc__rc$next[0:0]$6565 + attribute \src "libresoc.v:134012.5-134012.29" switch \initial - attribute \src "libresoc.v:44852.9-44852.17" + attribute \src "libresoc.v:134012.9-134012.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$387 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } assign { } { } - assign $1\sr0__oe$next[0:0]$1375 \sr0_isir + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$next[31:0]$6547 $1\logical_op__data_len$next[3:0]$6542 $1\logical_op__is_signed$next[0:0]$6552 $1\logical_op__is_32bit$next[0:0]$6551 $1\logical_op__output_carry$next[0:0]$6555 $1\logical_op__write_cr0$next[0:0]$6558 $1\logical_op__invert_out$next[0:0]$6550 $1\logical_op__input_carry$next[1:0]$6546 $1\logical_op__zero_a$next[0:0]$6559 $1\logical_op__invert_in$next[0:0]$6549 $1\logical_op__oe__ok$next[0:0]$6554 $1\logical_op__oe__oe$next[0:0]$6553 $1\logical_op__rc__ok$next[0:0]$6556 $1\logical_op__rc__rc$next[0:0]$6557 $1\logical_op__imm_data__ok$next[0:0]$6545 $1\logical_op__imm_data__data$next[63:0]$6544 $1\logical_op__fn_unit$next[11:0]$6543 $1\logical_op__insn_type$next[6:0]$6548 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } attribute \src "libresoc.v:0.0-0.0" - case + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } assign { } { } - assign $1\sr0__oe$next[0:0]$1375 1'0 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$next[31:0]$6547 $1\logical_op__data_len$next[3:0]$6542 $1\logical_op__is_signed$next[0:0]$6552 $1\logical_op__is_32bit$next[0:0]$6551 $1\logical_op__output_carry$next[0:0]$6555 $1\logical_op__write_cr0$next[0:0]$6558 $1\logical_op__invert_out$next[0:0]$6550 $1\logical_op__input_carry$next[1:0]$6546 $1\logical_op__zero_a$next[0:0]$6559 $1\logical_op__invert_in$next[0:0]$6549 $1\logical_op__oe__ok$next[0:0]$6554 $1\logical_op__oe__oe$next[0:0]$6553 $1\logical_op__rc__ok$next[0:0]$6556 $1\logical_op__rc__rc$next[0:0]$6557 $1\logical_op__imm_data__ok$next[0:0]$6545 $1\logical_op__imm_data__data$next[63:0]$6544 $1\logical_op__fn_unit$next[11:0]$6543 $1\logical_op__insn_type$next[6:0]$6548 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } + case + assign $1\logical_op__data_len$next[3:0]$6542 \logical_op__data_len + assign $1\logical_op__fn_unit$next[11:0]$6543 \logical_op__fn_unit + assign $1\logical_op__imm_data__data$next[63:0]$6544 \logical_op__imm_data__data + assign $1\logical_op__imm_data__ok$next[0:0]$6545 \logical_op__imm_data__ok + assign $1\logical_op__input_carry$next[1:0]$6546 \logical_op__input_carry + assign $1\logical_op__insn$next[31:0]$6547 \logical_op__insn + assign $1\logical_op__insn_type$next[6:0]$6548 \logical_op__insn_type + assign $1\logical_op__invert_in$next[0:0]$6549 \logical_op__invert_in + assign $1\logical_op__invert_out$next[0:0]$6550 \logical_op__invert_out + assign $1\logical_op__is_32bit$next[0:0]$6551 \logical_op__is_32bit + assign $1\logical_op__is_signed$next[0:0]$6552 \logical_op__is_signed + assign $1\logical_op__oe__oe$next[0:0]$6553 \logical_op__oe__oe + assign $1\logical_op__oe__ok$next[0:0]$6554 \logical_op__oe__ok + assign $1\logical_op__output_carry$next[0:0]$6555 \logical_op__output_carry + assign $1\logical_op__rc__ok$next[0:0]$6556 \logical_op__rc__ok + assign $1\logical_op__rc__rc$next[0:0]$6557 \logical_op__rc__rc + assign $1\logical_op__write_cr0$next[0:0]$6558 \logical_op__write_cr0 + assign $1\logical_op__zero_a$next[0:0]$6559 \logical_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sr0__oe$next[0:0]$1376 1'0 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\logical_op__imm_data__data$next[63:0]$6560 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$next[0:0]$6561 1'0 + assign $2\logical_op__rc__rc$next[0:0]$6565 1'0 + assign $2\logical_op__rc__ok$next[0:0]$6564 1'0 + assign $2\logical_op__oe__oe$next[0:0]$6562 1'0 + assign $2\logical_op__oe__ok$next[0:0]$6563 1'0 case - assign $2\sr0__oe$next[0:0]$1376 $1\sr0__oe$next[0:0]$1375 + assign $2\logical_op__imm_data__data$next[63:0]$6560 $1\logical_op__imm_data__data$next[63:0]$6544 + assign $2\logical_op__imm_data__ok$next[0:0]$6561 $1\logical_op__imm_data__ok$next[0:0]$6545 + assign $2\logical_op__oe__oe$next[0:0]$6562 $1\logical_op__oe__oe$next[0:0]$6553 + assign $2\logical_op__oe__ok$next[0:0]$6563 $1\logical_op__oe__ok$next[0:0]$6554 + assign $2\logical_op__rc__ok$next[0:0]$6564 $1\logical_op__rc__ok$next[0:0]$6556 + assign $2\logical_op__rc__rc$next[0:0]$6565 $1\logical_op__rc__rc$next[0:0]$6557 end sync always - update \sr0__oe$next $0\sr0__oe$next[0:0]$1374 + update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$6524 + update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[11:0]$6525 + update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$6526 + update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$6527 + update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$6528 + update \logical_op__insn$next $0\logical_op__insn$next[31:0]$6529 + update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$6530 + update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$6531 + update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$6532 + update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$6533 + update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$6534 + update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$6535 + update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$6536 + update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$6537 + update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$6538 + update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$6539 + update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$6540 + update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$6541 end - attribute \src "libresoc.v:44868.3-44888.6" - process $proc$libresoc.v:44868$1377 + attribute \src "libresoc.v:134053.3-134071.6" + process $proc$libresoc.v:134053$6566 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\sr0_reg$next[2:0]$1378 $3\sr0_reg$next[2:0]$1381 - attribute \src "libresoc.v:44869.5-44869.29" + assign $0\o$next[63:0]$6567 $1\o$next[63:0]$6569 + assign { } { } + assign $0\o_ok$next[0:0]$6568 $2\o_ok$next[0:0]$6571 + attribute \src "libresoc.v:134054.5-134054.29" switch \initial - attribute \src "libresoc.v:44869.9-44869.17" + attribute \src "libresoc.v:134054.9-134054.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" - switch \sr0_shift + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 assign { } { } - assign $1\sr0_reg$next[2:0]$1379 { \TAP_bus__tdi \sr0_reg [2:1] } - case - assign $1\sr0_reg$next[2:0]$1379 \sr0_reg - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" - switch \sr0_capture - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $2\sr0_reg$next[2:0]$1380 \sr0__i - case - assign $2\sr0_reg$next[2:0]$1380 $1\sr0_reg$next[2:0]$1379 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \posjtag_rst + assign { $1\o_ok$next[0:0]$6570 $1\o$next[63:0]$6569 } { \o_ok$86 \o$85 } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'1- assign { } { } - assign $3\sr0_reg$next[2:0]$1381 3'000 - case - assign $3\sr0_reg$next[2:0]$1381 $2\sr0_reg$next[2:0]$1380 - end - sync always - update \sr0_reg$next $0\sr0_reg$next[2:0]$1378 - end - attribute \src "libresoc.v:44889.3-44897.6" - process $proc$libresoc.v:44889$1382 - assign { } { } - assign { } { } - assign $0\jtag_wb_addrsr_update_core$next[0:0]$1383 $1\jtag_wb_addrsr_update_core$next[0:0]$1384 - attribute \src "libresoc.v:44890.5-44890.29" - switch \initial - attribute \src "libresoc.v:44890.9-44890.17" - case 1'1 + assign { } { } + assign { $1\o_ok$next[0:0]$6570 $1\o$next[63:0]$6569 } { \o_ok$86 \o$85 } case + assign $1\o$next[63:0]$6569 \o + assign $1\o_ok$next[0:0]$6570 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_addrsr_update_core$next[0:0]$1384 1'0 + assign $2\o_ok$next[0:0]$6571 1'0 case - assign $1\jtag_wb_addrsr_update_core$next[0:0]$1384 \jtag_wb_addrsr_update + assign $2\o_ok$next[0:0]$6571 $1\o_ok$next[0:0]$6570 end sync always - update \jtag_wb_addrsr_update_core$next $0\jtag_wb_addrsr_update_core$next[0:0]$1383 + update \o$next $0\o$next[63:0]$6567 + update \o_ok$next $0\o_ok$next[0:0]$6568 end - attribute \src "libresoc.v:44898.3-44906.6" - process $proc$libresoc.v:44898$1385 + attribute \src "libresoc.v:134072.3-134090.6" + process $proc$libresoc.v:134072$6572 assign { } { } assign { } { } - assign $0\jtag_wb_addrsr_update_core_prev$next[0:0]$1386 $1\jtag_wb_addrsr_update_core_prev$next[0:0]$1387 - attribute \src "libresoc.v:44899.5-44899.29" - switch \initial - attribute \src "libresoc.v:44899.9-44899.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$1387 1'0 - case - assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$1387 \jtag_wb_addrsr_update_core - end - sync always - update \jtag_wb_addrsr_update_core_prev$next $0\jtag_wb_addrsr_update_core_prev$next[0:0]$1386 - end - attribute \src "libresoc.v:44907.3-44923.6" - process $proc$libresoc.v:44907$1388 assign { } { } assign { } { } - assign $0\jtag_wb_addrsr__oe$next[0:0]$1389 $2\jtag_wb_addrsr__oe$next[0:0]$1391 - attribute \src "libresoc.v:44908.5-44908.29" + assign $0\cr_a$next[3:0]$6573 $1\cr_a$next[3:0]$6575 + assign { } { } + assign $0\cr_a_ok$next[0:0]$6574 $2\cr_a_ok$next[0:0]$6577 + attribute \src "libresoc.v:134073.5-134073.29" switch \initial - attribute \src "libresoc.v:44908.9-44908.17" + attribute \src "libresoc.v:134073.9-134073.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$405 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 + assign { } { } assign { } { } - assign $1\jtag_wb_addrsr__oe$next[0:0]$1390 \jtag_wb_addrsr_isir + assign { $1\cr_a_ok$next[0:0]$6576 $1\cr_a$next[3:0]$6575 } { \cr_a_ok$88 \cr_a$87 } attribute \src "libresoc.v:0.0-0.0" - case + case 2'1- assign { } { } - assign $1\jtag_wb_addrsr__oe$next[0:0]$1390 1'0 + assign { } { } + assign { $1\cr_a_ok$next[0:0]$6576 $1\cr_a$next[3:0]$6575 } { \cr_a_ok$88 \cr_a$87 } + case + assign $1\cr_a$next[3:0]$6575 \cr_a + assign $1\cr_a_ok$next[0:0]$6576 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\jtag_wb_addrsr__oe$next[0:0]$1391 1'0 + assign $2\cr_a_ok$next[0:0]$6577 1'0 case - assign $2\jtag_wb_addrsr__oe$next[0:0]$1391 $1\jtag_wb_addrsr__oe$next[0:0]$1390 + assign $2\cr_a_ok$next[0:0]$6577 $1\cr_a_ok$next[0:0]$6576 end sync always - update \jtag_wb_addrsr__oe$next $0\jtag_wb_addrsr__oe$next[0:0]$1389 + update \cr_a$next $0\cr_a$next[3:0]$6573 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$6574 end - attribute \src "libresoc.v:44924.3-44944.6" - process $proc$libresoc.v:44924$1392 + attribute \src "libresoc.v:134091.3-134109.6" + process $proc$libresoc.v:134091$6578 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\jtag_wb_addrsr_reg$next[28:0]$1393 $3\jtag_wb_addrsr_reg$next[28:0]$1396 - attribute \src "libresoc.v:44925.5-44925.29" + assign $0\xer_so$next[0:0]$6579 $1\xer_so$next[0:0]$6581 + assign { } { } + assign $0\xer_so_ok$next[0:0]$6580 $2\xer_so_ok$next[0:0]$6583 + attribute \src "libresoc.v:134092.5-134092.29" switch \initial - attribute \src "libresoc.v:44925.9-44925.17" + attribute \src "libresoc.v:134092.9-134092.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" - switch \jtag_wb_addrsr_shift + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 assign { } { } - assign $1\jtag_wb_addrsr_reg$next[28:0]$1394 { \TAP_bus__tdi \jtag_wb_addrsr_reg [28:1] } - case - assign $1\jtag_wb_addrsr_reg$next[28:0]$1394 \jtag_wb_addrsr_reg - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" - switch \jtag_wb_addrsr_capture + assign { } { } + assign { $1\xer_so_ok$next[0:0]$6582 $1\xer_so$next[0:0]$6581 } { \xer_so_ok$92 \xer_so$91 } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'1- assign { } { } - assign $2\jtag_wb_addrsr_reg$next[28:0]$1395 \jtag_wb_addrsr__i + assign { } { } + assign { $1\xer_so_ok$next[0:0]$6582 $1\xer_so$next[0:0]$6581 } { \xer_so_ok$92 \xer_so$91 } case - assign $2\jtag_wb_addrsr_reg$next[28:0]$1395 $1\jtag_wb_addrsr_reg$next[28:0]$1394 + assign $1\xer_so$next[0:0]$6581 \xer_so + assign $1\xer_so_ok$next[0:0]$6582 \xer_so_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \posjtag_rst + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\jtag_wb_addrsr_reg$next[28:0]$1396 29'00000000000000000000000000000 - case - assign $3\jtag_wb_addrsr_reg$next[28:0]$1396 $2\jtag_wb_addrsr_reg$next[28:0]$1395 - end + assign $2\xer_so_ok$next[0:0]$6583 1'0 + case + assign $2\xer_so_ok$next[0:0]$6583 $1\xer_so_ok$next[0:0]$6582 + end + sync always + update \xer_so$next $0\xer_so$next[0:0]$6579 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$6580 + end + connect \$64 $and$libresoc.v:133827$6489_Y + connect \cr_a$89 4'0000 + connect \cr_a_ok$90 1'0 + connect \xer_so_ok$93 1'0 + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_so_ok$92 \xer_so$91 } { 1'0 \main_xer_so$62 } + connect { \cr_a_ok$88 \cr_a$87 } 5'00000 + connect { \o_ok$86 \o$85 } { \main_o_ok \main_o } + connect { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } { \main_logical_op__insn$61 \main_logical_op__data_len$60 \main_logical_op__is_signed$59 \main_logical_op__is_32bit$58 \main_logical_op__output_carry$57 \main_logical_op__write_cr0$56 \main_logical_op__invert_out$55 \main_logical_op__input_carry$54 \main_logical_op__zero_a$53 \main_logical_op__invert_in$52 \main_logical_op__oe__ok$51 \main_logical_op__oe__oe$50 \main_logical_op__rc__ok$49 \main_logical_op__rc__rc$48 \main_logical_op__imm_data__ok$47 \main_logical_op__imm_data__data$46 \main_logical_op__fn_unit$45 \main_logical_op__insn_type$44 } + connect \muxid$66 \main_muxid$43 + connect \p_valid_i_p_ready_o \$64 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$63 \p_valid_i + connect \main_xer_so \input_xer_so$42 + connect \main_rb \input_rb$41 + connect \main_ra \input_ra$40 + connect { \main_logical_op__insn \main_logical_op__data_len \main_logical_op__is_signed \main_logical_op__is_32bit \main_logical_op__output_carry \main_logical_op__write_cr0 \main_logical_op__invert_out \main_logical_op__input_carry \main_logical_op__zero_a \main_logical_op__invert_in \main_logical_op__oe__ok \main_logical_op__oe__oe \main_logical_op__rc__ok \main_logical_op__rc__rc \main_logical_op__imm_data__ok \main_logical_op__imm_data__data \main_logical_op__fn_unit \main_logical_op__insn_type } { \input_logical_op__insn$39 \input_logical_op__data_len$38 \input_logical_op__is_signed$37 \input_logical_op__is_32bit$36 \input_logical_op__output_carry$35 \input_logical_op__write_cr0$34 \input_logical_op__invert_out$33 \input_logical_op__input_carry$32 \input_logical_op__zero_a$31 \input_logical_op__invert_in$30 \input_logical_op__oe__ok$29 \input_logical_op__oe__oe$28 \input_logical_op__rc__ok$27 \input_logical_op__rc__rc$26 \input_logical_op__imm_data__ok$25 \input_logical_op__imm_data__data$24 \input_logical_op__fn_unit$23 \input_logical_op__insn_type$22 } + connect \main_muxid \input_muxid$21 + connect \input_xer_so \xer_so$20 + connect \input_rb \rb + connect \input_ra \ra + connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } + connect \input_muxid \muxid$1 +end +attribute \src "libresoc.v:134137.1-135155.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2" +attribute \generator "nMigen" +module \logical_pipe2 + attribute \src "libresoc.v:135122.3-135140.6" + wire width 4 $0\cr_a$22$next[3:0]$6716 + attribute \src "libresoc.v:134926.3-134927.33" + wire width 4 $0\cr_a$22[3:0]$6613 + attribute \src "libresoc.v:134149.13-134149.29" + wire width 4 $0\cr_a$22[3:0]$6723 + attribute \src "libresoc.v:135122.3-135140.6" + wire $0\cr_a_ok$23$next[0:0]$6717 + attribute \src "libresoc.v:134928.3-134929.39" + wire $0\cr_a_ok$23[0:0]$6615 + attribute \src "libresoc.v:134158.7-134158.26" + wire $0\cr_a_ok$23[0:0]$6725 + attribute \src "libresoc.v:134138.7-134138.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:135061.3-135102.6" + wire width 4 $0\logical_op__data_len$18$next[3:0]$6667 + attribute \src "libresoc.v:134966.3-134967.65" + wire width 4 $0\logical_op__data_len$18[3:0]$6653 + attribute \src "libresoc.v:134169.13-134169.45" + wire width 4 $0\logical_op__data_len$18[3:0]$6727 + attribute \src "libresoc.v:135061.3-135102.6" + wire width 12 $0\logical_op__fn_unit$3$next[11:0]$6668 + attribute \src "libresoc.v:134936.3-134937.61" + wire width 12 $0\logical_op__fn_unit$3[11:0]$6623 + attribute \src "libresoc.v:134204.14-134204.47" + wire width 12 $0\logical_op__fn_unit$3[11:0]$6729 + attribute \src "libresoc.v:135061.3-135102.6" + wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$6669 + attribute \src "libresoc.v:134938.3-134939.75" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$6625 + attribute \src "libresoc.v:134226.14-134226.67" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$6731 + attribute \src "libresoc.v:135061.3-135102.6" + wire $0\logical_op__imm_data__ok$5$next[0:0]$6670 + attribute \src "libresoc.v:134940.3-134941.71" + wire $0\logical_op__imm_data__ok$5[0:0]$6627 + attribute \src "libresoc.v:134235.7-134235.42" + wire $0\logical_op__imm_data__ok$5[0:0]$6733 + attribute \src "libresoc.v:135061.3-135102.6" + wire width 2 $0\logical_op__input_carry$12$next[1:0]$6671 + attribute \src "libresoc.v:134954.3-134955.71" + wire width 2 $0\logical_op__input_carry$12[1:0]$6641 + attribute \src "libresoc.v:134252.13-134252.48" + wire width 2 $0\logical_op__input_carry$12[1:0]$6735 + attribute \src "libresoc.v:135061.3-135102.6" + wire width 32 $0\logical_op__insn$19$next[31:0]$6672 + attribute \src "libresoc.v:134968.3-134969.57" + wire width 32 $0\logical_op__insn$19[31:0]$6655 + attribute \src "libresoc.v:134265.14-134265.43" + wire width 32 $0\logical_op__insn$19[31:0]$6737 + attribute \src "libresoc.v:135061.3-135102.6" + wire width 7 $0\logical_op__insn_type$2$next[6:0]$6673 + attribute \src "libresoc.v:134934.3-134935.65" + wire width 7 $0\logical_op__insn_type$2[6:0]$6621 + attribute \src "libresoc.v:134422.13-134422.46" + wire width 7 $0\logical_op__insn_type$2[6:0]$6739 + attribute \src "libresoc.v:135061.3-135102.6" + wire $0\logical_op__invert_in$10$next[0:0]$6674 + attribute \src "libresoc.v:134950.3-134951.67" + wire $0\logical_op__invert_in$10[0:0]$6637 + attribute \src "libresoc.v:134505.7-134505.40" + wire $0\logical_op__invert_in$10[0:0]$6741 + attribute \src "libresoc.v:135061.3-135102.6" + wire $0\logical_op__invert_out$13$next[0:0]$6675 + attribute \src "libresoc.v:134956.3-134957.69" + wire $0\logical_op__invert_out$13[0:0]$6643 + attribute \src "libresoc.v:134514.7-134514.41" + wire $0\logical_op__invert_out$13[0:0]$6743 + attribute \src "libresoc.v:135061.3-135102.6" + wire $0\logical_op__is_32bit$16$next[0:0]$6676 + attribute \src "libresoc.v:134962.3-134963.65" + wire $0\logical_op__is_32bit$16[0:0]$6649 + attribute \src "libresoc.v:134523.7-134523.39" + wire $0\logical_op__is_32bit$16[0:0]$6745 + attribute \src "libresoc.v:135061.3-135102.6" + wire $0\logical_op__is_signed$17$next[0:0]$6677 + attribute \src "libresoc.v:134964.3-134965.67" + wire $0\logical_op__is_signed$17[0:0]$6651 + attribute \src "libresoc.v:134532.7-134532.40" + wire $0\logical_op__is_signed$17[0:0]$6747 + attribute \src "libresoc.v:135061.3-135102.6" + wire $0\logical_op__oe__oe$8$next[0:0]$6678 + attribute \src "libresoc.v:134946.3-134947.59" + wire $0\logical_op__oe__oe$8[0:0]$6633 + attribute \src "libresoc.v:134543.7-134543.36" + wire $0\logical_op__oe__oe$8[0:0]$6749 + attribute \src "libresoc.v:135061.3-135102.6" + wire $0\logical_op__oe__ok$9$next[0:0]$6679 + attribute \src "libresoc.v:134948.3-134949.59" + wire $0\logical_op__oe__ok$9[0:0]$6635 + attribute \src "libresoc.v:134552.7-134552.36" + wire $0\logical_op__oe__ok$9[0:0]$6751 + attribute \src "libresoc.v:135061.3-135102.6" + wire $0\logical_op__output_carry$15$next[0:0]$6680 + attribute \src "libresoc.v:134960.3-134961.73" + wire $0\logical_op__output_carry$15[0:0]$6647 + attribute \src "libresoc.v:134559.7-134559.43" + wire $0\logical_op__output_carry$15[0:0]$6753 + attribute \src "libresoc.v:135061.3-135102.6" + wire $0\logical_op__rc__ok$7$next[0:0]$6681 + attribute \src "libresoc.v:134944.3-134945.59" + wire $0\logical_op__rc__ok$7[0:0]$6631 + attribute \src "libresoc.v:134570.7-134570.36" + wire $0\logical_op__rc__ok$7[0:0]$6755 + attribute \src "libresoc.v:135061.3-135102.6" + wire $0\logical_op__rc__rc$6$next[0:0]$6682 + attribute \src "libresoc.v:134942.3-134943.59" + wire $0\logical_op__rc__rc$6[0:0]$6629 + attribute \src "libresoc.v:134579.7-134579.36" + wire $0\logical_op__rc__rc$6[0:0]$6757 + attribute \src "libresoc.v:135061.3-135102.6" + wire $0\logical_op__write_cr0$14$next[0:0]$6683 + attribute \src "libresoc.v:134958.3-134959.67" + wire $0\logical_op__write_cr0$14[0:0]$6645 + attribute \src "libresoc.v:134586.7-134586.40" + wire $0\logical_op__write_cr0$14[0:0]$6759 + attribute \src "libresoc.v:135061.3-135102.6" + wire $0\logical_op__zero_a$11$next[0:0]$6684 + attribute \src "libresoc.v:134952.3-134953.61" + wire $0\logical_op__zero_a$11[0:0]$6639 + attribute \src "libresoc.v:134595.7-134595.37" + wire $0\logical_op__zero_a$11[0:0]$6761 + attribute \src "libresoc.v:135048.3-135060.6" + wire width 2 $0\muxid$1$next[1:0]$6664 + attribute \src "libresoc.v:134970.3-134971.33" + wire width 2 $0\muxid$1[1:0]$6657 + attribute \src "libresoc.v:134604.13-134604.29" + wire width 2 $0\muxid$1[1:0]$6763 + attribute \src "libresoc.v:135103.3-135121.6" + wire width 64 $0\o$20$next[63:0]$6710 + attribute \src "libresoc.v:134930.3-134931.27" + wire width 64 $0\o$20[63:0]$6617 + attribute \src "libresoc.v:134619.14-134619.43" + wire width 64 $0\o$20[63:0]$6765 + attribute \src "libresoc.v:135103.3-135121.6" + wire $0\o_ok$21$next[0:0]$6711 + attribute \src "libresoc.v:134932.3-134933.33" + wire $0\o_ok$21[0:0]$6619 + attribute \src "libresoc.v:134628.7-134628.23" + wire $0\o_ok$21[0:0]$6767 + attribute \src "libresoc.v:135030.3-135047.6" + wire $0\r_busy$next[0:0]$6660 + attribute \src "libresoc.v:134972.3-134973.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:135122.3-135140.6" + wire width 4 $1\cr_a$22$next[3:0]$6718 + attribute \src "libresoc.v:135122.3-135140.6" + wire $1\cr_a_ok$23$next[0:0]$6719 + attribute \src "libresoc.v:135061.3-135102.6" + wire width 4 $1\logical_op__data_len$18$next[3:0]$6685 + attribute \src "libresoc.v:135061.3-135102.6" + wire width 12 $1\logical_op__fn_unit$3$next[11:0]$6686 + attribute \src "libresoc.v:135061.3-135102.6" + wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$6687 + attribute \src "libresoc.v:135061.3-135102.6" + wire $1\logical_op__imm_data__ok$5$next[0:0]$6688 + attribute \src "libresoc.v:135061.3-135102.6" + wire width 2 $1\logical_op__input_carry$12$next[1:0]$6689 + attribute \src "libresoc.v:135061.3-135102.6" + wire width 32 $1\logical_op__insn$19$next[31:0]$6690 + attribute \src "libresoc.v:135061.3-135102.6" + wire width 7 $1\logical_op__insn_type$2$next[6:0]$6691 + attribute \src "libresoc.v:135061.3-135102.6" + wire $1\logical_op__invert_in$10$next[0:0]$6692 + attribute \src "libresoc.v:135061.3-135102.6" + wire $1\logical_op__invert_out$13$next[0:0]$6693 + attribute \src "libresoc.v:135061.3-135102.6" + wire $1\logical_op__is_32bit$16$next[0:0]$6694 + attribute \src "libresoc.v:135061.3-135102.6" + wire $1\logical_op__is_signed$17$next[0:0]$6695 + attribute \src "libresoc.v:135061.3-135102.6" + wire $1\logical_op__oe__oe$8$next[0:0]$6696 + attribute \src "libresoc.v:135061.3-135102.6" + wire $1\logical_op__oe__ok$9$next[0:0]$6697 + attribute \src "libresoc.v:135061.3-135102.6" + wire $1\logical_op__output_carry$15$next[0:0]$6698 + attribute \src "libresoc.v:135061.3-135102.6" + wire $1\logical_op__rc__ok$7$next[0:0]$6699 + attribute \src "libresoc.v:135061.3-135102.6" + wire $1\logical_op__rc__rc$6$next[0:0]$6700 + attribute \src "libresoc.v:135061.3-135102.6" + wire $1\logical_op__write_cr0$14$next[0:0]$6701 + attribute \src "libresoc.v:135061.3-135102.6" + wire $1\logical_op__zero_a$11$next[0:0]$6702 + attribute \src "libresoc.v:135048.3-135060.6" + wire width 2 $1\muxid$1$next[1:0]$6665 + attribute \src "libresoc.v:135103.3-135121.6" + wire width 64 $1\o$20$next[63:0]$6712 + attribute \src "libresoc.v:135103.3-135121.6" + wire $1\o_ok$21$next[0:0]$6713 + attribute \src "libresoc.v:135030.3-135047.6" + wire $1\r_busy$next[0:0]$6661 + attribute \src "libresoc.v:134916.7-134916.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:135122.3-135140.6" + wire $2\cr_a_ok$23$next[0:0]$6720 + attribute \src "libresoc.v:135061.3-135102.6" + wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$6703 + attribute \src "libresoc.v:135061.3-135102.6" + wire $2\logical_op__imm_data__ok$5$next[0:0]$6704 + attribute \src "libresoc.v:135061.3-135102.6" + wire $2\logical_op__oe__oe$8$next[0:0]$6705 + attribute \src "libresoc.v:135061.3-135102.6" + wire $2\logical_op__oe__ok$9$next[0:0]$6706 + attribute \src "libresoc.v:135061.3-135102.6" + wire $2\logical_op__rc__ok$7$next[0:0]$6707 + attribute \src "libresoc.v:135061.3-135102.6" + wire $2\logical_op__rc__rc$6$next[0:0]$6708 + attribute \src "libresoc.v:135103.3-135121.6" + wire $2\o_ok$21$next[0:0]$6714 + attribute \src "libresoc.v:135030.3-135047.6" + wire $2\r_busy$next[0:0]$6662 + attribute \src "libresoc.v:134925.18-134925.118" + wire $and$libresoc.v:134925$6611_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 54 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 input 25 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 52 \cr_a$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 26 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 53 \cr_a_ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$73 + attribute \src "libresoc.v:134138.7-134138.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 48 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$68 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 6 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 33 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_op__fn_unit$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 34 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \logical_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$55 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 15 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 42 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$12$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 49 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$69 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 32 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 43 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 46 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 47 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 45 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 44 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$61 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 31 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 30 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 29 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 23 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 50 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 24 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 51 \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_logical_op__data_len$41 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \output_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \output_logical_op__fn_unit$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_logical_op__imm_data__data$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__imm_data__ok$28 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_logical_op__input_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_logical_op__insn$42 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_logical_op__insn_type$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_in$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_out$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_32bit$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_signed$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__oe$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__output_carry$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__rc$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__write_cr0$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__zero_a$34 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_muxid$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$48 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 27 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 28 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$47 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$libresoc.v:134925$6611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$48 + connect \B \p_ready_o + connect \Y $and$libresoc.v:134925$6611_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:134974.10-134977.4" + cell \n$53 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:134978.15-135025.4" + cell \output$54 \output + connect \cr_a \output_cr_a + connect \cr_a$22 \output_cr_a$45 + connect \cr_a_ok \output_cr_a_ok + connect \logical_op__data_len \output_logical_op__data_len + connect \logical_op__data_len$18 \output_logical_op__data_len$41 + connect \logical_op__fn_unit \output_logical_op__fn_unit + connect \logical_op__fn_unit$3 \output_logical_op__fn_unit$26 + connect \logical_op__imm_data__data \output_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \output_logical_op__imm_data__data$27 + connect \logical_op__imm_data__ok \output_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \output_logical_op__imm_data__ok$28 + connect \logical_op__input_carry \output_logical_op__input_carry + connect \logical_op__input_carry$12 \output_logical_op__input_carry$35 + connect \logical_op__insn \output_logical_op__insn + connect \logical_op__insn$19 \output_logical_op__insn$42 + connect \logical_op__insn_type \output_logical_op__insn_type + connect \logical_op__insn_type$2 \output_logical_op__insn_type$25 + connect \logical_op__invert_in \output_logical_op__invert_in + connect \logical_op__invert_in$10 \output_logical_op__invert_in$33 + connect \logical_op__invert_out \output_logical_op__invert_out + connect \logical_op__invert_out$13 \output_logical_op__invert_out$36 + connect \logical_op__is_32bit \output_logical_op__is_32bit + connect \logical_op__is_32bit$16 \output_logical_op__is_32bit$39 + connect \logical_op__is_signed \output_logical_op__is_signed + connect \logical_op__is_signed$17 \output_logical_op__is_signed$40 + connect \logical_op__oe__oe \output_logical_op__oe__oe + connect \logical_op__oe__oe$8 \output_logical_op__oe__oe$31 + connect \logical_op__oe__ok \output_logical_op__oe__ok + connect \logical_op__oe__ok$9 \output_logical_op__oe__ok$32 + connect \logical_op__output_carry \output_logical_op__output_carry + connect \logical_op__output_carry$15 \output_logical_op__output_carry$38 + connect \logical_op__rc__ok \output_logical_op__rc__ok + connect \logical_op__rc__ok$7 \output_logical_op__rc__ok$30 + connect \logical_op__rc__rc \output_logical_op__rc__rc + connect \logical_op__rc__rc$6 \output_logical_op__rc__rc$29 + connect \logical_op__write_cr0 \output_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \output_logical_op__write_cr0$37 + connect \logical_op__zero_a \output_logical_op__zero_a + connect \logical_op__zero_a$11 \output_logical_op__zero_a$34 + connect \muxid \output_muxid + connect \muxid$1 \output_muxid$24 + connect \o \output_o + connect \o$20 \output_o$43 + connect \o_ok \output_o_ok + connect \o_ok$21 \output_o_ok$44 + connect \xer_so \output_xer_so + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:135026.10-135029.4" + cell \p$52 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:134138.7-134138.20" + process $proc$libresoc.v:134138$6721 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:134149.13-134149.29" + process $proc$libresoc.v:134149$6722 + assign { } { } + assign $0\cr_a$22[3:0]$6723 4'0000 + sync always + sync init + update \cr_a$22 $0\cr_a$22[3:0]$6723 + end + attribute \src "libresoc.v:134158.7-134158.26" + process $proc$libresoc.v:134158$6724 + assign { } { } + assign $0\cr_a_ok$23[0:0]$6725 1'0 + sync always + sync init + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$6725 + end + attribute \src "libresoc.v:134169.13-134169.45" + process $proc$libresoc.v:134169$6726 + assign { } { } + assign $0\logical_op__data_len$18[3:0]$6727 4'0000 sync always - update \jtag_wb_addrsr_reg$next $0\jtag_wb_addrsr_reg$next[28:0]$1393 + sync init + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$6727 end - attribute \src "libresoc.v:44945.3-44953.6" - process $proc$libresoc.v:44945$1397 - assign { } { } + attribute \src "libresoc.v:134204.14-134204.47" + process $proc$libresoc.v:134204$6728 assign { } { } - assign $0\jtag_wb_datasr_update_core$next[0:0]$1398 $1\jtag_wb_datasr_update_core$next[0:0]$1399 - attribute \src "libresoc.v:44946.5-44946.29" - switch \initial - attribute \src "libresoc.v:44946.9-44946.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\jtag_wb_datasr_update_core$next[0:0]$1399 1'0 - case - assign $1\jtag_wb_datasr_update_core$next[0:0]$1399 \jtag_wb_datasr_update - end + assign $0\logical_op__fn_unit$3[11:0]$6729 12'000000000000 sync always - update \jtag_wb_datasr_update_core$next $0\jtag_wb_datasr_update_core$next[0:0]$1398 + sync init + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[11:0]$6729 end - attribute \src "libresoc.v:44954.3-44962.6" - process $proc$libresoc.v:44954$1400 + attribute \src "libresoc.v:134226.14-134226.67" + process $proc$libresoc.v:134226$6730 assign { } { } + assign $0\logical_op__imm_data__data$4[63:0]$6731 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$6731 + end + attribute \src "libresoc.v:134235.7-134235.42" + process $proc$libresoc.v:134235$6732 assign { } { } - assign $0\jtag_wb_datasr_update_core_prev$next[0:0]$1401 $1\jtag_wb_datasr_update_core_prev$next[0:0]$1402 - attribute \src "libresoc.v:44955.5-44955.29" - switch \initial - attribute \src "libresoc.v:44955.9-44955.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$1402 1'0 - case - assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$1402 \jtag_wb_datasr_update_core - end + assign $0\logical_op__imm_data__ok$5[0:0]$6733 1'0 sync always - update \jtag_wb_datasr_update_core_prev$next $0\jtag_wb_datasr_update_core_prev$next[0:0]$1401 + sync init + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$6733 end - attribute \src "libresoc.v:44963.3-44979.6" - process $proc$libresoc.v:44963$1403 + attribute \src "libresoc.v:134252.13-134252.48" + process $proc$libresoc.v:134252$6734 assign { } { } + assign $0\logical_op__input_carry$12[1:0]$6735 2'00 + sync always + sync init + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$6735 + end + attribute \src "libresoc.v:134265.14-134265.43" + process $proc$libresoc.v:134265$6736 assign { } { } - assign $0\jtag_wb_datasr__oe$next[1:0]$1404 $2\jtag_wb_datasr__oe$next[1:0]$1406 - attribute \src "libresoc.v:44964.5-44964.29" - switch \initial - attribute \src "libresoc.v:44964.9-44964.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$425 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\jtag_wb_datasr__oe$next[1:0]$1405 \jtag_wb_datasr_isir - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\jtag_wb_datasr__oe$next[1:0]$1405 2'00 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\jtag_wb_datasr__oe$next[1:0]$1406 2'00 - case - assign $2\jtag_wb_datasr__oe$next[1:0]$1406 $1\jtag_wb_datasr__oe$next[1:0]$1405 - end + assign $0\logical_op__insn$19[31:0]$6737 0 sync always - update \jtag_wb_datasr__oe$next $0\jtag_wb_datasr__oe$next[1:0]$1404 + sync init + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$6737 end - attribute \src "libresoc.v:44980.3-45000.6" - process $proc$libresoc.v:44980$1407 + attribute \src "libresoc.v:134422.13-134422.46" + process $proc$libresoc.v:134422$6738 assign { } { } + assign $0\logical_op__insn_type$2[6:0]$6739 7'0000000 + sync always + sync init + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$6739 + end + attribute \src "libresoc.v:134505.7-134505.40" + process $proc$libresoc.v:134505$6740 assign { } { } + assign $0\logical_op__invert_in$10[0:0]$6741 1'0 + sync always + sync init + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$6741 + end + attribute \src "libresoc.v:134514.7-134514.41" + process $proc$libresoc.v:134514$6742 assign { } { } + assign $0\logical_op__invert_out$13[0:0]$6743 1'0 + sync always + sync init + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$6743 + end + attribute \src "libresoc.v:134523.7-134523.39" + process $proc$libresoc.v:134523$6744 assign { } { } - assign $0\jtag_wb_datasr_reg$next[63:0]$1408 $3\jtag_wb_datasr_reg$next[63:0]$1411 - attribute \src "libresoc.v:44981.5-44981.29" - switch \initial - attribute \src "libresoc.v:44981.9-44981.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" - switch \jtag_wb_datasr_shift - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\jtag_wb_datasr_reg$next[63:0]$1409 { \TAP_bus__tdi \jtag_wb_datasr_reg [63:1] } - case - assign $1\jtag_wb_datasr_reg$next[63:0]$1409 \jtag_wb_datasr_reg - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" - switch \jtag_wb_datasr_capture - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\jtag_wb_datasr_reg$next[63:0]$1410 \jtag_wb_datasr__i - case - assign $2\jtag_wb_datasr_reg$next[63:0]$1410 $1\jtag_wb_datasr_reg$next[63:0]$1409 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \posjtag_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\jtag_wb_datasr_reg$next[63:0]$1411 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $3\jtag_wb_datasr_reg$next[63:0]$1411 $2\jtag_wb_datasr_reg$next[63:0]$1410 - end + assign $0\logical_op__is_32bit$16[0:0]$6745 1'0 sync always - update \jtag_wb_datasr_reg$next $0\jtag_wb_datasr_reg$next[63:0]$1408 + sync init + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$6745 end - attribute \src "libresoc.v:45001.3-45009.6" - process $proc$libresoc.v:45001$1412 + attribute \src "libresoc.v:134532.7-134532.40" + process $proc$libresoc.v:134532$6746 assign { } { } + assign $0\logical_op__is_signed$17[0:0]$6747 1'0 + sync always + sync init + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$6747 + end + attribute \src "libresoc.v:134543.7-134543.36" + process $proc$libresoc.v:134543$6748 assign { } { } - assign $0\dmi0_addrsr_update_core$next[0:0]$1413 $1\dmi0_addrsr_update_core$next[0:0]$1414 - attribute \src "libresoc.v:45002.5-45002.29" - switch \initial - attribute \src "libresoc.v:45002.9-45002.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi0_addrsr_update_core$next[0:0]$1414 1'0 - case - assign $1\dmi0_addrsr_update_core$next[0:0]$1414 \dmi0_addrsr_update - end + assign $0\logical_op__oe__oe$8[0:0]$6749 1'0 sync always - update \dmi0_addrsr_update_core$next $0\dmi0_addrsr_update_core$next[0:0]$1413 + sync init + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$6749 end - attribute \src "libresoc.v:45010.3-45018.6" - process $proc$libresoc.v:45010$1415 + attribute \src "libresoc.v:134552.7-134552.36" + process $proc$libresoc.v:134552$6750 assign { } { } + assign $0\logical_op__oe__ok$9[0:0]$6751 1'0 + sync always + sync init + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$6751 + end + attribute \src "libresoc.v:134559.7-134559.43" + process $proc$libresoc.v:134559$6752 assign { } { } - assign $0\dmi0_addrsr_update_core_prev$next[0:0]$1416 $1\dmi0_addrsr_update_core_prev$next[0:0]$1417 - attribute \src "libresoc.v:45011.5-45011.29" - switch \initial - attribute \src "libresoc.v:45011.9-45011.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi0_addrsr_update_core_prev$next[0:0]$1417 1'0 - case - assign $1\dmi0_addrsr_update_core_prev$next[0:0]$1417 \dmi0_addrsr_update_core - end + assign $0\logical_op__output_carry$15[0:0]$6753 1'0 sync always - update \dmi0_addrsr_update_core_prev$next $0\dmi0_addrsr_update_core_prev$next[0:0]$1416 + sync init + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$6753 end - attribute \src "libresoc.v:45019.3-45035.6" - process $proc$libresoc.v:45019$1418 + attribute \src "libresoc.v:134570.7-134570.36" + process $proc$libresoc.v:134570$6754 assign { } { } + assign $0\logical_op__rc__ok$7[0:0]$6755 1'0 + sync always + sync init + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$6755 + end + attribute \src "libresoc.v:134579.7-134579.36" + process $proc$libresoc.v:134579$6756 assign { } { } - assign $0\dmi0_addrsr__oe$next[0:0]$1419 $2\dmi0_addrsr__oe$next[0:0]$1421 - attribute \src "libresoc.v:45020.5-45020.29" - switch \initial - attribute \src "libresoc.v:45020.9-45020.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$443 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi0_addrsr__oe$next[0:0]$1420 \dmi0_addrsr_isir - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\dmi0_addrsr__oe$next[0:0]$1420 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dmi0_addrsr__oe$next[0:0]$1421 1'0 - case - assign $2\dmi0_addrsr__oe$next[0:0]$1421 $1\dmi0_addrsr__oe$next[0:0]$1420 - end + assign $0\logical_op__rc__rc$6[0:0]$6757 1'0 sync always - update \dmi0_addrsr__oe$next $0\dmi0_addrsr__oe$next[0:0]$1419 + sync init + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$6757 end - attribute \src "libresoc.v:45036.3-45056.6" - process $proc$libresoc.v:45036$1422 + attribute \src "libresoc.v:134586.7-134586.40" + process $proc$libresoc.v:134586$6758 assign { } { } + assign $0\logical_op__write_cr0$14[0:0]$6759 1'0 + sync always + sync init + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$6759 + end + attribute \src "libresoc.v:134595.7-134595.37" + process $proc$libresoc.v:134595$6760 assign { } { } + assign $0\logical_op__zero_a$11[0:0]$6761 1'0 + sync always + sync init + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$6761 + end + attribute \src "libresoc.v:134604.13-134604.29" + process $proc$libresoc.v:134604$6762 assign { } { } + assign $0\muxid$1[1:0]$6763 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$6763 + end + attribute \src "libresoc.v:134619.14-134619.43" + process $proc$libresoc.v:134619$6764 assign { } { } - assign $0\dmi0_addrsr_reg$next[7:0]$1423 $3\dmi0_addrsr_reg$next[7:0]$1426 - attribute \src "libresoc.v:45037.5-45037.29" - switch \initial - attribute \src "libresoc.v:45037.9-45037.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" - switch \dmi0_addrsr_shift - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi0_addrsr_reg$next[7:0]$1424 { \TAP_bus__tdi \dmi0_addrsr_reg [7:1] } - case - assign $1\dmi0_addrsr_reg$next[7:0]$1424 \dmi0_addrsr_reg - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" - switch \dmi0_addrsr_capture - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dmi0_addrsr_reg$next[7:0]$1425 \dmi0_addrsr__i - case - assign $2\dmi0_addrsr_reg$next[7:0]$1425 $1\dmi0_addrsr_reg$next[7:0]$1424 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \posjtag_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\dmi0_addrsr_reg$next[7:0]$1426 8'00000000 - case - assign $3\dmi0_addrsr_reg$next[7:0]$1426 $2\dmi0_addrsr_reg$next[7:0]$1425 - end + assign $0\o$20[63:0]$6765 64'0000000000000000000000000000000000000000000000000000000000000000 sync always - update \dmi0_addrsr_reg$next $0\dmi0_addrsr_reg$next[7:0]$1423 + sync init + update \o$20 $0\o$20[63:0]$6765 end - attribute \src "libresoc.v:45057.3-45065.6" - process $proc$libresoc.v:45057$1427 + attribute \src "libresoc.v:134628.7-134628.23" + process $proc$libresoc.v:134628$6766 assign { } { } + assign $0\o_ok$21[0:0]$6767 1'0 + sync always + sync init + update \o_ok$21 $0\o_ok$21[0:0]$6767 + end + attribute \src "libresoc.v:134916.7-134916.20" + process $proc$libresoc.v:134916$6768 assign { } { } - assign $0\dmi0_datasr_update_core$next[0:0]$1428 $1\dmi0_datasr_update_core$next[0:0]$1429 - attribute \src "libresoc.v:45058.5-45058.29" - switch \initial - attribute \src "libresoc.v:45058.9-45058.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi0_datasr_update_core$next[0:0]$1429 1'0 - case - assign $1\dmi0_datasr_update_core$next[0:0]$1429 \dmi0_datasr_update - end + assign $1\r_busy[0:0] 1'0 sync always - update \dmi0_datasr_update_core$next $0\dmi0_datasr_update_core$next[0:0]$1428 + sync init + update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:45066.3-45074.6" - process $proc$libresoc.v:45066$1430 + attribute \src "libresoc.v:134926.3-134927.33" + process $proc$libresoc.v:134926$6612 assign { } { } + assign $0\cr_a$22[3:0]$6613 \cr_a$22$next + sync posedge \coresync_clk + update \cr_a$22 $0\cr_a$22[3:0]$6613 + end + attribute \src "libresoc.v:134928.3-134929.39" + process $proc$libresoc.v:134928$6614 assign { } { } - assign $0\dmi0_datasr_update_core_prev$next[0:0]$1431 $1\dmi0_datasr_update_core_prev$next[0:0]$1432 - attribute \src "libresoc.v:45067.5-45067.29" - switch \initial - attribute \src "libresoc.v:45067.9-45067.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi0_datasr_update_core_prev$next[0:0]$1432 1'0 - case - assign $1\dmi0_datasr_update_core_prev$next[0:0]$1432 \dmi0_datasr_update_core - end - sync always - update \dmi0_datasr_update_core_prev$next $0\dmi0_datasr_update_core_prev$next[0:0]$1431 + assign $0\cr_a_ok$23[0:0]$6615 \cr_a_ok$23$next + sync posedge \coresync_clk + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$6615 end - attribute \src "libresoc.v:45075.3-45091.6" - process $proc$libresoc.v:45075$1433 + attribute \src "libresoc.v:134930.3-134931.27" + process $proc$libresoc.v:134930$6616 assign { } { } + assign $0\o$20[63:0]$6617 \o$20$next + sync posedge \coresync_clk + update \o$20 $0\o$20[63:0]$6617 + end + attribute \src "libresoc.v:134932.3-134933.33" + process $proc$libresoc.v:134932$6618 assign { } { } - assign $0\dmi0_datasr__oe$next[1:0]$1434 $2\dmi0_datasr__oe$next[1:0]$1436 - attribute \src "libresoc.v:45076.5-45076.29" - switch \initial - attribute \src "libresoc.v:45076.9-45076.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$463 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi0_datasr__oe$next[1:0]$1435 \dmi0_datasr_isir - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\dmi0_datasr__oe$next[1:0]$1435 2'00 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dmi0_datasr__oe$next[1:0]$1436 2'00 - case - assign $2\dmi0_datasr__oe$next[1:0]$1436 $1\dmi0_datasr__oe$next[1:0]$1435 - end - sync always - update \dmi0_datasr__oe$next $0\dmi0_datasr__oe$next[1:0]$1434 + assign $0\o_ok$21[0:0]$6619 \o_ok$21$next + sync posedge \coresync_clk + update \o_ok$21 $0\o_ok$21[0:0]$6619 end - attribute \src "libresoc.v:45092.3-45112.6" - process $proc$libresoc.v:45092$1437 + attribute \src "libresoc.v:134934.3-134935.65" + process $proc$libresoc.v:134934$6620 assign { } { } + assign $0\logical_op__insn_type$2[6:0]$6621 \logical_op__insn_type$2$next + sync posedge \coresync_clk + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$6621 + end + attribute \src "libresoc.v:134936.3-134937.61" + process $proc$libresoc.v:134936$6622 assign { } { } + assign $0\logical_op__fn_unit$3[11:0]$6623 \logical_op__fn_unit$3$next + sync posedge \coresync_clk + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[11:0]$6623 + end + attribute \src "libresoc.v:134938.3-134939.75" + process $proc$libresoc.v:134938$6624 assign { } { } + assign $0\logical_op__imm_data__data$4[63:0]$6625 \logical_op__imm_data__data$4$next + sync posedge \coresync_clk + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$6625 + end + attribute \src "libresoc.v:134940.3-134941.71" + process $proc$libresoc.v:134940$6626 assign { } { } - assign $0\dmi0_datasr_reg$next[63:0]$1438 $3\dmi0_datasr_reg$next[63:0]$1441 - attribute \src "libresoc.v:45093.5-45093.29" - switch \initial - attribute \src "libresoc.v:45093.9-45093.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" - switch \dmi0_datasr_shift - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi0_datasr_reg$next[63:0]$1439 { \TAP_bus__tdi \dmi0_datasr_reg [63:1] } - case - assign $1\dmi0_datasr_reg$next[63:0]$1439 \dmi0_datasr_reg - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" - switch \dmi0_datasr_capture - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dmi0_datasr_reg$next[63:0]$1440 \dmi0_datasr__i - case - assign $2\dmi0_datasr_reg$next[63:0]$1440 $1\dmi0_datasr_reg$next[63:0]$1439 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \posjtag_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\dmi0_datasr_reg$next[63:0]$1441 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $3\dmi0_datasr_reg$next[63:0]$1441 $2\dmi0_datasr_reg$next[63:0]$1440 - end - sync always - update \dmi0_datasr_reg$next $0\dmi0_datasr_reg$next[63:0]$1438 + assign $0\logical_op__imm_data__ok$5[0:0]$6627 \logical_op__imm_data__ok$5$next + sync posedge \coresync_clk + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$6627 end - attribute \src "libresoc.v:45113.3-45121.6" - process $proc$libresoc.v:45113$1442 + attribute \src "libresoc.v:134942.3-134943.59" + process $proc$libresoc.v:134942$6628 assign { } { } + assign $0\logical_op__rc__rc$6[0:0]$6629 \logical_op__rc__rc$6$next + sync posedge \coresync_clk + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$6629 + end + attribute \src "libresoc.v:134944.3-134945.59" + process $proc$libresoc.v:134944$6630 assign { } { } - assign $0\sr5_update_core$next[0:0]$1443 $1\sr5_update_core$next[0:0]$1444 - attribute \src "libresoc.v:45114.5-45114.29" - switch \initial - attribute \src "libresoc.v:45114.9-45114.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\sr5_update_core$next[0:0]$1444 1'0 - case - assign $1\sr5_update_core$next[0:0]$1444 \sr5_update - end - sync always - update \sr5_update_core$next $0\sr5_update_core$next[0:0]$1443 + assign $0\logical_op__rc__ok$7[0:0]$6631 \logical_op__rc__ok$7$next + sync posedge \coresync_clk + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$6631 end - attribute \src "libresoc.v:45122.3-45130.6" - process $proc$libresoc.v:45122$1445 + attribute \src "libresoc.v:134946.3-134947.59" + process $proc$libresoc.v:134946$6632 assign { } { } + assign $0\logical_op__oe__oe$8[0:0]$6633 \logical_op__oe__oe$8$next + sync posedge \coresync_clk + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$6633 + end + attribute \src "libresoc.v:134948.3-134949.59" + process $proc$libresoc.v:134948$6634 assign { } { } - assign $0\sr5_update_core_prev$next[0:0]$1446 $1\sr5_update_core_prev$next[0:0]$1447 - attribute \src "libresoc.v:45123.5-45123.29" - switch \initial - attribute \src "libresoc.v:45123.9-45123.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\sr5_update_core_prev$next[0:0]$1447 1'0 - case - assign $1\sr5_update_core_prev$next[0:0]$1447 \sr5_update_core - end - sync always - update \sr5_update_core_prev$next $0\sr5_update_core_prev$next[0:0]$1446 + assign $0\logical_op__oe__ok$9[0:0]$6635 \logical_op__oe__ok$9$next + sync posedge \coresync_clk + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$6635 end - attribute \src "libresoc.v:45131.3-45147.6" - process $proc$libresoc.v:45131$1448 + attribute \src "libresoc.v:134950.3-134951.67" + process $proc$libresoc.v:134950$6636 assign { } { } + assign $0\logical_op__invert_in$10[0:0]$6637 \logical_op__invert_in$10$next + sync posedge \coresync_clk + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$6637 + end + attribute \src "libresoc.v:134952.3-134953.61" + process $proc$libresoc.v:134952$6638 assign { } { } - assign $0\sr5__oe$next[0:0]$1449 $2\sr5__oe$next[0:0]$1451 - attribute \src "libresoc.v:45132.5-45132.29" - switch \initial - attribute \src "libresoc.v:45132.9-45132.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$481 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\sr5__oe$next[0:0]$1450 \sr5_isir - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\sr5__oe$next[0:0]$1450 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\sr5__oe$next[0:0]$1451 1'0 - case - assign $2\sr5__oe$next[0:0]$1451 $1\sr5__oe$next[0:0]$1450 - end - sync always - update \sr5__oe$next $0\sr5__oe$next[0:0]$1449 + assign $0\logical_op__zero_a$11[0:0]$6639 \logical_op__zero_a$11$next + sync posedge \coresync_clk + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$6639 end - attribute \src "libresoc.v:45148.3-45168.6" - process $proc$libresoc.v:45148$1452 + attribute \src "libresoc.v:134954.3-134955.71" + process $proc$libresoc.v:134954$6640 assign { } { } + assign $0\logical_op__input_carry$12[1:0]$6641 \logical_op__input_carry$12$next + sync posedge \coresync_clk + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$6641 + end + attribute \src "libresoc.v:134956.3-134957.69" + process $proc$libresoc.v:134956$6642 assign { } { } + assign $0\logical_op__invert_out$13[0:0]$6643 \logical_op__invert_out$13$next + sync posedge \coresync_clk + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$6643 + end + attribute \src "libresoc.v:134958.3-134959.67" + process $proc$libresoc.v:134958$6644 assign { } { } + assign $0\logical_op__write_cr0$14[0:0]$6645 \logical_op__write_cr0$14$next + sync posedge \coresync_clk + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$6645 + end + attribute \src "libresoc.v:134960.3-134961.73" + process $proc$libresoc.v:134960$6646 assign { } { } - assign $0\sr5_reg$next[1:0]$1453 $3\sr5_reg$next[1:0]$1456 - attribute \src "libresoc.v:45149.5-45149.29" - switch \initial - attribute \src "libresoc.v:45149.9-45149.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" - switch \sr5_shift - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\sr5_reg$next[1:0]$1454 { \TAP_bus__tdi \sr5_reg [1] } - case - assign $1\sr5_reg$next[1:0]$1454 \sr5_reg - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" - switch \sr5_capture - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\sr5_reg$next[1:0]$1455 \sr5__i - case - assign $2\sr5_reg$next[1:0]$1455 $1\sr5_reg$next[1:0]$1454 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \posjtag_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\sr5_reg$next[1:0]$1456 2'00 - case - assign $3\sr5_reg$next[1:0]$1456 $2\sr5_reg$next[1:0]$1455 - end - sync always - update \sr5_reg$next $0\sr5_reg$next[1:0]$1453 + assign $0\logical_op__output_carry$15[0:0]$6647 \logical_op__output_carry$15$next + sync posedge \coresync_clk + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$6647 end - attribute \src "libresoc.v:45169.3-45195.6" - process $proc$libresoc.v:45169$1457 + attribute \src "libresoc.v:134962.3-134963.65" + process $proc$libresoc.v:134962$6648 assign { } { } - assign $0\TAP_bus__tdo[0:0] $1\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:45170.5-45170.29" - switch \initial - attribute \src "libresoc.v:45170.9-45170.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:685" - switch { \sr5_shift \dmi0_datasr_shift \dmi0_addrsr_shift \jtag_wb_datasr_shift \jtag_wb_addrsr_shift \sr0_shift } - attribute \src "libresoc.v:0.0-0.0" - case 6'-----1 - assign { } { } - assign $1\TAP_bus__tdo[0:0] \sr0_reg [0] - attribute \src "libresoc.v:0.0-0.0" - case 6'----1- - assign { } { } - assign $1\TAP_bus__tdo[0:0] \jtag_wb_addrsr_reg [0] - attribute \src "libresoc.v:0.0-0.0" - case 6'---1-- - assign { } { } - assign $1\TAP_bus__tdo[0:0] \jtag_wb_datasr_reg [0] - attribute \src "libresoc.v:0.0-0.0" - case 6'--1--- - assign { } { } - assign $1\TAP_bus__tdo[0:0] \dmi0_addrsr_reg [0] - attribute \src "libresoc.v:0.0-0.0" - case 6'-1---- - assign { } { } - assign $1\TAP_bus__tdo[0:0] \dmi0_datasr_reg [0] - attribute \src "libresoc.v:0.0-0.0" - case 6'1----- - assign { } { } - assign $1\TAP_bus__tdo[0:0] \sr5_reg [0] - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\TAP_bus__tdo[0:0] \TAP_tdo - end - sync always - update \TAP_bus__tdo $0\TAP_bus__tdo[0:0] + assign $0\logical_op__is_32bit$16[0:0]$6649 \logical_op__is_32bit$16$next + sync posedge \coresync_clk + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$6649 end - attribute \src "libresoc.v:45196.3-45228.6" - process $proc$libresoc.v:45196$1458 + attribute \src "libresoc.v:134964.3-134965.67" + process $proc$libresoc.v:134964$6650 assign { } { } + assign $0\logical_op__is_signed$17[0:0]$6651 \logical_op__is_signed$17$next + sync posedge \coresync_clk + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$6651 + end + attribute \src "libresoc.v:134966.3-134967.65" + process $proc$libresoc.v:134966$6652 assign { } { } + assign $0\logical_op__data_len$18[3:0]$6653 \logical_op__data_len$18$next + sync posedge \coresync_clk + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$6653 + end + attribute \src "libresoc.v:134968.3-134969.57" + process $proc$libresoc.v:134968$6654 assign { } { } - assign $0\jtag_wb__adr$next[28:0]$1459 $4\jtag_wb__adr$next[28:0]$1463 - attribute \src "libresoc.v:45197.5-45197.29" - switch \initial - attribute \src "libresoc.v:45197.9-45197.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 3'000 - assign { } { } - assign $1\jtag_wb__adr$next[28:0]$1460 $2\jtag_wb__adr$next[28:0]$1461 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" - switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $2\jtag_wb__adr$next[28:0]$1461 \jtag_wb_addrsr__o - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign $2\jtag_wb__adr$next[28:0]$1461 \$495 [28:0] - case - assign $2\jtag_wb__adr$next[28:0]$1461 \jtag_wb__adr - end - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\jtag_wb__adr$next[28:0]$1460 $3\jtag_wb__adr$next[28:0]$1462 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" - switch \jtag_wb__ack - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\jtag_wb__adr$next[28:0]$1462 \$498 [28:0] - case - assign $3\jtag_wb__adr$next[28:0]$1462 \jtag_wb__adr - end - case - assign $1\jtag_wb__adr$next[28:0]$1460 \jtag_wb__adr - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\jtag_wb__adr$next[28:0]$1463 29'00000000000000000000000000000 - case - assign $4\jtag_wb__adr$next[28:0]$1463 $1\jtag_wb__adr$next[28:0]$1460 - end - sync always - update \jtag_wb__adr$next $0\jtag_wb__adr$next[28:0]$1459 + assign $0\logical_op__insn$19[31:0]$6655 \logical_op__insn$19$next + sync posedge \coresync_clk + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$6655 + end + attribute \src "libresoc.v:134970.3-134971.33" + process $proc$libresoc.v:134970$6656 + assign { } { } + assign $0\muxid$1[1:0]$6657 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$6657 + end + attribute \src "libresoc.v:134972.3-134973.29" + process $proc$libresoc.v:134972$6658 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:45229.3-45281.6" - process $proc$libresoc.v:45229$1464 + attribute \src "libresoc.v:135030.3-135047.6" + process $proc$libresoc.v:135030$6659 assign { } { } assign { } { } assign { } { } - assign $0\fsm_state$next[2:0]$1465 $5\fsm_state$next[2:0]$1470 - attribute \src "libresoc.v:45230.5-45230.29" + assign $0\r_busy$next[0:0]$6660 $2\r_busy$next[0:0]$6662 + attribute \src "libresoc.v:135031.5-135031.29" switch \initial - attribute \src "libresoc.v:45230.9-45230.17" + attribute \src "libresoc.v:135031.9-135031.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 3'000 - assign { } { } - assign $1\fsm_state$next[2:0]$1466 $2\fsm_state$next[2:0]$1467 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" - switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $2\fsm_state$next[2:0]$1467 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign $2\fsm_state$next[2:0]$1467 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $2\fsm_state$next[2:0]$1467 3'010 - case - assign $2\fsm_state$next[2:0]$1467 \fsm_state - end - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\fsm_state$next[2:0]$1466 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\fsm_state$next[2:0]$1466 $3\fsm_state$next[2:0]$1468 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" - switch \jtag_wb__ack - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fsm_state$next[2:0]$1468 3'000 - case - assign $3\fsm_state$next[2:0]$1468 \fsm_state - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" - case 3'010 + case 2'-1 assign { } { } - assign $1\fsm_state$next[2:0]$1466 3'100 + assign $1\r_busy$next[0:0]$6661 1'1 attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 2'1- assign { } { } - assign $1\fsm_state$next[2:0]$1466 $4\fsm_state$next[2:0]$1469 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" - switch \jtag_wb__ack - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\fsm_state$next[2:0]$1469 3'001 - case - assign $4\fsm_state$next[2:0]$1469 \fsm_state - end + assign $1\r_busy$next[0:0]$6661 1'0 case - assign $1\fsm_state$next[2:0]$1466 \fsm_state + assign $1\r_busy$next[0:0]$6661 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fsm_state$next[2:0]$1470 3'000 + assign $2\r_busy$next[0:0]$6662 1'0 case - assign $5\fsm_state$next[2:0]$1470 $1\fsm_state$next[2:0]$1466 + assign $2\r_busy$next[0:0]$6662 $1\r_busy$next[0:0]$6661 end sync always - update \fsm_state$next $0\fsm_state$next[2:0]$1465 + update \r_busy$next $0\r_busy$next[0:0]$6660 end - attribute \src "libresoc.v:45282.3-45308.6" - process $proc$libresoc.v:45282$1471 + attribute \src "libresoc.v:135048.3-135060.6" + process $proc$libresoc.v:135048$6663 assign { } { } assign { } { } - assign { } { } - assign $0\jtag_wb__dat_w$next[63:0]$1472 $3\jtag_wb__dat_w$next[63:0]$1475 - attribute \src "libresoc.v:45283.5-45283.29" + assign $0\muxid$1$next[1:0]$6664 $1\muxid$1$next[1:0]$6665 + attribute \src "libresoc.v:135049.5-135049.29" switch \initial - attribute \src "libresoc.v:45283.9-45283.17" + attribute \src "libresoc.v:135049.9-135049.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" - switch \fsm_state + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" - case 3'000 + case 2'-1 assign { } { } - assign $1\jtag_wb__dat_w$next[63:0]$1473 $2\jtag_wb__dat_w$next[63:0]$1474 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" - switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign $2\jtag_wb__dat_w$next[63:0]$1474 \jtag_wb__dat_w - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign $2\jtag_wb__dat_w$next[63:0]$1474 \jtag_wb__dat_w - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $2\jtag_wb__dat_w$next[63:0]$1474 \jtag_wb_datasr__o - case - assign $2\jtag_wb__dat_w$next[63:0]$1474 \jtag_wb__dat_w - end - case - assign $1\jtag_wb__dat_w$next[63:0]$1473 \jtag_wb__dat_w - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + assign $1\muxid$1$next[1:0]$6665 \muxid$51 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'1- assign { } { } - assign $3\jtag_wb__dat_w$next[63:0]$1475 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\muxid$1$next[1:0]$6665 \muxid$51 case - assign $3\jtag_wb__dat_w$next[63:0]$1475 $1\jtag_wb__dat_w$next[63:0]$1473 + assign $1\muxid$1$next[1:0]$6665 \muxid$1 end sync always - update \jtag_wb__dat_w$next $0\jtag_wb__dat_w$next[63:0]$1472 + update \muxid$1$next $0\muxid$1$next[1:0]$6664 end - attribute \src "libresoc.v:45309.3-45329.6" - process $proc$libresoc.v:45309$1476 + attribute \src "libresoc.v:135061.3-135102.6" + process $proc$libresoc.v:135061$6666 + assign { } { } + assign { } { } + assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\jtag_wb_datasr__i$next[63:0]$1477 $3\jtag_wb_datasr__i$next[63:0]$1480 - attribute \src "libresoc.v:45310.5-45310.29" - switch \initial - attribute \src "libresoc.v:45310.9-45310.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\jtag_wb_datasr__i$next[63:0]$1478 $2\jtag_wb_datasr__i$next[63:0]$1479 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" - switch \jtag_wb__ack - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\jtag_wb_datasr__i$next[63:0]$1479 \jtag_wb__dat_r - case - assign $2\jtag_wb_datasr__i$next[63:0]$1479 \jtag_wb_datasr__i - end - case - assign $1\jtag_wb_datasr__i$next[63:0]$1478 \jtag_wb_datasr__i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\jtag_wb_datasr__i$next[63:0]$1480 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $3\jtag_wb_datasr__i$next[63:0]$1480 $1\jtag_wb_datasr__i$next[63:0]$1478 - end - sync always - update \jtag_wb_datasr__i$next $0\jtag_wb_datasr__i$next[63:0]$1477 - end - attribute \src "libresoc.v:45330.3-45362.6" - process $proc$libresoc.v:45330$1481 assign { } { } assign { } { } assign { } { } - assign $0\dmi0__addr_i$next[3:0]$1482 $4\dmi0__addr_i$next[3:0]$1486 - attribute \src "libresoc.v:45331.5-45331.29" - switch \initial - attribute \src "libresoc.v:45331.9-45331.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - switch \fsm_state$503 - attribute \src "libresoc.v:0.0-0.0" - case 3'000 - assign { } { } - assign $1\dmi0__addr_i$next[3:0]$1483 $2\dmi0__addr_i$next[3:0]$1484 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" - switch { \dmi0_datasr__oe \dmi0_addrsr__oe } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $2\dmi0__addr_i$next[3:0]$1484 \dmi0_addrsr__o [3:0] - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign $2\dmi0__addr_i$next[3:0]$1484 \$512 [3:0] - case - assign $2\dmi0__addr_i$next[3:0]$1484 \dmi0__addr_i - end - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\dmi0__addr_i$next[3:0]$1483 $3\dmi0__addr_i$next[3:0]$1485 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" - switch \dmi0__ack_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\dmi0__addr_i$next[3:0]$1485 \$515 [3:0] - case - assign $3\dmi0__addr_i$next[3:0]$1485 \dmi0__addr_i - end - case - assign $1\dmi0__addr_i$next[3:0]$1483 \dmi0__addr_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\dmi0__addr_i$next[3:0]$1486 4'0000 - case - assign $4\dmi0__addr_i$next[3:0]$1486 $1\dmi0__addr_i$next[3:0]$1483 - end - sync always - update \dmi0__addr_i$next $0\dmi0__addr_i$next[3:0]$1482 - end - attribute \src "libresoc.v:45363.3-45415.6" - process $proc$libresoc.v:45363$1487 assign { } { } assign { } { } assign { } { } - assign $0\fsm_state$503$next[2:0]$1488 $5\fsm_state$503$next[2:0]$1493 - attribute \src "libresoc.v:45364.5-45364.29" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\logical_op__data_len$18$next[3:0]$6667 $1\logical_op__data_len$18$next[3:0]$6685 + assign $0\logical_op__fn_unit$3$next[11:0]$6668 $1\logical_op__fn_unit$3$next[11:0]$6686 + assign { } { } + assign { } { } + assign $0\logical_op__input_carry$12$next[1:0]$6671 $1\logical_op__input_carry$12$next[1:0]$6689 + assign $0\logical_op__insn$19$next[31:0]$6672 $1\logical_op__insn$19$next[31:0]$6690 + assign $0\logical_op__insn_type$2$next[6:0]$6673 $1\logical_op__insn_type$2$next[6:0]$6691 + assign $0\logical_op__invert_in$10$next[0:0]$6674 $1\logical_op__invert_in$10$next[0:0]$6692 + assign $0\logical_op__invert_out$13$next[0:0]$6675 $1\logical_op__invert_out$13$next[0:0]$6693 + assign $0\logical_op__is_32bit$16$next[0:0]$6676 $1\logical_op__is_32bit$16$next[0:0]$6694 + assign $0\logical_op__is_signed$17$next[0:0]$6677 $1\logical_op__is_signed$17$next[0:0]$6695 + assign { } { } + assign { } { } + assign $0\logical_op__output_carry$15$next[0:0]$6680 $1\logical_op__output_carry$15$next[0:0]$6698 + assign { } { } + assign { } { } + assign $0\logical_op__write_cr0$14$next[0:0]$6683 $1\logical_op__write_cr0$14$next[0:0]$6701 + assign $0\logical_op__zero_a$11$next[0:0]$6684 $1\logical_op__zero_a$11$next[0:0]$6702 + assign $0\logical_op__imm_data__data$4$next[63:0]$6669 $2\logical_op__imm_data__data$4$next[63:0]$6703 + assign $0\logical_op__imm_data__ok$5$next[0:0]$6670 $2\logical_op__imm_data__ok$5$next[0:0]$6704 + assign $0\logical_op__oe__oe$8$next[0:0]$6678 $2\logical_op__oe__oe$8$next[0:0]$6705 + assign $0\logical_op__oe__ok$9$next[0:0]$6679 $2\logical_op__oe__ok$9$next[0:0]$6706 + assign $0\logical_op__rc__ok$7$next[0:0]$6681 $2\logical_op__rc__ok$7$next[0:0]$6707 + assign $0\logical_op__rc__rc$6$next[0:0]$6682 $2\logical_op__rc__rc$6$next[0:0]$6708 + attribute \src "libresoc.v:135062.5-135062.29" switch \initial - attribute \src "libresoc.v:45364.9-45364.17" + attribute \src "libresoc.v:135062.9-135062.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - switch \fsm_state$503 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" - case 3'000 + case 2'-1 assign { } { } - assign $1\fsm_state$503$next[2:0]$1489 $2\fsm_state$503$next[2:0]$1490 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" - switch { \dmi0_datasr__oe \dmi0_addrsr__oe } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $2\fsm_state$503$next[2:0]$1490 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign $2\fsm_state$503$next[2:0]$1490 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $2\fsm_state$503$next[2:0]$1490 3'010 - case - assign $2\fsm_state$503$next[2:0]$1490 \fsm_state$503 - end - attribute \src "libresoc.v:0.0-0.0" - case 3'001 assign { } { } - assign $1\fsm_state$503$next[2:0]$1489 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 assign { } { } - assign $1\fsm_state$503$next[2:0]$1489 $3\fsm_state$503$next[2:0]$1491 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" - switch \dmi0__ack_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fsm_state$503$next[2:0]$1491 3'000 - case - assign $3\fsm_state$503$next[2:0]$1491 \fsm_state$503 - end - attribute \src "libresoc.v:0.0-0.0" - case 3'010 assign { } { } - assign $1\fsm_state$503$next[2:0]$1489 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 3'100 assign { } { } - assign $1\fsm_state$503$next[2:0]$1489 $4\fsm_state$503$next[2:0]$1492 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" - switch \dmi0__ack_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\fsm_state$503$next[2:0]$1492 3'001 - case - assign $4\fsm_state$503$next[2:0]$1492 \fsm_state$503 - end - case - assign $1\fsm_state$503$next[2:0]$1489 \fsm_state$503 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $5\fsm_state$503$next[2:0]$1493 3'000 - case - assign $5\fsm_state$503$next[2:0]$1493 $1\fsm_state$503$next[2:0]$1489 - end - sync always - update \fsm_state$503$next $0\fsm_state$503$next[2:0]$1488 - end - attribute \src "libresoc.v:45416.3-45442.6" - process $proc$libresoc.v:45416$1494 - assign { } { } - assign { } { } - assign { } { } - assign $0\dmi0__din$next[63:0]$1495 $3\dmi0__din$next[63:0]$1498 - attribute \src "libresoc.v:45417.5-45417.29" - switch \initial - attribute \src "libresoc.v:45417.9-45417.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - switch \fsm_state$503 - attribute \src "libresoc.v:0.0-0.0" - case 3'000 assign { } { } - assign $1\dmi0__din$next[63:0]$1496 $2\dmi0__din$next[63:0]$1497 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" - switch { \dmi0_datasr__oe \dmi0_addrsr__oe } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign $2\dmi0__din$next[63:0]$1497 \dmi0__din - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign $2\dmi0__din$next[63:0]$1497 \dmi0__din - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $2\dmi0__din$next[63:0]$1497 \dmi0_datasr__o - case - assign $2\dmi0__din$next[63:0]$1497 \dmi0__din - end - case - assign $1\dmi0__din$next[63:0]$1496 \dmi0__din - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $3\dmi0__din$next[63:0]$1498 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $3\dmi0__din$next[63:0]$1498 $1\dmi0__din$next[63:0]$1496 - end - sync always - update \dmi0__din$next $0\dmi0__din$next[63:0]$1495 - end - attribute \src "libresoc.v:45443.3-45463.6" - process $proc$libresoc.v:45443$1499 - assign { } { } - assign { } { } - assign { } { } - assign $0\dmi0_datasr__i$next[63:0]$1500 $3\dmi0_datasr__i$next[63:0]$1503 - attribute \src "libresoc.v:45444.5-45444.29" - switch \initial - attribute \src "libresoc.v:45444.9-45444.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - switch \fsm_state$503 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$19$next[31:0]$6690 $1\logical_op__data_len$18$next[3:0]$6685 $1\logical_op__is_signed$17$next[0:0]$6695 $1\logical_op__is_32bit$16$next[0:0]$6694 $1\logical_op__output_carry$15$next[0:0]$6698 $1\logical_op__write_cr0$14$next[0:0]$6701 $1\logical_op__invert_out$13$next[0:0]$6693 $1\logical_op__input_carry$12$next[1:0]$6689 $1\logical_op__zero_a$11$next[0:0]$6702 $1\logical_op__invert_in$10$next[0:0]$6692 $1\logical_op__oe__ok$9$next[0:0]$6697 $1\logical_op__oe__oe$8$next[0:0]$6696 $1\logical_op__rc__ok$7$next[0:0]$6699 $1\logical_op__rc__rc$6$next[0:0]$6700 $1\logical_op__imm_data__ok$5$next[0:0]$6688 $1\logical_op__imm_data__data$4$next[63:0]$6687 $1\logical_op__fn_unit$3$next[11:0]$6686 $1\logical_op__insn_type$2$next[6:0]$6691 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 2'1- assign { } { } - assign $1\dmi0_datasr__i$next[63:0]$1501 $2\dmi0_datasr__i$next[63:0]$1502 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" - switch \dmi0__ack_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dmi0_datasr__i$next[63:0]$1502 \dmi0__dout - case - assign $2\dmi0_datasr__i$next[63:0]$1502 \dmi0_datasr__i - end + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$19$next[31:0]$6690 $1\logical_op__data_len$18$next[3:0]$6685 $1\logical_op__is_signed$17$next[0:0]$6695 $1\logical_op__is_32bit$16$next[0:0]$6694 $1\logical_op__output_carry$15$next[0:0]$6698 $1\logical_op__write_cr0$14$next[0:0]$6701 $1\logical_op__invert_out$13$next[0:0]$6693 $1\logical_op__input_carry$12$next[1:0]$6689 $1\logical_op__zero_a$11$next[0:0]$6702 $1\logical_op__invert_in$10$next[0:0]$6692 $1\logical_op__oe__ok$9$next[0:0]$6697 $1\logical_op__oe__oe$8$next[0:0]$6696 $1\logical_op__rc__ok$7$next[0:0]$6699 $1\logical_op__rc__rc$6$next[0:0]$6700 $1\logical_op__imm_data__ok$5$next[0:0]$6688 $1\logical_op__imm_data__data$4$next[63:0]$6687 $1\logical_op__fn_unit$3$next[11:0]$6686 $1\logical_op__insn_type$2$next[6:0]$6691 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } case - assign $1\dmi0_datasr__i$next[63:0]$1501 \dmi0_datasr__i + assign $1\logical_op__data_len$18$next[3:0]$6685 \logical_op__data_len$18 + assign $1\logical_op__fn_unit$3$next[11:0]$6686 \logical_op__fn_unit$3 + assign $1\logical_op__imm_data__data$4$next[63:0]$6687 \logical_op__imm_data__data$4 + assign $1\logical_op__imm_data__ok$5$next[0:0]$6688 \logical_op__imm_data__ok$5 + assign $1\logical_op__input_carry$12$next[1:0]$6689 \logical_op__input_carry$12 + assign $1\logical_op__insn$19$next[31:0]$6690 \logical_op__insn$19 + assign $1\logical_op__insn_type$2$next[6:0]$6691 \logical_op__insn_type$2 + assign $1\logical_op__invert_in$10$next[0:0]$6692 \logical_op__invert_in$10 + assign $1\logical_op__invert_out$13$next[0:0]$6693 \logical_op__invert_out$13 + assign $1\logical_op__is_32bit$16$next[0:0]$6694 \logical_op__is_32bit$16 + assign $1\logical_op__is_signed$17$next[0:0]$6695 \logical_op__is_signed$17 + assign $1\logical_op__oe__oe$8$next[0:0]$6696 \logical_op__oe__oe$8 + assign $1\logical_op__oe__ok$9$next[0:0]$6697 \logical_op__oe__ok$9 + assign $1\logical_op__output_carry$15$next[0:0]$6698 \logical_op__output_carry$15 + assign $1\logical_op__rc__ok$7$next[0:0]$6699 \logical_op__rc__ok$7 + assign $1\logical_op__rc__rc$6$next[0:0]$6700 \logical_op__rc__rc$6 + assign $1\logical_op__write_cr0$14$next[0:0]$6701 \logical_op__write_cr0$14 + assign $1\logical_op__zero_a$11$next[0:0]$6702 \logical_op__zero_a$11 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dmi0_datasr__i$next[63:0]$1503 64'0000000000000000000000000000000000000000000000000000000000000000 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\logical_op__imm_data__data$4$next[63:0]$6703 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$5$next[0:0]$6704 1'0 + assign $2\logical_op__rc__rc$6$next[0:0]$6708 1'0 + assign $2\logical_op__rc__ok$7$next[0:0]$6707 1'0 + assign $2\logical_op__oe__oe$8$next[0:0]$6705 1'0 + assign $2\logical_op__oe__ok$9$next[0:0]$6706 1'0 case - assign $3\dmi0_datasr__i$next[63:0]$1503 $1\dmi0_datasr__i$next[63:0]$1501 + assign $2\logical_op__imm_data__data$4$next[63:0]$6703 $1\logical_op__imm_data__data$4$next[63:0]$6687 + assign $2\logical_op__imm_data__ok$5$next[0:0]$6704 $1\logical_op__imm_data__ok$5$next[0:0]$6688 + assign $2\logical_op__oe__oe$8$next[0:0]$6705 $1\logical_op__oe__oe$8$next[0:0]$6696 + assign $2\logical_op__oe__ok$9$next[0:0]$6706 $1\logical_op__oe__ok$9$next[0:0]$6697 + assign $2\logical_op__rc__ok$7$next[0:0]$6707 $1\logical_op__rc__ok$7$next[0:0]$6699 + assign $2\logical_op__rc__rc$6$next[0:0]$6708 $1\logical_op__rc__rc$6$next[0:0]$6700 end sync always - update \dmi0_datasr__i$next $0\dmi0_datasr__i$next[63:0]$1500 + update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$6667 + update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[11:0]$6668 + update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$6669 + update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$6670 + update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$6671 + update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$6672 + update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$6673 + update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$6674 + update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$6675 + update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$6676 + update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$6677 + update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$6678 + update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$6679 + update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$6680 + update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$6681 + update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$6682 + update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$6683 + update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$6684 end - attribute \src "libresoc.v:45464.3-45482.6" - process $proc$libresoc.v:45464$1504 - assign { } { } + attribute \src "libresoc.v:135103.3-135121.6" + process $proc$libresoc.v:135103$6709 assign { } { } assign { } { } assign { } { } assign { } { } + assign $0\o$20$next[63:0]$6710 $1\o$20$next[63:0]$6712 assign { } { } - assign $0\wb_dcache_en$next[0:0]$1505 $2\wb_dcache_en$next[0:0]$1509 - assign $0\wb_icache_en$next[0:0]$1506 $2\wb_icache_en$next[0:0]$1510 - attribute \src "libresoc.v:45465.5-45465.29" + assign $0\o_ok$21$next[0:0]$6711 $2\o_ok$21$next[0:0]$6714 + attribute \src "libresoc.v:135104.5-135104.29" switch \initial - attribute \src "libresoc.v:45465.9-45465.17" + attribute \src "libresoc.v:135104.9-135104.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:102" - switch \sr5__oe + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 assign { } { } assign { } { } - assign { $1\wb_dcache_en$next[0:0]$1507 $1\wb_icache_en$next[0:0]$1508 } \sr5__o - case - assign $1\wb_dcache_en$next[0:0]$1507 \wb_dcache_en - assign $1\wb_icache_en$next[0:0]$1508 \wb_icache_en - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + assign { $1\o_ok$21$next[0:0]$6713 $1\o$20$next[63:0]$6712 } { \o_ok$71 \o$70 } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'1- assign { } { } assign { } { } - assign $2\wb_icache_en$next[0:0]$1510 1'1 - assign $2\wb_dcache_en$next[0:0]$1509 1'1 - case - assign $2\wb_dcache_en$next[0:0]$1509 $1\wb_dcache_en$next[0:0]$1507 - assign $2\wb_icache_en$next[0:0]$1510 $1\wb_icache_en$next[0:0]$1508 - end - sync always - update \wb_dcache_en$next $0\wb_dcache_en$next[0:0]$1505 - update \wb_icache_en$next $0\wb_icache_en$next[0:0]$1506 - end - attribute \src "libresoc.v:45483.3-45492.6" - process $proc$libresoc.v:45483$1511 - assign { } { } - assign { } { } - assign $0\sr5__i[1:0] $1\sr5__i[1:0] - attribute \src "libresoc.v:45484.5-45484.29" - switch \initial - attribute \src "libresoc.v:45484.9-45484.17" - case 1'1 + assign { $1\o_ok$21$next[0:0]$6713 $1\o$20$next[63:0]$6712 } { \o_ok$71 \o$70 } case + assign $1\o$20$next[63:0]$6712 \o$20 + assign $1\o_ok$21$next[0:0]$6713 \o_ok$21 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:105" - switch \sr5__ie + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr5__i[1:0] { \wb_dcache_en \wb_icache_en } + assign $2\o_ok$21$next[0:0]$6714 1'0 case - assign $1\sr5__i[1:0] 2'00 + assign $2\o_ok$21$next[0:0]$6714 $1\o_ok$21$next[0:0]$6713 end sync always - update \sr5__i $0\sr5__i[1:0] + update \o$20$next $0\o$20$next[63:0]$6710 + update \o_ok$21$next $0\o_ok$21$next[0:0]$6711 end - attribute \src "libresoc.v:45493.3-45510.6" - process $proc$libresoc.v:45493$1512 + attribute \src "libresoc.v:135122.3-135140.6" + process $proc$libresoc.v:135122$6715 + assign { } { } + assign { } { } assign { } { } assign { } { } + assign $0\cr_a$22$next[3:0]$6716 $1\cr_a$22$next[3:0]$6718 assign { } { } - assign $0\io_sr$next[153:0]$1513 $2\io_sr$next[153:0]$1515 - attribute \src "libresoc.v:45494.5-45494.29" + assign $0\cr_a_ok$23$next[0:0]$6717 $2\cr_a_ok$23$next[0:0]$6720 + attribute \src "libresoc.v:135123.5-135123.29" switch \initial - attribute \src "libresoc.v:45494.9-45494.17" + attribute \src "libresoc.v:135123.9-135123.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:552" - switch { \io_update \io_shift \io_capture } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" - case 3'--1 + case 2'-1 assign { } { } - assign $1\io_sr$next[153:0]$1514 { \sdr_dq_15__core__oe \sdr_dq_15__core__o \sdr_dq_15__pad__i \sdr_dq_14__core__oe \sdr_dq_14__core__o \sdr_dq_14__pad__i \sdr_dq_13__core__oe \sdr_dq_13__core__o \sdr_dq_13__pad__i \sdr_dq_12__core__oe \sdr_dq_12__core__o \sdr_dq_12__pad__i \sdr_dq_11__core__oe \sdr_dq_11__core__o \sdr_dq_11__pad__i \sdr_dq_10__core__oe \sdr_dq_10__core__o \sdr_dq_10__pad__i \sdr_dq_9__core__oe \sdr_dq_9__core__o \sdr_dq_9__pad__i \sdr_dq_8__core__oe \sdr_dq_8__core__o \sdr_dq_8__pad__i \sdr_dm_1__core__oe \sdr_dm_1__core__o \sdr_dm_1__pad__i \sdr_a_12__core__o \sdr_a_11__core__o \sdr_a_10__core__o \sdr_cs_n__core__o \sdr_we_n__core__o \sdr_cas_n__core__o \sdr_ras_n__core__o \sdr_cke__core__o \sdr_clock__core__o \sdr_ba_1__core__o \sdr_ba_0__core__o \sdr_a_9__core__o \sdr_a_8__core__o \sdr_a_7__core__o \sdr_a_6__core__o \sdr_a_5__core__o \sdr_a_4__core__o \sdr_a_3__core__o \sdr_a_2__core__o \sdr_a_1__core__o \sdr_a_0__core__o \sdr_dq_7__core__oe \sdr_dq_7__core__o \sdr_dq_7__pad__i \sdr_dq_6__core__oe \sdr_dq_6__core__o \sdr_dq_6__pad__i \sdr_dq_5__core__oe \sdr_dq_5__core__o \sdr_dq_5__pad__i \sdr_dq_4__core__oe \sdr_dq_4__core__o \sdr_dq_4__pad__i \sdr_dq_3__core__oe \sdr_dq_3__core__o \sdr_dq_3__pad__i \sdr_dq_2__core__oe \sdr_dq_2__core__o \sdr_dq_2__pad__i \sdr_dq_1__core__oe \sdr_dq_1__core__o \sdr_dq_1__pad__i \sdr_dq_0__core__oe \sdr_dq_0__core__o \sdr_dq_0__pad__i \sdr_dm_0__core__o \sd0_data3__core__oe \sd0_data3__core__o \sd0_data3__pad__i \sd0_data2__core__oe \sd0_data2__core__o \sd0_data2__pad__i \sd0_data1__core__oe \sd0_data1__core__o \sd0_data1__pad__i \sd0_data0__core__oe \sd0_data0__core__o \sd0_data0__pad__i \sd0_clk__core__o \sd0_cmd__core__oe \sd0_cmd__core__o \sd0_cmd__pad__i \pwm_1__core__o \pwm_0__core__o \mtwi_scl__core__o \mtwi_sda__core__oe \mtwi_sda__core__o \mtwi_sda__pad__i \mspi1_miso__pad__i \mspi1_mosi__core__o \mspi1_cs_n__core__o \mspi1_clk__core__o \mspi0_miso__pad__i \mspi0_mosi__core__o \mspi0_cs_n__core__o \mspi0_clk__core__o \gpio_s7__core__oe \gpio_s7__core__o \gpio_s7__pad__i \gpio_s6__core__oe \gpio_s6__core__o \gpio_s6__pad__i \gpio_s5__core__oe \gpio_s5__core__o \gpio_s5__pad__i \gpio_s4__core__oe \gpio_s4__core__o \gpio_s4__pad__i \gpio_s3__core__oe \gpio_s3__core__o \gpio_s3__pad__i \gpio_s2__core__oe \gpio_s2__core__o \gpio_s2__pad__i \gpio_s1__core__oe \gpio_s1__core__o \gpio_s1__pad__i \gpio_s0__core__oe \gpio_s0__core__o \gpio_s0__pad__i \gpio_e15__core__oe \gpio_e15__core__o \gpio_e15__pad__i \gpio_e14__core__oe \gpio_e14__core__o \gpio_e14__pad__i \gpio_e13__core__oe \gpio_e13__core__o \gpio_e13__pad__i \gpio_e12__core__oe \gpio_e12__core__o \gpio_e12__pad__i \gpio_e11__core__oe \gpio_e11__core__o \gpio_e11__pad__i \gpio_e10__core__oe \gpio_e10__core__o \gpio_e10__pad__i \gpio_e9__core__oe \gpio_e9__core__o \gpio_e9__pad__i \gpio_e8__core__oe \gpio_e8__core__o \gpio_e8__pad__i \eint_2__pad__i \eint_1__pad__i \eint_0__pad__i } + assign { } { } + assign { $1\cr_a_ok$23$next[0:0]$6719 $1\cr_a$22$next[3:0]$6718 } { \cr_a_ok$73 \cr_a$72 } attribute \src "libresoc.v:0.0-0.0" - case 3'-1- + case 2'1- + assign { } { } assign { } { } - assign $1\io_sr$next[153:0]$1514 { \io_sr [152:0] \TAP_bus__tdi } + assign { $1\cr_a_ok$23$next[0:0]$6719 $1\cr_a$22$next[3:0]$6718 } { \cr_a_ok$73 \cr_a$72 } case - assign $1\io_sr$next[153:0]$1514 \io_sr + assign $1\cr_a$22$next[3:0]$6718 \cr_a$22 + assign $1\cr_a_ok$23$next[0:0]$6719 \cr_a_ok$23 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \posjtag_rst + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\io_sr$next[153:0]$1515 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $2\cr_a_ok$23$next[0:0]$6720 1'0 case - assign $2\io_sr$next[153:0]$1515 $1\io_sr$next[153:0]$1514 + assign $2\cr_a_ok$23$next[0:0]$6720 $1\cr_a_ok$23$next[0:0]$6719 end sync always - update \io_sr$next $0\io_sr$next[153:0]$1513 + update \cr_a$22$next $0\cr_a$22$next[3:0]$6716 + update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$6717 end - attribute \src "libresoc.v:45511.3-45531.6" - process $proc$libresoc.v:45511$1516 - assign { } { } - assign { } { } - assign { } { } - assign $0\io_bd$next[153:0]$1517 $2\io_bd$next[153:0]$1519 - attribute \src "libresoc.v:45512.5-45512.29" - switch \initial - attribute \src "libresoc.v:45512.9-45512.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:552" - switch { \io_update \io_shift \io_capture } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign $1\io_bd$next[153:0]$1518 \io_bd - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign $1\io_bd$next[153:0]$1518 \io_bd - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $1\io_bd$next[153:0]$1518 \io_sr - case - assign $1\io_bd$next[153:0]$1518 \io_bd - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \negjtag_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\io_bd$next[153:0]$1519 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\io_bd$next[153:0]$1519 $1\io_bd$next[153:0]$1518 - end - sync always - update \io_bd$next $0\io_bd$next[153:0]$1517 - end - connect \$9 $eq$libresoc.v:44454$1072_Y - connect \$99 $ternary$libresoc.v:44455$1073_Y - connect \$101 $ternary$libresoc.v:44456$1074_Y - connect \$103 $ternary$libresoc.v:44457$1075_Y - connect \$105 $ternary$libresoc.v:44458$1076_Y - connect \$107 $ternary$libresoc.v:44459$1077_Y - connect \$109 $ternary$libresoc.v:44460$1078_Y - connect \$111 $ternary$libresoc.v:44461$1079_Y - connect \$113 $ternary$libresoc.v:44462$1080_Y - connect \$115 $ternary$libresoc.v:44463$1081_Y - connect \$117 $ternary$libresoc.v:44464$1082_Y - connect \$11 $eq$libresoc.v:44465$1083_Y - connect \$119 $ternary$libresoc.v:44466$1084_Y - connect \$121 $ternary$libresoc.v:44467$1085_Y - connect \$123 $ternary$libresoc.v:44468$1086_Y - connect \$125 $ternary$libresoc.v:44469$1087_Y - connect \$127 $ternary$libresoc.v:44470$1088_Y - connect \$129 $ternary$libresoc.v:44471$1089_Y - connect \$131 $ternary$libresoc.v:44472$1090_Y - connect \$133 $ternary$libresoc.v:44473$1091_Y - connect \$135 $ternary$libresoc.v:44474$1092_Y - connect \$137 $ternary$libresoc.v:44475$1093_Y - connect \$13 $eq$libresoc.v:44476$1094_Y - connect \$139 $ternary$libresoc.v:44477$1095_Y - connect \$141 $ternary$libresoc.v:44478$1096_Y - connect \$143 $ternary$libresoc.v:44479$1097_Y - connect \$145 $ternary$libresoc.v:44480$1098_Y - connect \$147 $ternary$libresoc.v:44481$1099_Y - connect \$149 $ternary$libresoc.v:44482$1100_Y - connect \$151 $ternary$libresoc.v:44483$1101_Y - connect \$153 $ternary$libresoc.v:44484$1102_Y - connect \$155 $ternary$libresoc.v:44485$1103_Y - connect \$157 $ternary$libresoc.v:44486$1104_Y - connect \$15 $or$libresoc.v:44487$1105_Y - connect \$159 $ternary$libresoc.v:44488$1106_Y - connect \$161 $ternary$libresoc.v:44489$1107_Y - connect \$163 $ternary$libresoc.v:44490$1108_Y - connect \$165 $ternary$libresoc.v:44491$1109_Y - connect \$167 $ternary$libresoc.v:44492$1110_Y - connect \$169 $ternary$libresoc.v:44493$1111_Y - connect \$171 $ternary$libresoc.v:44494$1112_Y - connect \$173 $ternary$libresoc.v:44495$1113_Y - connect \$175 $ternary$libresoc.v:44496$1114_Y - connect \$177 $ternary$libresoc.v:44497$1115_Y - connect \$17 $and$libresoc.v:44498$1116_Y - connect \$179 $ternary$libresoc.v:44499$1117_Y - connect \$181 $ternary$libresoc.v:44500$1118_Y - connect \$183 $ternary$libresoc.v:44501$1119_Y - connect \$185 $ternary$libresoc.v:44502$1120_Y - connect \$187 $ternary$libresoc.v:44503$1121_Y - connect \$189 $ternary$libresoc.v:44504$1122_Y - connect \$191 $ternary$libresoc.v:44505$1123_Y - connect \$193 $ternary$libresoc.v:44506$1124_Y - connect \$195 $ternary$libresoc.v:44507$1125_Y - connect \$197 $ternary$libresoc.v:44508$1126_Y - connect \$1 $eq$libresoc.v:44509$1127_Y - connect \$19 $eq$libresoc.v:44510$1128_Y - connect \$199 $ternary$libresoc.v:44511$1129_Y - connect \$201 $ternary$libresoc.v:44512$1130_Y - connect \$203 $ternary$libresoc.v:44513$1131_Y - connect \$205 $ternary$libresoc.v:44514$1132_Y - connect \$207 $ternary$libresoc.v:44515$1133_Y - connect \$209 $ternary$libresoc.v:44516$1134_Y - connect \$211 $ternary$libresoc.v:44517$1135_Y - connect \$213 $ternary$libresoc.v:44518$1136_Y - connect \$215 $ternary$libresoc.v:44519$1137_Y - connect \$217 $ternary$libresoc.v:44520$1138_Y - connect \$21 $eq$libresoc.v:44521$1139_Y - connect \$219 $ternary$libresoc.v:44522$1140_Y - connect \$221 $ternary$libresoc.v:44523$1141_Y - connect \$223 $ternary$libresoc.v:44524$1142_Y - connect \$225 $ternary$libresoc.v:44525$1143_Y - connect \$227 $ternary$libresoc.v:44526$1144_Y - connect \$229 $ternary$libresoc.v:44527$1145_Y - connect \$231 $ternary$libresoc.v:44528$1146_Y - connect \$233 $ternary$libresoc.v:44529$1147_Y - connect \$235 $ternary$libresoc.v:44530$1148_Y - connect \$237 $ternary$libresoc.v:44531$1149_Y - connect \$23 $or$libresoc.v:44532$1150_Y - connect \$239 $ternary$libresoc.v:44533$1151_Y - connect \$241 $ternary$libresoc.v:44534$1152_Y - connect \$243 $ternary$libresoc.v:44535$1153_Y - connect \$245 $ternary$libresoc.v:44536$1154_Y - connect \$247 $ternary$libresoc.v:44537$1155_Y - connect \$249 $ternary$libresoc.v:44538$1156_Y - connect \$251 $ternary$libresoc.v:44539$1157_Y - connect \$253 $ternary$libresoc.v:44540$1158_Y - connect \$255 $ternary$libresoc.v:44541$1159_Y - connect \$257 $ternary$libresoc.v:44542$1160_Y - connect \$25 $eq$libresoc.v:44543$1161_Y - connect \$259 $ternary$libresoc.v:44544$1162_Y - connect \$261 $ternary$libresoc.v:44545$1163_Y - connect \$263 $ternary$libresoc.v:44546$1164_Y - connect \$265 $ternary$libresoc.v:44547$1165_Y - connect \$267 $ternary$libresoc.v:44548$1166_Y - connect \$269 $ternary$libresoc.v:44549$1167_Y - connect \$271 $ternary$libresoc.v:44550$1168_Y - connect \$273 $ternary$libresoc.v:44551$1169_Y - connect \$275 $ternary$libresoc.v:44552$1170_Y - connect \$277 $ternary$libresoc.v:44553$1171_Y - connect \$27 $or$libresoc.v:44554$1172_Y - connect \$279 $ternary$libresoc.v:44555$1173_Y - connect \$281 $ternary$libresoc.v:44556$1174_Y - connect \$283 $ternary$libresoc.v:44557$1175_Y - connect \$285 $ternary$libresoc.v:44558$1176_Y - connect \$287 $ternary$libresoc.v:44559$1177_Y - connect \$289 $ternary$libresoc.v:44560$1178_Y - connect \$291 $ternary$libresoc.v:44561$1179_Y - connect \$293 $ternary$libresoc.v:44562$1180_Y - connect \$295 $ternary$libresoc.v:44563$1181_Y - connect \$297 $ternary$libresoc.v:44564$1182_Y - connect \$29 $and$libresoc.v:44565$1183_Y - connect \$299 $ternary$libresoc.v:44566$1184_Y - connect \$301 $ternary$libresoc.v:44567$1185_Y - connect \$303 $ternary$libresoc.v:44568$1186_Y - connect \$305 $ternary$libresoc.v:44569$1187_Y - connect \$307 $ternary$libresoc.v:44570$1188_Y - connect \$309 $ternary$libresoc.v:44571$1189_Y - connect \$311 $ternary$libresoc.v:44572$1190_Y - connect \$313 $ternary$libresoc.v:44573$1191_Y - connect \$315 $ternary$libresoc.v:44574$1192_Y - connect \$317 $ternary$libresoc.v:44575$1193_Y - connect \$31 $and$libresoc.v:44576$1194_Y - connect \$319 $ternary$libresoc.v:44577$1195_Y - connect \$321 $ternary$libresoc.v:44578$1196_Y - connect \$323 $ternary$libresoc.v:44579$1197_Y - connect \$325 $ternary$libresoc.v:44580$1198_Y - connect \$327 $ternary$libresoc.v:44581$1199_Y - connect \$329 $ternary$libresoc.v:44582$1200_Y - connect \$331 $ternary$libresoc.v:44583$1201_Y - connect \$333 $ternary$libresoc.v:44584$1202_Y - connect \$335 $ternary$libresoc.v:44585$1203_Y - connect \$337 $ternary$libresoc.v:44586$1204_Y - connect \$33 $eq$libresoc.v:44587$1205_Y - connect \$339 $ternary$libresoc.v:44588$1206_Y - connect \$341 $ternary$libresoc.v:44589$1207_Y - connect \$343 $ternary$libresoc.v:44590$1208_Y - connect \$345 $ternary$libresoc.v:44591$1209_Y - connect \$347 $ternary$libresoc.v:44592$1210_Y - connect \$349 $ternary$libresoc.v:44593$1211_Y - connect \$351 $ternary$libresoc.v:44594$1212_Y - connect \$353 $ternary$libresoc.v:44595$1213_Y - connect \$355 $ternary$libresoc.v:44596$1214_Y - connect \$357 $ternary$libresoc.v:44597$1215_Y - connect \$35 $eq$libresoc.v:44598$1216_Y - connect \$359 $eq$libresoc.v:44599$1217_Y - connect \$361 $eq$libresoc.v:44600$1218_Y - connect \$363 $or$libresoc.v:44601$1219_Y - connect \$365 $eq$libresoc.v:44602$1220_Y - connect \$367 $or$libresoc.v:44603$1221_Y - connect \$369 $and$libresoc.v:44604$1222_Y - connect \$371 $eq$libresoc.v:44605$1223_Y - connect \$373 $ne$libresoc.v:44606$1224_Y - connect \$375 $and$libresoc.v:44607$1225_Y - connect \$377 $ne$libresoc.v:44608$1226_Y - connect \$37 $or$libresoc.v:44609$1227_Y - connect \$379 $and$libresoc.v:44610$1228_Y - connect \$381 $ne$libresoc.v:44611$1229_Y - connect \$383 $and$libresoc.v:44612$1230_Y - connect \$385 $not$libresoc.v:44613$1231_Y - connect \$387 $and$libresoc.v:44614$1232_Y - connect \$389 $eq$libresoc.v:44615$1233_Y - connect \$391 $ne$libresoc.v:44616$1234_Y - connect \$393 $and$libresoc.v:44617$1235_Y - connect \$395 $ne$libresoc.v:44618$1236_Y - connect \$397 $and$libresoc.v:44619$1237_Y - connect \$3 $eq$libresoc.v:44620$1238_Y - connect \$39 $eq$libresoc.v:44621$1239_Y - connect \$399 $ne$libresoc.v:44622$1240_Y - connect \$401 $and$libresoc.v:44623$1241_Y - connect \$403 $not$libresoc.v:44624$1242_Y - connect \$405 $and$libresoc.v:44625$1243_Y - connect \$407 $eq$libresoc.v:44626$1244_Y - connect \$409 $eq$libresoc.v:44627$1245_Y - connect \$411 $ne$libresoc.v:44628$1246_Y - connect \$413 $and$libresoc.v:44629$1247_Y - connect \$415 $ne$libresoc.v:44630$1248_Y - connect \$417 $and$libresoc.v:44631$1249_Y - connect \$41 $or$libresoc.v:44632$1250_Y - connect \$419 $ne$libresoc.v:44633$1251_Y - connect \$421 $and$libresoc.v:44634$1252_Y - connect \$423 $not$libresoc.v:44635$1253_Y - connect \$425 $and$libresoc.v:44636$1254_Y - connect \$427 $eq$libresoc.v:44637$1255_Y - connect \$429 $ne$libresoc.v:44638$1256_Y - connect \$431 $and$libresoc.v:44639$1257_Y - connect \$433 $ne$libresoc.v:44640$1258_Y - connect \$435 $and$libresoc.v:44641$1259_Y - connect \$437 $ne$libresoc.v:44642$1260_Y - connect \$43 $and$libresoc.v:44643$1261_Y - connect \$439 $and$libresoc.v:44644$1262_Y - connect \$441 $not$libresoc.v:44645$1263_Y - connect \$443 $and$libresoc.v:44646$1264_Y - connect \$445 $eq$libresoc.v:44647$1265_Y - connect \$447 $eq$libresoc.v:44648$1266_Y - connect \$449 $ne$libresoc.v:44649$1267_Y - connect \$451 $and$libresoc.v:44650$1268_Y - connect \$453 $ne$libresoc.v:44651$1269_Y - connect \$455 $and$libresoc.v:44652$1270_Y - connect \$457 $ne$libresoc.v:44653$1271_Y - connect \$45 $and$libresoc.v:44654$1272_Y - connect \$459 $and$libresoc.v:44655$1273_Y - connect \$461 $not$libresoc.v:44656$1274_Y - connect \$463 $and$libresoc.v:44657$1275_Y - connect \$465 $eq$libresoc.v:44658$1276_Y - connect \$467 $ne$libresoc.v:44659$1277_Y - connect \$469 $and$libresoc.v:44660$1278_Y - connect \$471 $ne$libresoc.v:44661$1279_Y - connect \$473 $and$libresoc.v:44662$1280_Y - connect \$475 $ne$libresoc.v:44663$1281_Y - connect \$477 $and$libresoc.v:44664$1282_Y - connect \$47 $eq$libresoc.v:44665$1283_Y - connect \$479 $not$libresoc.v:44666$1284_Y - connect \$481 $and$libresoc.v:44667$1285_Y - connect \$484 $eq$libresoc.v:44668$1286_Y - connect \$483 $not$libresoc.v:44669$1287_Y - connect \$487 $eq$libresoc.v:44670$1288_Y - connect \$489 $eq$libresoc.v:44671$1289_Y - connect \$491 $or$libresoc.v:44672$1290_Y - connect \$493 $eq$libresoc.v:44673$1291_Y - connect \$496 $add$libresoc.v:44674$1292_Y - connect \$49 $eq$libresoc.v:44675$1293_Y - connect \$499 $add$libresoc.v:44676$1294_Y - connect \$501 $pos$libresoc.v:44677$1296_Y - connect \$504 $eq$libresoc.v:44678$1297_Y - connect \$506 $eq$libresoc.v:44679$1298_Y - connect \$508 $or$libresoc.v:44680$1299_Y - connect \$510 $eq$libresoc.v:44681$1300_Y - connect \$513 $add$libresoc.v:44682$1301_Y - connect \$516 $add$libresoc.v:44683$1302_Y - connect \$51 $ternary$libresoc.v:44684$1303_Y - connect \$53 $ternary$libresoc.v:44685$1304_Y - connect \$55 $ternary$libresoc.v:44686$1305_Y - connect \$57 $ternary$libresoc.v:44687$1306_Y - connect \$5 $or$libresoc.v:44688$1307_Y - connect \$59 $ternary$libresoc.v:44689$1308_Y - connect \$61 $ternary$libresoc.v:44690$1309_Y - connect \$63 $ternary$libresoc.v:44691$1310_Y - connect \$65 $ternary$libresoc.v:44692$1311_Y - connect \$67 $ternary$libresoc.v:44693$1312_Y - connect \$69 $ternary$libresoc.v:44694$1313_Y - connect \$71 $ternary$libresoc.v:44695$1314_Y - connect \$73 $ternary$libresoc.v:44696$1315_Y - connect \$75 $ternary$libresoc.v:44697$1316_Y - connect \$77 $ternary$libresoc.v:44698$1317_Y - connect \$7 $and$libresoc.v:44699$1318_Y - connect \$79 $ternary$libresoc.v:44700$1319_Y - connect \$81 $ternary$libresoc.v:44701$1320_Y - connect \$83 $ternary$libresoc.v:44702$1321_Y - connect \$85 $ternary$libresoc.v:44703$1322_Y - connect \$87 $ternary$libresoc.v:44704$1323_Y - connect \$89 $ternary$libresoc.v:44705$1324_Y - connect \$91 $ternary$libresoc.v:44706$1325_Y - connect \$93 $ternary$libresoc.v:44707$1326_Y - connect \$95 $ternary$libresoc.v:44708$1327_Y - connect \$97 $ternary$libresoc.v:44709$1328_Y - connect \$495 \$496 - connect \$498 \$499 - connect \$512 \$513 - connect \$515 \$516 - connect \sr5__ie 1'0 - connect \sr0__i \sr0__o - connect \dmi0__we_i \$510 - connect \dmi0__req_i \$508 - connect \dmi0_addrsr__i \$501 - connect \jtag_wb__we \$493 - connect \jtag_wb__stb \$491 - connect \jtag_wb__cyc \$483 - connect \jtag_wb__sel 1'1 - connect \jtag_wb_addrsr__i \jtag_wb__adr - connect \sr5_update \$477 - connect \sr5_shift \$473 - connect \sr5_capture \$469 - connect \sr5_isir \$465 - connect \sr5__o \sr5_reg - connect \dmi0_datasr_update \$459 - connect \dmi0_datasr_shift \$455 - connect \dmi0_datasr_capture \$451 - connect \dmi0_datasr_isir { \$447 \$445 } - connect \dmi0_datasr__o \dmi0_datasr_reg - connect \dmi0_addrsr_update \$439 - connect \dmi0_addrsr_shift \$435 - connect \dmi0_addrsr_capture \$431 - connect \dmi0_addrsr_isir \$427 - connect \dmi0_addrsr__o \dmi0_addrsr_reg - connect \jtag_wb_datasr_update \$421 - connect \jtag_wb_datasr_shift \$417 - connect \jtag_wb_datasr_capture \$413 - connect \jtag_wb_datasr_isir { \$409 \$407 } - connect \jtag_wb_datasr__o \jtag_wb_datasr_reg - connect \jtag_wb_addrsr_update \$401 - connect \jtag_wb_addrsr_shift \$397 - connect \jtag_wb_addrsr_capture \$393 - connect \jtag_wb_addrsr_isir \$389 - connect \jtag_wb_addrsr__o \jtag_wb_addrsr_reg - connect \sr0_update \$383 - connect \sr0_shift \$379 - connect \sr0_capture \$375 - connect \sr0_isir \$371 - connect \sr0__o \sr0_reg - connect \sdr_dq_15__pad__oe \$357 - connect \sdr_dq_15__pad__o \$355 - connect \sdr_dq_15__core__i \$353 - connect \sdr_dq_14__pad__oe \$351 - connect \sdr_dq_14__pad__o \$349 - connect \sdr_dq_14__core__i \$347 - connect \sdr_dq_13__pad__oe \$345 - connect \sdr_dq_13__pad__o \$343 - connect \sdr_dq_13__core__i \$341 - connect \sdr_dq_12__pad__oe \$339 - connect \sdr_dq_12__pad__o \$337 - connect \sdr_dq_12__core__i \$335 - connect \sdr_dq_11__pad__oe \$333 - connect \sdr_dq_11__pad__o \$331 - connect \sdr_dq_11__core__i \$329 - connect \sdr_dq_10__pad__oe \$327 - connect \sdr_dq_10__pad__o \$325 - connect \sdr_dq_10__core__i \$323 - connect \sdr_dq_9__pad__oe \$321 - connect \sdr_dq_9__pad__o \$319 - connect \sdr_dq_9__core__i \$317 - connect \sdr_dq_8__pad__oe \$315 - connect \sdr_dq_8__pad__o \$313 - connect \sdr_dq_8__core__i \$311 - connect \sdr_dm_1__pad__oe \$309 - connect \sdr_dm_1__pad__o \$307 - connect \sdr_dm_1__core__i \$305 - connect \sdr_a_12__pad__o \$303 - connect \sdr_a_11__pad__o \$301 - connect \sdr_a_10__pad__o \$299 - connect \sdr_cs_n__pad__o \$297 - connect \sdr_we_n__pad__o \$295 - connect \sdr_cas_n__pad__o \$293 - connect \sdr_ras_n__pad__o \$291 - connect \sdr_cke__pad__o \$289 - connect \sdr_clock__pad__o \$287 - connect \sdr_ba_1__pad__o \$285 - connect \sdr_ba_0__pad__o \$283 - connect \sdr_a_9__pad__o \$281 - connect \sdr_a_8__pad__o \$279 - connect \sdr_a_7__pad__o \$277 - connect \sdr_a_6__pad__o \$275 - connect \sdr_a_5__pad__o \$273 - connect \sdr_a_4__pad__o \$271 - connect \sdr_a_3__pad__o \$269 - connect \sdr_a_2__pad__o \$267 - connect \sdr_a_1__pad__o \$265 - connect \sdr_a_0__pad__o \$263 - connect \sdr_dq_7__pad__oe \$261 - connect \sdr_dq_7__pad__o \$259 - connect \sdr_dq_7__core__i \$257 - connect \sdr_dq_6__pad__oe \$255 - connect \sdr_dq_6__pad__o \$253 - connect \sdr_dq_6__core__i \$251 - connect \sdr_dq_5__pad__oe \$249 - connect \sdr_dq_5__pad__o \$247 - connect \sdr_dq_5__core__i \$245 - connect \sdr_dq_4__pad__oe \$243 - connect \sdr_dq_4__pad__o \$241 - connect \sdr_dq_4__core__i \$239 - connect \sdr_dq_3__pad__oe \$237 - connect \sdr_dq_3__pad__o \$235 - connect \sdr_dq_3__core__i \$233 - connect \sdr_dq_2__pad__oe \$231 - connect \sdr_dq_2__pad__o \$229 - connect \sdr_dq_2__core__i \$227 - connect \sdr_dq_1__pad__oe \$225 - connect \sdr_dq_1__pad__o \$223 - connect \sdr_dq_1__core__i \$221 - connect \sdr_dq_0__pad__oe \$219 - connect \sdr_dq_0__pad__o \$217 - connect \sdr_dq_0__core__i \$215 - connect \sdr_dm_0__pad__o \$213 - connect \sd0_data3__pad__oe \$211 - connect \sd0_data3__pad__o \$209 - connect \sd0_data3__core__i \$207 - connect \sd0_data2__pad__oe \$205 - connect \sd0_data2__pad__o \$203 - connect \sd0_data2__core__i \$201 - connect \sd0_data1__pad__oe \$199 - connect \sd0_data1__pad__o \$197 - connect \sd0_data1__core__i \$195 - connect \sd0_data0__pad__oe \$193 - connect \sd0_data0__pad__o \$191 - connect \sd0_data0__core__i \$189 - connect \sd0_clk__pad__o \$187 - connect \sd0_cmd__pad__oe \$185 - connect \sd0_cmd__pad__o \$183 - connect \sd0_cmd__core__i \$181 - connect \pwm_1__pad__o \$179 - connect \pwm_0__pad__o \$177 - connect \mtwi_scl__pad__o \$175 - connect \mtwi_sda__pad__oe \$173 - connect \mtwi_sda__pad__o \$171 - connect \mtwi_sda__core__i \$169 - connect \mspi1_miso__core__i \$167 - connect \mspi1_mosi__pad__o \$165 - connect \mspi1_cs_n__pad__o \$163 - connect \mspi1_clk__pad__o \$161 - connect \mspi0_miso__core__i \$159 - connect \mspi0_mosi__pad__o \$157 - connect \mspi0_cs_n__pad__o \$155 - connect \mspi0_clk__pad__o \$153 - connect \gpio_s7__pad__oe \$151 - connect \gpio_s7__pad__o \$149 - connect \gpio_s7__core__i \$147 - connect \gpio_s6__pad__oe \$145 - connect \gpio_s6__pad__o \$143 - connect \gpio_s6__core__i \$141 - connect \gpio_s5__pad__oe \$139 - connect \gpio_s5__pad__o \$137 - connect \gpio_s5__core__i \$135 - connect \gpio_s4__pad__oe \$133 - connect \gpio_s4__pad__o \$131 - connect \gpio_s4__core__i \$129 - connect \gpio_s3__pad__oe \$127 - connect \gpio_s3__pad__o \$125 - connect \gpio_s3__core__i \$123 - connect \gpio_s2__pad__oe \$121 - connect \gpio_s2__pad__o \$119 - connect \gpio_s2__core__i \$117 - connect \gpio_s1__pad__oe \$115 - connect \gpio_s1__pad__o \$113 - connect \gpio_s1__core__i \$111 - connect \gpio_s0__pad__oe \$109 - connect \gpio_s0__pad__o \$107 - connect \gpio_s0__core__i \$105 - connect \gpio_e15__pad__oe \$103 - connect \gpio_e15__pad__o \$101 - connect \gpio_e15__core__i \$99 - connect \gpio_e14__pad__oe \$97 - connect \gpio_e14__pad__o \$95 - connect \gpio_e14__core__i \$93 - connect \gpio_e13__pad__oe \$91 - connect \gpio_e13__pad__o \$89 - connect \gpio_e13__core__i \$87 - connect \gpio_e12__pad__oe \$85 - connect \gpio_e12__pad__o \$83 - connect \gpio_e12__core__i \$81 - connect \gpio_e11__pad__oe \$79 - connect \gpio_e11__pad__o \$77 - connect \gpio_e11__core__i \$75 - connect \gpio_e10__pad__oe \$73 - connect \gpio_e10__pad__o \$71 - connect \gpio_e10__core__i \$69 - connect \gpio_e9__pad__oe \$67 - connect \gpio_e9__pad__o \$65 - connect \gpio_e9__core__i \$63 - connect \gpio_e8__pad__oe \$61 - connect \gpio_e8__pad__o \$59 - connect \gpio_e8__core__i \$57 - connect \eint_2__core__i \$55 - connect \eint_1__core__i \$53 - connect \eint_0__core__i \$51 - connect \io_bd2core \$49 - connect \io_bd2io \$47 - connect \io_update \$45 - connect \io_shift \$31 - connect \io_capture \$17 - connect \_idblock_id_bypass \$9 - connect \_idblock_select_id \$7 + connect \$49 $and$libresoc.v:134925$6611_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \cr_a_ok$73 \cr_a$72 } { \output_cr_a_ok \output_cr_a$45 } + connect { \o_ok$71 \o$70 } { \output_o_ok$44 \output_o$43 } + connect { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } { \output_logical_op__insn$42 \output_logical_op__data_len$41 \output_logical_op__is_signed$40 \output_logical_op__is_32bit$39 \output_logical_op__output_carry$38 \output_logical_op__write_cr0$37 \output_logical_op__invert_out$36 \output_logical_op__input_carry$35 \output_logical_op__zero_a$34 \output_logical_op__invert_in$33 \output_logical_op__oe__ok$32 \output_logical_op__oe__oe$31 \output_logical_op__rc__ok$30 \output_logical_op__rc__rc$29 \output_logical_op__imm_data__ok$28 \output_logical_op__imm_data__data$27 \output_logical_op__fn_unit$26 \output_logical_op__insn_type$25 } + connect \muxid$51 \output_muxid$24 + connect \p_valid_i_p_ready_o \$49 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$48 \p_valid_i + connect { \xer_so_ok$47 \output_xer_so } { \xer_so_ok \xer_so } + connect { \cr_a_ok$46 \output_cr_a } { \cr_a_ok \cr_a } + connect { \output_o_ok \output_o } { \o_ok \o } + connect { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in \output_logical_op__oe__ok \output_logical_op__oe__oe \output_logical_op__rc__ok \output_logical_op__rc__rc \output_logical_op__imm_data__ok \output_logical_op__imm_data__data \output_logical_op__fn_unit \output_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \output_muxid \muxid end attribute \src "ls180.v:4.1-10555.10" attribute \cells_not_processed 1 @@ -82689,24 +231335,24 @@ module \ls180 wire \builder_sync_rhs_array_muxed6 attribute \src "ls180.v:1894.6-1894.18" wire \builder_wait - attribute \src "ls180.v:42.19-42.23" - wire width 3 input 38 \eint - attribute \src "ls180.v:157.12-157.18" + attribute \src "ls180.v:36.19-36.23" + wire width 3 input 32 \eint + attribute \src "ls180.v:153.12-153.18" wire width 3 \eint_1 - attribute \src "ls180.v:28.20-28.26" - wire width 16 input 24 \gpio_i - attribute \src "ls180.v:29.21-29.27" - wire width 16 output 25 \gpio_o - attribute \src "ls180.v:30.21-30.28" - wire width 16 output 26 \gpio_oe - attribute \src "ls180.v:35.14-35.21" - wire output 31 \i2c_scl - attribute \src "ls180.v:36.13-36.22" - wire input 32 \i2c_sda_i - attribute \src "ls180.v:37.14-37.23" - wire output 33 \i2c_sda_o - attribute \src "ls180.v:38.14-38.24" - wire output 34 \i2c_sda_oe + attribute \src "ls180.v:33.20-33.26" + wire width 16 input 29 \gpio_i + attribute \src "ls180.v:34.21-34.27" + wire width 16 output 30 \gpio_o + attribute \src "ls180.v:35.21-35.28" + wire width 16 output 31 \gpio_oe + attribute \src "ls180.v:29.14-29.21" + wire output 25 \i2c_scl + attribute \src "ls180.v:30.13-30.22" + wire input 26 \i2c_sda_i + attribute \src "ls180.v:31.14-31.23" + wire output 27 \i2c_sda_o + attribute \src "ls180.v:32.14-32.24" + wire output 28 \i2c_sda_oe attribute \src "ls180.v:49.13-49.21" wire input 45 \jtag_tck attribute \src "ls180.v:50.13-50.21" @@ -82999,65 +231645,65 @@ module \ls180 wire width 64 \main_libresocsim_libresoc2 attribute \src "ls180.v:123.12-123.45" wire width 2 \main_libresocsim_libresoc_clk_sel - attribute \src "ls180.v:145.13-145.67" + attribute \src "ls180.v:150.13-150.67" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_i - attribute \src "ls180.v:146.13-146.67" + attribute \src "ls180.v:151.13-151.67" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_o - attribute \src "ls180.v:147.13-147.68" + attribute \src "ls180.v:152.13-152.68" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe - attribute \src "ls180.v:152.6-152.61" + attribute \src "ls180.v:146.6-146.61" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl - attribute \src "ls180.v:153.6-153.63" + attribute \src "ls180.v:147.6-147.63" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i - attribute \src "ls180.v:154.6-154.63" + attribute \src "ls180.v:148.6-148.63" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o - attribute \src "ls180.v:155.6-155.64" + attribute \src "ls180.v:149.6-149.64" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe - attribute \src "ls180.v:125.6-125.64" + attribute \src "ls180.v:137.6-137.64" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk - attribute \src "ls180.v:126.6-126.66" + attribute \src "ls180.v:138.6-138.66" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i - attribute \src "ls180.v:127.6-127.66" + attribute \src "ls180.v:139.6-139.66" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o - attribute \src "ls180.v:128.6-128.67" + attribute \src "ls180.v:140.6-140.67" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe - attribute \src "ls180.v:133.13-133.68" + attribute \src "ls180.v:125.13-125.68" wire width 13 \main_libresocsim_libresoc_constraintmanager_obj_sdram_a - attribute \src "ls180.v:142.12-142.68" + attribute \src "ls180.v:134.12-134.68" wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba - attribute \src "ls180.v:139.6-139.65" + attribute \src "ls180.v:131.6-131.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n - attribute \src "ls180.v:141.6-141.63" + attribute \src "ls180.v:133.6-133.63" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke - attribute \src "ls180.v:140.6-140.64" + attribute \src "ls180.v:132.6-132.64" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n - attribute \src "ls180.v:143.12-143.68" + attribute \src "ls180.v:135.12-135.68" wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm - attribute \src "ls180.v:134.13-134.71" + attribute \src "ls180.v:126.13-126.71" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i - attribute \src "ls180.v:135.13-135.71" + attribute \src "ls180.v:127.13-127.71" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o - attribute \src "ls180.v:136.6-136.65" + attribute \src "ls180.v:128.6-128.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - attribute \src "ls180.v:138.6-138.65" + attribute \src "ls180.v:130.6-130.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n - attribute \src "ls180.v:137.6-137.64" + attribute \src "ls180.v:129.6-129.64" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n - attribute \src "ls180.v:129.6-129.67" + attribute \src "ls180.v:142.6-142.67" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk - attribute \src "ls180.v:131.6-131.68" + attribute \src "ls180.v:144.6-144.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n - attribute \src "ls180.v:132.6-132.68" + attribute \src "ls180.v:145.6-145.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso - attribute \src "ls180.v:130.6-130.68" + attribute \src "ls180.v:143.6-143.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi - attribute \src "ls180.v:148.6-148.67" + attribute \src "ls180.v:154.6-154.67" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk - attribute \src "ls180.v:150.6-150.68" + attribute \src "ls180.v:156.6-156.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n - attribute \src "ls180.v:151.6-151.68" + attribute \src "ls180.v:157.6-157.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso - attribute \src "ls180.v:149.6-149.68" + attribute \src "ls180.v:155.6-155.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi attribute \src "ls180.v:72.5-72.39" wire \main_libresocsim_libresoc_dbus_ack @@ -86227,50 +234873,50 @@ module \ls180 wire width 24 input 48 \nc attribute \src "ls180.v:247.6-247.13" wire \por_clk - attribute \src "ls180.v:41.19-41.22" - wire width 2 output 37 \pwm - attribute \src "ls180.v:156.12-156.17" + attribute \src "ls180.v:24.19-24.22" + wire width 2 output 20 \pwm + attribute \src "ls180.v:141.12-141.17" wire width 2 \pwm_1 - attribute \src "ls180.v:5.13-5.23" - wire output 1 \sdcard_clk - attribute \src "ls180.v:6.13-6.25" - wire input 2 \sdcard_cmd_i - attribute \src "ls180.v:7.13-7.25" - wire output 3 \sdcard_cmd_o - attribute \src "ls180.v:8.13-8.26" - wire output 4 \sdcard_cmd_oe - attribute \src "ls180.v:9.19-9.32" - wire width 4 input 5 \sdcard_data_i - attribute \src "ls180.v:10.19-10.32" - wire width 4 output 6 \sdcard_data_o - attribute \src "ls180.v:11.13-11.27" - wire output 7 \sdcard_data_oe - attribute \src "ls180.v:16.20-16.27" - wire width 13 output 12 \sdram_a - attribute \src "ls180.v:25.19-25.27" - wire width 2 output 21 \sdram_ba - attribute \src "ls180.v:22.13-22.24" - wire output 18 \sdram_cas_n - attribute \src "ls180.v:24.13-24.22" - wire output 20 \sdram_cke - attribute \src "ls180.v:27.13-27.24" - wire output 23 \sdram_clock - attribute \src "ls180.v:144.6-144.19" + attribute \src "ls180.v:17.13-17.23" + wire output 13 \sdcard_clk + attribute \src "ls180.v:18.13-18.25" + wire input 14 \sdcard_cmd_i + attribute \src "ls180.v:19.13-19.25" + wire output 15 \sdcard_cmd_o + attribute \src "ls180.v:20.13-20.26" + wire output 16 \sdcard_cmd_oe + attribute \src "ls180.v:21.19-21.32" + wire width 4 input 17 \sdcard_data_i + attribute \src "ls180.v:22.19-22.32" + wire width 4 output 18 \sdcard_data_o + attribute \src "ls180.v:23.13-23.27" + wire output 19 \sdcard_data_oe + attribute \src "ls180.v:5.20-5.27" + wire width 13 output 1 \sdram_a + attribute \src "ls180.v:14.19-14.27" + wire width 2 output 10 \sdram_ba + attribute \src "ls180.v:11.13-11.24" + wire output 7 \sdram_cas_n + attribute \src "ls180.v:13.13-13.22" + wire output 9 \sdram_cke + attribute \src "ls180.v:16.13-16.24" + wire output 12 \sdram_clock + attribute \src "ls180.v:136.6-136.19" wire \sdram_clock_1 - attribute \src "ls180.v:23.13-23.23" - wire output 19 \sdram_cs_n - attribute \src "ls180.v:26.19-26.27" - wire width 2 output 22 \sdram_dm - attribute \src "ls180.v:17.20-17.30" - wire width 16 input 13 \sdram_dq_i - attribute \src "ls180.v:18.20-18.30" - wire width 16 output 14 \sdram_dq_o - attribute \src "ls180.v:19.13-19.24" - wire output 15 \sdram_dq_oe - attribute \src "ls180.v:21.13-21.24" - wire output 17 \sdram_ras_n - attribute \src "ls180.v:20.13-20.23" - wire output 16 \sdram_we_n + attribute \src "ls180.v:12.13-12.23" + wire output 8 \sdram_cs_n + attribute \src "ls180.v:15.19-15.27" + wire width 2 output 11 \sdram_dm + attribute \src "ls180.v:6.20-6.30" + wire width 16 input 2 \sdram_dq_i + attribute \src "ls180.v:7.20-7.30" + wire width 16 output 3 \sdram_dq_o + attribute \src "ls180.v:8.13-8.24" + wire output 4 \sdram_dq_oe + attribute \src "ls180.v:10.13-10.24" + wire output 6 \sdram_ras_n + attribute \src "ls180.v:9.13-9.23" + wire output 5 \sdram_we_n attribute \src "ls180.v:2643.6-2643.15" wire \sdrio_clk attribute \src "ls180.v:2644.6-2644.17" @@ -86409,22 +235055,22 @@ module \ls180 wire \sdrio_clk_8 attribute \src "ls180.v:2652.6-2652.17" wire \sdrio_clk_9 - attribute \src "ls180.v:12.13-12.26" - wire output 8 \spimaster_clk - attribute \src "ls180.v:14.13-14.27" - wire output 10 \spimaster_cs_n - attribute \src "ls180.v:15.13-15.27" - wire input 11 \spimaster_miso - attribute \src "ls180.v:13.13-13.27" - wire output 9 \spimaster_mosi - attribute \src "ls180.v:31.13-31.26" - wire output 27 \spisdcard_clk - attribute \src "ls180.v:33.13-33.27" - wire output 29 \spisdcard_cs_n - attribute \src "ls180.v:34.13-34.27" - wire input 30 \spisdcard_miso - attribute \src "ls180.v:32.13-32.27" - wire output 28 \spisdcard_mosi + attribute \src "ls180.v:25.13-25.26" + wire output 21 \spimaster_clk + attribute \src "ls180.v:27.13-27.27" + wire output 23 \spimaster_cs_n + attribute \src "ls180.v:28.13-28.27" + wire input 24 \spimaster_miso + attribute \src "ls180.v:26.13-26.27" + wire output 22 \spimaster_mosi + attribute \src "ls180.v:37.13-37.26" + wire output 33 \spisdcard_clk + attribute \src "ls180.v:39.13-39.27" + wire output 35 \spisdcard_cs_n + attribute \src "ls180.v:40.13-40.27" + wire input 36 \spisdcard_miso + attribute \src "ls180.v:38.13-38.27" + wire output 34 \spisdcard_mosi attribute \src "ls180.v:43.13-43.20" wire input 39 \sys_clk attribute \src "ls180.v:245.6-245.15" @@ -86439,10 +235085,10 @@ module \ls180 wire input 40 \sys_rst attribute \src "ls180.v:246.6-246.15" wire \sys_rst_1 - attribute \src "ls180.v:40.13-40.20" - wire input 36 \uart_rx - attribute \src "ls180.v:39.13-39.20" - wire output 35 \uart_tx + attribute \src "ls180.v:42.13-42.20" + wire input 38 \uart_rx + attribute \src "ls180.v:41.13-41.20" + wire output 37 \uart_tx attribute \src "ls180.v:10041.12-10041.15" memory width 32 size 128 \mem attribute \src "ls180.v:10061.12-10061.19" @@ -126151,11 +274797,6 @@ module \ls180 assign $0\sdcard_data_o[3:0] [3] \main_sdphy_sdpads_data_o [3] assign $0\main_sdphy_sdpads_data_i[3:0] [3] \sdcard_data_i [3] sync posedge \sdrio_clk - update \sdcard_clk $0\sdcard_clk[0:0] - update \sdcard_cmd_o $0\sdcard_cmd_o[0:0] - update \sdcard_cmd_oe $0\sdcard_cmd_oe[0:0] - update \sdcard_data_o $0\sdcard_data_o[3:0] - update \sdcard_data_oe $0\sdcard_data_oe[0:0] update \sdram_a $0\sdram_a[12:0] update \sdram_dq_o $0\sdram_dq_o[15:0] update \sdram_dq_oe $0\sdram_dq_oe[0:0] @@ -126167,6 +274808,11 @@ module \ls180 update \sdram_ba $0\sdram_ba[1:0] update \sdram_dm $0\sdram_dm[1:0] update \sdram_clock $0\sdram_clock[0:0] + update \sdcard_clk $0\sdcard_clk[0:0] + update \sdcard_cmd_o $0\sdcard_cmd_o[0:0] + update \sdcard_cmd_oe $0\sdcard_cmd_oe[0:0] + update \sdcard_data_o $0\sdcard_data_o[3:0] + update \sdcard_data_oe $0\sdcard_data_oe[0:0] update \main_dfi_p0_rddata $0\main_dfi_p0_rddata[15:0] update \main_sdphy_sdpads_cmd_i $0\main_sdphy_sdpads_cmd_i[0:0] update \main_sdphy_sdpads_data_i $0\main_sdphy_sdpads_data_i[3:0] @@ -126221,6 +274867,7 @@ module \ls180 end attribute \src "ls180.v:7427.1-10039.4" process $proc$ls180.v:7427$2374 + assign $0\pwm[1:0] \pwm assign $0\spimaster_clk[0:0] \spimaster_clk assign $0\spimaster_mosi[0:0] \spimaster_mosi assign { } { } @@ -126228,7 +274875,6 @@ module \ls180 assign $0\spisdcard_mosi[0:0] \spisdcard_mosi assign { } { } assign $0\uart_tx[0:0] \uart_tx - assign $0\pwm[1:0] \pwm assign $0\main_libresocsim_reset_storage[0:0] \main_libresocsim_reset_storage assign { } { } assign $0\main_libresocsim_scratch_storage[31:0] \main_libresocsim_scratch_storage @@ -130753,6 +279399,7 @@ module \ls180 assign $0\main_libresocsim_scratch_storage[31:0] 305419896 assign $0\main_libresocsim_scratch_re[0:0] 1'0 assign $0\main_libresocsim_bus_errors[31:0] 0 + assign $0\pwm[1:0] 2'00 assign $0\spimaster_clk[0:0] 1'0 assign $0\spimaster_mosi[0:0] 1'0 assign $0\spimaster_cs_n[0:0] 1'0 @@ -130760,7 +279407,6 @@ module \ls180 assign $0\spisdcard_mosi[0:0] 1'0 assign $0\spisdcard_cs_n[0:0] 1'0 assign $0\uart_tx[0:0] 1'1 - assign $0\pwm[1:0] 2'00 assign $0\main_libresocsim_converter0_counter[0:0] 1'0 assign $0\main_libresocsim_converter1_counter[0:0] 1'0 assign $0\main_libresocsim_converter2_counter[0:0] 1'0 @@ -131044,6 +279690,7 @@ module \ls180 case end sync posedge \sys_clk_1 + update \pwm $0\pwm[1:0] update \spimaster_clk $0\spimaster_clk[0:0] update \spimaster_mosi $0\spimaster_mosi[0:0] update \spimaster_cs_n $0\spimaster_cs_n[0:0] @@ -131051,7 +279698,6 @@ module \ls180 update \spisdcard_mosi $0\spisdcard_mosi[0:0] update \spisdcard_cs_n $0\spisdcard_cs_n[0:0] update \uart_tx $0\uart_tx[0:0] - update \pwm $0\pwm[1:0] update \main_libresocsim_reset_storage $0\main_libresocsim_reset_storage[0:0] update \main_libresocsim_reset_re $0\main_libresocsim_reset_re[0:0] update \main_libresocsim_scratch_storage $0\main_libresocsim_scratch_storage[31:0] @@ -133920,6180 +282566,109279 @@ module \ls180 connect \main_sdmem2block_fifo_wrport_dat_r \memdat_9 connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10177$2749_DATA end -attribute \src "libresoc.v:45741.1-45785.10" +attribute \src "libresoc.v:135159.1-135217.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.lsd_l" +attribute \generator "nMigen" +module \lsd_l + attribute \src "libresoc.v:135160.7-135160.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:135205.3-135213.6" + wire $0\q_int$next[0:0]$6779 + attribute \src "libresoc.v:135203.3-135204.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:135205.3-135213.6" + wire $1\q_int$next[0:0]$6780 + attribute \src "libresoc.v:135182.7-135182.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:135195.17-135195.96" + wire $and$libresoc.v:135195$6769_Y + attribute \src "libresoc.v:135200.17-135200.96" + wire $and$libresoc.v:135200$6774_Y + attribute \src "libresoc.v:135197.18-135197.93" + wire $not$libresoc.v:135197$6771_Y + attribute \src "libresoc.v:135199.17-135199.92" + wire $not$libresoc.v:135199$6773_Y + attribute \src "libresoc.v:135202.17-135202.92" + wire $not$libresoc.v:135202$6776_Y + attribute \src "libresoc.v:135196.18-135196.98" + wire $or$libresoc.v:135196$6770_Y + attribute \src "libresoc.v:135198.18-135198.99" + wire $or$libresoc.v:135198$6772_Y + attribute \src "libresoc.v:135201.17-135201.97" + wire $or$libresoc.v:135201$6775_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:135160.7-135160.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:135195$6769 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:135195$6769_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:135200$6774 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:135200$6774_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:135197$6771 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_lsd + connect \Y $not$libresoc.v:135197$6771_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:135199$6773 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_lsd + connect \Y $not$libresoc.v:135199$6773_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:135202$6776 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_lsd + connect \Y $not$libresoc.v:135202$6776_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:135196$6770 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_lsd + connect \Y $or$libresoc.v:135196$6770_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:135198$6772 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_lsd + connect \B \q_int + connect \Y $or$libresoc.v:135198$6772_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:135201$6775 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_lsd + connect \Y $or$libresoc.v:135201$6775_Y + end + attribute \src "libresoc.v:135160.7-135160.20" + process $proc$libresoc.v:135160$6781 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:135182.7-135182.19" + process $proc$libresoc.v:135182$6782 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:135203.3-135204.27" + process $proc$libresoc.v:135203$6777 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:135205.3-135213.6" + process $proc$libresoc.v:135205$6778 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$6779 $1\q_int$next[0:0]$6780 + attribute \src "libresoc.v:135206.5-135206.29" + switch \initial + attribute \src "libresoc.v:135206.9-135206.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$6780 1'0 + case + assign $1\q_int$next[0:0]$6780 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$6779 + end + connect \$9 $and$libresoc.v:135195$6769_Y + connect \$11 $or$libresoc.v:135196$6770_Y + connect \$13 $not$libresoc.v:135197$6771_Y + connect \$15 $or$libresoc.v:135198$6772_Y + connect \$1 $not$libresoc.v:135199$6773_Y + connect \$3 $and$libresoc.v:135200$6774_Y + connect \$5 $or$libresoc.v:135201$6775_Y + connect \$7 $not$libresoc.v:135202$6776_Y + connect \qlq_lsd \$15 + connect \qn_lsd \$13 + connect \q_lsd \$11 +end +attribute \src "libresoc.v:135221.1-135755.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.lsmem" +attribute \generator "nMigen" +module \lsmem + attribute \src "libresoc.v:135609.3-135634.6" + wire width 45 $0\dbus__adr$next[44:0]$6868 + attribute \src "libresoc.v:135459.3-135460.35" + wire width 45 $0\dbus__adr[44:0] + attribute \src "libresoc.v:135469.3-135496.6" + wire $0\dbus__cyc$next[0:0]$6842 + attribute \src "libresoc.v:135467.3-135468.35" + wire $0\dbus__cyc[0:0] + attribute \src "libresoc.v:135661.3-135686.6" + wire width 64 $0\dbus__dat_w$next[63:0]$6878 + attribute \src "libresoc.v:135455.3-135456.39" + wire width 64 $0\dbus__dat_w[63:0] + attribute \src "libresoc.v:135553.3-135583.6" + wire width 8 $0\dbus__sel$next[7:0]$6856 + attribute \src "libresoc.v:135463.3-135464.35" + wire width 8 $0\dbus__sel[7:0] + attribute \src "libresoc.v:135497.3-135524.6" + wire $0\dbus__stb$next[0:0]$6848 + attribute \src "libresoc.v:135465.3-135466.35" + wire $0\dbus__stb[0:0] + attribute \src "libresoc.v:135635.3-135660.6" + wire $0\dbus__we$next[0:0]$6873 + attribute \src "libresoc.v:135457.3-135458.33" + wire $0\dbus__we[0:0] + attribute \src "libresoc.v:135222.7-135222.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:135733.3-135752.6" + wire width 45 $0\m_badaddr_o$next[44:0]$6893 + attribute \src "libresoc.v:135449.3-135450.39" + wire width 45 $0\m_badaddr_o[44:0] + attribute \src "libresoc.v:135535.3-135552.6" + wire $0\m_busy_o[0:0] + attribute \src "libresoc.v:135584.3-135608.6" + wire width 64 $0\m_ld_data_o$next[63:0]$6862 + attribute \src "libresoc.v:135461.3-135462.39" + wire width 64 $0\m_ld_data_o[63:0] + attribute \src "libresoc.v:135687.3-135709.6" + wire $0\m_load_err_o$next[0:0]$6883 + attribute \src "libresoc.v:135453.3-135454.41" + wire $0\m_load_err_o[0:0] + attribute \src "libresoc.v:135710.3-135732.6" + wire $0\m_store_err_o$next[0:0]$6888 + attribute \src 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connect \Y $or$libresoc.v:135432$6814_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $or $or$libresoc.v:135436$6818 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $or$libresoc.v:135436$6818_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" + cell $or $or$libresoc.v:135448$6830 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_load_err_o + connect \B \m_store_err_o + connect \Y $or$libresoc.v:135448$6830_Y + end + attribute \src "libresoc.v:135222.7-135222.20" + process $proc$libresoc.v:135222$6897 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:135327.14-135327.42" + process $proc$libresoc.v:135327$6898 + assign { } { } + assign $1\dbus__adr[44:0] 45'000000000000000000000000000000000000000000000 + sync always + sync init + update \dbus__adr $1\dbus__adr[44:0] + end + attribute \src "libresoc.v:135332.7-135332.23" + process $proc$libresoc.v:135332$6899 + assign { } { } + assign $1\dbus__cyc[0:0] 1'0 + sync always + sync init + update \dbus__cyc $1\dbus__cyc[0:0] + end + attribute \src "libresoc.v:135339.14-135339.48" + process $proc$libresoc.v:135339$6900 + assign { } { } + assign $1\dbus__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dbus__dat_w $1\dbus__dat_w[63:0] + end + attribute \src "libresoc.v:135346.13-135346.30" + process $proc$libresoc.v:135346$6901 + assign { } { } + assign $1\dbus__sel[7:0] 8'00000000 + sync always + sync init + update \dbus__sel $1\dbus__sel[7:0] + end + attribute \src "libresoc.v:135351.7-135351.23" + process $proc$libresoc.v:135351$6902 + assign { } { } + assign $1\dbus__stb[0:0] 1'0 + sync always + sync init + update \dbus__stb $1\dbus__stb[0:0] + end + attribute \src "libresoc.v:135356.7-135356.22" + process $proc$libresoc.v:135356$6903 + assign { } { } + assign $1\dbus__we[0:0] 1'0 + sync always + sync init + update \dbus__we $1\dbus__we[0:0] + end + attribute \src "libresoc.v:135360.14-135360.44" + process $proc$libresoc.v:135360$6904 + assign { } { } + assign $1\m_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 + sync always + sync init + update \m_badaddr_o $1\m_badaddr_o[44:0] + end + attribute \src "libresoc.v:135367.14-135367.48" + process $proc$libresoc.v:135367$6905 + assign { } { } + assign $1\m_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \m_ld_data_o $1\m_ld_data_o[63:0] + end + attribute \src "libresoc.v:135371.7-135371.26" + process $proc$libresoc.v:135371$6906 + assign { } { } + assign $1\m_load_err_o[0:0] 1'0 + sync always + sync init + update \m_load_err_o $1\m_load_err_o[0:0] + end + attribute \src "libresoc.v:135377.7-135377.27" + process $proc$libresoc.v:135377$6907 + assign { } { } + assign $1\m_store_err_o[0:0] 1'0 + sync always + sync init + update \m_store_err_o $1\m_store_err_o[0:0] + end + attribute \src "libresoc.v:135449.3-135450.39" + process $proc$libresoc.v:135449$6831 + assign { } { } + assign $0\m_badaddr_o[44:0] \m_badaddr_o$next + sync posedge \coresync_clk + update \m_badaddr_o $0\m_badaddr_o[44:0] + end + attribute \src "libresoc.v:135451.3-135452.43" + process $proc$libresoc.v:135451$6832 + assign { } { } + assign $0\m_store_err_o[0:0] \m_store_err_o$next + sync posedge \coresync_clk + update \m_store_err_o $0\m_store_err_o[0:0] + end + attribute \src "libresoc.v:135453.3-135454.41" + process $proc$libresoc.v:135453$6833 + assign { } { } + assign $0\m_load_err_o[0:0] \m_load_err_o$next + sync posedge \coresync_clk + update \m_load_err_o $0\m_load_err_o[0:0] + end + attribute \src "libresoc.v:135455.3-135456.39" + process $proc$libresoc.v:135455$6834 + assign { } { } + assign $0\dbus__dat_w[63:0] \dbus__dat_w$next + sync posedge \coresync_clk + update \dbus__dat_w $0\dbus__dat_w[63:0] + end + attribute \src "libresoc.v:135457.3-135458.33" + process $proc$libresoc.v:135457$6835 + assign { } { } + assign $0\dbus__we[0:0] \dbus__we$next + sync posedge \coresync_clk + update \dbus__we $0\dbus__we[0:0] + end + attribute \src "libresoc.v:135459.3-135460.35" + process $proc$libresoc.v:135459$6836 + assign { } { } + assign $0\dbus__adr[44:0] \dbus__adr$next + sync posedge \coresync_clk + update \dbus__adr $0\dbus__adr[44:0] + end + attribute \src "libresoc.v:135461.3-135462.39" + process $proc$libresoc.v:135461$6837 + assign { } { } + assign $0\m_ld_data_o[63:0] \m_ld_data_o$next + sync posedge \coresync_clk + update \m_ld_data_o $0\m_ld_data_o[63:0] + end + attribute \src "libresoc.v:135463.3-135464.35" + process $proc$libresoc.v:135463$6838 + assign { } { } + assign $0\dbus__sel[7:0] \dbus__sel$next + sync posedge \coresync_clk + update \dbus__sel $0\dbus__sel[7:0] + end + attribute \src "libresoc.v:135465.3-135466.35" + process $proc$libresoc.v:135465$6839 + assign { } { } + assign $0\dbus__stb[0:0] \dbus__stb$next + sync posedge \coresync_clk + update \dbus__stb $0\dbus__stb[0:0] + end + attribute \src "libresoc.v:135467.3-135468.35" + process $proc$libresoc.v:135467$6840 + assign { } { } + assign $0\dbus__cyc[0:0] \dbus__cyc$next + sync posedge \coresync_clk + update \dbus__cyc $0\dbus__cyc[0:0] + end + attribute \src "libresoc.v:135469.3-135496.6" + process $proc$libresoc.v:135469$6841 + assign { } { } + assign { } { } + assign { } { } + assign $0\dbus__cyc$next[0:0]$6842 $4\dbus__cyc$next[0:0]$6846 + attribute \src "libresoc.v:135470.5-135470.29" + switch \initial + attribute \src "libresoc.v:135470.9-135470.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbus__cyc$next[0:0]$6843 $2\dbus__cyc$next[0:0]$6844 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + switch { \$7 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\dbus__cyc$next[0:0]$6844 $3\dbus__cyc$next[0:0]$6845 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dbus__cyc$next[0:0]$6845 1'0 + case + assign $3\dbus__cyc$next[0:0]$6845 \dbus__cyc + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\dbus__cyc$next[0:0]$6844 1'1 + case + assign $2\dbus__cyc$next[0:0]$6844 \dbus__cyc + end + case + assign $1\dbus__cyc$next[0:0]$6843 \dbus__cyc + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\dbus__cyc$next[0:0]$6846 1'0 + case + assign $4\dbus__cyc$next[0:0]$6846 $1\dbus__cyc$next[0:0]$6843 + end + sync always + update \dbus__cyc$next $0\dbus__cyc$next[0:0]$6842 + end + attribute \src "libresoc.v:135497.3-135524.6" + process $proc$libresoc.v:135497$6847 + assign { } { } + assign { } { } + assign { } { } + assign $0\dbus__stb$next[0:0]$6848 $4\dbus__stb$next[0:0]$6852 + attribute \src "libresoc.v:135498.5-135498.29" + switch \initial + attribute \src "libresoc.v:135498.9-135498.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbus__stb$next[0:0]$6849 $2\dbus__stb$next[0:0]$6850 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + switch { \$21 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\dbus__stb$next[0:0]$6850 $3\dbus__stb$next[0:0]$6851 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dbus__stb$next[0:0]$6851 1'0 + case + assign $3\dbus__stb$next[0:0]$6851 \dbus__stb + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\dbus__stb$next[0:0]$6850 1'1 + case + assign $2\dbus__stb$next[0:0]$6850 \dbus__stb + end + case + assign $1\dbus__stb$next[0:0]$6849 \dbus__stb + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\dbus__stb$next[0:0]$6852 1'0 + case + assign $4\dbus__stb$next[0:0]$6852 $1\dbus__stb$next[0:0]$6849 + end + sync always + update \dbus__stb$next $0\dbus__stb$next[0:0]$6848 + end + attribute \src "libresoc.v:135525.3-135534.6" + process $proc$libresoc.v:135525$6853 + assign { } { } + assign { } { } + assign $0\x_busy_o[0:0] $1\x_busy_o[0:0] + attribute \src "libresoc.v:135526.5-135526.29" + switch \initial + attribute \src "libresoc.v:135526.9-135526.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\x_busy_o[0:0] \dbus__cyc + case + assign $1\x_busy_o[0:0] 1'0 + end + sync always + update \x_busy_o $0\x_busy_o[0:0] + end + attribute \src "libresoc.v:135535.3-135552.6" + process $proc$libresoc.v:135535$6854 + assign { } { } + assign { } { } + assign $0\m_busy_o[0:0] $1\m_busy_o[0:0] + attribute \src "libresoc.v:135536.5-135536.29" + switch \initial + attribute \src "libresoc.v:135536.9-135536.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\m_busy_o[0:0] $2\m_busy_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" + switch \$95 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\m_busy_o[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\m_busy_o[0:0] \dbus__cyc + end + case + assign $1\m_busy_o[0:0] 1'0 + end + sync always + update \m_busy_o $0\m_busy_o[0:0] + end + attribute \src "libresoc.v:135553.3-135583.6" + process $proc$libresoc.v:135553$6855 + assign { } { } + assign { } { } + assign { } { } + assign $0\dbus__sel$next[7:0]$6856 $4\dbus__sel$next[7:0]$6860 + attribute \src "libresoc.v:135554.5-135554.29" + switch \initial + attribute \src "libresoc.v:135554.9-135554.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbus__sel$next[7:0]$6857 $2\dbus__sel$next[7:0]$6858 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + switch { \$35 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\dbus__sel$next[7:0]$6858 $3\dbus__sel$next[7:0]$6859 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + switch \$41 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dbus__sel$next[7:0]$6859 8'00000000 + case + assign $3\dbus__sel$next[7:0]$6859 \dbus__sel + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\dbus__sel$next[7:0]$6858 \x_mask_i + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dbus__sel$next[7:0]$6858 8'00000000 + end + case + assign $1\dbus__sel$next[7:0]$6857 \dbus__sel + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\dbus__sel$next[7:0]$6860 8'00000000 + case + assign $4\dbus__sel$next[7:0]$6860 $1\dbus__sel$next[7:0]$6857 + end + sync always + update \dbus__sel$next $0\dbus__sel$next[7:0]$6856 + end + attribute \src "libresoc.v:135584.3-135608.6" + process $proc$libresoc.v:135584$6861 + assign { } { } + assign { } { } + assign { } { } + assign $0\m_ld_data_o$next[63:0]$6862 $4\m_ld_data_o$next[63:0]$6866 + attribute \src "libresoc.v:135585.5-135585.29" + switch \initial + attribute \src "libresoc.v:135585.9-135585.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\m_ld_data_o$next[63:0]$6863 $2\m_ld_data_o$next[63:0]$6864 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + switch { \$49 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\m_ld_data_o$next[63:0]$6864 $3\m_ld_data_o$next[63:0]$6865 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + switch \$55 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\m_ld_data_o$next[63:0]$6865 \dbus__dat_r + case + assign $3\m_ld_data_o$next[63:0]$6865 \m_ld_data_o + end + case + assign $2\m_ld_data_o$next[63:0]$6864 \m_ld_data_o + end + case + assign $1\m_ld_data_o$next[63:0]$6863 \m_ld_data_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\m_ld_data_o$next[63:0]$6866 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $4\m_ld_data_o$next[63:0]$6866 $1\m_ld_data_o$next[63:0]$6863 + end + sync always + update \m_ld_data_o$next $0\m_ld_data_o$next[63:0]$6862 + end + attribute \src "libresoc.v:135609.3-135634.6" + process $proc$libresoc.v:135609$6867 + assign { } { } + assign { } { } + assign { } { } + assign $0\dbus__adr$next[44:0]$6868 $3\dbus__adr$next[44:0]$6871 + attribute \src "libresoc.v:135610.5-135610.29" + switch \initial + attribute \src "libresoc.v:135610.9-135610.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbus__adr$next[44:0]$6869 $2\dbus__adr$next[44:0]$6870 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + switch { \$63 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign $2\dbus__adr$next[44:0]$6870 \dbus__adr + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\dbus__adr$next[44:0]$6870 \x_addr_i [47:3] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dbus__adr$next[44:0]$6870 45'000000000000000000000000000000000000000000000 + end + case + assign $1\dbus__adr$next[44:0]$6869 \dbus__adr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dbus__adr$next[44:0]$6871 45'000000000000000000000000000000000000000000000 + case + assign $3\dbus__adr$next[44:0]$6871 $1\dbus__adr$next[44:0]$6869 + end + sync always + update \dbus__adr$next $0\dbus__adr$next[44:0]$6868 + end + attribute \src "libresoc.v:135635.3-135660.6" + process $proc$libresoc.v:135635$6872 + assign { } { } + assign { } { } + assign { } { } + assign $0\dbus__we$next[0:0]$6873 $3\dbus__we$next[0:0]$6876 + attribute \src "libresoc.v:135636.5-135636.29" + switch \initial + attribute \src "libresoc.v:135636.9-135636.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbus__we$next[0:0]$6874 $2\dbus__we$next[0:0]$6875 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + switch { \$71 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign $2\dbus__we$next[0:0]$6875 \dbus__we + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\dbus__we$next[0:0]$6875 \x_st_i + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dbus__we$next[0:0]$6875 1'0 + end + case + assign $1\dbus__we$next[0:0]$6874 \dbus__we + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dbus__we$next[0:0]$6876 1'0 + case + assign $3\dbus__we$next[0:0]$6876 $1\dbus__we$next[0:0]$6874 + end + sync always + update \dbus__we$next $0\dbus__we$next[0:0]$6873 + end + attribute \src "libresoc.v:135661.3-135686.6" + process $proc$libresoc.v:135661$6877 + assign { } { } + assign { } { } + assign { } { } + assign $0\dbus__dat_w$next[63:0]$6878 $3\dbus__dat_w$next[63:0]$6881 + attribute \src "libresoc.v:135662.5-135662.29" + switch \initial + attribute \src "libresoc.v:135662.9-135662.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbus__dat_w$next[63:0]$6879 $2\dbus__dat_w$next[63:0]$6880 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + switch { \$79 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign $2\dbus__dat_w$next[63:0]$6880 \dbus__dat_w + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\dbus__dat_w$next[63:0]$6880 \x_st_data_i + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dbus__dat_w$next[63:0]$6880 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\dbus__dat_w$next[63:0]$6879 \dbus__dat_w + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dbus__dat_w$next[63:0]$6881 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dbus__dat_w$next[63:0]$6881 $1\dbus__dat_w$next[63:0]$6879 + end + sync always + update \dbus__dat_w$next $0\dbus__dat_w$next[63:0]$6878 + end + attribute \src "libresoc.v:135687.3-135709.6" + process $proc$libresoc.v:135687$6882 + assign { } { } + assign { } { } + assign { } { } + assign $0\m_load_err_o$next[0:0]$6883 $3\m_load_err_o$next[0:0]$6886 + attribute \src "libresoc.v:135688.5-135688.29" + switch \initial + attribute \src "libresoc.v:135688.9-135688.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\m_load_err_o$next[0:0]$6884 $2\m_load_err_o$next[0:0]$6885 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" + switch { \$83 \$81 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\m_load_err_o$next[0:0]$6885 \$85 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\m_load_err_o$next[0:0]$6885 1'0 + case + assign $2\m_load_err_o$next[0:0]$6885 \m_load_err_o + end + case + assign $1\m_load_err_o$next[0:0]$6884 \m_load_err_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\m_load_err_o$next[0:0]$6886 1'0 + case + assign $3\m_load_err_o$next[0:0]$6886 $1\m_load_err_o$next[0:0]$6884 + end + sync always + update \m_load_err_o$next $0\m_load_err_o$next[0:0]$6883 + end + attribute \src "libresoc.v:135710.3-135732.6" + process $proc$libresoc.v:135710$6887 + assign { } { } + assign { } { } + assign { } { } + assign $0\m_store_err_o$next[0:0]$6888 $3\m_store_err_o$next[0:0]$6891 + attribute \src "libresoc.v:135711.5-135711.29" + switch \initial + attribute \src "libresoc.v:135711.9-135711.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\m_store_err_o$next[0:0]$6889 $2\m_store_err_o$next[0:0]$6890 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" + switch { \$89 \$87 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\m_store_err_o$next[0:0]$6890 \dbus__we + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\m_store_err_o$next[0:0]$6890 1'0 + case + assign $2\m_store_err_o$next[0:0]$6890 \m_store_err_o + end + case + assign $1\m_store_err_o$next[0:0]$6889 \m_store_err_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\m_store_err_o$next[0:0]$6891 1'0 + case + assign $3\m_store_err_o$next[0:0]$6891 $1\m_store_err_o$next[0:0]$6889 + end + sync always + update \m_store_err_o$next $0\m_store_err_o$next[0:0]$6888 + end + attribute \src "libresoc.v:135733.3-135752.6" + process $proc$libresoc.v:135733$6892 + assign { } { } + assign { } { } + assign { } { } + assign $0\m_badaddr_o$next[44:0]$6893 $3\m_badaddr_o$next[44:0]$6896 + attribute \src "libresoc.v:135734.5-135734.29" + switch \initial + attribute \src "libresoc.v:135734.9-135734.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\m_badaddr_o$next[44:0]$6894 $2\m_badaddr_o$next[44:0]$6895 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" + switch { \$93 \$91 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\m_badaddr_o$next[44:0]$6895 \dbus__adr + case + assign $2\m_badaddr_o$next[44:0]$6895 \m_badaddr_o + end + case + assign $1\m_badaddr_o$next[44:0]$6894 \m_badaddr_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\m_badaddr_o$next[44:0]$6896 45'000000000000000000000000000000000000000000000 + case + assign $3\m_badaddr_o$next[44:0]$6896 $1\m_badaddr_o$next[44:0]$6894 + end + sync always + update \m_badaddr_o$next $0\m_badaddr_o$next[44:0]$6893 + end + connect \$9 $or$libresoc.v:135401$6783_Y + connect \$11 $not$libresoc.v:135402$6784_Y + connect \$13 $or$libresoc.v:135403$6785_Y + connect \$15 $or$libresoc.v:135404$6786_Y + connect \$17 $and$libresoc.v:135405$6787_Y + connect \$1 $or$libresoc.v:135406$6788_Y + connect \$19 $not$libresoc.v:135407$6789_Y + connect \$21 $and$libresoc.v:135408$6790_Y + connect \$23 $or$libresoc.v:135409$6791_Y + connect \$25 $not$libresoc.v:135410$6792_Y + connect \$27 $or$libresoc.v:135411$6793_Y + connect \$29 $or$libresoc.v:135412$6794_Y + connect \$31 $and$libresoc.v:135413$6795_Y + connect \$33 $not$libresoc.v:135414$6796_Y + connect \$35 $and$libresoc.v:135415$6797_Y + connect \$37 $or$libresoc.v:135416$6798_Y + connect \$3 $and$libresoc.v:135417$6799_Y + connect \$39 $not$libresoc.v:135418$6800_Y + connect \$41 $or$libresoc.v:135419$6801_Y + connect \$43 $or$libresoc.v:135420$6802_Y + connect \$45 $and$libresoc.v:135421$6803_Y + connect \$47 $not$libresoc.v:135422$6804_Y + connect \$49 $and$libresoc.v:135423$6805_Y + connect \$51 $or$libresoc.v:135424$6806_Y + connect \$53 $not$libresoc.v:135425$6807_Y + connect \$55 $or$libresoc.v:135426$6808_Y + connect \$57 $or$libresoc.v:135427$6809_Y + connect \$5 $not$libresoc.v:135428$6810_Y + connect \$59 $and$libresoc.v:135429$6811_Y + connect \$61 $not$libresoc.v:135430$6812_Y + connect \$63 $and$libresoc.v:135431$6813_Y + connect \$65 $or$libresoc.v:135432$6814_Y + connect \$67 $and$libresoc.v:135433$6815_Y + connect \$69 $not$libresoc.v:135434$6816_Y + connect \$71 $and$libresoc.v:135435$6817_Y + connect \$73 $or$libresoc.v:135436$6818_Y + connect \$75 $and$libresoc.v:135437$6819_Y + connect \$77 $not$libresoc.v:135438$6820_Y + connect \$7 $and$libresoc.v:135439$6821_Y + connect \$79 $and$libresoc.v:135440$6822_Y + connect \$81 $and$libresoc.v:135441$6823_Y + connect \$83 $not$libresoc.v:135442$6824_Y + connect \$85 $not$libresoc.v:135443$6825_Y + connect \$87 $and$libresoc.v:135444$6826_Y + connect \$89 $not$libresoc.v:135445$6827_Y + connect \$91 $and$libresoc.v:135446$6828_Y + connect \$93 $not$libresoc.v:135447$6829_Y + connect \$95 $or$libresoc.v:135448$6830_Y + connect \x_stall_i 1'0 + connect \m_stall_i 1'0 +end +attribute \src "libresoc.v:135759.1-136714.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.main" +attribute \generator "nMigen" +module \main + attribute \src "libresoc.v:136286.3-136308.6" + wire width 64 $0\a_i[63:0] + attribute \src "libresoc.v:136385.3-136411.6" + wire $0\a_lt[0:0] + attribute \src "libresoc.v:136666.3-136676.6" + wire width 64 $0\a_n[63:0] + attribute \src "libresoc.v:136636.3-136645.6" + wire width 66 $0\add_a[65:0] + attribute \src "libresoc.v:136646.3-136655.6" + wire width 66 $0\add_b[65:0] + attribute \src "libresoc.v:136656.3-136665.6" + wire width 66 $0\add_o[65:0] + attribute \src "libresoc.v:136524.3-136546.6" + wire width 64 $0\b_i[63:0] + attribute \src "libresoc.v:136510.3-136523.6" + wire width 2 $0\ca[1:0] + attribute \src "libresoc.v:136677.3-136687.6" + wire $0\carry_32[0:0] + attribute \src "libresoc.v:136688.3-136698.6" + wire $0\carry_64[0:0] + attribute \src "libresoc.v:136412.3-136437.6" + wire width 4 $0\cr_a[3:0] + attribute \src "libresoc.v:136438.3-136452.6" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:136616.3-136635.6" + wire width 8 $0\eqs[7:0] + attribute \src "libresoc.v:135760.7-135760.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:136276.3-136285.6" + wire $0\is_32bit[0:0] + attribute \src "libresoc.v:136347.3-136365.6" + wire $0\msb_a[0:0] + attribute \src "libresoc.v:136366.3-136384.6" + wire $0\msb_b[0:0] + attribute \src "libresoc.v:136453.3-136490.6" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:136491.3-136509.6" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:136569.3-136582.6" + wire width 2 $0\ov[1:0] + attribute \src "libresoc.v:136605.3-136615.6" + wire width 8 $0\src1[7:0] + attribute \src "libresoc.v:136320.3-136346.6" + wire width 5 $0\tval[4:0] + attribute \src "libresoc.v:136547.3-136557.6" + wire width 2 $0\xer_ca$20[1:0]$6983 + attribute \src "libresoc.v:136558.3-136568.6" + wire $0\xer_ca_ok[0:0] + attribute \src "libresoc.v:136583.3-136593.6" + wire width 2 $0\xer_ov[1:0] + attribute \src "libresoc.v:136594.3-136604.6" + wire $0\xer_ov_ok[0:0] + attribute \src "libresoc.v:136309.3-136319.6" + wire $0\zerohi[0:0] + attribute \src "libresoc.v:136699.3-136709.6" + wire $0\zerolo[0:0] + attribute \src "libresoc.v:136286.3-136308.6" + wire width 64 $1\a_i[63:0] + attribute \src "libresoc.v:136385.3-136411.6" + wire $1\a_lt[0:0] + attribute \src "libresoc.v:136666.3-136676.6" + wire width 64 $1\a_n[63:0] + attribute \src "libresoc.v:136636.3-136645.6" + wire width 66 $1\add_a[65:0] + attribute \src "libresoc.v:136646.3-136655.6" + wire width 66 $1\add_b[65:0] + attribute \src "libresoc.v:136656.3-136665.6" + wire width 66 $1\add_o[65:0] + attribute \src "libresoc.v:136524.3-136546.6" + wire width 64 $1\b_i[63:0] + attribute \src "libresoc.v:136510.3-136523.6" + wire width 2 $1\ca[1:0] + attribute \src "libresoc.v:136677.3-136687.6" + wire $1\carry_32[0:0] + attribute \src "libresoc.v:136688.3-136698.6" + wire $1\carry_64[0:0] + attribute \src "libresoc.v:136412.3-136437.6" + wire width 4 $1\cr_a[3:0] + attribute \src "libresoc.v:136438.3-136452.6" + wire $1\cr_a_ok[0:0] + attribute \src "libresoc.v:136616.3-136635.6" + wire width 8 $1\eqs[7:0] + attribute \src "libresoc.v:136276.3-136285.6" + wire $1\is_32bit[0:0] + attribute \src "libresoc.v:136347.3-136365.6" + wire $1\msb_a[0:0] + attribute \src "libresoc.v:136366.3-136384.6" + wire $1\msb_b[0:0] + attribute \src "libresoc.v:136453.3-136490.6" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:136491.3-136509.6" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:136569.3-136582.6" + wire width 2 $1\ov[1:0] + attribute \src "libresoc.v:136605.3-136615.6" + wire width 8 $1\src1[7:0] + attribute \src "libresoc.v:136320.3-136346.6" + wire width 5 $1\tval[4:0] + attribute \src "libresoc.v:136547.3-136557.6" + wire width 2 $1\xer_ca$20[1:0]$6984 + attribute \src "libresoc.v:136558.3-136568.6" + wire $1\xer_ca_ok[0:0] + attribute \src "libresoc.v:136583.3-136593.6" + wire width 2 $1\xer_ov[1:0] + attribute \src "libresoc.v:136594.3-136604.6" + wire $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:136309.3-136319.6" + wire $1\zerohi[0:0] + attribute \src "libresoc.v:136699.3-136709.6" + wire $1\zerolo[0:0] + attribute \src "libresoc.v:136286.3-136308.6" + wire width 64 $2\a_i[63:0] + attribute \src "libresoc.v:136385.3-136411.6" + wire $2\a_lt[0:0] + attribute \src "libresoc.v:136524.3-136546.6" + wire width 64 $2\b_i[63:0] + attribute \src "libresoc.v:136412.3-136437.6" + wire width 2 $2\cr_a[3:2] + attribute \src "libresoc.v:136347.3-136365.6" + wire $2\msb_a[0:0] + attribute \src "libresoc.v:136366.3-136384.6" + wire $2\msb_b[0:0] + attribute \src "libresoc.v:136453.3-136490.6" + wire width 64 $2\o[63:0] + attribute \src "libresoc.v:136320.3-136346.6" + wire width 5 $2\tval[4:0] + attribute \src "libresoc.v:136385.3-136411.6" + wire $3\a_lt[0:0] + attribute \src "libresoc.v:136453.3-136490.6" + wire width 64 $3\o[63:0] + attribute \src "libresoc.v:136320.3-136346.6" + wire width 5 $3\tval[4:0] + attribute \src "libresoc.v:136453.3-136490.6" + wire width 64 $4\o[63:0] + attribute \src "libresoc.v:136251.18-136251.105" + wire width 67 $add$libresoc.v:136251$6944_Y + attribute \src "libresoc.v:136225.19-136225.107" + wire $and$libresoc.v:136225$6918_Y + attribute \src "libresoc.v:136229.19-136229.107" + wire $and$libresoc.v:136229$6922_Y + attribute \src "libresoc.v:136262.18-136262.106" + wire $and$libresoc.v:136262$6955_Y + attribute \src "libresoc.v:136267.18-136267.106" + wire $and$libresoc.v:136267$6960_Y + attribute \src "libresoc.v:136270.18-136270.106" + wire $and$libresoc.v:136270$6963_Y + attribute \src "libresoc.v:136273.18-136273.106" + wire $and$libresoc.v:136273$6966_Y + attribute \src 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\enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 24 \alu_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \alu_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \alu_op__invert_out$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \alu_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \alu_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \alu_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \alu_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \alu_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \alu_op__write_cr0$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:66" + wire width 64 \b_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:150" + wire width 2 \ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100" + wire \carry_32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:101" + wire \carry_64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 44 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 45 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + wire width 8 \eqs + attribute \src "libresoc.v:135760.7-135760.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:54" + wire \is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:104" + wire \msb_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105" + wire \msb_b + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 51 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 23 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 42 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 43 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:156" + wire width 2 \ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:179" + wire width 8 \src1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:98" + wire width 5 \tval + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 22 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 46 \xer_ca$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 47 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 48 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 49 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 50 \xer_so$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:103" + wire \zerohi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:102" + wire \zerolo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:86" + cell $add $add$libresoc.v:136251$6944 + parameter \A_SIGNED 0 + parameter \A_WIDTH 66 + parameter \B_SIGNED 0 + parameter \B_WIDTH 66 + parameter \Y_WIDTH 67 + connect \A \add_a + connect \B \add_b + connect \Y $add$libresoc.v:136251$6944_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" + cell $and $and$libresoc.v:136225$6918 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$113 + connect \B \$115 + connect \Y $and$libresoc.v:136225$6918_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" + cell $and $and$libresoc.v:136229$6922 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$121 + connect \B \$123 + connect \Y $and$libresoc.v:136229$6922_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + cell $and $and$libresoc.v:136262$6955 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \zerolo + connect \B \$69 + connect \Y $and$libresoc.v:136262$6955_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + cell $and $and$libresoc.v:136267$6960 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \zerolo + connect \B \$79 + connect \Y $and$libresoc.v:136267$6960_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + cell $and $and$libresoc.v:136270$6963 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \zerolo + connect \B \$85 + connect \Y $and$libresoc.v:136270$6963_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + cell $and $and$libresoc.v:136273$6966 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \zerolo + connect \B \$91 + connect \Y $and$libresoc.v:136273$6966_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" + cell $eq $eq$libresoc.v:136216$6909 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_op__data_len + connect \B 1'1 + connect \Y $eq$libresoc.v:136216$6909_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" + cell $eq $eq$libresoc.v:136217$6910 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \alu_op__data_len + connect \B 2'10 + connect \Y $eq$libresoc.v:136217$6910_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" + cell $eq $eq$libresoc.v:136218$6911 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \alu_op__data_len + connect \B 3'100 + connect \Y $eq$libresoc.v:136218$6911_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" + cell $eq $eq$libresoc.v:136230$6923 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [7:0] + connect \Y $eq$libresoc.v:136230$6923_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" + cell $eq $eq$libresoc.v:136231$6924 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [15:8] + connect \Y $eq$libresoc.v:136231$6924_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" + cell $eq $eq$libresoc.v:136232$6925 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [23:16] + connect \Y $eq$libresoc.v:136232$6925_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" + cell $eq $eq$libresoc.v:136233$6926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [31:24] + connect \Y $eq$libresoc.v:136233$6926_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" + cell $eq $eq$libresoc.v:136234$6927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:136234$6927_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" + cell $eq $eq$libresoc.v:136235$6928 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:136235$6928_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" + cell $eq $eq$libresoc.v:136236$6929 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:136236$6929_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" + cell $eq $eq$libresoc.v:136237$6930 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [63:56] + connect \Y $eq$libresoc.v:136237$6930_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" + cell $eq $eq$libresoc.v:136238$6931 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:136238$6931_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" + cell $eq $eq$libresoc.v:136240$6933 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:136240$6933_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" + cell $eq $eq$libresoc.v:136241$6934 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:136241$6934_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" + cell $eq $eq$libresoc.v:136242$6935 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0000010 + connect \Y $eq$libresoc.v:136242$6935_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" + cell $eq $eq$libresoc.v:136243$6936 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:136243$6936_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" + cell $eq $eq$libresoc.v:136245$6938 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0000010 + connect \Y $eq$libresoc.v:136245$6938_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" + cell $eq $eq$libresoc.v:136246$6939 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:136246$6939_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" + cell $eq $eq$libresoc.v:136248$6941 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0000010 + connect \Y $eq$libresoc.v:136248$6941_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" + cell $eq $eq$libresoc.v:136249$6942 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:136249$6942_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" + cell $ne $ne$libresoc.v:136263$6956 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_a + connect \B \msb_b + connect \Y $ne$libresoc.v:136263$6956_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" + cell $ne $ne$libresoc.v:136274$6967 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_a + connect \B \msb_b + connect \Y $ne$libresoc.v:136274$6967_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" + cell $not $not$libresoc.v:136224$6917 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$116 + connect \Y $not$libresoc.v:136224$6917_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" + cell $not $not$libresoc.v:136228$6921 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$124 + connect \Y $not$libresoc.v:136228$6921_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:57" + cell $not $not$libresoc.v:136239$6932 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn [21] + connect \Y $not$libresoc.v:136239$6932_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" + cell $not $not$libresoc.v:136252$6945 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \Y $not$libresoc.v:136252$6945_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" + cell $not $not$libresoc.v:136257$6950 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$58 + connect \Y $not$libresoc.v:136257$6950_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" + cell $not $not$libresoc.v:136260$6953 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$64 + connect \Y $not$libresoc.v:136260$6953_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" + cell $not $not$libresoc.v:136264$6957 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_lt + connect \Y $not$libresoc.v:136264$6957_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" + cell $not $not$libresoc.v:136265$6958 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_lt + connect \Y $not$libresoc.v:136265$6958_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" + cell $or $or$libresoc.v:136244$6937 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$30 + connect \B \$32 + connect \Y $or$libresoc.v:136244$6937_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" + cell $or $or$libresoc.v:136247$6940 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$36 + connect \B \$38 + connect \Y $or$libresoc.v:136247$6940_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" + cell $or $or$libresoc.v:136250$6943 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$42 + connect \B \$44 + connect \Y $or$libresoc.v:136250$6943_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + cell $or $or$libresoc.v:136261$6954 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_32bit + connect \B \zerohi + connect \Y $or$libresoc.v:136261$6954_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + cell $or $or$libresoc.v:136266$6959 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_32bit + connect \B \zerohi + connect \Y $or$libresoc.v:136266$6959_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + cell $or $or$libresoc.v:136269$6962 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_32bit + connect \B \zerohi + connect \Y $or$libresoc.v:136269$6962_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + cell $or $or$libresoc.v:136272$6965 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_32bit + connect \B \zerohi + connect \Y $or$libresoc.v:136272$6965_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:185" + cell $reduce_or $reduce_or$libresoc.v:136215$6908 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \eqs + connect \Y $reduce_or$libresoc.v:136215$6908_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:183" + cell $reduce_or $reduce_or$libresoc.v:136219$6912 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \eqs + connect \Y $reduce_or$libresoc.v:136219$6912_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" + cell $reduce_or $reduce_or$libresoc.v:136256$6949 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \$59 + connect \Y $reduce_or$libresoc.v:136256$6949_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" + cell $reduce_or $reduce_or$libresoc.v:136259$6952 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \$65 + connect \Y $reduce_or$libresoc.v:136259$6952_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:120" + cell $mux $ternary$libresoc.v:136268$6961 + parameter \WIDTH 1 + connect \A \a_n [63] + connect \B \a_n [31] + connect \S \is_32bit + connect \Y $ternary$libresoc.v:136268$6961_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121" + cell $mux $ternary$libresoc.v:136271$6964 + parameter \WIDTH 1 + connect \A \rb [63] + connect \B \rb [31] + connect \S \is_32bit + connect \Y $ternary$libresoc.v:136271$6964_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:131" + cell $mux $ternary$libresoc.v:136275$6968 + parameter \WIDTH 1 + connect \A \carry_64 + connect \B \carry_32 + connect \S \is_32bit + connect \Y $ternary$libresoc.v:136275$6968_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" + cell $xor $xor$libresoc.v:136220$6913 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_i [32] + connect \B \b_i [32] + connect \Y $xor$libresoc.v:136220$6913_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" + cell $xor $xor$libresoc.v:136221$6914 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \add_o [33] + connect \B \$109 + connect \Y $xor$libresoc.v:136221$6914_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" + cell $xor $xor$libresoc.v:136222$6915 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ca [0] + connect \B \add_o [64] + connect \Y $xor$libresoc.v:136222$6915_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" + cell $xor $xor$libresoc.v:136223$6916 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_i [63] + connect \B \b_i [63] + connect \Y $xor$libresoc.v:136223$6916_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" + cell $xor $xor$libresoc.v:136226$6919 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ca [1] + connect \B \add_o [32] + connect \Y $xor$libresoc.v:136226$6919_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" + cell $xor $xor$libresoc.v:136227$6920 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_i [31] + connect \B \b_i [31] + connect \Y $xor$libresoc.v:136227$6920_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" + cell $xor $xor$libresoc.v:136253$6946 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \add_o [33] + connect \B \ra [32] + connect \Y $xor$libresoc.v:136253$6946_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" + cell $xor $xor$libresoc.v:136254$6947 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$53 + connect \B \rb [32] + connect \Y $xor$libresoc.v:136254$6947_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" + cell $xor $xor$libresoc.v:136255$6948 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \a_n [31:0] + connect \B \rb [31:0] + connect \Y $xor$libresoc.v:136255$6948_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" + cell $xor $xor$libresoc.v:136258$6951 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \a_n [63:32] + connect \B \rb [63:32] + connect \Y $xor$libresoc.v:136258$6951_Y + end + attribute \src "libresoc.v:135760.7-135760.20" + process $proc$libresoc.v:135760$6998 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:136276.3-136285.6" + process $proc$libresoc.v:136276$6969 + assign { } { } + assign { } { } + assign $0\is_32bit[0:0] $1\is_32bit[0:0] + attribute \src "libresoc.v:136277.5-136277.29" + switch \initial + attribute \src "libresoc.v:136277.9-136277.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" + switch \$22 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\is_32bit[0:0] \$24 + case + assign $1\is_32bit[0:0] 1'0 + end + sync always + update \is_32bit $0\is_32bit[0:0] + end + attribute \src "libresoc.v:136286.3-136308.6" + process $proc$libresoc.v:136286$6970 + assign { } { } + assign $0\a_i[63:0] $1\a_i[63:0] + attribute \src "libresoc.v:136287.5-136287.29" + switch \initial + attribute \src "libresoc.v:136287.9-136287.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" + switch { \is_32bit \$26 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\a_i[63:0] \ra + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\a_i[63:0] $2\a_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" + switch \alu_op__is_signed + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\a_i[63:0] { \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31:0] } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\a_i[63:0] { 32'00000000000000000000000000000000 \ra [31:0] } + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\a_i[63:0] \ra + end + sync always + update \a_i $0\a_i[63:0] + end + attribute \src "libresoc.v:136309.3-136319.6" + process $proc$libresoc.v:136309$6971 + assign { } { } + assign { } { } + assign $0\zerohi[0:0] $1\zerohi[0:0] + attribute \src "libresoc.v:136310.5-136310.29" + switch \initial + attribute \src "libresoc.v:136310.9-136310.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\zerohi[0:0] \$63 + case + assign $1\zerohi[0:0] 1'0 + end + sync always + update \zerohi $0\zerohi[0:0] + end + attribute \src "libresoc.v:136320.3-136346.6" + process $proc$libresoc.v:136320$6972 + assign { } { } + assign { } { } + assign $0\tval[4:0] $1\tval[4:0] + attribute \src "libresoc.v:136321.5-136321.29" + switch \initial + attribute \src "libresoc.v:136321.9-136321.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\tval[4:0] $2\tval[4:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + switch \$71 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { $2\tval[4:0] [4:3] $2\tval[4:0] [1:0] } 4'0000 + assign $2\tval[4:0] [2] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\tval[4:0] $3\tval[4:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" + switch \$73 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\tval[4:0] { \msb_a \msb_b 1'0 \msb_b \msb_a } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\tval[4:0] { \a_lt \$77 1'0 \a_lt \$75 } + end + end + case + assign $1\tval[4:0] 5'00000 + end + sync always + update \tval $0\tval[4:0] + end + attribute \src "libresoc.v:136347.3-136365.6" + process $proc$libresoc.v:136347$6973 + assign { } { } + assign { } { } + assign $0\msb_a[0:0] $1\msb_a[0:0] + attribute \src "libresoc.v:136348.5-136348.29" + switch \initial + attribute \src "libresoc.v:136348.9-136348.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\msb_a[0:0] $2\msb_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + switch \$81 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\msb_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\msb_a[0:0] \$83 + end + case + assign $1\msb_a[0:0] 1'0 + end + sync always + update \msb_a $0\msb_a[0:0] + end + attribute \src "libresoc.v:136366.3-136384.6" + process $proc$libresoc.v:136366$6974 + assign { } { } + assign { } { } + assign $0\msb_b[0:0] $1\msb_b[0:0] + attribute \src "libresoc.v:136367.5-136367.29" + switch \initial + attribute \src "libresoc.v:136367.9-136367.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\msb_b[0:0] $2\msb_b[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + switch \$87 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\msb_b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\msb_b[0:0] \$89 + end + case + assign $1\msb_b[0:0] 1'0 + end + sync always + update \msb_b $0\msb_b[0:0] + end + attribute \src "libresoc.v:136385.3-136411.6" + process $proc$libresoc.v:136385$6975 + assign { } { } + assign { } { } + assign $0\a_lt[0:0] $1\a_lt[0:0] + attribute \src "libresoc.v:136386.5-136386.29" + switch \initial + attribute \src "libresoc.v:136386.9-136386.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\a_lt[0:0] $2\a_lt[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + switch \$93 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\a_lt[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\a_lt[0:0] $3\a_lt[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" + switch \$95 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $3\a_lt[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\a_lt[0:0] \$97 + end + end + case + assign $1\a_lt[0:0] 1'0 + end + sync always + update \a_lt $0\a_lt[0:0] + end + attribute \src "libresoc.v:136412.3-136437.6" + process $proc$libresoc.v:136412$6976 + assign { } { } + assign { } { } + assign $0\cr_a[3:0] $1\cr_a[3:0] + attribute \src "libresoc.v:136413.5-136413.29" + switch \initial + attribute \src "libresoc.v:136413.9-136413.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\cr_a[3:0] [1:0] { \tval [2] \xer_so } + assign $1\cr_a[3:0] [3:2] $2\cr_a[3:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:134" + switch \alu_op__is_signed + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a[3:2] \tval [4:3] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_a[3:2] \tval [1:0] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'0001100 + assign { } { } + assign $1\cr_a[3:0] { 1'0 \$99 2'00 } + case + assign $1\cr_a[3:0] 4'0000 + end + sync always + update \cr_a $0\cr_a[3:0] + end + attribute \src "libresoc.v:136438.3-136452.6" + process $proc$libresoc.v:136438$6977 + assign { } { } + assign { } { } + assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] + attribute \src "libresoc.v:136439.5-136439.29" + switch \initial + attribute \src "libresoc.v:136439.9-136439.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\cr_a_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001100 + assign { } { } + assign $1\cr_a_ok[0:0] 1'1 + case + assign $1\cr_a_ok[0:0] 1'0 + end + sync always + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "libresoc.v:136453.3-136490.6" + process $proc$libresoc.v:136453$6978 + assign { } { } + assign { } { } + assign $0\o[63:0] $1\o[63:0] + attribute \src "libresoc.v:136454.5-136454.29" + switch \initial + attribute \src "libresoc.v:136454.9-136454.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\o[63:0] \add_o [64:1] + attribute \src "libresoc.v:0.0-0.0" + case 7'0011111 + assign { } { } + assign { } { } + assign { } { } + assign $1\o[63:0] $4\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" + switch \$101 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o[63:0] { \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7:0] } + case + assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" + switch \$103 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\o[63:0] { \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15:0] } + case + assign $3\o[63:0] $2\o[63:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" + switch \$105 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\o[63:0] { \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31:0] } + case + assign $4\o[63:0] $3\o[63:0] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'0001100 + assign $1\o[63:0] [63:1] 63'000000000000000000000000000000000000000000000000000000000000000 + assign $1\o[63:0] [0] \$107 + case + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \o $0\o[63:0] + end + attribute \src "libresoc.v:136491.3-136509.6" + process $proc$libresoc.v:136491$6979 + assign { } { } + assign { } { } + assign $0\o_ok[0:0] $1\o_ok[0:0] + attribute \src "libresoc.v:136492.5-136492.29" + switch \initial + attribute \src "libresoc.v:136492.9-136492.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0011111 + assign { } { } + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001100 + assign { } { } + assign $1\o_ok[0:0] 1'0 + case + assign $1\o_ok[0:0] 1'0 + end + sync always + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:136510.3-136523.6" + process $proc$libresoc.v:136510$6980 + assign { } { } + assign { } { } + assign $0\ca[1:0] $1\ca[1:0] + attribute \src "libresoc.v:136511.5-136511.29" + switch \initial + attribute \src "libresoc.v:136511.9-136511.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\ca[1:0] [0] \add_o [65] + assign $1\ca[1:0] [1] \$111 + case + assign $1\ca[1:0] 2'00 + end + sync always + update \ca $0\ca[1:0] + end + attribute \src "libresoc.v:136524.3-136546.6" + process $proc$libresoc.v:136524$6981 + assign { } { } + assign $0\b_i[63:0] $1\b_i[63:0] + attribute \src "libresoc.v:136525.5-136525.29" + switch \initial + attribute \src "libresoc.v:136525.9-136525.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" + switch { \is_32bit \$28 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\b_i[63:0] \rb + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\b_i[63:0] $2\b_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" + switch \alu_op__is_signed + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\b_i[63:0] { \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31:0] } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\b_i[63:0] { 32'00000000000000000000000000000000 \rb [31:0] } + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\b_i[63:0] \rb + end + sync always + update \b_i $0\b_i[63:0] + end + attribute \src "libresoc.v:136547.3-136557.6" + process $proc$libresoc.v:136547$6982 + assign { } { } + assign { } { } + assign $0\xer_ca$20[1:0]$6983 $1\xer_ca$20[1:0]$6984 + attribute \src "libresoc.v:136548.5-136548.29" + switch \initial + attribute \src "libresoc.v:136548.9-136548.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\xer_ca$20[1:0]$6984 \ca + case + assign $1\xer_ca$20[1:0]$6984 2'00 + end + sync always + update \xer_ca$20 $0\xer_ca$20[1:0]$6983 + end + attribute \src "libresoc.v:136558.3-136568.6" + process $proc$libresoc.v:136558$6985 + assign { } { } + assign { } { } + assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0] + attribute \src "libresoc.v:136559.5-136559.29" + switch \initial + attribute \src "libresoc.v:136559.9-136559.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\xer_ca_ok[0:0] 1'1 + case + assign $1\xer_ca_ok[0:0] 1'0 + end + sync always + update \xer_ca_ok $0\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:136569.3-136582.6" + process $proc$libresoc.v:136569$6986 + assign { } { } + assign { } { } + assign $0\ov[1:0] $1\ov[1:0] + attribute \src "libresoc.v:136570.5-136570.29" + switch \initial + attribute \src "libresoc.v:136570.9-136570.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\ov[1:0] [0] \$119 + assign $1\ov[1:0] [1] \$127 + case + assign $1\ov[1:0] 2'00 + end + sync always + update \ov $0\ov[1:0] + end + attribute \src "libresoc.v:136583.3-136593.6" + process $proc$libresoc.v:136583$6987 + assign { } { } + assign { } { } + assign $0\xer_ov[1:0] $1\xer_ov[1:0] + attribute \src "libresoc.v:136584.5-136584.29" + switch \initial + attribute \src "libresoc.v:136584.9-136584.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\xer_ov[1:0] \ov + case + assign $1\xer_ov[1:0] 2'00 + end + sync always + update \xer_ov $0\xer_ov[1:0] + end + attribute \src "libresoc.v:136594.3-136604.6" + process $proc$libresoc.v:136594$6988 + assign { } { } + assign { } { } + assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:136595.5-136595.29" + switch \initial + attribute \src "libresoc.v:136595.9-136595.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'1 + case + assign $1\xer_ov_ok[0:0] 1'0 + end + sync always + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:136605.3-136615.6" + process $proc$libresoc.v:136605$6989 + assign { } { } + assign { } { } + assign $0\src1[7:0] $1\src1[7:0] + attribute \src "libresoc.v:136606.5-136606.29" + switch \initial + attribute \src "libresoc.v:136606.9-136606.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001100 + assign { } { } + assign $1\src1[7:0] \ra [7:0] + case + assign $1\src1[7:0] 8'00000000 + end + sync always + update \src1 $0\src1[7:0] + end + attribute \src "libresoc.v:136616.3-136635.6" + process $proc$libresoc.v:136616$6990 + assign { } { } + assign { } { } + assign $0\eqs[7:0] $1\eqs[7:0] + attribute \src "libresoc.v:136617.5-136617.29" + switch \initial + attribute \src "libresoc.v:136617.9-136617.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001100 + assign { } { } + assign $1\eqs[7:0] [0] \$129 + assign $1\eqs[7:0] [1] \$131 + assign $1\eqs[7:0] [2] \$133 + assign $1\eqs[7:0] [3] \$135 + assign $1\eqs[7:0] [4] \$137 + assign $1\eqs[7:0] [5] \$139 + assign $1\eqs[7:0] [6] \$141 + assign $1\eqs[7:0] [7] \$143 + case + assign $1\eqs[7:0] 8'00000000 + end + sync always + update \eqs $0\eqs[7:0] + end + attribute \src "libresoc.v:136636.3-136645.6" + process $proc$libresoc.v:136636$6991 + assign { } { } + assign { } { } + assign $0\add_a[65:0] $1\add_a[65:0] + attribute \src "libresoc.v:136637.5-136637.29" + switch \initial + attribute \src "libresoc.v:136637.9-136637.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" + switch \$34 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\add_a[65:0] { 1'0 \a_i \xer_ca [0] } + case + assign $1\add_a[65:0] 66'000000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \add_a $0\add_a[65:0] + end + attribute \src "libresoc.v:136646.3-136655.6" + process $proc$libresoc.v:136646$6992 + assign { } { } + assign { } { } + assign $0\add_b[65:0] $1\add_b[65:0] + attribute \src "libresoc.v:136647.5-136647.29" + switch \initial + attribute \src "libresoc.v:136647.9-136647.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" + switch \$40 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\add_b[65:0] { 1'0 \b_i 1'1 } + case + assign $1\add_b[65:0] 66'000000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \add_b $0\add_b[65:0] + end + attribute \src "libresoc.v:136656.3-136665.6" + process $proc$libresoc.v:136656$6993 + assign { } { } + assign { } { } + assign $0\add_o[65:0] $1\add_o[65:0] + attribute \src "libresoc.v:136657.5-136657.29" + switch \initial + attribute \src "libresoc.v:136657.9-136657.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" + switch \$46 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\add_o[65:0] \$48 [65:0] + case + assign $1\add_o[65:0] 66'000000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \add_o $0\add_o[65:0] + end + attribute \src "libresoc.v:136666.3-136676.6" + process $proc$libresoc.v:136666$6994 + assign { } { } + assign { } { } + assign $0\a_n[63:0] $1\a_n[63:0] + attribute \src "libresoc.v:136667.5-136667.29" + switch \initial + attribute \src "libresoc.v:136667.9-136667.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\a_n[63:0] \$51 + case + assign $1\a_n[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \a_n $0\a_n[63:0] + end + attribute \src "libresoc.v:136677.3-136687.6" + process $proc$libresoc.v:136677$6995 + assign { } { } + assign { } { } + assign $0\carry_32[0:0] $1\carry_32[0:0] + attribute \src "libresoc.v:136678.5-136678.29" + switch \initial + attribute \src "libresoc.v:136678.9-136678.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\carry_32[0:0] \$55 + case + assign $1\carry_32[0:0] 1'0 + end + sync always + update \carry_32 $0\carry_32[0:0] + end + attribute \src "libresoc.v:136688.3-136698.6" + process $proc$libresoc.v:136688$6996 + assign { } { } + assign { } { } + assign $0\carry_64[0:0] $1\carry_64[0:0] + attribute \src "libresoc.v:136689.5-136689.29" + switch \initial + attribute \src "libresoc.v:136689.9-136689.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\carry_64[0:0] \add_o [65] + case + assign $1\carry_64[0:0] 1'0 + end + sync always + update \carry_64 $0\carry_64[0:0] + end + attribute \src "libresoc.v:136699.3-136709.6" + process $proc$libresoc.v:136699$6997 + assign { } { } + assign { } { } + assign $0\zerolo[0:0] $1\zerolo[0:0] + attribute \src "libresoc.v:136700.5-136700.29" + switch \initial + attribute \src "libresoc.v:136700.9-136700.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\zerolo[0:0] \$57 + case + assign $1\zerolo[0:0] 1'0 + end + sync always + update \zerolo $0\zerolo[0:0] + end + connect \$99 $reduce_or$libresoc.v:136215$6908_Y + connect \$101 $eq$libresoc.v:136216$6909_Y + connect \$103 $eq$libresoc.v:136217$6910_Y + connect \$105 $eq$libresoc.v:136218$6911_Y + connect \$107 $reduce_or$libresoc.v:136219$6912_Y + connect \$109 $xor$libresoc.v:136220$6913_Y + connect \$111 $xor$libresoc.v:136221$6914_Y + connect \$113 $xor$libresoc.v:136222$6915_Y + connect \$116 $xor$libresoc.v:136223$6916_Y + connect \$115 $not$libresoc.v:136224$6917_Y + connect \$119 $and$libresoc.v:136225$6918_Y + connect \$121 $xor$libresoc.v:136226$6919_Y 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 24 \sr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \sr_op__imm_data__data + attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \sr_op__input_cr$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 17 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 39 \sr_op__insn$18 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute 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\enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 2 \br_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 14 \br_op__insn_type$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \br_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \br_op__is_32bit$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \br_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 19 \br_op__lk$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:89" + wire \br_taken + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 11 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:110" + wire \cr_bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:129" + wire width 64 \ctr_m + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:124" + wire width 64 \ctr_n + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:115" + wire \ctr_write + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:135" + wire \ctr_zero_bo1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 9 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 21 \fast1$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 22 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 10 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 23 \fast2$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 24 \fast2_ok + attribute \src "libresoc.v:137131.7-137131.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 27 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 12 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 25 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 26 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" + cell $add $add$libresoc.v:137430$7004 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \br_imm_addr + connect \B \br_op__cia + connect \Y $add$libresoc.v:137430$7004_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" + cell $add $add$libresoc.v:137445$7020 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 65 + connect \A \br_op__cia + connect \B 3'100 + connect \Y $add$libresoc.v:137445$7020_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" + cell $and $and$libresoc.v:137437$7011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ctr_zero_bo1 + connect \B \$29 + connect \Y $and$libresoc.v:137437$7011_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140" + cell $and $and$libresoc.v:137438$7012 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ctr_zero_bo1 + connect \B \cr_bit + connect \Y $and$libresoc.v:137438$7012_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" + cell $and $and$libresoc.v:137444$7019 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \br_op__insn [10] + connect \B \$44 + connect \Y $and$libresoc.v:137444$7019_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" + cell $eq $eq$libresoc.v:137428$7002 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \br_op__insn_type + connect \B 7'0001000 + connect \Y $eq$libresoc.v:137428$7002_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" + cell $eq $eq$libresoc.v:137431$7005 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cr_bit + connect \B \bo [3] + connect \Y $eq$libresoc.v:137431$7005_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" + cell $eq $eq$libresoc.v:137433$7007 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \bo [4:3] + connect \B 1'0 + connect \Y $eq$libresoc.v:137433$7007_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" + cell $eq $eq$libresoc.v:137434$7008 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \bo [4:3] + connect \B 1'1 + connect \Y $eq$libresoc.v:137434$7008_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" + cell $eq $eq$libresoc.v:137435$7009 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \bo [4] + connect \B 1'1 + connect \Y $eq$libresoc.v:137435$7009_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $extend$libresoc.v:137440$7014 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \fast1 [31:0] + connect \Y $extend$libresoc.v:137440$7014_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" + cell $not $not$libresoc.v:137436$7010 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cr_bit + connect \Y $not$libresoc.v:137436$7010_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" + cell $not $not$libresoc.v:137443$7018 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \br_op__insn [6] + connect \Y $not$libresoc.v:137443$7018_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" + cell $or $or$libresoc.v:137429$7003 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \br_op__insn [1] + connect \B \$12 + connect \Y $or$libresoc.v:137429$7003_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" + cell $or $or$libresoc.v:137432$7006 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$19 + connect \B \bo [4] + connect \Y $or$libresoc.v:137432$7006_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $pos$libresoc.v:137440$7015 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:137440$7014_Y + connect \Y $pos$libresoc.v:137440$7015_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" + cell $reduce_or $reduce_or$libresoc.v:137441$7016 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \ctr_n + connect \Y $reduce_or$libresoc.v:137441$7016_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" + cell $sub $sub$libresoc.v:137439$7013 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \fast1 + connect \B 1'1 + connect \Y $sub$libresoc.v:137439$7013_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" + cell $xor $xor$libresoc.v:137442$7017 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \bo [1] + connect \B \$40 + connect \Y $xor$libresoc.v:137442$7017_Y + end + attribute \src "libresoc.v:137131.7-137131.20" + process $proc$libresoc.v:137131$7038 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:137446.3-137457.6" + process $proc$libresoc.v:137446$7021 + assign { } { } + assign $0\br_addr[63:0] $1\br_addr[63:0] + attribute \src "libresoc.v:137447.5-137447.29" + switch \initial + attribute \src "libresoc.v:137447.9-137447.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" + switch \$14 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\br_addr[63:0] \br_imm_addr + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\br_addr[63:0] \$16 [63:0] + end + sync always + update \br_addr $0\br_addr[63:0] + end + attribute \src "libresoc.v:137458.3-137484.6" + process $proc$libresoc.v:137458$7022 + assign { } { } + assign { } { } + assign $0\br_imm_addr[63:0] $1\br_imm_addr[63:0] + attribute \src "libresoc.v:137459.5-137459.29" + switch \initial + attribute \src "libresoc.v:137459.9-137459.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" + switch \br_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000110 + assign { } { } + assign $1\br_imm_addr[63:0] { \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25:2] 2'00 } + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 + assign { } { } + assign $1\br_imm_addr[63:0] { \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15:2] 2'00 } + attribute \src "libresoc.v:0.0-0.0" + case 7'0001000 + assign { } { } + assign $1\br_imm_addr[63:0] $2\br_imm_addr[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" + switch \$46 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\br_imm_addr[63:0] { \fast1 [63:2] 2'00 } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\br_imm_addr[63:0] { \fast2 [63:2] 2'00 } + end + case + assign $1\br_imm_addr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \br_imm_addr $0\br_imm_addr[63:0] + end + attribute \src "libresoc.v:137485.3-137503.6" + process $proc$libresoc.v:137485$7023 + assign { } { } + assign { } { } + assign $0\br_taken[0:0] $1\br_taken[0:0] + attribute \src "libresoc.v:137486.5-137486.29" + switch \initial + attribute \src "libresoc.v:137486.9-137486.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" + switch \br_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000110 + assign { } { } + assign $1\br_taken[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 + assign { } { } + assign $1\br_taken[0:0] \bc_taken + attribute \src "libresoc.v:0.0-0.0" + case 7'0001000 + assign { } { } + assign $1\br_taken[0:0] \bc_taken + case + assign $1\br_taken[0:0] 1'0 + end + sync always + update \br_taken $0\br_taken[0:0] + end + attribute \src "libresoc.v:137504.3-137518.6" + process $proc$libresoc.v:137504$7024 + assign { } { } + assign { } { } + assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] + attribute \src "libresoc.v:137505.5-137505.29" + switch \initial + attribute \src "libresoc.v:137505.9-137505.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" + switch \br_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 + assign { } { } + assign $1\fast1_ok[0:0] \ctr_write + attribute \src "libresoc.v:0.0-0.0" + case 7'0001000 + assign { } { } + assign $1\fast1_ok[0:0] \ctr_write + case + assign $1\fast1_ok[0:0] 1'0 + end + sync always + update \fast1_ok $0\fast1_ok[0:0] + end + attribute \src "libresoc.v:137519.3-137528.6" + process $proc$libresoc.v:137519$7025 + assign { } { } + assign { } { } + assign $0\fast2$11[63:0]$7026 $1\fast2$11[63:0]$7027 + attribute \src "libresoc.v:137520.5-137520.29" + switch \initial + attribute \src "libresoc.v:137520.9-137520.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" + switch \br_op__lk + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fast2$11[63:0]$7027 \$48 [63:0] + case + assign $1\fast2$11[63:0]$7027 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fast2$11 $0\fast2$11[63:0]$7026 + end + attribute \src "libresoc.v:137529.3-137538.6" + process $proc$libresoc.v:137529$7028 + assign { } { } + assign { } { } + assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] + attribute \src "libresoc.v:137530.5-137530.29" + switch \initial + attribute \src "libresoc.v:137530.9-137530.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" + switch \br_op__lk + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fast2_ok[0:0] 1'1 + case + assign $1\fast2_ok[0:0] 1'0 + end + sync always + update \fast2_ok $0\fast2_ok[0:0] + end + attribute \src "libresoc.v:137539.3-137553.6" + process $proc$libresoc.v:137539$7029 + assign { } { } + assign { } { } + assign $0\cr_bit[0:0] $1\cr_bit[0:0] + attribute \src "libresoc.v:137540.5-137540.29" + switch \initial + attribute \src "libresoc.v:137540.9-137540.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112" + switch \bi + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cr_bit[0:0] \cr_a [3] + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cr_bit[0:0] \cr_a [2] + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\cr_bit[0:0] \cr_a [1] + attribute \src "libresoc.v:0.0-0.0" + case 2'-- + assign { } { } + assign $1\cr_bit[0:0] \cr_a [0] + case + assign $1\cr_bit[0:0] 1'0 + end + sync always + update \cr_bit $0\cr_bit[0:0] + end + attribute \src "libresoc.v:137554.3-137566.6" + process $proc$libresoc.v:137554$7030 + assign { } { } + assign { } { } + assign $0\ctr_write[0:0] $1\ctr_write[0:0] + attribute \src "libresoc.v:137555.5-137555.29" + switch \initial + attribute \src "libresoc.v:137555.9-137555.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch \bo [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $1\ctr_write[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\ctr_write[0:0] 1'1 + end + sync always + update \ctr_write $0\ctr_write[0:0] + end + attribute \src "libresoc.v:137567.3-137590.6" + process $proc$libresoc.v:137567$7031 + assign { } { } + assign { } { } + assign $0\bc_taken[0:0] $1\bc_taken[0:0] + attribute \src "libresoc.v:137568.5-137568.29" + switch \initial + attribute \src "libresoc.v:137568.9-137568.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch \bo [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\bc_taken[0:0] \$21 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\bc_taken[0:0] $2\bc_taken[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" + switch { \$27 \$25 \$23 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\bc_taken[0:0] \$31 + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\bc_taken[0:0] \$33 + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\bc_taken[0:0] \ctr_zero_bo1 + case + assign $2\bc_taken[0:0] 1'0 + end + end + sync always + update \bc_taken $0\bc_taken[0:0] + end + attribute \src "libresoc.v:137591.3-137603.6" + process $proc$libresoc.v:137591$7032 + assign { } { } + assign { } { } + assign $0\ctr_n[63:0] $1\ctr_n[63:0] + attribute \src "libresoc.v:137592.5-137592.29" + switch \initial + attribute \src "libresoc.v:137592.9-137592.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch \bo [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $1\ctr_n[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\ctr_n[63:0] \$35 [63:0] + end + sync always + update \ctr_n $0\ctr_n[63:0] + end + attribute \src "libresoc.v:137604.3-137616.6" + process $proc$libresoc.v:137604$7033 + assign { } { } + assign { } { } + assign $0\fast1$10[63:0]$7034 $1\fast1$10[63:0]$7035 + attribute \src "libresoc.v:137605.5-137605.29" + switch \initial + attribute \src "libresoc.v:137605.9-137605.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch \bo [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $1\fast1$10[63:0]$7035 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\fast1$10[63:0]$7035 \ctr_n + end + sync always + update \fast1$10 $0\fast1$10[63:0]$7034 + end + attribute \src "libresoc.v:137617.3-137637.6" + process $proc$libresoc.v:137617$7036 + assign { } { } + assign { } { } + assign $0\ctr_m[63:0] $1\ctr_m[63:0] + attribute \src "libresoc.v:137618.5-137618.29" + switch \initial + attribute \src "libresoc.v:137618.9-137618.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch \bo [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $1\ctr_m[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\ctr_m[63:0] $2\ctr_m[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:130" + switch \br_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ctr_m[63:0] \$38 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\ctr_m[63:0] \fast1 + end + end + sync always + update \ctr_m $0\ctr_m[63:0] + end + attribute \src "libresoc.v:137638.3-137650.6" + process $proc$libresoc.v:137638$7037 + assign { } { } + assign { } { } + assign $0\ctr_zero_bo1[0:0] $1\ctr_zero_bo1[0:0] + attribute \src "libresoc.v:137639.5-137639.29" + switch \initial + attribute \src "libresoc.v:137639.9-137639.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch \bo [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $1\ctr_zero_bo1[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\ctr_zero_bo1[0:0] \$42 + end + sync always + update \ctr_zero_bo1 $0\ctr_zero_bo1[0:0] + end + connect \$12 $eq$libresoc.v:137428$7002_Y + connect \$14 $or$libresoc.v:137429$7003_Y + connect \$17 $add$libresoc.v:137430$7004_Y + connect \$19 $eq$libresoc.v:137431$7005_Y + connect \$21 $or$libresoc.v:137432$7006_Y + connect \$23 $eq$libresoc.v:137433$7007_Y + connect \$25 $eq$libresoc.v:137434$7008_Y + connect \$27 $eq$libresoc.v:137435$7009_Y + connect \$29 $not$libresoc.v:137436$7010_Y + connect \$31 $and$libresoc.v:137437$7011_Y + connect \$33 $and$libresoc.v:137438$7012_Y + connect \$36 $sub$libresoc.v:137439$7013_Y + connect \$38 $pos$libresoc.v:137440$7015_Y + connect \$40 $reduce_or$libresoc.v:137441$7016_Y + connect \$42 $xor$libresoc.v:137442$7017_Y + connect \$44 $not$libresoc.v:137443$7018_Y + connect \$46 $and$libresoc.v:137444$7019_Y + connect \$49 $add$libresoc.v:137445$7020_Y + connect \$16 \$17 + connect \$35 \$36 + connect \$48 \$49 + connect { \br_op__is_32bit$9 \br_op__lk$8 \br_op__imm_data__ok$7 \br_op__imm_data__data$6 \br_op__insn$5 \br_op__fn_unit$4 \br_op__insn_type$3 \br_op__cia$2 } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } + connect \muxid$1 \muxid + connect \nia_ok \br_taken + connect \nia \br_addr + connect \bi \br_op__insn [17:16] + connect \bo \br_op__insn [25:21] +end +attribute \src "libresoc.v:137664.1-138608.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.main" +attribute \generator "nMigen" +module \main$38 + attribute \src "libresoc.v:138573.3-138584.6" + wire width 64 $0\a[63:0] + attribute \src "libresoc.v:138071.3-138082.6" + wire width 64 $0\a_s[63:0] + attribute \src "libresoc.v:138585.3-138596.6" + wire width 64 $0\b[63:0] + attribute \src "libresoc.v:138354.3-138365.6" + wire width 64 $0\b_s[63:0] + attribute \src "libresoc.v:138147.3-138178.6" + wire width 64 $0\fast1$11[63:0]$7084 + attribute \src "libresoc.v:138179.3-138210.6" + wire $0\fast1_ok[0:0] + attribute \src "libresoc.v:138211.3-138293.6" + wire width 64 $0\fast2$12[63:0]$7089 + attribute \src "libresoc.v:138294.3-138325.6" + wire $0\fast2_ok[0:0] + attribute \src "libresoc.v:137665.7-137665.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:138366.3-138534.6" + wire width 64 $0\msr[63:0] + attribute \src "libresoc.v:138366.3-138534.6" + wire $0\msr_ok[0:0] + attribute \src "libresoc.v:138083.3-138114.6" + wire width 64 $0\nia[63:0] + attribute \src "libresoc.v:138115.3-138146.6" + wire $0\nia_ok[0:0] + attribute \src "libresoc.v:138535.3-138553.6" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:138554.3-138572.6" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:138326.3-138353.6" + wire $0\trapexc_$signal$60[0:0]$7103 + attribute \src "libresoc.v:138326.3-138353.6" + wire $0\trapexc_$signal$61[0:0]$7104 + attribute \src "libresoc.v:138326.3-138353.6" + wire $0\trapexc_$signal$62[0:0]$7105 + attribute \src "libresoc.v:138326.3-138353.6" + wire $0\trapexc_$signal$67[0:0]$7106 + attribute \src "libresoc.v:138326.3-138353.6" + wire $0\trapexc_$signal$68[0:0]$7107 + attribute \src "libresoc.v:138326.3-138353.6" + wire $0\trapexc_$signal$69[0:0]$7108 + attribute \src "libresoc.v:138326.3-138353.6" + wire $0\trapexc_$signal$70[0:0]$7109 + attribute \src "libresoc.v:138326.3-138353.6" + wire $0\trapexc_$signal[0:0]$7102 + attribute \src "libresoc.v:138211.3-138293.6" + wire $10\fast2$12[19:19]$7099 + attribute \src "libresoc.v:138366.3-138534.6" + wire width 2 $10\msr[5:4] + attribute \src "libresoc.v:138366.3-138534.6" + wire $11\msr[15:15] + attribute \src "libresoc.v:138366.3-138534.6" + wire $12\msr[12:12] + attribute \src "libresoc.v:138366.3-138534.6" + wire $13\msr[60:60] + attribute \src "libresoc.v:138366.3-138534.6" + wire $14\msr[12:12] + attribute \src "libresoc.v:138366.3-138534.6" + wire $15\msr[12:12] + attribute \src "libresoc.v:138366.3-138534.6" + wire width 2 $16\msr[5:4] + attribute \src "libresoc.v:138366.3-138534.6" + wire $17\msr[15:15] + attribute \src "libresoc.v:138366.3-138534.6" + wire width 3 $18\msr[34:32] + attribute \src "libresoc.v:138573.3-138584.6" + wire width 64 $1\a[63:0] + attribute \src "libresoc.v:138071.3-138082.6" + wire width 64 $1\a_s[63:0] + attribute \src "libresoc.v:138585.3-138596.6" + wire width 64 $1\b[63:0] + attribute \src "libresoc.v:138354.3-138365.6" + wire width 64 $1\b_s[63:0] + attribute \src "libresoc.v:138147.3-138178.6" + wire width 64 $1\fast1$11[63:0]$7085 + attribute \src "libresoc.v:138179.3-138210.6" + wire $1\fast1_ok[0:0] + attribute \src "libresoc.v:138211.3-138293.6" + wire width 64 $1\fast2$12[63:0]$7090 + attribute \src "libresoc.v:138294.3-138325.6" + wire $1\fast2_ok[0:0] + attribute \src "libresoc.v:138366.3-138534.6" + wire width 64 $1\msr[63:0] + attribute \src "libresoc.v:138366.3-138534.6" + wire $1\msr_ok[0:0] + attribute \src "libresoc.v:138083.3-138114.6" + wire width 64 $1\nia[63:0] + attribute \src "libresoc.v:138115.3-138146.6" + wire $1\nia_ok[0:0] + attribute \src "libresoc.v:138535.3-138553.6" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:138554.3-138572.6" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:138326.3-138353.6" + wire $1\trapexc_$signal$60[0:0]$7111 + attribute \src "libresoc.v:138326.3-138353.6" + wire $1\trapexc_$signal$61[0:0]$7112 + attribute \src "libresoc.v:138326.3-138353.6" + wire $1\trapexc_$signal$62[0:0]$7113 + attribute \src "libresoc.v:138326.3-138353.6" + wire $1\trapexc_$signal$67[0:0]$7114 + attribute \src "libresoc.v:138326.3-138353.6" + wire $1\trapexc_$signal$68[0:0]$7115 + attribute \src "libresoc.v:138326.3-138353.6" + wire $1\trapexc_$signal$69[0:0]$7116 + attribute \src "libresoc.v:138326.3-138353.6" + wire $1\trapexc_$signal$70[0:0]$7117 + attribute \src "libresoc.v:138326.3-138353.6" + wire $1\trapexc_$signal[0:0]$7110 + attribute \src "libresoc.v:138147.3-138178.6" + wire width 64 $2\fast1$11[63:0]$7086 + attribute \src "libresoc.v:138179.3-138210.6" + wire $2\fast1_ok[0:0] + attribute \src "libresoc.v:138211.3-138293.6" + wire width 64 $2\fast2$12[63:0]$7091 + attribute \src "libresoc.v:138294.3-138325.6" + wire $2\fast2_ok[0:0] + attribute \src "libresoc.v:138366.3-138534.6" + wire width 64 $2\msr[63:0] + attribute \src "libresoc.v:138366.3-138534.6" + wire $2\msr_ok[0:0] + attribute \src "libresoc.v:138083.3-138114.6" + wire width 64 $2\nia[63:0] + attribute \src "libresoc.v:138115.3-138146.6" + wire $2\nia_ok[0:0] + attribute \src "libresoc.v:138326.3-138353.6" + wire $2\trapexc_$signal$60[0:0]$7119 + attribute \src "libresoc.v:138326.3-138353.6" + wire $2\trapexc_$signal$61[0:0]$7120 + attribute \src "libresoc.v:138326.3-138353.6" + wire $2\trapexc_$signal$62[0:0]$7121 + attribute \src "libresoc.v:138326.3-138353.6" + wire $2\trapexc_$signal$67[0:0]$7122 + attribute \src "libresoc.v:138326.3-138353.6" + wire $2\trapexc_$signal$68[0:0]$7123 + attribute \src "libresoc.v:138326.3-138353.6" + wire $2\trapexc_$signal$69[0:0]$7124 + attribute \src "libresoc.v:138326.3-138353.6" + wire $2\trapexc_$signal$70[0:0]$7125 + attribute \src "libresoc.v:138326.3-138353.6" + wire $2\trapexc_$signal[0:0]$7118 + attribute \src "libresoc.v:138211.3-138293.6" + wire $3\fast2$12[17:17]$7092 + attribute \src "libresoc.v:138366.3-138534.6" + wire width 11 $3\msr[11:1] + attribute \src "libresoc.v:138326.3-138353.6" + wire $3\trapexc_$signal$60[0:0]$7127 + attribute \src "libresoc.v:138326.3-138353.6" + wire $3\trapexc_$signal$61[0:0]$7128 + attribute \src "libresoc.v:138326.3-138353.6" + wire $3\trapexc_$signal$62[0:0]$7129 + attribute \src "libresoc.v:138326.3-138353.6" + wire $3\trapexc_$signal$67[0:0]$7130 + attribute \src "libresoc.v:138326.3-138353.6" + wire $3\trapexc_$signal$68[0:0]$7131 + attribute \src "libresoc.v:138326.3-138353.6" + wire $3\trapexc_$signal$69[0:0]$7132 + attribute \src "libresoc.v:138326.3-138353.6" + wire $3\trapexc_$signal$70[0:0]$7133 + attribute \src "libresoc.v:138326.3-138353.6" + wire $3\trapexc_$signal[0:0]$7126 + attribute \src "libresoc.v:138211.3-138293.6" + wire $4\fast2$12[18:18]$7093 + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \trap_op__is_32bit$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 9 \trap_op__ldst_exc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 output 23 \trap_op__ldst_exc$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 4 \trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 18 \trap_op__msr$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 8 \trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 22 \trap_op__trapaddr$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 7 \trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 output 21 \trap_op__traptype$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:315" + cell $add $add$libresoc.v:138047$7055 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 65 + connect \A \trap_op__cia + connect \B 3'100 + connect \Y $add$libresoc.v:138047$7055_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" + cell $and $and$libresoc.v:138041$7048 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \trap_bits + connect \B \to + connect \Y $and$libresoc.v:138041$7048_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" + cell $and $and$libresoc.v:138049$7057 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 8 + connect \A \trap_op__traptype + connect \B 2'10 + connect \Y $and$libresoc.v:138049$7057_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" + cell $and $and$libresoc.v:138051$7059 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \trap_op__traptype + connect \B 1'1 + connect \Y $and$libresoc.v:138051$7059_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" + cell $and $and$libresoc.v:138053$7061 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \trap_op__traptype + connect \B 4'1000 + connect \Y $and$libresoc.v:138053$7061_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" + cell $and $and$libresoc.v:138055$7063 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A \trap_op__traptype + connect \B 7'1000000 + connect \Y $and$libresoc.v:138055$7063_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" + cell $and $and$libresoc.v:138057$7065 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \trap_op__traptype + connect \B 8'10000000 + connect \Y $and$libresoc.v:138057$7065_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" + cell $and $and$libresoc.v:138059$7067 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A \trap_op__traptype + connect \B 7'1000000 + connect \Y $and$libresoc.v:138059$7067_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" + cell $and $and$libresoc.v:138065$7074 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$79 + connect \B \$81 + connect \Y $and$libresoc.v:138065$7074_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" + cell $and $and$libresoc.v:138070$7079 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$89 + connect \B \$91 + connect \Y $and$libresoc.v:138070$7079_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167" + cell $eq $eq$libresoc.v:138040$7047 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \a + connect \B \b + connect \Y $eq$libresoc.v:138040$7047_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" + cell $eq $eq$libresoc.v:138048$7056 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \trap_op__traptype + connect \B 1'0 + connect \Y $eq$libresoc.v:138048$7056_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" + cell $eq $eq$libresoc.v:138062$7071 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \trap_op__insn_type + connect \B 7'1001000 + connect \Y $eq$libresoc.v:138062$7071_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:240" + cell $eq $eq$libresoc.v:138063$7072 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \trap_op__msr [34:32] + connect \B 3'010 + connect \Y $eq$libresoc.v:138063$7072_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" + cell $eq $eq$libresoc.v:138064$7073 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \ra [34:32] + connect \B 3'000 + connect \Y $eq$libresoc.v:138064$7073_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" + cell $eq $eq$libresoc.v:138068$7077 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \trap_op__msr [34:32] + connect \B 3'010 + connect \Y $eq$libresoc.v:138068$7077_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" + cell $eq $eq$libresoc.v:138069$7078 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \fast2 [34:32] + connect \B 3'000 + connect \Y $eq$libresoc.v:138069$7078_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $extend$libresoc.v:138034$7039 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \ra [31:0] + connect \Y $extend$libresoc.v:138034$7039_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $extend$libresoc.v:138035$7041 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \rb [31:0] + connect \Y $extend$libresoc.v:138035$7041_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" + cell $pos $extend$libresoc.v:138046$7053 + parameter \A_SIGNED 0 + parameter \A_WIDTH 20 + parameter \Y_WIDTH 64 + connect \A \$36 + connect \Y $extend$libresoc.v:138046$7053_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + cell $pos $extend$libresoc.v:138061$7069 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \trap_op__msr + connect \Y $extend$libresoc.v:138061$7069_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164" + cell $gt $gt$libresoc.v:138037$7044 + parameter \A_SIGNED 1 + parameter \A_WIDTH 64 + parameter \B_SIGNED 1 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \a_s + connect \B \b_s + connect \Y $gt$libresoc.v:138037$7044_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166" + cell $gt $gt$libresoc.v:138039$7046 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \a + connect \B \b + connect \Y $gt$libresoc.v:138039$7046_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" + cell $lt $lt$libresoc.v:138036$7043 + parameter \A_SIGNED 1 + parameter \A_WIDTH 64 + parameter \B_SIGNED 1 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \a_s + connect \B \b_s + connect \Y $lt$libresoc.v:138036$7043_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165" + cell $lt $lt$libresoc.v:138038$7045 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \a + connect \B \b + connect \Y $lt$libresoc.v:138038$7045_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" + cell $not $not$libresoc.v:138066$7075 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \trap_op__msr [60] + connect \Y $not$libresoc.v:138066$7075_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" + cell $not $not$libresoc.v:138067$7076 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \trap_op__insn [9] + connect \Y $not$libresoc.v:138067$7076_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" + cell $or $or$libresoc.v:138044$7051 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$27 + connect \B \$31 + connect \Y $or$libresoc.v:138044$7051_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $pos$libresoc.v:138034$7040 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:138034$7039_Y + connect \Y $pos$libresoc.v:138034$7040_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $pos$libresoc.v:138035$7042 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:138035$7041_Y + connect \Y $pos$libresoc.v:138035$7042_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" + cell $pos $pos$libresoc.v:138046$7054 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:138046$7053_Y + connect \Y $pos$libresoc.v:138046$7054_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + cell $pos $pos$libresoc.v:138061$7070 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:138061$7069_Y + connect \Y $pos$libresoc.v:138061$7070_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" + cell $reduce_or $reduce_or$libresoc.v:138042$7049 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $reduce_or$libresoc.v:138042$7049_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" + cell $reduce_or $reduce_or$libresoc.v:138043$7050 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \trap_op__traptype + connect \Y $reduce_or$libresoc.v:138043$7050_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:138050$7058 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \$45 + connect \Y $reduce_or$libresoc.v:138050$7058_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:138052$7060 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \$49 + connect \Y $reduce_or$libresoc.v:138052$7060_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:138054$7062 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \$53 + connect \Y $reduce_or$libresoc.v:138054$7062_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:138056$7064 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \$57 + connect \Y $reduce_or$libresoc.v:138056$7064_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:138058$7066 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \$64 + connect \Y $reduce_or$libresoc.v:138058$7066_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:138060$7068 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \$72 + connect \Y $reduce_or$libresoc.v:138060$7068_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" + cell $sshl $sshl$libresoc.v:138045$7052 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 20 + connect \A \trap_op__trapaddr + connect \B 3'100 + connect \Y $sshl$libresoc.v:138045$7052_Y + end + attribute \src "libresoc.v:137665.7-137665.20" + process $proc$libresoc.v:137665$7140 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:138071.3-138082.6" + process $proc$libresoc.v:138071$7080 + assign { } { } + assign $0\a_s[63:0] $1\a_s[63:0] + attribute \src "libresoc.v:138072.5-138072.29" + switch \initial + attribute \src "libresoc.v:138072.9-138072.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" + switch \trap_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a_s[63:0] { \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31:0] } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\a_s[63:0] \ra + end + sync always + update \a_s $0\a_s[63:0] + end + attribute \src "libresoc.v:138083.3-138114.6" + process $proc$libresoc.v:138083$7081 + assign { } { } + assign { } { } + assign $0\nia[63:0] $1\nia[63:0] + attribute \src "libresoc.v:138084.5-138084.29" + switch \initial + attribute \src "libresoc.v:138084.9-138084.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign $1\nia[63:0] $2\nia[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\nia[63:0] \$35 + case + assign $2\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign $1\nia[63:0] { \fast1 [63:2] 2'00 } + attribute \src "libresoc.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000110000000000 + case + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \nia $0\nia[63:0] + end + attribute \src "libresoc.v:138115.3-138146.6" + process $proc$libresoc.v:138115$7082 + assign { } { } + assign { } { } + assign $0\nia_ok[0:0] $1\nia_ok[0:0] + attribute \src "libresoc.v:138116.5-138116.29" + switch \initial + attribute \src "libresoc.v:138116.9-138116.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign $1\nia_ok[0:0] $2\nia_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\nia_ok[0:0] 1'1 + case + assign $2\nia_ok[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\nia_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign $1\nia_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign $1\nia_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign $1\nia_ok[0:0] 1'1 + case + assign $1\nia_ok[0:0] 1'0 + end + sync always + update \nia_ok $0\nia_ok[0:0] + end + attribute \src "libresoc.v:138147.3-138178.6" + process $proc$libresoc.v:138147$7083 + assign { } { } + assign { } { } + assign $0\fast1$11[63:0]$7084 $1\fast1$11[63:0]$7085 + attribute \src "libresoc.v:138148.5-138148.29" + switch \initial + attribute \src "libresoc.v:138148.9-138148.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign $1\fast1$11[63:0]$7085 $2\fast1$11[63:0]$7086 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast1$11[63:0]$7086 \trap_op__cia + case + assign $2\fast1$11[63:0]$7086 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\fast1$11[63:0]$7085 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign $1\fast1$11[63:0]$7085 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign $1\fast1$11[63:0]$7085 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign $1\fast1$11[63:0]$7085 \$39 [63:0] + case + assign $1\fast1$11[63:0]$7085 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fast1$11 $0\fast1$11[63:0]$7084 + end + attribute \src "libresoc.v:138179.3-138210.6" + process $proc$libresoc.v:138179$7087 + assign { } { } + assign { } { } + assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] + attribute \src "libresoc.v:138180.5-138180.29" + switch \initial + attribute \src "libresoc.v:138180.9-138180.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign $1\fast1_ok[0:0] $2\fast1_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast1_ok[0:0] 1'1 + case + assign $2\fast1_ok[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\fast1_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign $1\fast1_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign $1\fast1_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign $1\fast1_ok[0:0] 1'1 + case + assign $1\fast1_ok[0:0] 1'0 + end + sync always + update \fast1_ok $0\fast1_ok[0:0] + end + attribute \src "libresoc.v:138211.3-138293.6" + process $proc$libresoc.v:138211$7088 + assign { } { } + assign { } { } + assign $0\fast2$12[63:0]$7089 $1\fast2$12[63:0]$7090 + attribute \src "libresoc.v:138212.5-138212.29" + switch \initial + attribute \src "libresoc.v:138212.9-138212.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign $1\fast2$12[63:0]$7090 $2\fast2$12[63:0]$7091 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { $2\fast2$12[63:0]$7091 [29] $2\fast2$12[63:0]$7091 [27] $2\fast2$12[63:0]$7091 [21] } 3'000 + assign $2\fast2$12[63:0]$7091 [15:0] \trap_op__msr [15:0] + assign $2\fast2$12[63:0]$7091 [26:22] \trap_op__msr [26:22] + assign $2\fast2$12[63:0]$7091 [63:31] \trap_op__msr [63:31] + assign $2\fast2$12[63:0]$7091 [17] $3\fast2$12[17:17]$7092 + assign { } { } + assign $2\fast2$12[63:0]$7091 [20] $5\fast2$12[20:20]$7094 + assign $2\fast2$12[63:0]$7091 [16] $6\fast2$12[16:16]$7095 + assign $2\fast2$12[63:0]$7091 [18] $7\fast2$12[19:18]$7096 [0] + assign $2\fast2$12[63:0]$7091 [28] $8\fast2$12[28:28]$7097 + assign $2\fast2$12[63:0]$7091 [30] $9\fast2$12[30:30]$7098 + assign $2\fast2$12[63:0]$7091 [19] $10\fast2$12[19:19]$7099 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" + switch \$42 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fast2$12[17:17]$7092 1'1 + case + assign $3\fast2$12[17:17]$7092 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" + switch \$44 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fast2$12[18:18]$7093 1'1 + case + assign $4\fast2$12[18:18]$7093 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" + switch \$48 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fast2$12[20:20]$7094 1'1 + case + assign $5\fast2$12[20:20]$7094 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" + switch \$52 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\fast2$12[16:16]$7095 1'1 + case + assign $6\fast2$12[16:16]$7095 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" + switch \$56 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $9\fast2$12[30:30]$7098 \trapexc_$signal + assign $8\fast2$12[28:28]$7097 \trapexc_$signal$60 + assign $7\fast2$12[19:18]$7096 [1] \trapexc_$signal$61 + assign $7\fast2$12[19:18]$7096 [0] \trapexc_$signal$62 + case + assign $7\fast2$12[19:18]$7096 { 1'0 $4\fast2$12[18:18]$7093 } + assign $8\fast2$12[28:28]$7097 1'0 + assign $9\fast2$12[30:30]$7098 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" + switch \$63 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $10\fast2$12[19:19]$7099 1'1 + case + assign $10\fast2$12[19:19]$7099 $7\fast2$12[19:18]$7096 [1] + end + case + assign $2\fast2$12[63:0]$7091 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\fast2$12[63:0]$7090 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign $1\fast2$12[63:0]$7090 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign $1\fast2$12[63:0]$7090 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign { $1\fast2$12[63:0]$7090 [30:27] $1\fast2$12[63:0]$7090 [21:16] } 10'0000000000 + assign $1\fast2$12[63:0]$7090 [15:0] \trap_op__msr [15:0] + assign $1\fast2$12[63:0]$7090 [26:22] \trap_op__msr [26:22] + assign $1\fast2$12[63:0]$7090 [63:31] \trap_op__msr [63:31] + case + assign $1\fast2$12[63:0]$7090 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fast2$12 $0\fast2$12[63:0]$7089 + end + attribute \src "libresoc.v:138294.3-138325.6" + process $proc$libresoc.v:138294$7100 + assign { } { } + assign { } { } + assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] + attribute \src "libresoc.v:138295.5-138295.29" + switch \initial + attribute \src "libresoc.v:138295.9-138295.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign $1\fast2_ok[0:0] $2\fast2_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast2_ok[0:0] 1'1 + case + assign $2\fast2_ok[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\fast2_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign $1\fast2_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign $1\fast2_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign $1\fast2_ok[0:0] 1'1 + case + assign $1\fast2_ok[0:0] 1'0 + end + sync always + update \fast2_ok $0\fast2_ok[0:0] + end + attribute \src "libresoc.v:138326.3-138353.6" + process $proc$libresoc.v:138326$7101 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\trapexc_$signal[0:0]$7102 $1\trapexc_$signal[0:0]$7110 + assign $0\trapexc_$signal$60[0:0]$7103 $1\trapexc_$signal$60[0:0]$7111 + assign $0\trapexc_$signal$61[0:0]$7104 $1\trapexc_$signal$61[0:0]$7112 + assign $0\trapexc_$signal$62[0:0]$7105 $1\trapexc_$signal$62[0:0]$7113 + assign $0\trapexc_$signal$67[0:0]$7106 $1\trapexc_$signal$67[0:0]$7114 + assign $0\trapexc_$signal$68[0:0]$7107 $1\trapexc_$signal$68[0:0]$7115 + assign $0\trapexc_$signal$69[0:0]$7108 $1\trapexc_$signal$69[0:0]$7116 + assign $0\trapexc_$signal$70[0:0]$7109 $1\trapexc_$signal$70[0:0]$7117 + attribute \src "libresoc.v:138327.5-138327.29" + switch \initial + attribute \src "libresoc.v:138327.9-138327.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\trapexc_$signal[0:0]$7110 $2\trapexc_$signal[0:0]$7118 + assign $1\trapexc_$signal$60[0:0]$7111 $2\trapexc_$signal$60[0:0]$7119 + assign $1\trapexc_$signal$61[0:0]$7112 $2\trapexc_$signal$61[0:0]$7120 + assign $1\trapexc_$signal$62[0:0]$7113 $2\trapexc_$signal$62[0:0]$7121 + assign $1\trapexc_$signal$67[0:0]$7114 $2\trapexc_$signal$67[0:0]$7122 + assign $1\trapexc_$signal$68[0:0]$7115 $2\trapexc_$signal$68[0:0]$7123 + assign $1\trapexc_$signal$69[0:0]$7116 $2\trapexc_$signal$69[0:0]$7124 + assign $1\trapexc_$signal$70[0:0]$7117 $2\trapexc_$signal$70[0:0]$7125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\trapexc_$signal[0:0]$7118 $3\trapexc_$signal[0:0]$7126 + assign $2\trapexc_$signal$60[0:0]$7119 $3\trapexc_$signal$60[0:0]$7127 + assign $2\trapexc_$signal$61[0:0]$7120 $3\trapexc_$signal$61[0:0]$7128 + assign $2\trapexc_$signal$62[0:0]$7121 $3\trapexc_$signal$62[0:0]$7129 + assign $2\trapexc_$signal$67[0:0]$7122 $3\trapexc_$signal$67[0:0]$7130 + assign $2\trapexc_$signal$68[0:0]$7123 $3\trapexc_$signal$68[0:0]$7131 + assign $2\trapexc_$signal$69[0:0]$7124 $3\trapexc_$signal$69[0:0]$7132 + assign $2\trapexc_$signal$70[0:0]$7125 $3\trapexc_$signal$70[0:0]$7133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" + switch \$71 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $3\trapexc_$signal$70[0:0]$7133 $3\trapexc_$signal$62[0:0]$7129 $3\trapexc_$signal$60[0:0]$7127 $3\trapexc_$signal$61[0:0]$7128 $3\trapexc_$signal[0:0]$7126 $3\trapexc_$signal$69[0:0]$7132 $3\trapexc_$signal$68[0:0]$7131 $3\trapexc_$signal$67[0:0]$7130 } \trap_op__ldst_exc + case + assign $3\trapexc_$signal[0:0]$7126 1'0 + assign $3\trapexc_$signal$60[0:0]$7127 1'0 + assign $3\trapexc_$signal$61[0:0]$7128 1'0 + assign $3\trapexc_$signal$62[0:0]$7129 1'0 + assign $3\trapexc_$signal$67[0:0]$7130 1'0 + assign $3\trapexc_$signal$68[0:0]$7131 1'0 + assign $3\trapexc_$signal$69[0:0]$7132 1'0 + assign $3\trapexc_$signal$70[0:0]$7133 1'0 + end + case + assign $2\trapexc_$signal[0:0]$7118 1'0 + assign $2\trapexc_$signal$60[0:0]$7119 1'0 + assign $2\trapexc_$signal$61[0:0]$7120 1'0 + assign $2\trapexc_$signal$62[0:0]$7121 1'0 + assign $2\trapexc_$signal$67[0:0]$7122 1'0 + assign $2\trapexc_$signal$68[0:0]$7123 1'0 + assign $2\trapexc_$signal$69[0:0]$7124 1'0 + assign $2\trapexc_$signal$70[0:0]$7125 1'0 + end + case + assign $1\trapexc_$signal[0:0]$7110 1'0 + assign $1\trapexc_$signal$60[0:0]$7111 1'0 + assign $1\trapexc_$signal$61[0:0]$7112 1'0 + assign $1\trapexc_$signal$62[0:0]$7113 1'0 + assign $1\trapexc_$signal$67[0:0]$7114 1'0 + assign $1\trapexc_$signal$68[0:0]$7115 1'0 + assign $1\trapexc_$signal$69[0:0]$7116 1'0 + assign $1\trapexc_$signal$70[0:0]$7117 1'0 + end + sync always + update \trapexc_$signal $0\trapexc_$signal[0:0]$7102 + update \trapexc_$signal$60 $0\trapexc_$signal$60[0:0]$7103 + update \trapexc_$signal$61 $0\trapexc_$signal$61[0:0]$7104 + update \trapexc_$signal$62 $0\trapexc_$signal$62[0:0]$7105 + update \trapexc_$signal$67 $0\trapexc_$signal$67[0:0]$7106 + update \trapexc_$signal$68 $0\trapexc_$signal$68[0:0]$7107 + update \trapexc_$signal$69 $0\trapexc_$signal$69[0:0]$7108 + update \trapexc_$signal$70 $0\trapexc_$signal$70[0:0]$7109 + end + attribute \src "libresoc.v:138354.3-138365.6" + process $proc$libresoc.v:138354$7134 + assign { } { } + assign $0\b_s[63:0] $1\b_s[63:0] + attribute \src "libresoc.v:138355.5-138355.29" + switch \initial + attribute \src "libresoc.v:138355.9-138355.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" + switch \trap_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\b_s[63:0] { \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31:0] } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\b_s[63:0] \rb + end + sync always + update \b_s $0\b_s[63:0] + end + attribute \src "libresoc.v:138366.3-138534.6" + process $proc$libresoc.v:138366$7135 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\msr[63:0] $1\msr[63:0] + assign $0\msr_ok[0:0] $1\msr_ok[0:0] + attribute \src "libresoc.v:138367.5-138367.29" + switch \initial + attribute \src "libresoc.v:138367.9-138367.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign { } { } + assign $1\msr[63:0] $2\msr[63:0] + assign $1\msr_ok[0:0] $2\msr_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\msr[63:0] [62:59] $2\msr[63:0] [57:33] $2\msr[63:0] [31:26] $2\msr[63:0] [24] $2\msr[63:0] [22:16] $2\msr[63:0] [12] $2\msr[63:0] [7:6] $2\msr[63:0] [2] } { \trap_op__msr [62:59] \trap_op__msr [57:33] \trap_op__msr [31:26] \trap_op__msr [24] \trap_op__msr [22:16] \trap_op__msr [12] \trap_op__msr [7:6] \trap_op__msr [2] } + assign $2\msr[63:0] [63] 1'1 + assign $2\msr[63:0] [15] 1'0 + assign $2\msr[63:0] [14] 1'0 + assign $2\msr[63:0] [5] 1'0 + assign $2\msr[63:0] [4] 1'0 + assign $2\msr[63:0] [1] 1'0 + assign $2\msr[63:0] [0] 1'1 + assign $2\msr[63:0] [11] 1'0 + assign $2\msr[63:0] [8] 1'0 + assign $2\msr[63:0] [23] 1'0 + assign $2\msr[63:0] [32] 1'0 + assign $2\msr[63:0] [25] 1'0 + assign $2\msr[63:0] [13] 1'0 + assign $2\msr[63:0] [3] 1'0 + assign $2\msr[63:0] [10] 1'0 + assign $2\msr[63:0] [9] 1'0 + assign $2\msr[63:0] [58] 1'0 + assign $2\msr_ok[0:0] 1'1 + case + assign $2\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\msr_ok[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign { } { } + assign { } { } + assign $1\msr[63:0] [0] \$75 [0] + assign $1\msr[63:0] [11:1] $3\msr[11:1] + assign $1\msr[63:0] [59:13] $4\msr[59:13] + assign $1\msr[63:0] [63:61] $5\msr[63:61] + assign $1\msr[63:0] [12] $12\msr[12:12] + assign $1\msr[63:0] [60] $13\msr[60:60] + assign $1\msr_ok[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:227" + switch \trap_op__insn [21] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $3\msr[11:1] [10:1] \$75 [11:2] + assign { $4\msr[59:13] [46:3] $4\msr[59:13] [1:0] } { \$75 [59:16] \$75 [14:13] } + assign $5\msr[63:61] \$75 [63:61] + assign $3\msr[11:1] [0] \ra [1] + assign $4\msr[59:13] [2] \ra [15] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { $3\msr[11:1] [10:5] $3\msr[11:1] [2:0] } { $6\msr[11:1] [10:5] $6\msr[11:1] [2:0] } + assign { $4\msr[59:13] [46:3] $4\msr[59:13] [1:0] } { $7\msr[59:13] [46:3] $7\msr[59:13] [1:0] } + assign $5\msr[63:61] $8\msr[63:61] + assign $3\msr[11:1] [4:3] $10\msr[5:4] + assign $4\msr[59:13] [2] $11\msr[15:15] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" + switch \$77 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $6\msr[11:1] \ra [11:1] + assign { $7\msr[59:13] [46:22] $7\msr[59:13] [18:0] } { \ra [59:35] \ra [31:13] } + assign $8\msr[63:61] \ra [63:61] + assign $7\msr[59:13] [21:19] $9\msr[34:32] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" + switch \$83 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\msr[34:32] \trap_op__msr [34:32] + case + assign $9\msr[34:32] \ra [34:32] + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $7\msr[59:13] [46:19] \$75 [59:32] + assign $8\msr[63:61] \$75 [63:61] + assign $6\msr[11:1] \ra [11:1] + assign $7\msr[59:13] [18:0] \ra [31:13] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:49" + switch $7\msr[59:13] [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $11\msr[15:15] 1'1 + assign $10\msr[5:4] [1] 1'1 + assign $10\msr[5:4] [0] 1'1 + case + assign $10\msr[5:4] $6\msr[11:1] [4:3] + assign $11\msr[15:15] $7\msr[59:13] [2] + end + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" + switch \$85 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $13\msr[60:60] \trap_op__msr [60] + assign $12\msr[12:12] \trap_op__msr [12] + case + assign $12\msr[12:12] \$75 [12] + assign $13\msr[60:60] \$75 [60] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { $1\msr[63:0] [30:27] $1\msr[63:0] [21:16] } 10'0000000000 + assign { } { } + assign { $1\msr[63:0] [14:13] $1\msr[63:0] [11:6] $1\msr[63:0] [3:0] } { \fast2 [14:13] \fast2 [11:6] \fast2 [3:0] } + assign $1\msr[63:0] [26:22] \fast2 [26:22] + assign { $1\msr[63:0] [63:35] $1\msr[63:0] [31] } { \fast2 [63:35] \fast2 [31] } + assign $1\msr[63:0] [12] $14\msr[12:12] + assign $1\msr[63:0] [5:4] $16\msr[5:4] + assign $1\msr[63:0] [15] $17\msr[15:15] + assign $1\msr[63:0] [34:32] $18\msr[34:32] + assign $1\msr_ok[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" + switch \$87 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $14\msr[12:12] $15\msr[12:12] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:283" + switch \trap_op__msr [60] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $15\msr[12:12] \fast2 [12] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $15\msr[12:12] \trap_op__msr [12] + end + case + assign $14\msr[12:12] \fast2 [12] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:49" + switch \fast2 [14] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $17\msr[15:15] 1'1 + assign $16\msr[5:4] [1] 1'1 + assign $16\msr[5:4] [0] 1'1 + case + assign $16\msr[5:4] \fast2 [5:4] + assign $17\msr[15:15] \fast2 [15] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" + switch \$93 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $18\msr[34:32] \trap_op__msr [34:32] + case + assign $18\msr[34:32] \fast2 [34:32] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign { } { } + assign { $1\msr[63:0] [62:59] $1\msr[63:0] [57:33] $1\msr[63:0] [31:26] $1\msr[63:0] [24] $1\msr[63:0] [22:16] $1\msr[63:0] [12] $1\msr[63:0] [7:6] $1\msr[63:0] [2] } { \trap_op__msr [62:59] \trap_op__msr [57:33] \trap_op__msr [31:26] \trap_op__msr [24] \trap_op__msr [22:16] \trap_op__msr [12] \trap_op__msr [7:6] \trap_op__msr [2] } + assign $1\msr[63:0] [63] 1'1 + assign $1\msr[63:0] [15] 1'0 + assign $1\msr[63:0] [14] 1'0 + assign $1\msr[63:0] [5] 1'0 + assign $1\msr[63:0] [4] 1'0 + assign $1\msr[63:0] [1] 1'0 + assign $1\msr[63:0] [0] 1'1 + assign $1\msr[63:0] [11] 1'0 + assign $1\msr[63:0] [8] 1'0 + assign $1\msr[63:0] [23] 1'0 + assign $1\msr[63:0] [32] 1'0 + assign $1\msr[63:0] [25] 1'0 + assign $1\msr[63:0] [13] 1'0 + assign $1\msr[63:0] [3] 1'0 + assign $1\msr[63:0] [10] 1'0 + assign $1\msr[63:0] [9] 1'0 + assign $1\msr[63:0] [58] 1'0 + assign $1\msr_ok[0:0] 1'1 + case + assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr_ok[0:0] 1'0 + end + sync always + update \msr $0\msr[63:0] + update \msr_ok $0\msr_ok[0:0] + end + attribute \src "libresoc.v:138535.3-138553.6" + process $proc$libresoc.v:138535$7136 + assign { } { } + assign { } { } + assign $0\o[63:0] $1\o[63:0] + attribute \src "libresoc.v:138536.5-138536.29" + switch \initial + attribute \src "libresoc.v:138536.9-138536.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign { } { } + assign $1\o[63:0] \trap_op__msr + case + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \o $0\o[63:0] + end + attribute \src "libresoc.v:138554.3-138572.6" + process $proc$libresoc.v:138554$7137 + assign { } { } + assign { } { } + assign $0\o_ok[0:0] $1\o_ok[0:0] + attribute \src "libresoc.v:138555.5-138555.29" + switch \initial + attribute \src "libresoc.v:138555.9-138555.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign $1\o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign { } { } + assign $1\o_ok[0:0] 1'1 + case + assign $1\o_ok[0:0] 1'0 + end + sync always + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:138573.3-138584.6" + process $proc$libresoc.v:138573$7138 + assign { } { } + assign $0\a[63:0] $1\a[63:0] + attribute \src "libresoc.v:138574.5-138574.29" + switch \initial + attribute \src "libresoc.v:138574.9-138574.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" + switch \trap_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a[63:0] \$13 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\a[63:0] \ra + end + sync always + update \a $0\a[63:0] + end + attribute \src "libresoc.v:138585.3-138596.6" + process $proc$libresoc.v:138585$7139 + assign { } { } + assign $0\b[63:0] $1\b[63:0] + attribute \src "libresoc.v:138586.5-138586.29" + switch \initial + attribute \src "libresoc.v:138586.9-138586.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" + switch \trap_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\b[63:0] \$15 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\b[63:0] \rb + end + sync always + update \b $0\b[63:0] + end + connect \$13 $pos$libresoc.v:138034$7040_Y + connect \$15 $pos$libresoc.v:138035$7042_Y + connect \$17 $lt$libresoc.v:138036$7043_Y + connect \$19 $gt$libresoc.v:138037$7044_Y + connect \$21 $lt$libresoc.v:138038$7045_Y + connect \$23 $gt$libresoc.v:138039$7046_Y + connect \$25 $eq$libresoc.v:138040$7047_Y + connect \$28 $and$libresoc.v:138041$7048_Y + connect \$27 $reduce_or$libresoc.v:138042$7049_Y + connect \$31 $reduce_or$libresoc.v:138043$7050_Y + connect \$33 $or$libresoc.v:138044$7051_Y + connect \$36 $sshl$libresoc.v:138045$7052_Y + connect \$35 $pos$libresoc.v:138046$7054_Y + connect \$40 $add$libresoc.v:138047$7055_Y + connect \$42 $eq$libresoc.v:138048$7056_Y + connect \$45 $and$libresoc.v:138049$7057_Y + connect \$44 $reduce_or$libresoc.v:138050$7058_Y + connect \$49 $and$libresoc.v:138051$7059_Y + connect \$48 $reduce_or$libresoc.v:138052$7060_Y + connect \$53 $and$libresoc.v:138053$7061_Y + connect \$52 $reduce_or$libresoc.v:138054$7062_Y + connect \$57 $and$libresoc.v:138055$7063_Y + connect \$56 $reduce_or$libresoc.v:138056$7064_Y + connect \$64 $and$libresoc.v:138057$7065_Y + connect \$63 $reduce_or$libresoc.v:138058$7066_Y + connect \$72 $and$libresoc.v:138059$7067_Y + connect \$71 $reduce_or$libresoc.v:138060$7068_Y + connect \$75 $pos$libresoc.v:138061$7070_Y + connect \$77 $eq$libresoc.v:138062$7071_Y + connect \$79 $eq$libresoc.v:138063$7072_Y + connect \$81 $eq$libresoc.v:138064$7073_Y + connect \$83 $and$libresoc.v:138065$7074_Y + connect \$85 $not$libresoc.v:138066$7075_Y + connect \$87 $not$libresoc.v:138067$7076_Y + connect \$89 $eq$libresoc.v:138068$7077_Y + connect \$91 $eq$libresoc.v:138069$7078_Y + connect \$93 $and$libresoc.v:138070$7079_Y + connect \$39 \$40 + connect { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } + connect \muxid$1 \muxid + connect \should_trap \$33 + connect \trap_bits { \lt_s \gt_s \equal \lt_u \gt_u } + connect \equal \$25 + connect \gt_u \$23 + connect \lt_u \$21 + connect \gt_s \$19 + connect \lt_s \$17 + connect \to \trap_op__insn [25:21] +end +attribute \src "libresoc.v:138612.1-139355.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main" +attribute \generator "nMigen" +module \main$51 + attribute \src "libresoc.v:139322.3-139332.6" + wire width 32 $0\a32[31:0] + attribute \src "libresoc.v:139267.3-139277.6" + wire width 64 $0\b[63:0] + attribute \src "libresoc.v:139245.3-139255.6" + wire width 64 $0\bpermd_rb[63:0] + attribute \src "libresoc.v:139234.3-139244.6" + wire width 64 $0\bpermd_rs[63:0] + attribute \src "libresoc.v:139223.3-139233.6" + wire width 64 $0\clz_sig_in[63:0] + attribute \src "libresoc.v:139333.3-139351.6" + wire width 64 $0\cntz_i[63:0] + attribute \src "libresoc.v:139311.3-139321.6" + wire $0\count_right[0:0] + attribute \src "libresoc.v:138613.7-138613.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:139168.3-139222.6" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:139168.3-139222.6" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:139289.3-139299.6" + wire $0\par0[0:0] + attribute \src "libresoc.v:139300.3-139310.6" + wire $0\par1[0:0] + attribute \src "libresoc.v:139256.3-139266.6" + wire width 64 $0\popcount_a[63:0] + attribute \src "libresoc.v:139278.3-139288.6" + wire width 64 $0\popcount_data_len[63:0] + attribute \src "libresoc.v:139322.3-139332.6" + wire width 32 $1\a32[31:0] + attribute \src "libresoc.v:139267.3-139277.6" + wire width 64 $1\b[63:0] + attribute \src "libresoc.v:139245.3-139255.6" + wire width 64 $1\bpermd_rb[63:0] + attribute \src "libresoc.v:139234.3-139244.6" + wire width 64 $1\bpermd_rs[63:0] + attribute \src "libresoc.v:139223.3-139233.6" + wire width 64 $1\clz_sig_in[63:0] + attribute \src "libresoc.v:139333.3-139351.6" + wire width 64 $1\cntz_i[63:0] + attribute \src "libresoc.v:139311.3-139321.6" + wire $1\count_right[0:0] + attribute \src "libresoc.v:139168.3-139222.6" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:139168.3-139222.6" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:139289.3-139299.6" + wire $1\par0[0:0] + attribute \src "libresoc.v:139300.3-139310.6" + wire $1\par1[0:0] + attribute \src "libresoc.v:139256.3-139266.6" + wire width 64 $1\popcount_a[63:0] + attribute \src "libresoc.v:139278.3-139288.6" + wire width 64 $1\popcount_data_len[63:0] + attribute \src "libresoc.v:139333.3-139351.6" + wire width 64 $2\cntz_i[63:0] + attribute \src "libresoc.v:139168.3-139222.6" + wire width 64 $2\o[63:0] + attribute \src "libresoc.v:139115.18-139115.103" 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"NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 24 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 25 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 33 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 40 \logical_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 23 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 44 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 22 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 41 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 42 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:84" + wire \par0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:85" + wire \par1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:27" + wire width 64 \popcount_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:29" + wire width 64 \popcount_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:30" + wire width 64 \popcount_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 43 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" + cell $and $and$libresoc.v:139115$7187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \B \rb + connect \Y $and$libresoc.v:139115$7187_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:139074$7141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:139074$7141_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:139075$7142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:139075$7142_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:139076$7143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:139076$7143_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:139077$7144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:139077$7144_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:139078$7145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:139078$7145_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:139079$7146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:139079$7146_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:139080$7147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:139080$7147_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:139081$7148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:139081$7148_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:139082$7149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:139082$7149_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:139083$7150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:139083$7150_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:139084$7151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:139084$7151_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:139085$7152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:139085$7152_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:139086$7153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:139086$7153_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:139087$7154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:139087$7154_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:139088$7155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:139088$7155_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:139089$7156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter 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cell $eq $eq$libresoc.v:139152$7224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:139152$7224_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:139153$7225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:139153$7225_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" + cell $pos $extend$libresoc.v:139104$7171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 64 + connect \A \$158 + connect \Y $extend$libresoc.v:139104$7171_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" + cell $pos $extend$libresoc.v:139106$7174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A \clz_lz + connect \Y $extend$libresoc.v:139106$7174_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" + cell $pos $extend$libresoc.v:139108$7177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 64 + connect \A \$166 + connect \Y $extend$libresoc.v:139108$7177_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + cell $pos $extend$libresoc.v:139109$7179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 64 + connect \A \logical_op__data_len + connect \Y $extend$libresoc.v:139109$7179_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" + cell $pos $extend$libresoc.v:139113$7184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \$176 + connect \Y $extend$libresoc.v:139113$7184_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" + cell $or $or$libresoc.v:139116$7188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \B \rb + connect \Y $or$libresoc.v:139116$7188_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" + cell $pos $pos$libresoc.v:139104$7172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:139104$7171_Y + connect \Y $pos$libresoc.v:139104$7172_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" + cell $pos $pos$libresoc.v:139106$7175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:139106$7174_Y + connect \Y $pos$libresoc.v:139106$7175_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" + cell $pos $pos$libresoc.v:139108$7178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:139108$7177_Y + connect \Y $pos$libresoc.v:139108$7178_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + cell $pos $pos$libresoc.v:139109$7180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:139109$7179_Y + connect \Y $pos$libresoc.v:139109$7180_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" + cell $pos $pos$libresoc.v:139113$7185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:139113$7184_Y + connect \Y $pos$libresoc.v:139113$7185_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" + cell $reduce_xor $reduce_xor$libresoc.v:139110$7181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \ra [24] \ra [16] \ra [8] \ra [0] } + connect \Y $reduce_xor$libresoc.v:139110$7181_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" + cell $reduce_xor $reduce_xor$libresoc.v:139111$7182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \ra [56] \ra [48] \ra [40] \ra [32] } + connect \Y $reduce_xor$libresoc.v:139111$7182_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" + cell $sub $sub$libresoc.v:139105$7173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 8 + connect \A \clz_lz + connect \B 6'100000 + connect \Y $sub$libresoc.v:139105$7173_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" + cell $mux $ternary$libresoc.v:139107$7176 + parameter \WIDTH 8 + connect \A \$164 + connect \B \$162 + connect \S \logical_op__is_32bit + connect \Y $ternary$libresoc.v:139107$7176_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" + cell $mux $ternary$libresoc.v:139112$7183 + parameter \WIDTH 32 + connect \A \a32 + connect \B { \a32 [0] \a32 [1] \a32 [2] \a32 [3] \a32 [4] \a32 [5] \a32 [6] \a32 [7] \a32 [8] \a32 [9] \a32 [10] \a32 [11] \a32 [12] \a32 [13] \a32 [14] \a32 [15] \a32 [16] \a32 [17] \a32 [18] \a32 [19] \a32 [20] \a32 [21] \a32 [22] \a32 [23] \a32 [24] \a32 [25] \a32 [26] \a32 [27] \a32 [28] \a32 [29] \a32 [30] \a32 [31] } + connect \S \count_right + connect \Y $ternary$libresoc.v:139112$7183_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109" + cell $mux $ternary$libresoc.v:139114$7186 + parameter \WIDTH 64 + connect \A \ra + connect \B { \ra [0] \ra [1] \ra [2] \ra [3] \ra [4] \ra [5] \ra [6] \ra [7] \ra [8] \ra [9] \ra [10] \ra [11] \ra [12] \ra [13] \ra [14] \ra [15] \ra [16] \ra [17] \ra [18] \ra [19] \ra [20] \ra [21] \ra [22] \ra [23] \ra [24] \ra [25] \ra [26] \ra [27] \ra [28] \ra [29] \ra [30] \ra [31] \ra [32] \ra [33] \ra [34] \ra [35] \ra [36] \ra [37] \ra [38] \ra [39] \ra [40] \ra [41] \ra [42] \ra [43] \ra [44] \ra [45] \ra [46] \ra [47] \ra [48] \ra [49] \ra [50] \ra [51] \ra [52] \ra [53] \ra [54] \ra [55] \ra [56] \ra [57] \ra [58] \ra [59] \ra [60] \ra [61] \ra [62] \ra [63] } + connect \S \count_right + connect \Y $ternary$libresoc.v:139114$7186_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" + cell $xor $xor$libresoc.v:139103$7170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \par0 + connect \B \par1 + connect \Y $xor$libresoc.v:139103$7170_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58" + cell $xor $xor$libresoc.v:139117$7189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \B \rb + connect \Y $xor$libresoc.v:139117$7189_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:139154.10-139158.4" + cell \bpermd \bpermd + connect \ra \bpermd_ra + connect \rb \bpermd_rb + connect \rs \bpermd_rs + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:139159.7-139162.4" + cell \clz \clz + connect \lz \clz_lz + connect \sig_in \clz_sig_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:139163.12-139167.4" + cell \popcount \popcount + connect \a \popcount_a + connect \data_len \popcount_data_len + connect \o \popcount_o + end + attribute \src "libresoc.v:138613.7-138613.20" + process $proc$libresoc.v:138613$7238 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:139168.3-139222.6" + process $proc$libresoc.v:139168$7226 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o_ok[0:0] $1\o_ok[0:0] + assign $0\o[63:0] $1\o[63:0] + attribute \src "libresoc.v:139169.5-139169.29" + switch \initial + attribute \src "libresoc.v:139169.9-139169.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000100 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] \$21 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110101 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] \$23 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000011 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] \$25 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001011 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] { \$139 \$141 \$143 \$145 \$147 \$149 \$151 \$153 \$123 \$125 \$127 \$129 \$131 \$133 \$135 \$137 \$107 \$109 \$111 \$113 \$115 \$117 \$119 \$121 \$91 \$93 \$95 \$97 \$99 \$101 \$103 \$105 \$75 \$77 \$79 \$81 \$83 \$85 \$87 \$89 \$59 \$61 \$63 \$65 \$67 \$69 \$71 \$73 \$43 \$45 \$47 \$49 \$51 \$53 \$55 \$57 \$27 \$29 \$31 \$33 \$35 \$37 \$39 \$41 } + attribute \src "libresoc.v:0.0-0.0" + case 7'0110110 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] \popcount_o + attribute \src "libresoc.v:0.0-0.0" + case 7'0110111 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] $2\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" + switch \$155 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o[63:0] \$157 + attribute \src "libresoc.v:0.0-0.0" + case + assign { $2\o[63:0] [63:33] $2\o[63:0] [31:1] } 62'00000000000000000000000000000000000000000000000000000000000000 + assign $2\o[63:0] [0] \par0 + assign $2\o[63:0] [32] \par1 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'0001110 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] \$161 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001001 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] \bpermd_ra + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\o_ok[0:0] 1'0 + end + sync always + update \o_ok $0\o_ok[0:0] + update \o $0\o[63:0] + end + attribute \src "libresoc.v:139223.3-139233.6" + process $proc$libresoc.v:139223$7227 + assign { } { } + assign { } { } + assign $0\clz_sig_in[63:0] $1\clz_sig_in[63:0] + attribute \src "libresoc.v:139224.5-139224.29" + switch \initial + attribute \src "libresoc.v:139224.9-139224.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001110 + assign { } { } + assign $1\clz_sig_in[63:0] \cntz_i + case + assign $1\clz_sig_in[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \clz_sig_in $0\clz_sig_in[63:0] + end + attribute \src "libresoc.v:139234.3-139244.6" + process $proc$libresoc.v:139234$7228 + assign { } { } + assign { } { } + assign $0\bpermd_rs[63:0] $1\bpermd_rs[63:0] + attribute \src "libresoc.v:139235.5-139235.29" + switch \initial + attribute \src "libresoc.v:139235.9-139235.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001001 + assign { } { } + assign $1\bpermd_rs[63:0] \ra + case + assign $1\bpermd_rs[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \bpermd_rs $0\bpermd_rs[63:0] + end + attribute \src "libresoc.v:139245.3-139255.6" + process $proc$libresoc.v:139245$7229 + assign { } { } + assign { } { } + assign $0\bpermd_rb[63:0] $1\bpermd_rb[63:0] + attribute \src "libresoc.v:139246.5-139246.29" + switch \initial + attribute \src "libresoc.v:139246.9-139246.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001001 + assign { } { } + assign $1\bpermd_rb[63:0] \rb + case + assign $1\bpermd_rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \bpermd_rb $0\bpermd_rb[63:0] + end + attribute \src "libresoc.v:139256.3-139266.6" + process $proc$libresoc.v:139256$7230 + assign { } { } + assign { } { } + assign $0\popcount_a[63:0] $1\popcount_a[63:0] + attribute \src "libresoc.v:139257.5-139257.29" + switch \initial + attribute \src "libresoc.v:139257.9-139257.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110110 + assign { } { } + assign $1\popcount_a[63:0] \ra + case + assign $1\popcount_a[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \popcount_a $0\popcount_a[63:0] + end + attribute \src "libresoc.v:139267.3-139277.6" + process $proc$libresoc.v:139267$7231 + assign { } { } + assign { } { } + assign $0\b[63:0] $1\b[63:0] + attribute \src "libresoc.v:139268.5-139268.29" + switch \initial + attribute \src "libresoc.v:139268.9-139268.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110110 + assign { } { } + assign $1\b[63:0] \rb + case + assign $1\b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \b $0\b[63:0] + end + attribute \src "libresoc.v:139278.3-139288.6" + process $proc$libresoc.v:139278$7232 + assign { } { } + assign { } { } + assign $0\popcount_data_len[63:0] $1\popcount_data_len[63:0] + attribute \src "libresoc.v:139279.5-139279.29" + switch \initial + attribute \src "libresoc.v:139279.9-139279.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110110 + assign { } { } + assign $1\popcount_data_len[63:0] \$169 + case + assign $1\popcount_data_len[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \popcount_data_len $0\popcount_data_len[63:0] + end + attribute \src "libresoc.v:139289.3-139299.6" + process $proc$libresoc.v:139289$7233 + assign { } { } + assign { } { } + assign $0\par0[0:0] $1\par0[0:0] + attribute \src "libresoc.v:139290.5-139290.29" + switch \initial + attribute \src "libresoc.v:139290.9-139290.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110111 + assign { } { } + assign $1\par0[0:0] \$171 + case + assign $1\par0[0:0] 1'0 + end + sync always + update \par0 $0\par0[0:0] + end + attribute \src "libresoc.v:139300.3-139310.6" + process $proc$libresoc.v:139300$7234 + assign { } { } + assign { } { } + assign $0\par1[0:0] $1\par1[0:0] + attribute \src "libresoc.v:139301.5-139301.29" + switch \initial + attribute \src "libresoc.v:139301.9-139301.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110111 + assign { } { } + assign $1\par1[0:0] \$173 + case + assign $1\par1[0:0] 1'0 + end + sync always + update \par1 $0\par1[0:0] + end + attribute \src "libresoc.v:139311.3-139321.6" + process $proc$libresoc.v:139311$7235 + assign { } { } + assign { } { } + assign $0\count_right[0:0] $1\count_right[0:0] + attribute \src "libresoc.v:139312.5-139312.29" + switch \initial + attribute \src "libresoc.v:139312.9-139312.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001110 + assign { } { } + assign $1\count_right[0:0] \logical_op__insn [10] + case + assign $1\count_right[0:0] 1'0 + end + sync always + update \count_right $0\count_right[0:0] + end + attribute \src "libresoc.v:139322.3-139332.6" + process $proc$libresoc.v:139322$7236 + assign { } { } + assign { } { } + assign $0\a32[31:0] $1\a32[31:0] + attribute \src "libresoc.v:139323.5-139323.29" + switch \initial + attribute \src "libresoc.v:139323.9-139323.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001110 + assign { } { } + assign $1\a32[31:0] \ra [31:0] + case + assign $1\a32[31:0] 0 + end + sync always + update \a32 $0\a32[31:0] + end + attribute \src "libresoc.v:139333.3-139351.6" + process $proc$libresoc.v:139333$7237 + assign { } { } + assign { } { } + assign $0\cntz_i[63:0] $1\cntz_i[63:0] + attribute \src "libresoc.v:139334.5-139334.29" + switch \initial + attribute \src "libresoc.v:139334.9-139334.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001110 + assign { } { } + assign $1\cntz_i[63:0] $2\cntz_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:106" + switch \logical_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cntz_i[63:0] \$175 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cntz_i[63:0] \$179 + end + case + assign $1\cntz_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \cntz_i $0\cntz_i[63:0] + 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\enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 11 \cr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 32 input 6 \full_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 32 output 16 \full_cr$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 17 \full_cr_ok + attribute \src "libresoc.v:139360.7-139360.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" + wire width 4 \lut + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 20 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 10 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 14 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 15 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 4 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 5 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$libresoc.v:139631$7245 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \full_cr + connect \Y $extend$libresoc.v:139631$7245_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" + cell $pos $extend$libresoc.v:139633$7248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \$27 + connect \Y $extend$libresoc.v:139633$7248_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$libresoc.v:139634$7250 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 5 + connect \A \cr_a + connect \Y $extend$libresoc.v:139634$7250_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:139631$7246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:139631$7245_Y + connect \Y $pos$libresoc.v:139631$7246_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" + cell $pos $pos$libresoc.v:139633$7249 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:139633$7248_Y + connect \Y $pos$libresoc.v:139633$7249_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:139634$7251 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A $extend$libresoc.v:139634$7250_Y + connect \Y $pos$libresoc.v:139634$7251_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" + cell $sub $sub$libresoc.v:139625$7239 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A 2'11 + connect \B \cr_op__insn [22:21] + connect \Y $sub$libresoc.v:139625$7239_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" + cell $sub $sub$libresoc.v:139626$7240 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A 2'11 + connect \B \cr_op__insn [17:16] + connect \Y $sub$libresoc.v:139626$7240_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" + cell $sub $sub$libresoc.v:139627$7241 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A 2'11 + connect \B \cr_op__insn [12:11] + connect \Y $sub$libresoc.v:139627$7241_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" + cell $mux $ternary$libresoc.v:139628$7242 + parameter \WIDTH 1 + connect \A \lut [1] + connect \B \lut [3] + connect \S \bit_a + connect \Y $ternary$libresoc.v:139628$7242_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" + cell $mux $ternary$libresoc.v:139629$7243 + parameter \WIDTH 1 + connect \A \lut [0] + connect \B \lut [2] + connect \S \bit_a + connect \Y $ternary$libresoc.v:139629$7243_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" + cell $mux $ternary$libresoc.v:139630$7244 + parameter \WIDTH 1 + connect \A \$20 + connect \B \$18 + connect \S \bit_b + connect \Y $ternary$libresoc.v:139630$7244_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" + cell $mux $ternary$libresoc.v:139632$7247 + parameter \WIDTH 64 + connect \A \rb + connect \B \ra + connect \S \cr_bit + connect \Y $ternary$libresoc.v:139632$7247_Y + end + attribute \src "libresoc.v:139360.7-139360.20" + process $proc$libresoc.v:139360$7270 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:139635.3-139669.6" + process $proc$libresoc.v:139635$7252 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] + assign $0\cr_a$6[3:0]$7253 $1\cr_a$6[3:0]$7254 + attribute \src "libresoc.v:139636.5-139636.29" + switch \initial + attribute \src "libresoc.v:139636.9-139636.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0101010 + assign { } { } + assign { } { } + assign $1\cr_a$6[3:0]$7254 \$7 [3:0] + assign $1\cr_a_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign { } { } + assign { } { } + assign $1\cr_a$6[3:0]$7254 $2\cr_a$6[3:0]$7255 + assign $1\cr_a_ok[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:105" + switch \bt + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign $2\cr_a$6[3:0]$7255 [3:1] \cr_c [3:1] + assign $2\cr_a$6[3:0]$7255 [0] \bit_o + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { $2\cr_a$6[3:0]$7255 [3:2] $2\cr_a$6[3:0]$7255 [0] } { \cr_c [3:2] \cr_c [0] } + assign $2\cr_a$6[3:0]$7255 [1] \bit_o + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { $2\cr_a$6[3:0]$7255 [3] $2\cr_a$6[3:0]$7255 [1:0] } { \cr_c [3] \cr_c [1:0] } + assign $2\cr_a$6[3:0]$7255 [2] \bit_o + attribute \src "libresoc.v:0.0-0.0" + case 2'-- + assign $2\cr_a$6[3:0]$7255 [2:0] \cr_c [2:0] + assign $2\cr_a$6[3:0]$7255 [3] \bit_o + case + assign $2\cr_a$6[3:0]$7255 \cr_c + end + case + assign $1\cr_a_ok[0:0] 1'0 + assign $1\cr_a$6[3:0]$7254 4'0000 + end + sync always + update \cr_a_ok $0\cr_a_ok[0:0] + update \cr_a$6 $0\cr_a$6[3:0]$7253 + end + attribute \src "libresoc.v:139670.3-139680.6" + process $proc$libresoc.v:139670$7256 + assign { } { } + assign { } { } + assign $0\full_cr_ok[0:0] $1\full_cr_ok[0:0] + attribute \src "libresoc.v:139671.5-139671.29" + switch \initial + attribute \src "libresoc.v:139671.9-139671.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110000 + assign { } { } + assign $1\full_cr_ok[0:0] 1'1 + case + assign $1\full_cr_ok[0:0] 1'0 + end + sync always + update \full_cr_ok $0\full_cr_ok[0:0] + end + attribute \src "libresoc.v:139681.3-139722.6" + process $proc$libresoc.v:139681$7257 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o_ok[0:0] $1\o_ok[0:0] + assign $0\o[63:0] $1\o[63:0] + attribute \src "libresoc.v:139682.5-139682.29" + switch \initial + attribute \src "libresoc.v:139682.9-139682.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0101101 + assign { } { } + assign { } { } + assign $1\o[63:0] \$24 + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0100011 + assign { } { } + assign { } { } + assign $1\o[63:0] \$26 [63:0] + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0111011 + assign { } { } + assign { } { } + assign $1\o[63:0] $2\o[63:0] + assign $1\o_ok[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:144" + switch { \cr_a [2] \cr_a [3] } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\o[63:0] 64'1111111111111111111111111111111111111111111111111111111111111111 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000001 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\o_ok[0:0] 1'0 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \o_ok $0\o_ok[0:0] + update \o $0\o[63:0] + end + attribute \src "libresoc.v:139723.3-139733.6" + process $proc$libresoc.v:139723$7258 + assign { } { } + assign { } { } + assign $0\BC[1:0] $1\BC[1:0] + attribute \src "libresoc.v:139724.5-139724.29" + switch \initial + attribute \src "libresoc.v:139724.9-139724.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0100011 + assign { } { } + assign $1\BC[1:0] \cr_op__insn [7:6] + case + assign $1\BC[1:0] 2'00 + end + sync always + update \BC $0\BC[1:0] + end + attribute \src "libresoc.v:139734.3-139754.6" + process $proc$libresoc.v:139734$7259 + assign { } { } + assign { } { } + assign $0\cr_bit[0:0] $1\cr_bit[0:0] + attribute \src "libresoc.v:139735.5-139735.29" + switch \initial + attribute \src "libresoc.v:139735.9-139735.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0100011 + assign { } { } + assign $1\cr_bit[0:0] $2\cr_bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:137" + switch \BC + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $2\cr_bit[0:0] \cr_a [3] + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $2\cr_bit[0:0] \cr_a [2] + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\cr_bit[0:0] \cr_a [1] + attribute \src "libresoc.v:0.0-0.0" + case 2'-- + assign { } { } + assign $2\cr_bit[0:0] \cr_a [0] + case + assign $2\cr_bit[0:0] 1'0 + end + case + assign $1\cr_bit[0:0] 1'0 + end + sync always + update \cr_bit $0\cr_bit[0:0] + end + attribute \src "libresoc.v:139755.3-139765.6" + process $proc$libresoc.v:139755$7260 + assign { } { } + assign { } { } + assign $0\lut[3:0] $1\lut[3:0] + attribute \src "libresoc.v:139756.5-139756.29" + switch \initial + attribute \src "libresoc.v:139756.9-139756.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\lut[3:0] \cr_op__insn [9:6] + case + assign $1\lut[3:0] 4'0000 + end + sync always + update \lut $0\lut[3:0] + end + attribute \src "libresoc.v:139766.3-139776.6" + process $proc$libresoc.v:139766$7261 + assign { } { } + assign { } { } + assign $0\bt[1:0] $1\bt[1:0] + attribute \src "libresoc.v:139767.5-139767.29" + switch \initial + attribute \src "libresoc.v:139767.9-139767.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\bt[1:0] \$9 [1:0] + case + assign $1\bt[1:0] 2'00 + end + sync always + update \bt $0\bt[1:0] + end + attribute \src "libresoc.v:139777.3-139787.6" + process $proc$libresoc.v:139777$7262 + assign { } { } + assign { } { } + assign $0\ba[1:0] $1\ba[1:0] + attribute \src "libresoc.v:139778.5-139778.29" + switch \initial + attribute \src "libresoc.v:139778.9-139778.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\ba[1:0] \$12 [1:0] + case + assign $1\ba[1:0] 2'00 + end + sync always + update \ba $0\ba[1:0] + end + attribute \src "libresoc.v:139788.3-139798.6" + process $proc$libresoc.v:139788$7263 + assign { } { } + assign { } { } + assign $0\bb[1:0] $1\bb[1:0] + attribute \src "libresoc.v:139789.5-139789.29" + switch \initial + attribute \src "libresoc.v:139789.9-139789.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\bb[1:0] \$15 [1:0] + case + assign $1\bb[1:0] 2'00 + end + sync always + update \bb $0\bb[1:0] + end + attribute \src "libresoc.v:139799.3-139819.6" + process $proc$libresoc.v:139799$7264 + assign { } { } + assign { } { } + assign $0\bit_a[0:0] $1\bit_a[0:0] + attribute \src "libresoc.v:139800.5-139800.29" + switch \initial + attribute \src "libresoc.v:139800.9-139800.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\bit_a[0:0] $2\bit_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:93" + switch \ba + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $2\bit_a[0:0] \cr_a [0] + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $2\bit_a[0:0] \cr_a [1] + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\bit_a[0:0] \cr_a [2] + attribute \src "libresoc.v:0.0-0.0" + case 2'-- + assign { } { } + assign $2\bit_a[0:0] \cr_a [3] + case + assign $2\bit_a[0:0] 1'0 + end + case + assign $1\bit_a[0:0] 1'0 + end + sync always + update \bit_a $0\bit_a[0:0] + end + attribute \src "libresoc.v:139820.3-139840.6" + process $proc$libresoc.v:139820$7265 + assign { } { } + assign { } { } + assign $0\bit_b[0:0] $1\bit_b[0:0] + attribute \src "libresoc.v:139821.5-139821.29" + switch \initial + attribute \src "libresoc.v:139821.9-139821.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\bit_b[0:0] $2\bit_b[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:94" + switch \bb + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $2\bit_b[0:0] \cr_b [0] + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $2\bit_b[0:0] \cr_b [1] + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\bit_b[0:0] \cr_b [2] + attribute \src "libresoc.v:0.0-0.0" + case 2'-- + assign { } { } + assign $2\bit_b[0:0] \cr_b [3] + case + assign $2\bit_b[0:0] 1'0 + end + case + assign $1\bit_b[0:0] 1'0 + end + sync always + update \bit_b $0\bit_b[0:0] + end + attribute \src "libresoc.v:139841.3-139851.6" + process $proc$libresoc.v:139841$7266 + assign { } { } + assign { } { } + assign $0\bit_o[0:0] $1\bit_o[0:0] + attribute \src "libresoc.v:139842.5-139842.29" + switch \initial + attribute \src "libresoc.v:139842.9-139842.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\bit_o[0:0] \$22 + case + assign $1\bit_o[0:0] 1'0 + end + sync always + update \bit_o $0\bit_o[0:0] + end + attribute \src "libresoc.v:139852.3-139862.6" + process $proc$libresoc.v:139852$7267 + assign { } { } + assign { } { } + assign $0\full_cr$5[31:0]$7268 $1\full_cr$5[31:0]$7269 + attribute \src "libresoc.v:139853.5-139853.29" + switch \initial + attribute \src "libresoc.v:139853.9-139853.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110000 + assign { } { } + assign $1\full_cr$5[31:0]$7269 \ra [31:0] + case + assign $1\full_cr$5[31:0]$7269 0 + end + sync always + update \full_cr$5 $0\full_cr$5[31:0]$7268 + end + connect \$10 $sub$libresoc.v:139625$7239_Y + connect \$13 $sub$libresoc.v:139626$7240_Y + connect \$16 $sub$libresoc.v:139627$7241_Y + connect \$18 $ternary$libresoc.v:139628$7242_Y + connect \$20 $ternary$libresoc.v:139629$7243_Y + connect \$22 $ternary$libresoc.v:139630$7244_Y + connect \$24 $pos$libresoc.v:139631$7246_Y + connect \$27 $ternary$libresoc.v:139632$7247_Y + connect \$26 $pos$libresoc.v:139633$7249_Y + connect \$7 $pos$libresoc.v:139634$7251_Y + connect \$9 \$10 + connect \$12 \$13 + connect \$15 \$16 + connect { \cr_op__insn$4 \cr_op__fn_unit$3 \cr_op__insn_type$2 } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } + connect \muxid$1 \muxid +end +attribute \src "libresoc.v:139872.1-141027.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0" +attribute \generator "nMigen" +module \mul0 + attribute \src "libresoc.v:140598.3-140599.25" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:140596.3-140597.40" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:140939.3-140947.6" + wire $0\alu_l_r_alu$next[0:0]$7476 + attribute \src "libresoc.v:140524.3-140525.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:140779.3-140811.6" + wire width 12 $0\alu_mul0_mul_op__fn_unit$next[11:0]$7401 + attribute \src "libresoc.v:140552.3-140553.65" + wire width 12 $0\alu_mul0_mul_op__fn_unit[11:0] + attribute \src "libresoc.v:140779.3-140811.6" + wire width 64 $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7402 + attribute \src "libresoc.v:140554.3-140555.79" + wire width 64 $0\alu_mul0_mul_op__imm_data__data[63:0] + attribute \src "libresoc.v:140779.3-140811.6" + wire $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7403 + attribute \src "libresoc.v:140556.3-140557.75" + wire $0\alu_mul0_mul_op__imm_data__ok[0:0] + attribute \src "libresoc.v:140779.3-140811.6" + wire width 32 $0\alu_mul0_mul_op__insn$next[31:0]$7404 + attribute \src "libresoc.v:140572.3-140573.59" + wire width 32 $0\alu_mul0_mul_op__insn[31:0] + attribute \src "libresoc.v:140779.3-140811.6" + wire width 7 $0\alu_mul0_mul_op__insn_type$next[6:0]$7405 + attribute \src "libresoc.v:140550.3-140551.69" + wire width 7 $0\alu_mul0_mul_op__insn_type[6:0] + attribute \src "libresoc.v:140779.3-140811.6" + wire $0\alu_mul0_mul_op__is_32bit$next[0:0]$7406 + attribute \src "libresoc.v:140568.3-140569.67" + wire $0\alu_mul0_mul_op__is_32bit[0:0] + attribute \src "libresoc.v:140779.3-140811.6" + wire $0\alu_mul0_mul_op__is_signed$next[0:0]$7407 + attribute \src "libresoc.v:140570.3-140571.69" + wire $0\alu_mul0_mul_op__is_signed[0:0] + attribute \src "libresoc.v:140779.3-140811.6" + wire $0\alu_mul0_mul_op__oe__oe$next[0:0]$7408 + attribute \src "libresoc.v:140562.3-140563.63" + wire $0\alu_mul0_mul_op__oe__oe[0:0] + attribute \src "libresoc.v:140779.3-140811.6" + wire $0\alu_mul0_mul_op__oe__ok$next[0:0]$7409 + attribute \src "libresoc.v:140564.3-140565.63" + wire $0\alu_mul0_mul_op__oe__ok[0:0] + attribute \src "libresoc.v:140779.3-140811.6" + wire $0\alu_mul0_mul_op__rc__ok$next[0:0]$7410 + attribute \src "libresoc.v:140560.3-140561.63" + wire $0\alu_mul0_mul_op__rc__ok[0:0] + attribute \src "libresoc.v:140779.3-140811.6" + wire $0\alu_mul0_mul_op__rc__rc$next[0:0]$7411 + attribute \src "libresoc.v:140558.3-140559.63" + wire $0\alu_mul0_mul_op__rc__rc[0:0] + attribute \src "libresoc.v:140779.3-140811.6" + wire $0\alu_mul0_mul_op__write_cr0$next[0:0]$7412 + attribute \src "libresoc.v:140566.3-140567.69" + wire $0\alu_mul0_mul_op__write_cr0[0:0] + attribute \src "libresoc.v:140930.3-140938.6" + wire $0\alui_l_r_alui$next[0:0]$7473 + attribute \src "libresoc.v:140526.3-140527.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:140812.3-140833.6" + wire width 64 $0\data_r0__o$next[63:0]$7432 + attribute \src "libresoc.v:140546.3-140547.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "libresoc.v:140812.3-140833.6" + wire $0\data_r0__o_ok$next[0:0]$7433 + attribute \src "libresoc.v:140548.3-140549.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "libresoc.v:140834.3-140855.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$7440 + attribute \src "libresoc.v:140542.3-140543.43" + wire width 4 $0\data_r1__cr_a[3:0] + attribute \src "libresoc.v:140834.3-140855.6" + wire $0\data_r1__cr_a_ok$next[0:0]$7441 + attribute \src "libresoc.v:140544.3-140545.49" + wire $0\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:140856.3-140877.6" + wire width 2 $0\data_r2__xer_ov$next[1:0]$7448 + attribute \src "libresoc.v:140538.3-140539.47" + wire width 2 $0\data_r2__xer_ov[1:0] + attribute \src "libresoc.v:140856.3-140877.6" + wire $0\data_r2__xer_ov_ok$next[0:0]$7449 + attribute \src "libresoc.v:140540.3-140541.53" + wire $0\data_r2__xer_ov_ok[0:0] + attribute \src "libresoc.v:140878.3-140899.6" + wire $0\data_r3__xer_so$next[0:0]$7456 + attribute \src "libresoc.v:140534.3-140535.47" + wire $0\data_r3__xer_so[0:0] + attribute \src "libresoc.v:140878.3-140899.6" + wire $0\data_r3__xer_so_ok$next[0:0]$7457 + attribute \src "libresoc.v:140536.3-140537.53" + wire $0\data_r3__xer_so_ok[0:0] + attribute \src "libresoc.v:140948.3-140957.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:140958.3-140967.6" + wire width 4 $0\dest2_o[3:0] + attribute \src "libresoc.v:140968.3-140977.6" + wire width 2 $0\dest3_o[1:0] + attribute \src "libresoc.v:140978.3-140987.6" + wire $0\dest4_o[0:0] + attribute \src "libresoc.v:139873.7-139873.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:140734.3-140742.6" + wire $0\opc_l_r_opc$next[0:0]$7386 + attribute \src "libresoc.v:140582.3-140583.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:140725.3-140733.6" + wire $0\opc_l_s_opc$next[0:0]$7383 + attribute \src "libresoc.v:140584.3-140585.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:140988.3-140996.6" + wire width 4 $0\prev_wr_go$next[3:0]$7483 + attribute \src "libresoc.v:140594.3-140595.37" + wire width 4 $0\prev_wr_go[3:0] + attribute \src "libresoc.v:140679.3-140688.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:140770.3-140778.6" + wire width 4 $0\req_l_r_req$next[3:0]$7398 + attribute \src "libresoc.v:140574.3-140575.39" + wire width 4 $0\req_l_r_req[3:0] + attribute \src "libresoc.v:140761.3-140769.6" + wire width 4 $0\req_l_s_req$next[3:0]$7395 + attribute \src "libresoc.v:140576.3-140577.39" + wire width 4 $0\req_l_s_req[3:0] + attribute \src "libresoc.v:140698.3-140706.6" + wire $0\rok_l_r_rdok$next[0:0]$7374 + attribute \src "libresoc.v:140590.3-140591.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:140689.3-140697.6" + wire $0\rok_l_s_rdok$next[0:0]$7371 + attribute \src "libresoc.v:140592.3-140593.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:140716.3-140724.6" + wire $0\rst_l_r_rst$next[0:0]$7380 + attribute \src "libresoc.v:140586.3-140587.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:140707.3-140715.6" + wire $0\rst_l_s_rst$next[0:0]$7377 + attribute \src "libresoc.v:140588.3-140589.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:140752.3-140760.6" + wire width 3 $0\src_l_r_src$next[2:0]$7392 + attribute \src "libresoc.v:140578.3-140579.39" + wire width 3 $0\src_l_r_src[2:0] + attribute \src "libresoc.v:140743.3-140751.6" + wire width 3 $0\src_l_s_src$next[2:0]$7389 + attribute \src "libresoc.v:140580.3-140581.39" + wire width 3 $0\src_l_s_src[2:0] + attribute \src "libresoc.v:140900.3-140909.6" + wire width 64 $0\src_r0$next[63:0]$7464 + attribute \src "libresoc.v:140532.3-140533.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:140910.3-140919.6" + wire width 64 $0\src_r1$next[63:0]$7467 + attribute \src "libresoc.v:140530.3-140531.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:140920.3-140929.6" + wire $0\src_r2$next[0:0]$7470 + attribute \src "libresoc.v:140528.3-140529.29" + wire $0\src_r2[0:0] + attribute \src "libresoc.v:139997.7-139997.24" + wire $1\all_rd_dly[0:0] + attribute \src "libresoc.v:140007.7-140007.26" + wire $1\alu_done_dly[0:0] + attribute \src "libresoc.v:140939.3-140947.6" + wire $1\alu_l_r_alu$next[0:0]$7477 + attribute \src "libresoc.v:140015.7-140015.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "libresoc.v:140779.3-140811.6" + wire width 12 $1\alu_mul0_mul_op__fn_unit$next[11:0]$7413 + attribute \src "libresoc.v:140036.14-140036.48" + wire width 12 $1\alu_mul0_mul_op__fn_unit[11:0] + attribute \src "libresoc.v:140779.3-140811.6" + wire width 64 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7414 + attribute \src "libresoc.v:140040.14-140040.68" + wire width 64 $1\alu_mul0_mul_op__imm_data__data[63:0] + attribute \src "libresoc.v:140779.3-140811.6" + wire $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7415 + attribute \src "libresoc.v:140044.7-140044.43" + wire $1\alu_mul0_mul_op__imm_data__ok[0:0] + attribute \src "libresoc.v:140779.3-140811.6" + wire width 32 $1\alu_mul0_mul_op__insn$next[31:0]$7416 + attribute \src "libresoc.v:140048.14-140048.43" + wire width 32 $1\alu_mul0_mul_op__insn[31:0] + attribute \src "libresoc.v:140779.3-140811.6" + wire width 7 $1\alu_mul0_mul_op__insn_type$next[6:0]$7417 + attribute \src "libresoc.v:140126.13-140126.47" + wire width 7 $1\alu_mul0_mul_op__insn_type[6:0] + attribute \src "libresoc.v:140779.3-140811.6" + wire $1\alu_mul0_mul_op__is_32bit$next[0:0]$7418 + attribute \src "libresoc.v:140130.7-140130.39" + wire $1\alu_mul0_mul_op__is_32bit[0:0] + attribute \src "libresoc.v:140779.3-140811.6" + wire $1\alu_mul0_mul_op__is_signed$next[0:0]$7419 + attribute \src "libresoc.v:140134.7-140134.40" + wire $1\alu_mul0_mul_op__is_signed[0:0] + attribute \src "libresoc.v:140779.3-140811.6" + wire $1\alu_mul0_mul_op__oe__oe$next[0:0]$7420 + attribute \src "libresoc.v:140138.7-140138.37" + wire $1\alu_mul0_mul_op__oe__oe[0:0] + attribute \src "libresoc.v:140779.3-140811.6" + wire $1\alu_mul0_mul_op__oe__ok$next[0:0]$7421 + attribute \src "libresoc.v:140142.7-140142.37" + wire $1\alu_mul0_mul_op__oe__ok[0:0] + attribute \src "libresoc.v:140779.3-140811.6" + wire $1\alu_mul0_mul_op__rc__ok$next[0:0]$7422 + attribute \src "libresoc.v:140146.7-140146.37" + wire $1\alu_mul0_mul_op__rc__ok[0:0] + attribute \src "libresoc.v:140779.3-140811.6" + wire $1\alu_mul0_mul_op__rc__rc$next[0:0]$7423 + attribute \src "libresoc.v:140150.7-140150.37" + wire $1\alu_mul0_mul_op__rc__rc[0:0] + attribute \src "libresoc.v:140779.3-140811.6" + wire $1\alu_mul0_mul_op__write_cr0$next[0:0]$7424 + attribute \src "libresoc.v:140154.7-140154.40" + wire $1\alu_mul0_mul_op__write_cr0[0:0] + attribute \src "libresoc.v:140930.3-140938.6" + wire $1\alui_l_r_alui$next[0:0]$7474 + attribute \src "libresoc.v:140184.7-140184.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "libresoc.v:140812.3-140833.6" + wire width 64 $1\data_r0__o$next[63:0]$7434 + attribute \src "libresoc.v:140218.14-140218.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "libresoc.v:140812.3-140833.6" + wire $1\data_r0__o_ok$next[0:0]$7435 + attribute \src "libresoc.v:140222.7-140222.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "libresoc.v:140834.3-140855.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$7442 + attribute \src "libresoc.v:140226.13-140226.33" + wire width 4 $1\data_r1__cr_a[3:0] + attribute \src "libresoc.v:140834.3-140855.6" + wire $1\data_r1__cr_a_ok$next[0:0]$7443 + attribute \src "libresoc.v:140230.7-140230.30" + wire $1\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:140856.3-140877.6" + wire width 2 $1\data_r2__xer_ov$next[1:0]$7450 + attribute \src "libresoc.v:140234.13-140234.35" + wire width 2 $1\data_r2__xer_ov[1:0] + attribute \src "libresoc.v:140856.3-140877.6" + wire $1\data_r2__xer_ov_ok$next[0:0]$7451 + attribute \src "libresoc.v:140238.7-140238.32" + wire $1\data_r2__xer_ov_ok[0:0] + attribute \src "libresoc.v:140878.3-140899.6" + wire $1\data_r3__xer_so$next[0:0]$7458 + attribute \src "libresoc.v:140242.7-140242.29" + wire $1\data_r3__xer_so[0:0] + attribute \src "libresoc.v:140878.3-140899.6" + wire $1\data_r3__xer_so_ok$next[0:0]$7459 + attribute \src "libresoc.v:140246.7-140246.32" + wire $1\data_r3__xer_so_ok[0:0] + attribute \src "libresoc.v:140948.3-140957.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "libresoc.v:140958.3-140967.6" + wire width 4 $1\dest2_o[3:0] + attribute \src "libresoc.v:140968.3-140977.6" + wire width 2 $1\dest3_o[1:0] + attribute \src "libresoc.v:140978.3-140987.6" + wire $1\dest4_o[0:0] + attribute \src "libresoc.v:140734.3-140742.6" + wire $1\opc_l_r_opc$next[0:0]$7387 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\enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_mul0_mul_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_mul0_mul_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \alu_mul0_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \alu_mul0_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \alu_mul0_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \alu_mul0_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \alu_mul0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_mul0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_mul0_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \alu_mul0_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \alu_mul0_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \alu_mul0_xer_so$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" + wire \alu_pulse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + wire width 4 \alu_pulsem + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \alui_l_s_alui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 32 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 26 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" 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"/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 23 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 4 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 25 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 27 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 29 \dest3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 31 \dest4_o + attribute \src "libresoc.v:139873.7-139873.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 22 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \opc_l_q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 3 \oper_i_alu_mul0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 4 \oper_i_alu_mul0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \oper_i_alu_mul0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 13 \oper_i_alu_mul0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + 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$not$libresoc.v:140481$7288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wrmask_o + connect \Y $not$libresoc.v:140481$7288_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:140484$7291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$23 + connect \Y $not$libresoc.v:140484$7291_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$libresoc.v:140490$7297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_mul0_n_ready_i + connect \Y $not$libresoc.v:140490$7297_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$libresoc.v:140501$7308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__rel_o + connect \Y $not$libresoc.v:140501$7308_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$libresoc.v:140521$7328 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_mul0_mul_op__imm_data__ok + connect \Y $not$libresoc.v:140521$7328_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$libresoc.v:140523$7330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rdmaskn_i + connect \Y $not$libresoc.v:140523$7330_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$libresoc.v:140489$7296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$32 + connect \B \$34 + connect \Y $or$libresoc.v:140489$7296_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$libresoc.v:140499$7306 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:140499$7306_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$libresoc.v:140500$7307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:140500$7307_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$libresoc.v:140502$7309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:140502$7309_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$libresoc.v:140503$7310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:140503$7310_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:140506$7313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$libresoc.v:140506$7313_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:140512$7319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$5 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:140512$7319_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:140518$7325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$7 + connect \Y $reduce_and$libresoc.v:140518$7325_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:140483$7290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \Y $reduce_or$libresoc.v:140483$7290_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:140487$7294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:140487$7294_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:140488$7295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:140488$7295_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:140511$7318 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_mul0_mul_op__imm_data__ok + connect \Y $ternary$libresoc.v:140511$7318_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:140513$7320 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_mul0_mul_op__imm_data__data + connect \S \alu_mul0_mul_op__imm_data__ok + connect \Y $ternary$libresoc.v:140513$7320_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:140514$7321 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $ternary$libresoc.v:140514$7321_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:140515$7322 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $ternary$libresoc.v:140515$7322_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:140516$7323 + parameter \WIDTH 1 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:140516$7323_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:140600.15-140606.4" + cell \alu_l$107 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:140607.12-140637.4" + cell \alu_mul0 \alu_mul0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \alu_mul0_cr_a + connect \cr_a_ok \cr_a_ok + connect \mul_op__fn_unit \alu_mul0_mul_op__fn_unit + connect \mul_op__imm_data__data \alu_mul0_mul_op__imm_data__data + connect \mul_op__imm_data__ok \alu_mul0_mul_op__imm_data__ok + connect \mul_op__insn \alu_mul0_mul_op__insn + connect \mul_op__insn_type \alu_mul0_mul_op__insn_type + connect \mul_op__is_32bit \alu_mul0_mul_op__is_32bit + connect \mul_op__is_signed \alu_mul0_mul_op__is_signed + connect \mul_op__oe__oe \alu_mul0_mul_op__oe__oe + connect \mul_op__oe__ok \alu_mul0_mul_op__oe__ok + connect \mul_op__rc__ok \alu_mul0_mul_op__rc__ok + connect \mul_op__rc__rc \alu_mul0_mul_op__rc__rc + connect \mul_op__write_cr0 \alu_mul0_mul_op__write_cr0 + connect \n_ready_i \alu_mul0_n_ready_i + connect \n_valid_o \alu_mul0_n_valid_o + connect \o \alu_mul0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_mul0_p_ready_o + connect \p_valid_i \alu_mul0_p_valid_i + connect \ra \alu_mul0_ra + connect \rb \alu_mul0_rb + connect \xer_ov \alu_mul0_xer_ov + connect \xer_ov_ok \xer_ov_ok + connect \xer_so \alu_mul0_xer_so + connect \xer_so$1 \alu_mul0_xer_so$1 + connect \xer_so_ok \xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:140638.16-140644.4" + cell \alui_l$106 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:140645.15-140651.4" + cell \opc_l$102 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:140652.15-140658.4" + cell \req_l$103 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:140659.15-140665.4" + cell \rok_l$105 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:140666.15-140671.4" + cell \rst_l$104 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:140672.15-140678.4" + cell \src_l$101 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "libresoc.v:139873.7-139873.20" + process $proc$libresoc.v:139873$7485 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:139997.7-139997.24" + process $proc$libresoc.v:139997$7486 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "libresoc.v:140007.7-140007.26" + process $proc$libresoc.v:140007$7487 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "libresoc.v:140015.7-140015.25" + process $proc$libresoc.v:140015$7488 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:140036.14-140036.48" + process $proc$libresoc.v:140036$7489 + assign { } { } + assign $1\alu_mul0_mul_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \alu_mul0_mul_op__fn_unit $1\alu_mul0_mul_op__fn_unit[11:0] + end + attribute \src "libresoc.v:140040.14-140040.68" + process $proc$libresoc.v:140040$7490 + assign { } { } + assign $1\alu_mul0_mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_mul0_mul_op__imm_data__data $1\alu_mul0_mul_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:140044.7-140044.43" + process $proc$libresoc.v:140044$7491 + assign { } { } + assign $1\alu_mul0_mul_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__imm_data__ok $1\alu_mul0_mul_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:140048.14-140048.43" + process $proc$libresoc.v:140048$7492 + assign { } { } + assign $1\alu_mul0_mul_op__insn[31:0] 0 + sync always + sync init + update \alu_mul0_mul_op__insn $1\alu_mul0_mul_op__insn[31:0] + end + attribute \src "libresoc.v:140126.13-140126.47" + process $proc$libresoc.v:140126$7493 + assign { } { } + assign $1\alu_mul0_mul_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_mul0_mul_op__insn_type $1\alu_mul0_mul_op__insn_type[6:0] + end + attribute \src "libresoc.v:140130.7-140130.39" + process $proc$libresoc.v:140130$7494 + assign { } { } + assign $1\alu_mul0_mul_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__is_32bit $1\alu_mul0_mul_op__is_32bit[0:0] + end + attribute \src "libresoc.v:140134.7-140134.40" + process $proc$libresoc.v:140134$7495 + assign { } { } + assign $1\alu_mul0_mul_op__is_signed[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__is_signed $1\alu_mul0_mul_op__is_signed[0:0] + end + attribute \src "libresoc.v:140138.7-140138.37" + process $proc$libresoc.v:140138$7496 + assign { } { } + assign $1\alu_mul0_mul_op__oe__oe[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__oe__oe $1\alu_mul0_mul_op__oe__oe[0:0] + end + attribute \src "libresoc.v:140142.7-140142.37" + process $proc$libresoc.v:140142$7497 + assign { } { } + assign $1\alu_mul0_mul_op__oe__ok[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__oe__ok $1\alu_mul0_mul_op__oe__ok[0:0] + end + attribute \src "libresoc.v:140146.7-140146.37" + process $proc$libresoc.v:140146$7498 + assign { } { } + assign $1\alu_mul0_mul_op__rc__ok[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__rc__ok $1\alu_mul0_mul_op__rc__ok[0:0] + end + attribute \src "libresoc.v:140150.7-140150.37" + process $proc$libresoc.v:140150$7499 + assign { } { } + assign $1\alu_mul0_mul_op__rc__rc[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__rc__rc $1\alu_mul0_mul_op__rc__rc[0:0] + end + attribute \src "libresoc.v:140154.7-140154.40" + process $proc$libresoc.v:140154$7500 + assign { } { } + assign $1\alu_mul0_mul_op__write_cr0[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__write_cr0 $1\alu_mul0_mul_op__write_cr0[0:0] + end + attribute \src "libresoc.v:140184.7-140184.27" + process $proc$libresoc.v:140184$7501 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:140218.14-140218.47" + process $proc$libresoc.v:140218$7502 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "libresoc.v:140222.7-140222.27" + process $proc$libresoc.v:140222$7503 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:140226.13-140226.33" + process $proc$libresoc.v:140226$7504 + assign { } { } + assign $1\data_r1__cr_a[3:0] 4'0000 + sync always + sync init + update \data_r1__cr_a $1\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:140230.7-140230.30" + process $proc$libresoc.v:140230$7505 + assign { } { } + assign $1\data_r1__cr_a_ok[0:0] 1'0 + sync always + sync init + update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:140234.13-140234.35" + process $proc$libresoc.v:140234$7506 + assign { } { } + assign $1\data_r2__xer_ov[1:0] 2'00 + sync always + sync init + update \data_r2__xer_ov $1\data_r2__xer_ov[1:0] + end + attribute \src "libresoc.v:140238.7-140238.32" + process $proc$libresoc.v:140238$7507 + assign { } { } + assign $1\data_r2__xer_ov_ok[0:0] 1'0 + sync always + sync init + update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0] + end + attribute \src "libresoc.v:140242.7-140242.29" + process $proc$libresoc.v:140242$7508 + assign { } { } + assign $1\data_r3__xer_so[0:0] 1'0 + sync always + sync init + update \data_r3__xer_so $1\data_r3__xer_so[0:0] + end + attribute \src "libresoc.v:140246.7-140246.32" + process $proc$libresoc.v:140246$7509 + assign { } { } + assign $1\data_r3__xer_so_ok[0:0] 1'0 + sync always + sync init + update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] + end + attribute \src "libresoc.v:140266.7-140266.25" + process $proc$libresoc.v:140266$7510 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:140270.7-140270.25" + process $proc$libresoc.v:140270$7511 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:140385.13-140385.30" + process $proc$libresoc.v:140385$7512 + assign { } { } + assign $1\prev_wr_go[3:0] 4'0000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[3:0] + end + attribute \src "libresoc.v:140393.13-140393.31" + process $proc$libresoc.v:140393$7513 + assign { } { } + assign $1\req_l_r_req[3:0] 4'1111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[3:0] + end + attribute \src "libresoc.v:140397.13-140397.31" + process $proc$libresoc.v:140397$7514 + assign { } { } + assign $1\req_l_s_req[3:0] 4'0000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[3:0] + end + attribute \src "libresoc.v:140409.7-140409.26" + process $proc$libresoc.v:140409$7515 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:140413.7-140413.26" + process $proc$libresoc.v:140413$7516 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:140417.7-140417.25" + process $proc$libresoc.v:140417$7517 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:140421.7-140421.25" + process $proc$libresoc.v:140421$7518 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:140435.13-140435.31" + process $proc$libresoc.v:140435$7519 + assign { } { } + assign $1\src_l_r_src[2:0] 3'111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[2:0] + end + attribute \src "libresoc.v:140439.13-140439.31" + process $proc$libresoc.v:140439$7520 + assign { } { } + assign $1\src_l_s_src[2:0] 3'000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[2:0] + end + attribute \src "libresoc.v:140445.14-140445.43" + process $proc$libresoc.v:140445$7521 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:140449.14-140449.43" + process $proc$libresoc.v:140449$7522 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:140453.7-140453.20" + process $proc$libresoc.v:140453$7523 + assign { } { } + assign $1\src_r2[0:0] 1'0 + sync always + sync init + update \src_r2 $1\src_r2[0:0] + end + attribute \src "libresoc.v:140524.3-140525.39" + process $proc$libresoc.v:140524$7331 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:140526.3-140527.43" + process $proc$libresoc.v:140526$7332 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:140528.3-140529.29" + process $proc$libresoc.v:140528$7333 + assign { } { } + assign $0\src_r2[0:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[0:0] + end + attribute \src "libresoc.v:140530.3-140531.29" + process $proc$libresoc.v:140530$7334 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:140532.3-140533.29" + process $proc$libresoc.v:140532$7335 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:140534.3-140535.47" + process $proc$libresoc.v:140534$7336 + assign { } { } + assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next + sync posedge \coresync_clk + update \data_r3__xer_so $0\data_r3__xer_so[0:0] + end + attribute \src "libresoc.v:140536.3-140537.53" + process $proc$libresoc.v:140536$7337 + assign { } { } + assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next + sync posedge \coresync_clk + update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] + end + attribute \src "libresoc.v:140538.3-140539.47" + process $proc$libresoc.v:140538$7338 + assign { } { } + assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next + sync posedge \coresync_clk + update \data_r2__xer_ov $0\data_r2__xer_ov[1:0] + end + attribute \src "libresoc.v:140540.3-140541.53" + process $proc$libresoc.v:140540$7339 + assign { } { } + assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next + sync posedge \coresync_clk + update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0] + end + attribute \src "libresoc.v:140542.3-140543.43" + process $proc$libresoc.v:140542$7340 + assign { } { } + assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next + sync posedge \coresync_clk + update \data_r1__cr_a $0\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:140544.3-140545.49" + process $proc$libresoc.v:140544$7341 + assign { } { } + assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next + sync posedge \coresync_clk + update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:140546.3-140547.37" + process $proc$libresoc.v:140546$7342 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "libresoc.v:140548.3-140549.43" + process $proc$libresoc.v:140548$7343 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:140550.3-140551.69" + process $proc$libresoc.v:140550$7344 + assign { } { } + assign $0\alu_mul0_mul_op__insn_type[6:0] \alu_mul0_mul_op__insn_type$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__insn_type $0\alu_mul0_mul_op__insn_type[6:0] + end + attribute \src "libresoc.v:140552.3-140553.65" + process $proc$libresoc.v:140552$7345 + assign { } { } + assign $0\alu_mul0_mul_op__fn_unit[11:0] \alu_mul0_mul_op__fn_unit$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__fn_unit $0\alu_mul0_mul_op__fn_unit[11:0] + end + attribute \src "libresoc.v:140554.3-140555.79" + process $proc$libresoc.v:140554$7346 + assign { } { } + assign $0\alu_mul0_mul_op__imm_data__data[63:0] \alu_mul0_mul_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__imm_data__data $0\alu_mul0_mul_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:140556.3-140557.75" + process $proc$libresoc.v:140556$7347 + assign { } { } + assign $0\alu_mul0_mul_op__imm_data__ok[0:0] \alu_mul0_mul_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__imm_data__ok $0\alu_mul0_mul_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:140558.3-140559.63" + process $proc$libresoc.v:140558$7348 + assign { } { } + assign $0\alu_mul0_mul_op__rc__rc[0:0] \alu_mul0_mul_op__rc__rc$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__rc__rc $0\alu_mul0_mul_op__rc__rc[0:0] + end + attribute \src "libresoc.v:140560.3-140561.63" + process $proc$libresoc.v:140560$7349 + assign { } { } + assign $0\alu_mul0_mul_op__rc__ok[0:0] \alu_mul0_mul_op__rc__ok$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__rc__ok $0\alu_mul0_mul_op__rc__ok[0:0] + end + attribute \src "libresoc.v:140562.3-140563.63" + process $proc$libresoc.v:140562$7350 + assign { } { } + assign $0\alu_mul0_mul_op__oe__oe[0:0] \alu_mul0_mul_op__oe__oe$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__oe__oe $0\alu_mul0_mul_op__oe__oe[0:0] + end + attribute \src "libresoc.v:140564.3-140565.63" + process $proc$libresoc.v:140564$7351 + assign { } { } + assign $0\alu_mul0_mul_op__oe__ok[0:0] \alu_mul0_mul_op__oe__ok$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__oe__ok $0\alu_mul0_mul_op__oe__ok[0:0] + end + attribute \src "libresoc.v:140566.3-140567.69" + process $proc$libresoc.v:140566$7352 + assign { } { } + assign $0\alu_mul0_mul_op__write_cr0[0:0] \alu_mul0_mul_op__write_cr0$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__write_cr0 $0\alu_mul0_mul_op__write_cr0[0:0] + end + attribute \src "libresoc.v:140568.3-140569.67" + process $proc$libresoc.v:140568$7353 + assign { } { } + assign $0\alu_mul0_mul_op__is_32bit[0:0] \alu_mul0_mul_op__is_32bit$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__is_32bit $0\alu_mul0_mul_op__is_32bit[0:0] + end + attribute \src "libresoc.v:140570.3-140571.69" + process $proc$libresoc.v:140570$7354 + assign { } { } + assign $0\alu_mul0_mul_op__is_signed[0:0] \alu_mul0_mul_op__is_signed$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__is_signed $0\alu_mul0_mul_op__is_signed[0:0] + end + attribute \src "libresoc.v:140572.3-140573.59" + process $proc$libresoc.v:140572$7355 + assign { } { } + assign $0\alu_mul0_mul_op__insn[31:0] \alu_mul0_mul_op__insn$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__insn $0\alu_mul0_mul_op__insn[31:0] + end + attribute \src "libresoc.v:140574.3-140575.39" + process $proc$libresoc.v:140574$7356 + assign { } { } + assign $0\req_l_r_req[3:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[3:0] + end + attribute \src "libresoc.v:140576.3-140577.39" + process $proc$libresoc.v:140576$7357 + assign { } { } + assign $0\req_l_s_req[3:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[3:0] + end + attribute \src "libresoc.v:140578.3-140579.39" + process $proc$libresoc.v:140578$7358 + assign { } { } + assign $0\src_l_r_src[2:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[2:0] + end + attribute \src "libresoc.v:140580.3-140581.39" + process $proc$libresoc.v:140580$7359 + assign { } { } + assign $0\src_l_s_src[2:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[2:0] + end + attribute \src "libresoc.v:140582.3-140583.39" + process $proc$libresoc.v:140582$7360 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:140584.3-140585.39" + process $proc$libresoc.v:140584$7361 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:140586.3-140587.39" + process $proc$libresoc.v:140586$7362 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:140588.3-140589.39" + process $proc$libresoc.v:140588$7363 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:140590.3-140591.41" + process $proc$libresoc.v:140590$7364 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:140592.3-140593.41" + process $proc$libresoc.v:140592$7365 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:140594.3-140595.37" + process $proc$libresoc.v:140594$7366 + assign { } { } + assign $0\prev_wr_go[3:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[3:0] + end + attribute \src "libresoc.v:140596.3-140597.40" + process $proc$libresoc.v:140596$7367 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_mul0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "libresoc.v:140598.3-140599.25" + process $proc$libresoc.v:140598$7368 + assign { } { } + assign $0\all_rd_dly[0:0] \$10 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "libresoc.v:140679.3-140688.6" + process $proc$libresoc.v:140679$7369 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:140680.5-140680.29" + switch \initial + attribute \src "libresoc.v:140680.9-140680.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$54 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$46 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "libresoc.v:140689.3-140697.6" + process $proc$libresoc.v:140689$7370 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$7371 $1\rok_l_s_rdok$next[0:0]$7372 + attribute \src "libresoc.v:140690.5-140690.29" + switch \initial + attribute \src "libresoc.v:140690.9-140690.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$7372 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$7372 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$7371 + end + attribute \src "libresoc.v:140698.3-140706.6" + process $proc$libresoc.v:140698$7373 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$7374 $1\rok_l_r_rdok$next[0:0]$7375 + attribute \src "libresoc.v:140699.5-140699.29" + switch \initial + attribute \src "libresoc.v:140699.9-140699.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$7375 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$7375 \$64 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$7374 + end + attribute \src "libresoc.v:140707.3-140715.6" + process $proc$libresoc.v:140707$7376 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$7377 $1\rst_l_s_rst$next[0:0]$7378 + attribute \src "libresoc.v:140708.5-140708.29" + switch \initial + attribute \src "libresoc.v:140708.9-140708.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$7378 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$7378 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$7377 + end + attribute \src "libresoc.v:140716.3-140724.6" + process $proc$libresoc.v:140716$7379 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$7380 $1\rst_l_r_rst$next[0:0]$7381 + attribute \src "libresoc.v:140717.5-140717.29" + switch \initial + attribute \src "libresoc.v:140717.9-140717.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$7381 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$7381 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$7380 + end + attribute \src "libresoc.v:140725.3-140733.6" + process $proc$libresoc.v:140725$7382 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$7383 $1\opc_l_s_opc$next[0:0]$7384 + attribute \src "libresoc.v:140726.5-140726.29" + switch \initial + attribute \src "libresoc.v:140726.9-140726.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$7384 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$7384 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$7383 + end + attribute \src "libresoc.v:140734.3-140742.6" + process $proc$libresoc.v:140734$7385 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$7386 $1\opc_l_r_opc$next[0:0]$7387 + attribute \src "libresoc.v:140735.5-140735.29" + switch \initial + attribute \src "libresoc.v:140735.9-140735.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$7387 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$7387 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$7386 + end + attribute \src "libresoc.v:140743.3-140751.6" + process $proc$libresoc.v:140743$7388 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[2:0]$7389 $1\src_l_s_src$next[2:0]$7390 + attribute \src "libresoc.v:140744.5-140744.29" + switch \initial + attribute \src "libresoc.v:140744.9-140744.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[2:0]$7390 3'000 + case + assign $1\src_l_s_src$next[2:0]$7390 { \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$7389 + end + attribute \src "libresoc.v:140752.3-140760.6" + process $proc$libresoc.v:140752$7391 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[2:0]$7392 $1\src_l_r_src$next[2:0]$7393 + attribute \src "libresoc.v:140753.5-140753.29" + switch \initial + attribute \src "libresoc.v:140753.9-140753.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[2:0]$7393 3'111 + case + assign $1\src_l_r_src$next[2:0]$7393 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$7392 + end + attribute \src "libresoc.v:140761.3-140769.6" + process $proc$libresoc.v:140761$7394 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[3:0]$7395 $1\req_l_s_req$next[3:0]$7396 + attribute \src "libresoc.v:140762.5-140762.29" + switch \initial + attribute \src "libresoc.v:140762.9-140762.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[3:0]$7396 4'0000 + case + assign $1\req_l_s_req$next[3:0]$7396 \$66 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[3:0]$7395 + end + attribute \src "libresoc.v:140770.3-140778.6" + process $proc$libresoc.v:140770$7397 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[3:0]$7398 $1\req_l_r_req$next[3:0]$7399 + attribute \src "libresoc.v:140771.5-140771.29" + switch \initial + attribute \src "libresoc.v:140771.9-140771.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[3:0]$7399 4'1111 + case + assign $1\req_l_r_req$next[3:0]$7399 \$68 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[3:0]$7398 + end + attribute \src "libresoc.v:140779.3-140811.6" + process $proc$libresoc.v:140779$7400 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_mul0_mul_op__fn_unit$next[11:0]$7401 $1\alu_mul0_mul_op__fn_unit$next[11:0]$7413 + assign { } { } + assign { } { } + assign $0\alu_mul0_mul_op__insn$next[31:0]$7404 $1\alu_mul0_mul_op__insn$next[31:0]$7416 + assign $0\alu_mul0_mul_op__insn_type$next[6:0]$7405 $1\alu_mul0_mul_op__insn_type$next[6:0]$7417 + assign $0\alu_mul0_mul_op__is_32bit$next[0:0]$7406 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7418 + assign $0\alu_mul0_mul_op__is_signed$next[0:0]$7407 $1\alu_mul0_mul_op__is_signed$next[0:0]$7419 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_mul0_mul_op__write_cr0$next[0:0]$7412 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7424 + assign $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7402 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7425 + assign $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7403 $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7426 + assign $0\alu_mul0_mul_op__oe__oe$next[0:0]$7408 $2\alu_mul0_mul_op__oe__oe$next[0:0]$7427 + assign $0\alu_mul0_mul_op__oe__ok$next[0:0]$7409 $2\alu_mul0_mul_op__oe__ok$next[0:0]$7428 + assign $0\alu_mul0_mul_op__rc__ok$next[0:0]$7410 $2\alu_mul0_mul_op__rc__ok$next[0:0]$7429 + assign $0\alu_mul0_mul_op__rc__rc$next[0:0]$7411 $2\alu_mul0_mul_op__rc__rc$next[0:0]$7430 + attribute \src "libresoc.v:140780.5-140780.29" + switch \initial + attribute \src "libresoc.v:140780.9-140780.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_mul0_mul_op__insn$next[31:0]$7416 $1\alu_mul0_mul_op__is_signed$next[0:0]$7419 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7418 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7424 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7421 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7420 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7422 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7423 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7415 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7414 $1\alu_mul0_mul_op__fn_unit$next[11:0]$7413 $1\alu_mul0_mul_op__insn_type$next[6:0]$7417 } { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type } + case + assign $1\alu_mul0_mul_op__fn_unit$next[11:0]$7413 \alu_mul0_mul_op__fn_unit + assign $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7414 \alu_mul0_mul_op__imm_data__data + assign $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7415 \alu_mul0_mul_op__imm_data__ok + assign $1\alu_mul0_mul_op__insn$next[31:0]$7416 \alu_mul0_mul_op__insn + assign $1\alu_mul0_mul_op__insn_type$next[6:0]$7417 \alu_mul0_mul_op__insn_type + assign $1\alu_mul0_mul_op__is_32bit$next[0:0]$7418 \alu_mul0_mul_op__is_32bit + assign $1\alu_mul0_mul_op__is_signed$next[0:0]$7419 \alu_mul0_mul_op__is_signed + assign $1\alu_mul0_mul_op__oe__oe$next[0:0]$7420 \alu_mul0_mul_op__oe__oe + assign $1\alu_mul0_mul_op__oe__ok$next[0:0]$7421 \alu_mul0_mul_op__oe__ok + assign $1\alu_mul0_mul_op__rc__ok$next[0:0]$7422 \alu_mul0_mul_op__rc__ok + assign $1\alu_mul0_mul_op__rc__rc$next[0:0]$7423 \alu_mul0_mul_op__rc__rc + assign $1\alu_mul0_mul_op__write_cr0$next[0:0]$7424 \alu_mul0_mul_op__write_cr0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7425 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7426 1'0 + assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7430 1'0 + assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7429 1'0 + assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7427 1'0 + assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7428 1'0 + case + assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7425 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7414 + assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7426 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7415 + assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7427 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7420 + assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7428 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7421 + assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7429 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7422 + assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7430 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7423 + end + sync always + update \alu_mul0_mul_op__fn_unit$next $0\alu_mul0_mul_op__fn_unit$next[11:0]$7401 + update \alu_mul0_mul_op__imm_data__data$next $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7402 + update \alu_mul0_mul_op__imm_data__ok$next $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7403 + update \alu_mul0_mul_op__insn$next $0\alu_mul0_mul_op__insn$next[31:0]$7404 + update \alu_mul0_mul_op__insn_type$next $0\alu_mul0_mul_op__insn_type$next[6:0]$7405 + update \alu_mul0_mul_op__is_32bit$next $0\alu_mul0_mul_op__is_32bit$next[0:0]$7406 + update \alu_mul0_mul_op__is_signed$next $0\alu_mul0_mul_op__is_signed$next[0:0]$7407 + update \alu_mul0_mul_op__oe__oe$next $0\alu_mul0_mul_op__oe__oe$next[0:0]$7408 + update \alu_mul0_mul_op__oe__ok$next $0\alu_mul0_mul_op__oe__ok$next[0:0]$7409 + update \alu_mul0_mul_op__rc__ok$next $0\alu_mul0_mul_op__rc__ok$next[0:0]$7410 + update \alu_mul0_mul_op__rc__rc$next $0\alu_mul0_mul_op__rc__rc$next[0:0]$7411 + update \alu_mul0_mul_op__write_cr0$next $0\alu_mul0_mul_op__write_cr0$next[0:0]$7412 + end + attribute \src "libresoc.v:140812.3-140833.6" + process $proc$libresoc.v:140812$7431 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$7432 $2\data_r0__o$next[63:0]$7436 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$7433 $3\data_r0__o_ok$next[0:0]$7438 + attribute \src "libresoc.v:140813.5-140813.29" + switch \initial + attribute \src "libresoc.v:140813.9-140813.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$7435 $1\data_r0__o$next[63:0]$7434 } { \o_ok \alu_mul0_o } + case + assign $1\data_r0__o$next[63:0]$7434 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$7435 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$7437 $2\data_r0__o$next[63:0]$7436 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$7436 $1\data_r0__o$next[63:0]$7434 + assign $2\data_r0__o_ok$next[0:0]$7437 $1\data_r0__o_ok$next[0:0]$7435 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$7438 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$7438 $2\data_r0__o_ok$next[0:0]$7437 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$7432 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$7433 + end + attribute \src "libresoc.v:140834.3-140855.6" + process $proc$libresoc.v:140834$7439 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__cr_a$next[3:0]$7440 $2\data_r1__cr_a$next[3:0]$7444 + assign { } { } + assign $0\data_r1__cr_a_ok$next[0:0]$7441 $3\data_r1__cr_a_ok$next[0:0]$7446 + attribute \src "libresoc.v:140835.5-140835.29" + switch \initial + attribute \src "libresoc.v:140835.9-140835.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__cr_a_ok$next[0:0]$7443 $1\data_r1__cr_a$next[3:0]$7442 } { \cr_a_ok \alu_mul0_cr_a } + case + assign $1\data_r1__cr_a$next[3:0]$7442 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$7443 \data_r1__cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__cr_a_ok$next[0:0]$7445 $2\data_r1__cr_a$next[3:0]$7444 } 5'00000 + case + assign $2\data_r1__cr_a$next[3:0]$7444 $1\data_r1__cr_a$next[3:0]$7442 + assign $2\data_r1__cr_a_ok$next[0:0]$7445 $1\data_r1__cr_a_ok$next[0:0]$7443 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__cr_a_ok$next[0:0]$7446 1'0 + case + assign $3\data_r1__cr_a_ok$next[0:0]$7446 $2\data_r1__cr_a_ok$next[0:0]$7445 + end + sync always + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$7440 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$7441 + end + attribute \src "libresoc.v:140856.3-140877.6" + process $proc$libresoc.v:140856$7447 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__xer_ov$next[1:0]$7448 $2\data_r2__xer_ov$next[1:0]$7452 + assign { } { } + assign $0\data_r2__xer_ov_ok$next[0:0]$7449 $3\data_r2__xer_ov_ok$next[0:0]$7454 + attribute \src "libresoc.v:140857.5-140857.29" + switch \initial + attribute \src "libresoc.v:140857.9-140857.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__xer_ov_ok$next[0:0]$7451 $1\data_r2__xer_ov$next[1:0]$7450 } { \xer_ov_ok \alu_mul0_xer_ov } + case + assign $1\data_r2__xer_ov$next[1:0]$7450 \data_r2__xer_ov + assign $1\data_r2__xer_ov_ok$next[0:0]$7451 \data_r2__xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__xer_ov_ok$next[0:0]$7453 $2\data_r2__xer_ov$next[1:0]$7452 } 3'000 + case + assign $2\data_r2__xer_ov$next[1:0]$7452 $1\data_r2__xer_ov$next[1:0]$7450 + assign $2\data_r2__xer_ov_ok$next[0:0]$7453 $1\data_r2__xer_ov_ok$next[0:0]$7451 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__xer_ov_ok$next[0:0]$7454 1'0 + case + assign $3\data_r2__xer_ov_ok$next[0:0]$7454 $2\data_r2__xer_ov_ok$next[0:0]$7453 + end + sync always + update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$7448 + update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$7449 + end + attribute \src "libresoc.v:140878.3-140899.6" + process $proc$libresoc.v:140878$7455 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r3__xer_so$next[0:0]$7456 $2\data_r3__xer_so$next[0:0]$7460 + assign { } { } + assign $0\data_r3__xer_so_ok$next[0:0]$7457 $3\data_r3__xer_so_ok$next[0:0]$7462 + attribute \src "libresoc.v:140879.5-140879.29" + switch \initial + attribute \src "libresoc.v:140879.9-140879.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r3__xer_so_ok$next[0:0]$7459 $1\data_r3__xer_so$next[0:0]$7458 } { \xer_so_ok \alu_mul0_xer_so } + case + assign $1\data_r3__xer_so$next[0:0]$7458 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$7459 \data_r3__xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r3__xer_so_ok$next[0:0]$7461 $2\data_r3__xer_so$next[0:0]$7460 } 2'00 + case + assign $2\data_r3__xer_so$next[0:0]$7460 $1\data_r3__xer_so$next[0:0]$7458 + assign $2\data_r3__xer_so_ok$next[0:0]$7461 $1\data_r3__xer_so_ok$next[0:0]$7459 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r3__xer_so_ok$next[0:0]$7462 1'0 + case + assign $3\data_r3__xer_so_ok$next[0:0]$7462 $2\data_r3__xer_so_ok$next[0:0]$7461 + end + sync always + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$7456 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$7457 + end + attribute \src "libresoc.v:140900.3-140909.6" + process $proc$libresoc.v:140900$7463 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$7464 $1\src_r0$next[63:0]$7465 + attribute \src "libresoc.v:140901.5-140901.29" + switch \initial + attribute \src "libresoc.v:140901.9-140901.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$7465 \src1_i + case + assign $1\src_r0$next[63:0]$7465 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$7464 + end + attribute \src "libresoc.v:140910.3-140919.6" + process $proc$libresoc.v:140910$7466 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$7467 $1\src_r1$next[63:0]$7468 + attribute \src "libresoc.v:140911.5-140911.29" + switch \initial + attribute \src "libresoc.v:140911.9-140911.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_sel + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$7468 \src_or_imm + case + assign $1\src_r1$next[63:0]$7468 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$7467 + end + attribute \src "libresoc.v:140920.3-140929.6" + process $proc$libresoc.v:140920$7469 + assign { } { } + assign { } { } + assign $0\src_r2$next[0:0]$7470 $1\src_r2$next[0:0]$7471 + attribute \src "libresoc.v:140921.5-140921.29" + switch \initial + attribute \src "libresoc.v:140921.9-140921.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[0:0]$7471 \src3_i + case + assign $1\src_r2$next[0:0]$7471 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[0:0]$7470 + end + attribute \src "libresoc.v:140930.3-140938.6" + process $proc$libresoc.v:140930$7472 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$7473 $1\alui_l_r_alui$next[0:0]$7474 + attribute \src "libresoc.v:140931.5-140931.29" + switch \initial + attribute \src "libresoc.v:140931.9-140931.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$7474 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$7474 \$88 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$7473 + end + attribute \src "libresoc.v:140939.3-140947.6" + process $proc$libresoc.v:140939$7475 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$7476 $1\alu_l_r_alu$next[0:0]$7477 + attribute \src "libresoc.v:140940.5-140940.29" + switch \initial + attribute \src "libresoc.v:140940.9-140940.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$7477 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$7477 \$90 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$7476 + end + attribute \src "libresoc.v:140948.3-140957.6" + process $proc$libresoc.v:140948$7478 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:140949.5-140949.29" + switch \initial + attribute \src "libresoc.v:140949.9-140949.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$114 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__o + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "libresoc.v:140958.3-140967.6" + process $proc$libresoc.v:140958$7479 + assign { } { } + assign { } { } + assign $0\dest2_o[3:0] $1\dest2_o[3:0] + attribute \src "libresoc.v:140959.5-140959.29" + switch \initial + attribute \src "libresoc.v:140959.9-140959.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$116 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[3:0] \data_r1__cr_a + case + assign $1\dest2_o[3:0] 4'0000 + end + sync always + update \dest2_o $0\dest2_o[3:0] + end + attribute \src "libresoc.v:140968.3-140977.6" + process $proc$libresoc.v:140968$7480 + assign { } { } + assign { } { } + assign $0\dest3_o[1:0] $1\dest3_o[1:0] + attribute \src "libresoc.v:140969.5-140969.29" + switch \initial + attribute \src "libresoc.v:140969.9-140969.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$118 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest3_o[1:0] \data_r2__xer_ov + case + assign $1\dest3_o[1:0] 2'00 + end + sync always + update \dest3_o $0\dest3_o[1:0] + end + attribute \src "libresoc.v:140978.3-140987.6" + process $proc$libresoc.v:140978$7481 + assign { } { } + assign { } { } + assign $0\dest4_o[0:0] $1\dest4_o[0:0] + attribute \src "libresoc.v:140979.5-140979.29" + switch \initial + attribute \src "libresoc.v:140979.9-140979.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$120 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest4_o[0:0] \data_r3__xer_so + case + assign $1\dest4_o[0:0] 1'0 + end + sync always + update \dest4_o $0\dest4_o[0:0] + end + attribute \src "libresoc.v:140988.3-140996.6" + process $proc$libresoc.v:140988$7482 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[3:0]$7483 $1\prev_wr_go$next[3:0]$7484 + attribute \src "libresoc.v:140989.5-140989.29" + switch \initial + attribute \src "libresoc.v:140989.9-140989.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[3:0]$7484 4'0000 + case + assign $1\prev_wr_go$next[3:0]$7484 \$20 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[3:0]$7483 + end + connect \$100 $and$libresoc.v:140464$7271_Y + connect \$102 $and$libresoc.v:140465$7272_Y + connect \$104 $and$libresoc.v:140466$7273_Y + connect \$106 $and$libresoc.v:140467$7274_Y + connect \$108 $and$libresoc.v:140468$7275_Y + connect \$10 $and$libresoc.v:140469$7276_Y + connect \$110 $and$libresoc.v:140470$7277_Y + connect \$112 $and$libresoc.v:140471$7278_Y + connect \$114 $and$libresoc.v:140472$7279_Y + connect \$116 $and$libresoc.v:140473$7280_Y + connect \$118 $and$libresoc.v:140474$7281_Y + connect \$120 $and$libresoc.v:140475$7282_Y + connect \$12 $not$libresoc.v:140476$7283_Y + connect \$14 $and$libresoc.v:140477$7284_Y + connect \$16 $not$libresoc.v:140478$7285_Y + connect \$18 $and$libresoc.v:140479$7286_Y + connect \$20 $and$libresoc.v:140480$7287_Y + connect \$24 $not$libresoc.v:140481$7288_Y + connect \$26 $and$libresoc.v:140482$7289_Y + connect \$23 $reduce_or$libresoc.v:140483$7290_Y + connect \$22 $not$libresoc.v:140484$7291_Y + connect \$2 $and$libresoc.v:140485$7292_Y + connect \$30 $and$libresoc.v:140486$7293_Y + connect \$32 $reduce_or$libresoc.v:140487$7294_Y + connect \$34 $reduce_or$libresoc.v:140488$7295_Y + connect \$36 $or$libresoc.v:140489$7296_Y + connect \$38 $not$libresoc.v:140490$7297_Y + connect \$40 $and$libresoc.v:140491$7298_Y + connect \$42 $and$libresoc.v:140492$7299_Y + connect \$44 $eq$libresoc.v:140493$7300_Y + connect \$46 $and$libresoc.v:140494$7301_Y + connect \$48 $eq$libresoc.v:140495$7302_Y + connect \$50 $and$libresoc.v:140496$7303_Y + connect \$52 $and$libresoc.v:140497$7304_Y + connect \$54 $and$libresoc.v:140498$7305_Y + connect \$56 $or$libresoc.v:140499$7306_Y + connect \$58 $or$libresoc.v:140500$7307_Y + connect \$5 $not$libresoc.v:140501$7308_Y + connect \$60 $or$libresoc.v:140502$7309_Y + connect \$62 $or$libresoc.v:140503$7310_Y + connect \$64 $and$libresoc.v:140504$7311_Y + connect \$66 $and$libresoc.v:140505$7312_Y + connect \$68 $or$libresoc.v:140506$7313_Y + connect \$70 $and$libresoc.v:140507$7314_Y + connect \$72 $and$libresoc.v:140508$7315_Y + connect \$74 $and$libresoc.v:140509$7316_Y + connect \$76 $and$libresoc.v:140510$7317_Y + connect \$78 $ternary$libresoc.v:140511$7318_Y + connect \$7 $or$libresoc.v:140512$7319_Y + connect \$80 $ternary$libresoc.v:140513$7320_Y + connect \$82 $ternary$libresoc.v:140514$7321_Y + connect \$84 $ternary$libresoc.v:140515$7322_Y + connect \$86 $ternary$libresoc.v:140516$7323_Y + connect \$88 $and$libresoc.v:140517$7324_Y + connect \$4 $reduce_and$libresoc.v:140518$7325_Y + connect \$90 $and$libresoc.v:140519$7326_Y + connect \$92 $and$libresoc.v:140520$7327_Y + connect \$94 $not$libresoc.v:140521$7328_Y + connect \$96 $and$libresoc.v:140522$7329_Y + connect \$98 $not$libresoc.v:140523$7330_Y + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \cu_wr__rel_o \$112 + connect \cu_rd__rel_o \$100 + connect \cu_busy_o \opc_l_q_opc + connect \alu_l_s_alu \all_rd_pulse + connect \alu_mul0_n_ready_i \alu_l_q_alu + connect \alui_l_s_alui \all_rd_pulse + connect \alu_mul0_p_valid_i \alui_l_q_alui + connect \alu_mul0_xer_so$1 \$86 + connect \alu_mul0_rb \$84 + connect \alu_mul0_ra \$82 + connect \src_or_imm \$80 + connect \src_sel \$78 + connect \cu_wrmask_o { \$76 \$74 \$72 \$70 } + connect \reset_r \$62 + connect \reset_w \$60 + connect \rst_r \$58 + connect \reset \$56 + connect \wr_any \$36 + connect \cu_done_o \$30 + connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse } + connect \alu_pulse \alu_done_rise + connect \alu_done_rise \$18 + connect \alu_done_dly$next \alu_done + connect \alu_done \alu_mul0_n_valid_o + connect \all_rd_pulse \all_rd_rise + connect \all_rd_rise \$14 + connect \all_rd_dly$next \all_rd + connect \all_rd \$10 +end +attribute \src "libresoc.v:141031.1-141358.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.mul1" +attribute \generator "nMigen" +module \mul1 + attribute \src "libresoc.v:141325.18-141325.116" + wire $and$libresoc.v:141325$7525_Y + attribute \src "libresoc.v:141327.18-141327.116" + wire $and$libresoc.v:141327$7527_Y + attribute \src "libresoc.v:141328.18-141328.117" + wire $and$libresoc.v:141328$7528_Y + attribute \src "libresoc.v:141329.18-141329.117" + wire $and$libresoc.v:141329$7529_Y + attribute \src "libresoc.v:141332.18-141332.95" + wire width 65 $extend$libresoc.v:141332$7532_Y + attribute \src "libresoc.v:141333.18-141333.91" + wire width 65 $extend$libresoc.v:141333$7534_Y + attribute \src "libresoc.v:141335.18-141335.95" + wire width 65 $extend$libresoc.v:141335$7537_Y + attribute \src "libresoc.v:141336.18-141336.91" + wire width 65 $extend$libresoc.v:141336$7539_Y + attribute \src "libresoc.v:141332.18-141332.95" + wire width 65 $neg$libresoc.v:141332$7533_Y + attribute \src "libresoc.v:141335.18-141335.95" + wire width 65 $neg$libresoc.v:141335$7538_Y + attribute \src "libresoc.v:141333.18-141333.91" + wire width 65 $pos$libresoc.v:141333$7535_Y + attribute \src "libresoc.v:141336.18-141336.91" + wire width 65 $pos$libresoc.v:141336$7540_Y + attribute \src "libresoc.v:141324.18-141324.125" + wire $ternary$libresoc.v:141324$7524_Y + attribute \src "libresoc.v:141326.18-141326.125" + wire $ternary$libresoc.v:141326$7526_Y + attribute \src "libresoc.v:141334.18-141334.112" + wire width 65 $ternary$libresoc.v:141334$7536_Y + attribute \src "libresoc.v:141337.18-141337.112" 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attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute 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"OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 17 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 23 \mul_op__oe__oe$8 + attribute \src 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connect \Y $neg$libresoc.v:141332$7533_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" + cell $neg $neg$libresoc.v:141335$7538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:141335$7537_Y + connect \Y $neg$libresoc.v:141335$7538_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:141333$7535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:141333$7534_Y + connect \Y $pos$libresoc.v:141333$7535_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:141336$7540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:141336$7539_Y + connect \Y $pos$libresoc.v:141336$7540_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" + cell $mux $ternary$libresoc.v:141324$7524 + parameter \WIDTH 1 + connect \A \ra [63] + connect \B \ra [31] + connect \S \mul_op__is_32bit + connect \Y $ternary$libresoc.v:141324$7524_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" + cell $mux $ternary$libresoc.v:141326$7526 + parameter \WIDTH 1 + connect \A \rb [63] + connect \B \rb [31] + connect \S \mul_op__is_32bit + connect \Y $ternary$libresoc.v:141326$7526_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" + cell $mux $ternary$libresoc.v:141334$7536 + parameter \WIDTH 65 + connect \A \$36 + connect \B \$34 + connect \S \sign_a + connect \Y $ternary$libresoc.v:141334$7536_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" + cell $mux $ternary$libresoc.v:141337$7541 + parameter \WIDTH 65 + connect \A \$43 + connect \B \$41 + connect \S \sign_b + connect \Y $ternary$libresoc.v:141337$7541_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" + cell $mux $ternary$libresoc.v:141338$7542 + parameter \WIDTH 32 + connect \A \abs_a [63:32] + connect \B 0 + connect \S \is_32bit + connect \Y $ternary$libresoc.v:141338$7542_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" + cell $mux $ternary$libresoc.v:141339$7543 + parameter \WIDTH 32 + connect \A \abs_b [63:32] + connect \B 0 + connect \S \is_32bit + connect \Y $ternary$libresoc.v:141339$7543_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44" + cell $xor $xor$libresoc.v:141330$7530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sign_a + connect \B \sign_b + connect \Y $xor$libresoc.v:141330$7530_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45" + cell $xor $xor$libresoc.v:141331$7531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sign32_a + connect \B \sign32_b + connect \Y $xor$libresoc.v:141331$7531_Y + end + connect \$17 $ternary$libresoc.v:141324$7524_Y + connect \$19 $and$libresoc.v:141325$7525_Y + connect \$21 $ternary$libresoc.v:141326$7526_Y + connect \$23 $and$libresoc.v:141327$7527_Y + connect \$25 $and$libresoc.v:141328$7528_Y + connect \$27 $and$libresoc.v:141329$7529_Y + connect \$29 $xor$libresoc.v:141330$7530_Y + connect \$31 $xor$libresoc.v:141331$7531_Y + connect \$34 $neg$libresoc.v:141332$7533_Y + connect \$36 $pos$libresoc.v:141333$7535_Y + connect \$38 $ternary$libresoc.v:141334$7536_Y + connect \$41 $neg$libresoc.v:141335$7538_Y + connect \$43 $pos$libresoc.v:141336$7540_Y + connect \$45 $ternary$libresoc.v:141337$7541_Y + connect \$47 $ternary$libresoc.v:141338$7542_Y + connect \$49 $ternary$libresoc.v:141339$7543_Y + connect \$33 \$38 + connect \$40 \$45 + connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$16 \xer_so + connect \rb$15 [63:32] \$49 + connect \rb$15 [31:0] \abs_b [31:0] + connect \ra$14 [63:32] \$47 + connect \ra$14 [31:0] \abs_a [31:0] + connect \abs_b \$45 [63:0] + connect \abs_a \$38 [63:0] + connect \neg_res32 \$31 + connect \neg_res \$29 + connect \sign32_b \$27 + connect \sign32_a \$25 + connect \sign_b \$23 + connect \sign_a \$19 + connect \is_32bit \mul_op__is_32bit +end +attribute \src "libresoc.v:141362.1-141619.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.mul2" +attribute \generator "nMigen" +module \mul2 + attribute \src "libresoc.v:141612.18-141612.98" + wire width 129 $extend$libresoc.v:141612$7545_Y + attribute \src "libresoc.v:141611.18-141611.99" + wire width 128 $mul$libresoc.v:141611$7544_Y + attribute \src "libresoc.v:141612.18-141612.98" + wire width 129 $pos$libresoc.v:141612$7546_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" + wire width 129 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" + wire width 128 \$18 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 20 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 21 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 22 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 12 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 30 \mul_op__insn$13 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 19 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 25 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 24 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 23 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 35 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 18 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire input 16 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire output 33 \neg_res$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire input 17 \neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire output 34 \neg_res32$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 output 31 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 13 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 15 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 32 \xer_so$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" + cell $pos $extend$libresoc.v:141612$7545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \Y_WIDTH 129 + connect \A \$18 + connect \Y $extend$libresoc.v:141612$7545_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" + cell $mul $mul$libresoc.v:141611$7544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 128 + connect \A \ra + connect \B \rb + connect \Y $mul$libresoc.v:141611$7544_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" + cell $pos $pos$libresoc.v:141612$7546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 129 + parameter \Y_WIDTH 129 + connect \A $extend$libresoc.v:141612$7545_Y + connect \Y $pos$libresoc.v:141612$7546_Y + end + connect \$18 $mul$libresoc.v:141611$7544_Y + connect \$17 $pos$libresoc.v:141612$7546_Y + connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$14 \xer_so + connect \neg_res32$16 \neg_res32 + connect \neg_res$15 \neg_res + connect \o \$17 +end +attribute \src "libresoc.v:141623.1-142002.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy 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$reduce_and$libresoc.v:141909$7553_Y + attribute \src "libresoc.v:141913.18-141913.107" + wire $reduce_and$libresoc.v:141913$7557_Y + attribute \src "libresoc.v:141908.18-141908.106" + wire $reduce_or$libresoc.v:141908$7552_Y + attribute \src "libresoc.v:141912.18-141912.107" + wire $reduce_or$libresoc.v:141912$7556_Y + attribute \src "libresoc.v:141907.18-141907.114" + wire width 130 $ternary$libresoc.v:141907$7551_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + wire width 130 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + wire width 130 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 130 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + wire width 130 \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \$39 + attribute \src "libresoc.v:141624.7-141624.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:36" + wire \is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:40" + wire width 129 \mul_o + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 18 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 19 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 12 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 28 \mul_op__insn$13 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 17 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 23 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 24 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 22 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 21 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 25 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:60" + wire \mul_ov + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 35 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 16 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire input 15 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 input 13 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 29 \o$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 30 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 31 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 32 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 14 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 33 \xer_so$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 34 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + cell $and $and$libresoc.v:141911$7555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$23 + connect \B \$25 + connect \Y $and$libresoc.v:141911$7555_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + cell $and $and$libresoc.v:141915$7559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$31 + connect \B \$33 + connect \Y $and$libresoc.v:141915$7559_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + cell $pos $extend$libresoc.v:141905$7547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 129 + parameter \Y_WIDTH 130 + connect \A \o + connect \Y $extend$libresoc.v:141905$7547_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$libresoc.v:141906$7549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 129 + parameter \Y_WIDTH 130 + connect \A \o + connect \Y $extend$libresoc.v:141906$7549_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$libresoc.v:141916$7560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \xer_so + connect \Y $extend$libresoc.v:141916$7560_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + cell $neg $neg$libresoc.v:141905$7548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 130 + parameter \Y_WIDTH 130 + connect \A $extend$libresoc.v:141905$7547_Y + connect \Y $neg$libresoc.v:141905$7548_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + cell $not $not$libresoc.v:141910$7554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \Y $not$libresoc.v:141910$7554_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + cell $not $not$libresoc.v:141914$7558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$34 + connect \Y $not$libresoc.v:141914$7558_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:141906$7550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 130 + parameter \Y_WIDTH 130 + connect \A $extend$libresoc.v:141906$7549_Y + connect \Y $pos$libresoc.v:141906$7550_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:141916$7561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A $extend$libresoc.v:141916$7560_Y + connect \Y $pos$libresoc.v:141916$7561_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + cell $reduce_and $reduce_and$libresoc.v:141909$7553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 33 + parameter \Y_WIDTH 1 + connect \A \mul_o [63:31] + connect \Y $reduce_and$libresoc.v:141909$7553_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + cell $reduce_and $reduce_and$libresoc.v:141913$7557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 1 + connect \A \mul_o [127:63] + connect \Y $reduce_and$libresoc.v:141913$7557_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + cell $reduce_or $reduce_or$libresoc.v:141908$7552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 33 + parameter \Y_WIDTH 1 + connect \A \mul_o [63:31] + connect \Y $reduce_or$libresoc.v:141908$7552_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + cell $reduce_or $reduce_or$libresoc.v:141912$7556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 1 + connect \A \mul_o [127:63] + connect \Y $reduce_or$libresoc.v:141912$7556_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + cell $mux $ternary$libresoc.v:141907$7551 + parameter \WIDTH 130 + connect \A \$19 + connect \B \$17 + connect \S \neg_res + connect \Y $ternary$libresoc.v:141907$7551_Y + end + attribute \src "libresoc.v:141624.7-141624.20" + process $proc$libresoc.v:141624$7569 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:141917.3-141935.6" + process $proc$libresoc.v:141917$7562 + assign { } { } + assign { } { } + assign $0\o$14[63:0]$7563 $1\o$14[63:0]$7564 + attribute \src "libresoc.v:141918.5-141918.29" + switch \initial + attribute \src "libresoc.v:141918.9-141918.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" + switch \mul_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110100 + assign { } { } + assign $1\o$14[63:0]$7564 { \mul_o [63:32] \mul_o [63:32] } + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 + assign { } { } + assign $1\o$14[63:0]$7564 \mul_o [127:64] + attribute \src "libresoc.v:0.0-0.0" + case 7'0110010 + assign { } { } + assign $1\o$14[63:0]$7564 \mul_o [63:0] + case + assign $1\o$14[63:0]$7564 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \o$14 $0\o$14[63:0]$7563 + end + attribute \src "libresoc.v:141936.3-141954.6" + process $proc$libresoc.v:141936$7565 + assign { } { } + assign { } { } + assign $0\o_ok[0:0] $1\o_ok[0:0] + attribute \src "libresoc.v:141937.5-141937.29" + switch \initial + attribute \src "libresoc.v:141937.9-141937.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" + switch \mul_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110100 + assign { } { } + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 + assign { } { } + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110010 + assign { } { } + assign $1\o_ok[0:0] 1'1 + case + assign $1\o_ok[0:0] 1'0 + end + sync always + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:141955.3-141973.6" + process $proc$libresoc.v:141955$7566 + assign { } { } + assign { } { } + assign $0\mul_ov[0:0] $1\mul_ov[0:0] + attribute \src "libresoc.v:141956.5-141956.29" + switch \initial + attribute \src "libresoc.v:141956.9-141956.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" + switch \mul_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110010 + assign { } { } + assign $1\mul_ov[0:0] $2\mul_ov[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:61" + switch \is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\mul_ov[0:0] \$29 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\mul_ov[0:0] \$37 + end + case + assign $1\mul_ov[0:0] 1'0 + end + sync always + update \mul_ov $0\mul_ov[0:0] + end + attribute \src "libresoc.v:141974.3-141984.6" + process $proc$libresoc.v:141974$7567 + assign { } { } + assign { } { } + assign $0\xer_ov[1:0] $1\xer_ov[1:0] + attribute \src "libresoc.v:141975.5-141975.29" + switch \initial + attribute \src "libresoc.v:141975.9-141975.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" + switch \mul_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110010 + assign { } { } + assign $1\xer_ov[1:0] { \mul_ov \mul_ov } + case + assign $1\xer_ov[1:0] 2'00 + end + sync always + update \xer_ov $0\xer_ov[1:0] + end + attribute \src "libresoc.v:141985.3-141995.6" + process $proc$libresoc.v:141985$7568 + assign { } { } + assign { } { } + assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:141986.5-141986.29" + switch \initial + attribute \src "libresoc.v:141986.9-141986.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" + switch \mul_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110010 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'1 + case + assign $1\xer_ov_ok[0:0] 1'0 + end + sync always + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + connect \$17 $neg$libresoc.v:141905$7548_Y + connect \$19 $pos$libresoc.v:141906$7550_Y + connect \$21 $ternary$libresoc.v:141907$7551_Y + connect \$23 $reduce_or$libresoc.v:141908$7552_Y + connect \$26 $reduce_and$libresoc.v:141909$7553_Y + connect \$25 $not$libresoc.v:141910$7554_Y + connect \$29 $and$libresoc.v:141911$7555_Y + connect \$31 $reduce_or$libresoc.v:141912$7556_Y + connect \$34 $reduce_and$libresoc.v:141913$7557_Y + connect \$33 $not$libresoc.v:141914$7558_Y + connect \$37 $and$libresoc.v:141915$7559_Y + connect \$39 $pos$libresoc.v:141916$7561_Y + connect \$16 \$21 + connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \muxid$1 \muxid + connect { \xer_so_ok \xer_so$15 } \$39 + connect \mul_o \$21 [128:0] + connect \is_32bit \mul_op__is_32bit +end +attribute \src "libresoc.v:142006.1-143202.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1" +attribute \generator "nMigen" +module \mul_pipe1 + attribute \src "libresoc.v:142007.7-142007.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:143079.3-143114.6" + wire width 12 $0\mul_op__fn_unit$next[11:0]$7598 + attribute \src "libresoc.v:142944.3-142945.47" + wire width 12 $0\mul_op__fn_unit[11:0] + attribute \src "libresoc.v:143079.3-143114.6" + wire width 64 $0\mul_op__imm_data__data$next[63:0]$7599 + attribute \src "libresoc.v:142946.3-142947.61" + wire width 64 $0\mul_op__imm_data__data[63:0] + attribute \src "libresoc.v:143079.3-143114.6" + wire $0\mul_op__imm_data__ok$next[0:0]$7600 + attribute \src "libresoc.v:142948.3-142949.57" + wire $0\mul_op__imm_data__ok[0:0] + attribute \src "libresoc.v:143079.3-143114.6" + wire width 32 $0\mul_op__insn$next[31:0]$7601 + attribute \src "libresoc.v:142964.3-142965.41" + wire width 32 $0\mul_op__insn[31:0] + attribute \src "libresoc.v:143079.3-143114.6" + wire width 7 $0\mul_op__insn_type$next[6:0]$7602 + attribute \src "libresoc.v:142942.3-142943.51" + wire width 7 $0\mul_op__insn_type[6:0] + attribute \src "libresoc.v:143079.3-143114.6" + wire $0\mul_op__is_32bit$next[0:0]$7603 + attribute \src "libresoc.v:142960.3-142961.49" + wire $0\mul_op__is_32bit[0:0] + attribute \src "libresoc.v:143079.3-143114.6" + wire $0\mul_op__is_signed$next[0:0]$7604 + attribute \src "libresoc.v:142962.3-142963.51" + wire $0\mul_op__is_signed[0:0] + attribute \src "libresoc.v:143079.3-143114.6" + wire $0\mul_op__oe__oe$next[0:0]$7605 + attribute \src "libresoc.v:142954.3-142955.45" + wire $0\mul_op__oe__oe[0:0] + attribute \src "libresoc.v:143079.3-143114.6" + wire $0\mul_op__oe__ok$next[0:0]$7606 + attribute \src "libresoc.v:142956.3-142957.45" + wire $0\mul_op__oe__ok[0:0] + attribute \src "libresoc.v:143079.3-143114.6" + wire $0\mul_op__rc__ok$next[0:0]$7607 + attribute \src "libresoc.v:142952.3-142953.45" + wire $0\mul_op__rc__ok[0:0] + attribute \src "libresoc.v:143079.3-143114.6" + wire $0\mul_op__rc__rc$next[0:0]$7608 + attribute \src "libresoc.v:142950.3-142951.45" + wire $0\mul_op__rc__rc[0:0] + attribute \src "libresoc.v:143079.3-143114.6" + wire $0\mul_op__write_cr0$next[0:0]$7609 + attribute \src "libresoc.v:142958.3-142959.51" + wire $0\mul_op__write_cr0[0:0] + attribute \src "libresoc.v:143066.3-143078.6" + wire width 2 $0\muxid$next[1:0]$7595 + attribute \src "libresoc.v:142966.3-142967.27" + wire width 2 $0\muxid[1:0] + attribute \src "libresoc.v:143154.3-143166.6" + wire $0\neg_res$next[0:0]$7638 + attribute \src "libresoc.v:143167.3-143179.6" + wire $0\neg_res32$next[0:0]$7641 + attribute \src "libresoc.v:142932.3-142933.35" + wire $0\neg_res32[0:0] + attribute \src "libresoc.v:142934.3-142935.31" + wire $0\neg_res[0:0] + attribute \src "libresoc.v:143048.3-143065.6" + wire $0\r_busy$next[0:0]$7591 + attribute \src "libresoc.v:142968.3-142969.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:143115.3-143127.6" + wire width 64 $0\ra$next[63:0]$7629 + attribute \src "libresoc.v:142940.3-142941.21" + wire width 64 $0\ra[63:0] + attribute \src "libresoc.v:143128.3-143140.6" + wire width 64 $0\rb$next[63:0]$7632 + attribute \src "libresoc.v:142938.3-142939.21" + wire width 64 $0\rb[63:0] + attribute \src "libresoc.v:143141.3-143153.6" + wire $0\xer_so$next[0:0]$7635 + attribute \src "libresoc.v:142936.3-142937.29" + wire $0\xer_so[0:0] + attribute \src "libresoc.v:143079.3-143114.6" + wire width 12 $1\mul_op__fn_unit$next[11:0]$7610 + attribute \src "libresoc.v:142509.14-142509.39" + wire width 12 $1\mul_op__fn_unit[11:0] + attribute \src "libresoc.v:143079.3-143114.6" + wire width 64 $1\mul_op__imm_data__data$next[63:0]$7611 + attribute \src "libresoc.v:142544.14-142544.59" + wire width 64 $1\mul_op__imm_data__data[63:0] + attribute \src "libresoc.v:143079.3-143114.6" + wire $1\mul_op__imm_data__ok$next[0:0]$7612 + attribute \src "libresoc.v:142553.7-142553.34" + wire $1\mul_op__imm_data__ok[0:0] + attribute \src "libresoc.v:143079.3-143114.6" + wire width 32 $1\mul_op__insn$next[31:0]$7613 + attribute \src "libresoc.v:142562.14-142562.34" + wire width 32 $1\mul_op__insn[31:0] + attribute \src "libresoc.v:143079.3-143114.6" + wire width 7 $1\mul_op__insn_type$next[6:0]$7614 + attribute \src "libresoc.v:142645.13-142645.38" + wire width 7 $1\mul_op__insn_type[6:0] + attribute \src "libresoc.v:143079.3-143114.6" + wire $1\mul_op__is_32bit$next[0:0]$7615 + attribute \src "libresoc.v:142802.7-142802.30" + wire $1\mul_op__is_32bit[0:0] + attribute \src "libresoc.v:143079.3-143114.6" + wire $1\mul_op__is_signed$next[0:0]$7616 + attribute \src "libresoc.v:142811.7-142811.31" + wire $1\mul_op__is_signed[0:0] + attribute \src "libresoc.v:143079.3-143114.6" + wire $1\mul_op__oe__oe$next[0:0]$7617 + attribute \src "libresoc.v:142820.7-142820.28" + wire $1\mul_op__oe__oe[0:0] + attribute \src "libresoc.v:143079.3-143114.6" + wire $1\mul_op__oe__ok$next[0:0]$7618 + attribute \src "libresoc.v:142829.7-142829.28" + wire $1\mul_op__oe__ok[0:0] + attribute \src "libresoc.v:143079.3-143114.6" + wire $1\mul_op__rc__ok$next[0:0]$7619 + attribute \src "libresoc.v:142838.7-142838.28" + wire $1\mul_op__rc__ok[0:0] + attribute \src "libresoc.v:143079.3-143114.6" + wire $1\mul_op__rc__rc$next[0:0]$7620 + attribute \src "libresoc.v:142847.7-142847.28" + wire $1\mul_op__rc__rc[0:0] + attribute \src "libresoc.v:143079.3-143114.6" + wire $1\mul_op__write_cr0$next[0:0]$7621 + attribute \src "libresoc.v:142856.7-142856.31" + wire $1\mul_op__write_cr0[0:0] + attribute \src "libresoc.v:143066.3-143078.6" + wire width 2 $1\muxid$next[1:0]$7596 + attribute \src "libresoc.v:142865.13-142865.25" + wire width 2 $1\muxid[1:0] + attribute \src "libresoc.v:143154.3-143166.6" + wire $1\neg_res$next[0:0]$7639 + attribute \src "libresoc.v:143167.3-143179.6" + wire $1\neg_res32$next[0:0]$7642 + attribute \src "libresoc.v:142887.7-142887.23" + wire $1\neg_res32[0:0] + attribute \src "libresoc.v:142880.7-142880.21" + wire $1\neg_res[0:0] + attribute \src "libresoc.v:143048.3-143065.6" + wire $1\r_busy$next[0:0]$7592 + attribute \src "libresoc.v:142901.7-142901.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:143115.3-143127.6" + wire width 64 $1\ra$next[63:0]$7630 + attribute \src "libresoc.v:142906.14-142906.39" + wire width 64 $1\ra[63:0] + attribute \src "libresoc.v:143128.3-143140.6" + wire width 64 $1\rb$next[63:0]$7633 + attribute \src "libresoc.v:142915.14-142915.39" + wire width 64 $1\rb[63:0] + attribute \src "libresoc.v:143141.3-143153.6" + wire $1\xer_so$next[0:0]$7636 + attribute \src "libresoc.v:142924.7-142924.20" + wire $1\xer_so[0:0] + attribute \src "libresoc.v:143079.3-143114.6" + wire width 64 $2\mul_op__imm_data__data$next[63:0]$7622 + attribute \src "libresoc.v:143079.3-143114.6" + wire $2\mul_op__imm_data__ok$next[0:0]$7623 + attribute \src "libresoc.v:143079.3-143114.6" + wire $2\mul_op__oe__oe$next[0:0]$7624 + attribute \src "libresoc.v:143079.3-143114.6" + wire $2\mul_op__oe__ok$next[0:0]$7625 + attribute \src "libresoc.v:143079.3-143114.6" + wire $2\mul_op__rc__ok$next[0:0]$7626 + attribute \src "libresoc.v:143079.3-143114.6" + wire $2\mul_op__rc__rc$next[0:0]$7627 + attribute \src "libresoc.v:143048.3-143065.6" + wire $2\r_busy$next[0:0]$7593 + attribute \src "libresoc.v:142931.18-142931.118" + wire $and$libresoc.v:142931$7570_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 40 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:142007.7-142007.15" + wire \initial + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \input_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \input_mul_op__fn_unit$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_mul_op__imm_data__data$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__imm_data__ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_mul_op__insn$29 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_mul_op__insn_type$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__is_32bit$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__is_signed$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__oe__oe$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__oe__ok$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__rc__ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__rc__rc$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__write_cr0$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so$32 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul1_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul1_mul_op__fn_unit$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul1_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul1_mul_op__imm_data__data$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__imm_data__ok$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul1_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul1_mul_op__insn$45 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul1_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul1_mul_op__insn_type$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__is_32bit$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__is_signed$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__oe__oe$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__oe__ok$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__rc__ok$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__rc__rc$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__write_cr0$42 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul1_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul1_muxid$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire \mul1_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire \mul1_neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul1_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul1_ra$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul1_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul1_rb$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul1_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul1_xer_so$48 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 6 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 26 \mul_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_op__fn_unit$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 27 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__data$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 28 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 16 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 36 \mul_op__insn$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 5 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 25 \mul_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 34 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_32bit$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 35 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_signed$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__oe$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 31 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__ok$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 32 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 30 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 29 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 33 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 24 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$52 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire output 20 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire \neg_res$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire \neg_res$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire output 21 \neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire \neg_res32$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire \neg_res32$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 23 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 22 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$49 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 17 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 37 \ra$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 18 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 38 \rb$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 19 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 39 \xer_so$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$libresoc.v:142931$7570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$49 + connect \B \p_ready_o + connect \Y $and$libresoc.v:142931$7570_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:142970.14-143003.4" + cell \input$95 \input + connect \mul_op__fn_unit \input_mul_op__fn_unit + connect \mul_op__fn_unit$3 \input_mul_op__fn_unit$19 + connect \mul_op__imm_data__data \input_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \input_mul_op__imm_data__data$20 + connect \mul_op__imm_data__ok \input_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \input_mul_op__imm_data__ok$21 + connect \mul_op__insn \input_mul_op__insn + connect \mul_op__insn$13 \input_mul_op__insn$29 + connect \mul_op__insn_type \input_mul_op__insn_type + connect \mul_op__insn_type$2 \input_mul_op__insn_type$18 + connect \mul_op__is_32bit \input_mul_op__is_32bit + connect \mul_op__is_32bit$11 \input_mul_op__is_32bit$27 + connect \mul_op__is_signed \input_mul_op__is_signed + connect \mul_op__is_signed$12 \input_mul_op__is_signed$28 + connect \mul_op__oe__oe \input_mul_op__oe__oe + connect \mul_op__oe__oe$8 \input_mul_op__oe__oe$24 + connect \mul_op__oe__ok \input_mul_op__oe__ok + connect \mul_op__oe__ok$9 \input_mul_op__oe__ok$25 + connect \mul_op__rc__ok \input_mul_op__rc__ok + connect \mul_op__rc__ok$7 \input_mul_op__rc__ok$23 + connect \mul_op__rc__rc \input_mul_op__rc__rc + connect \mul_op__rc__rc$6 \input_mul_op__rc__rc$22 + connect \mul_op__write_cr0 \input_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \input_mul_op__write_cr0$26 + connect \muxid \input_muxid + connect \muxid$1 \input_muxid$17 + connect \ra \input_ra + connect \ra$14 \input_ra$30 + connect \rb \input_rb + connect \rb$15 \input_rb$31 + connect \xer_so \input_xer_so + connect \xer_so$16 \input_xer_so$32 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:143004.8-143039.4" + cell \mul1 \mul1 + connect \mul_op__fn_unit \mul1_mul_op__fn_unit + connect \mul_op__fn_unit$3 \mul1_mul_op__fn_unit$35 + connect \mul_op__imm_data__data \mul1_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \mul1_mul_op__imm_data__data$36 + connect \mul_op__imm_data__ok \mul1_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \mul1_mul_op__imm_data__ok$37 + connect \mul_op__insn \mul1_mul_op__insn + connect \mul_op__insn$13 \mul1_mul_op__insn$45 + connect \mul_op__insn_type \mul1_mul_op__insn_type + connect \mul_op__insn_type$2 \mul1_mul_op__insn_type$34 + connect \mul_op__is_32bit \mul1_mul_op__is_32bit + connect \mul_op__is_32bit$11 \mul1_mul_op__is_32bit$43 + connect \mul_op__is_signed \mul1_mul_op__is_signed + connect \mul_op__is_signed$12 \mul1_mul_op__is_signed$44 + connect \mul_op__oe__oe \mul1_mul_op__oe__oe + connect \mul_op__oe__oe$8 \mul1_mul_op__oe__oe$40 + connect \mul_op__oe__ok \mul1_mul_op__oe__ok + connect \mul_op__oe__ok$9 \mul1_mul_op__oe__ok$41 + connect \mul_op__rc__ok \mul1_mul_op__rc__ok + connect \mul_op__rc__ok$7 \mul1_mul_op__rc__ok$39 + connect \mul_op__rc__rc \mul1_mul_op__rc__rc + connect \mul_op__rc__rc$6 \mul1_mul_op__rc__rc$38 + connect \mul_op__write_cr0 \mul1_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \mul1_mul_op__write_cr0$42 + connect \muxid \mul1_muxid + connect \muxid$1 \mul1_muxid$33 + connect \neg_res \mul1_neg_res + connect \neg_res32 \mul1_neg_res32 + connect \ra \mul1_ra + connect \ra$14 \mul1_ra$46 + connect \rb \mul1_rb + connect \rb$15 \mul1_rb$47 + connect \xer_so \mul1_xer_so + connect \xer_so$16 \mul1_xer_so$48 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:143040.10-143043.4" + cell \n$94 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:143044.10-143047.4" + cell \p$93 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:142007.7-142007.20" + process $proc$libresoc.v:142007$7643 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:142509.14-142509.39" + process $proc$libresoc.v:142509$7644 + assign { } { } + assign $1\mul_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \mul_op__fn_unit $1\mul_op__fn_unit[11:0] + end + attribute \src "libresoc.v:142544.14-142544.59" + process $proc$libresoc.v:142544$7645 + assign { } { } + assign $1\mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \mul_op__imm_data__data $1\mul_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:142553.7-142553.34" + process $proc$libresoc.v:142553$7646 + assign { } { } + assign $1\mul_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \mul_op__imm_data__ok $1\mul_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:142562.14-142562.34" + process $proc$libresoc.v:142562$7647 + assign { } { } + assign $1\mul_op__insn[31:0] 0 + sync always + sync init + update \mul_op__insn $1\mul_op__insn[31:0] + end + attribute \src "libresoc.v:142645.13-142645.38" + process $proc$libresoc.v:142645$7648 + assign { } { } + assign $1\mul_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \mul_op__insn_type $1\mul_op__insn_type[6:0] + end + attribute \src "libresoc.v:142802.7-142802.30" + process $proc$libresoc.v:142802$7649 + assign { } { } + assign $1\mul_op__is_32bit[0:0] 1'0 + sync always + sync init + update \mul_op__is_32bit $1\mul_op__is_32bit[0:0] + end + attribute \src "libresoc.v:142811.7-142811.31" + process $proc$libresoc.v:142811$7650 + assign { } { } + assign $1\mul_op__is_signed[0:0] 1'0 + sync always + sync init + update \mul_op__is_signed $1\mul_op__is_signed[0:0] + end + attribute \src "libresoc.v:142820.7-142820.28" + process $proc$libresoc.v:142820$7651 + assign { } { } + assign $1\mul_op__oe__oe[0:0] 1'0 + sync always + sync init + update \mul_op__oe__oe $1\mul_op__oe__oe[0:0] + end + attribute \src "libresoc.v:142829.7-142829.28" + process $proc$libresoc.v:142829$7652 + assign { } { } + assign $1\mul_op__oe__ok[0:0] 1'0 + sync always + sync init + update \mul_op__oe__ok $1\mul_op__oe__ok[0:0] + end + attribute \src "libresoc.v:142838.7-142838.28" + process $proc$libresoc.v:142838$7653 + assign { } { } + assign $1\mul_op__rc__ok[0:0] 1'0 + sync always + sync init + update \mul_op__rc__ok $1\mul_op__rc__ok[0:0] + end + attribute \src "libresoc.v:142847.7-142847.28" + process $proc$libresoc.v:142847$7654 + assign { } { } + assign $1\mul_op__rc__rc[0:0] 1'0 + sync always + sync init + update \mul_op__rc__rc $1\mul_op__rc__rc[0:0] + end + attribute \src "libresoc.v:142856.7-142856.31" + process $proc$libresoc.v:142856$7655 + assign { } { } + assign $1\mul_op__write_cr0[0:0] 1'0 + sync always + sync init + update \mul_op__write_cr0 $1\mul_op__write_cr0[0:0] + end + attribute \src "libresoc.v:142865.13-142865.25" + process $proc$libresoc.v:142865$7656 + assign { } { } + assign $1\muxid[1:0] 2'00 + sync always + sync init + update \muxid $1\muxid[1:0] + end + attribute \src "libresoc.v:142880.7-142880.21" + process $proc$libresoc.v:142880$7657 + assign { } { } + assign $1\neg_res[0:0] 1'0 + sync always + sync init + update \neg_res $1\neg_res[0:0] + end + attribute \src "libresoc.v:142887.7-142887.23" + process $proc$libresoc.v:142887$7658 + assign { } { } + assign $1\neg_res32[0:0] 1'0 + sync always + sync init + update \neg_res32 $1\neg_res32[0:0] + end + attribute \src "libresoc.v:142901.7-142901.20" + process $proc$libresoc.v:142901$7659 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:142906.14-142906.39" + process $proc$libresoc.v:142906$7660 + assign { } { } + assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ra $1\ra[63:0] + end + attribute \src "libresoc.v:142915.14-142915.39" + process $proc$libresoc.v:142915$7661 + assign { } { } + assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \rb $1\rb[63:0] + end + attribute \src "libresoc.v:142924.7-142924.20" + process $proc$libresoc.v:142924$7662 + assign { } { } + assign $1\xer_so[0:0] 1'0 + sync always + sync init + update \xer_so $1\xer_so[0:0] + end + attribute \src "libresoc.v:142932.3-142933.35" + process $proc$libresoc.v:142932$7571 + assign { } { } + assign $0\neg_res32[0:0] \neg_res32$next + sync posedge \coresync_clk + update \neg_res32 $0\neg_res32[0:0] + end + attribute \src "libresoc.v:142934.3-142935.31" + process $proc$libresoc.v:142934$7572 + assign { } { } + assign $0\neg_res[0:0] \neg_res$next + sync posedge \coresync_clk + update \neg_res $0\neg_res[0:0] + end + attribute \src "libresoc.v:142936.3-142937.29" + process $proc$libresoc.v:142936$7573 + assign { } { } + assign $0\xer_so[0:0] \xer_so$next + sync posedge \coresync_clk + update \xer_so $0\xer_so[0:0] + end + attribute \src "libresoc.v:142938.3-142939.21" + process $proc$libresoc.v:142938$7574 + assign { } { } + assign $0\rb[63:0] \rb$next + sync posedge \coresync_clk + update \rb $0\rb[63:0] + end + attribute \src "libresoc.v:142940.3-142941.21" + process $proc$libresoc.v:142940$7575 + assign { } { } + assign $0\ra[63:0] \ra$next + sync posedge \coresync_clk + update \ra $0\ra[63:0] + end + attribute \src "libresoc.v:142942.3-142943.51" + process $proc$libresoc.v:142942$7576 + assign { } { } + assign $0\mul_op__insn_type[6:0] \mul_op__insn_type$next + sync posedge \coresync_clk + update \mul_op__insn_type $0\mul_op__insn_type[6:0] + end + attribute \src "libresoc.v:142944.3-142945.47" + process $proc$libresoc.v:142944$7577 + assign { } { } + assign $0\mul_op__fn_unit[11:0] \mul_op__fn_unit$next + sync posedge \coresync_clk + update \mul_op__fn_unit $0\mul_op__fn_unit[11:0] + end + attribute \src "libresoc.v:142946.3-142947.61" + process $proc$libresoc.v:142946$7578 + assign { } { } + assign $0\mul_op__imm_data__data[63:0] \mul_op__imm_data__data$next + sync posedge \coresync_clk + update \mul_op__imm_data__data $0\mul_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:142948.3-142949.57" + process $proc$libresoc.v:142948$7579 + assign { } { } + assign $0\mul_op__imm_data__ok[0:0] \mul_op__imm_data__ok$next + sync posedge \coresync_clk + update \mul_op__imm_data__ok $0\mul_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:142950.3-142951.45" + process $proc$libresoc.v:142950$7580 + assign { } { } + assign $0\mul_op__rc__rc[0:0] \mul_op__rc__rc$next + sync posedge \coresync_clk + update \mul_op__rc__rc $0\mul_op__rc__rc[0:0] + end + attribute \src "libresoc.v:142952.3-142953.45" + process $proc$libresoc.v:142952$7581 + assign { } { } + assign $0\mul_op__rc__ok[0:0] \mul_op__rc__ok$next + sync posedge \coresync_clk + update \mul_op__rc__ok $0\mul_op__rc__ok[0:0] + end + attribute \src "libresoc.v:142954.3-142955.45" + process $proc$libresoc.v:142954$7582 + assign { } { } + assign $0\mul_op__oe__oe[0:0] \mul_op__oe__oe$next + sync posedge \coresync_clk + update \mul_op__oe__oe $0\mul_op__oe__oe[0:0] + end + attribute \src "libresoc.v:142956.3-142957.45" + process $proc$libresoc.v:142956$7583 + assign { } { } + assign $0\mul_op__oe__ok[0:0] \mul_op__oe__ok$next + sync posedge \coresync_clk + update \mul_op__oe__ok $0\mul_op__oe__ok[0:0] + end + attribute \src "libresoc.v:142958.3-142959.51" + process $proc$libresoc.v:142958$7584 + assign { } { } + assign $0\mul_op__write_cr0[0:0] \mul_op__write_cr0$next + sync posedge \coresync_clk + update \mul_op__write_cr0 $0\mul_op__write_cr0[0:0] + end + attribute \src "libresoc.v:142960.3-142961.49" + process $proc$libresoc.v:142960$7585 + assign { } { } + assign $0\mul_op__is_32bit[0:0] \mul_op__is_32bit$next + sync posedge \coresync_clk + update \mul_op__is_32bit $0\mul_op__is_32bit[0:0] + end + attribute \src "libresoc.v:142962.3-142963.51" + process $proc$libresoc.v:142962$7586 + assign { } { } + assign $0\mul_op__is_signed[0:0] \mul_op__is_signed$next + sync posedge \coresync_clk + update \mul_op__is_signed $0\mul_op__is_signed[0:0] + end + attribute \src "libresoc.v:142964.3-142965.41" + process $proc$libresoc.v:142964$7587 + assign { } { } + assign $0\mul_op__insn[31:0] \mul_op__insn$next + sync posedge \coresync_clk + update \mul_op__insn $0\mul_op__insn[31:0] + end + attribute \src "libresoc.v:142966.3-142967.27" + process $proc$libresoc.v:142966$7588 + assign { } { } + assign $0\muxid[1:0] \muxid$next + sync posedge \coresync_clk + update \muxid $0\muxid[1:0] + end + attribute \src "libresoc.v:142968.3-142969.29" + process $proc$libresoc.v:142968$7589 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:143048.3-143065.6" + process $proc$libresoc.v:143048$7590 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$7591 $2\r_busy$next[0:0]$7593 + attribute \src "libresoc.v:143049.5-143049.29" + switch \initial + attribute \src "libresoc.v:143049.9-143049.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$7592 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$7592 1'0 + case + assign $1\r_busy$next[0:0]$7592 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$7593 1'0 + case + assign $2\r_busy$next[0:0]$7593 $1\r_busy$next[0:0]$7592 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$7591 + end + attribute \src "libresoc.v:143066.3-143078.6" + process $proc$libresoc.v:143066$7594 + assign { } { } + assign { } { } + assign $0\muxid$next[1:0]$7595 $1\muxid$next[1:0]$7596 + attribute \src "libresoc.v:143067.5-143067.29" + switch \initial + attribute \src "libresoc.v:143067.9-143067.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$next[1:0]$7596 \muxid$52 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$next[1:0]$7596 \muxid$52 + case + assign $1\muxid$next[1:0]$7596 \muxid + end + sync always + update \muxid$next $0\muxid$next[1:0]$7595 + end + attribute \src "libresoc.v:143079.3-143114.6" + process $proc$libresoc.v:143079$7597 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mul_op__fn_unit$next[11:0]$7598 $1\mul_op__fn_unit$next[11:0]$7610 + assign { } { } + assign { } { } + assign $0\mul_op__insn$next[31:0]$7601 $1\mul_op__insn$next[31:0]$7613 + assign $0\mul_op__insn_type$next[6:0]$7602 $1\mul_op__insn_type$next[6:0]$7614 + assign $0\mul_op__is_32bit$next[0:0]$7603 $1\mul_op__is_32bit$next[0:0]$7615 + assign $0\mul_op__is_signed$next[0:0]$7604 $1\mul_op__is_signed$next[0:0]$7616 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mul_op__write_cr0$next[0:0]$7609 $1\mul_op__write_cr0$next[0:0]$7621 + assign $0\mul_op__imm_data__data$next[63:0]$7599 $2\mul_op__imm_data__data$next[63:0]$7622 + assign $0\mul_op__imm_data__ok$next[0:0]$7600 $2\mul_op__imm_data__ok$next[0:0]$7623 + assign $0\mul_op__oe__oe$next[0:0]$7605 $2\mul_op__oe__oe$next[0:0]$7624 + assign $0\mul_op__oe__ok$next[0:0]$7606 $2\mul_op__oe__ok$next[0:0]$7625 + assign $0\mul_op__rc__ok$next[0:0]$7607 $2\mul_op__rc__ok$next[0:0]$7626 + assign $0\mul_op__rc__rc$next[0:0]$7608 $2\mul_op__rc__rc$next[0:0]$7627 + attribute \src "libresoc.v:143080.5-143080.29" + switch \initial + attribute \src "libresoc.v:143080.9-143080.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\mul_op__insn$next[31:0]$7613 $1\mul_op__is_signed$next[0:0]$7616 $1\mul_op__is_32bit$next[0:0]$7615 $1\mul_op__write_cr0$next[0:0]$7621 $1\mul_op__oe__ok$next[0:0]$7618 $1\mul_op__oe__oe$next[0:0]$7617 $1\mul_op__rc__ok$next[0:0]$7619 $1\mul_op__rc__rc$next[0:0]$7620 $1\mul_op__imm_data__ok$next[0:0]$7612 $1\mul_op__imm_data__data$next[63:0]$7611 $1\mul_op__fn_unit$next[11:0]$7610 $1\mul_op__insn_type$next[6:0]$7614 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\mul_op__insn$next[31:0]$7613 $1\mul_op__is_signed$next[0:0]$7616 $1\mul_op__is_32bit$next[0:0]$7615 $1\mul_op__write_cr0$next[0:0]$7621 $1\mul_op__oe__ok$next[0:0]$7618 $1\mul_op__oe__oe$next[0:0]$7617 $1\mul_op__rc__ok$next[0:0]$7619 $1\mul_op__rc__rc$next[0:0]$7620 $1\mul_op__imm_data__ok$next[0:0]$7612 $1\mul_op__imm_data__data$next[63:0]$7611 $1\mul_op__fn_unit$next[11:0]$7610 $1\mul_op__insn_type$next[6:0]$7614 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } + case + assign $1\mul_op__fn_unit$next[11:0]$7610 \mul_op__fn_unit + assign $1\mul_op__imm_data__data$next[63:0]$7611 \mul_op__imm_data__data + assign $1\mul_op__imm_data__ok$next[0:0]$7612 \mul_op__imm_data__ok + assign $1\mul_op__insn$next[31:0]$7613 \mul_op__insn + assign $1\mul_op__insn_type$next[6:0]$7614 \mul_op__insn_type + assign $1\mul_op__is_32bit$next[0:0]$7615 \mul_op__is_32bit + assign $1\mul_op__is_signed$next[0:0]$7616 \mul_op__is_signed + assign $1\mul_op__oe__oe$next[0:0]$7617 \mul_op__oe__oe + assign $1\mul_op__oe__ok$next[0:0]$7618 \mul_op__oe__ok + assign $1\mul_op__rc__ok$next[0:0]$7619 \mul_op__rc__ok + assign $1\mul_op__rc__rc$next[0:0]$7620 \mul_op__rc__rc + assign $1\mul_op__write_cr0$next[0:0]$7621 \mul_op__write_cr0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\mul_op__imm_data__data$next[63:0]$7622 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$next[0:0]$7623 1'0 + assign $2\mul_op__rc__rc$next[0:0]$7627 1'0 + assign $2\mul_op__rc__ok$next[0:0]$7626 1'0 + assign $2\mul_op__oe__oe$next[0:0]$7624 1'0 + assign $2\mul_op__oe__ok$next[0:0]$7625 1'0 + case + assign $2\mul_op__imm_data__data$next[63:0]$7622 $1\mul_op__imm_data__data$next[63:0]$7611 + assign $2\mul_op__imm_data__ok$next[0:0]$7623 $1\mul_op__imm_data__ok$next[0:0]$7612 + assign $2\mul_op__oe__oe$next[0:0]$7624 $1\mul_op__oe__oe$next[0:0]$7617 + assign $2\mul_op__oe__ok$next[0:0]$7625 $1\mul_op__oe__ok$next[0:0]$7618 + assign $2\mul_op__rc__ok$next[0:0]$7626 $1\mul_op__rc__ok$next[0:0]$7619 + assign $2\mul_op__rc__rc$next[0:0]$7627 $1\mul_op__rc__rc$next[0:0]$7620 + end + sync always + update \mul_op__fn_unit$next $0\mul_op__fn_unit$next[11:0]$7598 + update \mul_op__imm_data__data$next $0\mul_op__imm_data__data$next[63:0]$7599 + update \mul_op__imm_data__ok$next $0\mul_op__imm_data__ok$next[0:0]$7600 + update \mul_op__insn$next $0\mul_op__insn$next[31:0]$7601 + update \mul_op__insn_type$next $0\mul_op__insn_type$next[6:0]$7602 + update \mul_op__is_32bit$next $0\mul_op__is_32bit$next[0:0]$7603 + update \mul_op__is_signed$next $0\mul_op__is_signed$next[0:0]$7604 + update \mul_op__oe__oe$next $0\mul_op__oe__oe$next[0:0]$7605 + update \mul_op__oe__ok$next $0\mul_op__oe__ok$next[0:0]$7606 + update \mul_op__rc__ok$next $0\mul_op__rc__ok$next[0:0]$7607 + update \mul_op__rc__rc$next $0\mul_op__rc__rc$next[0:0]$7608 + update \mul_op__write_cr0$next $0\mul_op__write_cr0$next[0:0]$7609 + end + attribute \src "libresoc.v:143115.3-143127.6" + process $proc$libresoc.v:143115$7628 + assign { } { } + assign { } { } + assign $0\ra$next[63:0]$7629 $1\ra$next[63:0]$7630 + attribute \src "libresoc.v:143116.5-143116.29" + switch \initial + attribute \src "libresoc.v:143116.9-143116.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\ra$next[63:0]$7630 \ra$65 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\ra$next[63:0]$7630 \ra$65 + case + assign $1\ra$next[63:0]$7630 \ra + end + sync always + update \ra$next $0\ra$next[63:0]$7629 + end + attribute \src "libresoc.v:143128.3-143140.6" + process $proc$libresoc.v:143128$7631 + assign { } { } + assign { } { } + assign $0\rb$next[63:0]$7632 $1\rb$next[63:0]$7633 + attribute \src "libresoc.v:143129.5-143129.29" + switch \initial + attribute \src "libresoc.v:143129.9-143129.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\rb$next[63:0]$7633 \rb$66 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\rb$next[63:0]$7633 \rb$66 + case + assign $1\rb$next[63:0]$7633 \rb + end + sync always + update \rb$next $0\rb$next[63:0]$7632 + end + attribute \src "libresoc.v:143141.3-143153.6" + process $proc$libresoc.v:143141$7634 + assign { } { } + assign { } { } + assign $0\xer_so$next[0:0]$7635 $1\xer_so$next[0:0]$7636 + attribute \src "libresoc.v:143142.5-143142.29" + switch \initial + attribute \src "libresoc.v:143142.9-143142.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\xer_so$next[0:0]$7636 \xer_so$67 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\xer_so$next[0:0]$7636 \xer_so$67 + case + assign $1\xer_so$next[0:0]$7636 \xer_so + end + sync always + update \xer_so$next $0\xer_so$next[0:0]$7635 + end + attribute \src "libresoc.v:143154.3-143166.6" + process $proc$libresoc.v:143154$7637 + assign { } { } + assign { } { } + assign $0\neg_res$next[0:0]$7638 $1\neg_res$next[0:0]$7639 + attribute \src "libresoc.v:143155.5-143155.29" + switch \initial + attribute \src "libresoc.v:143155.9-143155.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\neg_res$next[0:0]$7639 \neg_res$68 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\neg_res$next[0:0]$7639 \neg_res$68 + case + assign $1\neg_res$next[0:0]$7639 \neg_res + end + sync always + update \neg_res$next $0\neg_res$next[0:0]$7638 + end + attribute \src "libresoc.v:143167.3-143179.6" + process $proc$libresoc.v:143167$7640 + assign { } { } + assign { } { } + assign $0\neg_res32$next[0:0]$7641 $1\neg_res32$next[0:0]$7642 + attribute \src "libresoc.v:143168.5-143168.29" + switch \initial + attribute \src "libresoc.v:143168.9-143168.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\neg_res32$next[0:0]$7642 \neg_res32$69 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\neg_res32$next[0:0]$7642 \neg_res32$69 + case + assign $1\neg_res32$next[0:0]$7642 \neg_res32 + end + sync always + update \neg_res32$next $0\neg_res32$next[0:0]$7641 + end + connect \$50 $and$libresoc.v:142931$7570_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect \neg_res32$69 \mul1_neg_res32 + connect \neg_res$68 \mul1_neg_res + connect \xer_so$67 \mul1_xer_so$48 + connect \rb$66 \mul1_rb$47 + connect \ra$65 \mul1_ra$46 + connect { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } { \mul1_mul_op__insn$45 \mul1_mul_op__is_signed$44 \mul1_mul_op__is_32bit$43 \mul1_mul_op__write_cr0$42 \mul1_mul_op__oe__ok$41 \mul1_mul_op__oe__oe$40 \mul1_mul_op__rc__ok$39 \mul1_mul_op__rc__rc$38 \mul1_mul_op__imm_data__ok$37 \mul1_mul_op__imm_data__data$36 \mul1_mul_op__fn_unit$35 \mul1_mul_op__insn_type$34 } + connect \muxid$52 \mul1_muxid$33 + connect \p_valid_i_p_ready_o \$50 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$49 \p_valid_i + connect \mul1_xer_so \input_xer_so$32 + connect \mul1_rb \input_rb$31 + connect \mul1_ra \input_ra$30 + connect { \mul1_mul_op__insn \mul1_mul_op__is_signed \mul1_mul_op__is_32bit \mul1_mul_op__write_cr0 \mul1_mul_op__oe__ok \mul1_mul_op__oe__oe \mul1_mul_op__rc__ok \mul1_mul_op__rc__rc \mul1_mul_op__imm_data__ok \mul1_mul_op__imm_data__data \mul1_mul_op__fn_unit \mul1_mul_op__insn_type } { \input_mul_op__insn$29 \input_mul_op__is_signed$28 \input_mul_op__is_32bit$27 \input_mul_op__write_cr0$26 \input_mul_op__oe__ok$25 \input_mul_op__oe__oe$24 \input_mul_op__rc__ok$23 \input_mul_op__rc__rc$22 \input_mul_op__imm_data__ok$21 \input_mul_op__imm_data__data$20 \input_mul_op__fn_unit$19 \input_mul_op__insn_type$18 } + connect \mul1_muxid \input_muxid$17 + connect \input_xer_so \xer_so$16 + connect \input_rb \rb$15 + connect \input_ra \ra$14 + connect { \input_mul_op__insn \input_mul_op__is_signed \input_mul_op__is_32bit \input_mul_op__write_cr0 \input_mul_op__oe__ok \input_mul_op__oe__oe \input_mul_op__rc__ok \input_mul_op__rc__rc \input_mul_op__imm_data__ok \input_mul_op__imm_data__data \input_mul_op__fn_unit \input_mul_op__insn_type } { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } + connect \input_muxid \muxid$1 +end +attribute \src "libresoc.v:143206.1-144111.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2" +attribute \generator "nMigen" +module \mul_pipe2 + attribute \src "libresoc.v:143207.7-143207.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:144005.3-144040.6" + wire width 12 $0\mul_op__fn_unit$3$next[11:0]$7706 + attribute \src "libresoc.v:143903.3-143904.53" + wire width 12 $0\mul_op__fn_unit$3[11:0]$7674 + attribute \src "libresoc.v:143488.14-143488.43" + wire width 12 $0\mul_op__fn_unit$3[11:0]$7750 + attribute \src "libresoc.v:144005.3-144040.6" + wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$7707 + attribute \src "libresoc.v:143905.3-143906.67" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$7676 + attribute \src "libresoc.v:143512.14-143512.63" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$7752 + attribute \src "libresoc.v:144005.3-144040.6" + wire $0\mul_op__imm_data__ok$5$next[0:0]$7708 + attribute \src "libresoc.v:143907.3-143908.63" + wire $0\mul_op__imm_data__ok$5[0:0]$7678 + attribute \src "libresoc.v:143521.7-143521.38" + wire $0\mul_op__imm_data__ok$5[0:0]$7754 + attribute \src "libresoc.v:144005.3-144040.6" + wire width 32 $0\mul_op__insn$13$next[31:0]$7709 + attribute \src "libresoc.v:143923.3-143924.49" + wire width 32 $0\mul_op__insn$13[31:0]$7694 + attribute \src "libresoc.v:143528.14-143528.39" + wire width 32 $0\mul_op__insn$13[31:0]$7756 + attribute \src "libresoc.v:144005.3-144040.6" + wire width 7 $0\mul_op__insn_type$2$next[6:0]$7710 + attribute \src "libresoc.v:143901.3-143902.57" + wire width 7 $0\mul_op__insn_type$2[6:0]$7672 + attribute \src "libresoc.v:143685.13-143685.42" + wire width 7 $0\mul_op__insn_type$2[6:0]$7758 + attribute \src "libresoc.v:144005.3-144040.6" + wire $0\mul_op__is_32bit$11$next[0:0]$7711 + attribute \src "libresoc.v:143919.3-143920.57" + wire $0\mul_op__is_32bit$11[0:0]$7690 + attribute \src "libresoc.v:143768.7-143768.35" + wire $0\mul_op__is_32bit$11[0:0]$7760 + attribute \src "libresoc.v:144005.3-144040.6" + wire $0\mul_op__is_signed$12$next[0:0]$7712 + attribute \src "libresoc.v:143921.3-143922.59" + wire $0\mul_op__is_signed$12[0:0]$7692 + attribute \src "libresoc.v:143777.7-143777.36" + wire $0\mul_op__is_signed$12[0:0]$7762 + attribute \src "libresoc.v:144005.3-144040.6" + wire $0\mul_op__oe__oe$8$next[0:0]$7713 + attribute \src "libresoc.v:143913.3-143914.51" + wire $0\mul_op__oe__oe$8[0:0]$7684 + attribute \src "libresoc.v:143788.7-143788.32" + wire $0\mul_op__oe__oe$8[0:0]$7764 + attribute \src "libresoc.v:144005.3-144040.6" + wire $0\mul_op__oe__ok$9$next[0:0]$7714 + attribute \src "libresoc.v:143915.3-143916.51" + wire $0\mul_op__oe__ok$9[0:0]$7686 + attribute \src "libresoc.v:143797.7-143797.32" + wire $0\mul_op__oe__ok$9[0:0]$7766 + attribute \src "libresoc.v:144005.3-144040.6" + wire $0\mul_op__rc__ok$7$next[0:0]$7715 + attribute \src "libresoc.v:143911.3-143912.51" + wire $0\mul_op__rc__ok$7[0:0]$7682 + attribute \src "libresoc.v:143806.7-143806.32" + wire $0\mul_op__rc__ok$7[0:0]$7768 + attribute \src "libresoc.v:144005.3-144040.6" + wire $0\mul_op__rc__rc$6$next[0:0]$7716 + attribute \src "libresoc.v:143909.3-143910.51" + wire $0\mul_op__rc__rc$6[0:0]$7680 + attribute \src "libresoc.v:143815.7-143815.32" + wire $0\mul_op__rc__rc$6[0:0]$7770 + attribute \src "libresoc.v:144005.3-144040.6" + wire $0\mul_op__write_cr0$10$next[0:0]$7717 + attribute \src "libresoc.v:143917.3-143918.59" + wire $0\mul_op__write_cr0$10[0:0]$7688 + attribute \src "libresoc.v:143822.7-143822.36" + wire $0\mul_op__write_cr0$10[0:0]$7772 + attribute \src "libresoc.v:143992.3-144004.6" + wire width 2 $0\muxid$1$next[1:0]$7703 + attribute \src "libresoc.v:143925.3-143926.33" + wire width 2 $0\muxid$1[1:0]$7696 + attribute \src "libresoc.v:143831.13-143831.29" + wire width 2 $0\muxid$1[1:0]$7774 + attribute \src "libresoc.v:144067.3-144079.6" + wire $0\neg_res$15$next[0:0]$7743 + attribute \src "libresoc.v:143895.3-143896.39" + wire $0\neg_res$15[0:0]$7667 + attribute \src "libresoc.v:143846.7-143846.26" + wire $0\neg_res$15[0:0]$7776 + attribute \src "libresoc.v:144080.3-144092.6" + wire $0\neg_res32$16$next[0:0]$7746 + attribute \src "libresoc.v:143893.3-143894.43" + wire $0\neg_res32$16[0:0]$7665 + attribute \src "libresoc.v:143855.7-143855.28" + wire $0\neg_res32$16[0:0]$7778 + attribute \src "libresoc.v:144041.3-144053.6" + wire width 129 $0\o$next[128:0]$7737 + attribute \src "libresoc.v:143899.3-143900.19" + wire width 129 $0\o[128:0] + attribute \src "libresoc.v:143974.3-143991.6" + wire $0\r_busy$next[0:0]$7699 + attribute \src "libresoc.v:143927.3-143928.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:144054.3-144066.6" + wire $0\xer_so$14$next[0:0]$7740 + attribute \src "libresoc.v:143897.3-143898.37" + wire $0\xer_so$14[0:0]$7669 + attribute \src "libresoc.v:143887.7-143887.25" + wire $0\xer_so$14[0:0]$7782 + attribute \src "libresoc.v:144005.3-144040.6" + wire width 12 $1\mul_op__fn_unit$3$next[11:0]$7718 + attribute \src "libresoc.v:144005.3-144040.6" + wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$7719 + attribute \src "libresoc.v:144005.3-144040.6" + wire $1\mul_op__imm_data__ok$5$next[0:0]$7720 + attribute \src "libresoc.v:144005.3-144040.6" + wire width 32 $1\mul_op__insn$13$next[31:0]$7721 + attribute \src "libresoc.v:144005.3-144040.6" + wire width 7 $1\mul_op__insn_type$2$next[6:0]$7722 + attribute \src "libresoc.v:144005.3-144040.6" + wire $1\mul_op__is_32bit$11$next[0:0]$7723 + attribute \src "libresoc.v:144005.3-144040.6" + wire $1\mul_op__is_signed$12$next[0:0]$7724 + attribute \src "libresoc.v:144005.3-144040.6" + wire $1\mul_op__oe__oe$8$next[0:0]$7725 + attribute \src "libresoc.v:144005.3-144040.6" + wire $1\mul_op__oe__ok$9$next[0:0]$7726 + attribute \src "libresoc.v:144005.3-144040.6" + wire $1\mul_op__rc__ok$7$next[0:0]$7727 + attribute \src "libresoc.v:144005.3-144040.6" + wire $1\mul_op__rc__rc$6$next[0:0]$7728 + attribute \src "libresoc.v:144005.3-144040.6" + wire $1\mul_op__write_cr0$10$next[0:0]$7729 + attribute \src "libresoc.v:143992.3-144004.6" + wire width 2 $1\muxid$1$next[1:0]$7704 + attribute \src "libresoc.v:144067.3-144079.6" + wire $1\neg_res$15$next[0:0]$7744 + attribute \src "libresoc.v:144080.3-144092.6" + wire $1\neg_res32$16$next[0:0]$7747 + attribute \src "libresoc.v:144041.3-144053.6" + wire width 129 $1\o$next[128:0]$7738 + attribute \src "libresoc.v:143862.15-143862.57" + wire width 129 $1\o[128:0] + attribute \src "libresoc.v:143974.3-143991.6" + wire $1\r_busy$next[0:0]$7700 + attribute \src "libresoc.v:143876.7-143876.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:144054.3-144066.6" + wire $1\xer_so$14$next[0:0]$7741 + attribute \src "libresoc.v:144005.3-144040.6" + wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$7730 + attribute \src "libresoc.v:144005.3-144040.6" + wire $2\mul_op__imm_data__ok$5$next[0:0]$7731 + attribute \src "libresoc.v:144005.3-144040.6" + wire $2\mul_op__oe__oe$8$next[0:0]$7732 + attribute \src "libresoc.v:144005.3-144040.6" + wire $2\mul_op__oe__ok$9$next[0:0]$7733 + attribute \src "libresoc.v:144005.3-144040.6" + wire $2\mul_op__rc__ok$7$next[0:0]$7734 + attribute \src "libresoc.v:144005.3-144040.6" + wire $2\mul_op__rc__rc$6$next[0:0]$7735 + attribute \src "libresoc.v:143974.3-143991.6" + wire $2\r_busy$next[0:0]$7701 + attribute \src "libresoc.v:143892.18-143892.118" + wire $and$libresoc.v:143892$7663_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 41 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:143207.7-143207.15" + wire \initial + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul2_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul2_mul_op__fn_unit$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul2_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul2_mul_op__imm_data__data$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__imm_data__ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul2_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul2_mul_op__insn$29 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul2_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul2_mul_op__insn_type$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__is_32bit$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__is_signed$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__oe__oe$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__oe__ok$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__rc__ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__rc__rc$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__write_cr0$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul2_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul2_muxid$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire \mul2_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire \mul2_neg_res$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire \mul2_neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire \mul2_neg_res32$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \mul2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul2_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul2_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul2_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul2_xer_so$30 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 6 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 26 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_op__fn_unit$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__data$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 27 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__data$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 16 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 36 \mul_op__insn$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$48 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 25 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_32bit$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_32bit$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_signed$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_signed$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__oe$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__ok$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$45 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 24 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$36 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 23 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 22 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire input 20 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire output 39 \neg_res$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire \neg_res$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire \neg_res$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire input 21 \neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire output 40 \neg_res32$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire \neg_res32$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire \neg_res32$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 output 37 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \o$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 17 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 18 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 19 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 38 \xer_so$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$50 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$libresoc.v:143892$7663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$33 + connect \B \p_ready_o + connect \Y $and$libresoc.v:143892$7663_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:143929.8-143965.4" + cell \mul2 \mul2 + connect \mul_op__fn_unit \mul2_mul_op__fn_unit + connect \mul_op__fn_unit$3 \mul2_mul_op__fn_unit$19 + connect \mul_op__imm_data__data \mul2_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \mul2_mul_op__imm_data__data$20 + connect \mul_op__imm_data__ok \mul2_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \mul2_mul_op__imm_data__ok$21 + connect \mul_op__insn \mul2_mul_op__insn + connect \mul_op__insn$13 \mul2_mul_op__insn$29 + connect \mul_op__insn_type \mul2_mul_op__insn_type + connect \mul_op__insn_type$2 \mul2_mul_op__insn_type$18 + connect \mul_op__is_32bit \mul2_mul_op__is_32bit + connect \mul_op__is_32bit$11 \mul2_mul_op__is_32bit$27 + connect \mul_op__is_signed \mul2_mul_op__is_signed + connect \mul_op__is_signed$12 \mul2_mul_op__is_signed$28 + connect \mul_op__oe__oe \mul2_mul_op__oe__oe + connect \mul_op__oe__oe$8 \mul2_mul_op__oe__oe$24 + connect \mul_op__oe__ok \mul2_mul_op__oe__ok + connect \mul_op__oe__ok$9 \mul2_mul_op__oe__ok$25 + connect \mul_op__rc__ok \mul2_mul_op__rc__ok + connect \mul_op__rc__ok$7 \mul2_mul_op__rc__ok$23 + connect \mul_op__rc__rc \mul2_mul_op__rc__rc + connect \mul_op__rc__rc$6 \mul2_mul_op__rc__rc$22 + connect \mul_op__write_cr0 \mul2_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \mul2_mul_op__write_cr0$26 + connect \muxid \mul2_muxid + connect \muxid$1 \mul2_muxid$17 + connect \neg_res \mul2_neg_res + connect \neg_res$15 \mul2_neg_res$31 + connect \neg_res32 \mul2_neg_res32 + connect \neg_res32$16 \mul2_neg_res32$32 + connect \o \mul2_o + connect \ra \mul2_ra + connect \rb \mul2_rb + connect \xer_so \mul2_xer_so + connect \xer_so$14 \mul2_xer_so$30 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:143966.10-143969.4" + cell \n$97 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:143970.10-143973.4" + cell \p$96 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:143207.7-143207.20" + process $proc$libresoc.v:143207$7748 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:143488.14-143488.43" + process $proc$libresoc.v:143488$7749 + assign { } { } + assign $0\mul_op__fn_unit$3[11:0]$7750 12'000000000000 + sync always + sync init + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[11:0]$7750 + end + attribute \src "libresoc.v:143512.14-143512.63" + process $proc$libresoc.v:143512$7751 + assign { } { } + assign $0\mul_op__imm_data__data$4[63:0]$7752 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7752 + end + attribute \src "libresoc.v:143521.7-143521.38" + process $proc$libresoc.v:143521$7753 + assign { } { } + assign $0\mul_op__imm_data__ok$5[0:0]$7754 1'0 + sync always + sync init + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$7754 + end + attribute \src "libresoc.v:143528.14-143528.39" + process $proc$libresoc.v:143528$7755 + assign { } { } + assign $0\mul_op__insn$13[31:0]$7756 0 + sync always + sync init + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7756 + end + attribute \src "libresoc.v:143685.13-143685.42" + process $proc$libresoc.v:143685$7757 + assign { } { } + assign $0\mul_op__insn_type$2[6:0]$7758 7'0000000 + sync always + sync init + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7758 + end + attribute \src "libresoc.v:143768.7-143768.35" + process $proc$libresoc.v:143768$7759 + assign { } { } + assign $0\mul_op__is_32bit$11[0:0]$7760 1'0 + sync always + sync init + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$7760 + end + attribute \src "libresoc.v:143777.7-143777.36" + process $proc$libresoc.v:143777$7761 + assign { } { } + assign $0\mul_op__is_signed$12[0:0]$7762 1'0 + sync always + sync init + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7762 + end + attribute \src "libresoc.v:143788.7-143788.32" + process $proc$libresoc.v:143788$7763 + assign { } { } + assign $0\mul_op__oe__oe$8[0:0]$7764 1'0 + sync always + sync init + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$7764 + end + attribute \src "libresoc.v:143797.7-143797.32" + process $proc$libresoc.v:143797$7765 + assign { } { } + assign $0\mul_op__oe__ok$9[0:0]$7766 1'0 + sync always + sync init + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$7766 + end + attribute \src "libresoc.v:143806.7-143806.32" + process $proc$libresoc.v:143806$7767 + assign { } { } + assign $0\mul_op__rc__ok$7[0:0]$7768 1'0 + sync always + sync init + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$7768 + end + attribute \src "libresoc.v:143815.7-143815.32" + process $proc$libresoc.v:143815$7769 + assign { } { } + assign $0\mul_op__rc__rc$6[0:0]$7770 1'0 + sync always + sync init + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$7770 + end + attribute \src "libresoc.v:143822.7-143822.36" + process $proc$libresoc.v:143822$7771 + assign { } { } + assign $0\mul_op__write_cr0$10[0:0]$7772 1'0 + sync always + sync init + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$7772 + end + attribute \src "libresoc.v:143831.13-143831.29" + process $proc$libresoc.v:143831$7773 + assign { } { } + assign $0\muxid$1[1:0]$7774 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$7774 + end + attribute \src "libresoc.v:143846.7-143846.26" + process $proc$libresoc.v:143846$7775 + assign { } { } + assign $0\neg_res$15[0:0]$7776 1'0 + sync always + sync init + update \neg_res$15 $0\neg_res$15[0:0]$7776 + end + attribute \src "libresoc.v:143855.7-143855.28" + process $proc$libresoc.v:143855$7777 + assign { } { } + assign $0\neg_res32$16[0:0]$7778 1'0 + sync always + sync init + update \neg_res32$16 $0\neg_res32$16[0:0]$7778 + end + attribute \src "libresoc.v:143862.15-143862.57" + process $proc$libresoc.v:143862$7779 + assign { } { } + assign $1\o[128:0] 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[128:0] + end + attribute \src "libresoc.v:143876.7-143876.20" + process $proc$libresoc.v:143876$7780 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:143887.7-143887.25" + process $proc$libresoc.v:143887$7781 + assign { } { } + assign $0\xer_so$14[0:0]$7782 1'0 + sync always + sync init + update \xer_so$14 $0\xer_so$14[0:0]$7782 + end + attribute \src "libresoc.v:143893.3-143894.43" + process $proc$libresoc.v:143893$7664 + assign { } { } + assign $0\neg_res32$16[0:0]$7665 \neg_res32$16$next + sync posedge \coresync_clk + update \neg_res32$16 $0\neg_res32$16[0:0]$7665 + end + attribute \src "libresoc.v:143895.3-143896.39" + process $proc$libresoc.v:143895$7666 + assign { } { } + assign $0\neg_res$15[0:0]$7667 \neg_res$15$next + sync posedge \coresync_clk + update \neg_res$15 $0\neg_res$15[0:0]$7667 + end + attribute \src "libresoc.v:143897.3-143898.37" + process $proc$libresoc.v:143897$7668 + assign { } { } + assign $0\xer_so$14[0:0]$7669 \xer_so$14$next + sync posedge \coresync_clk + update \xer_so$14 $0\xer_so$14[0:0]$7669 + end + attribute \src "libresoc.v:143899.3-143900.19" + process $proc$libresoc.v:143899$7670 + assign { } { } + assign $0\o[128:0] \o$next + sync posedge \coresync_clk + update \o $0\o[128:0] + end + attribute \src "libresoc.v:143901.3-143902.57" + process $proc$libresoc.v:143901$7671 + assign { } { } + assign $0\mul_op__insn_type$2[6:0]$7672 \mul_op__insn_type$2$next + sync posedge \coresync_clk + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7672 + end + attribute \src "libresoc.v:143903.3-143904.53" + process $proc$libresoc.v:143903$7673 + assign { } { } + assign $0\mul_op__fn_unit$3[11:0]$7674 \mul_op__fn_unit$3$next + sync posedge \coresync_clk + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[11:0]$7674 + end + attribute \src "libresoc.v:143905.3-143906.67" + process $proc$libresoc.v:143905$7675 + assign { } { } + assign $0\mul_op__imm_data__data$4[63:0]$7676 \mul_op__imm_data__data$4$next + sync posedge \coresync_clk + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7676 + end + attribute \src "libresoc.v:143907.3-143908.63" + process $proc$libresoc.v:143907$7677 + assign { } { } + assign $0\mul_op__imm_data__ok$5[0:0]$7678 \mul_op__imm_data__ok$5$next + sync posedge \coresync_clk + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$7678 + end + attribute \src "libresoc.v:143909.3-143910.51" + process $proc$libresoc.v:143909$7679 + assign { } { } + assign $0\mul_op__rc__rc$6[0:0]$7680 \mul_op__rc__rc$6$next + sync posedge \coresync_clk + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$7680 + end + attribute \src "libresoc.v:143911.3-143912.51" + process $proc$libresoc.v:143911$7681 + assign { } { } + assign $0\mul_op__rc__ok$7[0:0]$7682 \mul_op__rc__ok$7$next + sync posedge \coresync_clk + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$7682 + end + attribute \src "libresoc.v:143913.3-143914.51" + process $proc$libresoc.v:143913$7683 + assign { } { } + assign $0\mul_op__oe__oe$8[0:0]$7684 \mul_op__oe__oe$8$next + sync posedge \coresync_clk + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$7684 + end + attribute \src "libresoc.v:143915.3-143916.51" + process $proc$libresoc.v:143915$7685 + assign { } { } + assign $0\mul_op__oe__ok$9[0:0]$7686 \mul_op__oe__ok$9$next + sync posedge \coresync_clk + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$7686 + end + attribute \src "libresoc.v:143917.3-143918.59" + process $proc$libresoc.v:143917$7687 + assign { } { } + assign $0\mul_op__write_cr0$10[0:0]$7688 \mul_op__write_cr0$10$next + sync posedge \coresync_clk + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$7688 + end + attribute \src "libresoc.v:143919.3-143920.57" + process $proc$libresoc.v:143919$7689 + assign { } { } + assign $0\mul_op__is_32bit$11[0:0]$7690 \mul_op__is_32bit$11$next + sync posedge \coresync_clk + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$7690 + end + attribute \src "libresoc.v:143921.3-143922.59" + process $proc$libresoc.v:143921$7691 + assign { } { } + assign $0\mul_op__is_signed$12[0:0]$7692 \mul_op__is_signed$12$next + sync posedge \coresync_clk + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7692 + end + attribute \src "libresoc.v:143923.3-143924.49" + process $proc$libresoc.v:143923$7693 + assign { } { } + assign $0\mul_op__insn$13[31:0]$7694 \mul_op__insn$13$next + sync posedge \coresync_clk + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7694 + end + attribute \src "libresoc.v:143925.3-143926.33" + process $proc$libresoc.v:143925$7695 + assign { } { } + assign $0\muxid$1[1:0]$7696 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$7696 + end + attribute \src "libresoc.v:143927.3-143928.29" + process $proc$libresoc.v:143927$7697 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:143974.3-143991.6" + process $proc$libresoc.v:143974$7698 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$7699 $2\r_busy$next[0:0]$7701 + attribute \src "libresoc.v:143975.5-143975.29" + switch \initial + attribute \src "libresoc.v:143975.9-143975.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$7700 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$7700 1'0 + case + assign $1\r_busy$next[0:0]$7700 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$7701 1'0 + case + assign $2\r_busy$next[0:0]$7701 $1\r_busy$next[0:0]$7700 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$7699 + end + attribute \src "libresoc.v:143992.3-144004.6" + process $proc$libresoc.v:143992$7702 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$7703 $1\muxid$1$next[1:0]$7704 + attribute \src "libresoc.v:143993.5-143993.29" + switch \initial + attribute \src "libresoc.v:143993.9-143993.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$7704 \muxid$36 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$7704 \muxid$36 + case + assign $1\muxid$1$next[1:0]$7704 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$7703 + end + attribute \src "libresoc.v:144005.3-144040.6" + process $proc$libresoc.v:144005$7705 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mul_op__fn_unit$3$next[11:0]$7706 $1\mul_op__fn_unit$3$next[11:0]$7718 + assign { } { } + assign { } { } + assign $0\mul_op__insn$13$next[31:0]$7709 $1\mul_op__insn$13$next[31:0]$7721 + assign $0\mul_op__insn_type$2$next[6:0]$7710 $1\mul_op__insn_type$2$next[6:0]$7722 + assign $0\mul_op__is_32bit$11$next[0:0]$7711 $1\mul_op__is_32bit$11$next[0:0]$7723 + assign $0\mul_op__is_signed$12$next[0:0]$7712 $1\mul_op__is_signed$12$next[0:0]$7724 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mul_op__write_cr0$10$next[0:0]$7717 $1\mul_op__write_cr0$10$next[0:0]$7729 + assign $0\mul_op__imm_data__data$4$next[63:0]$7707 $2\mul_op__imm_data__data$4$next[63:0]$7730 + assign $0\mul_op__imm_data__ok$5$next[0:0]$7708 $2\mul_op__imm_data__ok$5$next[0:0]$7731 + assign $0\mul_op__oe__oe$8$next[0:0]$7713 $2\mul_op__oe__oe$8$next[0:0]$7732 + assign $0\mul_op__oe__ok$9$next[0:0]$7714 $2\mul_op__oe__ok$9$next[0:0]$7733 + assign $0\mul_op__rc__ok$7$next[0:0]$7715 $2\mul_op__rc__ok$7$next[0:0]$7734 + assign $0\mul_op__rc__rc$6$next[0:0]$7716 $2\mul_op__rc__rc$6$next[0:0]$7735 + attribute \src "libresoc.v:144006.5-144006.29" + switch \initial + attribute \src "libresoc.v:144006.9-144006.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\mul_op__insn$13$next[31:0]$7721 $1\mul_op__is_signed$12$next[0:0]$7724 $1\mul_op__is_32bit$11$next[0:0]$7723 $1\mul_op__write_cr0$10$next[0:0]$7729 $1\mul_op__oe__ok$9$next[0:0]$7726 $1\mul_op__oe__oe$8$next[0:0]$7725 $1\mul_op__rc__ok$7$next[0:0]$7727 $1\mul_op__rc__rc$6$next[0:0]$7728 $1\mul_op__imm_data__ok$5$next[0:0]$7720 $1\mul_op__imm_data__data$4$next[63:0]$7719 $1\mul_op__fn_unit$3$next[11:0]$7718 $1\mul_op__insn_type$2$next[6:0]$7722 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\mul_op__insn$13$next[31:0]$7721 $1\mul_op__is_signed$12$next[0:0]$7724 $1\mul_op__is_32bit$11$next[0:0]$7723 $1\mul_op__write_cr0$10$next[0:0]$7729 $1\mul_op__oe__ok$9$next[0:0]$7726 $1\mul_op__oe__oe$8$next[0:0]$7725 $1\mul_op__rc__ok$7$next[0:0]$7727 $1\mul_op__rc__rc$6$next[0:0]$7728 $1\mul_op__imm_data__ok$5$next[0:0]$7720 $1\mul_op__imm_data__data$4$next[63:0]$7719 $1\mul_op__fn_unit$3$next[11:0]$7718 $1\mul_op__insn_type$2$next[6:0]$7722 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } + case + assign $1\mul_op__fn_unit$3$next[11:0]$7718 \mul_op__fn_unit$3 + assign $1\mul_op__imm_data__data$4$next[63:0]$7719 \mul_op__imm_data__data$4 + assign $1\mul_op__imm_data__ok$5$next[0:0]$7720 \mul_op__imm_data__ok$5 + assign $1\mul_op__insn$13$next[31:0]$7721 \mul_op__insn$13 + assign $1\mul_op__insn_type$2$next[6:0]$7722 \mul_op__insn_type$2 + assign $1\mul_op__is_32bit$11$next[0:0]$7723 \mul_op__is_32bit$11 + assign $1\mul_op__is_signed$12$next[0:0]$7724 \mul_op__is_signed$12 + assign $1\mul_op__oe__oe$8$next[0:0]$7725 \mul_op__oe__oe$8 + assign $1\mul_op__oe__ok$9$next[0:0]$7726 \mul_op__oe__ok$9 + assign $1\mul_op__rc__ok$7$next[0:0]$7727 \mul_op__rc__ok$7 + assign $1\mul_op__rc__rc$6$next[0:0]$7728 \mul_op__rc__rc$6 + assign $1\mul_op__write_cr0$10$next[0:0]$7729 \mul_op__write_cr0$10 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\mul_op__imm_data__data$4$next[63:0]$7730 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$5$next[0:0]$7731 1'0 + assign $2\mul_op__rc__rc$6$next[0:0]$7735 1'0 + assign $2\mul_op__rc__ok$7$next[0:0]$7734 1'0 + assign $2\mul_op__oe__oe$8$next[0:0]$7732 1'0 + assign $2\mul_op__oe__ok$9$next[0:0]$7733 1'0 + case + assign $2\mul_op__imm_data__data$4$next[63:0]$7730 $1\mul_op__imm_data__data$4$next[63:0]$7719 + assign $2\mul_op__imm_data__ok$5$next[0:0]$7731 $1\mul_op__imm_data__ok$5$next[0:0]$7720 + assign $2\mul_op__oe__oe$8$next[0:0]$7732 $1\mul_op__oe__oe$8$next[0:0]$7725 + assign $2\mul_op__oe__ok$9$next[0:0]$7733 $1\mul_op__oe__ok$9$next[0:0]$7726 + assign $2\mul_op__rc__ok$7$next[0:0]$7734 $1\mul_op__rc__ok$7$next[0:0]$7727 + assign $2\mul_op__rc__rc$6$next[0:0]$7735 $1\mul_op__rc__rc$6$next[0:0]$7728 + end + sync always + update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[11:0]$7706 + update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$7707 + update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$7708 + update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$7709 + update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$7710 + update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$7711 + update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$7712 + update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$7713 + update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$7714 + update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$7715 + update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$7716 + update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$7717 + end + attribute \src "libresoc.v:144041.3-144053.6" + process $proc$libresoc.v:144041$7736 + assign { } { } + assign { } { } + assign $0\o$next[128:0]$7737 $1\o$next[128:0]$7738 + attribute \src "libresoc.v:144042.5-144042.29" + switch \initial + attribute \src "libresoc.v:144042.9-144042.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\o$next[128:0]$7738 \o$49 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\o$next[128:0]$7738 \o$49 + case + assign $1\o$next[128:0]$7738 \o + end + sync always + update \o$next $0\o$next[128:0]$7737 + end + attribute \src "libresoc.v:144054.3-144066.6" + process $proc$libresoc.v:144054$7739 + assign { } { } + assign { } { } + assign $0\xer_so$14$next[0:0]$7740 $1\xer_so$14$next[0:0]$7741 + attribute \src "libresoc.v:144055.5-144055.29" + switch \initial + attribute \src "libresoc.v:144055.9-144055.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\xer_so$14$next[0:0]$7741 \xer_so$50 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\xer_so$14$next[0:0]$7741 \xer_so$50 + case + assign $1\xer_so$14$next[0:0]$7741 \xer_so$14 + end + sync always + update \xer_so$14$next $0\xer_so$14$next[0:0]$7740 + end + attribute \src "libresoc.v:144067.3-144079.6" + process $proc$libresoc.v:144067$7742 + assign { } { } + assign { } { } + assign $0\neg_res$15$next[0:0]$7743 $1\neg_res$15$next[0:0]$7744 + attribute \src "libresoc.v:144068.5-144068.29" + switch \initial + attribute \src "libresoc.v:144068.9-144068.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\neg_res$15$next[0:0]$7744 \neg_res$51 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\neg_res$15$next[0:0]$7744 \neg_res$51 + case + assign $1\neg_res$15$next[0:0]$7744 \neg_res$15 + end + sync always + update \neg_res$15$next $0\neg_res$15$next[0:0]$7743 + end + attribute \src "libresoc.v:144080.3-144092.6" + process $proc$libresoc.v:144080$7745 + assign { } { } + assign { } { } + assign $0\neg_res32$16$next[0:0]$7746 $1\neg_res32$16$next[0:0]$7747 + attribute \src "libresoc.v:144081.5-144081.29" + switch \initial + attribute \src "libresoc.v:144081.9-144081.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\neg_res32$16$next[0:0]$7747 \neg_res32$52 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\neg_res32$16$next[0:0]$7747 \neg_res32$52 + case + assign $1\neg_res32$16$next[0:0]$7747 \neg_res32$16 + end + sync always + update \neg_res32$16$next $0\neg_res32$16$next[0:0]$7746 + end + connect \$34 $and$libresoc.v:143892$7663_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect \neg_res32$52 \mul2_neg_res32$32 + connect \neg_res$51 \mul2_neg_res$31 + connect \xer_so$50 \mul2_xer_so$30 + connect \o$49 \mul2_o + connect { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } { \mul2_mul_op__insn$29 \mul2_mul_op__is_signed$28 \mul2_mul_op__is_32bit$27 \mul2_mul_op__write_cr0$26 \mul2_mul_op__oe__ok$25 \mul2_mul_op__oe__oe$24 \mul2_mul_op__rc__ok$23 \mul2_mul_op__rc__rc$22 \mul2_mul_op__imm_data__ok$21 \mul2_mul_op__imm_data__data$20 \mul2_mul_op__fn_unit$19 \mul2_mul_op__insn_type$18 } + connect \muxid$36 \mul2_muxid$17 + connect \p_valid_i_p_ready_o \$34 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$33 \p_valid_i + connect \mul2_neg_res32 \neg_res32 + connect \mul2_neg_res \neg_res + connect \mul2_xer_so \xer_so + connect \mul2_rb \rb + connect \mul2_ra \ra + connect { \mul2_mul_op__insn \mul2_mul_op__is_signed \mul2_mul_op__is_32bit \mul2_mul_op__write_cr0 \mul2_mul_op__oe__ok \mul2_mul_op__oe__oe \mul2_mul_op__rc__ok \mul2_mul_op__rc__rc \mul2_mul_op__imm_data__ok \mul2_mul_op__imm_data__data \mul2_mul_op__fn_unit \mul2_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \mul2_muxid \muxid +end +attribute \src "libresoc.v:144115.1-145390.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3" +attribute \generator "nMigen" +module \mul_pipe3 + attribute \src "libresoc.v:145308.3-145326.6" + wire width 4 $0\cr_a$next[3:0]$7866 + attribute \src "libresoc.v:145100.3-145101.25" + wire width 4 $0\cr_a[3:0] + attribute \src "libresoc.v:145308.3-145326.6" + wire $0\cr_a_ok$next[0:0]$7867 + attribute \src "libresoc.v:145102.3-145103.31" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:144116.7-144116.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:145253.3-145288.6" + wire width 12 $0\mul_op__fn_unit$3$next[11:0]$7829 + attribute \src "libresoc.v:145110.3-145111.53" + wire width 12 $0\mul_op__fn_unit$3[11:0]$7797 + attribute \src "libresoc.v:144417.14-144417.43" + wire width 12 $0\mul_op__fn_unit$3[11:0]$7887 + attribute \src "libresoc.v:145253.3-145288.6" + wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$7830 + attribute \src "libresoc.v:145112.3-145113.67" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$7799 + attribute \src "libresoc.v:144439.14-144439.63" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$7889 + attribute \src "libresoc.v:145253.3-145288.6" + wire $0\mul_op__imm_data__ok$5$next[0:0]$7831 + attribute \src "libresoc.v:145114.3-145115.63" + wire $0\mul_op__imm_data__ok$5[0:0]$7801 + attribute \src "libresoc.v:144448.7-144448.38" + wire $0\mul_op__imm_data__ok$5[0:0]$7891 + attribute \src "libresoc.v:145253.3-145288.6" + wire width 32 $0\mul_op__insn$13$next[31:0]$7832 + attribute \src "libresoc.v:145130.3-145131.49" + wire width 32 $0\mul_op__insn$13[31:0]$7817 + attribute \src "libresoc.v:144457.14-144457.39" + wire width 32 $0\mul_op__insn$13[31:0]$7893 + attribute \src "libresoc.v:145253.3-145288.6" + wire width 7 $0\mul_op__insn_type$2$next[6:0]$7833 + attribute \src "libresoc.v:145108.3-145109.57" + wire width 7 $0\mul_op__insn_type$2[6:0]$7795 + attribute \src "libresoc.v:144614.13-144614.42" + wire width 7 $0\mul_op__insn_type$2[6:0]$7895 + attribute \src "libresoc.v:145253.3-145288.6" + wire $0\mul_op__is_32bit$11$next[0:0]$7834 + attribute \src "libresoc.v:145126.3-145127.57" + wire $0\mul_op__is_32bit$11[0:0]$7813 + attribute \src "libresoc.v:144697.7-144697.35" + wire $0\mul_op__is_32bit$11[0:0]$7897 + attribute \src "libresoc.v:145253.3-145288.6" + wire $0\mul_op__is_signed$12$next[0:0]$7835 + attribute \src "libresoc.v:145128.3-145129.59" + wire $0\mul_op__is_signed$12[0:0]$7815 + attribute \src "libresoc.v:144706.7-144706.36" + wire $0\mul_op__is_signed$12[0:0]$7899 + attribute \src "libresoc.v:145253.3-145288.6" + wire $0\mul_op__oe__oe$8$next[0:0]$7836 + attribute \src "libresoc.v:145120.3-145121.51" + wire $0\mul_op__oe__oe$8[0:0]$7807 + attribute \src "libresoc.v:144717.7-144717.32" + wire $0\mul_op__oe__oe$8[0:0]$7901 + attribute \src "libresoc.v:145253.3-145288.6" + wire $0\mul_op__oe__ok$9$next[0:0]$7837 + attribute \src "libresoc.v:145122.3-145123.51" + wire $0\mul_op__oe__ok$9[0:0]$7809 + attribute \src "libresoc.v:144726.7-144726.32" + wire $0\mul_op__oe__ok$9[0:0]$7903 + attribute \src "libresoc.v:145253.3-145288.6" + wire $0\mul_op__rc__ok$7$next[0:0]$7838 + attribute \src "libresoc.v:145118.3-145119.51" + wire $0\mul_op__rc__ok$7[0:0]$7805 + attribute \src "libresoc.v:144735.7-144735.32" + wire $0\mul_op__rc__ok$7[0:0]$7905 + attribute \src "libresoc.v:145253.3-145288.6" + wire $0\mul_op__rc__rc$6$next[0:0]$7839 + attribute \src "libresoc.v:145116.3-145117.51" + wire $0\mul_op__rc__rc$6[0:0]$7803 + attribute \src "libresoc.v:144742.7-144742.32" + wire $0\mul_op__rc__rc$6[0:0]$7907 + attribute \src "libresoc.v:145253.3-145288.6" + wire $0\mul_op__write_cr0$10$next[0:0]$7840 + attribute \src "libresoc.v:145124.3-145125.59" + wire $0\mul_op__write_cr0$10[0:0]$7811 + attribute \src "libresoc.v:144751.7-144751.36" + wire $0\mul_op__write_cr0$10[0:0]$7909 + attribute \src "libresoc.v:145240.3-145252.6" + wire width 2 $0\muxid$1$next[1:0]$7826 + attribute \src "libresoc.v:145132.3-145133.33" + wire width 2 $0\muxid$1[1:0]$7819 + attribute \src "libresoc.v:144760.13-144760.29" + wire width 2 $0\muxid$1[1:0]$7911 + attribute \src "libresoc.v:145289.3-145307.6" + wire width 64 $0\o$14$next[63:0]$7861 + attribute \src "libresoc.v:145104.3-145105.27" + wire width 64 $0\o$14[63:0]$7792 + attribute \src "libresoc.v:144781.14-144781.43" + wire width 64 $0\o$14[63:0]$7913 + attribute \src "libresoc.v:145289.3-145307.6" + wire $0\o_ok$next[0:0]$7860 + attribute \src "libresoc.v:145106.3-145107.25" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:145222.3-145239.6" + wire $0\r_busy$next[0:0]$7822 + attribute \src "libresoc.v:145134.3-145135.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:145327.3-145345.6" + wire width 2 $0\xer_ov$next[1:0]$7872 + attribute \src "libresoc.v:145096.3-145097.29" + wire width 2 $0\xer_ov[1:0] + attribute \src "libresoc.v:145327.3-145345.6" + wire $0\xer_ov_ok$next[0:0]$7873 + attribute \src "libresoc.v:145098.3-145099.35" + wire $0\xer_ov_ok[0:0] + attribute \src "libresoc.v:145346.3-145364.6" + wire $0\xer_so$15$next[0:0]$7879 + attribute \src "libresoc.v:145092.3-145093.37" + wire $0\xer_so$15[0:0]$7785 + attribute \src "libresoc.v:145077.7-145077.25" + wire $0\xer_so$15[0:0]$7919 + attribute \src "libresoc.v:145346.3-145364.6" + wire $0\xer_so_ok$next[0:0]$7878 + attribute \src "libresoc.v:145094.3-145095.35" + wire $0\xer_so_ok[0:0] + attribute \src "libresoc.v:145308.3-145326.6" + wire width 4 $1\cr_a$next[3:0]$7868 + attribute \src "libresoc.v:144125.13-144125.24" + wire width 4 $1\cr_a[3:0] + attribute \src "libresoc.v:145308.3-145326.6" + wire $1\cr_a_ok$next[0:0]$7869 + attribute \src "libresoc.v:144134.7-144134.21" + wire $1\cr_a_ok[0:0] + attribute \src "libresoc.v:145253.3-145288.6" + wire width 12 $1\mul_op__fn_unit$3$next[11:0]$7841 + attribute \src "libresoc.v:145253.3-145288.6" + wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$7842 + attribute \src "libresoc.v:145253.3-145288.6" + wire $1\mul_op__imm_data__ok$5$next[0:0]$7843 + attribute \src "libresoc.v:145253.3-145288.6" + wire width 32 $1\mul_op__insn$13$next[31:0]$7844 + attribute \src "libresoc.v:145253.3-145288.6" + wire width 7 $1\mul_op__insn_type$2$next[6:0]$7845 + attribute \src "libresoc.v:145253.3-145288.6" + wire $1\mul_op__is_32bit$11$next[0:0]$7846 + attribute \src "libresoc.v:145253.3-145288.6" + wire $1\mul_op__is_signed$12$next[0:0]$7847 + attribute \src "libresoc.v:145253.3-145288.6" + wire $1\mul_op__oe__oe$8$next[0:0]$7848 + attribute \src "libresoc.v:145253.3-145288.6" + wire $1\mul_op__oe__ok$9$next[0:0]$7849 + attribute \src "libresoc.v:145253.3-145288.6" + wire $1\mul_op__rc__ok$7$next[0:0]$7850 + attribute \src "libresoc.v:145253.3-145288.6" + wire $1\mul_op__rc__rc$6$next[0:0]$7851 + attribute \src "libresoc.v:145253.3-145288.6" + wire $1\mul_op__write_cr0$10$next[0:0]$7852 + attribute \src "libresoc.v:145240.3-145252.6" + wire width 2 $1\muxid$1$next[1:0]$7827 + attribute \src "libresoc.v:145289.3-145307.6" + wire width 64 $1\o$14$next[63:0]$7863 + attribute \src "libresoc.v:145289.3-145307.6" + wire $1\o_ok$next[0:0]$7862 + attribute \src "libresoc.v:144788.7-144788.18" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:145222.3-145239.6" + wire $1\r_busy$next[0:0]$7823 + attribute \src "libresoc.v:145054.7-145054.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:145327.3-145345.6" + wire width 2 $1\xer_ov$next[1:0]$7874 + attribute \src "libresoc.v:145059.13-145059.26" + wire width 2 $1\xer_ov[1:0] + attribute \src "libresoc.v:145327.3-145345.6" + wire $1\xer_ov_ok$next[0:0]$7875 + attribute \src "libresoc.v:145066.7-145066.23" + wire $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:145346.3-145364.6" + wire $1\xer_so$15$next[0:0]$7881 + attribute \src "libresoc.v:145346.3-145364.6" + wire $1\xer_so_ok$next[0:0]$7880 + attribute \src "libresoc.v:145084.7-145084.23" + wire $1\xer_so_ok[0:0] + attribute \src "libresoc.v:145308.3-145326.6" + wire $2\cr_a_ok$next[0:0]$7870 + attribute \src "libresoc.v:145253.3-145288.6" + wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$7853 + attribute \src "libresoc.v:145253.3-145288.6" + wire $2\mul_op__imm_data__ok$5$next[0:0]$7854 + attribute \src "libresoc.v:145253.3-145288.6" + wire $2\mul_op__oe__oe$8$next[0:0]$7855 + attribute \src "libresoc.v:145253.3-145288.6" + wire $2\mul_op__oe__ok$9$next[0:0]$7856 + attribute \src "libresoc.v:145253.3-145288.6" + wire $2\mul_op__rc__ok$7$next[0:0]$7857 + attribute \src "libresoc.v:145253.3-145288.6" + wire $2\mul_op__rc__rc$6$next[0:0]$7858 + attribute \src "libresoc.v:145289.3-145307.6" + wire $2\o_ok$next[0:0]$7864 + attribute \src "libresoc.v:145222.3-145239.6" + wire $2\r_busy$next[0:0]$7824 + attribute \src "libresoc.v:145327.3-145345.6" + wire $2\xer_ov_ok$next[0:0]$7876 + attribute \src "libresoc.v:145346.3-145364.6" + wire $2\xer_so_ok$next[0:0]$7882 + attribute \src "libresoc.v:145091.18-145091.118" + wire $and$libresoc.v:145091$7783_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 44 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 38 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 39 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$next + attribute \src "libresoc.v:144116.7-144116.15" + wire \initial + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul3_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul3_mul_op__fn_unit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul3_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul3_mul_op__imm_data__data$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__imm_data__ok$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul3_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul3_mul_op__insn$28 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul3_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul3_mul_op__insn_type$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__is_32bit$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__is_signed$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__oe__oe$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__oe__ok$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__rc__ok$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__rc__rc$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__write_cr0$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul3_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul3_muxid$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire \mul3_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \mul3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \mul3_o$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \mul3_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \mul3_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \mul3_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul3_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \mul3_xer_so$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \mul3_xer_so_ok + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 6 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 25 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_op__fn_unit$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 26 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__data$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__data$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 16 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 35 \mul_op__insn$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$70 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 24 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_32bit$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_32bit$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_signed$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_signed$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__oe$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__ok$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$67 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 23 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$58 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 22 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 21 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire input 19 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire input 20 \neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire \neg_res32$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 input 17 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 36 \o$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 37 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_cr_a_ok + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \output_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \output_mul_op__fn_unit$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_mul_op__imm_data__data$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__imm_data__ok$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_mul_op__insn$43 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_mul_op__insn_type$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__is_32bit$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__is_signed$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__oe__oe$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__oe__ok$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__rc__ok$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__rc__rc$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__write_cr0$40 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_muxid$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ov$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$55 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 40 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 41 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 18 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 42 \xer_so$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 43 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$libresoc.v:145091$7783 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$55 + connect \B \p_ready_o + connect \Y $and$libresoc.v:145091$7783_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:145136.8-145172.4" + cell \mul3 \mul3 + connect \mul_op__fn_unit \mul3_mul_op__fn_unit + connect \mul_op__fn_unit$3 \mul3_mul_op__fn_unit$18 + connect \mul_op__imm_data__data \mul3_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \mul3_mul_op__imm_data__data$19 + connect \mul_op__imm_data__ok \mul3_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \mul3_mul_op__imm_data__ok$20 + connect \mul_op__insn \mul3_mul_op__insn + connect \mul_op__insn$13 \mul3_mul_op__insn$28 + connect \mul_op__insn_type \mul3_mul_op__insn_type + connect \mul_op__insn_type$2 \mul3_mul_op__insn_type$17 + connect \mul_op__is_32bit \mul3_mul_op__is_32bit + connect \mul_op__is_32bit$11 \mul3_mul_op__is_32bit$26 + connect \mul_op__is_signed \mul3_mul_op__is_signed + connect \mul_op__is_signed$12 \mul3_mul_op__is_signed$27 + connect \mul_op__oe__oe \mul3_mul_op__oe__oe + connect \mul_op__oe__oe$8 \mul3_mul_op__oe__oe$23 + connect \mul_op__oe__ok \mul3_mul_op__oe__ok + connect \mul_op__oe__ok$9 \mul3_mul_op__oe__ok$24 + connect \mul_op__rc__ok \mul3_mul_op__rc__ok + connect \mul_op__rc__ok$7 \mul3_mul_op__rc__ok$22 + connect \mul_op__rc__rc \mul3_mul_op__rc__rc + connect \mul_op__rc__rc$6 \mul3_mul_op__rc__rc$21 + connect \mul_op__write_cr0 \mul3_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \mul3_mul_op__write_cr0$25 + connect \muxid \mul3_muxid + connect \muxid$1 \mul3_muxid$16 + connect \neg_res \mul3_neg_res + connect \o \mul3_o + connect \o$14 \mul3_o$29 + connect \o_ok \mul3_o_ok + connect \xer_ov \mul3_xer_ov + connect \xer_ov_ok \mul3_xer_ov_ok + connect \xer_so \mul3_xer_so + connect \xer_so$15 \mul3_xer_so$30 + connect \xer_so_ok \mul3_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:145173.10-145176.4" + cell \n$99 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:145177.16-145217.4" + cell \output$100 \output + connect \cr_a \output_cr_a + connect \cr_a$16 \output_cr_a$46 + connect \cr_a_ok \output_cr_a_ok + connect \mul_op__fn_unit \output_mul_op__fn_unit + connect \mul_op__fn_unit$3 \output_mul_op__fn_unit$33 + connect \mul_op__imm_data__data \output_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \output_mul_op__imm_data__data$34 + connect \mul_op__imm_data__ok \output_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \output_mul_op__imm_data__ok$35 + connect \mul_op__insn \output_mul_op__insn + connect \mul_op__insn$13 \output_mul_op__insn$43 + connect \mul_op__insn_type \output_mul_op__insn_type + connect \mul_op__insn_type$2 \output_mul_op__insn_type$32 + connect \mul_op__is_32bit \output_mul_op__is_32bit + connect \mul_op__is_32bit$11 \output_mul_op__is_32bit$41 + connect \mul_op__is_signed \output_mul_op__is_signed + connect \mul_op__is_signed$12 \output_mul_op__is_signed$42 + connect \mul_op__oe__oe \output_mul_op__oe__oe + connect \mul_op__oe__oe$8 \output_mul_op__oe__oe$38 + connect \mul_op__oe__ok \output_mul_op__oe__ok + connect \mul_op__oe__ok$9 \output_mul_op__oe__ok$39 + connect \mul_op__rc__ok \output_mul_op__rc__ok + connect \mul_op__rc__ok$7 \output_mul_op__rc__ok$37 + connect \mul_op__rc__rc \output_mul_op__rc__rc + connect \mul_op__rc__rc$6 \output_mul_op__rc__rc$36 + connect \mul_op__write_cr0 \output_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \output_mul_op__write_cr0$40 + connect \muxid \output_muxid + connect \muxid$1 \output_muxid$31 + connect \o \output_o + connect \o$14 \output_o$44 + connect \o_ok \output_o_ok + connect \o_ok$15 \output_o_ok$45 + connect \xer_ov \output_xer_ov + connect \xer_ov$17 \output_xer_ov$47 + connect \xer_ov_ok \output_xer_ov_ok + connect \xer_so \output_xer_so + connect \xer_so$18 \output_xer_so$48 + connect \xer_so_ok \output_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:145218.10-145221.4" + cell \p$98 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:144116.7-144116.20" + process $proc$libresoc.v:144116$7883 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:144125.13-144125.24" + process $proc$libresoc.v:144125$7884 + assign { } { } + assign $1\cr_a[3:0] 4'0000 + sync always + sync init + update \cr_a $1\cr_a[3:0] + end + attribute \src "libresoc.v:144134.7-144134.21" + process $proc$libresoc.v:144134$7885 + assign { } { } + assign $1\cr_a_ok[0:0] 1'0 + sync always + sync init + update \cr_a_ok $1\cr_a_ok[0:0] + end + attribute \src "libresoc.v:144417.14-144417.43" + process $proc$libresoc.v:144417$7886 + assign { } { } + assign $0\mul_op__fn_unit$3[11:0]$7887 12'000000000000 + sync always + sync init + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[11:0]$7887 + end + attribute \src "libresoc.v:144439.14-144439.63" + process $proc$libresoc.v:144439$7888 + assign { } { } + assign $0\mul_op__imm_data__data$4[63:0]$7889 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7889 + end + attribute \src "libresoc.v:144448.7-144448.38" + process $proc$libresoc.v:144448$7890 + assign { } { } + assign $0\mul_op__imm_data__ok$5[0:0]$7891 1'0 + sync always + sync init + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$7891 + end + attribute \src "libresoc.v:144457.14-144457.39" + process $proc$libresoc.v:144457$7892 + assign { } { } + assign $0\mul_op__insn$13[31:0]$7893 0 + sync always + sync init + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7893 + end + attribute \src "libresoc.v:144614.13-144614.42" + process $proc$libresoc.v:144614$7894 + assign { } { } + assign $0\mul_op__insn_type$2[6:0]$7895 7'0000000 + sync always + sync init + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7895 + end + attribute \src "libresoc.v:144697.7-144697.35" + process $proc$libresoc.v:144697$7896 + assign { } { } + assign $0\mul_op__is_32bit$11[0:0]$7897 1'0 + sync always + sync init + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$7897 + end + attribute \src "libresoc.v:144706.7-144706.36" + process $proc$libresoc.v:144706$7898 + assign { } { } + assign $0\mul_op__is_signed$12[0:0]$7899 1'0 + sync always + sync init + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7899 + end + attribute \src "libresoc.v:144717.7-144717.32" + process $proc$libresoc.v:144717$7900 + assign { } { } + assign $0\mul_op__oe__oe$8[0:0]$7901 1'0 + sync always + sync init + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$7901 + end + attribute \src "libresoc.v:144726.7-144726.32" + process $proc$libresoc.v:144726$7902 + assign { } { } + assign $0\mul_op__oe__ok$9[0:0]$7903 1'0 + sync always + sync init + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$7903 + end + attribute \src "libresoc.v:144735.7-144735.32" + process $proc$libresoc.v:144735$7904 + assign { } { } + assign $0\mul_op__rc__ok$7[0:0]$7905 1'0 + sync always + sync init + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$7905 + end + attribute \src "libresoc.v:144742.7-144742.32" + process $proc$libresoc.v:144742$7906 + assign { } { } + assign $0\mul_op__rc__rc$6[0:0]$7907 1'0 + sync always + sync init + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$7907 + end + attribute \src "libresoc.v:144751.7-144751.36" + process $proc$libresoc.v:144751$7908 + assign { } { } + assign $0\mul_op__write_cr0$10[0:0]$7909 1'0 + sync always + sync init + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$7909 + end + attribute \src "libresoc.v:144760.13-144760.29" + process $proc$libresoc.v:144760$7910 + assign { } { } + assign $0\muxid$1[1:0]$7911 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$7911 + end + attribute \src "libresoc.v:144781.14-144781.43" + process $proc$libresoc.v:144781$7912 + assign { } { } + assign $0\o$14[63:0]$7913 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o$14 $0\o$14[63:0]$7913 + end + attribute \src "libresoc.v:144788.7-144788.18" + process $proc$libresoc.v:144788$7914 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "libresoc.v:145054.7-145054.20" + process $proc$libresoc.v:145054$7915 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:145059.13-145059.26" + process $proc$libresoc.v:145059$7916 + assign { } { } + assign $1\xer_ov[1:0] 2'00 + sync always + sync init + update \xer_ov $1\xer_ov[1:0] + end + attribute \src "libresoc.v:145066.7-145066.23" + process $proc$libresoc.v:145066$7917 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'0 + sync always + sync init + update \xer_ov_ok $1\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:145077.7-145077.25" + process $proc$libresoc.v:145077$7918 + assign { } { } + assign $0\xer_so$15[0:0]$7919 1'0 + sync always + sync init + update \xer_so$15 $0\xer_so$15[0:0]$7919 + end + attribute \src "libresoc.v:145084.7-145084.23" + process $proc$libresoc.v:145084$7920 + assign { } { } + assign $1\xer_so_ok[0:0] 1'0 + sync always + sync init + update \xer_so_ok $1\xer_so_ok[0:0] + end + attribute \src "libresoc.v:145092.3-145093.37" + process $proc$libresoc.v:145092$7784 + assign { } { } + assign $0\xer_so$15[0:0]$7785 \xer_so$15$next + sync posedge \coresync_clk + update \xer_so$15 $0\xer_so$15[0:0]$7785 + end + attribute \src "libresoc.v:145094.3-145095.35" + process $proc$libresoc.v:145094$7786 + assign { } { } + assign $0\xer_so_ok[0:0] \xer_so_ok$next + sync posedge \coresync_clk + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:145096.3-145097.29" + process $proc$libresoc.v:145096$7787 + assign { } { } + assign $0\xer_ov[1:0] \xer_ov$next + sync posedge \coresync_clk + update \xer_ov $0\xer_ov[1:0] + end + attribute \src "libresoc.v:145098.3-145099.35" + process $proc$libresoc.v:145098$7788 + assign { } { } + assign $0\xer_ov_ok[0:0] \xer_ov_ok$next + sync posedge \coresync_clk + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:145100.3-145101.25" + process $proc$libresoc.v:145100$7789 + assign { } { } + assign $0\cr_a[3:0] \cr_a$next + sync posedge \coresync_clk + update \cr_a $0\cr_a[3:0] + end + attribute \src "libresoc.v:145102.3-145103.31" + process $proc$libresoc.v:145102$7790 + assign { } { } + assign $0\cr_a_ok[0:0] \cr_a_ok$next + sync posedge \coresync_clk + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "libresoc.v:145104.3-145105.27" + process $proc$libresoc.v:145104$7791 + assign { } { } + assign $0\o$14[63:0]$7792 \o$14$next + sync posedge \coresync_clk + update \o$14 $0\o$14[63:0]$7792 + end + attribute \src "libresoc.v:145106.3-145107.25" + process $proc$libresoc.v:145106$7793 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:145108.3-145109.57" + process $proc$libresoc.v:145108$7794 + assign { } { } + assign $0\mul_op__insn_type$2[6:0]$7795 \mul_op__insn_type$2$next + sync posedge \coresync_clk + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7795 + end + attribute \src "libresoc.v:145110.3-145111.53" + process $proc$libresoc.v:145110$7796 + assign { } { } + assign $0\mul_op__fn_unit$3[11:0]$7797 \mul_op__fn_unit$3$next + sync posedge \coresync_clk + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[11:0]$7797 + end + attribute \src "libresoc.v:145112.3-145113.67" + process $proc$libresoc.v:145112$7798 + assign { } { } + assign $0\mul_op__imm_data__data$4[63:0]$7799 \mul_op__imm_data__data$4$next + sync posedge \coresync_clk + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7799 + end + attribute \src "libresoc.v:145114.3-145115.63" + process $proc$libresoc.v:145114$7800 + assign { } { } + assign $0\mul_op__imm_data__ok$5[0:0]$7801 \mul_op__imm_data__ok$5$next + sync posedge \coresync_clk + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$7801 + end + attribute \src "libresoc.v:145116.3-145117.51" + process $proc$libresoc.v:145116$7802 + assign { } { } + assign $0\mul_op__rc__rc$6[0:0]$7803 \mul_op__rc__rc$6$next + sync posedge \coresync_clk + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$7803 + end + attribute \src "libresoc.v:145118.3-145119.51" + process $proc$libresoc.v:145118$7804 + assign { } { } + assign $0\mul_op__rc__ok$7[0:0]$7805 \mul_op__rc__ok$7$next + sync posedge \coresync_clk + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$7805 + end + attribute \src "libresoc.v:145120.3-145121.51" + process $proc$libresoc.v:145120$7806 + assign { } { } + assign $0\mul_op__oe__oe$8[0:0]$7807 \mul_op__oe__oe$8$next + sync posedge \coresync_clk + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$7807 + end + attribute \src "libresoc.v:145122.3-145123.51" + process $proc$libresoc.v:145122$7808 + assign { } { } + assign $0\mul_op__oe__ok$9[0:0]$7809 \mul_op__oe__ok$9$next + sync posedge \coresync_clk + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$7809 + end + attribute \src "libresoc.v:145124.3-145125.59" + process $proc$libresoc.v:145124$7810 + assign { } { } + assign $0\mul_op__write_cr0$10[0:0]$7811 \mul_op__write_cr0$10$next + sync posedge \coresync_clk + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$7811 + end + attribute \src "libresoc.v:145126.3-145127.57" + process $proc$libresoc.v:145126$7812 + assign { } { } + assign $0\mul_op__is_32bit$11[0:0]$7813 \mul_op__is_32bit$11$next + sync posedge \coresync_clk + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$7813 + end + attribute \src "libresoc.v:145128.3-145129.59" + process $proc$libresoc.v:145128$7814 + assign { } { } + assign $0\mul_op__is_signed$12[0:0]$7815 \mul_op__is_signed$12$next + sync posedge \coresync_clk + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7815 + end + attribute \src "libresoc.v:145130.3-145131.49" + process $proc$libresoc.v:145130$7816 + assign { } { } + assign $0\mul_op__insn$13[31:0]$7817 \mul_op__insn$13$next + sync posedge \coresync_clk + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7817 + end + attribute \src "libresoc.v:145132.3-145133.33" + process $proc$libresoc.v:145132$7818 + assign { } { } + assign $0\muxid$1[1:0]$7819 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$7819 + end + attribute \src "libresoc.v:145134.3-145135.29" + process $proc$libresoc.v:145134$7820 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:145222.3-145239.6" + process $proc$libresoc.v:145222$7821 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$7822 $2\r_busy$next[0:0]$7824 + attribute \src "libresoc.v:145223.5-145223.29" + switch \initial + attribute \src "libresoc.v:145223.9-145223.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$7823 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$7823 1'0 + case + assign $1\r_busy$next[0:0]$7823 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$7824 1'0 + case + assign $2\r_busy$next[0:0]$7824 $1\r_busy$next[0:0]$7823 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$7822 + end + attribute \src "libresoc.v:145240.3-145252.6" + process $proc$libresoc.v:145240$7825 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$7826 $1\muxid$1$next[1:0]$7827 + attribute \src "libresoc.v:145241.5-145241.29" + switch \initial + attribute \src "libresoc.v:145241.9-145241.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$7827 \muxid$58 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$7827 \muxid$58 + case + assign $1\muxid$1$next[1:0]$7827 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$7826 + end + attribute \src "libresoc.v:145253.3-145288.6" + process $proc$libresoc.v:145253$7828 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mul_op__fn_unit$3$next[11:0]$7829 $1\mul_op__fn_unit$3$next[11:0]$7841 + assign { } { } + assign { } { } + assign $0\mul_op__insn$13$next[31:0]$7832 $1\mul_op__insn$13$next[31:0]$7844 + assign $0\mul_op__insn_type$2$next[6:0]$7833 $1\mul_op__insn_type$2$next[6:0]$7845 + assign $0\mul_op__is_32bit$11$next[0:0]$7834 $1\mul_op__is_32bit$11$next[0:0]$7846 + assign $0\mul_op__is_signed$12$next[0:0]$7835 $1\mul_op__is_signed$12$next[0:0]$7847 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mul_op__write_cr0$10$next[0:0]$7840 $1\mul_op__write_cr0$10$next[0:0]$7852 + assign $0\mul_op__imm_data__data$4$next[63:0]$7830 $2\mul_op__imm_data__data$4$next[63:0]$7853 + assign $0\mul_op__imm_data__ok$5$next[0:0]$7831 $2\mul_op__imm_data__ok$5$next[0:0]$7854 + assign $0\mul_op__oe__oe$8$next[0:0]$7836 $2\mul_op__oe__oe$8$next[0:0]$7855 + assign $0\mul_op__oe__ok$9$next[0:0]$7837 $2\mul_op__oe__ok$9$next[0:0]$7856 + assign $0\mul_op__rc__ok$7$next[0:0]$7838 $2\mul_op__rc__ok$7$next[0:0]$7857 + assign $0\mul_op__rc__rc$6$next[0:0]$7839 $2\mul_op__rc__rc$6$next[0:0]$7858 + attribute \src "libresoc.v:145254.5-145254.29" + switch \initial + attribute \src "libresoc.v:145254.9-145254.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\mul_op__insn$13$next[31:0]$7844 $1\mul_op__is_signed$12$next[0:0]$7847 $1\mul_op__is_32bit$11$next[0:0]$7846 $1\mul_op__write_cr0$10$next[0:0]$7852 $1\mul_op__oe__ok$9$next[0:0]$7849 $1\mul_op__oe__oe$8$next[0:0]$7848 $1\mul_op__rc__ok$7$next[0:0]$7850 $1\mul_op__rc__rc$6$next[0:0]$7851 $1\mul_op__imm_data__ok$5$next[0:0]$7843 $1\mul_op__imm_data__data$4$next[63:0]$7842 $1\mul_op__fn_unit$3$next[11:0]$7841 $1\mul_op__insn_type$2$next[6:0]$7845 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\mul_op__insn$13$next[31:0]$7844 $1\mul_op__is_signed$12$next[0:0]$7847 $1\mul_op__is_32bit$11$next[0:0]$7846 $1\mul_op__write_cr0$10$next[0:0]$7852 $1\mul_op__oe__ok$9$next[0:0]$7849 $1\mul_op__oe__oe$8$next[0:0]$7848 $1\mul_op__rc__ok$7$next[0:0]$7850 $1\mul_op__rc__rc$6$next[0:0]$7851 $1\mul_op__imm_data__ok$5$next[0:0]$7843 $1\mul_op__imm_data__data$4$next[63:0]$7842 $1\mul_op__fn_unit$3$next[11:0]$7841 $1\mul_op__insn_type$2$next[6:0]$7845 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } + case + assign $1\mul_op__fn_unit$3$next[11:0]$7841 \mul_op__fn_unit$3 + assign $1\mul_op__imm_data__data$4$next[63:0]$7842 \mul_op__imm_data__data$4 + assign $1\mul_op__imm_data__ok$5$next[0:0]$7843 \mul_op__imm_data__ok$5 + assign $1\mul_op__insn$13$next[31:0]$7844 \mul_op__insn$13 + assign $1\mul_op__insn_type$2$next[6:0]$7845 \mul_op__insn_type$2 + assign $1\mul_op__is_32bit$11$next[0:0]$7846 \mul_op__is_32bit$11 + assign $1\mul_op__is_signed$12$next[0:0]$7847 \mul_op__is_signed$12 + assign $1\mul_op__oe__oe$8$next[0:0]$7848 \mul_op__oe__oe$8 + assign $1\mul_op__oe__ok$9$next[0:0]$7849 \mul_op__oe__ok$9 + assign $1\mul_op__rc__ok$7$next[0:0]$7850 \mul_op__rc__ok$7 + assign $1\mul_op__rc__rc$6$next[0:0]$7851 \mul_op__rc__rc$6 + assign $1\mul_op__write_cr0$10$next[0:0]$7852 \mul_op__write_cr0$10 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\mul_op__imm_data__data$4$next[63:0]$7853 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$5$next[0:0]$7854 1'0 + assign $2\mul_op__rc__rc$6$next[0:0]$7858 1'0 + assign $2\mul_op__rc__ok$7$next[0:0]$7857 1'0 + assign $2\mul_op__oe__oe$8$next[0:0]$7855 1'0 + assign $2\mul_op__oe__ok$9$next[0:0]$7856 1'0 + case + assign $2\mul_op__imm_data__data$4$next[63:0]$7853 $1\mul_op__imm_data__data$4$next[63:0]$7842 + assign $2\mul_op__imm_data__ok$5$next[0:0]$7854 $1\mul_op__imm_data__ok$5$next[0:0]$7843 + assign $2\mul_op__oe__oe$8$next[0:0]$7855 $1\mul_op__oe__oe$8$next[0:0]$7848 + assign $2\mul_op__oe__ok$9$next[0:0]$7856 $1\mul_op__oe__ok$9$next[0:0]$7849 + assign $2\mul_op__rc__ok$7$next[0:0]$7857 $1\mul_op__rc__ok$7$next[0:0]$7850 + assign $2\mul_op__rc__rc$6$next[0:0]$7858 $1\mul_op__rc__rc$6$next[0:0]$7851 + end + sync always + update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[11:0]$7829 + update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$7830 + update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$7831 + update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$7832 + update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$7833 + update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$7834 + update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$7835 + update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$7836 + update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$7837 + update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$7838 + update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$7839 + update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$7840 + end + attribute \src "libresoc.v:145289.3-145307.6" + process $proc$libresoc.v:145289$7859 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$14$next[63:0]$7861 $1\o$14$next[63:0]$7863 + assign $0\o_ok$next[0:0]$7860 $2\o_ok$next[0:0]$7864 + attribute \src "libresoc.v:145290.5-145290.29" + switch \initial + attribute \src "libresoc.v:145290.9-145290.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$7862 $1\o$14$next[63:0]$7863 } { \o_ok$72 \o$71 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$7862 $1\o$14$next[63:0]$7863 } { \o_ok$72 \o$71 } + case + assign $1\o_ok$next[0:0]$7862 \o_ok + assign $1\o$14$next[63:0]$7863 \o$14 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$7864 1'0 + case + assign $2\o_ok$next[0:0]$7864 $1\o_ok$next[0:0]$7862 + end + sync always + update \o_ok$next $0\o_ok$next[0:0]$7860 + update \o$14$next $0\o$14$next[63:0]$7861 + end + attribute \src "libresoc.v:145308.3-145326.6" + process $proc$libresoc.v:145308$7865 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$next[3:0]$7866 $1\cr_a$next[3:0]$7868 + assign { } { } + assign $0\cr_a_ok$next[0:0]$7867 $2\cr_a_ok$next[0:0]$7870 + attribute \src "libresoc.v:145309.5-145309.29" + switch \initial + attribute \src "libresoc.v:145309.9-145309.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$7869 $1\cr_a$next[3:0]$7868 } { \cr_a_ok$74 \cr_a$73 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$7869 $1\cr_a$next[3:0]$7868 } { \cr_a_ok$74 \cr_a$73 } + case + assign $1\cr_a$next[3:0]$7868 \cr_a + assign $1\cr_a_ok$next[0:0]$7869 \cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$next[0:0]$7870 1'0 + case + assign $2\cr_a_ok$next[0:0]$7870 $1\cr_a_ok$next[0:0]$7869 + end + sync always + update \cr_a$next $0\cr_a$next[3:0]$7866 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$7867 + end + attribute \src "libresoc.v:145327.3-145345.6" + process $proc$libresoc.v:145327$7871 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ov$next[1:0]$7872 $1\xer_ov$next[1:0]$7874 + assign { } { } + assign $0\xer_ov_ok$next[0:0]$7873 $2\xer_ov_ok$next[0:0]$7876 + attribute \src "libresoc.v:145328.5-145328.29" + switch \initial + attribute \src "libresoc.v:145328.9-145328.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$7875 $1\xer_ov$next[1:0]$7874 } { \xer_ov_ok$76 \xer_ov$75 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$7875 $1\xer_ov$next[1:0]$7874 } { \xer_ov_ok$76 \xer_ov$75 } + case + assign $1\xer_ov$next[1:0]$7874 \xer_ov + assign $1\xer_ov_ok$next[0:0]$7875 \xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ov_ok$next[0:0]$7876 1'0 + case + assign $2\xer_ov_ok$next[0:0]$7876 $1\xer_ov_ok$next[0:0]$7875 + end + sync always + update \xer_ov$next $0\xer_ov$next[1:0]$7872 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$7873 + end + attribute \src "libresoc.v:145346.3-145364.6" + process $proc$libresoc.v:145346$7877 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$15$next[0:0]$7879 $1\xer_so$15$next[0:0]$7881 + assign $0\xer_so_ok$next[0:0]$7878 $2\xer_so_ok$next[0:0]$7882 + attribute \src "libresoc.v:145347.5-145347.29" + switch \initial + attribute \src "libresoc.v:145347.9-145347.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$7880 $1\xer_so$15$next[0:0]$7881 } { \xer_so_ok$78 \xer_so$77 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$7880 $1\xer_so$15$next[0:0]$7881 } { \xer_so_ok$78 \xer_so$77 } + case + assign $1\xer_so_ok$next[0:0]$7880 \xer_so_ok + assign $1\xer_so$15$next[0:0]$7881 \xer_so$15 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$next[0:0]$7882 1'0 + case + assign $2\xer_so_ok$next[0:0]$7882 $1\xer_so_ok$next[0:0]$7880 + end + sync always + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$7878 + update \xer_so$15$next $0\xer_so$15$next[0:0]$7879 + end + connect \$56 $and$libresoc.v:145091$7783_Y + connect \cr_a$51 4'0000 + connect \cr_a_ok$52 1'0 + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_so_ok$78 \xer_so$77 } { \output_xer_so_ok \output_xer_so$48 } + connect { \xer_ov_ok$76 \xer_ov$75 } { \output_xer_ov_ok \output_xer_ov$47 } + connect { \cr_a_ok$74 \cr_a$73 } { \output_cr_a_ok \output_cr_a$46 } + connect { \o_ok$72 \o$71 } { \output_o_ok$45 \output_o$44 } + connect { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } { \output_mul_op__insn$43 \output_mul_op__is_signed$42 \output_mul_op__is_32bit$41 \output_mul_op__write_cr0$40 \output_mul_op__oe__ok$39 \output_mul_op__oe__oe$38 \output_mul_op__rc__ok$37 \output_mul_op__rc__rc$36 \output_mul_op__imm_data__ok$35 \output_mul_op__imm_data__data$34 \output_mul_op__fn_unit$33 \output_mul_op__insn_type$32 } + connect \muxid$58 \output_muxid$31 + connect \p_valid_i_p_ready_o \$56 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$55 \p_valid_i + connect { \xer_so_ok$54 \output_xer_so } { \mul3_xer_so_ok \mul3_xer_so$30 } + connect { \xer_ov_ok$53 \output_xer_ov } { \mul3_xer_ov_ok \mul3_xer_ov } + connect { \cr_a_ok$50 \output_cr_a } 5'00000 + connect { \output_o_ok \output_o } { \mul3_o_ok \mul3_o$29 } + connect { \output_mul_op__insn \output_mul_op__is_signed \output_mul_op__is_32bit \output_mul_op__write_cr0 \output_mul_op__oe__ok \output_mul_op__oe__oe \output_mul_op__rc__ok \output_mul_op__rc__rc \output_mul_op__imm_data__ok \output_mul_op__imm_data__data \output_mul_op__fn_unit \output_mul_op__insn_type } { \mul3_mul_op__insn$28 \mul3_mul_op__is_signed$27 \mul3_mul_op__is_32bit$26 \mul3_mul_op__write_cr0$25 \mul3_mul_op__oe__ok$24 \mul3_mul_op__oe__oe$23 \mul3_mul_op__rc__ok$22 \mul3_mul_op__rc__rc$21 \mul3_mul_op__imm_data__ok$20 \mul3_mul_op__imm_data__data$19 \mul3_mul_op__fn_unit$18 \mul3_mul_op__insn_type$17 } + connect \output_muxid \mul3_muxid$16 + connect \neg_res32$49 \neg_res32 + connect \mul3_neg_res \neg_res + connect \mul3_xer_so \xer_so + connect \mul3_o \o + connect { \mul3_mul_op__insn \mul3_mul_op__is_signed \mul3_mul_op__is_32bit \mul3_mul_op__write_cr0 \mul3_mul_op__oe__ok \mul3_mul_op__oe__oe \mul3_mul_op__rc__ok \mul3_mul_op__rc__rc \mul3_mul_op__imm_data__ok \mul3_mul_op__imm_data__data \mul3_mul_op__fn_unit \mul3_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \mul3_muxid \muxid +end +attribute \src "libresoc.v:145394.1-145405.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.n" +attribute \generator "nMigen" +module \n + attribute \src "libresoc.v:145403.17-145403.111" + wire $and$libresoc.v:145403$7921_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $and$libresoc.v:145403$7921 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:145403$7921_Y + end + connect \$1 $and$libresoc.v:145403$7921_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:145409.1-145420.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.n" +attribute \generator "nMigen" +module \n$109 + attribute \src "libresoc.v:145418.17-145418.111" + wire $and$libresoc.v:145418$7922_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src 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\r_opc + connect \Y $not$libresoc.v:145889$7968_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:145883$7962 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:145883$7962_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:145885$7964 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:145885$7964_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:145888$7967 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:145888$7967_Y + end + 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\r_opc + connect \Y $not$libresoc.v:145951$7982_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:145945$7976 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:145945$7976_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:145947$7978 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:145947$7978_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:145950$7981 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:145950$7981_Y + end + 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\coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$7986 1'0 + case + assign $1\q_int$next[0:0]$7986 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$7985 + end + connect \$9 $and$libresoc.v:145944$7975_Y + connect \$11 $or$libresoc.v:145945$7976_Y + connect \$13 $not$libresoc.v:145946$7977_Y + connect \$15 $or$libresoc.v:145947$7978_Y + connect \$1 $not$libresoc.v:145948$7979_Y + connect \$3 $and$libresoc.v:145949$7980_Y + connect \$5 $or$libresoc.v:145950$7981_Y + connect \$7 $not$libresoc.v:145951$7982_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "libresoc.v:145970.1-146028.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.opc_l" +attribute \generator "nMigen" +module \opc_l$120 + attribute \src "libresoc.v:145971.7-145971.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:146016.3-146024.6" + wire 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\r_opc + connect \Y $not$libresoc.v:146075$8010_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:146069$8004 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:146069$8004_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:146071$8006 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:146071$8006_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:146074$8009 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:146074$8009_Y + end + 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\coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$8014 1'0 + case + assign $1\q_int$next[0:0]$8014 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$8013 + end + connect \$9 $and$libresoc.v:146068$8003_Y + connect \$11 $or$libresoc.v:146069$8004_Y + connect \$13 $not$libresoc.v:146070$8005_Y + connect \$15 $or$libresoc.v:146071$8006_Y + connect \$1 $not$libresoc.v:146072$8007_Y + connect \$3 $and$libresoc.v:146073$8008_Y + connect \$5 $or$libresoc.v:146074$8009_Y + connect \$7 $not$libresoc.v:146075$8010_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "libresoc.v:146094.1-146152.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.opc_l" +attribute \generator "nMigen" +module \opc_l$24 + attribute \src "libresoc.v:146095.7-146095.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:146140.3-146148.6" + wire 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:146135$8022 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:146135$8022_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:146132$8019 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$libresoc.v:146132$8019_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:146134$8021 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:146134$8021_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:146137$8024 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:146137$8024_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:146131$8018 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:146131$8018_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:146133$8020 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:146133$8020_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:146136$8023 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:146136$8023_Y + end + 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\coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$8028 1'0 + case + assign $1\q_int$next[0:0]$8028 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$8027 + end + connect \$9 $and$libresoc.v:146130$8017_Y + connect \$11 $or$libresoc.v:146131$8018_Y + connect \$13 $not$libresoc.v:146132$8019_Y + connect \$15 $or$libresoc.v:146133$8020_Y + connect \$1 $not$libresoc.v:146134$8021_Y + connect \$3 $and$libresoc.v:146135$8022_Y + connect \$5 $or$libresoc.v:146136$8023_Y + connect \$7 $not$libresoc.v:146137$8024_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "libresoc.v:146156.1-146214.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.opc_l" +attribute \generator "nMigen" +module \opc_l$40 + attribute \src "libresoc.v:146157.7-146157.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:146202.3-146210.6" + wire $0\q_int$next[0:0]$8041 + attribute \src "libresoc.v:146200.3-146201.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:146202.3-146210.6" + wire $1\q_int$next[0:0]$8042 + attribute \src "libresoc.v:146179.7-146179.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:146192.17-146192.96" + wire $and$libresoc.v:146192$8031_Y + attribute \src "libresoc.v:146197.17-146197.96" + wire $and$libresoc.v:146197$8036_Y + attribute \src "libresoc.v:146194.18-146194.93" + wire $not$libresoc.v:146194$8033_Y + attribute \src "libresoc.v:146196.17-146196.92" + wire $not$libresoc.v:146196$8035_Y + attribute \src "libresoc.v:146199.17-146199.92" + wire $not$libresoc.v:146199$8038_Y + attribute \src "libresoc.v:146193.18-146193.98" + wire $or$libresoc.v:146193$8032_Y + attribute \src "libresoc.v:146195.18-146195.99" + wire $or$libresoc.v:146195$8034_Y + attribute \src "libresoc.v:146198.17-146198.97" + wire $or$libresoc.v:146198$8037_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:146157.7-146157.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:146192$8031 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:146192$8031_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:146197$8036 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:146197$8036_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:146194$8033 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$libresoc.v:146194$8033_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:146196$8035 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:146196$8035_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:146199$8038 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:146199$8038_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:146193$8032 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:146193$8032_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:146195$8034 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:146195$8034_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:146198$8037 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:146198$8037_Y + end + attribute \src "libresoc.v:146157.7-146157.20" + process $proc$libresoc.v:146157$8043 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:146179.7-146179.19" + process $proc$libresoc.v:146179$8044 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:146200.3-146201.27" + process $proc$libresoc.v:146200$8039 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:146202.3-146210.6" + process $proc$libresoc.v:146202$8040 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$8041 $1\q_int$next[0:0]$8042 + attribute \src "libresoc.v:146203.5-146203.29" + switch \initial + attribute \src "libresoc.v:146203.9-146203.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$8042 1'0 + case + assign $1\q_int$next[0:0]$8042 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$8041 + end + connect \$9 $and$libresoc.v:146192$8031_Y + connect \$11 $or$libresoc.v:146193$8032_Y + connect \$13 $not$libresoc.v:146194$8033_Y + connect \$15 $or$libresoc.v:146195$8034_Y + connect \$1 $not$libresoc.v:146196$8035_Y + connect \$3 $and$libresoc.v:146197$8036_Y + connect \$5 $or$libresoc.v:146198$8037_Y + connect \$7 $not$libresoc.v:146199$8038_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "libresoc.v:146218.1-146276.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.opc_l" +attribute \generator "nMigen" +module \opc_l$56 + attribute \src "libresoc.v:146219.7-146219.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:146264.3-146272.6" + wire $0\q_int$next[0:0]$8055 + attribute \src "libresoc.v:146262.3-146263.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:146264.3-146272.6" + wire $1\q_int$next[0:0]$8056 + attribute \src "libresoc.v:146241.7-146241.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:146254.17-146254.96" + wire $and$libresoc.v:146254$8045_Y + attribute \src "libresoc.v:146259.17-146259.96" + wire $and$libresoc.v:146259$8050_Y + attribute \src "libresoc.v:146256.18-146256.93" + wire $not$libresoc.v:146256$8047_Y + attribute \src "libresoc.v:146258.17-146258.92" + wire $not$libresoc.v:146258$8049_Y + attribute \src "libresoc.v:146261.17-146261.92" + wire $not$libresoc.v:146261$8052_Y + attribute \src "libresoc.v:146255.18-146255.98" + wire $or$libresoc.v:146255$8046_Y + attribute \src "libresoc.v:146257.18-146257.99" + wire $or$libresoc.v:146257$8048_Y + attribute \src "libresoc.v:146260.17-146260.97" + wire $or$libresoc.v:146260$8051_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:146219.7-146219.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:146254$8045 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:146254$8045_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:146259$8050 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:146259$8050_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:146256$8047 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$libresoc.v:146256$8047_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:146258$8049 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:146258$8049_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:146261$8052 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:146261$8052_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:146255$8046 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:146255$8046_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:146257$8048 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:146257$8048_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:146260$8051 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:146260$8051_Y + end + attribute \src "libresoc.v:146219.7-146219.20" + process $proc$libresoc.v:146219$8057 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:146241.7-146241.19" + process $proc$libresoc.v:146241$8058 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:146262.3-146263.27" + process $proc$libresoc.v:146262$8053 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:146264.3-146272.6" + process $proc$libresoc.v:146264$8054 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$8055 $1\q_int$next[0:0]$8056 + attribute \src "libresoc.v:146265.5-146265.29" + switch \initial + attribute \src "libresoc.v:146265.9-146265.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$8056 1'0 + case + assign $1\q_int$next[0:0]$8056 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$8055 + end + connect \$9 $and$libresoc.v:146254$8045_Y + connect \$11 $or$libresoc.v:146255$8046_Y + connect \$13 $not$libresoc.v:146256$8047_Y + connect \$15 $or$libresoc.v:146257$8048_Y + connect \$1 $not$libresoc.v:146258$8049_Y + connect \$3 $and$libresoc.v:146259$8050_Y + connect \$5 $or$libresoc.v:146260$8051_Y + connect \$7 $not$libresoc.v:146261$8052_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "libresoc.v:146280.1-146338.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.opc_l" +attribute \generator "nMigen" +module \opc_l$68 + attribute \src "libresoc.v:146281.7-146281.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:146326.3-146334.6" + wire $0\q_int$next[0:0]$8069 + attribute \src "libresoc.v:146324.3-146325.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:146326.3-146334.6" + wire $1\q_int$next[0:0]$8070 + attribute \src "libresoc.v:146303.7-146303.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:146316.17-146316.96" + wire $and$libresoc.v:146316$8059_Y + attribute \src "libresoc.v:146321.17-146321.96" + wire $and$libresoc.v:146321$8064_Y + attribute \src "libresoc.v:146318.18-146318.93" + wire $not$libresoc.v:146318$8061_Y + attribute \src "libresoc.v:146320.17-146320.92" + wire $not$libresoc.v:146320$8063_Y + attribute \src "libresoc.v:146323.17-146323.92" + wire $not$libresoc.v:146323$8066_Y + attribute \src "libresoc.v:146317.18-146317.98" + wire $or$libresoc.v:146317$8060_Y + attribute \src "libresoc.v:146319.18-146319.99" + wire $or$libresoc.v:146319$8062_Y + attribute \src "libresoc.v:146322.17-146322.97" + wire $or$libresoc.v:146322$8065_Y + attribute \src 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attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 26 \alu_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \alu_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \alu_op__invert_out$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \alu_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \alu_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \alu_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \alu_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \alu_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \alu_op__write_cr0$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" + wire width 4 \cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 input 21 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 46 \cr_a$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 47 \cr_a_ok + attribute \src "libresoc.v:146405.7-146405.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" + wire \is_cmp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" + wire \is_cmpeqb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" + wire \is_negative + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" + wire \is_nzero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" + wire \is_positive + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" + wire \msb_test + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 54 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 25 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 19 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 44 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" + wire width 65 \o$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 20 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 45 \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" + wire \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" + wire \oe$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" + wire \so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" + wire width 64 \target + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 input 22 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 48 \xer_ca$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 49 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 input 23 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 50 \xer_ov$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 51 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 24 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 52 \xer_so$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 53 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" + cell $and $and$libresoc.v:146750$8087 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_op__oe__oe + connect \B \alu_op__oe__ok + connect \Y $and$libresoc.v:146750$8087_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $and $and$libresoc.v:146758$8097 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \B \$41 + connect \Y $and$libresoc.v:146758$8097_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + cell $and $and$libresoc.v:146761$8100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_op__oe__oe + connect \B \alu_op__oe__ok + connect \Y $and$libresoc.v:146761$8100_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $eq $eq$libresoc.v:146754$8093 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:146754$8093_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + cell $eq $eq$libresoc.v:146755$8094 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001100 + connect \Y $eq$libresoc.v:146755$8094_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $pos $extend$libresoc.v:146752$8089 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \$30 + connect \Y $extend$libresoc.v:146752$8089_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:146753$8091 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \o + connect \Y $extend$libresoc.v:146753$8091_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $not $not$libresoc.v:146751$8088 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \o + connect \Y $not$libresoc.v:146751$8088_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $not $not$libresoc.v:146757$8096 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_test + connect \Y $not$libresoc.v:146757$8096_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + cell $not $not$libresoc.v:146760$8099 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \Y $not$libresoc.v:146760$8099_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + cell $or $or$libresoc.v:146759$8098 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_cmpeqb + connect \B \is_cmp + connect \Y $or$libresoc.v:146759$8098_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" + cell $or $or$libresoc.v:146762$8101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_so + connect \B \xer_ov [0] + connect \Y $or$libresoc.v:146762$8101_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $pos $pos$libresoc.v:146752$8090 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:146752$8089_Y + connect \Y $pos$libresoc.v:146752$8090_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $pos$libresoc.v:146753$8092 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:146753$8091_Y + connect \Y $pos$libresoc.v:146753$8092_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + cell $reduce_or $reduce_or$libresoc.v:146756$8095 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \target + connect \Y $reduce_or$libresoc.v:146756$8095_Y + end + attribute \src "libresoc.v:146405.7-146405.20" + process $proc$libresoc.v:146405$8115 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:146763.3-146774.6" + process $proc$libresoc.v:146763$8102 + assign { } { } + assign $0\so[0:0] $1\so[0:0] + attribute \src "libresoc.v:146764.5-146764.29" + switch \initial + attribute \src "libresoc.v:146764.9-146764.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" + switch \oe + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\so[0:0] \xer_so$25 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\so[0:0] \xer_so + end + sync always + update \so $0\so[0:0] + end + attribute \src "libresoc.v:146775.3-146786.6" + process $proc$libresoc.v:146775$8103 + assign { } { } + assign $0\cr0[3:0] $1\cr0[3:0] + attribute \src "libresoc.v:146776.5-146776.29" + switch \initial + attribute \src "libresoc.v:146776.9-146776.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + switch \$45 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cr0[3:0] \cr_a + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cr0[3:0] { \is_negative \is_positive \$47 \so } + end + sync always + update \cr0 $0\cr0[3:0] + end + attribute \src "libresoc.v:146787.3-146798.6" + process $proc$libresoc.v:146787$8104 + assign { } { } + assign $0\o$28[64:0]$8105 $1\o$28[64:0]$8106 + attribute \src "libresoc.v:146788.5-146788.29" + switch \initial + attribute \src "libresoc.v:146788.9-146788.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" + switch \alu_op__invert_out + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\o$28[64:0]$8106 \$29 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\o$28[64:0]$8106 \$33 + end + sync always + update \o$28 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"/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" + wire \$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" + wire width 4 \cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 input 15 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 33 \cr_a$16 + attribute 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\enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 19 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 25 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 24 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 23 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 39 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 18 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 13 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 31 \o$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" + wire width 65 \o$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 14 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 32 \o_ok$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" + wire \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" + wire \oe$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" + wire \so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" + wire width 64 \target + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 input 16 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 35 \xer_ov$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 36 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 17 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 37 \xer_so$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 38 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" + cell $and $and$libresoc.v:147164$8116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \mul_op__oe__oe + connect \B \mul_op__oe__ok + connect \Y $and$libresoc.v:147164$8116_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $and $and$libresoc.v:147170$8123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \B \$30 + connect \Y $and$libresoc.v:147170$8123_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + cell $and $and$libresoc.v:147173$8126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \mul_op__oe__oe + connect \B \mul_op__oe__ok + connect \Y $and$libresoc.v:147173$8126_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $eq $eq$libresoc.v:147166$8119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \mul_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:147166$8119_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + cell $eq $eq$libresoc.v:147167$8120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \mul_op__insn_type + connect \B 7'0001100 + connect \Y $eq$libresoc.v:147167$8120_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:147165$8117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \o + connect \Y $extend$libresoc.v:147165$8117_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $not $not$libresoc.v:147169$8122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_test + connect \Y $not$libresoc.v:147169$8122_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + cell $not $not$libresoc.v:147172$8125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \Y $not$libresoc.v:147172$8125_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + cell $or $or$libresoc.v:147171$8124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_cmpeqb + connect \B \is_cmp + connect \Y $or$libresoc.v:147171$8124_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" + cell $or $or$libresoc.v:147174$8127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_so + connect \B \xer_ov [0] + connect \Y $or$libresoc.v:147174$8127_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $pos$libresoc.v:147165$8118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:147165$8117_Y + connect \Y $pos$libresoc.v:147165$8118_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + cell $reduce_or $reduce_or$libresoc.v:147168$8121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \target + connect \Y $reduce_or$libresoc.v:147168$8121_Y + end + attribute \src "libresoc.v:146861.7-146861.20" + process $proc$libresoc.v:146861$8138 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:147175.3-147186.6" + process $proc$libresoc.v:147175$8128 + assign { } { } + assign $0\so[0:0] $1\so[0:0] + attribute \src "libresoc.v:147176.5-147176.29" + switch \initial + attribute \src "libresoc.v:147176.9-147176.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" + switch \oe + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\so[0:0] \xer_so$18 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\so[0:0] \xer_so + end + sync always + update \so $0\so[0:0] + end + attribute \src "libresoc.v:147187.3-147198.6" + process $proc$libresoc.v:147187$8129 + assign { } { } + assign $0\cr0[3:0] $1\cr0[3:0] + attribute \src "libresoc.v:147188.5-147188.29" + switch \initial + attribute \src "libresoc.v:147188.9-147188.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + switch \$34 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cr0[3:0] \cr_a + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cr0[3:0] { \is_negative \is_positive \$36 \so } + end + sync always + update \cr0 $0\cr0[3:0] + end + attribute \src "libresoc.v:147199.3-147208.6" + process $proc$libresoc.v:147199$8130 + assign { } { } + assign { } { } + assign $0\xer_so$18[0:0]$8131 $1\xer_so$18[0:0]$8132 + attribute \src "libresoc.v:147200.5-147200.29" + switch \initial + attribute \src "libresoc.v:147200.9-147200.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$38 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_so$18[0:0]$8132 \$41 + case + assign $1\xer_so$18[0:0]$8132 1'0 + end + sync always + update \xer_so$18 $0\xer_so$18[0:0]$8131 + end + attribute \src "libresoc.v:147209.3-147218.6" + process $proc$libresoc.v:147209$8133 + assign { } { } + assign { } { } + assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] + attribute \src "libresoc.v:147210.5-147210.29" + switch \initial + attribute \src "libresoc.v:147210.9-147210.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$38 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_so_ok[0:0] 1'1 + case + assign $1\xer_so_ok[0:0] 1'0 + end + sync always + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:147219.3-147228.6" + process $proc$libresoc.v:147219$8134 + assign { } { } + assign { } { } + assign $0\xer_ov$17[1:0]$8135 $1\xer_ov$17[1:0]$8136 + attribute \src "libresoc.v:147220.5-147220.29" + switch \initial + attribute \src "libresoc.v:147220.9-147220.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$38 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_ov$17[1:0]$8136 \xer_ov + case + assign $1\xer_ov$17[1:0]$8136 2'00 + end + sync always + update \xer_ov$17 $0\xer_ov$17[1:0]$8135 + end + attribute \src "libresoc.v:147229.3-147238.6" + process $proc$libresoc.v:147229$8137 + assign { } { } + assign { } { } + assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:147230.5-147230.29" + switch \initial + attribute \src "libresoc.v:147230.9-147230.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$38 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'1 + case + assign $1\xer_ov_ok[0:0] 1'0 + end + sync always + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + connect \$19 $and$libresoc.v:147164$8116_Y + connect \$22 $pos$libresoc.v:147165$8118_Y + connect \$24 $eq$libresoc.v:147166$8119_Y + connect \$26 $eq$libresoc.v:147167$8120_Y + connect \$28 $reduce_or$libresoc.v:147168$8121_Y + connect \$30 $not$libresoc.v:147169$8122_Y + connect \$32 $and$libresoc.v:147170$8123_Y + connect \$34 $or$libresoc.v:147171$8124_Y + connect \$36 $not$libresoc.v:147172$8125_Y + connect \$39 $and$libresoc.v:147173$8126_Y + connect \$41 $or$libresoc.v:147174$8127_Y + connect \oe$38 \$39 + connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \muxid$1 \muxid + connect \cr_a_ok \mul_op__write_cr0 + connect \cr_a$16 \cr0 + connect \o_ok$15 \o_ok + connect \o$14 \o$21 [63:0] + connect \is_positive \$32 + connect \is_negative \msb_test + connect \is_nzero \$28 + connect \msb_test \target [63] + connect \is_cmpeqb \$26 + connect \is_cmp \$24 + connect \target \o$21 [63:0] + connect \o$21 \$22 + connect \oe \$19 +end +attribute \src "libresoc.v:147259.1-147607.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.output" +attribute \generator "nMigen" +module \output$118 + attribute \src "libresoc.v:147579.3-147590.6" + wire width 4 $0\cr0[3:0] + attribute \src "libresoc.v:147260.7-147260.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:147579.3-147590.6" + wire width 4 $1\cr0[3:0] + attribute \src "libresoc.v:147576.18-147576.112" + wire $and$libresoc.v:147576$8145_Y + attribute \src "libresoc.v:147572.18-147572.122" + wire $eq$libresoc.v:147572$8141_Y + attribute \src "libresoc.v:147573.18-147573.122" + wire $eq$libresoc.v:147573$8142_Y + attribute \src "libresoc.v:147571.18-147571.101" + wire width 65 $extend$libresoc.v:147571$8139_Y + attribute \src "libresoc.v:147575.18-147575.107" + wire $not$libresoc.v:147575$8144_Y + attribute \src "libresoc.v:147578.18-147578.107" + wire $not$libresoc.v:147578$8147_Y + attribute \src "libresoc.v:147577.18-147577.115" + wire $or$libresoc.v:147577$8146_Y + attribute \src "libresoc.v:147571.18-147571.101" + wire width 65 $pos$libresoc.v:147571$8140_Y + attribute \src "libresoc.v:147574.18-147574.105" + wire $reduce_or$libresoc.v:147574$8143_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 65 \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + wire \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" + wire width 4 \cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 input 20 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 43 \cr_a$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 44 \cr_a_ok + attribute \src "libresoc.v:147260.7-147260.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" + wire \is_cmp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" + wire \is_cmpeqb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" + wire \is_negative + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" + wire \is_nzero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" + wire \is_positive + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" + wire \msb_test + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 47 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 23 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 18 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 41 \o$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" + wire width 65 \o$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 19 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 42 \o_ok$20 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 25 \sr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 26 \sr_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \sr_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 34 \sr_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \sr_op__input_cr$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 17 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 40 \sr_op__insn$18 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute 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attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" + wire \is_cmp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" + wire \is_cmpeqb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" + wire \is_negative + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" + wire \is_nzero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" + wire \is_positive + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 40 \logical_op__data_len$18 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 25 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 26 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 34 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 41 \logical_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 24 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" + wire \msb_test + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 46 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 23 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 19 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 42 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" + wire width 65 \o$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 20 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 43 \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" + wire width 64 \target + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 22 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $and $and$libresoc.v:147932$8159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \B \$36 + connect \Y $and$libresoc.v:147932$8159_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $eq $eq$libresoc.v:147928$8155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \logical_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:147928$8155_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + cell $eq $eq$libresoc.v:147929$8156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \logical_op__insn_type + connect \B 7'0001100 + connect \Y $eq$libresoc.v:147929$8156_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $pos $extend$libresoc.v:147926$8151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \$25 + connect \Y $extend$libresoc.v:147926$8151_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:147927$8153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \o + connect \Y $extend$libresoc.v:147927$8153_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $not $not$libresoc.v:147925$8150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \o + connect \Y $not$libresoc.v:147925$8150_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $not $not$libresoc.v:147931$8158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" + wire \msb_test + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 51 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 24 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 19 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 43 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" + wire width 65 \o$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 20 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 44 \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" + wire \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" + wire \oe$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" + wire \so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" + wire width 64 \target + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 input 22 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 47 \xer_ov$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 48 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 49 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 50 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" + cell $and $and$libresoc.v:148316$8167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \logical_op__oe__oe + connect \B \logical_op__oe__ok + connect \Y $and$libresoc.v:148316$8167_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $and $and$libresoc.v:148324$8177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \B \$40 + connect \Y $and$libresoc.v:148324$8177_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + cell $and $and$libresoc.v:148327$8180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \logical_op__oe__oe + connect \B \logical_op__oe__ok + connect \Y $and$libresoc.v:148327$8180_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $eq $eq$libresoc.v:148320$8173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \logical_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:148320$8173_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + cell $eq $eq$libresoc.v:148321$8174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \logical_op__insn_type + connect \B 7'0001100 + connect \Y $eq$libresoc.v:148321$8174_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $pos $extend$libresoc.v:148318$8169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \$29 + connect \Y $extend$libresoc.v:148318$8169_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:148319$8171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \o + connect \Y $extend$libresoc.v:148319$8171_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $not $not$libresoc.v:148317$8168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \o + connect \Y $not$libresoc.v:148317$8168_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $not $not$libresoc.v:148323$8176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_test + connect \Y $not$libresoc.v:148323$8176_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + cell $not $not$libresoc.v:148326$8179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \Y $not$libresoc.v:148326$8179_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + cell $or $or$libresoc.v:148325$8178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_cmpeqb + connect \B \is_cmp + connect \Y $or$libresoc.v:148325$8178_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" + cell $or $or$libresoc.v:148328$8181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_so + connect \B \xer_ov [0] + connect \Y $or$libresoc.v:148328$8181_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $pos $pos$libresoc.v:148318$8170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:148318$8169_Y + connect \Y $pos$libresoc.v:148318$8170_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $pos$libresoc.v:148319$8172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:148319$8171_Y + connect \Y $pos$libresoc.v:148319$8172_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + cell $reduce_or $reduce_or$libresoc.v:148322$8175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \target + connect \Y $reduce_or$libresoc.v:148322$8175_Y + end + attribute \src "libresoc.v:147977.7-147977.20" + process $proc$libresoc.v:147977$8195 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:148329.3-148340.6" + process $proc$libresoc.v:148329$8182 + assign { } { } + assign $0\so[0:0] $1\so[0:0] + attribute \src "libresoc.v:148330.5-148330.29" + switch \initial + attribute \src "libresoc.v:148330.9-148330.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" + switch \oe + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\so[0:0] \xer_so$24 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\so[0:0] \xer_so + end + sync always + update \so $0\so[0:0] + end + attribute \src "libresoc.v:148341.3-148352.6" + process $proc$libresoc.v:148341$8183 + assign { } { } + assign $0\cr0[3:0] $1\cr0[3:0] + attribute \src "libresoc.v:148342.5-148342.29" + switch \initial + attribute \src "libresoc.v:148342.9-148342.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + switch \$44 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cr0[3:0] \cr_a + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cr0[3:0] { \is_negative \is_positive \$46 \so } + end + sync always + update \cr0 $0\cr0[3:0] + end + attribute \src "libresoc.v:148353.3-148364.6" + process $proc$libresoc.v:148353$8184 + assign { } { } + assign $0\o$27[64:0]$8185 $1\o$27[64:0]$8186 + attribute \src "libresoc.v:148354.5-148354.29" + switch \initial + attribute \src "libresoc.v:148354.9-148354.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" + switch \logical_op__invert_out + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\o$27[64:0]$8186 \$28 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\o$27[64:0]$8186 \$32 + end + sync always + update \o$27 $0\o$27[64:0]$8185 + end + attribute \src "libresoc.v:148365.3-148374.6" + process $proc$libresoc.v:148365$8187 + assign { } { } + assign { } { } + assign $0\xer_so$24[0:0]$8188 $1\xer_so$24[0:0]$8189 + attribute \src "libresoc.v:148366.5-148366.29" + switch \initial + attribute \src "libresoc.v:148366.9-148366.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$48 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_so$24[0:0]$8189 \$51 + case + assign $1\xer_so$24[0:0]$8189 1'0 + end + sync always + update \xer_so$24 $0\xer_so$24[0:0]$8188 + end + attribute \src "libresoc.v:148375.3-148384.6" + process $proc$libresoc.v:148375$8190 + assign { } { } + assign { } { } + assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] + attribute \src "libresoc.v:148376.5-148376.29" + switch \initial + attribute \src "libresoc.v:148376.9-148376.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$48 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_so_ok[0:0] 1'1 + case + assign $1\xer_so_ok[0:0] 1'0 + end + sync always + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:148385.3-148394.6" + process $proc$libresoc.v:148385$8191 + assign { } { } + assign { } { } + assign $0\xer_ov$23[1:0]$8192 $1\xer_ov$23[1:0]$8193 + attribute \src "libresoc.v:148386.5-148386.29" + switch \initial + attribute \src "libresoc.v:148386.9-148386.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$48 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_ov$23[1:0]$8193 \xer_ov + case + assign $1\xer_ov$23[1:0]$8193 2'00 + end + sync always + update \xer_ov$23 $0\xer_ov$23[1:0]$8192 + end + attribute \src "libresoc.v:148395.3-148404.6" + process $proc$libresoc.v:148395$8194 + assign { } { } + assign { } { } + assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:148396.5-148396.29" + switch \initial + attribute \src "libresoc.v:148396.9-148396.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$48 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'1 + case + assign $1\xer_ov_ok[0:0] 1'0 + end + sync always + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + connect \$25 $and$libresoc.v:148316$8167_Y + connect \$29 $not$libresoc.v:148317$8168_Y + connect \$28 $pos$libresoc.v:148318$8170_Y + connect \$32 $pos$libresoc.v:148319$8172_Y + connect \$34 $eq$libresoc.v:148320$8173_Y + connect \$36 $eq$libresoc.v:148321$8174_Y + connect \$38 $reduce_or$libresoc.v:148322$8175_Y + connect \$40 $not$libresoc.v:148323$8176_Y + connect \$42 $and$libresoc.v:148324$8177_Y + connect \$44 $or$libresoc.v:148325$8178_Y + connect \$46 $not$libresoc.v:148326$8179_Y + connect \$49 $and$libresoc.v:148327$8180_Y + connect \$51 $or$libresoc.v:148328$8181_Y + connect \oe$48 \$49 + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit 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"OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 51 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 27 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 46 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 47 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:75" + wire \ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:26" + wire width 65 \quotient_65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:24" + wire \quotient_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 64 input 25 \quotient_root + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" + wire width 192 input 26 \remainder + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:27" + wire width 64 \remainder_64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:25" + wire \remainder_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" + wire width 32 \remainder_s32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:99" + wire width 64 \remainder_s32_as_s64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 48 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 49 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 19 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 50 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" + cell $and $and$libresoc.v:148772$8209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \logical_op__is_signed + connect \B \$38 + connect \Y $and$libresoc.v:148772$8209_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" + cell $pos $extend$libresoc.v:148764$8197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \quotient_root + connect \Y $extend$libresoc.v:148764$8197_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + cell $pos $extend$libresoc.v:148765$8199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \quotient_root + connect \Y $extend$libresoc.v:148765$8199_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + cell $pos $extend$libresoc.v:148767$8202 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \remainder [127:64] + connect \Y $extend$libresoc.v:148767$8202_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $extend$libresoc.v:148768$8204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \remainder [127:64] + connect \Y $extend$libresoc.v:148768$8204_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" + cell $pos $extend$libresoc.v:148776$8213 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_65 [31:0] + connect \Y $extend$libresoc.v:148776$8213_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" + cell $pos $extend$libresoc.v:148777$8215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_65 [31:0] + connect \Y $extend$libresoc.v:148777$8215_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" + cell $pos $extend$libresoc.v:148778$8217 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_65 [31:0] + connect \Y $extend$libresoc.v:148778$8217_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" + cell $pos $extend$libresoc.v:148779$8219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_65 [31:0] + connect \Y $extend$libresoc.v:148779$8219_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" + cell $pos $extend$libresoc.v:148780$8221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \remainder_64 [31:0] + connect \Y $extend$libresoc.v:148780$8221_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" + cell $ne $ne$libresoc.v:148773$8210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \quotient_65 [32] + connect \B \quotient_65 [31] + connect \Y $ne$libresoc.v:148773$8210_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" + cell $neg $neg$libresoc.v:148764$8198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:148764$8197_Y + connect \Y $neg$libresoc.v:148764$8198_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + cell $neg $neg$libresoc.v:148767$8203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:148767$8202_Y + connect \Y $neg$libresoc.v:148767$8203_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" + cell $not $not$libresoc.v:148770$8207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \logical_op__is_32bit + connect \Y $not$libresoc.v:148770$8207_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" + cell $not $not$libresoc.v:148775$8212 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ov + connect \Y $not$libresoc.v:148775$8212_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + cell $pos $pos$libresoc.v:148765$8200 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:148765$8199_Y + connect \Y $pos$libresoc.v:148765$8200_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $pos$libresoc.v:148768$8205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:148768$8204_Y + connect \Y $pos$libresoc.v:148768$8205_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" + cell $pos $pos$libresoc.v:148774$8211 + parameter \A_SIGNED 1 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 } + connect \Y $pos$libresoc.v:148774$8211_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" + cell $pos $pos$libresoc.v:148776$8214 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:148776$8213_Y + connect \Y $pos$libresoc.v:148776$8214_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" + cell $pos $pos$libresoc.v:148777$8216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:148777$8215_Y + connect \Y $pos$libresoc.v:148777$8216_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" + cell $pos $pos$libresoc.v:148778$8218 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:148778$8217_Y + connect \Y $pos$libresoc.v:148778$8218_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" + cell $pos $pos$libresoc.v:148779$8220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:148779$8219_Y + connect \Y $pos$libresoc.v:148779$8220_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" + cell $pos $pos$libresoc.v:148780$8222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:148780$8221_Y + connect \Y $pos$libresoc.v:148780$8222_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" + cell $mux $ternary$libresoc.v:148766$8201 + parameter \WIDTH 65 + connect \A \$25 + connect \B \$23 + connect \S \quotient_neg + connect \Y $ternary$libresoc.v:148766$8201_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + cell $mux $ternary$libresoc.v:148769$8206 + parameter \WIDTH 65 + connect \A \$32 + connect \B \$30 + connect \S \remainder_neg + connect \Y $ternary$libresoc.v:148769$8206_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" + cell $xor $xor$libresoc.v:148763$8196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dividend_neg + connect \B \divisor_neg + connect \Y $xor$libresoc.v:148763$8196_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" + cell $xor $xor$libresoc.v:148771$8208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \quotient_65 [64] + connect \B \quotient_65 [63] + connect \Y $xor$libresoc.v:148771$8208_Y + end + attribute \src "libresoc.v:148425.7-148425.20" + process $proc$libresoc.v:148425$8225 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:148781.3-148852.6" + process $proc$libresoc.v:148781$8223 + assign { } { } + assign { } { } + assign $0\o[63:0] $1\o[63:0] + attribute \src "libresoc.v:148782.5-148782.29" + switch \initial + attribute \src "libresoc.v:148782.9-148782.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" + switch \$46 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\o[63:0] $2\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:103" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0011110 + assign { } { } + assign $2\o[63:0] $3\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:105" + switch \logical_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\o[63:0] $4\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:106" + switch \logical_op__is_signed + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\o[63:0] \$48 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\o[63:0] \$50 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\o[63:0] \quotient_65 [63:0] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'0011101 + assign { } { } + assign $2\o[63:0] $5\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:114" + switch \logical_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\o[63:0] $6\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:115" + switch \logical_op__is_signed + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\o[63:0] \$52 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $6\o[63:0] \$54 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $5\o[63:0] \quotient_65 [63:0] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'0101111 + assign { } { } + assign $2\o[63:0] $7\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:123" + switch \logical_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\o[63:0] $8\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:124" + switch \logical_op__is_signed + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\o[63:0] \remainder_s32_as_s64 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $8\o[63:0] \$56 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $7\o[63:0] \remainder_64 + end + case + assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \o $0\o[63:0] + end + attribute \src "libresoc.v:148853.3-148886.6" + process $proc$libresoc.v:148853$8224 + assign { } { } + assign $0\ov[0:0] $1\ov[0:0] + attribute \src "libresoc.v:148854.5-148854.29" + switch \initial + attribute \src "libresoc.v:148854.9-148854.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:76" + switch { \logical_op__is_signed \$36 \div_by_zero } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\ov[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign { } { } + assign $1\ov[0:0] $2\ov[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" + switch \$40 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ov[0:0] 1'1 + case + assign $2\ov[0:0] \dive_abs_ov64 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign { } { } + assign $1\ov[0:0] $3\ov[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" + switch \$42 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ov[0:0] 1'1 + case + assign $3\ov[0:0] \dive_abs_ov32 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\ov[0:0] \dive_abs_ov32 + end + sync always + update \ov $0\ov[0:0] + end + connect \$21 $xor$libresoc.v:148763$8196_Y + connect \$23 $neg$libresoc.v:148764$8198_Y + connect \$25 $pos$libresoc.v:148765$8200_Y + connect \$27 $ternary$libresoc.v:148766$8201_Y + connect \$30 $neg$libresoc.v:148767$8203_Y + connect \$32 $pos$libresoc.v:148768$8205_Y + connect \$34 $ternary$libresoc.v:148769$8206_Y + connect \$36 $not$libresoc.v:148770$8207_Y + connect \$38 $xor$libresoc.v:148771$8208_Y + connect \$40 $and$libresoc.v:148772$8209_Y + connect \$42 $ne$libresoc.v:148773$8210_Y + connect \$44 $pos$libresoc.v:148774$8211_Y + connect \$46 $not$libresoc.v:148775$8212_Y + connect \$48 $pos$libresoc.v:148776$8214_Y + connect \$50 $pos$libresoc.v:148777$8216_Y + connect \$52 $pos$libresoc.v:148778$8218_Y + connect \$54 $pos$libresoc.v:148779$8220_Y + connect \$56 $pos$libresoc.v:148780$8222_Y + connect \$29 \$34 + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$20 \xer_so + connect \remainder_s32_as_s64 \$44 + connect \remainder_s32 \remainder_64 [31:0] + connect \o_ok 1'1 + connect \xer_ov { \ov \ov } + connect \xer_ov_ok 1'1 + connect \remainder_64 \$34 [63:0] + connect \quotient_65 \$27 + connect \remainder_neg \dividend_neg + connect \quotient_neg \$21 +end +attribute \src "libresoc.v:148904.1-148915.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.p" +attribute \generator "nMigen" +module \p + attribute \src "libresoc.v:148913.17-148913.111" + wire $and$libresoc.v:148913$8226_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $and$libresoc.v:148913$8226 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:148913$8226_Y + end + connect \$1 $and$libresoc.v:148913$8226_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:148919.1-148930.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.p" +attribute \generator "nMigen" +module \p$1 + attribute \src "libresoc.v:148928.17-148928.111" + wire $and$libresoc.v:148928$8227_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src 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\reset_l_q_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \reset_l_r_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \reset_l_s_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \st_active_q_st_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \st_active_r_st_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \st_active_s_st_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \st_done_q_st_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \st_done_r_st_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \st_done_s_st_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \st_done_s_st_done$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:270" + wire width 64 \stdata + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207" + wire \sts + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \sts_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \sts_dly$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \sts_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \valid_l_q_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \valid_l_r_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \valid_l_s_valid + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" + wire width 48 output 9 \x_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:66" + wire input 17 \x_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52" + wire output 19 \x_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51" + wire width 8 output 8 \x_mask_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:54" + wire width 64 output 16 \x_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53" + wire output 20 \x_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" + wire output 22 \x_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" + cell $and $and$libresoc.v:149568$8256 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_busy_o + connect \B \$9 + connect \Y $and$libresoc.v:149568$8256_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:149570$8258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lds + connect \B \$13 + connect \Y $and$libresoc.v:149570$8258_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" + cell $and $and$libresoc.v:149572$8260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \st_active_q_st_active + connect \B \ldst_port0_st_data_i_ok + connect \Y $and$libresoc.v:149572$8260_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:149573$8261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sts + connect \B \$17 + connect \Y $and$libresoc.v:149573$8261_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + cell $and $and$libresoc.v:149576$8266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_addr_i_ok + connect \B \adrok_l_qn_addr_acked + connect \Y $and$libresoc.v:149576$8266_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + cell $and $and$libresoc.v:149577$8267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_addr_i_ok + connect \B \adrok_l_qn_addr_acked + connect \Y $and$libresoc.v:149577$8267_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + cell $and $and$libresoc.v:149578$8268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_addr_i_ok + connect \B \adrok_l_qn_addr_acked + connect \Y $and$libresoc.v:149578$8268_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + cell $and $and$libresoc.v:149579$8269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_addr_i_ok + connect \B \adrok_l_qn_addr_acked + connect \Y $and$libresoc.v:149579$8269_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" + cell $and $and$libresoc.v:149580$8270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ld_active_q_ld_active + connect \B \adrok_l_q_addr_acked + connect \Y $and$libresoc.v:149580$8270_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:257" + cell $and $and$libresoc.v:149585$8275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 176 + parameter \Y_WIDTH 176 + connect \A \m_ld_data_o + connect \B \lenexp_rexp_o + connect \Y $and$libresoc.v:149585$8275_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" + cell $and $and$libresoc.v:149588$8278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ld_active_q_ld_active + connect \B \adrok_l_q_addr_acked + connect \Y $and$libresoc.v:149588$8278_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" + cell $and $and$libresoc.v:149589$8279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ld_active_q_ld_active + connect \B \adrok_l_q_addr_acked + connect \Y $and$libresoc.v:149589$8279_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" + cell $and $and$libresoc.v:149591$8281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \st_active_q_st_active + connect \B \ldst_port0_st_data_i_ok + connect \Y $and$libresoc.v:149591$8281_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" + cell $and $and$libresoc.v:149595$8285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \st_active_q_st_active + connect \B \ldst_port0_st_data_i_ok + connect \Y $and$libresoc.v:149595$8285_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + cell $and $and$libresoc.v:149597$8287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$63 + connect \B \valid_l_q_valid + connect \Y $and$libresoc.v:149597$8287_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + cell $and $and$libresoc.v:149599$8289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$67 + connect \B \valid_l_q_valid + connect \Y $and$libresoc.v:149599$8289_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" + cell $and $and$libresoc.v:149603$8293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$73 + connect \B \$75 + connect \Y $and$libresoc.v:149603$8293_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + cell $and $and$libresoc.v:149604$8294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_addr_i_ok + connect \B \adrok_l_qn_addr_acked + connect \Y $and$libresoc.v:149604$8294_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:149607$8297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lsui_active + connect \B \$81 + connect \Y $and$libresoc.v:149607$8297_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $extend$libresoc.v:149574$8262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A \ldst_port0_addr_i [2:0] + connect \Y $extend$libresoc.v:149574$8262_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $extend$libresoc.v:149575$8264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A \ldst_port0_addr_i [2:0] + connect \Y $extend$libresoc.v:149575$8264_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" + cell $mul $mul$libresoc.v:149586$8276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \lenexp_addr_i + connect \B 4'1000 + connect \Y $mul$libresoc.v:149586$8276_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" + cell $mul $mul$libresoc.v:149592$8282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \lenexp_addr_i + connect \B 4'1000 + connect \Y $mul$libresoc.v:149592$8282_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" + cell $not $not$libresoc.v:149567$8255 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \busy_delay + connect \Y $not$libresoc.v:149567$8255_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:149569$8257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lds_dly + connect \Y $not$libresoc.v:149569$8257_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:149571$8259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sts_dly + connect \Y $not$libresoc.v:149571$8259_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" + cell $not $not$libresoc.v:149581$8271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lsui_busy + connect \Y $not$libresoc.v:149581$8271_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" + cell $not $not$libresoc.v:149584$8274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$38 + connect \Y $not$libresoc.v:149584$8274_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" + cell $not $not$libresoc.v:149590$8280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lsui_busy + connect \Y $not$libresoc.v:149590$8280_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:224" + cell $not $not$libresoc.v:149593$8283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \busy_delay + connect \Y $not$libresoc.v:149593$8283_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" + cell $not $not$libresoc.v:149600$8290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_busy_o + connect \Y $not$libresoc.v:149600$8290_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" + cell $not $not$libresoc.v:149601$8291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_is_st_i + connect \Y $not$libresoc.v:149601$8291_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" + cell $not $not$libresoc.v:149602$8292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_busy_o + connect \Y $not$libresoc.v:149602$8292_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:108" + cell $not $not$libresoc.v:149605$8295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_busy_o + connect \Y $not$libresoc.v:149605$8295_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:149606$8296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lsui_active_dly + connect \Y $not$libresoc.v:149606$8296_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" + cell $or $or$libresoc.v:149582$8272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_busy_o + connect \B \lsui_busy + connect \Y $or$libresoc.v:149582$8272_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" + cell $or $or$libresoc.v:149583$8273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_is_ld_i + connect \B \ldst_port0_is_st_i + connect \Y $or$libresoc.v:149583$8273_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + cell $or $or$libresoc.v:149596$8286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_is_ld_i + connect \B \ldst_port0_is_st_i + connect \Y $or$libresoc.v:149596$8286_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + cell $or $or$libresoc.v:149598$8288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_is_ld_i + connect \B \ldst_port0_is_st_i + connect \Y $or$libresoc.v:149598$8288_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $pos$libresoc.v:149574$8263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $extend$libresoc.v:149574$8262_Y + connect \Y $pos$libresoc.v:149574$8263_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $pos$libresoc.v:149575$8265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $extend$libresoc.v:149575$8264_Y + connect \Y $pos$libresoc.v:149575$8265_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" + cell $sshl $sshl$libresoc.v:149594$8284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 319 + connect \A \ldst_port0_st_data_i + connect \B \$57 + connect \Y $sshl$libresoc.v:149594$8284_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" + cell $sshr $sshr$libresoc.v:149587$8277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 176 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 176 + connect \A \$42 + connect \B \$44 + connect \Y $sshr$libresoc.v:149587$8277_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:149624.11-149631.4" + cell \adrok_l \adrok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_addr_acked \adrok_l_q_addr_acked + connect \qn_addr_acked \adrok_l_qn_addr_acked + connect \r_addr_acked \adrok_l_r_addr_acked + connect \s_addr_acked \adrok_l_s_addr_acked + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:149632.10-149638.4" + cell \busy_l \busy_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_busy \busy_l_q_busy + connect \r_busy \busy_l_r_busy + connect \s_busy \busy_l_s_busy + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:149639.9-149645.4" + cell \cyc_l \cyc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_cyc \cyc_l_q_cyc + connect \r_cyc \cyc_l_r_cyc + connect \s_cyc \cyc_l_s_cyc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:149646.13-149652.4" + cell \ld_active \ld_active + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_ld_active \ld_active_q_ld_active + connect \r_ld_active \ld_active_r_ld_active + connect \s_ld_active \ld_active_s_ld_active + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:149653.10-149658.4" + cell \lenexp \lenexp + connect \addr_i \lenexp_addr_i + connect \len_i \lenexp_len_i + connect \lexp_o \lenexp_lexp_o + connect \rexp_o \lenexp_rexp_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:149659.11-149665.4" + cell \reset_l \reset_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_reset \reset_l_q_reset + connect \r_reset \reset_l_r_reset + connect \s_reset \reset_l_s_reset + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:149666.13-149672.4" + cell \st_active \st_active + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_st_active \st_active_q_st_active + connect \r_st_active \st_active_r_st_active + connect \s_st_active \st_active_s_st_active + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:149673.11-149679.4" + cell \st_done \st_done + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_st_done \st_done_q_st_done + connect \r_st_done \st_done_r_st_done + connect \s_st_done \st_done_s_st_done + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:149680.11-149686.4" + cell \valid_l \valid_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_valid \valid_l_q_valid + connect \r_valid \valid_l_r_valid + connect \s_valid \valid_l_s_valid + end + attribute \src "libresoc.v:149322.7-149322.20" + process $proc$libresoc.v:149322$8352 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:149416.7-149416.34" + process $proc$libresoc.v:149416$8353 + assign { } { } + assign $1\adrok_l_s_addr_acked[0:0] 1'0 + sync always + sync init + update \adrok_l_s_addr_acked $1\adrok_l_s_addr_acked[0:0] + end + attribute \src "libresoc.v:149420.7-149420.24" + process $proc$libresoc.v:149420$8354 + assign { } { } + assign $1\busy_delay[0:0] 1'0 + sync always + sync init + update \busy_delay $1\busy_delay[0:0] + end + attribute \src "libresoc.v:149442.13-149442.29" + process $proc$libresoc.v:149442$8355 + assign { } { } + assign $1\fsm_state[1:0] 2'00 + sync always + sync init + update \fsm_state $1\fsm_state[1:0] + end + attribute \src "libresoc.v:149456.7-149456.21" + process $proc$libresoc.v:149456$8356 + assign { } { } + assign $1\lds_dly[0:0] 1'0 + sync always + sync init + update \lds_dly $1\lds_dly[0:0] + end + attribute \src "libresoc.v:149499.7-149499.29" + process $proc$libresoc.v:149499$8357 + assign { } { } + assign $1\lsui_active_dly[0:0] 1'0 + sync always + sync init + update \lsui_active_dly $1\lsui_active_dly[0:0] + end + attribute \src "libresoc.v:149511.7-149511.25" + process $proc$libresoc.v:149511$8358 + assign { } { } + assign $1\reset_delay[0:0] 1'0 + sync always + sync init + update \reset_delay $1\reset_delay[0:0] + end + attribute \src "libresoc.v:149531.7-149531.31" + process $proc$libresoc.v:149531$8359 + assign { } { } + assign $1\st_done_s_st_done[0:0] 1'0 + sync always + sync init + update \st_done_s_st_done $1\st_done_s_st_done[0:0] + end + attribute \src "libresoc.v:149539.7-149539.21" + process $proc$libresoc.v:149539$8360 + assign { } { } + assign $1\sts_dly[0:0] 1'0 + sync always + sync init + update \sts_dly $1\sts_dly[0:0] + end + attribute \src "libresoc.v:149608.3-149609.47" + process $proc$libresoc.v:149608$8298 + assign { } { } + assign $0\lsui_active_dly[0:0] \lsui_active_dly$next + sync posedge \coresync_clk + update \lsui_active_dly $0\lsui_active_dly[0:0] + end + attribute \src "libresoc.v:149610.3-149611.35" + process $proc$libresoc.v:149610$8299 + assign { } { } + assign $0\fsm_state[1:0] \fsm_state$next + sync posedge \coresync_clk + update \fsm_state $0\fsm_state[1:0] + end + attribute \src "libresoc.v:149612.3-149613.36" + process $proc$libresoc.v:149612$8300 + assign { } { } + assign $0\reset_delay[0:0] \reset_l_q_reset + sync posedge \coresync_clk + update \reset_delay $0\reset_delay[0:0] + end + attribute \src "libresoc.v:149614.3-149615.35" + process $proc$libresoc.v:149614$8301 + assign { } { } + assign $0\sts_dly[0:0] \ldst_port0_is_st_i + sync posedge \coresync_clk + update \sts_dly $0\sts_dly[0:0] + end + attribute \src "libresoc.v:149616.3-149617.35" + process $proc$libresoc.v:149616$8302 + assign { } { } + assign $0\lds_dly[0:0] \ldst_port0_is_ld_i + sync posedge \coresync_clk + update \lds_dly $0\lds_dly[0:0] + end + attribute \src "libresoc.v:149618.3-149619.37" + process $proc$libresoc.v:149618$8303 + assign { } { } + assign $0\busy_delay[0:0] \busy_delay$next + sync posedge \coresync_clk + update \busy_delay $0\busy_delay[0:0] + end + attribute \src "libresoc.v:149620.3-149621.57" + process $proc$libresoc.v:149620$8304 + assign { } { } + assign $0\adrok_l_s_addr_acked[0:0] \adrok_l_s_addr_acked$next + sync posedge \coresync_clk + update \adrok_l_s_addr_acked $0\adrok_l_s_addr_acked[0:0] + end + attribute \src "libresoc.v:149622.3-149623.51" + process $proc$libresoc.v:149622$8305 + assign { } { } + assign $0\st_done_s_st_done[0:0] \st_done_s_st_done$next + sync posedge \coresync_clk + update \st_done_s_st_done $0\st_done_s_st_done[0:0] + end + attribute \src "libresoc.v:149687.3-149701.6" + process $proc$libresoc.v:149687$8306 + assign { } { } + assign { } { } + assign { } { } + assign $0\st_done_s_st_done$next[0:0]$8307 $2\st_done_s_st_done$next[0:0]$8309 + attribute \src "libresoc.v:149688.5-149688.29" + switch \initial + attribute \src "libresoc.v:149688.9-149688.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\st_done_s_st_done$next[0:0]$8308 1'1 + case + assign $1\st_done_s_st_done$next[0:0]$8308 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\st_done_s_st_done$next[0:0]$8309 1'0 + case + assign $2\st_done_s_st_done$next[0:0]$8309 $1\st_done_s_st_done$next[0:0]$8308 + end + sync always + update \st_done_s_st_done$next $0\st_done_s_st_done$next[0:0]$8307 + end + attribute \src "libresoc.v:149702.3-149711.6" + process $proc$libresoc.v:149702$8310 + assign { } { } + assign { } { } + assign $0\st_done_r_st_done[0:0] $1\st_done_r_st_done[0:0] + attribute \src "libresoc.v:149703.5-149703.29" + switch \initial + attribute \src "libresoc.v:149703.9-149703.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" + switch \reset_l_q_reset + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\st_done_r_st_done[0:0] 1'1 + case + assign $1\st_done_r_st_done[0:0] 1'0 + end + sync always + update \st_done_r_st_done $0\st_done_r_st_done[0:0] + end + attribute \src "libresoc.v:149712.3-149720.6" + process $proc$libresoc.v:149712$8311 + assign { } { } + assign { } { } + assign $0\busy_delay$next[0:0]$8312 $1\busy_delay$next[0:0]$8313 + attribute \src "libresoc.v:149713.5-149713.29" + switch \initial + attribute \src "libresoc.v:149713.9-149713.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\busy_delay$next[0:0]$8313 1'0 + case + assign $1\busy_delay$next[0:0]$8313 \ldst_port0_busy_o + end + sync always + update \busy_delay$next $0\busy_delay$next[0:0]$8312 + end + attribute \src "libresoc.v:149721.3-149730.6" + process $proc$libresoc.v:149721$8314 + assign { } { } + assign { } { } + assign $0\st_active_r_st_active[0:0] $1\st_active_r_st_active[0:0] + attribute \src "libresoc.v:149722.5-149722.29" + switch \initial + attribute \src "libresoc.v:149722.9-149722.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" + switch \reset_l_q_reset + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\st_active_r_st_active[0:0] 1'1 + case + assign $1\st_active_r_st_active[0:0] 1'0 + end + sync always + update \st_active_r_st_active $0\st_active_r_st_active[0:0] + end + attribute \src "libresoc.v:149731.3-149746.6" + process $proc$libresoc.v:149731$8315 + assign { } { } + assign { } { } + assign { } { } + assign $0\lenexp_len_i[3:0] $2\lenexp_len_i[3:0] + attribute \src "libresoc.v:149732.5-149732.29" + switch \initial + attribute \src "libresoc.v:149732.9-149732.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch \ld_active_q_ld_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\lenexp_len_i[3:0] \ldst_port0_data_len + case + assign $1\lenexp_len_i[3:0] 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" + switch \st_active_q_st_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\lenexp_len_i[3:0] \ldst_port0_data_len + case + assign $2\lenexp_len_i[3:0] $1\lenexp_len_i[3:0] + end + sync always + update \lenexp_len_i $0\lenexp_len_i[3:0] + end + attribute \src "libresoc.v:149747.3-149762.6" + process $proc$libresoc.v:149747$8316 + assign { } { } + assign { } { } + assign { } { } + assign $0\lenexp_addr_i[3:0] $2\lenexp_addr_i[3:0] + attribute \src "libresoc.v:149748.5-149748.29" + switch \initial + attribute \src "libresoc.v:149748.9-149748.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch \ld_active_q_ld_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\lenexp_addr_i[3:0] \$21 + case + assign $1\lenexp_addr_i[3:0] 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" + switch \st_active_q_st_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\lenexp_addr_i[3:0] \$23 + case + assign $2\lenexp_addr_i[3:0] $1\lenexp_addr_i[3:0] + end + sync always + update \lenexp_addr_i $0\lenexp_addr_i[3:0] + end + attribute \src "libresoc.v:149763.3-149788.6" + process $proc$libresoc.v:149763$8317 + assign { } { } + assign { } { } + assign { } { } + assign $0\valid_l_s_valid[0:0] $3\valid_l_s_valid[0:0] + attribute \src "libresoc.v:149764.5-149764.29" + switch \initial + attribute \src "libresoc.v:149764.9-149764.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch \ld_active_q_ld_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\valid_l_s_valid[0:0] $2\valid_l_s_valid[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\valid_l_s_valid[0:0] 1'1 + case + assign $2\valid_l_s_valid[0:0] 1'0 + end + case + assign $1\valid_l_s_valid[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" + switch \st_active_q_st_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\valid_l_s_valid[0:0] $4\valid_l_s_valid[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" + switch \ldst_port0_addr_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\valid_l_s_valid[0:0] 1'1 + case + assign $4\valid_l_s_valid[0:0] $1\valid_l_s_valid[0:0] + end + case + assign $3\valid_l_s_valid[0:0] $1\valid_l_s_valid[0:0] + end + sync always + update \valid_l_s_valid $0\valid_l_s_valid[0:0] + end + attribute \src "libresoc.v:149789.3-149814.6" + process $proc$libresoc.v:149789$8318 + assign { } { } + assign { } { } + assign { } { } + assign $0\x_mask_i[7:0] $3\x_mask_i[7:0] + attribute \src "libresoc.v:149790.5-149790.29" + switch \initial + attribute \src "libresoc.v:149790.9-149790.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch \ld_active_q_ld_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\x_mask_i[7:0] $2\x_mask_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\x_mask_i[7:0] \lenexp_lexp_o [7:0] + case + assign $2\x_mask_i[7:0] 8'00000000 + end + case + assign $1\x_mask_i[7:0] 8'00000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" + switch \st_active_q_st_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\x_mask_i[7:0] $4\x_mask_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" + switch \ldst_port0_addr_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\x_mask_i[7:0] \lenexp_lexp_o [7:0] + case + assign $4\x_mask_i[7:0] $1\x_mask_i[7:0] + end + case + assign $3\x_mask_i[7:0] $1\x_mask_i[7:0] + end + sync always + update \x_mask_i $0\x_mask_i[7:0] + end + attribute \src "libresoc.v:149815.3-149840.6" + process $proc$libresoc.v:149815$8319 + assign { } { } + assign { } { } + assign { } { } + assign $0\x_addr_i[47:0] $3\x_addr_i[47:0] + attribute \src "libresoc.v:149816.5-149816.29" + switch \initial + attribute \src "libresoc.v:149816.9-149816.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch \ld_active_q_ld_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\x_addr_i[47:0] $2\x_addr_i[47:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\x_addr_i[47:0] \ldst_port0_addr_i + case + assign $2\x_addr_i[47:0] 48'000000000000000000000000000000000000000000000000 + end + case + assign $1\x_addr_i[47:0] 48'000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" + switch \st_active_q_st_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\x_addr_i[47:0] $4\x_addr_i[47:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" + switch \ldst_port0_addr_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\x_addr_i[47:0] \ldst_port0_addr_i + case + assign $4\x_addr_i[47:0] $1\x_addr_i[47:0] + end + case + assign $3\x_addr_i[47:0] $1\x_addr_i[47:0] + end + sync always + update \x_addr_i $0\x_addr_i[47:0] + end + attribute \src "libresoc.v:149841.3-149871.6" + process $proc$libresoc.v:149841$8320 + assign { } { } + assign { } { } + assign { } { } + assign $0\ldst_port0_addr_ok_o[0:0] $3\ldst_port0_addr_ok_o[0:0] + attribute \src "libresoc.v:149842.5-149842.29" + switch \initial + attribute \src "libresoc.v:149842.9-149842.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch \ld_active_q_ld_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_addr_ok_o[0:0] $2\ldst_port0_addr_ok_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + switch \$31 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ldst_port0_addr_ok_o[0:0] 1'1 + case + assign $2\ldst_port0_addr_ok_o[0:0] 1'0 + end + case + assign $1\ldst_port0_addr_ok_o[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" + switch \st_active_q_st_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ldst_port0_addr_ok_o[0:0] $4\ldst_port0_addr_ok_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" + switch \ldst_port0_addr_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\ldst_port0_addr_ok_o[0:0] $5\ldst_port0_addr_ok_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" + switch \adrok_l_qn_addr_acked + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\ldst_port0_addr_ok_o[0:0] 1'1 + case + assign $5\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] + end + case + assign $4\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] + end + case + assign $3\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] + end + sync always + update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] + end + attribute \src "libresoc.v:149872.3-149887.6" + process $proc$libresoc.v:149872$8321 + assign { } { } + assign { } { } + assign { } { } + assign $0\reset_l_s_reset[0:0] $2\reset_l_s_reset[0:0] + attribute \src "libresoc.v:149873.5-149873.29" + switch \initial + attribute \src "libresoc.v:149873.9-149873.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" + switch \$33 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reset_l_s_reset[0:0] \$35 + case + assign $1\reset_l_s_reset[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:276" + switch \st_done_q_st_done + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reset_l_s_reset[0:0] \$37 + case + assign $2\reset_l_s_reset[0:0] $1\reset_l_s_reset[0:0] + end + sync always + update \reset_l_s_reset $0\reset_l_s_reset[0:0] + end + attribute \src "libresoc.v:149888.3-149897.6" + process $proc$libresoc.v:149888$8322 + assign { } { } + assign { } { } + assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] + attribute \src "libresoc.v:149889.5-149889.29" + switch \initial + attribute \src "libresoc.v:149889.9-149889.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" + switch \reset_l_q_reset + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reset_l_r_reset[0:0] 1'1 + case + assign $1\reset_l_r_reset[0:0] 1'0 + end + sync always + update \reset_l_r_reset $0\reset_l_r_reset[0:0] + end + attribute \src "libresoc.v:149898.3-149907.6" + process $proc$libresoc.v:149898$8323 + assign { } { } + assign { } { } + assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] + attribute \src "libresoc.v:149899.5-149899.29" + switch \initial + attribute \src "libresoc.v:149899.9-149899.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" + switch \$48 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_ld_data_o[63:0] \lddata + case + assign $1\ldst_port0_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] + end + attribute \src "libresoc.v:149908.3-149917.6" + process $proc$libresoc.v:149908$8324 + assign { } { } + assign { } { } + assign $0\ld_active_r_ld_active[0:0] $1\ld_active_r_ld_active[0:0] + attribute \src "libresoc.v:149909.5-149909.29" + switch \initial + attribute \src "libresoc.v:149909.9-149909.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" + switch \reset_l_q_reset + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ld_active_r_ld_active[0:0] 1'1 + case + assign $1\ld_active_r_ld_active[0:0] 1'0 + end + sync always + update \ld_active_r_ld_active $0\ld_active_r_ld_active[0:0] + end + attribute \src "libresoc.v:149918.3-149927.6" + process $proc$libresoc.v:149918$8325 + assign { } { } + assign { } { } + assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] + attribute \src "libresoc.v:149919.5-149919.29" + switch \initial + attribute \src "libresoc.v:149919.9-149919.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" + switch \$50 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_ld_data_o_ok[0:0] \$52 + case + assign $1\ldst_port0_ld_data_o_ok[0:0] 1'0 + end + sync always + update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] + end + attribute \src "libresoc.v:149928.3-149937.6" + process $proc$libresoc.v:149928$8326 + assign { } { } + assign { } { } + assign $0\stdata[63:0] $1\stdata[63:0] + attribute \src "libresoc.v:149929.5-149929.29" + switch \initial + attribute \src "libresoc.v:149929.9-149929.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" + switch \$54 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\stdata[63:0] \$56 [63:0] + case + assign $1\stdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \stdata $0\stdata[63:0] + end + attribute \src "libresoc.v:149938.3-149947.6" + process $proc$libresoc.v:149938$8327 + assign { } { } + assign { } { } + assign $0\x_st_data_i[63:0] $1\x_st_data_i[63:0] + attribute \src "libresoc.v:149939.5-149939.29" + switch \initial + attribute \src "libresoc.v:149939.9-149939.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" + switch \$61 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\x_st_data_i[63:0] \stdata + case + assign $1\x_st_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \x_st_data_i $0\x_st_data_i[63:0] + end + attribute \src "libresoc.v:149948.3-149967.6" + process $proc$libresoc.v:149948$8328 + assign { } { } + assign { } { } + assign $0\lsui_busy[0:0] $1\lsui_busy[0:0] + attribute \src "libresoc.v:149949.5-149949.29" + switch \initial + attribute \src "libresoc.v:149949.9-149949.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\lsui_busy[0:0] $2\lsui_busy[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + switch \$65 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\lsui_busy[0:0] 1'1 + case + assign $2\lsui_busy[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\lsui_busy[0:0] 1'1 + case + assign $1\lsui_busy[0:0] 1'0 + end + sync always + update \lsui_busy $0\lsui_busy[0:0] + end + attribute \src "libresoc.v:149968.3-150006.6" + process $proc$libresoc.v:149968$8329 + assign { } { } + assign { } { } + assign { } { } + assign $0\fsm_state$next[1:0]$8330 $5\fsm_state$next[1:0]$8335 + attribute \src "libresoc.v:149969.5-149969.29" + switch \initial + attribute \src "libresoc.v:149969.9-149969.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\fsm_state$next[1:0]$8331 $2\fsm_state$next[1:0]$8332 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + switch \$69 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fsm_state$next[1:0]$8332 2'01 + case + assign $2\fsm_state$next[1:0]$8332 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\fsm_state$next[1:0]$8331 $3\fsm_state$next[1:0]$8333 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" + switch \$71 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fsm_state$next[1:0]$8333 2'10 + case + assign $3\fsm_state$next[1:0]$8333 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\fsm_state$next[1:0]$8331 $4\fsm_state$next[1:0]$8334 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" + switch \$77 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$next[1:0]$8334 2'00 + case + assign $4\fsm_state$next[1:0]$8334 \fsm_state + end + case + assign $1\fsm_state$next[1:0]$8331 \fsm_state + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fsm_state$next[1:0]$8335 2'00 + case + assign $5\fsm_state$next[1:0]$8335 $1\fsm_state$next[1:0]$8331 + end + sync always + update \fsm_state$next $0\fsm_state$next[1:0]$8330 + end + attribute \src "libresoc.v:150007.3-150016.6" + process $proc$libresoc.v:150007$8336 + assign { } { } + assign { } { } + assign $0\cyc_l_s_cyc[0:0] $1\cyc_l_s_cyc[0:0] + attribute \src "libresoc.v:150008.5-150008.29" + switch \initial + attribute \src "libresoc.v:150008.9-150008.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:299" + switch \reset_l_s_reset + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cyc_l_s_cyc[0:0] 1'1 + case + assign $1\cyc_l_s_cyc[0:0] 1'0 + end + sync always + update \cyc_l_s_cyc $0\cyc_l_s_cyc[0:0] + end + attribute \src "libresoc.v:150017.3-150025.6" + process $proc$libresoc.v:150017$8337 + assign { } { } + assign { } { } + assign $0\lsui_active_dly$next[0:0]$8338 $1\lsui_active_dly$next[0:0]$8339 + attribute \src "libresoc.v:150018.5-150018.29" + switch \initial + attribute \src "libresoc.v:150018.9-150018.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\lsui_active_dly$next[0:0]$8339 1'0 + case + assign $1\lsui_active_dly$next[0:0]$8339 \lsui_active + end + sync always + update \lsui_active_dly$next $0\lsui_active_dly$next[0:0]$8338 + end + attribute \src "libresoc.v:150026.3-150035.6" + process $proc$libresoc.v:150026$8340 + assign { } { } + assign { } { } + assign $0\cyc_l_r_cyc[0:0] $1\cyc_l_r_cyc[0:0] + attribute \src "libresoc.v:150027.5-150027.29" + switch \initial + attribute \src "libresoc.v:150027.9-150027.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:302" + switch \cyc_l_q_cyc + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cyc_l_r_cyc[0:0] 1'1 + case + assign $1\cyc_l_r_cyc[0:0] 1'0 + end + sync always + update \cyc_l_r_cyc $0\cyc_l_r_cyc[0:0] + end + attribute \src "libresoc.v:150036.3-150045.6" + process $proc$libresoc.v:150036$8341 + assign { } { } + assign { } { } + assign $0\busy_l_s_busy[0:0] $1\busy_l_s_busy[0:0] + attribute \src "libresoc.v:150037.5-150037.29" + switch \initial + attribute \src "libresoc.v:150037.9-150037.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\busy_l_s_busy[0:0] \$5 + case + assign $1\busy_l_s_busy[0:0] 1'0 + end + sync always + update \busy_l_s_busy $0\busy_l_s_busy[0:0] + end + attribute \src "libresoc.v:150046.3-150061.6" + process $proc$libresoc.v:150046$8342 + assign { } { } + assign { } { } + assign { } { } + assign $0\busy_l_r_busy[0:0] $2\busy_l_r_busy[0:0] + attribute \src "libresoc.v:150047.5-150047.29" + switch \initial + attribute \src "libresoc.v:150047.9-150047.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:294" + switch \ldst_port0_exc_$signal + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\busy_l_r_busy[0:0] 1'1 + case + assign $1\busy_l_r_busy[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:302" + switch \cyc_l_q_cyc + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\busy_l_r_busy[0:0] 1'1 + case + assign $2\busy_l_r_busy[0:0] $1\busy_l_r_busy[0:0] + end + sync always + update \busy_l_r_busy $0\busy_l_r_busy[0:0] + end + attribute \src "libresoc.v:150062.3-150097.6" + process $proc$libresoc.v:150062$8343 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\adrok_l_s_addr_acked$next[0:0]$8344 $6\adrok_l_s_addr_acked$next[0:0]$8350 + attribute \src "libresoc.v:150063.5-150063.29" + switch \initial + attribute \src "libresoc.v:150063.9-150063.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch \ld_active_q_ld_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\adrok_l_s_addr_acked$next[0:0]$8345 $2\adrok_l_s_addr_acked$next[0:0]$8346 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\adrok_l_s_addr_acked$next[0:0]$8346 1'1 + case + assign $2\adrok_l_s_addr_acked$next[0:0]$8346 1'0 + end + case + assign $1\adrok_l_s_addr_acked$next[0:0]$8345 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" + switch \st_active_q_st_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\adrok_l_s_addr_acked$next[0:0]$8347 $4\adrok_l_s_addr_acked$next[0:0]$8348 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" + switch \ldst_port0_addr_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\adrok_l_s_addr_acked$next[0:0]$8348 $5\adrok_l_s_addr_acked$next[0:0]$8349 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" + switch \adrok_l_qn_addr_acked + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\adrok_l_s_addr_acked$next[0:0]$8349 1'1 + case + assign $5\adrok_l_s_addr_acked$next[0:0]$8349 $1\adrok_l_s_addr_acked$next[0:0]$8345 + end + case + assign $4\adrok_l_s_addr_acked$next[0:0]$8348 $1\adrok_l_s_addr_acked$next[0:0]$8345 + end + case + assign $3\adrok_l_s_addr_acked$next[0:0]$8347 $1\adrok_l_s_addr_acked$next[0:0]$8345 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\adrok_l_s_addr_acked$next[0:0]$8350 1'0 + case + assign $6\adrok_l_s_addr_acked$next[0:0]$8350 $3\adrok_l_s_addr_acked$next[0:0]$8347 + end + sync always + update \adrok_l_s_addr_acked$next $0\adrok_l_s_addr_acked$next[0:0]$8344 + end + attribute \src "libresoc.v:150098.3-150113.6" + process $proc$libresoc.v:150098$8351 + assign { } { } + assign { } { } + assign { } { } + assign $0\adrok_l_r_addr_acked[0:0] $2\adrok_l_r_addr_acked[0:0] + attribute \src "libresoc.v:150099.5-150099.29" + switch \initial + attribute \src "libresoc.v:150099.9-150099.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:282" + switch \reset_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\adrok_l_r_addr_acked[0:0] 1'1 + case + assign $1\adrok_l_r_addr_acked[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" + switch \reset_l_q_reset + attribute \src "libresoc.v:0.0-0.0" + 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\enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \cr_op__insn_type$17 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 17 \cr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \cr_op__insn_type$2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 32 input 10 \full_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 32 \full_cr$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 32 output 22 \full_cr$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 32 \full_cr$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 23 \full_cr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \full_cr_ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \full_cr_ok$next + attribute \src "libresoc.v:150140.7-150140.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \main_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \main_cr_a$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \main_cr_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \main_cr_c + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \main_cr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \main_cr_op__fn_unit$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_cr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_cr_op__insn$10 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_cr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_cr_op__insn_type$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 32 \main_full_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 32 \main_full_cr$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_full_cr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rb + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 16 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 15 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 14 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 20 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 21 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 8 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 9 \rb + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$libresoc.v:150730$8361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$13 + connect \B \p_ready_o + connect \Y $and$libresoc.v:150730$8361_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:150753.12-150774.4" + cell \main$9 \main + connect \cr_a \main_cr_a + connect \cr_a$6 \main_cr_a$12 + connect \cr_a_ok \main_cr_a_ok + connect \cr_b \main_cr_b + connect \cr_c \main_cr_c + connect \cr_op__fn_unit \main_cr_op__fn_unit + connect \cr_op__fn_unit$3 \main_cr_op__fn_unit$9 + connect \cr_op__insn \main_cr_op__insn + connect \cr_op__insn$4 \main_cr_op__insn$10 + connect \cr_op__insn_type \main_cr_op__insn_type + connect \cr_op__insn_type$2 \main_cr_op__insn_type$8 + connect \full_cr \main_full_cr + connect \full_cr$5 \main_full_cr$11 + connect \full_cr_ok \main_full_cr_ok + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$7 + connect \o \main_o + connect \o_ok \main_o_ok + connect \ra \main_ra + connect \rb \main_rb + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:150775.9-150778.4" + cell \n$8 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:150779.9-150782.4" + cell \p$7 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:150140.7-150140.20" + process $proc$libresoc.v:150140$8411 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:150153.13-150153.28" + process $proc$libresoc.v:150153$8412 + assign { } { } + assign $0\cr_a$6[3:0]$8413 4'0000 + sync always + sync init + update \cr_a$6 $0\cr_a$6[3:0]$8413 + end + attribute \src "libresoc.v:150158.7-150158.21" + process $proc$libresoc.v:150158$8414 + assign { } { } + assign $1\cr_a_ok[0:0] 1'0 + sync always + sync init + update \cr_a_ok $1\cr_a_ok[0:0] + end + attribute \src "libresoc.v:150212.14-150212.42" + process $proc$libresoc.v:150212$8415 + assign { } { } + assign $0\cr_op__fn_unit$3[11:0]$8416 12'000000000000 + sync always + sync init + update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[11:0]$8416 + end + attribute \src "libresoc.v:150221.14-150221.37" + process $proc$libresoc.v:150221$8417 + assign { } { } + assign $0\cr_op__insn$4[31:0]$8418 0 + sync always + sync init + update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8418 + end + attribute \src "libresoc.v:150452.13-150452.41" + process $proc$libresoc.v:150452$8419 + assign { } { } + assign $0\cr_op__insn_type$2[6:0]$8420 7'0000000 + sync always + sync init + update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8420 + end + attribute \src "libresoc.v:150461.14-150461.33" + process $proc$libresoc.v:150461$8421 + assign { } { } + assign $0\full_cr$5[31:0]$8422 0 + sync always + sync init + update \full_cr$5 $0\full_cr$5[31:0]$8422 + end + attribute \src "libresoc.v:150466.7-150466.24" + process $proc$libresoc.v:150466$8423 + assign { } { } + assign $1\full_cr_ok[0:0] 1'0 + sync always + sync init + update \full_cr_ok $1\full_cr_ok[0:0] + end + attribute \src "libresoc.v:150689.13-150689.29" + process $proc$libresoc.v:150689$8424 + assign { } { } + assign $0\muxid$1[1:0]$8425 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$8425 + end + attribute \src "libresoc.v:150702.14-150702.38" + process $proc$libresoc.v:150702$8426 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "libresoc.v:150709.7-150709.18" + process $proc$libresoc.v:150709$8427 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "libresoc.v:150723.7-150723.20" + process $proc$libresoc.v:150723$8428 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:150731.3-150732.31" + process $proc$libresoc.v:150731$8362 + assign { } { } + assign $0\cr_a$6[3:0]$8363 \cr_a$6$next + sync posedge \coresync_clk + update \cr_a$6 $0\cr_a$6[3:0]$8363 + end + attribute \src "libresoc.v:150733.3-150734.31" + process $proc$libresoc.v:150733$8364 + assign { } { } + assign $0\cr_a_ok[0:0] \cr_a_ok$next + sync posedge \coresync_clk + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "libresoc.v:150735.3-150736.37" + process $proc$libresoc.v:150735$8365 + assign { } { } + assign $0\full_cr$5[31:0]$8366 \full_cr$5$next + sync posedge \coresync_clk + update \full_cr$5 $0\full_cr$5[31:0]$8366 + end + attribute \src "libresoc.v:150737.3-150738.37" + process $proc$libresoc.v:150737$8367 + assign { } { } + assign $0\full_cr_ok[0:0] \full_cr_ok$next + sync posedge \coresync_clk + update \full_cr_ok $0\full_cr_ok[0:0] + end + attribute \src "libresoc.v:150739.3-150740.19" + process $proc$libresoc.v:150739$8368 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] + end + attribute \src "libresoc.v:150741.3-150742.25" + process $proc$libresoc.v:150741$8369 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:150743.3-150744.55" + process $proc$libresoc.v:150743$8370 + assign { } { } + assign $0\cr_op__insn_type$2[6:0]$8371 \cr_op__insn_type$2$next + sync posedge \coresync_clk + update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8371 + end + attribute \src "libresoc.v:150745.3-150746.51" + process $proc$libresoc.v:150745$8372 + assign { } { } + assign $0\cr_op__fn_unit$3[11:0]$8373 \cr_op__fn_unit$3$next + sync posedge \coresync_clk + update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[11:0]$8373 + end + attribute \src "libresoc.v:150747.3-150748.45" + process $proc$libresoc.v:150747$8374 + assign { } { } + assign $0\cr_op__insn$4[31:0]$8375 \cr_op__insn$4$next + sync posedge \coresync_clk + update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8375 + end + attribute \src "libresoc.v:150749.3-150750.33" + process $proc$libresoc.v:150749$8376 + assign { } { } + assign $0\muxid$1[1:0]$8377 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$8377 + end + attribute \src "libresoc.v:150751.3-150752.29" + process $proc$libresoc.v:150751$8378 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:150783.3-150800.6" + process $proc$libresoc.v:150783$8379 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$8380 $2\r_busy$next[0:0]$8382 + attribute \src "libresoc.v:150784.5-150784.29" + switch \initial + attribute \src "libresoc.v:150784.9-150784.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$8381 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$8381 1'0 + case + assign $1\r_busy$next[0:0]$8381 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$8382 1'0 + case + assign $2\r_busy$next[0:0]$8382 $1\r_busy$next[0:0]$8381 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$8380 + end + attribute \src "libresoc.v:150801.3-150813.6" + process $proc$libresoc.v:150801$8383 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$8384 $1\muxid$1$next[1:0]$8385 + attribute \src "libresoc.v:150802.5-150802.29" + switch \initial + attribute \src "libresoc.v:150802.9-150802.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$8385 \muxid$16 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$8385 \muxid$16 + case + assign $1\muxid$1$next[1:0]$8385 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$8384 + end + attribute \src "libresoc.v:150814.3-150828.6" + process $proc$libresoc.v:150814$8386 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_op__fn_unit$3$next[11:0]$8387 $1\cr_op__fn_unit$3$next[11:0]$8390 + assign $0\cr_op__insn$4$next[31:0]$8388 $1\cr_op__insn$4$next[31:0]$8391 + assign $0\cr_op__insn_type$2$next[6:0]$8389 $1\cr_op__insn_type$2$next[6:0]$8392 + attribute \src "libresoc.v:150815.5-150815.29" + switch \initial + attribute \src "libresoc.v:150815.9-150815.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { $1\cr_op__insn$4$next[31:0]$8391 $1\cr_op__fn_unit$3$next[11:0]$8390 $1\cr_op__insn_type$2$next[6:0]$8392 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { $1\cr_op__insn$4$next[31:0]$8391 $1\cr_op__fn_unit$3$next[11:0]$8390 $1\cr_op__insn_type$2$next[6:0]$8392 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } + case + assign $1\cr_op__fn_unit$3$next[11:0]$8390 \cr_op__fn_unit$3 + assign $1\cr_op__insn$4$next[31:0]$8391 \cr_op__insn$4 + assign $1\cr_op__insn_type$2$next[6:0]$8392 \cr_op__insn_type$2 + end + sync always + update \cr_op__fn_unit$3$next $0\cr_op__fn_unit$3$next[11:0]$8387 + update \cr_op__insn$4$next $0\cr_op__insn$4$next[31:0]$8388 + update \cr_op__insn_type$2$next $0\cr_op__insn_type$2$next[6:0]$8389 + end + attribute \src "libresoc.v:150829.3-150847.6" + process $proc$libresoc.v:150829$8393 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$8394 $1\o$next[63:0]$8396 + assign { } { } + assign $0\o_ok$next[0:0]$8395 $2\o_ok$next[0:0]$8398 + attribute \src "libresoc.v:150830.5-150830.29" + switch \initial + attribute \src "libresoc.v:150830.9-150830.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8397 $1\o$next[63:0]$8396 } { \o_ok$21 \o$20 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8397 $1\o$next[63:0]$8396 } { \o_ok$21 \o$20 } + case + assign $1\o$next[63:0]$8396 \o + assign $1\o_ok$next[0:0]$8397 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$8398 1'0 + case + assign $2\o_ok$next[0:0]$8398 $1\o_ok$next[0:0]$8397 + end + sync always + update \o$next $0\o$next[63:0]$8394 + update \o_ok$next $0\o_ok$next[0:0]$8395 + end + attribute \src "libresoc.v:150848.3-150866.6" + process $proc$libresoc.v:150848$8399 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\full_cr$5$next[31:0]$8400 $1\full_cr$5$next[31:0]$8402 + assign { } { } + assign $0\full_cr_ok$next[0:0]$8401 $2\full_cr_ok$next[0:0]$8404 + attribute \src "libresoc.v:150849.5-150849.29" + switch \initial + attribute \src "libresoc.v:150849.9-150849.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\full_cr_ok$next[0:0]$8403 $1\full_cr$5$next[31:0]$8402 } { \full_cr_ok$23 \full_cr$22 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\full_cr_ok$next[0:0]$8403 $1\full_cr$5$next[31:0]$8402 } { \full_cr_ok$23 \full_cr$22 } + case + assign $1\full_cr$5$next[31:0]$8402 \full_cr$5 + assign $1\full_cr_ok$next[0:0]$8403 \full_cr_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\full_cr_ok$next[0:0]$8404 1'0 + case + assign $2\full_cr_ok$next[0:0]$8404 $1\full_cr_ok$next[0:0]$8403 + end + sync always + update \full_cr$5$next $0\full_cr$5$next[31:0]$8400 + update \full_cr_ok$next $0\full_cr_ok$next[0:0]$8401 + end + attribute \src "libresoc.v:150867.3-150885.6" + process $proc$libresoc.v:150867$8405 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$6$next[3:0]$8407 $1\cr_a$6$next[3:0]$8409 + assign $0\cr_a_ok$next[0:0]$8406 $2\cr_a_ok$next[0:0]$8410 + attribute \src "libresoc.v:150868.5-150868.29" + switch \initial + attribute \src "libresoc.v:150868.9-150868.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$8408 $1\cr_a$6$next[3:0]$8409 } { \cr_a_ok$25 \cr_a$24 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$8408 $1\cr_a$6$next[3:0]$8409 } { \cr_a_ok$25 \cr_a$24 } + case + assign $1\cr_a_ok$next[0:0]$8408 \cr_a_ok + assign $1\cr_a$6$next[3:0]$8409 \cr_a$6 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$next[0:0]$8410 1'0 + case + assign $2\cr_a_ok$next[0:0]$8410 $1\cr_a_ok$next[0:0]$8408 + end + sync always + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8406 + update \cr_a$6$next $0\cr_a$6$next[3:0]$8407 + end + connect \$14 $and$libresoc.v:150730$8361_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \cr_a_ok$25 \cr_a$24 } { \main_cr_a_ok \main_cr_a$12 } + connect { \full_cr_ok$23 \full_cr$22 } { \main_full_cr_ok \main_full_cr$11 } + connect { \o_ok$21 \o$20 } { \main_o_ok \main_o } + connect { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } { \main_cr_op__insn$10 \main_cr_op__fn_unit$9 \main_cr_op__insn_type$8 } + connect \muxid$16 \main_muxid$7 + connect \p_valid_i_p_ready_o \$14 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$13 \p_valid_i + connect \main_cr_c \cr_c + connect \main_cr_b \cr_b + connect \main_cr_a \cr_a + connect \main_full_cr \full_cr + connect \main_rb \rb + connect \main_ra \ra + connect { \main_cr_op__insn \main_cr_op__fn_unit \main_cr_op__insn_type } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } + connect \main_muxid \muxid +end +attribute \src "libresoc.v:150908.1-151753.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe" +attribute \generator "nMigen" +module \pipe$19 + attribute \src "libresoc.v:151653.3-151680.6" + wire width 64 $0\br_op__cia$2$next[63:0]$8465 + attribute \src "libresoc.v:151565.3-151566.43" + wire width 64 $0\br_op__cia$2[63:0]$8439 + attribute \src "libresoc.v:150916.14-150916.51" + wire width 64 $0\br_op__cia$2[63:0]$8503 + attribute \src "libresoc.v:151653.3-151680.6" + wire width 12 $0\br_op__fn_unit$4$next[11:0]$8466 + attribute \src "libresoc.v:151569.3-151570.51" + wire width 12 $0\br_op__fn_unit$4[11:0]$8443 + attribute \src "libresoc.v:150966.14-150966.42" + wire width 12 $0\br_op__fn_unit$4[11:0]$8505 + attribute \src "libresoc.v:151653.3-151680.6" + wire width 64 $0\br_op__imm_data__data$6$next[63:0]$8467 + attribute \src "libresoc.v:151573.3-151574.65" + wire width 64 $0\br_op__imm_data__data$6[63:0]$8447 + attribute \src "libresoc.v:150975.14-150975.62" + wire width 64 $0\br_op__imm_data__data$6[63:0]$8507 + attribute \src "libresoc.v:151653.3-151680.6" + wire $0\br_op__imm_data__ok$7$next[0:0]$8468 + attribute \src "libresoc.v:151575.3-151576.61" + wire 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$0\fast2_ok$next[0:0]$8491 + attribute \src "libresoc.v:151559.3-151560.33" + wire $0\fast2_ok[0:0] + attribute \src "libresoc.v:150909.7-150909.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:151640.3-151652.6" + wire width 2 $0\muxid$1$next[1:0]$8462 + attribute \src "libresoc.v:151581.3-151582.33" + wire width 2 $0\muxid$1[1:0]$8455 + attribute \src "libresoc.v:151515.13-151515.29" + wire width 2 $0\muxid$1[1:0]$8525 + attribute \src "libresoc.v:151719.3-151737.6" + wire width 64 $0\nia$next[63:0]$8496 + attribute \src "libresoc.v:151553.3-151554.23" + wire width 64 $0\nia[63:0] + attribute \src "libresoc.v:151719.3-151737.6" + wire $0\nia_ok$next[0:0]$8497 + attribute \src "libresoc.v:151555.3-151556.29" + wire $0\nia_ok[0:0] + attribute \src "libresoc.v:151622.3-151639.6" + wire $0\r_busy$next[0:0]$8458 + attribute \src "libresoc.v:151583.3-151584.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:151653.3-151680.6" + wire width 64 $1\br_op__cia$2$next[63:0]$8473 + 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+ attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 7 \br_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \br_op__fn_unit$29 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 21 \br_op__fn_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \br_op__fn_unit$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 9 \br_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \br_op__imm_data__data$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 23 \br_op__imm_data__data$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \br_op__imm_data__data$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \br_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__imm_data__ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 24 \br_op__imm_data__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__imm_data__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 8 \br_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \br_op__insn$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 22 \br_op__insn$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \br_op__insn$5$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 6 \br_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute 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"OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \br_op__insn_type$28 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 20 \br_op__insn_type$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \br_op__insn_type$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \br_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__is_32bit$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \br_op__is_32bit$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__is_32bit$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \br_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__lk$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 25 \br_op__lk$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__lk$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 33 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 15 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 13 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 27 \fast1$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \fast1$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \fast1$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 28 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fast1_ok$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fast1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 29 \fast2$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \fast2$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \fast2$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 30 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fast2_ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fast2_ok$next + attribute \src "libresoc.v:150909.7-150909.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_br_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_br_op__cia$13 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \main_br_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \main_br_op__fn_unit$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_br_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_br_op__imm_data__data$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_br_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_br_op__imm_data__ok$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_br_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_br_op__insn$16 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_br_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_br_op__insn_type$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_br_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_br_op__is_32bit$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_br_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_br_op__lk$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \main_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_fast1$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_fast2$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_fast2_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_nia_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 18 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 17 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 16 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 31 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \nia$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \nia$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 32 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \nia_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \nia_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$libresoc.v:151552$8429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$23 + connect \B \p_ready_o + connect \Y $and$libresoc.v:151552$8429_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:151585.13-151613.4" + cell \main$22 \main + connect \br_op__cia \main_br_op__cia + connect \br_op__cia$2 \main_br_op__cia$13 + connect \br_op__fn_unit \main_br_op__fn_unit + connect \br_op__fn_unit$4 \main_br_op__fn_unit$15 + connect \br_op__imm_data__data \main_br_op__imm_data__data + connect \br_op__imm_data__data$6 \main_br_op__imm_data__data$17 + connect \br_op__imm_data__ok \main_br_op__imm_data__ok + connect \br_op__imm_data__ok$7 \main_br_op__imm_data__ok$18 + connect \br_op__insn \main_br_op__insn + connect \br_op__insn$5 \main_br_op__insn$16 + connect \br_op__insn_type \main_br_op__insn_type + connect \br_op__insn_type$3 \main_br_op__insn_type$14 + connect \br_op__is_32bit \main_br_op__is_32bit + connect \br_op__is_32bit$9 \main_br_op__is_32bit$20 + connect \br_op__lk \main_br_op__lk + connect \br_op__lk$8 \main_br_op__lk$19 + connect \cr_a \main_cr_a + connect \fast1 \main_fast1 + connect \fast1$10 \main_fast1$21 + connect \fast1_ok \main_fast1_ok + connect \fast2 \main_fast2 + connect \fast2$11 \main_fast2$22 + connect \fast2_ok \main_fast2_ok + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$12 + connect \nia \main_nia + connect \nia_ok \main_nia_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:151614.10-151617.4" + cell \n$21 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:151618.10-151621.4" + cell \p$20 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:150909.7-150909.20" + process $proc$libresoc.v:150909$8501 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:150916.14-150916.51" + process $proc$libresoc.v:150916$8502 + assign { } { } + assign $0\br_op__cia$2[63:0]$8503 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \br_op__cia$2 $0\br_op__cia$2[63:0]$8503 + end + attribute \src "libresoc.v:150966.14-150966.42" + process $proc$libresoc.v:150966$8504 + assign { } { } + assign $0\br_op__fn_unit$4[11:0]$8505 12'000000000000 + sync always + sync init + update \br_op__fn_unit$4 $0\br_op__fn_unit$4[11:0]$8505 + end + attribute \src "libresoc.v:150975.14-150975.62" + process $proc$libresoc.v:150975$8506 + assign { } { } + assign $0\br_op__imm_data__data$6[63:0]$8507 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8507 + end + attribute \src "libresoc.v:150984.7-150984.37" + process $proc$libresoc.v:150984$8508 + assign { } { } + assign $0\br_op__imm_data__ok$7[0:0]$8509 1'0 + sync always + sync init + update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8509 + end + attribute \src "libresoc.v:150993.14-150993.37" + process $proc$libresoc.v:150993$8510 + assign { } { } + assign $0\br_op__insn$5[31:0]$8511 0 + sync always + sync init + update \br_op__insn$5 $0\br_op__insn$5[31:0]$8511 + end + attribute \src "libresoc.v:151224.13-151224.41" + process $proc$libresoc.v:151224$8512 + assign { } { } + assign $0\br_op__insn_type$3[6:0]$8513 7'0000000 + sync always + sync init + update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8513 + end + attribute \src "libresoc.v:151233.7-151233.33" + process $proc$libresoc.v:151233$8514 + assign { } { } + assign $0\br_op__is_32bit$9[0:0]$8515 1'0 + sync always + sync init + update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8515 + end + attribute \src "libresoc.v:151242.7-151242.27" + process $proc$libresoc.v:151242$8516 + assign { } { } + assign $0\br_op__lk$8[0:0]$8517 1'0 + sync always + sync init + update \br_op__lk$8 $0\br_op__lk$8[0:0]$8517 + end + attribute \src "libresoc.v:151255.14-151255.47" + process $proc$libresoc.v:151255$8518 + assign { } { } + assign $0\fast1$10[63:0]$8519 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \fast1$10 $0\fast1$10[63:0]$8519 + end + attribute \src "libresoc.v:151262.7-151262.22" + process $proc$libresoc.v:151262$8520 + assign { } { } + assign $1\fast1_ok[0:0] 1'0 + sync always + sync init + update \fast1_ok $1\fast1_ok[0:0] + end + attribute \src "libresoc.v:151271.14-151271.47" + process $proc$libresoc.v:151271$8521 + assign { } { } + assign $0\fast2$11[63:0]$8522 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \fast2$11 $0\fast2$11[63:0]$8522 + end + attribute \src "libresoc.v:151278.7-151278.22" + process $proc$libresoc.v:151278$8523 + assign { } { } + assign $1\fast2_ok[0:0] 1'0 + sync always + sync init + update \fast2_ok $1\fast2_ok[0:0] + end + attribute \src "libresoc.v:151515.13-151515.29" + process $proc$libresoc.v:151515$8524 + assign { } { } + assign $0\muxid$1[1:0]$8525 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$8525 + end + attribute \src "libresoc.v:151528.14-151528.40" + process $proc$libresoc.v:151528$8526 + assign { } { } + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \nia $1\nia[63:0] + end + attribute \src "libresoc.v:151535.7-151535.20" + process $proc$libresoc.v:151535$8527 + assign { } { } + assign $1\nia_ok[0:0] 1'0 + sync always + sync init + update \nia_ok $1\nia_ok[0:0] + end + attribute \src "libresoc.v:151549.7-151549.20" + process $proc$libresoc.v:151549$8528 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:151553.3-151554.23" + process $proc$libresoc.v:151553$8430 + assign { } { } + assign $0\nia[63:0] \nia$next + sync posedge \coresync_clk + update \nia $0\nia[63:0] + end + attribute \src "libresoc.v:151555.3-151556.29" + process $proc$libresoc.v:151555$8431 + assign { } { } + assign $0\nia_ok[0:0] \nia_ok$next + sync posedge \coresync_clk + update \nia_ok $0\nia_ok[0:0] + end + attribute \src "libresoc.v:151557.3-151558.35" + process $proc$libresoc.v:151557$8432 + assign { } { } + assign $0\fast2$11[63:0]$8433 \fast2$11$next + sync posedge \coresync_clk + update \fast2$11 $0\fast2$11[63:0]$8433 + end + attribute \src "libresoc.v:151559.3-151560.33" + process $proc$libresoc.v:151559$8434 + assign { } { } + assign $0\fast2_ok[0:0] \fast2_ok$next + sync posedge \coresync_clk + update \fast2_ok $0\fast2_ok[0:0] + end + attribute \src "libresoc.v:151561.3-151562.35" + process $proc$libresoc.v:151561$8435 + assign { } { } + assign $0\fast1$10[63:0]$8436 \fast1$10$next + sync posedge \coresync_clk + update \fast1$10 $0\fast1$10[63:0]$8436 + end + attribute \src "libresoc.v:151563.3-151564.33" + process $proc$libresoc.v:151563$8437 + assign { } { } + assign $0\fast1_ok[0:0] \fast1_ok$next + sync posedge \coresync_clk + update \fast1_ok $0\fast1_ok[0:0] + end + attribute \src "libresoc.v:151565.3-151566.43" + process $proc$libresoc.v:151565$8438 + assign { } { } + assign $0\br_op__cia$2[63:0]$8439 \br_op__cia$2$next + sync posedge \coresync_clk + update \br_op__cia$2 $0\br_op__cia$2[63:0]$8439 + end + attribute \src "libresoc.v:151567.3-151568.55" + process $proc$libresoc.v:151567$8440 + assign { } { } + assign $0\br_op__insn_type$3[6:0]$8441 \br_op__insn_type$3$next + sync posedge \coresync_clk + update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8441 + end + attribute \src "libresoc.v:151569.3-151570.51" + process $proc$libresoc.v:151569$8442 + assign { } { } + assign $0\br_op__fn_unit$4[11:0]$8443 \br_op__fn_unit$4$next + sync posedge \coresync_clk + update \br_op__fn_unit$4 $0\br_op__fn_unit$4[11:0]$8443 + end + attribute \src "libresoc.v:151571.3-151572.45" + process $proc$libresoc.v:151571$8444 + assign { } { } + assign $0\br_op__insn$5[31:0]$8445 \br_op__insn$5$next + sync posedge \coresync_clk + update \br_op__insn$5 $0\br_op__insn$5[31:0]$8445 + end + attribute \src "libresoc.v:151573.3-151574.65" + process $proc$libresoc.v:151573$8446 + assign { } { } + assign $0\br_op__imm_data__data$6[63:0]$8447 \br_op__imm_data__data$6$next + sync posedge \coresync_clk + update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8447 + end + attribute \src "libresoc.v:151575.3-151576.61" + process $proc$libresoc.v:151575$8448 + assign { } { } + assign $0\br_op__imm_data__ok$7[0:0]$8449 \br_op__imm_data__ok$7$next + sync posedge \coresync_clk + update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8449 + end + attribute \src "libresoc.v:151577.3-151578.41" + process $proc$libresoc.v:151577$8450 + assign { } { } + assign $0\br_op__lk$8[0:0]$8451 \br_op__lk$8$next + sync posedge \coresync_clk + update \br_op__lk$8 $0\br_op__lk$8[0:0]$8451 + end + attribute \src "libresoc.v:151579.3-151580.53" + process $proc$libresoc.v:151579$8452 + assign { } { } + assign $0\br_op__is_32bit$9[0:0]$8453 \br_op__is_32bit$9$next + sync posedge \coresync_clk + update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8453 + end + attribute \src "libresoc.v:151581.3-151582.33" + process $proc$libresoc.v:151581$8454 + assign { } { } + assign $0\muxid$1[1:0]$8455 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$8455 + end + attribute \src "libresoc.v:151583.3-151584.29" + process $proc$libresoc.v:151583$8456 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:151622.3-151639.6" + process $proc$libresoc.v:151622$8457 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$8458 $2\r_busy$next[0:0]$8460 + attribute \src "libresoc.v:151623.5-151623.29" + switch \initial + attribute \src "libresoc.v:151623.9-151623.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$8459 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$8459 1'0 + case + assign $1\r_busy$next[0:0]$8459 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$8460 1'0 + case + assign $2\r_busy$next[0:0]$8460 $1\r_busy$next[0:0]$8459 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$8458 + end + attribute \src "libresoc.v:151640.3-151652.6" + process $proc$libresoc.v:151640$8461 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$8462 $1\muxid$1$next[1:0]$8463 + attribute \src "libresoc.v:151641.5-151641.29" + switch \initial + attribute \src "libresoc.v:151641.9-151641.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$8463 \muxid$26 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$8463 \muxid$26 + case + assign $1\muxid$1$next[1:0]$8463 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$8462 + end + attribute \src "libresoc.v:151653.3-151680.6" + process $proc$libresoc.v:151653$8464 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\br_op__cia$2$next[63:0]$8465 $1\br_op__cia$2$next[63:0]$8473 + assign $0\br_op__fn_unit$4$next[11:0]$8466 $1\br_op__fn_unit$4$next[11:0]$8474 + assign { } { } + assign { } { } + assign $0\br_op__insn$5$next[31:0]$8469 $1\br_op__insn$5$next[31:0]$8477 + assign $0\br_op__insn_type$3$next[6:0]$8470 $1\br_op__insn_type$3$next[6:0]$8478 + assign $0\br_op__is_32bit$9$next[0:0]$8471 $1\br_op__is_32bit$9$next[0:0]$8479 + assign $0\br_op__lk$8$next[0:0]$8472 $1\br_op__lk$8$next[0:0]$8480 + assign $0\br_op__imm_data__data$6$next[63:0]$8467 $2\br_op__imm_data__data$6$next[63:0]$8481 + assign $0\br_op__imm_data__ok$7$next[0:0]$8468 $2\br_op__imm_data__ok$7$next[0:0]$8482 + attribute \src "libresoc.v:151654.5-151654.29" + switch \initial + attribute \src "libresoc.v:151654.9-151654.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\br_op__is_32bit$9$next[0:0]$8479 $1\br_op__lk$8$next[0:0]$8480 $1\br_op__imm_data__ok$7$next[0:0]$8476 $1\br_op__imm_data__data$6$next[63:0]$8475 $1\br_op__insn$5$next[31:0]$8477 $1\br_op__fn_unit$4$next[11:0]$8474 $1\br_op__insn_type$3$next[6:0]$8478 $1\br_op__cia$2$next[63:0]$8473 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\br_op__is_32bit$9$next[0:0]$8479 $1\br_op__lk$8$next[0:0]$8480 $1\br_op__imm_data__ok$7$next[0:0]$8476 $1\br_op__imm_data__data$6$next[63:0]$8475 $1\br_op__insn$5$next[31:0]$8477 $1\br_op__fn_unit$4$next[11:0]$8474 $1\br_op__insn_type$3$next[6:0]$8478 $1\br_op__cia$2$next[63:0]$8473 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } + case + assign $1\br_op__cia$2$next[63:0]$8473 \br_op__cia$2 + assign $1\br_op__fn_unit$4$next[11:0]$8474 \br_op__fn_unit$4 + assign $1\br_op__imm_data__data$6$next[63:0]$8475 \br_op__imm_data__data$6 + assign $1\br_op__imm_data__ok$7$next[0:0]$8476 \br_op__imm_data__ok$7 + assign $1\br_op__insn$5$next[31:0]$8477 \br_op__insn$5 + assign $1\br_op__insn_type$3$next[6:0]$8478 \br_op__insn_type$3 + assign $1\br_op__is_32bit$9$next[0:0]$8479 \br_op__is_32bit$9 + assign $1\br_op__lk$8$next[0:0]$8480 \br_op__lk$8 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $2\br_op__imm_data__data$6$next[63:0]$8481 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\br_op__imm_data__ok$7$next[0:0]$8482 1'0 + case + assign $2\br_op__imm_data__data$6$next[63:0]$8481 $1\br_op__imm_data__data$6$next[63:0]$8475 + assign $2\br_op__imm_data__ok$7$next[0:0]$8482 $1\br_op__imm_data__ok$7$next[0:0]$8476 + end + sync always + update \br_op__cia$2$next $0\br_op__cia$2$next[63:0]$8465 + update \br_op__fn_unit$4$next $0\br_op__fn_unit$4$next[11:0]$8466 + update \br_op__imm_data__data$6$next $0\br_op__imm_data__data$6$next[63:0]$8467 + update \br_op__imm_data__ok$7$next $0\br_op__imm_data__ok$7$next[0:0]$8468 + update \br_op__insn$5$next $0\br_op__insn$5$next[31:0]$8469 + update \br_op__insn_type$3$next $0\br_op__insn_type$3$next[6:0]$8470 + update \br_op__is_32bit$9$next $0\br_op__is_32bit$9$next[0:0]$8471 + update \br_op__lk$8$next $0\br_op__lk$8$next[0:0]$8472 + end + attribute \src "libresoc.v:151681.3-151699.6" + process $proc$libresoc.v:151681$8483 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast1$10$next[63:0]$8484 $1\fast1$10$next[63:0]$8486 + assign { } { } + assign $0\fast1_ok$next[0:0]$8485 $2\fast1_ok$next[0:0]$8488 + attribute \src "libresoc.v:151682.5-151682.29" + switch \initial + attribute \src "libresoc.v:151682.9-151682.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\fast1_ok$next[0:0]$8487 $1\fast1$10$next[63:0]$8486 } { \fast1_ok$36 \fast1$35 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\fast1_ok$next[0:0]$8487 $1\fast1$10$next[63:0]$8486 } { \fast1_ok$36 \fast1$35 } + case + assign $1\fast1$10$next[63:0]$8486 \fast1$10 + assign $1\fast1_ok$next[0:0]$8487 \fast1_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast1_ok$next[0:0]$8488 1'0 + case + assign $2\fast1_ok$next[0:0]$8488 $1\fast1_ok$next[0:0]$8487 + end + sync always + update \fast1$10$next $0\fast1$10$next[63:0]$8484 + update \fast1_ok$next $0\fast1_ok$next[0:0]$8485 + end + attribute \src "libresoc.v:151700.3-151718.6" + process $proc$libresoc.v:151700$8489 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast2$11$next[63:0]$8490 $1\fast2$11$next[63:0]$8492 + assign { } { } + assign $0\fast2_ok$next[0:0]$8491 $2\fast2_ok$next[0:0]$8494 + attribute \src "libresoc.v:151701.5-151701.29" + switch \initial + attribute \src "libresoc.v:151701.9-151701.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\fast2_ok$next[0:0]$8493 $1\fast2$11$next[63:0]$8492 } { \fast2_ok$38 \fast2$37 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\fast2_ok$next[0:0]$8493 $1\fast2$11$next[63:0]$8492 } { \fast2_ok$38 \fast2$37 } + case + assign $1\fast2$11$next[63:0]$8492 \fast2$11 + assign $1\fast2_ok$next[0:0]$8493 \fast2_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast2_ok$next[0:0]$8494 1'0 + case + assign $2\fast2_ok$next[0:0]$8494 $1\fast2_ok$next[0:0]$8493 + end + sync always + update \fast2$11$next $0\fast2$11$next[63:0]$8490 + update \fast2_ok$next $0\fast2_ok$next[0:0]$8491 + end + attribute \src "libresoc.v:151719.3-151737.6" + process $proc$libresoc.v:151719$8495 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\nia$next[63:0]$8496 $1\nia$next[63:0]$8498 + assign { } { } + assign $0\nia_ok$next[0:0]$8497 $2\nia_ok$next[0:0]$8500 + attribute \src "libresoc.v:151720.5-151720.29" + switch \initial + attribute \src "libresoc.v:151720.9-151720.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\nia_ok$next[0:0]$8499 $1\nia$next[63:0]$8498 } { \nia_ok$40 \nia$39 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\nia_ok$next[0:0]$8499 $1\nia$next[63:0]$8498 } { \nia_ok$40 \nia$39 } + case + assign $1\nia$next[63:0]$8498 \nia + assign $1\nia_ok$next[0:0]$8499 \nia_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\nia_ok$next[0:0]$8500 1'0 + case + assign $2\nia_ok$next[0:0]$8500 $1\nia_ok$next[0:0]$8499 + end + sync always + update \nia$next $0\nia$next[63:0]$8496 + update \nia_ok$next $0\nia_ok$next[0:0]$8497 + end + connect \$24 $and$libresoc.v:151552$8429_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \nia_ok$40 \nia$39 } { \main_nia_ok \main_nia } + connect { \fast2_ok$38 \fast2$37 } { \main_fast2_ok \main_fast2$22 } + connect { \fast1_ok$36 \fast1$35 } { \main_fast1_ok \main_fast1$21 } + connect { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } { \main_br_op__is_32bit$20 \main_br_op__lk$19 \main_br_op__imm_data__ok$18 \main_br_op__imm_data__data$17 \main_br_op__insn$16 \main_br_op__fn_unit$15 \main_br_op__insn_type$14 \main_br_op__cia$13 } + connect \muxid$26 \main_muxid$12 + connect \p_valid_i_p_ready_o \$24 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$23 \p_valid_i + connect \main_cr_a \cr_a + connect \main_fast2 \fast2 + connect \main_fast1 \fast1 + connect { \main_br_op__is_32bit \main_br_op__lk \main_br_op__imm_data__ok \main_br_op__imm_data__data \main_br_op__insn \main_br_op__fn_unit \main_br_op__insn_type \main_br_op__cia } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } + connect \main_muxid \muxid +end +attribute \src "libresoc.v:151757.1-152672.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe" +attribute \generator "nMigen" +module \pipe$64 + attribute \src "libresoc.v:152575.3-152593.6" + wire width 64 $0\fast1$7$next[63:0]$8588 + attribute \src "libresoc.v:152428.3-152429.33" + wire width 64 $0\fast1$7[63:0]$8540 + attribute \src "libresoc.v:151771.14-151771.46" + wire width 64 $0\fast1$7[63:0]$8612 + attribute \src "libresoc.v:152575.3-152593.6" + wire $0\fast1_ok$next[0:0]$8587 + attribute \src "libresoc.v:152430.3-152431.33" + wire $0\fast1_ok[0:0] + attribute \src "libresoc.v:151758.7-151758.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:152508.3-152520.6" + wire width 2 $0\muxid$1$next[1:0]$8563 + attribute \src "libresoc.v:152448.3-152449.33" + wire width 2 $0\muxid$1[1:0]$8556 + attribute \src "libresoc.v:151785.13-151785.29" + wire width 2 $0\muxid$1[1:0]$8615 + attribute \src "libresoc.v:152537.3-152555.6" + wire width 64 $0\o$next[63:0]$8575 + attribute \src "libresoc.v:152436.3-152437.19" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:152537.3-152555.6" + wire $0\o_ok$next[0:0]$8576 + attribute \src "libresoc.v:152438.3-152439.25" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:152490.3-152507.6" + wire $0\r_busy$next[0:0]$8559 + attribute \src "libresoc.v:152450.3-152451.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:152556.3-152574.6" + wire width 64 $0\spr1$6$next[63:0]$8581 + attribute \src "libresoc.v:152432.3-152433.31" + wire width 64 $0\spr1$6[63:0]$8543 + attribute \src "libresoc.v:151830.14-151830.45" + wire width 64 $0\spr1$6[63:0]$8620 + attribute \src "libresoc.v:152556.3-152574.6" + wire $0\spr1_ok$next[0:0]$8582 + attribute \src "libresoc.v:152434.3-152435.31" + wire $0\spr1_ok[0:0] + attribute \src "libresoc.v:152521.3-152536.6" + wire width 12 $0\spr_op__fn_unit$3$next[11:0]$8566 + attribute \src "libresoc.v:152442.3-152443.53" + wire width 12 $0\spr_op__fn_unit$3[11:0]$8550 + attribute \src "libresoc.v:152115.14-152115.43" + wire width 12 $0\spr_op__fn_unit$3[11:0]$8623 + attribute \src "libresoc.v:152521.3-152536.6" + wire width 32 $0\spr_op__insn$4$next[31:0]$8567 + attribute \src "libresoc.v:152444.3-152445.47" + wire width 32 $0\spr_op__insn$4[31:0]$8552 + attribute \src "libresoc.v:152124.14-152124.38" + wire width 32 $0\spr_op__insn$4[31:0]$8625 + attribute \src "libresoc.v:152521.3-152536.6" + wire width 7 $0\spr_op__insn_type$2$next[6:0]$8568 + attribute \src "libresoc.v:152440.3-152441.57" + wire width 7 $0\spr_op__insn_type$2[6:0]$8548 + attribute \src "libresoc.v:152279.13-152279.42" + wire width 7 $0\spr_op__insn_type$2[6:0]$8627 + attribute \src "libresoc.v:152521.3-152536.6" + wire $0\spr_op__is_32bit$5$next[0:0]$8569 + attribute \src "libresoc.v:152446.3-152447.55" + wire $0\spr_op__is_32bit$5[0:0]$8554 + attribute \src "libresoc.v:152364.7-152364.34" + wire $0\spr_op__is_32bit$5[0:0]$8629 + attribute \src "libresoc.v:152632.3-152650.6" + wire width 2 $0\xer_ca$10$next[1:0]$8605 + attribute \src "libresoc.v:152416.3-152417.37" + wire width 2 $0\xer_ca$10[1:0]$8531 + attribute \src "libresoc.v:152371.13-152371.31" + wire width 2 $0\xer_ca$10[1:0]$8631 + attribute \src "libresoc.v:152632.3-152650.6" + wire $0\xer_ca_ok$next[0:0]$8606 + attribute \src "libresoc.v:152418.3-152419.35" + wire $0\xer_ca_ok[0:0] + attribute \src "libresoc.v:152613.3-152631.6" + wire width 2 $0\xer_ov$9$next[1:0]$8600 + attribute \src "libresoc.v:152420.3-152421.35" + wire width 2 $0\xer_ov$9[1:0]$8534 + attribute \src "libresoc.v:152389.13-152389.30" + wire width 2 $0\xer_ov$9[1:0]$8634 + attribute \src "libresoc.v:152613.3-152631.6" + wire $0\xer_ov_ok$next[0:0]$8599 + attribute \src "libresoc.v:152422.3-152423.35" + wire $0\xer_ov_ok[0:0] + attribute \src "libresoc.v:152594.3-152612.6" + wire $0\xer_so$8$next[0:0]$8594 + attribute \src "libresoc.v:152424.3-152425.35" + wire $0\xer_so$8[0:0]$8537 + attribute \src "libresoc.v:152405.7-152405.24" + wire $0\xer_so$8[0:0]$8637 + attribute \src "libresoc.v:152594.3-152612.6" + wire $0\xer_so_ok$next[0:0]$8593 + attribute \src "libresoc.v:152426.3-152427.35" + wire $0\xer_so_ok[0:0] + attribute \src "libresoc.v:152575.3-152593.6" + wire width 64 $1\fast1$7$next[63:0]$8590 + attribute \src "libresoc.v:152575.3-152593.6" + wire $1\fast1_ok$next[0:0]$8589 + attribute \src "libresoc.v:151776.7-151776.22" + wire $1\fast1_ok[0:0] + attribute \src "libresoc.v:152508.3-152520.6" + wire width 2 $1\muxid$1$next[1:0]$8564 + attribute \src "libresoc.v:152537.3-152555.6" + wire width 64 $1\o$next[63:0]$8577 + attribute \src "libresoc.v:151798.14-151798.38" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:152537.3-152555.6" + wire $1\o_ok$next[0:0]$8578 + attribute \src "libresoc.v:151805.7-151805.18" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:152490.3-152507.6" + wire $1\r_busy$next[0:0]$8560 + attribute \src "libresoc.v:151819.7-151819.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:152556.3-152574.6" + wire width 64 $1\spr1$6$next[63:0]$8583 + attribute \src "libresoc.v:152556.3-152574.6" + wire $1\spr1_ok$next[0:0]$8584 + attribute \src "libresoc.v:151835.7-151835.21" + wire $1\spr1_ok[0:0] + attribute \src "libresoc.v:152521.3-152536.6" + wire width 12 $1\spr_op__fn_unit$3$next[11:0]$8570 + attribute \src "libresoc.v:152521.3-152536.6" + wire width 32 $1\spr_op__insn$4$next[31:0]$8571 + attribute \src "libresoc.v:152521.3-152536.6" + wire width 7 $1\spr_op__insn_type$2$next[6:0]$8572 + attribute \src "libresoc.v:152521.3-152536.6" + wire $1\spr_op__is_32bit$5$next[0:0]$8573 + attribute \src "libresoc.v:152632.3-152650.6" + wire width 2 $1\xer_ca$10$next[1:0]$8607 + attribute \src "libresoc.v:152632.3-152650.6" + wire $1\xer_ca_ok$next[0:0]$8608 + attribute \src "libresoc.v:152378.7-152378.23" + wire $1\xer_ca_ok[0:0] + attribute \src "libresoc.v:152613.3-152631.6" + wire width 2 $1\xer_ov$9$next[1:0]$8602 + attribute \src "libresoc.v:152613.3-152631.6" + wire $1\xer_ov_ok$next[0:0]$8601 + attribute \src "libresoc.v:152394.7-152394.23" + wire $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:152594.3-152612.6" + wire $1\xer_so$8$next[0:0]$8596 + attribute \src "libresoc.v:152594.3-152612.6" + wire $1\xer_so_ok$next[0:0]$8595 + attribute \src "libresoc.v:152410.7-152410.23" + wire $1\xer_so_ok[0:0] + attribute \src "libresoc.v:152575.3-152593.6" + wire $2\fast1_ok$next[0:0]$8591 + attribute \src "libresoc.v:152537.3-152555.6" + wire $2\o_ok$next[0:0]$8579 + attribute \src "libresoc.v:152490.3-152507.6" + wire $2\r_busy$next[0:0]$8561 + attribute \src "libresoc.v:152556.3-152574.6" + wire $2\spr1_ok$next[0:0]$8585 + attribute \src "libresoc.v:152632.3-152650.6" + wire $2\xer_ca_ok$next[0:0]$8609 + attribute \src "libresoc.v:152613.3-152631.6" + wire $2\xer_ov_ok$next[0:0]$8603 + attribute \src "libresoc.v:152594.3-152612.6" + wire $2\xer_so_ok$next[0:0]$8597 + attribute \src "libresoc.v:152415.18-152415.118" + wire $and$libresoc.v:152415$8529_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 34 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 11 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \fast1$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 26 \fast1$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \fast1$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 27 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fast1_ok$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fast1_ok$next + attribute \src "libresoc.v:151758.7-151758.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 17 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 16 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 15 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 22 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 23 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 9 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 10 \spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \spr1$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 24 \spr1$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \spr1$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 25 \spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \spr1_ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \spr1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \spr_main_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \spr_main_fast1$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \spr_main_fast1_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \spr_main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \spr_main_muxid$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \spr_main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \spr_main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \spr_main_ra + attribute \src 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\enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 18 \spr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \spr_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \spr_op__insn_type$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \spr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \spr_op__is_32bit$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 21 \spr_op__is_32bit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \spr_op__is_32bit$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 14 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 32 \xer_ca$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 33 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 13 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 30 \xer_ov$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 31 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 12 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 28 \xer_so$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 29 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$libresoc.v:152415$8529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$21 + connect \B \p_ready_o + connect \Y $and$libresoc.v:152415$8529_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:152452.10-152455.4" + cell \n$66 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:152456.10-152459.4" + cell \p$65 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:152460.12-152489.4" + cell \spr_main \spr_main + connect \fast1 \spr_main_fast1 + connect \fast1$7 \spr_main_fast1$17 + connect \fast1_ok \spr_main_fast1_ok + connect \muxid \spr_main_muxid + connect \muxid$1 \spr_main_muxid$11 + connect \o \spr_main_o + connect \o_ok \spr_main_o_ok + connect \ra \spr_main_ra + connect \spr1 \spr_main_spr1 + connect \spr1$6 \spr_main_spr1$16 + connect \spr1_ok \spr_main_spr1_ok + connect \spr_op__fn_unit \spr_main_spr_op__fn_unit + connect \spr_op__fn_unit$3 \spr_main_spr_op__fn_unit$13 + connect \spr_op__insn \spr_main_spr_op__insn + connect \spr_op__insn$4 \spr_main_spr_op__insn$14 + connect \spr_op__insn_type \spr_main_spr_op__insn_type + connect \spr_op__insn_type$2 \spr_main_spr_op__insn_type$12 + connect \spr_op__is_32bit \spr_main_spr_op__is_32bit + connect \spr_op__is_32bit$5 \spr_main_spr_op__is_32bit$15 + connect \xer_ca \spr_main_xer_ca + connect \xer_ca$10 \spr_main_xer_ca$20 + connect \xer_ca_ok \spr_main_xer_ca_ok + connect \xer_ov \spr_main_xer_ov + connect \xer_ov$9 \spr_main_xer_ov$19 + connect \xer_ov_ok \spr_main_xer_ov_ok + connect \xer_so \spr_main_xer_so + connect \xer_so$8 \spr_main_xer_so$18 + connect \xer_so_ok \spr_main_xer_so_ok + end + attribute \src "libresoc.v:151758.7-151758.20" + process $proc$libresoc.v:151758$8610 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:151771.14-151771.46" + process $proc$libresoc.v:151771$8611 + assign { } { } + assign $0\fast1$7[63:0]$8612 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \fast1$7 $0\fast1$7[63:0]$8612 + end + attribute \src "libresoc.v:151776.7-151776.22" + process $proc$libresoc.v:151776$8613 + assign { } { } + assign $1\fast1_ok[0:0] 1'0 + sync always + sync init + update \fast1_ok $1\fast1_ok[0:0] + end + attribute \src "libresoc.v:151785.13-151785.29" + process $proc$libresoc.v:151785$8614 + assign { } { } + assign $0\muxid$1[1:0]$8615 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$8615 + end + attribute \src "libresoc.v:151798.14-151798.38" + process $proc$libresoc.v:151798$8616 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "libresoc.v:151805.7-151805.18" + process $proc$libresoc.v:151805$8617 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "libresoc.v:151819.7-151819.20" + process $proc$libresoc.v:151819$8618 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:151830.14-151830.45" + process $proc$libresoc.v:151830$8619 + assign { } { } + assign $0\spr1$6[63:0]$8620 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \spr1$6 $0\spr1$6[63:0]$8620 + end + attribute \src "libresoc.v:151835.7-151835.21" + process $proc$libresoc.v:151835$8621 + assign { } { } + assign $1\spr1_ok[0:0] 1'0 + sync always + sync init + update \spr1_ok $1\spr1_ok[0:0] + end + attribute \src "libresoc.v:152115.14-152115.43" + process $proc$libresoc.v:152115$8622 + assign { } { } + assign $0\spr_op__fn_unit$3[11:0]$8623 12'000000000000 + sync always + sync init + update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[11:0]$8623 + end + attribute \src "libresoc.v:152124.14-152124.38" + process $proc$libresoc.v:152124$8624 + assign { } { } + assign $0\spr_op__insn$4[31:0]$8625 0 + sync always + sync init + update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8625 + end + attribute \src "libresoc.v:152279.13-152279.42" + process $proc$libresoc.v:152279$8626 + assign { } { } + assign $0\spr_op__insn_type$2[6:0]$8627 7'0000000 + sync always + sync init + update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8627 + end + attribute \src "libresoc.v:152364.7-152364.34" + process $proc$libresoc.v:152364$8628 + assign { } { } + assign $0\spr_op__is_32bit$5[0:0]$8629 1'0 + sync always + sync init + update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8629 + end + attribute \src "libresoc.v:152371.13-152371.31" + process $proc$libresoc.v:152371$8630 + assign { } { } + assign $0\xer_ca$10[1:0]$8631 2'00 + sync always + sync init + update \xer_ca$10 $0\xer_ca$10[1:0]$8631 + end + attribute \src "libresoc.v:152378.7-152378.23" + process $proc$libresoc.v:152378$8632 + assign { } { } + assign $1\xer_ca_ok[0:0] 1'0 + sync always + sync init + update \xer_ca_ok $1\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:152389.13-152389.30" + process $proc$libresoc.v:152389$8633 + assign { } { } + assign $0\xer_ov$9[1:0]$8634 2'00 + sync always + sync init + update \xer_ov$9 $0\xer_ov$9[1:0]$8634 + end + attribute \src "libresoc.v:152394.7-152394.23" + process $proc$libresoc.v:152394$8635 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'0 + sync always + sync init + update \xer_ov_ok $1\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:152405.7-152405.24" + process $proc$libresoc.v:152405$8636 + assign { } { } + assign $0\xer_so$8[0:0]$8637 1'0 + sync always + sync init + update \xer_so$8 $0\xer_so$8[0:0]$8637 + end + attribute \src "libresoc.v:152410.7-152410.23" + process $proc$libresoc.v:152410$8638 + assign { } { } + assign $1\xer_so_ok[0:0] 1'0 + sync always + sync init + update \xer_so_ok $1\xer_so_ok[0:0] + end + attribute \src "libresoc.v:152416.3-152417.37" + process $proc$libresoc.v:152416$8530 + assign { } { } + assign $0\xer_ca$10[1:0]$8531 \xer_ca$10$next + sync posedge \coresync_clk + update \xer_ca$10 $0\xer_ca$10[1:0]$8531 + end + attribute \src "libresoc.v:152418.3-152419.35" + process $proc$libresoc.v:152418$8532 + assign { } { } + assign $0\xer_ca_ok[0:0] \xer_ca_ok$next + sync posedge \coresync_clk + update \xer_ca_ok $0\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:152420.3-152421.35" + process $proc$libresoc.v:152420$8533 + assign { } { } + assign $0\xer_ov$9[1:0]$8534 \xer_ov$9$next + sync posedge \coresync_clk + update \xer_ov$9 $0\xer_ov$9[1:0]$8534 + end + attribute \src "libresoc.v:152422.3-152423.35" + process $proc$libresoc.v:152422$8535 + assign { } { } + assign $0\xer_ov_ok[0:0] \xer_ov_ok$next + sync posedge \coresync_clk + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:152424.3-152425.35" + process $proc$libresoc.v:152424$8536 + assign { } { } + assign $0\xer_so$8[0:0]$8537 \xer_so$8$next + sync posedge \coresync_clk + update \xer_so$8 $0\xer_so$8[0:0]$8537 + end + attribute \src "libresoc.v:152426.3-152427.35" + process $proc$libresoc.v:152426$8538 + assign { } { } + assign $0\xer_so_ok[0:0] \xer_so_ok$next + sync posedge \coresync_clk + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:152428.3-152429.33" + process $proc$libresoc.v:152428$8539 + assign { } { } + assign $0\fast1$7[63:0]$8540 \fast1$7$next + sync posedge \coresync_clk + update \fast1$7 $0\fast1$7[63:0]$8540 + end + attribute \src "libresoc.v:152430.3-152431.33" + process $proc$libresoc.v:152430$8541 + assign { } { } + assign $0\fast1_ok[0:0] \fast1_ok$next + sync posedge \coresync_clk + update \fast1_ok $0\fast1_ok[0:0] + end + attribute \src "libresoc.v:152432.3-152433.31" + process $proc$libresoc.v:152432$8542 + assign { } { } + assign $0\spr1$6[63:0]$8543 \spr1$6$next + sync posedge \coresync_clk + update \spr1$6 $0\spr1$6[63:0]$8543 + end + attribute \src "libresoc.v:152434.3-152435.31" + process $proc$libresoc.v:152434$8544 + assign { } { } + assign $0\spr1_ok[0:0] \spr1_ok$next + sync posedge \coresync_clk + update \spr1_ok $0\spr1_ok[0:0] + end + attribute \src "libresoc.v:152436.3-152437.19" + process $proc$libresoc.v:152436$8545 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] + end + attribute \src "libresoc.v:152438.3-152439.25" + process $proc$libresoc.v:152438$8546 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:152440.3-152441.57" + process $proc$libresoc.v:152440$8547 + assign { } { } + assign $0\spr_op__insn_type$2[6:0]$8548 \spr_op__insn_type$2$next + sync posedge \coresync_clk + update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8548 + end + attribute \src "libresoc.v:152442.3-152443.53" + process $proc$libresoc.v:152442$8549 + assign { } { } + assign $0\spr_op__fn_unit$3[11:0]$8550 \spr_op__fn_unit$3$next + sync posedge \coresync_clk + update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[11:0]$8550 + end + attribute \src "libresoc.v:152444.3-152445.47" + process $proc$libresoc.v:152444$8551 + assign { } { } + assign $0\spr_op__insn$4[31:0]$8552 \spr_op__insn$4$next + sync posedge \coresync_clk + update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8552 + end + attribute \src "libresoc.v:152446.3-152447.55" + process $proc$libresoc.v:152446$8553 + assign { } { } + assign $0\spr_op__is_32bit$5[0:0]$8554 \spr_op__is_32bit$5$next + sync posedge \coresync_clk + update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8554 + end + attribute \src "libresoc.v:152448.3-152449.33" + process $proc$libresoc.v:152448$8555 + assign { } { } + assign $0\muxid$1[1:0]$8556 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$8556 + end + attribute \src "libresoc.v:152450.3-152451.29" + process $proc$libresoc.v:152450$8557 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:152490.3-152507.6" + process $proc$libresoc.v:152490$8558 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$8559 $2\r_busy$next[0:0]$8561 + attribute \src "libresoc.v:152491.5-152491.29" + switch \initial + attribute \src "libresoc.v:152491.9-152491.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$8560 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$8560 1'0 + case + assign $1\r_busy$next[0:0]$8560 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$8561 1'0 + case + assign $2\r_busy$next[0:0]$8561 $1\r_busy$next[0:0]$8560 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$8559 + end + attribute \src "libresoc.v:152508.3-152520.6" + process $proc$libresoc.v:152508$8562 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$8563 $1\muxid$1$next[1:0]$8564 + attribute \src "libresoc.v:152509.5-152509.29" + switch \initial + attribute \src "libresoc.v:152509.9-152509.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$8564 \muxid$24 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$8564 \muxid$24 + case + assign $1\muxid$1$next[1:0]$8564 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$8563 + end + attribute \src "libresoc.v:152521.3-152536.6" + process $proc$libresoc.v:152521$8565 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\spr_op__fn_unit$3$next[11:0]$8566 $1\spr_op__fn_unit$3$next[11:0]$8570 + assign $0\spr_op__insn$4$next[31:0]$8567 $1\spr_op__insn$4$next[31:0]$8571 + assign $0\spr_op__insn_type$2$next[6:0]$8568 $1\spr_op__insn_type$2$next[6:0]$8572 + assign $0\spr_op__is_32bit$5$next[0:0]$8569 $1\spr_op__is_32bit$5$next[0:0]$8573 + attribute \src "libresoc.v:152522.5-152522.29" + switch \initial + attribute \src "libresoc.v:152522.9-152522.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\spr_op__is_32bit$5$next[0:0]$8573 $1\spr_op__insn$4$next[31:0]$8571 $1\spr_op__fn_unit$3$next[11:0]$8570 $1\spr_op__insn_type$2$next[6:0]$8572 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\spr_op__is_32bit$5$next[0:0]$8573 $1\spr_op__insn$4$next[31:0]$8571 $1\spr_op__fn_unit$3$next[11:0]$8570 $1\spr_op__insn_type$2$next[6:0]$8572 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } + case + assign $1\spr_op__fn_unit$3$next[11:0]$8570 \spr_op__fn_unit$3 + assign $1\spr_op__insn$4$next[31:0]$8571 \spr_op__insn$4 + assign $1\spr_op__insn_type$2$next[6:0]$8572 \spr_op__insn_type$2 + assign $1\spr_op__is_32bit$5$next[0:0]$8573 \spr_op__is_32bit$5 + end + sync always + update \spr_op__fn_unit$3$next $0\spr_op__fn_unit$3$next[11:0]$8566 + update \spr_op__insn$4$next $0\spr_op__insn$4$next[31:0]$8567 + update \spr_op__insn_type$2$next $0\spr_op__insn_type$2$next[6:0]$8568 + update \spr_op__is_32bit$5$next $0\spr_op__is_32bit$5$next[0:0]$8569 + end + attribute \src "libresoc.v:152537.3-152555.6" + process $proc$libresoc.v:152537$8574 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$8575 $1\o$next[63:0]$8577 + assign { } { } + assign $0\o_ok$next[0:0]$8576 $2\o_ok$next[0:0]$8579 + attribute \src "libresoc.v:152538.5-152538.29" + switch \initial + attribute \src "libresoc.v:152538.9-152538.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8578 $1\o$next[63:0]$8577 } { \o_ok$30 \o$29 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8578 $1\o$next[63:0]$8577 } { \o_ok$30 \o$29 } + case + assign $1\o$next[63:0]$8577 \o + assign $1\o_ok$next[0:0]$8578 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$8579 1'0 + case + assign $2\o_ok$next[0:0]$8579 $1\o_ok$next[0:0]$8578 + end + sync always + update \o$next $0\o$next[63:0]$8575 + update \o_ok$next $0\o_ok$next[0:0]$8576 + end + attribute \src "libresoc.v:152556.3-152574.6" + process $proc$libresoc.v:152556$8580 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\spr1$6$next[63:0]$8581 $1\spr1$6$next[63:0]$8583 + assign { } { } + assign $0\spr1_ok$next[0:0]$8582 $2\spr1_ok$next[0:0]$8585 + attribute \src "libresoc.v:152557.5-152557.29" + switch \initial + attribute \src "libresoc.v:152557.9-152557.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\spr1_ok$next[0:0]$8584 $1\spr1$6$next[63:0]$8583 } { \spr1_ok$32 \spr1$31 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\spr1_ok$next[0:0]$8584 $1\spr1$6$next[63:0]$8583 } { \spr1_ok$32 \spr1$31 } + case + assign $1\spr1$6$next[63:0]$8583 \spr1$6 + assign $1\spr1_ok$next[0:0]$8584 \spr1_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\spr1_ok$next[0:0]$8585 1'0 + case + assign $2\spr1_ok$next[0:0]$8585 $1\spr1_ok$next[0:0]$8584 + end + sync always + update \spr1$6$next $0\spr1$6$next[63:0]$8581 + update \spr1_ok$next $0\spr1_ok$next[0:0]$8582 + end + attribute \src "libresoc.v:152575.3-152593.6" + process $proc$libresoc.v:152575$8586 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast1$7$next[63:0]$8588 $1\fast1$7$next[63:0]$8590 + assign $0\fast1_ok$next[0:0]$8587 $2\fast1_ok$next[0:0]$8591 + attribute \src "libresoc.v:152576.5-152576.29" + switch \initial + attribute \src "libresoc.v:152576.9-152576.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\fast1_ok$next[0:0]$8589 $1\fast1$7$next[63:0]$8590 } { \fast1_ok$34 \fast1$33 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\fast1_ok$next[0:0]$8589 $1\fast1$7$next[63:0]$8590 } { \fast1_ok$34 \fast1$33 } + case + assign $1\fast1_ok$next[0:0]$8589 \fast1_ok + assign $1\fast1$7$next[63:0]$8590 \fast1$7 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast1_ok$next[0:0]$8591 1'0 + case + assign $2\fast1_ok$next[0:0]$8591 $1\fast1_ok$next[0:0]$8589 + end + sync always + update \fast1_ok$next $0\fast1_ok$next[0:0]$8587 + update \fast1$7$next $0\fast1$7$next[63:0]$8588 + end + attribute \src "libresoc.v:152594.3-152612.6" + process $proc$libresoc.v:152594$8592 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$8$next[0:0]$8594 $1\xer_so$8$next[0:0]$8596 + assign $0\xer_so_ok$next[0:0]$8593 $2\xer_so_ok$next[0:0]$8597 + attribute \src "libresoc.v:152595.5-152595.29" + switch \initial + attribute \src "libresoc.v:152595.9-152595.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$8595 $1\xer_so$8$next[0:0]$8596 } { \xer_so_ok$36 \xer_so$35 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$8595 $1\xer_so$8$next[0:0]$8596 } { \xer_so_ok$36 \xer_so$35 } + case + assign $1\xer_so_ok$next[0:0]$8595 \xer_so_ok + assign $1\xer_so$8$next[0:0]$8596 \xer_so$8 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$next[0:0]$8597 1'0 + case + assign $2\xer_so_ok$next[0:0]$8597 $1\xer_so_ok$next[0:0]$8595 + end + sync always + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8593 + update \xer_so$8$next $0\xer_so$8$next[0:0]$8594 + end + attribute \src "libresoc.v:152613.3-152631.6" + process $proc$libresoc.v:152613$8598 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ov$9$next[1:0]$8600 $1\xer_ov$9$next[1:0]$8602 + assign $0\xer_ov_ok$next[0:0]$8599 $2\xer_ov_ok$next[0:0]$8603 + attribute \src "libresoc.v:152614.5-152614.29" + switch \initial + attribute \src "libresoc.v:152614.9-152614.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$8601 $1\xer_ov$9$next[1:0]$8602 } { \xer_ov_ok$38 \xer_ov$37 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$8601 $1\xer_ov$9$next[1:0]$8602 } { \xer_ov_ok$38 \xer_ov$37 } + case + assign $1\xer_ov_ok$next[0:0]$8601 \xer_ov_ok + assign $1\xer_ov$9$next[1:0]$8602 \xer_ov$9 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ov_ok$next[0:0]$8603 1'0 + case + assign $2\xer_ov_ok$next[0:0]$8603 $1\xer_ov_ok$next[0:0]$8601 + end + sync always + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8599 + update \xer_ov$9$next $0\xer_ov$9$next[1:0]$8600 + end + attribute \src "libresoc.v:152632.3-152650.6" + process $proc$libresoc.v:152632$8604 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ca$10$next[1:0]$8605 $1\xer_ca$10$next[1:0]$8607 + assign { } { } + assign $0\xer_ca_ok$next[0:0]$8606 $2\xer_ca_ok$next[0:0]$8609 + attribute \src "libresoc.v:152633.5-152633.29" + switch \initial + attribute \src "libresoc.v:152633.9-152633.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$8608 $1\xer_ca$10$next[1:0]$8607 } { \xer_ca_ok$40 \xer_ca$39 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$8608 $1\xer_ca$10$next[1:0]$8607 } { \xer_ca_ok$40 \xer_ca$39 } + case + assign $1\xer_ca$10$next[1:0]$8607 \xer_ca$10 + assign $1\xer_ca_ok$next[0:0]$8608 \xer_ca_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ca_ok$next[0:0]$8609 1'0 + case + assign $2\xer_ca_ok$next[0:0]$8609 $1\xer_ca_ok$next[0:0]$8608 + end + sync always + update \xer_ca$10$next $0\xer_ca$10$next[1:0]$8605 + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8606 + end + connect \$22 $and$libresoc.v:152415$8529_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_ca_ok$40 \xer_ca$39 } { \spr_main_xer_ca_ok \spr_main_xer_ca$20 } + connect { \xer_ov_ok$38 \xer_ov$37 } { \spr_main_xer_ov_ok \spr_main_xer_ov$19 } + connect { \xer_so_ok$36 \xer_so$35 } { \spr_main_xer_so_ok \spr_main_xer_so$18 } + connect { \fast1_ok$34 \fast1$33 } { \spr_main_fast1_ok \spr_main_fast1$17 } + connect { \spr1_ok$32 \spr1$31 } { \spr_main_spr1_ok \spr_main_spr1$16 } + connect { \o_ok$30 \o$29 } { \spr_main_o_ok \spr_main_o } + connect { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } { \spr_main_spr_op__is_32bit$15 \spr_main_spr_op__insn$14 \spr_main_spr_op__fn_unit$13 \spr_main_spr_op__insn_type$12 } + connect \muxid$24 \spr_main_muxid$11 + connect \p_valid_i_p_ready_o \$22 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$21 \p_valid_i + connect \spr_main_xer_ca \xer_ca + connect \spr_main_xer_ov \xer_ov + connect \spr_main_xer_so \xer_so + connect \spr_main_fast1 \fast1 + connect \spr_main_spr1 \spr1 + connect \spr_main_ra \ra + connect { \spr_main_spr_op__is_32bit \spr_main_spr_op__insn \spr_main_spr_op__fn_unit \spr_main_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } + connect \spr_main_muxid \muxid +end +attribute \src "libresoc.v:152676.1-154147.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1" +attribute \generator "nMigen" +module \pipe1 + attribute \src "libresoc.v:154061.3-154102.6" + wire width 4 $0\alu_op__data_len$next[3:0]$8702 + attribute \src "libresoc.v:153837.3-153838.49" + wire width 4 $0\alu_op__data_len[3:0] + attribute \src "libresoc.v:154061.3-154102.6" + wire width 12 $0\alu_op__fn_unit$next[11:0]$8703 + attribute \src "libresoc.v:153807.3-153808.47" + wire width 12 $0\alu_op__fn_unit[11:0] + attribute \src "libresoc.v:154061.3-154102.6" + wire width 64 $0\alu_op__imm_data__data$next[63:0]$8704 + attribute \src "libresoc.v:153809.3-153810.61" + wire width 64 $0\alu_op__imm_data__data[63:0] + attribute \src "libresoc.v:154061.3-154102.6" + wire $0\alu_op__imm_data__ok$next[0:0]$8705 + attribute \src "libresoc.v:153811.3-153812.57" + wire $0\alu_op__imm_data__ok[0:0] + attribute \src "libresoc.v:154061.3-154102.6" + wire width 2 $0\alu_op__input_carry$next[1:0]$8706 + attribute \src "libresoc.v:153829.3-153830.55" + wire width 2 $0\alu_op__input_carry[1:0] + attribute \src "libresoc.v:154061.3-154102.6" + wire width 32 $0\alu_op__insn$next[31:0]$8707 + attribute \src "libresoc.v:153839.3-153840.41" + wire width 32 $0\alu_op__insn[31:0] + attribute \src "libresoc.v:154061.3-154102.6" + wire width 7 $0\alu_op__insn_type$next[6:0]$8708 + attribute \src "libresoc.v:153805.3-153806.51" + wire width 7 $0\alu_op__insn_type[6:0] + attribute \src "libresoc.v:154061.3-154102.6" + wire $0\alu_op__invert_in$next[0:0]$8709 + attribute \src "libresoc.v:153821.3-153822.51" + wire $0\alu_op__invert_in[0:0] + attribute \src "libresoc.v:154061.3-154102.6" + wire $0\alu_op__invert_out$next[0:0]$8710 + attribute \src "libresoc.v:153825.3-153826.53" + wire $0\alu_op__invert_out[0:0] + attribute \src "libresoc.v:154061.3-154102.6" + wire $0\alu_op__is_32bit$next[0:0]$8711 + attribute \src "libresoc.v:153833.3-153834.49" + wire $0\alu_op__is_32bit[0:0] + attribute \src "libresoc.v:154061.3-154102.6" + wire $0\alu_op__is_signed$next[0:0]$8712 + attribute \src "libresoc.v:153835.3-153836.51" + wire $0\alu_op__is_signed[0:0] + attribute \src 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$0\alu_op__write_cr0[0:0] + attribute \src "libresoc.v:154061.3-154102.6" + wire $0\alu_op__zero_a$next[0:0]$8719 + attribute \src "libresoc.v:153823.3-153824.45" + wire $0\alu_op__zero_a[0:0] + attribute \src "libresoc.v:153954.3-153972.6" + wire width 4 $0\cr_a$next[3:0]$8671 + attribute \src "libresoc.v:153797.3-153798.25" + wire width 4 $0\cr_a[3:0] + attribute \src "libresoc.v:153954.3-153972.6" + wire $0\cr_a_ok$next[0:0]$8672 + attribute \src "libresoc.v:153799.3-153800.31" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:152677.7-152677.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:154048.3-154060.6" + wire width 2 $0\muxid$next[1:0]$8699 + attribute \src "libresoc.v:153841.3-153842.27" + wire width 2 $0\muxid[1:0] + attribute \src "libresoc.v:154103.3-154121.6" + wire width 64 $0\o$next[63:0]$8745 + attribute \src "libresoc.v:153801.3-153802.19" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:154103.3-154121.6" + wire $0\o_ok$next[0:0]$8746 + attribute \src "libresoc.v:153803.3-153804.25" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:154030.3-154047.6" + wire $0\r_busy$next[0:0]$8695 + attribute \src "libresoc.v:153843.3-153844.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:153973.3-153991.6" + wire width 2 $0\xer_ca$next[1:0]$8678 + attribute \src "libresoc.v:153793.3-153794.29" + wire width 2 $0\xer_ca[1:0] + attribute \src "libresoc.v:153973.3-153991.6" + wire $0\xer_ca_ok$next[0:0]$8677 + attribute \src "libresoc.v:153795.3-153796.35" + wire $0\xer_ca_ok[0:0] + attribute \src "libresoc.v:153992.3-154010.6" + wire width 2 $0\xer_ov$next[1:0]$8683 + attribute \src "libresoc.v:153789.3-153790.29" + wire width 2 $0\xer_ov[1:0] + attribute \src "libresoc.v:153992.3-154010.6" + wire $0\xer_ov_ok$next[0:0]$8684 + attribute \src "libresoc.v:153791.3-153792.35" + wire $0\xer_ov_ok[0:0] + attribute \src "libresoc.v:154011.3-154029.6" + wire $0\xer_so$next[0:0]$8689 + attribute \src "libresoc.v:153785.3-153786.29" + wire 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$1\alu_op__input_carry$next[1:0]$8724 + attribute \src "libresoc.v:152761.13-152761.39" + wire width 2 $1\alu_op__input_carry[1:0] + attribute \src "libresoc.v:154061.3-154102.6" + wire width 32 $1\alu_op__insn$next[31:0]$8725 + attribute \src "libresoc.v:152778.14-152778.34" + wire width 32 $1\alu_op__insn[31:0] + attribute \src "libresoc.v:154061.3-154102.6" + wire width 7 $1\alu_op__insn_type$next[6:0]$8726 + attribute \src "libresoc.v:152861.13-152861.38" + wire width 7 $1\alu_op__insn_type[6:0] + attribute \src "libresoc.v:154061.3-154102.6" + wire $1\alu_op__invert_in$next[0:0]$8727 + attribute \src "libresoc.v:153018.7-153018.31" + wire $1\alu_op__invert_in[0:0] + attribute \src "libresoc.v:154061.3-154102.6" + wire $1\alu_op__invert_out$next[0:0]$8728 + attribute \src "libresoc.v:153027.7-153027.32" + wire $1\alu_op__invert_out[0:0] + attribute \src "libresoc.v:154061.3-154102.6" + wire $1\alu_op__is_32bit$next[0:0]$8729 + attribute \src "libresoc.v:153036.7-153036.30" + wire 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attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_op__fn_unit$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 38 \alu_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__data$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 39 \alu_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__imm_data__ok$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 17 \alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 48 \alu_op__input_carry$14 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 22 \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 53 \alu_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 5 \alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 36 \alu_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_op__insn_type$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 44 \alu_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_in$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 46 \alu_op__invert_out$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_out$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 19 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 50 \alu_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_32bit$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 51 \alu_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_signed$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__oe$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 42 \alu_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__ok$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 43 \alu_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 18 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 49 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__output_carry$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 41 \alu_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__ok$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 40 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__rc$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 47 \alu_op__write_cr0$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__write_cr0$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 45 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__zero_a$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__zero_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 58 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 25 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 26 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$next + attribute \src "libresoc.v:152677.7-152677.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_alu_op__data_len$39 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \input_alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \input_alu_op__fn_unit$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_alu_op__imm_data__data$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__imm_data__ok$26 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_alu_op__input_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_alu_op__insn$40 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute 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\src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__is_32bit$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__is_signed$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__oe__oe$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__oe__ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__output_carry$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__rc__ok$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__rc__rc$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__write_cr0$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__zero_a$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \input_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \input_xer_ca$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \main_alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \main_alu_op__data_len$62 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \main_alu_op__fn_unit + attribute \enum_base_type "Function" + attribute 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\main_alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__imm_data__ok$49 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_alu_op__input_carry$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_alu_op__insn$63 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute 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attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute 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attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_alu_op__insn_type$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__invert_in$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__invert_out$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__is_32bit$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__is_signed$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__oe__oe$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__oe__ok$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__output_carry$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__rc__ok$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__rc__rc$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__write_cr0$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__zero_a$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \main_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \main_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \main_xer_ca$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \main_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \main_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_xer_so$65 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 35 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$69 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 23 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 24 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 34 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 33 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$66 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 54 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 55 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 27 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 57 \xer_ca$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 28 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 29 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 30 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 31 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 56 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 32 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$libresoc.v:153784$8639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$66 + connect \B \p_ready_o + connect \Y $and$libresoc.v:153784$8639_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:153845.11-153892.4" + cell \input \input + connect \alu_op__data_len \input_alu_op__data_len + connect \alu_op__data_len$18 \input_alu_op__data_len$39 + connect \alu_op__fn_unit \input_alu_op__fn_unit + connect \alu_op__fn_unit$3 \input_alu_op__fn_unit$24 + connect \alu_op__imm_data__data \input_alu_op__imm_data__data + connect \alu_op__imm_data__data$4 \input_alu_op__imm_data__data$25 + connect \alu_op__imm_data__ok \input_alu_op__imm_data__ok + connect \alu_op__imm_data__ok$5 \input_alu_op__imm_data__ok$26 + connect \alu_op__input_carry \input_alu_op__input_carry + connect \alu_op__input_carry$14 \input_alu_op__input_carry$35 + connect \alu_op__insn \input_alu_op__insn + connect \alu_op__insn$19 \input_alu_op__insn$40 + connect \alu_op__insn_type \input_alu_op__insn_type + connect \alu_op__insn_type$2 \input_alu_op__insn_type$23 + connect \alu_op__invert_in \input_alu_op__invert_in + connect \alu_op__invert_in$10 \input_alu_op__invert_in$31 + connect \alu_op__invert_out \input_alu_op__invert_out + connect \alu_op__invert_out$12 \input_alu_op__invert_out$33 + connect \alu_op__is_32bit \input_alu_op__is_32bit + connect \alu_op__is_32bit$16 \input_alu_op__is_32bit$37 + connect \alu_op__is_signed \input_alu_op__is_signed + connect \alu_op__is_signed$17 \input_alu_op__is_signed$38 + connect \alu_op__oe__oe \input_alu_op__oe__oe + connect \alu_op__oe__oe$8 \input_alu_op__oe__oe$29 + connect \alu_op__oe__ok \input_alu_op__oe__ok + connect \alu_op__oe__ok$9 \input_alu_op__oe__ok$30 + connect \alu_op__output_carry \input_alu_op__output_carry + connect \alu_op__output_carry$15 \input_alu_op__output_carry$36 + connect \alu_op__rc__ok \input_alu_op__rc__ok + connect \alu_op__rc__ok$7 \input_alu_op__rc__ok$28 + connect \alu_op__rc__rc \input_alu_op__rc__rc + connect \alu_op__rc__rc$6 \input_alu_op__rc__rc$27 + connect \alu_op__write_cr0 \input_alu_op__write_cr0 + connect \alu_op__write_cr0$13 \input_alu_op__write_cr0$34 + connect \alu_op__zero_a \input_alu_op__zero_a + connect \alu_op__zero_a$11 \input_alu_op__zero_a$32 + connect \muxid \input_muxid + connect \muxid$1 \input_muxid$22 + connect \ra \input_ra + connect \ra$20 \input_ra$41 + connect \rb \input_rb + connect \rb$21 \input_rb$42 + connect \xer_ca \input_xer_ca + connect \xer_ca$23 \input_xer_ca$44 + connect \xer_so \input_xer_so + connect \xer_so$22 \input_xer_so$43 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:153893.8-153945.4" + cell \main \main + connect \alu_op__data_len \main_alu_op__data_len + connect \alu_op__data_len$18 \main_alu_op__data_len$62 + connect \alu_op__fn_unit \main_alu_op__fn_unit + connect \alu_op__fn_unit$3 \main_alu_op__fn_unit$47 + connect \alu_op__imm_data__data \main_alu_op__imm_data__data + connect \alu_op__imm_data__data$4 \main_alu_op__imm_data__data$48 + connect \alu_op__imm_data__ok \main_alu_op__imm_data__ok + connect \alu_op__imm_data__ok$5 \main_alu_op__imm_data__ok$49 + connect \alu_op__input_carry \main_alu_op__input_carry + connect \alu_op__input_carry$14 \main_alu_op__input_carry$58 + connect \alu_op__insn \main_alu_op__insn + connect \alu_op__insn$19 \main_alu_op__insn$63 + connect \alu_op__insn_type \main_alu_op__insn_type + connect \alu_op__insn_type$2 \main_alu_op__insn_type$46 + connect \alu_op__invert_in \main_alu_op__invert_in + connect \alu_op__invert_in$10 \main_alu_op__invert_in$54 + connect \alu_op__invert_out \main_alu_op__invert_out + connect \alu_op__invert_out$12 \main_alu_op__invert_out$56 + connect \alu_op__is_32bit \main_alu_op__is_32bit + connect \alu_op__is_32bit$16 \main_alu_op__is_32bit$60 + connect \alu_op__is_signed \main_alu_op__is_signed + connect \alu_op__is_signed$17 \main_alu_op__is_signed$61 + connect \alu_op__oe__oe \main_alu_op__oe__oe + connect \alu_op__oe__oe$8 \main_alu_op__oe__oe$52 + connect \alu_op__oe__ok \main_alu_op__oe__ok + connect \alu_op__oe__ok$9 \main_alu_op__oe__ok$53 + connect \alu_op__output_carry \main_alu_op__output_carry + connect \alu_op__output_carry$15 \main_alu_op__output_carry$59 + connect \alu_op__rc__ok \main_alu_op__rc__ok + connect \alu_op__rc__ok$7 \main_alu_op__rc__ok$51 + connect \alu_op__rc__rc \main_alu_op__rc__rc + connect \alu_op__rc__rc$6 \main_alu_op__rc__rc$50 + connect \alu_op__write_cr0 \main_alu_op__write_cr0 + connect \alu_op__write_cr0$13 \main_alu_op__write_cr0$57 + connect \alu_op__zero_a \main_alu_op__zero_a + connect \alu_op__zero_a$11 \main_alu_op__zero_a$55 + connect \cr_a \main_cr_a + connect \cr_a_ok \main_cr_a_ok + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$45 + connect \o \main_o + connect \o_ok \main_o_ok + connect \ra \main_ra + connect \rb \main_rb + connect \xer_ca \main_xer_ca + connect \xer_ca$20 \main_xer_ca$64 + connect \xer_ca_ok \main_xer_ca_ok + connect \xer_ov \main_xer_ov + connect \xer_ov_ok \main_xer_ov_ok + connect \xer_so \main_xer_so + connect \xer_so$21 \main_xer_so$65 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:153946.9-153949.4" + cell \n$2 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:153950.9-153953.4" + cell \p$1 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:152677.7-152677.20" + process $proc$libresoc.v:152677$8750 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:152682.13-152682.36" + process $proc$libresoc.v:152682$8751 + assign { } { } + assign $1\alu_op__data_len[3:0] 4'0000 + sync always + sync init + update \alu_op__data_len $1\alu_op__data_len[3:0] + end + attribute \src "libresoc.v:152704.14-152704.39" + process $proc$libresoc.v:152704$8752 + assign { } { } + assign $1\alu_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \alu_op__fn_unit $1\alu_op__fn_unit[11:0] + end + attribute \src "libresoc.v:152739.14-152739.59" + process $proc$libresoc.v:152739$8753 + assign { } { } + assign $1\alu_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_op__imm_data__data $1\alu_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:152748.7-152748.34" + process $proc$libresoc.v:152748$8754 + assign { } { } + assign $1\alu_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \alu_op__imm_data__ok $1\alu_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:152761.13-152761.39" + process $proc$libresoc.v:152761$8755 + assign { } { } + assign $1\alu_op__input_carry[1:0] 2'00 + sync always + sync init + update \alu_op__input_carry $1\alu_op__input_carry[1:0] + end + attribute \src "libresoc.v:152778.14-152778.34" + process $proc$libresoc.v:152778$8756 + assign { } { } + assign $1\alu_op__insn[31:0] 0 + sync always + sync init + update \alu_op__insn $1\alu_op__insn[31:0] + end + attribute \src "libresoc.v:152861.13-152861.38" + process $proc$libresoc.v:152861$8757 + assign { } { } + assign $1\alu_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_op__insn_type $1\alu_op__insn_type[6:0] + end + attribute \src "libresoc.v:153018.7-153018.31" + process $proc$libresoc.v:153018$8758 + assign { } { } + assign $1\alu_op__invert_in[0:0] 1'0 + sync always + sync init + update \alu_op__invert_in $1\alu_op__invert_in[0:0] + end + attribute \src "libresoc.v:153027.7-153027.32" + process $proc$libresoc.v:153027$8759 + assign { } { } + assign $1\alu_op__invert_out[0:0] 1'0 + sync always + sync init + update \alu_op__invert_out $1\alu_op__invert_out[0:0] + end + attribute \src "libresoc.v:153036.7-153036.30" + process $proc$libresoc.v:153036$8760 + assign { } { } + assign $1\alu_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_op__is_32bit $1\alu_op__is_32bit[0:0] + end + attribute \src "libresoc.v:153045.7-153045.31" + process $proc$libresoc.v:153045$8761 + assign { } { } + assign $1\alu_op__is_signed[0:0] 1'0 + sync always + sync init + update \alu_op__is_signed $1\alu_op__is_signed[0:0] + end + attribute \src "libresoc.v:153054.7-153054.28" + process $proc$libresoc.v:153054$8762 + assign { } { } + assign $1\alu_op__oe__oe[0:0] 1'0 + sync always + sync init + update \alu_op__oe__oe $1\alu_op__oe__oe[0:0] + end + attribute \src "libresoc.v:153063.7-153063.28" + process $proc$libresoc.v:153063$8763 + assign { } { } + assign $1\alu_op__oe__ok[0:0] 1'0 + sync always + sync init + update \alu_op__oe__ok $1\alu_op__oe__ok[0:0] + end + attribute \src "libresoc.v:153072.7-153072.34" + process $proc$libresoc.v:153072$8764 + assign { } { } + assign $1\alu_op__output_carry[0:0] 1'0 + sync always + sync init + update \alu_op__output_carry $1\alu_op__output_carry[0:0] + end + attribute \src "libresoc.v:153081.7-153081.28" + process $proc$libresoc.v:153081$8765 + assign { } { } + assign $1\alu_op__rc__ok[0:0] 1'0 + sync always + sync init + update \alu_op__rc__ok $1\alu_op__rc__ok[0:0] + end + attribute \src "libresoc.v:153090.7-153090.28" + process $proc$libresoc.v:153090$8766 + assign { } { } + assign $1\alu_op__rc__rc[0:0] 1'0 + sync always + sync init + update \alu_op__rc__rc $1\alu_op__rc__rc[0:0] + end + attribute \src "libresoc.v:153099.7-153099.31" + process $proc$libresoc.v:153099$8767 + assign { } { } + assign $1\alu_op__write_cr0[0:0] 1'0 + sync always + sync init + update \alu_op__write_cr0 $1\alu_op__write_cr0[0:0] + end + attribute \src "libresoc.v:153108.7-153108.28" + process $proc$libresoc.v:153108$8768 + assign { } { } + assign $1\alu_op__zero_a[0:0] 1'0 + sync always + sync init + update \alu_op__zero_a $1\alu_op__zero_a[0:0] + end + attribute \src "libresoc.v:153121.13-153121.24" + process $proc$libresoc.v:153121$8769 + assign { } { } + assign $1\cr_a[3:0] 4'0000 + sync always + sync init + update \cr_a $1\cr_a[3:0] + end + attribute \src "libresoc.v:153128.7-153128.21" + process $proc$libresoc.v:153128$8770 + assign { } { } + assign $1\cr_a_ok[0:0] 1'0 + sync always + sync init + update \cr_a_ok $1\cr_a_ok[0:0] + end + attribute \src "libresoc.v:153693.13-153693.25" + process $proc$libresoc.v:153693$8771 + assign { } { } + assign $1\muxid[1:0] 2'00 + sync always + sync init + update \muxid $1\muxid[1:0] + end + attribute \src "libresoc.v:153708.14-153708.38" + process $proc$libresoc.v:153708$8772 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "libresoc.v:153715.7-153715.18" + process $proc$libresoc.v:153715$8773 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "libresoc.v:153729.7-153729.20" + process $proc$libresoc.v:153729$8774 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:153738.13-153738.26" + process $proc$libresoc.v:153738$8775 + assign { } { } + assign $1\xer_ca[1:0] 2'00 + sync always + sync init + update \xer_ca $1\xer_ca[1:0] + end + attribute \src "libresoc.v:153747.7-153747.23" + process $proc$libresoc.v:153747$8776 + assign { } { } + assign $1\xer_ca_ok[0:0] 1'0 + sync always + sync init + update \xer_ca_ok $1\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:153754.13-153754.26" + process $proc$libresoc.v:153754$8777 + assign { } { } + assign $1\xer_ov[1:0] 2'00 + sync always + sync init + update \xer_ov $1\xer_ov[1:0] + end + attribute \src "libresoc.v:153761.7-153761.23" + process $proc$libresoc.v:153761$8778 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'0 + sync always + sync init + update \xer_ov_ok $1\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:153768.7-153768.20" + process $proc$libresoc.v:153768$8779 + assign { } { } + assign $1\xer_so[0:0] 1'0 + sync always + sync init + update \xer_so $1\xer_so[0:0] + end + attribute \src "libresoc.v:153777.7-153777.23" + process $proc$libresoc.v:153777$8780 + assign { } { } + assign $1\xer_so_ok[0:0] 1'0 + sync always + sync init + update \xer_so_ok $1\xer_so_ok[0:0] + end + attribute \src "libresoc.v:153785.3-153786.29" + process $proc$libresoc.v:153785$8640 + assign { } { } + assign $0\xer_so[0:0] \xer_so$next + sync posedge \coresync_clk + update \xer_so $0\xer_so[0:0] + end + attribute \src "libresoc.v:153787.3-153788.35" + process $proc$libresoc.v:153787$8641 + assign { } { } + assign $0\xer_so_ok[0:0] \xer_so_ok$next + sync posedge \coresync_clk + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:153789.3-153790.29" + process $proc$libresoc.v:153789$8642 + assign { } { } + assign $0\xer_ov[1:0] \xer_ov$next + sync posedge \coresync_clk + update \xer_ov $0\xer_ov[1:0] + end + attribute \src "libresoc.v:153791.3-153792.35" + process $proc$libresoc.v:153791$8643 + assign { } { } + assign $0\xer_ov_ok[0:0] \xer_ov_ok$next + sync posedge \coresync_clk + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:153793.3-153794.29" + process $proc$libresoc.v:153793$8644 + assign { } { } + assign $0\xer_ca[1:0] \xer_ca$next + sync posedge \coresync_clk + update \xer_ca $0\xer_ca[1:0] + end + attribute \src "libresoc.v:153795.3-153796.35" + process $proc$libresoc.v:153795$8645 + assign { } { } + assign $0\xer_ca_ok[0:0] \xer_ca_ok$next + sync posedge \coresync_clk + update \xer_ca_ok $0\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:153797.3-153798.25" + process $proc$libresoc.v:153797$8646 + assign { } { } + assign $0\cr_a[3:0] \cr_a$next + sync posedge \coresync_clk + update \cr_a $0\cr_a[3:0] + end + attribute \src "libresoc.v:153799.3-153800.31" + process $proc$libresoc.v:153799$8647 + assign { } { } + assign $0\cr_a_ok[0:0] \cr_a_ok$next + sync posedge \coresync_clk + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "libresoc.v:153801.3-153802.19" + process $proc$libresoc.v:153801$8648 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] + end + attribute \src "libresoc.v:153803.3-153804.25" + process $proc$libresoc.v:153803$8649 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:153805.3-153806.51" + process $proc$libresoc.v:153805$8650 + assign { } { } + assign $0\alu_op__insn_type[6:0] \alu_op__insn_type$next + sync posedge \coresync_clk + update \alu_op__insn_type $0\alu_op__insn_type[6:0] + end + attribute \src "libresoc.v:153807.3-153808.47" + process $proc$libresoc.v:153807$8651 + assign { } { } + assign $0\alu_op__fn_unit[11:0] \alu_op__fn_unit$next + sync posedge \coresync_clk + update \alu_op__fn_unit $0\alu_op__fn_unit[11:0] + end + attribute \src "libresoc.v:153809.3-153810.61" + process $proc$libresoc.v:153809$8652 + assign { } { } + assign $0\alu_op__imm_data__data[63:0] \alu_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_op__imm_data__data $0\alu_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:153811.3-153812.57" + process $proc$libresoc.v:153811$8653 + assign { } { } + assign $0\alu_op__imm_data__ok[0:0] \alu_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_op__imm_data__ok $0\alu_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:153813.3-153814.45" + process $proc$libresoc.v:153813$8654 + assign { } { } + assign $0\alu_op__rc__rc[0:0] \alu_op__rc__rc$next + sync posedge \coresync_clk + update \alu_op__rc__rc $0\alu_op__rc__rc[0:0] + end + attribute \src "libresoc.v:153815.3-153816.45" + process $proc$libresoc.v:153815$8655 + assign { } { } + assign $0\alu_op__rc__ok[0:0] \alu_op__rc__ok$next + sync posedge \coresync_clk + update \alu_op__rc__ok $0\alu_op__rc__ok[0:0] + end + attribute \src "libresoc.v:153817.3-153818.45" + process $proc$libresoc.v:153817$8656 + assign { } { } + assign $0\alu_op__oe__oe[0:0] \alu_op__oe__oe$next + sync posedge \coresync_clk + update \alu_op__oe__oe $0\alu_op__oe__oe[0:0] + end + attribute \src "libresoc.v:153819.3-153820.45" + process $proc$libresoc.v:153819$8657 + assign { } { } + assign $0\alu_op__oe__ok[0:0] \alu_op__oe__ok$next + sync posedge \coresync_clk + update \alu_op__oe__ok $0\alu_op__oe__ok[0:0] + end + attribute \src "libresoc.v:153821.3-153822.51" + process $proc$libresoc.v:153821$8658 + assign { } { } + assign $0\alu_op__invert_in[0:0] \alu_op__invert_in$next + sync posedge \coresync_clk + update \alu_op__invert_in $0\alu_op__invert_in[0:0] + end + attribute \src "libresoc.v:153823.3-153824.45" + process $proc$libresoc.v:153823$8659 + assign { } { } + assign $0\alu_op__zero_a[0:0] \alu_op__zero_a$next + sync posedge \coresync_clk + update \alu_op__zero_a $0\alu_op__zero_a[0:0] + end + attribute \src "libresoc.v:153825.3-153826.53" + process $proc$libresoc.v:153825$8660 + assign { } { } + assign $0\alu_op__invert_out[0:0] \alu_op__invert_out$next + sync posedge \coresync_clk + update \alu_op__invert_out $0\alu_op__invert_out[0:0] + end + attribute \src "libresoc.v:153827.3-153828.51" + process $proc$libresoc.v:153827$8661 + assign { } { } + assign $0\alu_op__write_cr0[0:0] \alu_op__write_cr0$next + sync posedge \coresync_clk + update \alu_op__write_cr0 $0\alu_op__write_cr0[0:0] + end + attribute \src "libresoc.v:153829.3-153830.55" + process $proc$libresoc.v:153829$8662 + assign { } { } + assign $0\alu_op__input_carry[1:0] \alu_op__input_carry$next + sync posedge \coresync_clk + update \alu_op__input_carry $0\alu_op__input_carry[1:0] + end + attribute \src "libresoc.v:153831.3-153832.57" + process $proc$libresoc.v:153831$8663 + assign { } { } + assign $0\alu_op__output_carry[0:0] \alu_op__output_carry$next + sync posedge \coresync_clk + update \alu_op__output_carry $0\alu_op__output_carry[0:0] + end + attribute \src "libresoc.v:153833.3-153834.49" + process $proc$libresoc.v:153833$8664 + assign { } { } + assign $0\alu_op__is_32bit[0:0] \alu_op__is_32bit$next + sync posedge \coresync_clk + update \alu_op__is_32bit $0\alu_op__is_32bit[0:0] + end + attribute \src "libresoc.v:153835.3-153836.51" + process $proc$libresoc.v:153835$8665 + assign { } { } + assign $0\alu_op__is_signed[0:0] \alu_op__is_signed$next + sync posedge \coresync_clk + update \alu_op__is_signed $0\alu_op__is_signed[0:0] + end + attribute \src "libresoc.v:153837.3-153838.49" + process $proc$libresoc.v:153837$8666 + assign { } { } + assign $0\alu_op__data_len[3:0] \alu_op__data_len$next + sync posedge \coresync_clk + update \alu_op__data_len $0\alu_op__data_len[3:0] + end + attribute \src "libresoc.v:153839.3-153840.41" + process $proc$libresoc.v:153839$8667 + assign { } { } + assign $0\alu_op__insn[31:0] \alu_op__insn$next + sync posedge \coresync_clk + update \alu_op__insn $0\alu_op__insn[31:0] + end + attribute \src "libresoc.v:153841.3-153842.27" + process $proc$libresoc.v:153841$8668 + assign { } { } + assign $0\muxid[1:0] \muxid$next + sync posedge \coresync_clk + update \muxid $0\muxid[1:0] + end + attribute \src "libresoc.v:153843.3-153844.29" + process $proc$libresoc.v:153843$8669 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:153954.3-153972.6" + process $proc$libresoc.v:153954$8670 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$next[3:0]$8671 $1\cr_a$next[3:0]$8673 + assign { } { } + assign $0\cr_a_ok$next[0:0]$8672 $2\cr_a_ok$next[0:0]$8675 + attribute \src "libresoc.v:153955.5-153955.29" + switch \initial + attribute \src "libresoc.v:153955.9-153955.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$8674 $1\cr_a$next[3:0]$8673 } { \cr_a_ok$91 \cr_a$90 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$8674 $1\cr_a$next[3:0]$8673 } { \cr_a_ok$91 \cr_a$90 } + case + assign $1\cr_a$next[3:0]$8673 \cr_a + assign $1\cr_a_ok$next[0:0]$8674 \cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$next[0:0]$8675 1'0 + case + assign $2\cr_a_ok$next[0:0]$8675 $1\cr_a_ok$next[0:0]$8674 + end + sync always + update \cr_a$next $0\cr_a$next[3:0]$8671 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8672 + end + attribute \src "libresoc.v:153973.3-153991.6" + process $proc$libresoc.v:153973$8676 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ca$next[1:0]$8678 $1\xer_ca$next[1:0]$8680 + assign $0\xer_ca_ok$next[0:0]$8677 $2\xer_ca_ok$next[0:0]$8681 + attribute \src "libresoc.v:153974.5-153974.29" + switch \initial + attribute \src "libresoc.v:153974.9-153974.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$8679 $1\xer_ca$next[1:0]$8680 } { \xer_ca_ok$93 \xer_ca$92 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$8679 $1\xer_ca$next[1:0]$8680 } { \xer_ca_ok$93 \xer_ca$92 } + case + assign $1\xer_ca_ok$next[0:0]$8679 \xer_ca_ok + assign $1\xer_ca$next[1:0]$8680 \xer_ca + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ca_ok$next[0:0]$8681 1'0 + case + assign $2\xer_ca_ok$next[0:0]$8681 $1\xer_ca_ok$next[0:0]$8679 + end + sync always + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8677 + update \xer_ca$next $0\xer_ca$next[1:0]$8678 + end + attribute \src "libresoc.v:153992.3-154010.6" + process $proc$libresoc.v:153992$8682 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ov$next[1:0]$8683 $1\xer_ov$next[1:0]$8685 + assign { } { } + assign $0\xer_ov_ok$next[0:0]$8684 $2\xer_ov_ok$next[0:0]$8687 + attribute \src "libresoc.v:153993.5-153993.29" + switch \initial + attribute \src "libresoc.v:153993.9-153993.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$8686 $1\xer_ov$next[1:0]$8685 } { \xer_ov_ok$95 \xer_ov$94 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$8686 $1\xer_ov$next[1:0]$8685 } { \xer_ov_ok$95 \xer_ov$94 } + case + assign $1\xer_ov$next[1:0]$8685 \xer_ov + assign $1\xer_ov_ok$next[0:0]$8686 \xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ov_ok$next[0:0]$8687 1'0 + case + assign $2\xer_ov_ok$next[0:0]$8687 $1\xer_ov_ok$next[0:0]$8686 + end + sync always + update \xer_ov$next $0\xer_ov$next[1:0]$8683 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8684 + end + attribute \src "libresoc.v:154011.3-154029.6" + process $proc$libresoc.v:154011$8688 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$next[0:0]$8689 $1\xer_so$next[0:0]$8691 + assign { } { } + assign $0\xer_so_ok$next[0:0]$8690 $2\xer_so_ok$next[0:0]$8693 + attribute \src "libresoc.v:154012.5-154012.29" + switch \initial + attribute \src "libresoc.v:154012.9-154012.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$8692 $1\xer_so$next[0:0]$8691 } { \xer_so_ok$97 \xer_so$96 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$8692 $1\xer_so$next[0:0]$8691 } { \xer_so_ok$97 \xer_so$96 } + case + assign $1\xer_so$next[0:0]$8691 \xer_so + assign $1\xer_so_ok$next[0:0]$8692 \xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$next[0:0]$8693 1'0 + case + assign $2\xer_so_ok$next[0:0]$8693 $1\xer_so_ok$next[0:0]$8692 + end + sync always + update \xer_so$next $0\xer_so$next[0:0]$8689 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8690 + end + attribute \src "libresoc.v:154030.3-154047.6" + process $proc$libresoc.v:154030$8694 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$8695 $2\r_busy$next[0:0]$8697 + attribute \src "libresoc.v:154031.5-154031.29" + switch \initial + attribute \src "libresoc.v:154031.9-154031.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$8696 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$8696 1'0 + case + assign $1\r_busy$next[0:0]$8696 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$8697 1'0 + case + assign $2\r_busy$next[0:0]$8697 $1\r_busy$next[0:0]$8696 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$8695 + end + attribute \src "libresoc.v:154048.3-154060.6" + process $proc$libresoc.v:154048$8698 + assign { } { } + assign { } { } + assign $0\muxid$next[1:0]$8699 $1\muxid$next[1:0]$8700 + attribute \src "libresoc.v:154049.5-154049.29" + switch \initial + attribute \src "libresoc.v:154049.9-154049.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$next[1:0]$8700 \muxid$69 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$next[1:0]$8700 \muxid$69 + case + assign $1\muxid$next[1:0]$8700 \muxid + end + sync always + update \muxid$next $0\muxid$next[1:0]$8699 + end + attribute \src "libresoc.v:154061.3-154102.6" + process $proc$libresoc.v:154061$8701 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_op__data_len$next[3:0]$8702 $1\alu_op__data_len$next[3:0]$8720 + assign $0\alu_op__fn_unit$next[11:0]$8703 $1\alu_op__fn_unit$next[11:0]$8721 + assign { } { } + assign { } { } + assign $0\alu_op__input_carry$next[1:0]$8706 $1\alu_op__input_carry$next[1:0]$8724 + assign $0\alu_op__insn$next[31:0]$8707 $1\alu_op__insn$next[31:0]$8725 + assign $0\alu_op__insn_type$next[6:0]$8708 $1\alu_op__insn_type$next[6:0]$8726 + assign $0\alu_op__invert_in$next[0:0]$8709 $1\alu_op__invert_in$next[0:0]$8727 + assign $0\alu_op__invert_out$next[0:0]$8710 $1\alu_op__invert_out$next[0:0]$8728 + assign $0\alu_op__is_32bit$next[0:0]$8711 $1\alu_op__is_32bit$next[0:0]$8729 + assign $0\alu_op__is_signed$next[0:0]$8712 $1\alu_op__is_signed$next[0:0]$8730 + assign { } { } + assign { } { } + assign $0\alu_op__output_carry$next[0:0]$8715 $1\alu_op__output_carry$next[0:0]$8733 + assign { } { } + assign { } { } + assign $0\alu_op__write_cr0$next[0:0]$8718 $1\alu_op__write_cr0$next[0:0]$8736 + assign $0\alu_op__zero_a$next[0:0]$8719 $1\alu_op__zero_a$next[0:0]$8737 + assign $0\alu_op__imm_data__data$next[63:0]$8704 $2\alu_op__imm_data__data$next[63:0]$8738 + assign $0\alu_op__imm_data__ok$next[0:0]$8705 $2\alu_op__imm_data__ok$next[0:0]$8739 + assign $0\alu_op__oe__oe$next[0:0]$8713 $2\alu_op__oe__oe$next[0:0]$8740 + assign $0\alu_op__oe__ok$next[0:0]$8714 $2\alu_op__oe__ok$next[0:0]$8741 + assign $0\alu_op__rc__ok$next[0:0]$8716 $2\alu_op__rc__ok$next[0:0]$8742 + assign $0\alu_op__rc__rc$next[0:0]$8717 $2\alu_op__rc__rc$next[0:0]$8743 + attribute \src "libresoc.v:154062.5-154062.29" + switch \initial + attribute \src "libresoc.v:154062.9-154062.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_op__insn$next[31:0]$8725 $1\alu_op__data_len$next[3:0]$8720 $1\alu_op__is_signed$next[0:0]$8730 $1\alu_op__is_32bit$next[0:0]$8729 $1\alu_op__output_carry$next[0:0]$8733 $1\alu_op__input_carry$next[1:0]$8724 $1\alu_op__write_cr0$next[0:0]$8736 $1\alu_op__invert_out$next[0:0]$8728 $1\alu_op__zero_a$next[0:0]$8737 $1\alu_op__invert_in$next[0:0]$8727 $1\alu_op__oe__ok$next[0:0]$8732 $1\alu_op__oe__oe$next[0:0]$8731 $1\alu_op__rc__ok$next[0:0]$8734 $1\alu_op__rc__rc$next[0:0]$8735 $1\alu_op__imm_data__ok$next[0:0]$8723 $1\alu_op__imm_data__data$next[63:0]$8722 $1\alu_op__fn_unit$next[11:0]$8721 $1\alu_op__insn_type$next[6:0]$8726 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_op__insn$next[31:0]$8725 $1\alu_op__data_len$next[3:0]$8720 $1\alu_op__is_signed$next[0:0]$8730 $1\alu_op__is_32bit$next[0:0]$8729 $1\alu_op__output_carry$next[0:0]$8733 $1\alu_op__input_carry$next[1:0]$8724 $1\alu_op__write_cr0$next[0:0]$8736 $1\alu_op__invert_out$next[0:0]$8728 $1\alu_op__zero_a$next[0:0]$8737 $1\alu_op__invert_in$next[0:0]$8727 $1\alu_op__oe__ok$next[0:0]$8732 $1\alu_op__oe__oe$next[0:0]$8731 $1\alu_op__rc__ok$next[0:0]$8734 $1\alu_op__rc__rc$next[0:0]$8735 $1\alu_op__imm_data__ok$next[0:0]$8723 $1\alu_op__imm_data__data$next[63:0]$8722 $1\alu_op__fn_unit$next[11:0]$8721 $1\alu_op__insn_type$next[6:0]$8726 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } + case + assign $1\alu_op__data_len$next[3:0]$8720 \alu_op__data_len + assign $1\alu_op__fn_unit$next[11:0]$8721 \alu_op__fn_unit + assign $1\alu_op__imm_data__data$next[63:0]$8722 \alu_op__imm_data__data + assign $1\alu_op__imm_data__ok$next[0:0]$8723 \alu_op__imm_data__ok + assign $1\alu_op__input_carry$next[1:0]$8724 \alu_op__input_carry + assign $1\alu_op__insn$next[31:0]$8725 \alu_op__insn + assign $1\alu_op__insn_type$next[6:0]$8726 \alu_op__insn_type + assign $1\alu_op__invert_in$next[0:0]$8727 \alu_op__invert_in + assign $1\alu_op__invert_out$next[0:0]$8728 \alu_op__invert_out + assign $1\alu_op__is_32bit$next[0:0]$8729 \alu_op__is_32bit + assign $1\alu_op__is_signed$next[0:0]$8730 \alu_op__is_signed + assign $1\alu_op__oe__oe$next[0:0]$8731 \alu_op__oe__oe + assign $1\alu_op__oe__ok$next[0:0]$8732 \alu_op__oe__ok + assign $1\alu_op__output_carry$next[0:0]$8733 \alu_op__output_carry + assign $1\alu_op__rc__ok$next[0:0]$8734 \alu_op__rc__ok + assign $1\alu_op__rc__rc$next[0:0]$8735 \alu_op__rc__rc + assign $1\alu_op__write_cr0$next[0:0]$8736 \alu_op__write_cr0 + assign $1\alu_op__zero_a$next[0:0]$8737 \alu_op__zero_a + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_op__imm_data__data$next[63:0]$8738 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_op__imm_data__ok$next[0:0]$8739 1'0 + assign $2\alu_op__rc__rc$next[0:0]$8743 1'0 + assign $2\alu_op__rc__ok$next[0:0]$8742 1'0 + assign $2\alu_op__oe__oe$next[0:0]$8740 1'0 + assign $2\alu_op__oe__ok$next[0:0]$8741 1'0 + case + assign $2\alu_op__imm_data__data$next[63:0]$8738 $1\alu_op__imm_data__data$next[63:0]$8722 + assign $2\alu_op__imm_data__ok$next[0:0]$8739 $1\alu_op__imm_data__ok$next[0:0]$8723 + assign $2\alu_op__oe__oe$next[0:0]$8740 $1\alu_op__oe__oe$next[0:0]$8731 + assign $2\alu_op__oe__ok$next[0:0]$8741 $1\alu_op__oe__ok$next[0:0]$8732 + assign $2\alu_op__rc__ok$next[0:0]$8742 $1\alu_op__rc__ok$next[0:0]$8734 + assign $2\alu_op__rc__rc$next[0:0]$8743 $1\alu_op__rc__rc$next[0:0]$8735 + end + sync always + update \alu_op__data_len$next $0\alu_op__data_len$next[3:0]$8702 + update \alu_op__fn_unit$next $0\alu_op__fn_unit$next[11:0]$8703 + update \alu_op__imm_data__data$next $0\alu_op__imm_data__data$next[63:0]$8704 + update \alu_op__imm_data__ok$next $0\alu_op__imm_data__ok$next[0:0]$8705 + update \alu_op__input_carry$next $0\alu_op__input_carry$next[1:0]$8706 + update \alu_op__insn$next $0\alu_op__insn$next[31:0]$8707 + update \alu_op__insn_type$next $0\alu_op__insn_type$next[6:0]$8708 + update \alu_op__invert_in$next $0\alu_op__invert_in$next[0:0]$8709 + update \alu_op__invert_out$next $0\alu_op__invert_out$next[0:0]$8710 + update \alu_op__is_32bit$next $0\alu_op__is_32bit$next[0:0]$8711 + update \alu_op__is_signed$next $0\alu_op__is_signed$next[0:0]$8712 + update \alu_op__oe__oe$next $0\alu_op__oe__oe$next[0:0]$8713 + update \alu_op__oe__ok$next $0\alu_op__oe__ok$next[0:0]$8714 + update \alu_op__output_carry$next $0\alu_op__output_carry$next[0:0]$8715 + update \alu_op__rc__ok$next $0\alu_op__rc__ok$next[0:0]$8716 + update \alu_op__rc__rc$next $0\alu_op__rc__rc$next[0:0]$8717 + update \alu_op__write_cr0$next $0\alu_op__write_cr0$next[0:0]$8718 + update \alu_op__zero_a$next $0\alu_op__zero_a$next[0:0]$8719 + end + attribute \src "libresoc.v:154103.3-154121.6" + process $proc$libresoc.v:154103$8744 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$8745 $1\o$next[63:0]$8747 + assign { } { } + assign $0\o_ok$next[0:0]$8746 $2\o_ok$next[0:0]$8749 + attribute \src "libresoc.v:154104.5-154104.29" + switch \initial + attribute \src "libresoc.v:154104.9-154104.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8748 $1\o$next[63:0]$8747 } { \o_ok$89 \o$88 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8748 $1\o$next[63:0]$8747 } { \o_ok$89 \o$88 } + case + assign $1\o$next[63:0]$8747 \o + assign $1\o_ok$next[0:0]$8748 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$8749 1'0 + case + assign $2\o_ok$next[0:0]$8749 $1\o_ok$next[0:0]$8748 + end + sync always + update \o$next $0\o$next[63:0]$8745 + update \o_ok$next $0\o_ok$next[0:0]$8746 + end + connect \$67 $and$libresoc.v:153784$8639_Y + connect \xer_so_ok$98 1'0 + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_so_ok$97 \xer_so$96 } { 1'0 \main_xer_so$65 } + connect { \xer_ov_ok$95 \xer_ov$94 } { \main_xer_ov_ok \main_xer_ov } + connect { \xer_ca_ok$93 \xer_ca$92 } { \main_xer_ca_ok \main_xer_ca$64 } + connect { \cr_a_ok$91 \cr_a$90 } { \main_cr_a_ok \main_cr_a } + connect { \o_ok$89 \o$88 } { \main_o_ok \main_o } + connect { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } { \main_alu_op__insn$63 \main_alu_op__data_len$62 \main_alu_op__is_signed$61 \main_alu_op__is_32bit$60 \main_alu_op__output_carry$59 \main_alu_op__input_carry$58 \main_alu_op__write_cr0$57 \main_alu_op__invert_out$56 \main_alu_op__zero_a$55 \main_alu_op__invert_in$54 \main_alu_op__oe__ok$53 \main_alu_op__oe__oe$52 \main_alu_op__rc__ok$51 \main_alu_op__rc__rc$50 \main_alu_op__imm_data__ok$49 \main_alu_op__imm_data__data$48 \main_alu_op__fn_unit$47 \main_alu_op__insn_type$46 } + connect \muxid$69 \main_muxid$45 + connect \p_valid_i_p_ready_o \$67 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$66 \p_valid_i + connect \main_xer_ca \input_xer_ca$44 + connect \main_xer_so \input_xer_so$43 + connect \main_rb \input_rb$42 + connect \main_ra \input_ra$41 + connect { \main_alu_op__insn \main_alu_op__data_len \main_alu_op__is_signed \main_alu_op__is_32bit \main_alu_op__output_carry \main_alu_op__input_carry \main_alu_op__write_cr0 \main_alu_op__invert_out \main_alu_op__zero_a \main_alu_op__invert_in \main_alu_op__oe__ok \main_alu_op__oe__oe \main_alu_op__rc__ok \main_alu_op__rc__rc \main_alu_op__imm_data__ok \main_alu_op__imm_data__data \main_alu_op__fn_unit \main_alu_op__insn_type } { \input_alu_op__insn$40 \input_alu_op__data_len$39 \input_alu_op__is_signed$38 \input_alu_op__is_32bit$37 \input_alu_op__output_carry$36 \input_alu_op__input_carry$35 \input_alu_op__write_cr0$34 \input_alu_op__invert_out$33 \input_alu_op__zero_a$32 \input_alu_op__invert_in$31 \input_alu_op__oe__ok$30 \input_alu_op__oe__oe$29 \input_alu_op__rc__ok$28 \input_alu_op__rc__rc$27 \input_alu_op__imm_data__ok$26 \input_alu_op__imm_data__data$25 \input_alu_op__fn_unit$24 \input_alu_op__insn_type$23 } + connect \main_muxid \input_muxid$22 + connect \input_xer_ca \xer_ca$21 + connect \input_xer_so \xer_so$20 + connect \input_rb \rb + connect \input_ra \ra + connect { \input_alu_op__insn \input_alu_op__data_len \input_alu_op__is_signed \input_alu_op__is_32bit \input_alu_op__output_carry \input_alu_op__input_carry \input_alu_op__write_cr0 \input_alu_op__invert_out \input_alu_op__zero_a \input_alu_op__invert_in \input_alu_op__oe__ok \input_alu_op__oe__oe \input_alu_op__rc__ok \input_alu_op__rc__rc \input_alu_op__imm_data__ok \input_alu_op__imm_data__data \input_alu_op__fn_unit \input_alu_op__insn_type } { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } + connect \input_muxid \muxid$1 +end +attribute \src "libresoc.v:154151.1-155566.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1" +attribute \generator "nMigen" +module \pipe1$110 + attribute \src "libresoc.v:155499.3-155517.6" + wire width 4 $0\cr_a$next[3:0]$8870 + attribute \src "libresoc.v:155241.3-155242.25" + wire width 4 $0\cr_a[3:0] + attribute \src "libresoc.v:155499.3-155517.6" + wire $0\cr_a_ok$next[0:0]$8871 + attribute \src "libresoc.v:155243.3-155244.31" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:154152.7-154152.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:155426.3-155438.6" + wire width 2 $0\muxid$next[1:0]$8820 + attribute \src "libresoc.v:155283.3-155284.27" + wire width 2 $0\muxid[1:0] + attribute \src "libresoc.v:155480.3-155498.6" + wire width 64 $0\o$next[63:0]$8864 + attribute \src "libresoc.v:155245.3-155246.19" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:155480.3-155498.6" + wire $0\o_ok$next[0:0]$8865 + attribute \src "libresoc.v:155247.3-155248.25" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:155408.3-155425.6" + wire $0\r_busy$next[0:0]$8816 + attribute \src "libresoc.v:155285.3-155286.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:155439.3-155479.6" + wire width 12 $0\sr_op__fn_unit$next[11:0]$8823 + attribute \src "libresoc.v:155251.3-155252.45" + wire width 12 $0\sr_op__fn_unit[11:0] + attribute \src "libresoc.v:155439.3-155479.6" + wire width 64 $0\sr_op__imm_data__data$next[63:0]$8824 + attribute \src "libresoc.v:155253.3-155254.59" + wire width 64 $0\sr_op__imm_data__data[63:0] + attribute \src "libresoc.v:155439.3-155479.6" + wire $0\sr_op__imm_data__ok$next[0:0]$8825 + attribute \src "libresoc.v:155255.3-155256.55" + wire $0\sr_op__imm_data__ok[0:0] + attribute \src "libresoc.v:155439.3-155479.6" + wire width 2 $0\sr_op__input_carry$next[1:0]$8826 + attribute \src "libresoc.v:155269.3-155270.53" + wire width 2 $0\sr_op__input_carry[1:0] + attribute \src "libresoc.v:155439.3-155479.6" + wire $0\sr_op__input_cr$next[0:0]$8827 + attribute \src "libresoc.v:155273.3-155274.47" + wire $0\sr_op__input_cr[0:0] + attribute \src "libresoc.v:155439.3-155479.6" + wire width 32 $0\sr_op__insn$next[31:0]$8828 + attribute \src "libresoc.v:155281.3-155282.39" + wire width 32 $0\sr_op__insn[31:0] + attribute \src "libresoc.v:155439.3-155479.6" + wire width 7 $0\sr_op__insn_type$next[6:0]$8829 + attribute \src "libresoc.v:155249.3-155250.49" + wire width 7 $0\sr_op__insn_type[6:0] + attribute \src "libresoc.v:155439.3-155479.6" + wire $0\sr_op__invert_in$next[0:0]$8830 + attribute \src "libresoc.v:155267.3-155268.49" + wire $0\sr_op__invert_in[0:0] + attribute \src "libresoc.v:155439.3-155479.6" + wire $0\sr_op__is_32bit$next[0:0]$8831 + attribute \src "libresoc.v:155277.3-155278.47" + wire $0\sr_op__is_32bit[0:0] + attribute \src "libresoc.v:155439.3-155479.6" + wire $0\sr_op__is_signed$next[0:0]$8832 + attribute \src "libresoc.v:155279.3-155280.49" + wire $0\sr_op__is_signed[0:0] + attribute \src "libresoc.v:155439.3-155479.6" + wire $0\sr_op__oe__oe$next[0:0]$8833 + attribute \src "libresoc.v:155261.3-155262.43" + wire $0\sr_op__oe__oe[0:0] + attribute \src "libresoc.v:155439.3-155479.6" + wire $0\sr_op__oe__ok$next[0:0]$8834 + attribute \src "libresoc.v:155263.3-155264.43" + wire $0\sr_op__oe__ok[0:0] + attribute \src "libresoc.v:155439.3-155479.6" + wire $0\sr_op__output_carry$next[0:0]$8835 + attribute \src "libresoc.v:155271.3-155272.55" + wire $0\sr_op__output_carry[0:0] + attribute \src "libresoc.v:155439.3-155479.6" + wire $0\sr_op__output_cr$next[0:0]$8836 + attribute \src "libresoc.v:155275.3-155276.49" + wire $0\sr_op__output_cr[0:0] + attribute \src "libresoc.v:155439.3-155479.6" + wire $0\sr_op__rc__ok$next[0:0]$8837 + attribute \src "libresoc.v:155259.3-155260.43" + wire $0\sr_op__rc__ok[0:0] + attribute \src "libresoc.v:155439.3-155479.6" + wire $0\sr_op__rc__rc$next[0:0]$8838 + attribute \src "libresoc.v:155257.3-155258.43" + wire $0\sr_op__rc__rc[0:0] + attribute \src "libresoc.v:155439.3-155479.6" + wire $0\sr_op__write_cr0$next[0:0]$8839 + attribute \src "libresoc.v:155265.3-155266.49" + wire $0\sr_op__write_cr0[0:0] + attribute \src "libresoc.v:155389.3-155407.6" + wire width 2 $0\xer_ca$next[1:0]$8811 + attribute \src "libresoc.v:155233.3-155234.29" + wire width 2 $0\xer_ca[1:0] + attribute \src "libresoc.v:155389.3-155407.6" + wire $0\xer_ca_ok$next[0:0]$8810 + attribute \src "libresoc.v:155235.3-155236.35" + wire $0\xer_ca_ok[0:0] + attribute \src "libresoc.v:155518.3-155536.6" + wire $0\xer_so$next[0:0]$8876 + attribute \src "libresoc.v:155237.3-155238.29" + wire $0\xer_so[0:0] + attribute \src "libresoc.v:155518.3-155536.6" + wire $0\xer_so_ok$next[0:0]$8877 + attribute \src "libresoc.v:155239.3-155240.35" + wire $0\xer_so_ok[0:0] + attribute \src "libresoc.v:155499.3-155517.6" + wire width 4 $1\cr_a$next[3:0]$8872 + attribute \src "libresoc.v:154161.13-154161.24" + wire width 4 $1\cr_a[3:0] + attribute \src "libresoc.v:155499.3-155517.6" + wire $1\cr_a_ok$next[0:0]$8873 + attribute \src "libresoc.v:154170.7-154170.21" + wire $1\cr_a_ok[0:0] + attribute \src "libresoc.v:155426.3-155438.6" + wire width 2 $1\muxid$next[1:0]$8821 + attribute \src "libresoc.v:154723.13-154723.25" + wire width 2 $1\muxid[1:0] + attribute \src "libresoc.v:155480.3-155498.6" + wire width 64 $1\o$next[63:0]$8866 + attribute \src "libresoc.v:154738.14-154738.38" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:155480.3-155498.6" + wire $1\o_ok$next[0:0]$8867 + attribute \src "libresoc.v:154745.7-154745.18" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:155408.3-155425.6" + wire $1\r_busy$next[0:0]$8817 + attribute \src "libresoc.v:154759.7-154759.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:155439.3-155479.6" + wire width 12 $1\sr_op__fn_unit$next[11:0]$8840 + attribute \src "libresoc.v:154783.14-154783.38" + wire width 12 $1\sr_op__fn_unit[11:0] + attribute \src "libresoc.v:155439.3-155479.6" + wire width 64 $1\sr_op__imm_data__data$next[63:0]$8841 + attribute \src "libresoc.v:154818.14-154818.58" + wire width 64 $1\sr_op__imm_data__data[63:0] + attribute \src "libresoc.v:155439.3-155479.6" + wire $1\sr_op__imm_data__ok$next[0:0]$8842 + attribute \src "libresoc.v:154827.7-154827.33" + wire $1\sr_op__imm_data__ok[0:0] + attribute \src "libresoc.v:155439.3-155479.6" + wire width 2 $1\sr_op__input_carry$next[1:0]$8843 + attribute \src "libresoc.v:154840.13-154840.38" + wire width 2 $1\sr_op__input_carry[1:0] + attribute \src "libresoc.v:155439.3-155479.6" + wire $1\sr_op__input_cr$next[0:0]$8844 + attribute \src "libresoc.v:154857.7-154857.29" + wire $1\sr_op__input_cr[0:0] + attribute \src "libresoc.v:155439.3-155479.6" + wire width 32 $1\sr_op__insn$next[31:0]$8845 + attribute \src "libresoc.v:154866.14-154866.33" + wire width 32 $1\sr_op__insn[31:0] + attribute \src "libresoc.v:155439.3-155479.6" + wire width 7 $1\sr_op__insn_type$next[6:0]$8846 + attribute \src "libresoc.v:154949.13-154949.37" + wire width 7 $1\sr_op__insn_type[6:0] + attribute \src "libresoc.v:155439.3-155479.6" + wire $1\sr_op__invert_in$next[0:0]$8847 + attribute \src "libresoc.v:155106.7-155106.30" + wire $1\sr_op__invert_in[0:0] + attribute \src "libresoc.v:155439.3-155479.6" + wire $1\sr_op__is_32bit$next[0:0]$8848 + attribute \src "libresoc.v:155115.7-155115.29" + wire $1\sr_op__is_32bit[0:0] + attribute \src "libresoc.v:155439.3-155479.6" + wire $1\sr_op__is_signed$next[0:0]$8849 + attribute \src "libresoc.v:155124.7-155124.30" + wire $1\sr_op__is_signed[0:0] + attribute \src "libresoc.v:155439.3-155479.6" + wire $1\sr_op__oe__oe$next[0:0]$8850 + attribute \src "libresoc.v:155133.7-155133.27" + wire $1\sr_op__oe__oe[0:0] + attribute \src "libresoc.v:155439.3-155479.6" + wire $1\sr_op__oe__ok$next[0:0]$8851 + attribute \src "libresoc.v:155142.7-155142.27" + wire $1\sr_op__oe__ok[0:0] + attribute \src "libresoc.v:155439.3-155479.6" + wire $1\sr_op__output_carry$next[0:0]$8852 + attribute \src "libresoc.v:155151.7-155151.33" + wire $1\sr_op__output_carry[0:0] + attribute \src "libresoc.v:155439.3-155479.6" + wire $1\sr_op__output_cr$next[0:0]$8853 + attribute \src "libresoc.v:155160.7-155160.30" + wire $1\sr_op__output_cr[0:0] + attribute \src "libresoc.v:155439.3-155479.6" + wire $1\sr_op__rc__ok$next[0:0]$8854 + attribute \src "libresoc.v:155169.7-155169.27" + wire $1\sr_op__rc__ok[0:0] + attribute \src "libresoc.v:155439.3-155479.6" + wire $1\sr_op__rc__rc$next[0:0]$8855 + attribute \src "libresoc.v:155178.7-155178.27" + wire $1\sr_op__rc__rc[0:0] + attribute \src "libresoc.v:155439.3-155479.6" + wire $1\sr_op__write_cr0$next[0:0]$8856 + attribute \src "libresoc.v:155187.7-155187.30" + wire $1\sr_op__write_cr0[0:0] + attribute \src "libresoc.v:155389.3-155407.6" + wire width 2 $1\xer_ca$next[1:0]$8813 + attribute \src "libresoc.v:155196.13-155196.26" + wire width 2 $1\xer_ca[1:0] + attribute \src "libresoc.v:155389.3-155407.6" + wire $1\xer_ca_ok$next[0:0]$8812 + attribute \src "libresoc.v:155207.7-155207.23" + wire $1\xer_ca_ok[0:0] + attribute \src "libresoc.v:155518.3-155536.6" + wire $1\xer_so$next[0:0]$8878 + attribute \src "libresoc.v:155216.7-155216.20" + wire $1\xer_so[0:0] + attribute \src "libresoc.v:155518.3-155536.6" + wire $1\xer_so_ok$next[0:0]$8879 + attribute \src "libresoc.v:155225.7-155225.23" + wire $1\xer_so_ok[0:0] + attribute \src "libresoc.v:155499.3-155517.6" + wire $2\cr_a_ok$next[0:0]$8874 + attribute \src "libresoc.v:155480.3-155498.6" + wire $2\o_ok$next[0:0]$8868 + attribute \src "libresoc.v:155408.3-155425.6" + wire $2\r_busy$next[0:0]$8818 + attribute \src "libresoc.v:155439.3-155479.6" + wire width 64 $2\sr_op__imm_data__data$next[63:0]$8857 + attribute \src "libresoc.v:155439.3-155479.6" + wire $2\sr_op__imm_data__ok$next[0:0]$8858 + attribute \src "libresoc.v:155439.3-155479.6" + wire $2\sr_op__oe__oe$next[0:0]$8859 + attribute \src "libresoc.v:155439.3-155479.6" + wire $2\sr_op__oe__ok$next[0:0]$8860 + attribute \src "libresoc.v:155439.3-155479.6" + wire $2\sr_op__rc__ok$next[0:0]$8861 + attribute \src "libresoc.v:155439.3-155479.6" + wire $2\sr_op__rc__rc$next[0:0]$8862 + attribute \src "libresoc.v:155389.3-155407.6" + wire $2\xer_ca_ok$next[0:0]$8814 + attribute \src "libresoc.v:155518.3-155536.6" + wire $2\xer_so_ok$next[0:0]$8880 + attribute \src "libresoc.v:155232.18-155232.118" + wire $and$libresoc.v:155232$8781_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 55 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 24 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 25 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$next + attribute \src "libresoc.v:154152.7-154152.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rc$41 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \input_sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \input_sr_op__fn_unit$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_sr_op__imm_data__data$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__imm_data__ok$25 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_sr_op__input_carry$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__input_cr$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_sr_op__insn$38 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_sr_op__insn_type$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__invert_in$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__is_32bit$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__is_signed$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__oe__oe$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__oe__ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__output_carry$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__output_cr$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__rc__ok$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__rc__rc$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__write_cr0$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \input_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \input_xer_ca$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so$42 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rc + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \main_sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \main_sr_op__fn_unit$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_sr_op__imm_data__data$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__imm_data__ok$48 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_sr_op__input_carry$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__input_cr$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_sr_op__insn$61 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_sr_op__insn_type$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__invert_in$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__is_32bit$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__is_signed$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__oe__oe$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__oe__ok$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__output_carry$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__output_cr$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__rc__ok$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__rc__rc$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__write_cr0$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \main_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \main_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_xer_so$62 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 32 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$67 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 22 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 23 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 31 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 30 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$64 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 50 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 51 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 52 \rc + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 6 \sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 34 \sr_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \sr_op__fn_unit$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \sr_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 35 \sr_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__data$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 36 \sr_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__imm_data__ok$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 15 \sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 43 \sr_op__input_carry$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \sr_op__input_carry$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \sr_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 45 \sr_op__input_cr$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__input_cr$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__input_cr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 21 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 49 \sr_op__insn$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 5 \sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 33 \sr_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \sr_op__insn_type$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \sr_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \sr_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 42 \sr_op__invert_in$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__invert_in$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 19 \sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 47 \sr_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_32bit$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 48 \sr_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_signed$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__oe$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 39 \sr_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__ok$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 40 \sr_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 44 \sr_op__output_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_carry$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 18 \sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 46 \sr_op__output_cr$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_cr$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_cr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 38 \sr_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__ok$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 37 \sr_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__rc$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 41 \sr_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__write_cr0$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 28 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 54 \xer_ca$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \xer_ca$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 29 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 26 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 53 \xer_so$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 27 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$libresoc.v:155232$8781 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$64 + connect \B \p_ready_o + connect \Y $and$libresoc.v:155232$8781_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:155287.15-155334.4" + cell \input$113 \input + connect \muxid \input_muxid + connect \muxid$1 \input_muxid$21 + connect \ra \input_ra + connect \ra$19 \input_ra$39 + connect \rb \input_rb + connect \rb$20 \input_rb$40 + connect \rc \input_rc + connect \rc$21 \input_rc$41 + connect \sr_op__fn_unit \input_sr_op__fn_unit + connect \sr_op__fn_unit$3 \input_sr_op__fn_unit$23 + connect \sr_op__imm_data__data \input_sr_op__imm_data__data + connect \sr_op__imm_data__data$4 \input_sr_op__imm_data__data$24 + connect \sr_op__imm_data__ok \input_sr_op__imm_data__ok + connect \sr_op__imm_data__ok$5 \input_sr_op__imm_data__ok$25 + connect \sr_op__input_carry \input_sr_op__input_carry + connect \sr_op__input_carry$12 \input_sr_op__input_carry$32 + connect \sr_op__input_cr \input_sr_op__input_cr + connect \sr_op__input_cr$14 \input_sr_op__input_cr$34 + connect \sr_op__insn \input_sr_op__insn + connect \sr_op__insn$18 \input_sr_op__insn$38 + connect \sr_op__insn_type \input_sr_op__insn_type + connect \sr_op__insn_type$2 \input_sr_op__insn_type$22 + connect \sr_op__invert_in \input_sr_op__invert_in + connect \sr_op__invert_in$11 \input_sr_op__invert_in$31 + connect \sr_op__is_32bit \input_sr_op__is_32bit + connect \sr_op__is_32bit$16 \input_sr_op__is_32bit$36 + connect \sr_op__is_signed \input_sr_op__is_signed + connect \sr_op__is_signed$17 \input_sr_op__is_signed$37 + connect \sr_op__oe__oe \input_sr_op__oe__oe + connect \sr_op__oe__oe$8 \input_sr_op__oe__oe$28 + connect \sr_op__oe__ok \input_sr_op__oe__ok + connect \sr_op__oe__ok$9 \input_sr_op__oe__ok$29 + connect \sr_op__output_carry \input_sr_op__output_carry + connect \sr_op__output_carry$13 \input_sr_op__output_carry$33 + connect \sr_op__output_cr \input_sr_op__output_cr + connect \sr_op__output_cr$15 \input_sr_op__output_cr$35 + connect \sr_op__rc__ok \input_sr_op__rc__ok + connect \sr_op__rc__ok$7 \input_sr_op__rc__ok$27 + connect \sr_op__rc__rc \input_sr_op__rc__rc + connect \sr_op__rc__rc$6 \input_sr_op__rc__rc$26 + connect \sr_op__write_cr0 \input_sr_op__write_cr0 + connect \sr_op__write_cr0$10 \input_sr_op__write_cr0$30 + connect \xer_ca \input_xer_ca + connect \xer_ca$23 \input_xer_ca$43 + connect \xer_so \input_xer_so + connect \xer_so$22 \input_xer_so$42 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:155335.14-155380.4" + cell \main$114 \main + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$44 + connect \o \main_o + connect \o_ok \main_o_ok + connect \ra \main_ra + connect \rb \main_rb + connect \rc \main_rc + connect \sr_op__fn_unit \main_sr_op__fn_unit + connect \sr_op__fn_unit$3 \main_sr_op__fn_unit$46 + connect \sr_op__imm_data__data \main_sr_op__imm_data__data + connect \sr_op__imm_data__data$4 \main_sr_op__imm_data__data$47 + connect \sr_op__imm_data__ok \main_sr_op__imm_data__ok + connect \sr_op__imm_data__ok$5 \main_sr_op__imm_data__ok$48 + connect \sr_op__input_carry \main_sr_op__input_carry + connect \sr_op__input_carry$12 \main_sr_op__input_carry$55 + connect \sr_op__input_cr \main_sr_op__input_cr + connect \sr_op__input_cr$14 \main_sr_op__input_cr$57 + connect \sr_op__insn \main_sr_op__insn + connect \sr_op__insn$18 \main_sr_op__insn$61 + connect \sr_op__insn_type \main_sr_op__insn_type + connect \sr_op__insn_type$2 \main_sr_op__insn_type$45 + connect \sr_op__invert_in \main_sr_op__invert_in + connect \sr_op__invert_in$11 \main_sr_op__invert_in$54 + connect \sr_op__is_32bit \main_sr_op__is_32bit + connect \sr_op__is_32bit$16 \main_sr_op__is_32bit$59 + connect \sr_op__is_signed \main_sr_op__is_signed + connect \sr_op__is_signed$17 \main_sr_op__is_signed$60 + connect \sr_op__oe__oe \main_sr_op__oe__oe + connect \sr_op__oe__oe$8 \main_sr_op__oe__oe$51 + connect \sr_op__oe__ok \main_sr_op__oe__ok + connect \sr_op__oe__ok$9 \main_sr_op__oe__ok$52 + connect \sr_op__output_carry \main_sr_op__output_carry + connect \sr_op__output_carry$13 \main_sr_op__output_carry$56 + connect \sr_op__output_cr \main_sr_op__output_cr + connect \sr_op__output_cr$15 \main_sr_op__output_cr$58 + connect \sr_op__rc__ok \main_sr_op__rc__ok + connect \sr_op__rc__ok$7 \main_sr_op__rc__ok$50 + connect \sr_op__rc__rc \main_sr_op__rc__rc + connect \sr_op__rc__rc$6 \main_sr_op__rc__rc$49 + connect \sr_op__write_cr0 \main_sr_op__write_cr0 + connect \sr_op__write_cr0$10 \main_sr_op__write_cr0$53 + connect \xer_ca \main_xer_ca + connect \xer_so \main_xer_so + connect \xer_so$19 \main_xer_so$62 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:155381.11-155384.4" + cell \n$112 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:155385.11-155388.4" + cell \p$111 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:154152.7-154152.20" + process $proc$libresoc.v:154152$8881 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:154161.13-154161.24" + process $proc$libresoc.v:154161$8882 + assign { } { } + assign $1\cr_a[3:0] 4'0000 + sync always + sync init + update \cr_a $1\cr_a[3:0] + end + attribute \src "libresoc.v:154170.7-154170.21" + process $proc$libresoc.v:154170$8883 + assign { } { } + assign $1\cr_a_ok[0:0] 1'0 + sync always + sync init + update \cr_a_ok $1\cr_a_ok[0:0] + end + attribute \src "libresoc.v:154723.13-154723.25" + process $proc$libresoc.v:154723$8884 + assign { } { } + assign $1\muxid[1:0] 2'00 + sync always + sync init + update \muxid $1\muxid[1:0] + end + attribute \src "libresoc.v:154738.14-154738.38" + process $proc$libresoc.v:154738$8885 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "libresoc.v:154745.7-154745.18" + process $proc$libresoc.v:154745$8886 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "libresoc.v:154759.7-154759.20" + process $proc$libresoc.v:154759$8887 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:154783.14-154783.38" + process $proc$libresoc.v:154783$8888 + assign { } { } + assign $1\sr_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \sr_op__fn_unit $1\sr_op__fn_unit[11:0] + end + attribute \src "libresoc.v:154818.14-154818.58" + process $proc$libresoc.v:154818$8889 + assign { } { } + assign $1\sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \sr_op__imm_data__data $1\sr_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:154827.7-154827.33" + process $proc$libresoc.v:154827$8890 + assign { } { } + assign $1\sr_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \sr_op__imm_data__ok $1\sr_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:154840.13-154840.38" + process $proc$libresoc.v:154840$8891 + assign { } { } + assign $1\sr_op__input_carry[1:0] 2'00 + sync always + sync init + update \sr_op__input_carry $1\sr_op__input_carry[1:0] + end + attribute \src "libresoc.v:154857.7-154857.29" + process $proc$libresoc.v:154857$8892 + assign { } { } + assign $1\sr_op__input_cr[0:0] 1'0 + sync always + sync init + update \sr_op__input_cr $1\sr_op__input_cr[0:0] + end + attribute \src "libresoc.v:154866.14-154866.33" + process $proc$libresoc.v:154866$8893 + assign { } { } + assign $1\sr_op__insn[31:0] 0 + sync always + sync init + update \sr_op__insn $1\sr_op__insn[31:0] + end + attribute \src "libresoc.v:154949.13-154949.37" + process $proc$libresoc.v:154949$8894 + assign { } { } + assign $1\sr_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \sr_op__insn_type $1\sr_op__insn_type[6:0] + end + attribute \src "libresoc.v:155106.7-155106.30" + process $proc$libresoc.v:155106$8895 + assign { } { } + assign $1\sr_op__invert_in[0:0] 1'0 + sync always + sync init + update \sr_op__invert_in $1\sr_op__invert_in[0:0] + end + attribute \src "libresoc.v:155115.7-155115.29" + process $proc$libresoc.v:155115$8896 + assign { } { } + assign $1\sr_op__is_32bit[0:0] 1'0 + sync always + sync init + update \sr_op__is_32bit $1\sr_op__is_32bit[0:0] + end + attribute \src "libresoc.v:155124.7-155124.30" + process $proc$libresoc.v:155124$8897 + assign { } { } + assign $1\sr_op__is_signed[0:0] 1'0 + sync always + sync init + update \sr_op__is_signed $1\sr_op__is_signed[0:0] + end + attribute \src "libresoc.v:155133.7-155133.27" + process $proc$libresoc.v:155133$8898 + assign { } { } + assign $1\sr_op__oe__oe[0:0] 1'0 + sync always + sync init + update \sr_op__oe__oe $1\sr_op__oe__oe[0:0] + end + attribute \src "libresoc.v:155142.7-155142.27" + process $proc$libresoc.v:155142$8899 + assign { } { } + assign $1\sr_op__oe__ok[0:0] 1'0 + sync always + sync init + update \sr_op__oe__ok $1\sr_op__oe__ok[0:0] + end + attribute \src "libresoc.v:155151.7-155151.33" + process $proc$libresoc.v:155151$8900 + assign { } { } + assign $1\sr_op__output_carry[0:0] 1'0 + sync always + sync init + update \sr_op__output_carry $1\sr_op__output_carry[0:0] + end + attribute \src "libresoc.v:155160.7-155160.30" + process $proc$libresoc.v:155160$8901 + assign { } { } + assign $1\sr_op__output_cr[0:0] 1'0 + sync always + sync init + update \sr_op__output_cr $1\sr_op__output_cr[0:0] + end + attribute \src "libresoc.v:155169.7-155169.27" + process $proc$libresoc.v:155169$8902 + assign { } { } + assign $1\sr_op__rc__ok[0:0] 1'0 + sync always + sync init + update \sr_op__rc__ok $1\sr_op__rc__ok[0:0] + end + attribute \src "libresoc.v:155178.7-155178.27" + process $proc$libresoc.v:155178$8903 + assign { } { } + assign $1\sr_op__rc__rc[0:0] 1'0 + sync always + sync init + update \sr_op__rc__rc $1\sr_op__rc__rc[0:0] + end + attribute \src "libresoc.v:155187.7-155187.30" + process $proc$libresoc.v:155187$8904 + assign { } { } + assign $1\sr_op__write_cr0[0:0] 1'0 + sync always + sync init + update \sr_op__write_cr0 $1\sr_op__write_cr0[0:0] + end + attribute \src "libresoc.v:155196.13-155196.26" + process $proc$libresoc.v:155196$8905 + assign { } { } + assign $1\xer_ca[1:0] 2'00 + sync always + sync init + update \xer_ca $1\xer_ca[1:0] + end + attribute \src "libresoc.v:155207.7-155207.23" + process $proc$libresoc.v:155207$8906 + assign { } { } + assign $1\xer_ca_ok[0:0] 1'0 + sync always + sync init + update \xer_ca_ok $1\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:155216.7-155216.20" + process $proc$libresoc.v:155216$8907 + assign { } { } + assign $1\xer_so[0:0] 1'0 + sync always + sync init + update \xer_so $1\xer_so[0:0] + end + attribute \src "libresoc.v:155225.7-155225.23" + process $proc$libresoc.v:155225$8908 + assign { } { } + assign $1\xer_so_ok[0:0] 1'0 + sync always + sync init + update \xer_so_ok $1\xer_so_ok[0:0] + end + attribute \src "libresoc.v:155233.3-155234.29" + process $proc$libresoc.v:155233$8782 + assign { } { } + assign $0\xer_ca[1:0] \xer_ca$next + sync posedge \coresync_clk + update \xer_ca $0\xer_ca[1:0] + end + attribute \src "libresoc.v:155235.3-155236.35" + process $proc$libresoc.v:155235$8783 + assign { } { } + assign $0\xer_ca_ok[0:0] \xer_ca_ok$next + sync posedge \coresync_clk + update \xer_ca_ok $0\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:155237.3-155238.29" + process $proc$libresoc.v:155237$8784 + assign { } { } + assign $0\xer_so[0:0] \xer_so$next + sync posedge \coresync_clk + update \xer_so $0\xer_so[0:0] + end + attribute \src "libresoc.v:155239.3-155240.35" + process $proc$libresoc.v:155239$8785 + assign { } { } + assign $0\xer_so_ok[0:0] \xer_so_ok$next + sync posedge \coresync_clk + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:155241.3-155242.25" + process $proc$libresoc.v:155241$8786 + assign { } { } + assign $0\cr_a[3:0] \cr_a$next + sync posedge \coresync_clk + update \cr_a $0\cr_a[3:0] + end + attribute \src "libresoc.v:155243.3-155244.31" + process $proc$libresoc.v:155243$8787 + assign { } { } + assign $0\cr_a_ok[0:0] \cr_a_ok$next + sync posedge \coresync_clk + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "libresoc.v:155245.3-155246.19" + process $proc$libresoc.v:155245$8788 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] + end + attribute \src "libresoc.v:155247.3-155248.25" + process $proc$libresoc.v:155247$8789 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:155249.3-155250.49" + process $proc$libresoc.v:155249$8790 + assign { } { } + assign $0\sr_op__insn_type[6:0] \sr_op__insn_type$next + sync posedge \coresync_clk + update \sr_op__insn_type $0\sr_op__insn_type[6:0] + end + attribute \src "libresoc.v:155251.3-155252.45" + process $proc$libresoc.v:155251$8791 + assign { } { } + assign $0\sr_op__fn_unit[11:0] \sr_op__fn_unit$next + sync posedge \coresync_clk + update \sr_op__fn_unit $0\sr_op__fn_unit[11:0] + end + attribute \src "libresoc.v:155253.3-155254.59" + process $proc$libresoc.v:155253$8792 + assign { } { } + assign $0\sr_op__imm_data__data[63:0] \sr_op__imm_data__data$next + sync posedge \coresync_clk + update \sr_op__imm_data__data $0\sr_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:155255.3-155256.55" + process $proc$libresoc.v:155255$8793 + assign { } { } + assign $0\sr_op__imm_data__ok[0:0] \sr_op__imm_data__ok$next + sync posedge \coresync_clk + update \sr_op__imm_data__ok $0\sr_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:155257.3-155258.43" + process $proc$libresoc.v:155257$8794 + assign { } { } + assign $0\sr_op__rc__rc[0:0] \sr_op__rc__rc$next + sync posedge \coresync_clk + update \sr_op__rc__rc $0\sr_op__rc__rc[0:0] + end + attribute \src "libresoc.v:155259.3-155260.43" + process $proc$libresoc.v:155259$8795 + assign { } { } + assign $0\sr_op__rc__ok[0:0] \sr_op__rc__ok$next + sync posedge \coresync_clk + update \sr_op__rc__ok $0\sr_op__rc__ok[0:0] + end + attribute \src "libresoc.v:155261.3-155262.43" + process $proc$libresoc.v:155261$8796 + assign { } { } + assign $0\sr_op__oe__oe[0:0] \sr_op__oe__oe$next + sync posedge \coresync_clk + update \sr_op__oe__oe $0\sr_op__oe__oe[0:0] + end + attribute \src "libresoc.v:155263.3-155264.43" + process $proc$libresoc.v:155263$8797 + assign { } { } + assign $0\sr_op__oe__ok[0:0] \sr_op__oe__ok$next + sync posedge \coresync_clk + update \sr_op__oe__ok $0\sr_op__oe__ok[0:0] + end + attribute \src "libresoc.v:155265.3-155266.49" + process $proc$libresoc.v:155265$8798 + assign { } { } + assign $0\sr_op__write_cr0[0:0] \sr_op__write_cr0$next + sync posedge \coresync_clk + update \sr_op__write_cr0 $0\sr_op__write_cr0[0:0] + end + attribute \src "libresoc.v:155267.3-155268.49" + process $proc$libresoc.v:155267$8799 + assign { } { } + assign $0\sr_op__invert_in[0:0] \sr_op__invert_in$next + sync posedge \coresync_clk + update \sr_op__invert_in $0\sr_op__invert_in[0:0] + end + attribute \src "libresoc.v:155269.3-155270.53" + process $proc$libresoc.v:155269$8800 + assign { } { } + assign $0\sr_op__input_carry[1:0] \sr_op__input_carry$next + sync posedge \coresync_clk + update \sr_op__input_carry $0\sr_op__input_carry[1:0] + end + attribute \src "libresoc.v:155271.3-155272.55" + process $proc$libresoc.v:155271$8801 + assign { } { } + assign $0\sr_op__output_carry[0:0] \sr_op__output_carry$next + sync posedge \coresync_clk + update \sr_op__output_carry $0\sr_op__output_carry[0:0] + end + attribute \src "libresoc.v:155273.3-155274.47" + process $proc$libresoc.v:155273$8802 + assign { } { } + assign $0\sr_op__input_cr[0:0] \sr_op__input_cr$next + sync posedge \coresync_clk + update \sr_op__input_cr $0\sr_op__input_cr[0:0] + end + attribute \src "libresoc.v:155275.3-155276.49" + process $proc$libresoc.v:155275$8803 + assign { } { } + assign $0\sr_op__output_cr[0:0] \sr_op__output_cr$next + sync posedge \coresync_clk + update \sr_op__output_cr $0\sr_op__output_cr[0:0] + end + attribute \src "libresoc.v:155277.3-155278.47" + process $proc$libresoc.v:155277$8804 + assign { } { } + assign $0\sr_op__is_32bit[0:0] \sr_op__is_32bit$next + sync posedge \coresync_clk + update \sr_op__is_32bit $0\sr_op__is_32bit[0:0] + end + attribute \src "libresoc.v:155279.3-155280.49" + process $proc$libresoc.v:155279$8805 + assign { } { } + assign $0\sr_op__is_signed[0:0] \sr_op__is_signed$next + sync posedge \coresync_clk + update \sr_op__is_signed $0\sr_op__is_signed[0:0] + end + attribute \src "libresoc.v:155281.3-155282.39" + process $proc$libresoc.v:155281$8806 + assign { } { } + assign $0\sr_op__insn[31:0] \sr_op__insn$next + sync posedge \coresync_clk + update \sr_op__insn $0\sr_op__insn[31:0] + end + attribute \src "libresoc.v:155283.3-155284.27" + process $proc$libresoc.v:155283$8807 + assign { } { } + assign $0\muxid[1:0] \muxid$next + sync posedge \coresync_clk + update \muxid $0\muxid[1:0] + end + attribute \src "libresoc.v:155285.3-155286.29" + process $proc$libresoc.v:155285$8808 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:155389.3-155407.6" + process $proc$libresoc.v:155389$8809 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ca$next[1:0]$8811 $1\xer_ca$next[1:0]$8813 + assign $0\xer_ca_ok$next[0:0]$8810 $2\xer_ca_ok$next[0:0]$8814 + attribute \src "libresoc.v:155390.5-155390.29" + switch \initial + attribute \src "libresoc.v:155390.9-155390.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$8812 $1\xer_ca$next[1:0]$8813 } { \xer_ca_ok$95 \xer_ca$94 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$8812 $1\xer_ca$next[1:0]$8813 } { \xer_ca_ok$95 \xer_ca$94 } + case + assign $1\xer_ca_ok$next[0:0]$8812 \xer_ca_ok + assign $1\xer_ca$next[1:0]$8813 \xer_ca + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ca_ok$next[0:0]$8814 1'0 + case + assign $2\xer_ca_ok$next[0:0]$8814 $1\xer_ca_ok$next[0:0]$8812 + end + sync always + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8810 + update \xer_ca$next $0\xer_ca$next[1:0]$8811 + end + attribute \src "libresoc.v:155408.3-155425.6" + process $proc$libresoc.v:155408$8815 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$8816 $2\r_busy$next[0:0]$8818 + attribute \src "libresoc.v:155409.5-155409.29" + switch \initial + attribute \src "libresoc.v:155409.9-155409.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$8817 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$8817 1'0 + case + assign $1\r_busy$next[0:0]$8817 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$8818 1'0 + case + assign $2\r_busy$next[0:0]$8818 $1\r_busy$next[0:0]$8817 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$8816 + end + attribute \src "libresoc.v:155426.3-155438.6" + process $proc$libresoc.v:155426$8819 + assign { } { } + assign { } { } + assign $0\muxid$next[1:0]$8820 $1\muxid$next[1:0]$8821 + attribute \src "libresoc.v:155427.5-155427.29" + switch \initial + attribute \src "libresoc.v:155427.9-155427.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$next[1:0]$8821 \muxid$67 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$next[1:0]$8821 \muxid$67 + case + assign $1\muxid$next[1:0]$8821 \muxid + end + sync always + update \muxid$next $0\muxid$next[1:0]$8820 + end + attribute \src "libresoc.v:155439.3-155479.6" + process $proc$libresoc.v:155439$8822 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sr_op__fn_unit$next[11:0]$8823 $1\sr_op__fn_unit$next[11:0]$8840 + assign { } { } + assign { } { } + assign $0\sr_op__input_carry$next[1:0]$8826 $1\sr_op__input_carry$next[1:0]$8843 + assign $0\sr_op__input_cr$next[0:0]$8827 $1\sr_op__input_cr$next[0:0]$8844 + assign $0\sr_op__insn$next[31:0]$8828 $1\sr_op__insn$next[31:0]$8845 + assign $0\sr_op__insn_type$next[6:0]$8829 $1\sr_op__insn_type$next[6:0]$8846 + assign $0\sr_op__invert_in$next[0:0]$8830 $1\sr_op__invert_in$next[0:0]$8847 + assign $0\sr_op__is_32bit$next[0:0]$8831 $1\sr_op__is_32bit$next[0:0]$8848 + assign $0\sr_op__is_signed$next[0:0]$8832 $1\sr_op__is_signed$next[0:0]$8849 + assign { } { } + assign { } { } + assign $0\sr_op__output_carry$next[0:0]$8835 $1\sr_op__output_carry$next[0:0]$8852 + assign $0\sr_op__output_cr$next[0:0]$8836 $1\sr_op__output_cr$next[0:0]$8853 + assign { } { } + assign { } { } + assign $0\sr_op__write_cr0$next[0:0]$8839 $1\sr_op__write_cr0$next[0:0]$8856 + assign $0\sr_op__imm_data__data$next[63:0]$8824 $2\sr_op__imm_data__data$next[63:0]$8857 + assign $0\sr_op__imm_data__ok$next[0:0]$8825 $2\sr_op__imm_data__ok$next[0:0]$8858 + assign $0\sr_op__oe__oe$next[0:0]$8833 $2\sr_op__oe__oe$next[0:0]$8859 + assign $0\sr_op__oe__ok$next[0:0]$8834 $2\sr_op__oe__ok$next[0:0]$8860 + assign $0\sr_op__rc__ok$next[0:0]$8837 $2\sr_op__rc__ok$next[0:0]$8861 + assign $0\sr_op__rc__rc$next[0:0]$8838 $2\sr_op__rc__rc$next[0:0]$8862 + attribute \src "libresoc.v:155440.5-155440.29" + switch \initial + attribute \src "libresoc.v:155440.9-155440.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\sr_op__insn$next[31:0]$8845 $1\sr_op__is_signed$next[0:0]$8849 $1\sr_op__is_32bit$next[0:0]$8848 $1\sr_op__output_cr$next[0:0]$8853 $1\sr_op__input_cr$next[0:0]$8844 $1\sr_op__output_carry$next[0:0]$8852 $1\sr_op__input_carry$next[1:0]$8843 $1\sr_op__invert_in$next[0:0]$8847 $1\sr_op__write_cr0$next[0:0]$8856 $1\sr_op__oe__ok$next[0:0]$8851 $1\sr_op__oe__oe$next[0:0]$8850 $1\sr_op__rc__ok$next[0:0]$8854 $1\sr_op__rc__rc$next[0:0]$8855 $1\sr_op__imm_data__ok$next[0:0]$8842 $1\sr_op__imm_data__data$next[63:0]$8841 $1\sr_op__fn_unit$next[11:0]$8840 $1\sr_op__insn_type$next[6:0]$8846 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\sr_op__insn$next[31:0]$8845 $1\sr_op__is_signed$next[0:0]$8849 $1\sr_op__is_32bit$next[0:0]$8848 $1\sr_op__output_cr$next[0:0]$8853 $1\sr_op__input_cr$next[0:0]$8844 $1\sr_op__output_carry$next[0:0]$8852 $1\sr_op__input_carry$next[1:0]$8843 $1\sr_op__invert_in$next[0:0]$8847 $1\sr_op__write_cr0$next[0:0]$8856 $1\sr_op__oe__ok$next[0:0]$8851 $1\sr_op__oe__oe$next[0:0]$8850 $1\sr_op__rc__ok$next[0:0]$8854 $1\sr_op__rc__rc$next[0:0]$8855 $1\sr_op__imm_data__ok$next[0:0]$8842 $1\sr_op__imm_data__data$next[63:0]$8841 $1\sr_op__fn_unit$next[11:0]$8840 $1\sr_op__insn_type$next[6:0]$8846 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } + case + assign $1\sr_op__fn_unit$next[11:0]$8840 \sr_op__fn_unit + assign $1\sr_op__imm_data__data$next[63:0]$8841 \sr_op__imm_data__data + assign $1\sr_op__imm_data__ok$next[0:0]$8842 \sr_op__imm_data__ok + assign $1\sr_op__input_carry$next[1:0]$8843 \sr_op__input_carry + assign $1\sr_op__input_cr$next[0:0]$8844 \sr_op__input_cr + assign $1\sr_op__insn$next[31:0]$8845 \sr_op__insn + assign $1\sr_op__insn_type$next[6:0]$8846 \sr_op__insn_type + assign $1\sr_op__invert_in$next[0:0]$8847 \sr_op__invert_in + assign $1\sr_op__is_32bit$next[0:0]$8848 \sr_op__is_32bit + assign $1\sr_op__is_signed$next[0:0]$8849 \sr_op__is_signed + assign $1\sr_op__oe__oe$next[0:0]$8850 \sr_op__oe__oe + assign $1\sr_op__oe__ok$next[0:0]$8851 \sr_op__oe__ok + assign $1\sr_op__output_carry$next[0:0]$8852 \sr_op__output_carry + assign $1\sr_op__output_cr$next[0:0]$8853 \sr_op__output_cr + assign $1\sr_op__rc__ok$next[0:0]$8854 \sr_op__rc__ok + assign $1\sr_op__rc__rc$next[0:0]$8855 \sr_op__rc__rc + assign $1\sr_op__write_cr0$next[0:0]$8856 \sr_op__write_cr0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\sr_op__imm_data__data$next[63:0]$8857 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sr_op__imm_data__ok$next[0:0]$8858 1'0 + assign $2\sr_op__rc__rc$next[0:0]$8862 1'0 + assign $2\sr_op__rc__ok$next[0:0]$8861 1'0 + assign $2\sr_op__oe__oe$next[0:0]$8859 1'0 + assign $2\sr_op__oe__ok$next[0:0]$8860 1'0 + case + assign $2\sr_op__imm_data__data$next[63:0]$8857 $1\sr_op__imm_data__data$next[63:0]$8841 + assign $2\sr_op__imm_data__ok$next[0:0]$8858 $1\sr_op__imm_data__ok$next[0:0]$8842 + assign $2\sr_op__oe__oe$next[0:0]$8859 $1\sr_op__oe__oe$next[0:0]$8850 + assign $2\sr_op__oe__ok$next[0:0]$8860 $1\sr_op__oe__ok$next[0:0]$8851 + assign $2\sr_op__rc__ok$next[0:0]$8861 $1\sr_op__rc__ok$next[0:0]$8854 + assign $2\sr_op__rc__rc$next[0:0]$8862 $1\sr_op__rc__rc$next[0:0]$8855 + end + sync always + update \sr_op__fn_unit$next $0\sr_op__fn_unit$next[11:0]$8823 + update \sr_op__imm_data__data$next $0\sr_op__imm_data__data$next[63:0]$8824 + update \sr_op__imm_data__ok$next $0\sr_op__imm_data__ok$next[0:0]$8825 + update \sr_op__input_carry$next $0\sr_op__input_carry$next[1:0]$8826 + update \sr_op__input_cr$next $0\sr_op__input_cr$next[0:0]$8827 + update \sr_op__insn$next $0\sr_op__insn$next[31:0]$8828 + update \sr_op__insn_type$next $0\sr_op__insn_type$next[6:0]$8829 + update \sr_op__invert_in$next $0\sr_op__invert_in$next[0:0]$8830 + update \sr_op__is_32bit$next $0\sr_op__is_32bit$next[0:0]$8831 + update \sr_op__is_signed$next $0\sr_op__is_signed$next[0:0]$8832 + update \sr_op__oe__oe$next $0\sr_op__oe__oe$next[0:0]$8833 + update \sr_op__oe__ok$next $0\sr_op__oe__ok$next[0:0]$8834 + update \sr_op__output_carry$next $0\sr_op__output_carry$next[0:0]$8835 + update \sr_op__output_cr$next $0\sr_op__output_cr$next[0:0]$8836 + update \sr_op__rc__ok$next $0\sr_op__rc__ok$next[0:0]$8837 + update \sr_op__rc__rc$next $0\sr_op__rc__rc$next[0:0]$8838 + update \sr_op__write_cr0$next $0\sr_op__write_cr0$next[0:0]$8839 + end + attribute \src "libresoc.v:155480.3-155498.6" + process $proc$libresoc.v:155480$8863 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$8864 $1\o$next[63:0]$8866 + assign { } { } + assign $0\o_ok$next[0:0]$8865 $2\o_ok$next[0:0]$8868 + attribute \src "libresoc.v:155481.5-155481.29" + switch \initial + attribute \src "libresoc.v:155481.9-155481.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8867 $1\o$next[63:0]$8866 } { \o_ok$86 \o$85 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8867 $1\o$next[63:0]$8866 } { \o_ok$86 \o$85 } + case + assign $1\o$next[63:0]$8866 \o + assign $1\o_ok$next[0:0]$8867 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$8868 1'0 + case + assign $2\o_ok$next[0:0]$8868 $1\o_ok$next[0:0]$8867 + end + sync always + update \o$next $0\o$next[63:0]$8864 + update \o_ok$next $0\o_ok$next[0:0]$8865 + end + attribute \src "libresoc.v:155499.3-155517.6" + process $proc$libresoc.v:155499$8869 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$next[3:0]$8870 $1\cr_a$next[3:0]$8872 + assign { } { } + assign $0\cr_a_ok$next[0:0]$8871 $2\cr_a_ok$next[0:0]$8874 + attribute \src "libresoc.v:155500.5-155500.29" + switch \initial + attribute \src "libresoc.v:155500.9-155500.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$8873 $1\cr_a$next[3:0]$8872 } { \cr_a_ok$88 \cr_a$87 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$8873 $1\cr_a$next[3:0]$8872 } { \cr_a_ok$88 \cr_a$87 } + case + assign $1\cr_a$next[3:0]$8872 \cr_a + assign $1\cr_a_ok$next[0:0]$8873 \cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$next[0:0]$8874 1'0 + case + assign $2\cr_a_ok$next[0:0]$8874 $1\cr_a_ok$next[0:0]$8873 + end + sync always + update \cr_a$next $0\cr_a$next[3:0]$8870 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8871 + end + attribute \src "libresoc.v:155518.3-155536.6" + process $proc$libresoc.v:155518$8875 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$next[0:0]$8876 $1\xer_so$next[0:0]$8878 + assign { } { } + assign $0\xer_so_ok$next[0:0]$8877 $2\xer_so_ok$next[0:0]$8880 + attribute \src "libresoc.v:155519.5-155519.29" + switch \initial + attribute \src "libresoc.v:155519.9-155519.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$8879 $1\xer_so$next[0:0]$8878 } { \xer_so_ok$92 \xer_so$91 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$8879 $1\xer_so$next[0:0]$8878 } { \xer_so_ok$92 \xer_so$91 } + case + assign $1\xer_so$next[0:0]$8878 \xer_so + assign $1\xer_so_ok$next[0:0]$8879 \xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$next[0:0]$8880 1'0 + case + assign $2\xer_so_ok$next[0:0]$8880 $1\xer_so_ok$next[0:0]$8879 + end + sync always + update \xer_so$next $0\xer_so$next[0:0]$8876 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8877 + end + connect \$65 $and$libresoc.v:155232$8781_Y + connect \cr_a$89 4'0000 + connect \cr_a_ok$90 1'0 + connect \xer_so_ok$93 1'0 + connect \xer_ca_ok$96 1'0 + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_ca_ok$95 \xer_ca$94 } { 1'0 \main_xer_ca } + connect { \xer_so_ok$92 \xer_so$91 } { 1'0 \main_xer_so$62 } + connect { \cr_a_ok$88 \cr_a$87 } 5'00000 + connect { \o_ok$86 \o$85 } { \main_o_ok \main_o } + connect { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } { \main_sr_op__insn$61 \main_sr_op__is_signed$60 \main_sr_op__is_32bit$59 \main_sr_op__output_cr$58 \main_sr_op__input_cr$57 \main_sr_op__output_carry$56 \main_sr_op__input_carry$55 \main_sr_op__invert_in$54 \main_sr_op__write_cr0$53 \main_sr_op__oe__ok$52 \main_sr_op__oe__oe$51 \main_sr_op__rc__ok$50 \main_sr_op__rc__rc$49 \main_sr_op__imm_data__ok$48 \main_sr_op__imm_data__data$47 \main_sr_op__fn_unit$46 \main_sr_op__insn_type$45 } + connect \muxid$67 \main_muxid$44 + connect \p_valid_i_p_ready_o \$65 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$64 \p_valid_i + connect \xer_ca$63 \input_xer_ca$43 + connect \main_xer_so \input_xer_so$42 + connect \main_rc \input_rc$41 + connect \main_rb \input_rb$40 + connect \main_ra \input_ra$39 + connect { \main_sr_op__insn \main_sr_op__is_signed \main_sr_op__is_32bit \main_sr_op__output_cr \main_sr_op__input_cr \main_sr_op__output_carry \main_sr_op__input_carry \main_sr_op__invert_in \main_sr_op__write_cr0 \main_sr_op__oe__ok \main_sr_op__oe__oe \main_sr_op__rc__ok \main_sr_op__rc__rc \main_sr_op__imm_data__ok \main_sr_op__imm_data__data \main_sr_op__fn_unit \main_sr_op__insn_type } { \input_sr_op__insn$38 \input_sr_op__is_signed$37 \input_sr_op__is_32bit$36 \input_sr_op__output_cr$35 \input_sr_op__input_cr$34 \input_sr_op__output_carry$33 \input_sr_op__input_carry$32 \input_sr_op__invert_in$31 \input_sr_op__write_cr0$30 \input_sr_op__oe__ok$29 \input_sr_op__oe__oe$28 \input_sr_op__rc__ok$27 \input_sr_op__rc__rc$26 \input_sr_op__imm_data__ok$25 \input_sr_op__imm_data__data$24 \input_sr_op__fn_unit$23 \input_sr_op__insn_type$22 } + connect \main_muxid \input_muxid$21 + connect \input_xer_ca \xer_ca$20 + connect \input_xer_so \xer_so$19 + connect \input_rc \rc + connect \input_rb \rb + connect \input_ra \ra + connect { \input_sr_op__insn \input_sr_op__is_signed \input_sr_op__is_32bit \input_sr_op__output_cr \input_sr_op__input_cr \input_sr_op__output_carry \input_sr_op__input_carry \input_sr_op__invert_in \input_sr_op__write_cr0 \input_sr_op__oe__ok \input_sr_op__oe__oe \input_sr_op__rc__ok \input_sr_op__rc__rc \input_sr_op__imm_data__ok \input_sr_op__imm_data__data \input_sr_op__fn_unit \input_sr_op__insn_type } { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } + connect \input_muxid \muxid$1 +end +attribute \src "libresoc.v:155570.1-156403.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1" +attribute \generator "nMigen" +module \pipe1$32 + attribute \src "libresoc.v:156360.3-156372.6" + wire width 64 $0\fast1$next[63:0]$8958 + attribute \src "libresoc.v:156234.3-156235.27" + wire width 64 $0\fast1[63:0] + attribute \src "libresoc.v:156373.3-156385.6" + wire width 64 $0\fast2$next[63:0]$8961 + attribute \src "libresoc.v:156232.3-156233.27" + wire width 64 $0\fast2[63:0] + attribute \src "libresoc.v:155571.7-155571.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:156300.3-156312.6" + wire width 2 $0\muxid$next[1:0]$8930 + attribute \src "libresoc.v:156228.3-156229.27" + wire width 2 $0\muxid[1:0] + attribute \src "libresoc.v:156282.3-156299.6" + wire $0\r_busy$next[0:0]$8926 + attribute \src "libresoc.v:156230.3-156231.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:156334.3-156346.6" + wire width 64 $0\ra$next[63:0]$8952 + attribute \src "libresoc.v:156238.3-156239.21" + wire width 64 $0\ra[63:0] + attribute \src "libresoc.v:156347.3-156359.6" + wire width 64 $0\rb$next[63:0]$8955 + attribute \src "libresoc.v:156236.3-156237.21" + wire width 64 $0\rb[63:0] + attribute \src "libresoc.v:156313.3-156333.6" + wire width 64 $0\trap_op__cia$next[63:0]$8933 + attribute \src "libresoc.v:156218.3-156219.41" + wire width 64 $0\trap_op__cia[63:0] + attribute \src "libresoc.v:156313.3-156333.6" + wire width 12 $0\trap_op__fn_unit$next[11:0]$8934 + attribute \src "libresoc.v:156242.3-156243.49" + wire width 12 $0\trap_op__fn_unit[11:0] + attribute \src "libresoc.v:156313.3-156333.6" + wire width 32 $0\trap_op__insn$next[31:0]$8935 + attribute \src "libresoc.v:156214.3-156215.43" + wire width 32 $0\trap_op__insn[31:0] + attribute \src "libresoc.v:156313.3-156333.6" + wire width 7 $0\trap_op__insn_type$next[6:0]$8936 + attribute \src "libresoc.v:156240.3-156241.53" + wire width 7 $0\trap_op__insn_type[6:0] + attribute \src "libresoc.v:156313.3-156333.6" + wire $0\trap_op__is_32bit$next[0:0]$8937 + attribute \src "libresoc.v:156220.3-156221.51" + wire $0\trap_op__is_32bit[0:0] + attribute \src "libresoc.v:156313.3-156333.6" + wire width 8 $0\trap_op__ldst_exc$next[7:0]$8938 + attribute \src "libresoc.v:156226.3-156227.51" + wire width 8 $0\trap_op__ldst_exc[7:0] + attribute \src "libresoc.v:156313.3-156333.6" + wire width 64 $0\trap_op__msr$next[63:0]$8939 + attribute \src "libresoc.v:156216.3-156217.41" + wire width 64 $0\trap_op__msr[63:0] + attribute \src "libresoc.v:156313.3-156333.6" + wire width 13 $0\trap_op__trapaddr$next[12:0]$8940 + attribute \src "libresoc.v:156224.3-156225.51" + wire width 13 $0\trap_op__trapaddr[12:0] + attribute \src "libresoc.v:156313.3-156333.6" + wire width 8 $0\trap_op__traptype$next[7:0]$8941 + attribute \src "libresoc.v:156222.3-156223.51" + wire width 8 $0\trap_op__traptype[7:0] + attribute \src "libresoc.v:156360.3-156372.6" + wire width 64 $1\fast1$next[63:0]$8959 + attribute \src "libresoc.v:155810.14-155810.42" + wire width 64 $1\fast1[63:0] + attribute \src "libresoc.v:156373.3-156385.6" + wire width 64 $1\fast2$next[63:0]$8962 + attribute \src "libresoc.v:155819.14-155819.42" + wire width 64 $1\fast2[63:0] + attribute \src "libresoc.v:156300.3-156312.6" + wire width 2 $1\muxid$next[1:0]$8931 + attribute \src "libresoc.v:155828.13-155828.25" + wire width 2 $1\muxid[1:0] + attribute \src "libresoc.v:156282.3-156299.6" + wire $1\r_busy$next[0:0]$8927 + attribute \src "libresoc.v:155850.7-155850.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:156334.3-156346.6" + wire width 64 $1\ra$next[63:0]$8953 + attribute \src "libresoc.v:155855.14-155855.39" + wire width 64 $1\ra[63:0] + attribute \src "libresoc.v:156347.3-156359.6" + wire width 64 $1\rb$next[63:0]$8956 + attribute \src "libresoc.v:155864.14-155864.39" + wire width 64 $1\rb[63:0] + attribute \src "libresoc.v:156313.3-156333.6" + wire width 64 $1\trap_op__cia$next[63:0]$8942 + attribute \src "libresoc.v:155873.14-155873.49" + wire width 64 $1\trap_op__cia[63:0] + attribute \src "libresoc.v:156313.3-156333.6" + wire width 12 $1\trap_op__fn_unit$next[11:0]$8943 + attribute \src "libresoc.v:155895.14-155895.40" + wire width 12 $1\trap_op__fn_unit[11:0] + attribute \src "libresoc.v:156313.3-156333.6" + wire width 32 $1\trap_op__insn$next[31:0]$8944 + attribute \src "libresoc.v:155930.14-155930.35" + wire width 32 $1\trap_op__insn[31:0] + attribute \src "libresoc.v:156313.3-156333.6" + wire width 7 $1\trap_op__insn_type$next[6:0]$8945 + attribute \src "libresoc.v:156013.13-156013.39" + wire width 7 $1\trap_op__insn_type[6:0] + attribute \src "libresoc.v:156313.3-156333.6" + wire $1\trap_op__is_32bit$next[0:0]$8946 + attribute \src "libresoc.v:156170.7-156170.31" + wire $1\trap_op__is_32bit[0:0] + attribute \src "libresoc.v:156313.3-156333.6" + wire width 8 $1\trap_op__ldst_exc$next[7:0]$8947 + attribute \src "libresoc.v:156179.13-156179.38" + wire width 8 $1\trap_op__ldst_exc[7:0] + attribute \src "libresoc.v:156313.3-156333.6" + wire width 64 $1\trap_op__msr$next[63:0]$8948 + attribute \src "libresoc.v:156188.14-156188.49" + wire width 64 $1\trap_op__msr[63:0] + attribute \src "libresoc.v:156313.3-156333.6" + wire width 13 $1\trap_op__trapaddr$next[12:0]$8949 + attribute \src "libresoc.v:156197.14-156197.42" + wire width 13 $1\trap_op__trapaddr[12:0] + attribute \src "libresoc.v:156313.3-156333.6" + wire width 8 $1\trap_op__traptype$next[7:0]$8950 + attribute \src "libresoc.v:156206.13-156206.38" + wire width 8 $1\trap_op__traptype[7:0] + attribute \src "libresoc.v:156282.3-156299.6" + wire $2\r_busy$next[0:0]$8928 + attribute \src "libresoc.v:156213.18-156213.118" + wire $and$libresoc.v:156213$8909_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 34 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_fast1$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_fast2$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \dummy_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \dummy_muxid$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_ra$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_rb$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \dummy_trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \dummy_trap_op__cia$20 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \dummy_trap_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \dummy_trap_op__fn_unit$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dummy_trap_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dummy_trap_op__insn$18 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \dummy_trap_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \dummy_trap_op__insn_type$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dummy_trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dummy_trap_op__is_32bit$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \dummy_trap_op__ldst_exc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \dummy_trap_op__ldst_exc$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \dummy_trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \dummy_trap_op__msr$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \dummy_trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \dummy_trap_op__trapaddr$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \dummy_trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \dummy_trap_op__traptype$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 16 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 32 \fast1$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \fast1$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \fast1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 17 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 33 \fast2$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \fast2$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \fast2$next + attribute \src "libresoc.v:155571.7-155571.15" + wire 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attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute 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attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute 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\src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 output 13 \trap_op__ldst_exc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 29 \trap_op__ldst_exc$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \trap_op__ldst_exc$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \trap_op__ldst_exc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 8 \trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__msr$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 24 \trap_op__msr$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__msr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 12 \trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \trap_op__trapaddr$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 28 \trap_op__trapaddr$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \trap_op__trapaddr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 output 11 \trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \trap_op__traptype$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 27 \trap_op__traptype$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \trap_op__traptype$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$libresoc.v:156213$8909 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$29 + connect \B \p_ready_o + connect \Y $and$libresoc.v:156213$8909_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:156244.9-156273.4" + cell \dummy \dummy + connect \fast1 \dummy_fast1 + connect \fast1$13 \dummy_fast1$27 + connect \fast2 \dummy_fast2 + connect \fast2$14 \dummy_fast2$28 + connect \muxid \dummy_muxid + connect \muxid$1 \dummy_muxid$15 + connect \ra \dummy_ra + connect \ra$11 \dummy_ra$25 + connect \rb \dummy_rb + connect \rb$12 \dummy_rb$26 + connect \trap_op__cia \dummy_trap_op__cia + connect \trap_op__cia$6 \dummy_trap_op__cia$20 + connect \trap_op__fn_unit \dummy_trap_op__fn_unit + connect \trap_op__fn_unit$3 \dummy_trap_op__fn_unit$17 + connect \trap_op__insn \dummy_trap_op__insn + connect \trap_op__insn$4 \dummy_trap_op__insn$18 + connect \trap_op__insn_type \dummy_trap_op__insn_type + connect \trap_op__insn_type$2 \dummy_trap_op__insn_type$16 + connect \trap_op__is_32bit \dummy_trap_op__is_32bit + connect \trap_op__is_32bit$7 \dummy_trap_op__is_32bit$21 + connect \trap_op__ldst_exc \dummy_trap_op__ldst_exc + connect \trap_op__ldst_exc$10 \dummy_trap_op__ldst_exc$24 + connect \trap_op__msr \dummy_trap_op__msr + connect \trap_op__msr$5 \dummy_trap_op__msr$19 + connect \trap_op__trapaddr \dummy_trap_op__trapaddr + connect \trap_op__trapaddr$9 \dummy_trap_op__trapaddr$23 + connect \trap_op__traptype \dummy_trap_op__traptype + connect \trap_op__traptype$8 \dummy_trap_op__traptype$22 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:156274.10-156277.4" + cell \n$34 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:156278.10-156281.4" + cell \p$33 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:155571.7-155571.20" + process $proc$libresoc.v:155571$8963 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:155810.14-155810.42" + process $proc$libresoc.v:155810$8964 + assign { } { } + assign $1\fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \fast1 $1\fast1[63:0] + end + attribute \src "libresoc.v:155819.14-155819.42" + process $proc$libresoc.v:155819$8965 + assign { } { } + assign $1\fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \fast2 $1\fast2[63:0] + end + attribute \src "libresoc.v:155828.13-155828.25" + process $proc$libresoc.v:155828$8966 + assign { } { } + assign $1\muxid[1:0] 2'00 + sync always + sync init + update \muxid $1\muxid[1:0] + end + attribute \src "libresoc.v:155850.7-155850.20" + process $proc$libresoc.v:155850$8967 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:155855.14-155855.39" + process $proc$libresoc.v:155855$8968 + assign { } { } + assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ra $1\ra[63:0] + end + attribute \src "libresoc.v:155864.14-155864.39" + process $proc$libresoc.v:155864$8969 + assign { } { } + assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \rb $1\rb[63:0] + end + attribute \src "libresoc.v:155873.14-155873.49" + process $proc$libresoc.v:155873$8970 + assign { } { } + assign $1\trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \trap_op__cia $1\trap_op__cia[63:0] + end + attribute \src "libresoc.v:155895.14-155895.40" + process $proc$libresoc.v:155895$8971 + assign { } { } + assign $1\trap_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \trap_op__fn_unit $1\trap_op__fn_unit[11:0] + end + attribute \src "libresoc.v:155930.14-155930.35" + process $proc$libresoc.v:155930$8972 + assign { } { } + assign $1\trap_op__insn[31:0] 0 + sync always + sync init + update \trap_op__insn $1\trap_op__insn[31:0] + end + attribute \src "libresoc.v:156013.13-156013.39" + process $proc$libresoc.v:156013$8973 + assign { } { } + assign $1\trap_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \trap_op__insn_type $1\trap_op__insn_type[6:0] + end + attribute \src "libresoc.v:156170.7-156170.31" + process $proc$libresoc.v:156170$8974 + assign { } { } + assign $1\trap_op__is_32bit[0:0] 1'0 + sync always + sync init + update \trap_op__is_32bit $1\trap_op__is_32bit[0:0] + end + attribute \src "libresoc.v:156179.13-156179.38" + process $proc$libresoc.v:156179$8975 + assign { } { } + assign $1\trap_op__ldst_exc[7:0] 8'00000000 + sync always + sync init + update \trap_op__ldst_exc $1\trap_op__ldst_exc[7:0] + end + attribute \src "libresoc.v:156188.14-156188.49" + process $proc$libresoc.v:156188$8976 + assign { } { } + assign $1\trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \trap_op__msr $1\trap_op__msr[63:0] + end + attribute \src "libresoc.v:156197.14-156197.42" + process $proc$libresoc.v:156197$8977 + assign { } { } + assign $1\trap_op__trapaddr[12:0] 13'0000000000000 + sync always + sync init + update \trap_op__trapaddr $1\trap_op__trapaddr[12:0] + end + attribute \src "libresoc.v:156206.13-156206.38" + process $proc$libresoc.v:156206$8978 + assign { } { } + assign $1\trap_op__traptype[7:0] 8'00000000 + sync always + sync init + update \trap_op__traptype $1\trap_op__traptype[7:0] + end + attribute \src "libresoc.v:156214.3-156215.43" + process $proc$libresoc.v:156214$8910 + assign { } { } + assign $0\trap_op__insn[31:0] \trap_op__insn$next + sync posedge \coresync_clk + update \trap_op__insn $0\trap_op__insn[31:0] + end + attribute \src "libresoc.v:156216.3-156217.41" + process $proc$libresoc.v:156216$8911 + assign { } { } + assign $0\trap_op__msr[63:0] \trap_op__msr$next + sync posedge \coresync_clk + update \trap_op__msr $0\trap_op__msr[63:0] + end + attribute \src "libresoc.v:156218.3-156219.41" + process $proc$libresoc.v:156218$8912 + assign { } { } + assign $0\trap_op__cia[63:0] \trap_op__cia$next + sync posedge \coresync_clk + update \trap_op__cia $0\trap_op__cia[63:0] + end + attribute \src "libresoc.v:156220.3-156221.51" + process $proc$libresoc.v:156220$8913 + assign { } { } + assign $0\trap_op__is_32bit[0:0] \trap_op__is_32bit$next + sync posedge \coresync_clk + update \trap_op__is_32bit $0\trap_op__is_32bit[0:0] + end + attribute \src "libresoc.v:156222.3-156223.51" + process $proc$libresoc.v:156222$8914 + assign { } { } + assign $0\trap_op__traptype[7:0] \trap_op__traptype$next + sync posedge \coresync_clk + update \trap_op__traptype $0\trap_op__traptype[7:0] + end + attribute \src "libresoc.v:156224.3-156225.51" + process $proc$libresoc.v:156224$8915 + assign { } { } + assign $0\trap_op__trapaddr[12:0] \trap_op__trapaddr$next + sync posedge \coresync_clk + update \trap_op__trapaddr $0\trap_op__trapaddr[12:0] + end + attribute \src "libresoc.v:156226.3-156227.51" + process $proc$libresoc.v:156226$8916 + assign { } { } + assign $0\trap_op__ldst_exc[7:0] \trap_op__ldst_exc$next + sync posedge \coresync_clk + update \trap_op__ldst_exc $0\trap_op__ldst_exc[7:0] + end + attribute \src "libresoc.v:156228.3-156229.27" + process $proc$libresoc.v:156228$8917 + assign { } { } + assign $0\muxid[1:0] \muxid$next + sync posedge \coresync_clk + update \muxid $0\muxid[1:0] + end + attribute \src "libresoc.v:156230.3-156231.29" + process $proc$libresoc.v:156230$8918 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:156232.3-156233.27" + process $proc$libresoc.v:156232$8919 + assign { } { } + assign $0\fast2[63:0] \fast2$next + sync posedge \coresync_clk + update \fast2 $0\fast2[63:0] + end + attribute \src "libresoc.v:156234.3-156235.27" + process $proc$libresoc.v:156234$8920 + assign { } { } + assign $0\fast1[63:0] \fast1$next + sync posedge \coresync_clk + update \fast1 $0\fast1[63:0] + end + attribute \src "libresoc.v:156236.3-156237.21" + process $proc$libresoc.v:156236$8921 + assign { } { } + assign $0\rb[63:0] \rb$next + sync posedge \coresync_clk + update \rb $0\rb[63:0] + end + attribute \src "libresoc.v:156238.3-156239.21" + process $proc$libresoc.v:156238$8922 + assign { } { } + assign $0\ra[63:0] \ra$next + sync posedge \coresync_clk + update \ra $0\ra[63:0] + end + attribute \src "libresoc.v:156240.3-156241.53" + process $proc$libresoc.v:156240$8923 + assign { } { } + assign $0\trap_op__insn_type[6:0] \trap_op__insn_type$next + sync posedge \coresync_clk + update \trap_op__insn_type $0\trap_op__insn_type[6:0] + end + attribute \src "libresoc.v:156242.3-156243.49" + process $proc$libresoc.v:156242$8924 + assign { } { } + assign $0\trap_op__fn_unit[11:0] \trap_op__fn_unit$next + sync posedge \coresync_clk + update \trap_op__fn_unit $0\trap_op__fn_unit[11:0] + end + attribute \src "libresoc.v:156282.3-156299.6" + process $proc$libresoc.v:156282$8925 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$8926 $2\r_busy$next[0:0]$8928 + attribute \src "libresoc.v:156283.5-156283.29" + switch \initial + attribute \src "libresoc.v:156283.9-156283.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$8927 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$8927 1'0 + case + assign $1\r_busy$next[0:0]$8927 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$8928 1'0 + case + assign $2\r_busy$next[0:0]$8928 $1\r_busy$next[0:0]$8927 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$8926 + end + attribute \src "libresoc.v:156300.3-156312.6" + process $proc$libresoc.v:156300$8929 + assign { } { } + assign { } { } + assign $0\muxid$next[1:0]$8930 $1\muxid$next[1:0]$8931 + attribute \src "libresoc.v:156301.5-156301.29" + switch \initial + attribute \src "libresoc.v:156301.9-156301.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$next[1:0]$8931 \muxid$32 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$next[1:0]$8931 \muxid$32 + case + assign $1\muxid$next[1:0]$8931 \muxid + end + sync always + update \muxid$next $0\muxid$next[1:0]$8930 + end + attribute \src "libresoc.v:156313.3-156333.6" + process $proc$libresoc.v:156313$8932 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\trap_op__cia$next[63:0]$8933 $1\trap_op__cia$next[63:0]$8942 + assign $0\trap_op__fn_unit$next[11:0]$8934 $1\trap_op__fn_unit$next[11:0]$8943 + assign $0\trap_op__insn$next[31:0]$8935 $1\trap_op__insn$next[31:0]$8944 + assign $0\trap_op__insn_type$next[6:0]$8936 $1\trap_op__insn_type$next[6:0]$8945 + assign $0\trap_op__is_32bit$next[0:0]$8937 $1\trap_op__is_32bit$next[0:0]$8946 + assign $0\trap_op__ldst_exc$next[7:0]$8938 $1\trap_op__ldst_exc$next[7:0]$8947 + assign $0\trap_op__msr$next[63:0]$8939 $1\trap_op__msr$next[63:0]$8948 + assign $0\trap_op__trapaddr$next[12:0]$8940 $1\trap_op__trapaddr$next[12:0]$8949 + assign $0\trap_op__traptype$next[7:0]$8941 $1\trap_op__traptype$next[7:0]$8950 + attribute \src "libresoc.v:156314.5-156314.29" + switch \initial + attribute \src "libresoc.v:156314.9-156314.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\trap_op__ldst_exc$next[7:0]$8947 $1\trap_op__trapaddr$next[12:0]$8949 $1\trap_op__traptype$next[7:0]$8950 $1\trap_op__is_32bit$next[0:0]$8946 $1\trap_op__cia$next[63:0]$8942 $1\trap_op__msr$next[63:0]$8948 $1\trap_op__insn$next[31:0]$8944 $1\trap_op__fn_unit$next[11:0]$8943 $1\trap_op__insn_type$next[6:0]$8945 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\trap_op__ldst_exc$next[7:0]$8947 $1\trap_op__trapaddr$next[12:0]$8949 $1\trap_op__traptype$next[7:0]$8950 $1\trap_op__is_32bit$next[0:0]$8946 $1\trap_op__cia$next[63:0]$8942 $1\trap_op__msr$next[63:0]$8948 $1\trap_op__insn$next[31:0]$8944 $1\trap_op__fn_unit$next[11:0]$8943 $1\trap_op__insn_type$next[6:0]$8945 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } + case + assign $1\trap_op__cia$next[63:0]$8942 \trap_op__cia + assign $1\trap_op__fn_unit$next[11:0]$8943 \trap_op__fn_unit + assign $1\trap_op__insn$next[31:0]$8944 \trap_op__insn + assign $1\trap_op__insn_type$next[6:0]$8945 \trap_op__insn_type + assign $1\trap_op__is_32bit$next[0:0]$8946 \trap_op__is_32bit + assign $1\trap_op__ldst_exc$next[7:0]$8947 \trap_op__ldst_exc + assign $1\trap_op__msr$next[63:0]$8948 \trap_op__msr + assign $1\trap_op__trapaddr$next[12:0]$8949 \trap_op__trapaddr + assign $1\trap_op__traptype$next[7:0]$8950 \trap_op__traptype + end + sync always + update \trap_op__cia$next $0\trap_op__cia$next[63:0]$8933 + update \trap_op__fn_unit$next $0\trap_op__fn_unit$next[11:0]$8934 + update \trap_op__insn$next $0\trap_op__insn$next[31:0]$8935 + update \trap_op__insn_type$next $0\trap_op__insn_type$next[6:0]$8936 + update \trap_op__is_32bit$next $0\trap_op__is_32bit$next[0:0]$8937 + update \trap_op__ldst_exc$next $0\trap_op__ldst_exc$next[7:0]$8938 + update \trap_op__msr$next $0\trap_op__msr$next[63:0]$8939 + update \trap_op__trapaddr$next $0\trap_op__trapaddr$next[12:0]$8940 + update \trap_op__traptype$next $0\trap_op__traptype$next[7:0]$8941 + end + attribute \src "libresoc.v:156334.3-156346.6" + process $proc$libresoc.v:156334$8951 + assign { } { } + assign { } { } + assign $0\ra$next[63:0]$8952 $1\ra$next[63:0]$8953 + attribute \src "libresoc.v:156335.5-156335.29" + switch \initial + attribute \src "libresoc.v:156335.9-156335.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\ra$next[63:0]$8953 \ra$42 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\ra$next[63:0]$8953 \ra$42 + case + assign $1\ra$next[63:0]$8953 \ra + end + sync always + update \ra$next $0\ra$next[63:0]$8952 + end + attribute \src "libresoc.v:156347.3-156359.6" + process $proc$libresoc.v:156347$8954 + assign { } { } + assign { } { } + assign $0\rb$next[63:0]$8955 $1\rb$next[63:0]$8956 + attribute \src "libresoc.v:156348.5-156348.29" + switch \initial + attribute \src "libresoc.v:156348.9-156348.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\rb$next[63:0]$8956 \rb$43 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\rb$next[63:0]$8956 \rb$43 + case + assign $1\rb$next[63:0]$8956 \rb + end + sync always + update \rb$next $0\rb$next[63:0]$8955 + end + attribute \src "libresoc.v:156360.3-156372.6" + process $proc$libresoc.v:156360$8957 + assign { } { } + assign { } { } + assign $0\fast1$next[63:0]$8958 $1\fast1$next[63:0]$8959 + attribute \src "libresoc.v:156361.5-156361.29" + switch \initial + attribute \src "libresoc.v:156361.9-156361.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\fast1$next[63:0]$8959 \fast1$44 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\fast1$next[63:0]$8959 \fast1$44 + case + assign $1\fast1$next[63:0]$8959 \fast1 + end + sync always + update \fast1$next $0\fast1$next[63:0]$8958 + end + attribute \src "libresoc.v:156373.3-156385.6" + process $proc$libresoc.v:156373$8960 + assign { } { } + assign { } { } + assign $0\fast2$next[63:0]$8961 $1\fast2$next[63:0]$8962 + attribute \src "libresoc.v:156374.5-156374.29" + switch \initial + attribute \src "libresoc.v:156374.9-156374.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\fast2$next[63:0]$8962 \fast2$45 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\fast2$next[63:0]$8962 \fast2$45 + case + assign $1\fast2$next[63:0]$8962 \fast2 + end + sync always + update \fast2$next $0\fast2$next[63:0]$8961 + end + connect \$30 $and$libresoc.v:156213$8909_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect \fast2$45 \dummy_fast2$28 + connect \fast1$44 \dummy_fast1$27 + connect \rb$43 \dummy_rb$26 + connect \ra$42 \dummy_ra$25 + connect { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } { \dummy_trap_op__ldst_exc$24 \dummy_trap_op__trapaddr$23 \dummy_trap_op__traptype$22 \dummy_trap_op__is_32bit$21 \dummy_trap_op__cia$20 \dummy_trap_op__msr$19 \dummy_trap_op__insn$18 \dummy_trap_op__fn_unit$17 \dummy_trap_op__insn_type$16 } + connect \muxid$32 \dummy_muxid$15 + connect \p_valid_i_p_ready_o \$30 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$29 \p_valid_i + connect \dummy_fast2 \fast2$14 + connect \dummy_fast1 \fast1$13 + connect \dummy_rb \rb$12 + connect \dummy_ra \ra$11 + connect { \dummy_trap_op__ldst_exc \dummy_trap_op__trapaddr \dummy_trap_op__traptype \dummy_trap_op__is_32bit \dummy_trap_op__cia \dummy_trap_op__msr \dummy_trap_op__insn \dummy_trap_op__fn_unit \dummy_trap_op__insn_type } { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } + connect \dummy_muxid \muxid$1 +end +attribute \src "libresoc.v:156407.1-157577.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2" +attribute \generator "nMigen" +module \pipe2 + attribute \src "libresoc.v:157421.3-157462.6" + wire width 4 $0\alu_op__data_len$18$next[3:0]$9047 + attribute \src "libresoc.v:157318.3-157319.57" + wire width 4 $0\alu_op__data_len$18[3:0]$9033 + attribute \src "libresoc.v:156415.13-156415.41" + wire width 4 $0\alu_op__data_len$18[3:0]$9121 + attribute \src "libresoc.v:157421.3-157462.6" + wire width 12 $0\alu_op__fn_unit$3$next[11:0]$9048 + attribute \src "libresoc.v:157288.3-157289.53" + wire width 12 $0\alu_op__fn_unit$3[11:0]$9003 + attribute \src "libresoc.v:156450.14-156450.43" + wire width 12 $0\alu_op__fn_unit$3[11:0]$9123 + attribute \src "libresoc.v:157421.3-157462.6" + wire width 64 $0\alu_op__imm_data__data$4$next[63:0]$9049 + attribute \src "libresoc.v:157290.3-157291.67" + wire width 64 $0\alu_op__imm_data__data$4[63:0]$9005 + attribute \src "libresoc.v:156472.14-156472.63" + wire width 64 $0\alu_op__imm_data__data$4[63:0]$9125 + attribute \src "libresoc.v:157421.3-157462.6" + wire $0\alu_op__imm_data__ok$5$next[0:0]$9050 + attribute \src "libresoc.v:157292.3-157293.63" + wire $0\alu_op__imm_data__ok$5[0:0]$9007 + attribute \src "libresoc.v:156481.7-156481.38" + wire $0\alu_op__imm_data__ok$5[0:0]$9127 + attribute \src "libresoc.v:157421.3-157462.6" + wire width 2 $0\alu_op__input_carry$14$next[1:0]$9051 + attribute \src "libresoc.v:157310.3-157311.63" + wire width 2 $0\alu_op__input_carry$14[1:0]$9025 + attribute \src "libresoc.v:156498.13-156498.44" + wire width 2 $0\alu_op__input_carry$14[1:0]$9129 + attribute \src "libresoc.v:157421.3-157462.6" + wire width 32 $0\alu_op__insn$19$next[31:0]$9052 + attribute \src "libresoc.v:157320.3-157321.49" + wire width 32 $0\alu_op__insn$19[31:0]$9035 + attribute \src "libresoc.v:156511.14-156511.39" + wire width 32 $0\alu_op__insn$19[31:0]$9131 + attribute \src "libresoc.v:157421.3-157462.6" + wire width 7 $0\alu_op__insn_type$2$next[6:0]$9053 + attribute \src "libresoc.v:157286.3-157287.57" + wire width 7 $0\alu_op__insn_type$2[6:0]$9001 + attribute \src "libresoc.v:156668.13-156668.42" + wire width 7 $0\alu_op__insn_type$2[6:0]$9133 + attribute \src "libresoc.v:157421.3-157462.6" + wire $0\alu_op__invert_in$10$next[0:0]$9054 + attribute \src "libresoc.v:157302.3-157303.59" + wire $0\alu_op__invert_in$10[0:0]$9017 + attribute \src "libresoc.v:156751.7-156751.36" + wire $0\alu_op__invert_in$10[0:0]$9135 + attribute \src "libresoc.v:157421.3-157462.6" + wire $0\alu_op__invert_out$12$next[0:0]$9055 + attribute \src "libresoc.v:157306.3-157307.61" + wire $0\alu_op__invert_out$12[0:0]$9021 + attribute \src "libresoc.v:156760.7-156760.37" + wire $0\alu_op__invert_out$12[0:0]$9137 + attribute \src "libresoc.v:157421.3-157462.6" + wire $0\alu_op__is_32bit$16$next[0:0]$9056 + attribute \src "libresoc.v:157314.3-157315.57" + wire $0\alu_op__is_32bit$16[0:0]$9029 + attribute \src "libresoc.v:156769.7-156769.35" + wire $0\alu_op__is_32bit$16[0:0]$9139 + attribute \src "libresoc.v:157421.3-157462.6" + wire $0\alu_op__is_signed$17$next[0:0]$9057 + attribute \src "libresoc.v:157316.3-157317.59" + wire $0\alu_op__is_signed$17[0:0]$9031 + attribute \src "libresoc.v:156778.7-156778.36" + wire $0\alu_op__is_signed$17[0:0]$9141 + attribute \src "libresoc.v:157421.3-157462.6" + wire $0\alu_op__oe__oe$8$next[0:0]$9058 + attribute \src "libresoc.v:157298.3-157299.51" + wire $0\alu_op__oe__oe$8[0:0]$9013 + attribute \src "libresoc.v:156789.7-156789.32" + wire $0\alu_op__oe__oe$8[0:0]$9143 + attribute \src "libresoc.v:157421.3-157462.6" + wire $0\alu_op__oe__ok$9$next[0:0]$9059 + attribute \src "libresoc.v:157300.3-157301.51" + wire $0\alu_op__oe__ok$9[0:0]$9015 + attribute \src "libresoc.v:156798.7-156798.32" + wire $0\alu_op__oe__ok$9[0:0]$9145 + attribute \src "libresoc.v:157421.3-157462.6" + wire $0\alu_op__output_carry$15$next[0:0]$9060 + attribute \src "libresoc.v:157312.3-157313.65" + wire $0\alu_op__output_carry$15[0:0]$9027 + attribute \src "libresoc.v:156805.7-156805.39" + wire $0\alu_op__output_carry$15[0:0]$9147 + attribute \src "libresoc.v:157421.3-157462.6" + wire $0\alu_op__rc__ok$7$next[0:0]$9061 + attribute \src "libresoc.v:157296.3-157297.51" + wire $0\alu_op__rc__ok$7[0:0]$9011 + attribute \src "libresoc.v:156816.7-156816.32" + wire $0\alu_op__rc__ok$7[0:0]$9149 + attribute \src "libresoc.v:157421.3-157462.6" + wire $0\alu_op__rc__rc$6$next[0:0]$9062 + attribute \src "libresoc.v:157294.3-157295.51" + wire $0\alu_op__rc__rc$6[0:0]$9009 + attribute \src "libresoc.v:156823.7-156823.32" + wire $0\alu_op__rc__rc$6[0:0]$9151 + attribute \src "libresoc.v:157421.3-157462.6" + wire $0\alu_op__write_cr0$13$next[0:0]$9063 + attribute \src "libresoc.v:157308.3-157309.59" + wire $0\alu_op__write_cr0$13[0:0]$9023 + attribute \src "libresoc.v:156832.7-156832.36" + wire $0\alu_op__write_cr0$13[0:0]$9153 + attribute \src "libresoc.v:157421.3-157462.6" + wire $0\alu_op__zero_a$11$next[0:0]$9064 + attribute \src "libresoc.v:157304.3-157305.53" + wire $0\alu_op__zero_a$11[0:0]$9019 + attribute \src "libresoc.v:156841.7-156841.33" + wire $0\alu_op__zero_a$11[0:0]$9155 + attribute \src "libresoc.v:157482.3-157500.6" + wire width 4 $0\cr_a$22$next[3:0]$9096 + attribute \src "libresoc.v:157278.3-157279.33" + wire width 4 $0\cr_a$22[3:0]$8993 + attribute \src "libresoc.v:156854.13-156854.29" + wire width 4 $0\cr_a$22[3:0]$9157 + attribute \src "libresoc.v:157482.3-157500.6" + wire $0\cr_a_ok$23$next[0:0]$9097 + attribute \src "libresoc.v:157280.3-157281.39" + wire $0\cr_a_ok$23[0:0]$8995 + attribute \src "libresoc.v:156863.7-156863.26" + wire $0\cr_a_ok$23[0:0]$9159 + attribute \src "libresoc.v:156408.7-156408.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:157408.3-157420.6" + wire width 2 $0\muxid$1$next[1:0]$9044 + attribute \src "libresoc.v:157322.3-157323.33" + wire width 2 $0\muxid$1[1:0]$9037 + attribute \src "libresoc.v:156874.13-156874.29" + wire width 2 $0\muxid$1[1:0]$9161 + attribute \src "libresoc.v:157463.3-157481.6" + wire width 64 $0\o$20$next[63:0]$9090 + attribute \src "libresoc.v:157282.3-157283.27" + wire width 64 $0\o$20[63:0]$8997 + attribute \src "libresoc.v:156889.14-156889.43" + wire width 64 $0\o$20[63:0]$9163 + attribute \src "libresoc.v:157463.3-157481.6" + wire $0\o_ok$21$next[0:0]$9091 + attribute \src "libresoc.v:157284.3-157285.33" + wire $0\o_ok$21[0:0]$8999 + attribute \src "libresoc.v:156898.7-156898.23" + wire $0\o_ok$21[0:0]$9165 + attribute \src "libresoc.v:157390.3-157407.6" + wire $0\r_busy$next[0:0]$9040 + attribute \src "libresoc.v:157324.3-157325.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:157501.3-157519.6" + wire width 2 $0\xer_ca$24$next[1:0]$9102 + attribute \src "libresoc.v:157274.3-157275.37" + wire width 2 $0\xer_ca$24[1:0]$8989 + attribute \src "libresoc.v:157209.13-157209.31" + wire width 2 $0\xer_ca$24[1:0]$9168 + attribute \src "libresoc.v:157501.3-157519.6" + wire $0\xer_ca_ok$25$next[0:0]$9103 + attribute \src "libresoc.v:157276.3-157277.43" + wire $0\xer_ca_ok$25[0:0]$8991 + attribute \src "libresoc.v:157218.7-157218.28" + wire $0\xer_ca_ok$25[0:0]$9170 + attribute \src "libresoc.v:157520.3-157538.6" + wire width 2 $0\xer_ov$26$next[1:0]$9108 + attribute \src "libresoc.v:157270.3-157271.37" + wire width 2 $0\xer_ov$26[1:0]$8985 + attribute \src "libresoc.v:157229.13-157229.31" + wire width 2 $0\xer_ov$26[1:0]$9172 + attribute \src "libresoc.v:157520.3-157538.6" + wire $0\xer_ov_ok$27$next[0:0]$9109 + attribute \src "libresoc.v:157272.3-157273.43" + wire $0\xer_ov_ok$27[0:0]$8987 + attribute \src "libresoc.v:157238.7-157238.28" + wire $0\xer_ov_ok$27[0:0]$9174 + attribute \src "libresoc.v:157539.3-157557.6" + wire $0\xer_so$28$next[0:0]$9114 + attribute \src "libresoc.v:157266.3-157267.37" + wire $0\xer_so$28[0:0]$8981 + attribute \src "libresoc.v:157249.7-157249.25" + wire $0\xer_so$28[0:0]$9176 + attribute \src "libresoc.v:157539.3-157557.6" + wire $0\xer_so_ok$29$next[0:0]$9115 + attribute \src "libresoc.v:157268.3-157269.43" + wire $0\xer_so_ok$29[0:0]$8983 + attribute \src "libresoc.v:157258.7-157258.28" + wire $0\xer_so_ok$29[0:0]$9178 + attribute \src "libresoc.v:157421.3-157462.6" + wire width 4 $1\alu_op__data_len$18$next[3:0]$9065 + attribute \src "libresoc.v:157421.3-157462.6" + wire width 12 $1\alu_op__fn_unit$3$next[11:0]$9066 + attribute \src "libresoc.v:157421.3-157462.6" + wire width 64 $1\alu_op__imm_data__data$4$next[63:0]$9067 + attribute \src "libresoc.v:157421.3-157462.6" + wire $1\alu_op__imm_data__ok$5$next[0:0]$9068 + attribute \src "libresoc.v:157421.3-157462.6" + wire width 2 $1\alu_op__input_carry$14$next[1:0]$9069 + attribute \src "libresoc.v:157421.3-157462.6" + wire width 32 $1\alu_op__insn$19$next[31:0]$9070 + attribute \src "libresoc.v:157421.3-157462.6" + wire width 7 $1\alu_op__insn_type$2$next[6:0]$9071 + attribute \src "libresoc.v:157421.3-157462.6" + wire $1\alu_op__invert_in$10$next[0:0]$9072 + attribute \src "libresoc.v:157421.3-157462.6" + wire $1\alu_op__invert_out$12$next[0:0]$9073 + attribute \src "libresoc.v:157421.3-157462.6" + wire $1\alu_op__is_32bit$16$next[0:0]$9074 + attribute \src "libresoc.v:157421.3-157462.6" + wire $1\alu_op__is_signed$17$next[0:0]$9075 + attribute \src "libresoc.v:157421.3-157462.6" + wire $1\alu_op__oe__oe$8$next[0:0]$9076 + attribute \src "libresoc.v:157421.3-157462.6" + wire $1\alu_op__oe__ok$9$next[0:0]$9077 + attribute \src "libresoc.v:157421.3-157462.6" + wire $1\alu_op__output_carry$15$next[0:0]$9078 + attribute \src "libresoc.v:157421.3-157462.6" + wire $1\alu_op__rc__ok$7$next[0:0]$9079 + attribute \src "libresoc.v:157421.3-157462.6" + wire $1\alu_op__rc__rc$6$next[0:0]$9080 + attribute \src "libresoc.v:157421.3-157462.6" + wire $1\alu_op__write_cr0$13$next[0:0]$9081 + attribute \src "libresoc.v:157421.3-157462.6" + wire $1\alu_op__zero_a$11$next[0:0]$9082 + attribute \src "libresoc.v:157482.3-157500.6" + wire width 4 $1\cr_a$22$next[3:0]$9098 + attribute \src "libresoc.v:157482.3-157500.6" + wire $1\cr_a_ok$23$next[0:0]$9099 + attribute \src "libresoc.v:157408.3-157420.6" + wire width 2 $1\muxid$1$next[1:0]$9045 + attribute \src "libresoc.v:157463.3-157481.6" + wire width 64 $1\o$20$next[63:0]$9092 + attribute \src "libresoc.v:157463.3-157481.6" + wire $1\o_ok$21$next[0:0]$9093 + attribute \src "libresoc.v:157390.3-157407.6" + wire $1\r_busy$next[0:0]$9041 + attribute \src "libresoc.v:157202.7-157202.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:157501.3-157519.6" + wire width 2 $1\xer_ca$24$next[1:0]$9104 + attribute \src "libresoc.v:157501.3-157519.6" + wire $1\xer_ca_ok$25$next[0:0]$9105 + attribute \src "libresoc.v:157520.3-157538.6" + wire width 2 $1\xer_ov$26$next[1:0]$9110 + attribute \src "libresoc.v:157520.3-157538.6" + wire $1\xer_ov_ok$27$next[0:0]$9111 + attribute \src "libresoc.v:157539.3-157557.6" + wire $1\xer_so$28$next[0:0]$9116 + attribute \src "libresoc.v:157539.3-157557.6" + wire $1\xer_so_ok$29$next[0:0]$9117 + attribute \src "libresoc.v:157421.3-157462.6" + wire width 64 $2\alu_op__imm_data__data$4$next[63:0]$9083 + attribute \src "libresoc.v:157421.3-157462.6" + wire $2\alu_op__imm_data__ok$5$next[0:0]$9084 + attribute \src "libresoc.v:157421.3-157462.6" + wire $2\alu_op__oe__oe$8$next[0:0]$9085 + attribute \src "libresoc.v:157421.3-157462.6" + wire $2\alu_op__oe__ok$9$next[0:0]$9086 + attribute \src "libresoc.v:157421.3-157462.6" + wire $2\alu_op__rc__ok$7$next[0:0]$9087 + attribute \src "libresoc.v:157421.3-157462.6" + wire $2\alu_op__rc__rc$6$next[0:0]$9088 + attribute \src "libresoc.v:157482.3-157500.6" + wire $2\cr_a_ok$23$next[0:0]$9100 + attribute \src "libresoc.v:157463.3-157481.6" + wire $2\o_ok$21$next[0:0]$9094 + attribute \src "libresoc.v:157390.3-157407.6" + wire $2\r_busy$next[0:0]$9042 + attribute \src "libresoc.v:157501.3-157519.6" + wire $2\xer_ca_ok$25$next[0:0]$9106 + attribute \src "libresoc.v:157520.3-157538.6" + wire $2\xer_ov_ok$27$next[0:0]$9112 + attribute \src "libresoc.v:157539.3-157557.6" + wire $2\xer_so_ok$29$next[0:0]$9118 + attribute \src "libresoc.v:157265.18-157265.118" + wire $and$libresoc.v:157265$8979_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 52 \alu_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$79 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 6 \alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 37 \alu_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_op__fn_unit$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 38 \alu_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__data$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__data$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \alu_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__imm_data__ok$66 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 17 \alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 48 \alu_op__input_carry$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$14$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 53 \alu_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$80 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 36 \alu_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_op__insn_type$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 44 \alu_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_in$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_in$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 46 \alu_op__invert_out$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_out$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_out$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 50 \alu_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_32bit$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 51 \alu_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_signed$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__oe$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 42 \alu_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__ok$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 43 \alu_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 49 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__output_carry$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__ok$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \alu_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__rc$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 47 \alu_op__write_cr0$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__write_cr0$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__write_cr0$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 45 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__zero_a$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__zero_a$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 64 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 input 25 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 56 \cr_a$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 26 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 57 \cr_a_ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$84 + attribute \src "libresoc.v:156408.7-156408.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 35 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$62 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 34 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 33 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 23 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 54 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 24 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 55 \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_alu_op__data_len$47 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \output_alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \output_alu_op__fn_unit$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_alu_op__imm_data__data$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__imm_data__ok$34 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_alu_op__input_carry$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_alu_op__insn$48 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_alu_op__insn_type$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__invert_in$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__invert_out$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__is_32bit$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__is_signed$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__oe__oe$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__oe__ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__output_carry$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__rc__ok$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__rc__rc$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__write_cr0$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__zero_a$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_muxid$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ca$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ov$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$59 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 input 27 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 58 \xer_ca$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 28 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 59 \xer_ca_ok$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$25$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 input 29 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 60 \xer_ov$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$26$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 30 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 61 \xer_ov_ok$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$27$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 31 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 62 \xer_so$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$28$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 32 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 63 \xer_so_ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$29$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$90 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$libresoc.v:157265$8979 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$59 + connect \B \p_ready_o + connect \Y $and$libresoc.v:157265$8979_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:157326.9-157329.4" + cell \n$4 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:157330.12-157385.4" + cell \output \output + connect \alu_op__data_len \output_alu_op__data_len + connect \alu_op__data_len$18 \output_alu_op__data_len$47 + connect \alu_op__fn_unit \output_alu_op__fn_unit + connect \alu_op__fn_unit$3 \output_alu_op__fn_unit$32 + connect \alu_op__imm_data__data \output_alu_op__imm_data__data + connect \alu_op__imm_data__data$4 \output_alu_op__imm_data__data$33 + connect \alu_op__imm_data__ok \output_alu_op__imm_data__ok + connect \alu_op__imm_data__ok$5 \output_alu_op__imm_data__ok$34 + connect \alu_op__input_carry \output_alu_op__input_carry + connect \alu_op__input_carry$14 \output_alu_op__input_carry$43 + connect \alu_op__insn \output_alu_op__insn + connect \alu_op__insn$19 \output_alu_op__insn$48 + connect \alu_op__insn_type \output_alu_op__insn_type + connect \alu_op__insn_type$2 \output_alu_op__insn_type$31 + connect \alu_op__invert_in \output_alu_op__invert_in + connect \alu_op__invert_in$10 \output_alu_op__invert_in$39 + connect \alu_op__invert_out \output_alu_op__invert_out + connect \alu_op__invert_out$12 \output_alu_op__invert_out$41 + connect \alu_op__is_32bit \output_alu_op__is_32bit + connect \alu_op__is_32bit$16 \output_alu_op__is_32bit$45 + connect \alu_op__is_signed \output_alu_op__is_signed + connect \alu_op__is_signed$17 \output_alu_op__is_signed$46 + connect \alu_op__oe__oe \output_alu_op__oe__oe + connect \alu_op__oe__oe$8 \output_alu_op__oe__oe$37 + connect \alu_op__oe__ok \output_alu_op__oe__ok + connect \alu_op__oe__ok$9 \output_alu_op__oe__ok$38 + connect \alu_op__output_carry \output_alu_op__output_carry + connect \alu_op__output_carry$15 \output_alu_op__output_carry$44 + connect \alu_op__rc__ok \output_alu_op__rc__ok + connect \alu_op__rc__ok$7 \output_alu_op__rc__ok$36 + connect \alu_op__rc__rc \output_alu_op__rc__rc + connect \alu_op__rc__rc$6 \output_alu_op__rc__rc$35 + connect \alu_op__write_cr0 \output_alu_op__write_cr0 + connect \alu_op__write_cr0$13 \output_alu_op__write_cr0$42 + connect \alu_op__zero_a \output_alu_op__zero_a + connect \alu_op__zero_a$11 \output_alu_op__zero_a$40 + connect \cr_a \output_cr_a + connect \cr_a$22 \output_cr_a$51 + connect \cr_a_ok \output_cr_a_ok + connect \muxid \output_muxid + connect \muxid$1 \output_muxid$30 + connect \o \output_o + connect \o$20 \output_o$49 + connect \o_ok \output_o_ok + connect \o_ok$21 \output_o_ok$50 + connect \xer_ca \output_xer_ca + connect \xer_ca$23 \output_xer_ca$52 + connect \xer_ca_ok \output_xer_ca_ok + connect \xer_ov \output_xer_ov + connect \xer_ov$24 \output_xer_ov$53 + connect \xer_ov_ok \output_xer_ov_ok + connect \xer_so \output_xer_so + connect \xer_so$25 \output_xer_so$54 + connect \xer_so_ok \output_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:157386.9-157389.4" + cell \p$3 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:156408.7-156408.20" + process $proc$libresoc.v:156408$9119 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:156415.13-156415.41" + process $proc$libresoc.v:156415$9120 + assign { } { } + assign $0\alu_op__data_len$18[3:0]$9121 4'0000 + sync always + sync init + update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9121 + end + attribute \src "libresoc.v:156450.14-156450.43" + process $proc$libresoc.v:156450$9122 + assign { } { } + assign $0\alu_op__fn_unit$3[11:0]$9123 12'000000000000 + sync always + sync init + update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[11:0]$9123 + end + attribute \src "libresoc.v:156472.14-156472.63" + process $proc$libresoc.v:156472$9124 + assign { } { } + assign $0\alu_op__imm_data__data$4[63:0]$9125 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9125 + end + attribute \src "libresoc.v:156481.7-156481.38" + process $proc$libresoc.v:156481$9126 + assign { } { } + assign $0\alu_op__imm_data__ok$5[0:0]$9127 1'0 + sync always + sync init + update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9127 + end + attribute \src "libresoc.v:156498.13-156498.44" + process $proc$libresoc.v:156498$9128 + assign { } { } + assign $0\alu_op__input_carry$14[1:0]$9129 2'00 + sync always + sync init + update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9129 + end + attribute \src "libresoc.v:156511.14-156511.39" + process $proc$libresoc.v:156511$9130 + assign { } { } + assign $0\alu_op__insn$19[31:0]$9131 0 + sync always + sync init + update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9131 + end + attribute \src "libresoc.v:156668.13-156668.42" + process $proc$libresoc.v:156668$9132 + assign { } { } + assign $0\alu_op__insn_type$2[6:0]$9133 7'0000000 + sync always + sync init + update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9133 + end + attribute \src "libresoc.v:156751.7-156751.36" + process $proc$libresoc.v:156751$9134 + assign { } { } + assign $0\alu_op__invert_in$10[0:0]$9135 1'0 + sync always + sync init + update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9135 + end + attribute \src "libresoc.v:156760.7-156760.37" + process $proc$libresoc.v:156760$9136 + assign { } { } + assign $0\alu_op__invert_out$12[0:0]$9137 1'0 + sync always + sync init + update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9137 + end + attribute \src "libresoc.v:156769.7-156769.35" + process $proc$libresoc.v:156769$9138 + assign { } { } + assign $0\alu_op__is_32bit$16[0:0]$9139 1'0 + sync always + sync init + update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9139 + end + attribute \src "libresoc.v:156778.7-156778.36" + process $proc$libresoc.v:156778$9140 + assign { } { } + assign $0\alu_op__is_signed$17[0:0]$9141 1'0 + sync always + sync init + update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9141 + end + attribute \src "libresoc.v:156789.7-156789.32" + process $proc$libresoc.v:156789$9142 + assign { } { } + assign $0\alu_op__oe__oe$8[0:0]$9143 1'0 + sync always + sync init + update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9143 + end + attribute \src "libresoc.v:156798.7-156798.32" + process $proc$libresoc.v:156798$9144 + assign { } { } + assign $0\alu_op__oe__ok$9[0:0]$9145 1'0 + sync always + sync init + update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9145 + end + attribute \src "libresoc.v:156805.7-156805.39" + process $proc$libresoc.v:156805$9146 + assign { } { } + assign $0\alu_op__output_carry$15[0:0]$9147 1'0 + sync always + sync init + update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9147 + end + attribute \src "libresoc.v:156816.7-156816.32" + process $proc$libresoc.v:156816$9148 + assign { } { } + assign $0\alu_op__rc__ok$7[0:0]$9149 1'0 + sync always + sync init + update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9149 + end + attribute \src "libresoc.v:156823.7-156823.32" + process $proc$libresoc.v:156823$9150 + assign { } { } + assign $0\alu_op__rc__rc$6[0:0]$9151 1'0 + sync always + sync init + update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9151 + end + attribute \src "libresoc.v:156832.7-156832.36" + process $proc$libresoc.v:156832$9152 + assign { } { } + assign $0\alu_op__write_cr0$13[0:0]$9153 1'0 + sync always + sync init + update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9153 + end + attribute \src "libresoc.v:156841.7-156841.33" + process $proc$libresoc.v:156841$9154 + assign { } { } + assign $0\alu_op__zero_a$11[0:0]$9155 1'0 + sync always + sync init + update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9155 + end + attribute \src "libresoc.v:156854.13-156854.29" + process $proc$libresoc.v:156854$9156 + assign { } { } + assign $0\cr_a$22[3:0]$9157 4'0000 + sync always + sync init + update \cr_a$22 $0\cr_a$22[3:0]$9157 + end + attribute \src "libresoc.v:156863.7-156863.26" + process $proc$libresoc.v:156863$9158 + assign { } { } + assign $0\cr_a_ok$23[0:0]$9159 1'0 + sync always + sync init + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9159 + end + attribute \src "libresoc.v:156874.13-156874.29" + process $proc$libresoc.v:156874$9160 + assign { } { } + assign $0\muxid$1[1:0]$9161 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$9161 + end + attribute \src "libresoc.v:156889.14-156889.43" + process $proc$libresoc.v:156889$9162 + assign { } { } + assign $0\o$20[63:0]$9163 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o$20 $0\o$20[63:0]$9163 + end + attribute \src "libresoc.v:156898.7-156898.23" + process $proc$libresoc.v:156898$9164 + assign { } { } + assign $0\o_ok$21[0:0]$9165 1'0 + sync always + sync init + update \o_ok$21 $0\o_ok$21[0:0]$9165 + end + attribute \src "libresoc.v:157202.7-157202.20" + process $proc$libresoc.v:157202$9166 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:157209.13-157209.31" + process $proc$libresoc.v:157209$9167 + assign { } { } + assign $0\xer_ca$24[1:0]$9168 2'00 + sync always + sync init + update \xer_ca$24 $0\xer_ca$24[1:0]$9168 + end + attribute \src "libresoc.v:157218.7-157218.28" + process $proc$libresoc.v:157218$9169 + assign { } { } + assign $0\xer_ca_ok$25[0:0]$9170 1'0 + sync always + sync init + update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9170 + end + attribute \src "libresoc.v:157229.13-157229.31" + process $proc$libresoc.v:157229$9171 + assign { } { } + assign $0\xer_ov$26[1:0]$9172 2'00 + sync always + sync init + update \xer_ov$26 $0\xer_ov$26[1:0]$9172 + end + attribute \src "libresoc.v:157238.7-157238.28" + process $proc$libresoc.v:157238$9173 + assign { } { } + assign $0\xer_ov_ok$27[0:0]$9174 1'0 + sync always + sync init + update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9174 + end + attribute \src "libresoc.v:157249.7-157249.25" + process $proc$libresoc.v:157249$9175 + assign { } { } + assign $0\xer_so$28[0:0]$9176 1'0 + sync always + sync init + update \xer_so$28 $0\xer_so$28[0:0]$9176 + end + attribute \src "libresoc.v:157258.7-157258.28" + process $proc$libresoc.v:157258$9177 + assign { } { } + assign $0\xer_so_ok$29[0:0]$9178 1'0 + sync always + sync init + update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9178 + end + attribute \src "libresoc.v:157266.3-157267.37" + process $proc$libresoc.v:157266$8980 + assign { } { } + assign $0\xer_so$28[0:0]$8981 \xer_so$28$next + sync posedge \coresync_clk + update \xer_so$28 $0\xer_so$28[0:0]$8981 + end + attribute \src "libresoc.v:157268.3-157269.43" + process $proc$libresoc.v:157268$8982 + assign { } { } + assign $0\xer_so_ok$29[0:0]$8983 \xer_so_ok$29$next + sync posedge \coresync_clk + update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$8983 + end + attribute \src "libresoc.v:157270.3-157271.37" + process $proc$libresoc.v:157270$8984 + assign { } { } + assign $0\xer_ov$26[1:0]$8985 \xer_ov$26$next + sync posedge \coresync_clk + update \xer_ov$26 $0\xer_ov$26[1:0]$8985 + end + attribute \src "libresoc.v:157272.3-157273.43" + process $proc$libresoc.v:157272$8986 + assign { } { } + assign $0\xer_ov_ok$27[0:0]$8987 \xer_ov_ok$27$next + sync posedge \coresync_clk + update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$8987 + end + attribute \src "libresoc.v:157274.3-157275.37" + process $proc$libresoc.v:157274$8988 + assign { } { } + assign $0\xer_ca$24[1:0]$8989 \xer_ca$24$next + sync posedge \coresync_clk + update \xer_ca$24 $0\xer_ca$24[1:0]$8989 + end + attribute \src "libresoc.v:157276.3-157277.43" + process $proc$libresoc.v:157276$8990 + assign { } { } + assign $0\xer_ca_ok$25[0:0]$8991 \xer_ca_ok$25$next + sync posedge \coresync_clk + update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$8991 + end + attribute \src "libresoc.v:157278.3-157279.33" + process $proc$libresoc.v:157278$8992 + assign { } { } + assign $0\cr_a$22[3:0]$8993 \cr_a$22$next + sync posedge \coresync_clk + update \cr_a$22 $0\cr_a$22[3:0]$8993 + end + attribute \src "libresoc.v:157280.3-157281.39" + process $proc$libresoc.v:157280$8994 + assign { } { } + assign $0\cr_a_ok$23[0:0]$8995 \cr_a_ok$23$next + sync posedge \coresync_clk + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$8995 + end + attribute \src "libresoc.v:157282.3-157283.27" + process $proc$libresoc.v:157282$8996 + assign { } { } + assign $0\o$20[63:0]$8997 \o$20$next + sync posedge \coresync_clk + update \o$20 $0\o$20[63:0]$8997 + end + attribute \src "libresoc.v:157284.3-157285.33" + process $proc$libresoc.v:157284$8998 + assign { } { } + assign $0\o_ok$21[0:0]$8999 \o_ok$21$next + sync posedge \coresync_clk + update \o_ok$21 $0\o_ok$21[0:0]$8999 + end + attribute \src "libresoc.v:157286.3-157287.57" + process $proc$libresoc.v:157286$9000 + assign { } { } + assign $0\alu_op__insn_type$2[6:0]$9001 \alu_op__insn_type$2$next + sync posedge \coresync_clk + update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9001 + end + attribute \src "libresoc.v:157288.3-157289.53" + process $proc$libresoc.v:157288$9002 + assign { } { } + assign $0\alu_op__fn_unit$3[11:0]$9003 \alu_op__fn_unit$3$next + sync posedge \coresync_clk + update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[11:0]$9003 + end + attribute \src "libresoc.v:157290.3-157291.67" + process $proc$libresoc.v:157290$9004 + assign { } { } + assign $0\alu_op__imm_data__data$4[63:0]$9005 \alu_op__imm_data__data$4$next + sync posedge \coresync_clk + update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9005 + end + attribute \src "libresoc.v:157292.3-157293.63" + process $proc$libresoc.v:157292$9006 + assign { } { } + assign $0\alu_op__imm_data__ok$5[0:0]$9007 \alu_op__imm_data__ok$5$next + sync posedge \coresync_clk + update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9007 + end + attribute \src "libresoc.v:157294.3-157295.51" + process $proc$libresoc.v:157294$9008 + assign { } { } + assign $0\alu_op__rc__rc$6[0:0]$9009 \alu_op__rc__rc$6$next + sync posedge \coresync_clk + update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9009 + end + attribute \src "libresoc.v:157296.3-157297.51" + process $proc$libresoc.v:157296$9010 + assign { } { } + assign $0\alu_op__rc__ok$7[0:0]$9011 \alu_op__rc__ok$7$next + sync posedge \coresync_clk + update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9011 + end + attribute \src "libresoc.v:157298.3-157299.51" + process $proc$libresoc.v:157298$9012 + assign { } { } + assign $0\alu_op__oe__oe$8[0:0]$9013 \alu_op__oe__oe$8$next + sync posedge \coresync_clk + update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9013 + end + attribute \src "libresoc.v:157300.3-157301.51" + process $proc$libresoc.v:157300$9014 + assign { } { } + assign $0\alu_op__oe__ok$9[0:0]$9015 \alu_op__oe__ok$9$next + sync posedge \coresync_clk + update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9015 + end + attribute \src "libresoc.v:157302.3-157303.59" + process $proc$libresoc.v:157302$9016 + assign { } { } + assign $0\alu_op__invert_in$10[0:0]$9017 \alu_op__invert_in$10$next + sync posedge \coresync_clk + update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9017 + end + attribute \src "libresoc.v:157304.3-157305.53" + process $proc$libresoc.v:157304$9018 + assign { } { } + assign $0\alu_op__zero_a$11[0:0]$9019 \alu_op__zero_a$11$next + sync posedge \coresync_clk + update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9019 + end + attribute \src "libresoc.v:157306.3-157307.61" + process $proc$libresoc.v:157306$9020 + assign { } { } + assign $0\alu_op__invert_out$12[0:0]$9021 \alu_op__invert_out$12$next + sync posedge \coresync_clk + update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9021 + end + attribute \src "libresoc.v:157308.3-157309.59" + process $proc$libresoc.v:157308$9022 + assign { } { } + assign $0\alu_op__write_cr0$13[0:0]$9023 \alu_op__write_cr0$13$next + sync posedge \coresync_clk + update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9023 + end + attribute \src "libresoc.v:157310.3-157311.63" + process $proc$libresoc.v:157310$9024 + assign { } { } + assign $0\alu_op__input_carry$14[1:0]$9025 \alu_op__input_carry$14$next + sync posedge \coresync_clk + update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9025 + end + attribute \src "libresoc.v:157312.3-157313.65" + process $proc$libresoc.v:157312$9026 + assign { } { } + assign $0\alu_op__output_carry$15[0:0]$9027 \alu_op__output_carry$15$next + sync posedge \coresync_clk + update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9027 + end + attribute \src "libresoc.v:157314.3-157315.57" + process $proc$libresoc.v:157314$9028 + assign { } { } + assign $0\alu_op__is_32bit$16[0:0]$9029 \alu_op__is_32bit$16$next + sync posedge \coresync_clk + update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9029 + end + attribute \src "libresoc.v:157316.3-157317.59" + process $proc$libresoc.v:157316$9030 + assign { } { } + assign $0\alu_op__is_signed$17[0:0]$9031 \alu_op__is_signed$17$next + sync posedge \coresync_clk + update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9031 + end + attribute \src "libresoc.v:157318.3-157319.57" + process $proc$libresoc.v:157318$9032 + assign { } { } + assign $0\alu_op__data_len$18[3:0]$9033 \alu_op__data_len$18$next + sync posedge \coresync_clk + update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9033 + end + attribute \src "libresoc.v:157320.3-157321.49" + process $proc$libresoc.v:157320$9034 + assign { } { } + assign $0\alu_op__insn$19[31:0]$9035 \alu_op__insn$19$next + sync posedge \coresync_clk + update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9035 + end + attribute \src "libresoc.v:157322.3-157323.33" + process $proc$libresoc.v:157322$9036 + assign { } { } + assign $0\muxid$1[1:0]$9037 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$9037 + end + attribute \src "libresoc.v:157324.3-157325.29" + process $proc$libresoc.v:157324$9038 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:157390.3-157407.6" + process $proc$libresoc.v:157390$9039 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$9040 $2\r_busy$next[0:0]$9042 + attribute \src "libresoc.v:157391.5-157391.29" + switch \initial + attribute \src "libresoc.v:157391.9-157391.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$9041 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$9041 1'0 + case + assign $1\r_busy$next[0:0]$9041 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$9042 1'0 + case + assign $2\r_busy$next[0:0]$9042 $1\r_busy$next[0:0]$9041 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$9040 + end + attribute \src "libresoc.v:157408.3-157420.6" + process $proc$libresoc.v:157408$9043 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$9044 $1\muxid$1$next[1:0]$9045 + attribute \src "libresoc.v:157409.5-157409.29" + switch \initial + attribute \src "libresoc.v:157409.9-157409.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$9045 \muxid$62 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$9045 \muxid$62 + case + assign $1\muxid$1$next[1:0]$9045 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$9044 + end + attribute \src "libresoc.v:157421.3-157462.6" + process $proc$libresoc.v:157421$9046 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_op__data_len$18$next[3:0]$9047 $1\alu_op__data_len$18$next[3:0]$9065 + assign $0\alu_op__fn_unit$3$next[11:0]$9048 $1\alu_op__fn_unit$3$next[11:0]$9066 + assign { } { } + assign { } { } + assign $0\alu_op__input_carry$14$next[1:0]$9051 $1\alu_op__input_carry$14$next[1:0]$9069 + assign $0\alu_op__insn$19$next[31:0]$9052 $1\alu_op__insn$19$next[31:0]$9070 + assign $0\alu_op__insn_type$2$next[6:0]$9053 $1\alu_op__insn_type$2$next[6:0]$9071 + assign $0\alu_op__invert_in$10$next[0:0]$9054 $1\alu_op__invert_in$10$next[0:0]$9072 + assign $0\alu_op__invert_out$12$next[0:0]$9055 $1\alu_op__invert_out$12$next[0:0]$9073 + assign $0\alu_op__is_32bit$16$next[0:0]$9056 $1\alu_op__is_32bit$16$next[0:0]$9074 + assign $0\alu_op__is_signed$17$next[0:0]$9057 $1\alu_op__is_signed$17$next[0:0]$9075 + assign { } { } + assign { } { } + assign $0\alu_op__output_carry$15$next[0:0]$9060 $1\alu_op__output_carry$15$next[0:0]$9078 + assign { } { } + assign { } { } + assign $0\alu_op__write_cr0$13$next[0:0]$9063 $1\alu_op__write_cr0$13$next[0:0]$9081 + assign $0\alu_op__zero_a$11$next[0:0]$9064 $1\alu_op__zero_a$11$next[0:0]$9082 + assign $0\alu_op__imm_data__data$4$next[63:0]$9049 $2\alu_op__imm_data__data$4$next[63:0]$9083 + assign $0\alu_op__imm_data__ok$5$next[0:0]$9050 $2\alu_op__imm_data__ok$5$next[0:0]$9084 + assign $0\alu_op__oe__oe$8$next[0:0]$9058 $2\alu_op__oe__oe$8$next[0:0]$9085 + assign $0\alu_op__oe__ok$9$next[0:0]$9059 $2\alu_op__oe__ok$9$next[0:0]$9086 + assign $0\alu_op__rc__ok$7$next[0:0]$9061 $2\alu_op__rc__ok$7$next[0:0]$9087 + assign $0\alu_op__rc__rc$6$next[0:0]$9062 $2\alu_op__rc__rc$6$next[0:0]$9088 + attribute \src "libresoc.v:157422.5-157422.29" + switch \initial + attribute \src "libresoc.v:157422.9-157422.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_op__insn$19$next[31:0]$9070 $1\alu_op__data_len$18$next[3:0]$9065 $1\alu_op__is_signed$17$next[0:0]$9075 $1\alu_op__is_32bit$16$next[0:0]$9074 $1\alu_op__output_carry$15$next[0:0]$9078 $1\alu_op__input_carry$14$next[1:0]$9069 $1\alu_op__write_cr0$13$next[0:0]$9081 $1\alu_op__invert_out$12$next[0:0]$9073 $1\alu_op__zero_a$11$next[0:0]$9082 $1\alu_op__invert_in$10$next[0:0]$9072 $1\alu_op__oe__ok$9$next[0:0]$9077 $1\alu_op__oe__oe$8$next[0:0]$9076 $1\alu_op__rc__ok$7$next[0:0]$9079 $1\alu_op__rc__rc$6$next[0:0]$9080 $1\alu_op__imm_data__ok$5$next[0:0]$9068 $1\alu_op__imm_data__data$4$next[63:0]$9067 $1\alu_op__fn_unit$3$next[11:0]$9066 $1\alu_op__insn_type$2$next[6:0]$9071 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_op__insn$19$next[31:0]$9070 $1\alu_op__data_len$18$next[3:0]$9065 $1\alu_op__is_signed$17$next[0:0]$9075 $1\alu_op__is_32bit$16$next[0:0]$9074 $1\alu_op__output_carry$15$next[0:0]$9078 $1\alu_op__input_carry$14$next[1:0]$9069 $1\alu_op__write_cr0$13$next[0:0]$9081 $1\alu_op__invert_out$12$next[0:0]$9073 $1\alu_op__zero_a$11$next[0:0]$9082 $1\alu_op__invert_in$10$next[0:0]$9072 $1\alu_op__oe__ok$9$next[0:0]$9077 $1\alu_op__oe__oe$8$next[0:0]$9076 $1\alu_op__rc__ok$7$next[0:0]$9079 $1\alu_op__rc__rc$6$next[0:0]$9080 $1\alu_op__imm_data__ok$5$next[0:0]$9068 $1\alu_op__imm_data__data$4$next[63:0]$9067 $1\alu_op__fn_unit$3$next[11:0]$9066 $1\alu_op__insn_type$2$next[6:0]$9071 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } + case + assign $1\alu_op__data_len$18$next[3:0]$9065 \alu_op__data_len$18 + assign $1\alu_op__fn_unit$3$next[11:0]$9066 \alu_op__fn_unit$3 + assign $1\alu_op__imm_data__data$4$next[63:0]$9067 \alu_op__imm_data__data$4 + assign $1\alu_op__imm_data__ok$5$next[0:0]$9068 \alu_op__imm_data__ok$5 + assign $1\alu_op__input_carry$14$next[1:0]$9069 \alu_op__input_carry$14 + assign $1\alu_op__insn$19$next[31:0]$9070 \alu_op__insn$19 + assign $1\alu_op__insn_type$2$next[6:0]$9071 \alu_op__insn_type$2 + assign $1\alu_op__invert_in$10$next[0:0]$9072 \alu_op__invert_in$10 + assign $1\alu_op__invert_out$12$next[0:0]$9073 \alu_op__invert_out$12 + assign $1\alu_op__is_32bit$16$next[0:0]$9074 \alu_op__is_32bit$16 + assign $1\alu_op__is_signed$17$next[0:0]$9075 \alu_op__is_signed$17 + assign $1\alu_op__oe__oe$8$next[0:0]$9076 \alu_op__oe__oe$8 + assign $1\alu_op__oe__ok$9$next[0:0]$9077 \alu_op__oe__ok$9 + assign $1\alu_op__output_carry$15$next[0:0]$9078 \alu_op__output_carry$15 + assign $1\alu_op__rc__ok$7$next[0:0]$9079 \alu_op__rc__ok$7 + assign $1\alu_op__rc__rc$6$next[0:0]$9080 \alu_op__rc__rc$6 + assign $1\alu_op__write_cr0$13$next[0:0]$9081 \alu_op__write_cr0$13 + assign $1\alu_op__zero_a$11$next[0:0]$9082 \alu_op__zero_a$11 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_op__imm_data__data$4$next[63:0]$9083 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_op__imm_data__ok$5$next[0:0]$9084 1'0 + assign $2\alu_op__rc__rc$6$next[0:0]$9088 1'0 + assign $2\alu_op__rc__ok$7$next[0:0]$9087 1'0 + assign $2\alu_op__oe__oe$8$next[0:0]$9085 1'0 + assign $2\alu_op__oe__ok$9$next[0:0]$9086 1'0 + case + assign $2\alu_op__imm_data__data$4$next[63:0]$9083 $1\alu_op__imm_data__data$4$next[63:0]$9067 + assign $2\alu_op__imm_data__ok$5$next[0:0]$9084 $1\alu_op__imm_data__ok$5$next[0:0]$9068 + assign $2\alu_op__oe__oe$8$next[0:0]$9085 $1\alu_op__oe__oe$8$next[0:0]$9076 + assign $2\alu_op__oe__ok$9$next[0:0]$9086 $1\alu_op__oe__ok$9$next[0:0]$9077 + assign $2\alu_op__rc__ok$7$next[0:0]$9087 $1\alu_op__rc__ok$7$next[0:0]$9079 + assign $2\alu_op__rc__rc$6$next[0:0]$9088 $1\alu_op__rc__rc$6$next[0:0]$9080 + end + sync always + update \alu_op__data_len$18$next $0\alu_op__data_len$18$next[3:0]$9047 + update \alu_op__fn_unit$3$next $0\alu_op__fn_unit$3$next[11:0]$9048 + update \alu_op__imm_data__data$4$next $0\alu_op__imm_data__data$4$next[63:0]$9049 + update \alu_op__imm_data__ok$5$next $0\alu_op__imm_data__ok$5$next[0:0]$9050 + update \alu_op__input_carry$14$next $0\alu_op__input_carry$14$next[1:0]$9051 + update \alu_op__insn$19$next $0\alu_op__insn$19$next[31:0]$9052 + update \alu_op__insn_type$2$next $0\alu_op__insn_type$2$next[6:0]$9053 + update \alu_op__invert_in$10$next $0\alu_op__invert_in$10$next[0:0]$9054 + update \alu_op__invert_out$12$next $0\alu_op__invert_out$12$next[0:0]$9055 + update \alu_op__is_32bit$16$next $0\alu_op__is_32bit$16$next[0:0]$9056 + update \alu_op__is_signed$17$next $0\alu_op__is_signed$17$next[0:0]$9057 + update \alu_op__oe__oe$8$next $0\alu_op__oe__oe$8$next[0:0]$9058 + update \alu_op__oe__ok$9$next $0\alu_op__oe__ok$9$next[0:0]$9059 + update \alu_op__output_carry$15$next $0\alu_op__output_carry$15$next[0:0]$9060 + update \alu_op__rc__ok$7$next $0\alu_op__rc__ok$7$next[0:0]$9061 + update \alu_op__rc__rc$6$next $0\alu_op__rc__rc$6$next[0:0]$9062 + update \alu_op__write_cr0$13$next $0\alu_op__write_cr0$13$next[0:0]$9063 + update \alu_op__zero_a$11$next $0\alu_op__zero_a$11$next[0:0]$9064 + end + attribute \src "libresoc.v:157463.3-157481.6" + process $proc$libresoc.v:157463$9089 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$20$next[63:0]$9090 $1\o$20$next[63:0]$9092 + assign { } { } + assign $0\o_ok$21$next[0:0]$9091 $2\o_ok$21$next[0:0]$9094 + attribute \src "libresoc.v:157464.5-157464.29" + switch \initial + attribute \src "libresoc.v:157464.9-157464.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$21$next[0:0]$9093 $1\o$20$next[63:0]$9092 } { \o_ok$82 \o$81 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$21$next[0:0]$9093 $1\o$20$next[63:0]$9092 } { \o_ok$82 \o$81 } + case + assign $1\o$20$next[63:0]$9092 \o$20 + assign $1\o_ok$21$next[0:0]$9093 \o_ok$21 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$21$next[0:0]$9094 1'0 + case + assign $2\o_ok$21$next[0:0]$9094 $1\o_ok$21$next[0:0]$9093 + end + sync always + update \o$20$next $0\o$20$next[63:0]$9090 + update \o_ok$21$next $0\o_ok$21$next[0:0]$9091 + end + attribute \src "libresoc.v:157482.3-157500.6" + process $proc$libresoc.v:157482$9095 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$22$next[3:0]$9096 $1\cr_a$22$next[3:0]$9098 + assign { } { } + assign $0\cr_a_ok$23$next[0:0]$9097 $2\cr_a_ok$23$next[0:0]$9100 + attribute \src "libresoc.v:157483.5-157483.29" + switch \initial + attribute \src "libresoc.v:157483.9-157483.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$23$next[0:0]$9099 $1\cr_a$22$next[3:0]$9098 } { \cr_a_ok$84 \cr_a$83 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$23$next[0:0]$9099 $1\cr_a$22$next[3:0]$9098 } { \cr_a_ok$84 \cr_a$83 } + case + assign $1\cr_a$22$next[3:0]$9098 \cr_a$22 + assign $1\cr_a_ok$23$next[0:0]$9099 \cr_a_ok$23 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$23$next[0:0]$9100 1'0 + case + assign $2\cr_a_ok$23$next[0:0]$9100 $1\cr_a_ok$23$next[0:0]$9099 + end + sync always + update \cr_a$22$next $0\cr_a$22$next[3:0]$9096 + update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$9097 + end + attribute \src "libresoc.v:157501.3-157519.6" + process $proc$libresoc.v:157501$9101 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ca$24$next[1:0]$9102 $1\xer_ca$24$next[1:0]$9104 + assign { } { } + assign $0\xer_ca_ok$25$next[0:0]$9103 $2\xer_ca_ok$25$next[0:0]$9106 + attribute \src "libresoc.v:157502.5-157502.29" + switch \initial + attribute \src "libresoc.v:157502.9-157502.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$25$next[0:0]$9105 $1\xer_ca$24$next[1:0]$9104 } { \xer_ca_ok$86 \xer_ca$85 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$25$next[0:0]$9105 $1\xer_ca$24$next[1:0]$9104 } { \xer_ca_ok$86 \xer_ca$85 } + case + assign $1\xer_ca$24$next[1:0]$9104 \xer_ca$24 + assign $1\xer_ca_ok$25$next[0:0]$9105 \xer_ca_ok$25 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ca_ok$25$next[0:0]$9106 1'0 + case + assign $2\xer_ca_ok$25$next[0:0]$9106 $1\xer_ca_ok$25$next[0:0]$9105 + end + sync always + update \xer_ca$24$next $0\xer_ca$24$next[1:0]$9102 + update \xer_ca_ok$25$next $0\xer_ca_ok$25$next[0:0]$9103 + end + attribute \src "libresoc.v:157520.3-157538.6" + process $proc$libresoc.v:157520$9107 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ov$26$next[1:0]$9108 $1\xer_ov$26$next[1:0]$9110 + assign { } { } + assign $0\xer_ov_ok$27$next[0:0]$9109 $2\xer_ov_ok$27$next[0:0]$9112 + attribute \src "libresoc.v:157521.5-157521.29" + switch \initial + attribute \src "libresoc.v:157521.9-157521.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$27$next[0:0]$9111 $1\xer_ov$26$next[1:0]$9110 } { \xer_ov_ok$88 \xer_ov$87 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$27$next[0:0]$9111 $1\xer_ov$26$next[1:0]$9110 } { \xer_ov_ok$88 \xer_ov$87 } + case + assign $1\xer_ov$26$next[1:0]$9110 \xer_ov$26 + assign $1\xer_ov_ok$27$next[0:0]$9111 \xer_ov_ok$27 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ov_ok$27$next[0:0]$9112 1'0 + case + assign $2\xer_ov_ok$27$next[0:0]$9112 $1\xer_ov_ok$27$next[0:0]$9111 + end + sync always + update \xer_ov$26$next $0\xer_ov$26$next[1:0]$9108 + update \xer_ov_ok$27$next $0\xer_ov_ok$27$next[0:0]$9109 + end + attribute \src "libresoc.v:157539.3-157557.6" + process $proc$libresoc.v:157539$9113 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$28$next[0:0]$9114 $1\xer_so$28$next[0:0]$9116 + assign { } { } + assign $0\xer_so_ok$29$next[0:0]$9115 $2\xer_so_ok$29$next[0:0]$9118 + attribute \src "libresoc.v:157540.5-157540.29" + switch \initial + attribute \src "libresoc.v:157540.9-157540.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$29$next[0:0]$9117 $1\xer_so$28$next[0:0]$9116 } { \xer_so_ok$90 \xer_so$89 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$29$next[0:0]$9117 $1\xer_so$28$next[0:0]$9116 } { \xer_so_ok$90 \xer_so$89 } + case + assign $1\xer_so$28$next[0:0]$9116 \xer_so$28 + assign $1\xer_so_ok$29$next[0:0]$9117 \xer_so_ok$29 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$29$next[0:0]$9118 1'0 + case + assign $2\xer_so_ok$29$next[0:0]$9118 $1\xer_so_ok$29$next[0:0]$9117 + end + sync always + update \xer_so$28$next $0\xer_so$28$next[0:0]$9114 + update \xer_so_ok$29$next $0\xer_so_ok$29$next[0:0]$9115 + end + connect \$60 $and$libresoc.v:157265$8979_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_so_ok$90 \xer_so$89 } { \output_xer_so_ok \output_xer_so$54 } + connect { \xer_ov_ok$88 \xer_ov$87 } { \output_xer_ov_ok \output_xer_ov$53 } + connect { \xer_ca_ok$86 \xer_ca$85 } { \output_xer_ca_ok \output_xer_ca$52 } + connect { \cr_a_ok$84 \cr_a$83 } { \output_cr_a_ok \output_cr_a$51 } + connect { \o_ok$82 \o$81 } { \output_o_ok$50 \output_o$49 } + connect { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } { \output_alu_op__insn$48 \output_alu_op__data_len$47 \output_alu_op__is_signed$46 \output_alu_op__is_32bit$45 \output_alu_op__output_carry$44 \output_alu_op__input_carry$43 \output_alu_op__write_cr0$42 \output_alu_op__invert_out$41 \output_alu_op__zero_a$40 \output_alu_op__invert_in$39 \output_alu_op__oe__ok$38 \output_alu_op__oe__oe$37 \output_alu_op__rc__ok$36 \output_alu_op__rc__rc$35 \output_alu_op__imm_data__ok$34 \output_alu_op__imm_data__data$33 \output_alu_op__fn_unit$32 \output_alu_op__insn_type$31 } + connect \muxid$62 \output_muxid$30 + connect \p_valid_i_p_ready_o \$60 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$59 \p_valid_i + connect { \xer_so_ok$58 \output_xer_so } { \xer_so_ok \xer_so } + connect { \xer_ov_ok$57 \output_xer_ov } { \xer_ov_ok \xer_ov } + connect { \xer_ca_ok$56 \output_xer_ca } { \xer_ca_ok \xer_ca } + connect { \cr_a_ok$55 \output_cr_a } { \cr_a_ok \cr_a } + connect { \output_o_ok \output_o } { \o_ok \o } + connect { \output_alu_op__insn \output_alu_op__data_len \output_alu_op__is_signed \output_alu_op__is_32bit \output_alu_op__output_carry \output_alu_op__input_carry \output_alu_op__write_cr0 \output_alu_op__invert_out \output_alu_op__zero_a \output_alu_op__invert_in \output_alu_op__oe__ok \output_alu_op__oe__oe \output_alu_op__rc__ok \output_alu_op__rc__rc \output_alu_op__imm_data__ok \output_alu_op__imm_data__data \output_alu_op__fn_unit \output_alu_op__insn_type } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } + connect \output_muxid \muxid +end +attribute \src "libresoc.v:157581.1-158635.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2" +attribute \generator "nMigen" +module \pipe2$115 + attribute \src "libresoc.v:158581.3-158599.6" + wire width 4 $0\cr_a$21$next[3:0]$9284 + attribute \src "libresoc.v:158387.3-158388.33" + wire width 4 $0\cr_a$21[3:0]$9185 + attribute \src "libresoc.v:157593.13-157593.29" + wire width 4 $0\cr_a$21[3:0]$9297 + attribute \src "libresoc.v:158581.3-158599.6" + wire $0\cr_a_ok$22$next[0:0]$9285 + attribute \src "libresoc.v:158389.3-158390.39" + wire $0\cr_a_ok$22[0:0]$9187 + attribute \src "libresoc.v:157602.7-157602.26" + wire $0\cr_a_ok$22[0:0]$9299 + attribute \src "libresoc.v:157582.7-157582.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:158508.3-158520.6" + wire width 2 $0\muxid$1$next[1:0]$9234 + attribute \src "libresoc.v:158429.3-158430.33" + wire width 2 $0\muxid$1[1:0]$9227 + attribute \src "libresoc.v:157613.13-157613.29" + wire width 2 $0\muxid$1[1:0]$9301 + attribute \src "libresoc.v:158562.3-158580.6" + wire width 64 $0\o$19$next[63:0]$9278 + attribute \src "libresoc.v:158391.3-158392.27" + wire width 64 $0\o$19[63:0]$9189 + attribute \src "libresoc.v:157628.14-157628.43" + wire width 64 $0\o$19[63:0]$9303 + attribute \src "libresoc.v:158562.3-158580.6" + wire $0\o_ok$20$next[0:0]$9279 + attribute \src "libresoc.v:158393.3-158394.33" + wire $0\o_ok$20[0:0]$9191 + attribute \src "libresoc.v:157637.7-157637.23" + wire $0\o_ok$20[0:0]$9305 + attribute \src "libresoc.v:158490.3-158507.6" + wire $0\r_busy$next[0:0]$9230 + attribute \src "libresoc.v:158431.3-158432.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:158521.3-158561.6" + wire width 12 $0\sr_op__fn_unit$3$next[11:0]$9237 + attribute \src "libresoc.v:158397.3-158398.51" + wire width 12 $0\sr_op__fn_unit$3[11:0]$9195 + attribute \src "libresoc.v:157960.14-157960.42" + wire width 12 $0\sr_op__fn_unit$3[11:0]$9308 + attribute \src "libresoc.v:158521.3-158561.6" + wire width 64 $0\sr_op__imm_data__data$4$next[63:0]$9238 + attribute \src "libresoc.v:158399.3-158400.65" + wire width 64 $0\sr_op__imm_data__data$4[63:0]$9197 + attribute \src "libresoc.v:157982.14-157982.62" + wire width 64 $0\sr_op__imm_data__data$4[63:0]$9310 + attribute \src "libresoc.v:158521.3-158561.6" + wire $0\sr_op__imm_data__ok$5$next[0:0]$9239 + attribute \src "libresoc.v:158401.3-158402.61" + wire $0\sr_op__imm_data__ok$5[0:0]$9199 + attribute \src "libresoc.v:157991.7-157991.37" + wire $0\sr_op__imm_data__ok$5[0:0]$9312 + attribute \src "libresoc.v:158521.3-158561.6" + wire width 2 $0\sr_op__input_carry$12$next[1:0]$9240 + attribute \src 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\enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_sr_op__insn_type$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__invert_in$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__is_32bit$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__is_signed$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__oe__oe$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__oe__ok$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__output_carry$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__output_cr$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__rc__ok$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__rc__rc$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__write_cr0$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ca$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$50 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 6 \sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 34 \sr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \sr_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \sr_op__fn_unit$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 35 \sr_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__data$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__data$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \sr_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__imm_data__ok$57 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 15 \sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 43 \sr_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \sr_op__input_carry$12$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \sr_op__input_carry$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 45 \sr_op__input_cr$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__input_cr$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__input_cr$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 21 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 49 \sr_op__insn$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$70 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 33 \sr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \sr_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \sr_op__insn_type$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \sr_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 42 \sr_op__invert_in$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__invert_in$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__invert_in$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 47 \sr_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_32bit$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 48 \sr_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_signed$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__oe$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \sr_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__ok$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \sr_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 44 \sr_op__output_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_carry$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_carry$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 46 \sr_op__output_cr$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_cr$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_cr$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__ok$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \sr_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__rc$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \sr_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \sr_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__write_cr0$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__write_cr0$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 input 28 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 54 \xer_ca$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 29 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 55 \xer_ca_ok$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 26 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 27 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$48 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$libresoc.v:158382$9179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$50 + connect \B \p_ready_o + connect \Y $and$libresoc.v:158382$9179_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:158433.11-158436.4" + cell \n$117 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:158437.16-158485.4" + cell \output$118 \output + connect \cr_a \output_cr_a + connect \cr_a$21 \output_cr_a$45 + connect \cr_a_ok \output_cr_a_ok + connect \muxid \output_muxid + connect \muxid$1 \output_muxid$25 + connect \o \output_o + connect \o$19 \output_o$43 + connect \o_ok \output_o_ok + connect \o_ok$20 \output_o_ok$44 + connect \sr_op__fn_unit \output_sr_op__fn_unit + connect \sr_op__fn_unit$3 \output_sr_op__fn_unit$27 + connect \sr_op__imm_data__data \output_sr_op__imm_data__data + connect \sr_op__imm_data__data$4 \output_sr_op__imm_data__data$28 + connect \sr_op__imm_data__ok \output_sr_op__imm_data__ok + connect \sr_op__imm_data__ok$5 \output_sr_op__imm_data__ok$29 + connect \sr_op__input_carry \output_sr_op__input_carry + connect \sr_op__input_carry$12 \output_sr_op__input_carry$36 + connect \sr_op__input_cr \output_sr_op__input_cr + connect \sr_op__input_cr$14 \output_sr_op__input_cr$38 + connect \sr_op__insn \output_sr_op__insn + connect \sr_op__insn$18 \output_sr_op__insn$42 + connect \sr_op__insn_type \output_sr_op__insn_type + connect \sr_op__insn_type$2 \output_sr_op__insn_type$26 + connect \sr_op__invert_in \output_sr_op__invert_in + connect \sr_op__invert_in$11 \output_sr_op__invert_in$35 + connect \sr_op__is_32bit \output_sr_op__is_32bit + connect \sr_op__is_32bit$16 \output_sr_op__is_32bit$40 + connect \sr_op__is_signed \output_sr_op__is_signed + connect \sr_op__is_signed$17 \output_sr_op__is_signed$41 + connect \sr_op__oe__oe \output_sr_op__oe__oe + connect \sr_op__oe__oe$8 \output_sr_op__oe__oe$32 + connect \sr_op__oe__ok \output_sr_op__oe__ok + connect \sr_op__oe__ok$9 \output_sr_op__oe__ok$33 + connect \sr_op__output_carry \output_sr_op__output_carry + connect \sr_op__output_carry$13 \output_sr_op__output_carry$37 + connect \sr_op__output_cr \output_sr_op__output_cr + connect \sr_op__output_cr$15 \output_sr_op__output_cr$39 + connect \sr_op__rc__ok \output_sr_op__rc__ok + connect \sr_op__rc__ok$7 \output_sr_op__rc__ok$31 + connect \sr_op__rc__rc \output_sr_op__rc__rc + connect \sr_op__rc__rc$6 \output_sr_op__rc__rc$30 + connect \sr_op__write_cr0 \output_sr_op__write_cr0 + connect \sr_op__write_cr0$10 \output_sr_op__write_cr0$34 + connect \xer_ca \output_xer_ca + connect \xer_ca$22 \output_xer_ca$46 + connect \xer_ca_ok \output_xer_ca_ok + connect \xer_so \output_xer_so + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:158486.11-158489.4" + cell \p$116 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:157582.7-157582.20" + process $proc$libresoc.v:157582$9295 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:157593.13-157593.29" + process $proc$libresoc.v:157593$9296 + assign { } { } + assign $0\cr_a$21[3:0]$9297 4'0000 + sync always + sync init + update \cr_a$21 $0\cr_a$21[3:0]$9297 + end + attribute \src "libresoc.v:157602.7-157602.26" + process $proc$libresoc.v:157602$9298 + assign { } { } + assign $0\cr_a_ok$22[0:0]$9299 1'0 + sync always + sync init + update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9299 + end + attribute \src "libresoc.v:157613.13-157613.29" + process $proc$libresoc.v:157613$9300 + assign { } { } + assign $0\muxid$1[1:0]$9301 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$9301 + end + attribute \src "libresoc.v:157628.14-157628.43" + process $proc$libresoc.v:157628$9302 + assign { } { } + assign $0\o$19[63:0]$9303 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o$19 $0\o$19[63:0]$9303 + end + attribute \src "libresoc.v:157637.7-157637.23" + process $proc$libresoc.v:157637$9304 + assign { } { } + assign $0\o_ok$20[0:0]$9305 1'0 + sync always + sync init + update \o_ok$20 $0\o_ok$20[0:0]$9305 + end + attribute \src "libresoc.v:157927.7-157927.20" + process $proc$libresoc.v:157927$9306 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:157960.14-157960.42" + process $proc$libresoc.v:157960$9307 + assign { } { } + assign $0\sr_op__fn_unit$3[11:0]$9308 12'000000000000 + sync always + sync init + update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[11:0]$9308 + end + attribute \src "libresoc.v:157982.14-157982.62" + process $proc$libresoc.v:157982$9309 + assign { } { } + assign $0\sr_op__imm_data__data$4[63:0]$9310 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9310 + end + attribute \src "libresoc.v:157991.7-157991.37" + process $proc$libresoc.v:157991$9311 + assign { } { } + assign $0\sr_op__imm_data__ok$5[0:0]$9312 1'0 + sync always + sync init + update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9312 + end + attribute \src "libresoc.v:158008.13-158008.43" + process $proc$libresoc.v:158008$9313 + assign { } { } + assign $0\sr_op__input_carry$12[1:0]$9314 2'00 + sync always + sync init + update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9314 + end + attribute \src "libresoc.v:158021.7-158021.34" + process $proc$libresoc.v:158021$9315 + assign { } { } + assign $0\sr_op__input_cr$14[0:0]$9316 1'0 + sync always + sync init + update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9316 + end + attribute \src "libresoc.v:158030.14-158030.38" + process $proc$libresoc.v:158030$9317 + assign { } { } + assign $0\sr_op__insn$18[31:0]$9318 0 + sync always + sync init + update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9318 + end + attribute \src "libresoc.v:158187.13-158187.41" + process $proc$libresoc.v:158187$9319 + assign { } { } + assign $0\sr_op__insn_type$2[6:0]$9320 7'0000000 + sync always + sync init + update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9320 + end + attribute \src "libresoc.v:158270.7-158270.35" + process $proc$libresoc.v:158270$9321 + assign { } { } + assign $0\sr_op__invert_in$11[0:0]$9322 1'0 + sync always + sync init + update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9322 + end + attribute \src "libresoc.v:158279.7-158279.34" + process $proc$libresoc.v:158279$9323 + assign { } { } + assign $0\sr_op__is_32bit$16[0:0]$9324 1'0 + sync always + sync init + update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9324 + end + attribute \src "libresoc.v:158288.7-158288.35" + process $proc$libresoc.v:158288$9325 + assign { } { } + assign $0\sr_op__is_signed$17[0:0]$9326 1'0 + sync always + sync init + update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9326 + end + attribute \src "libresoc.v:158299.7-158299.31" + process $proc$libresoc.v:158299$9327 + assign { } { } + assign $0\sr_op__oe__oe$8[0:0]$9328 1'0 + sync always + sync init + update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9328 + end + attribute \src "libresoc.v:158308.7-158308.31" + process $proc$libresoc.v:158308$9329 + assign { } { } + assign $0\sr_op__oe__ok$9[0:0]$9330 1'0 + sync always + sync init + update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9330 + end + attribute \src "libresoc.v:158315.7-158315.38" + process $proc$libresoc.v:158315$9331 + assign { } { } + assign $0\sr_op__output_carry$13[0:0]$9332 1'0 + sync always + sync init + update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9332 + end + attribute \src "libresoc.v:158324.7-158324.35" + process $proc$libresoc.v:158324$9333 + assign { } { } + assign $0\sr_op__output_cr$15[0:0]$9334 1'0 + sync always + sync init + update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9334 + end + attribute \src "libresoc.v:158335.7-158335.31" + process $proc$libresoc.v:158335$9335 + assign { } { } + assign $0\sr_op__rc__ok$7[0:0]$9336 1'0 + sync always + sync init + update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9336 + end + attribute \src "libresoc.v:158344.7-158344.31" + process $proc$libresoc.v:158344$9337 + assign { } { } + assign $0\sr_op__rc__rc$6[0:0]$9338 1'0 + sync always + sync init + update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9338 + end + attribute \src "libresoc.v:158351.7-158351.35" + process $proc$libresoc.v:158351$9339 + assign { } { } + assign $0\sr_op__write_cr0$10[0:0]$9340 1'0 + sync always + sync init + update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9340 + end + attribute \src "libresoc.v:158360.13-158360.31" + process $proc$libresoc.v:158360$9341 + assign { } { } + assign $0\xer_ca$23[1:0]$9342 2'00 + sync always + sync init + update \xer_ca$23 $0\xer_ca$23[1:0]$9342 + end + attribute \src "libresoc.v:158369.7-158369.28" + process $proc$libresoc.v:158369$9343 + assign { } { } + assign $0\xer_ca_ok$24[0:0]$9344 1'0 + sync always + sync init + update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9344 + end + attribute \src "libresoc.v:158383.3-158384.37" + process $proc$libresoc.v:158383$9180 + assign { } { } + assign $0\xer_ca$23[1:0]$9181 \xer_ca$23$next + sync posedge \coresync_clk + update \xer_ca$23 $0\xer_ca$23[1:0]$9181 + end + attribute \src "libresoc.v:158385.3-158386.43" + process $proc$libresoc.v:158385$9182 + assign { } { } + assign $0\xer_ca_ok$24[0:0]$9183 \xer_ca_ok$24$next + sync posedge \coresync_clk + update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9183 + end + attribute \src "libresoc.v:158387.3-158388.33" + process $proc$libresoc.v:158387$9184 + assign { } { } + assign $0\cr_a$21[3:0]$9185 \cr_a$21$next + sync posedge \coresync_clk + update \cr_a$21 $0\cr_a$21[3:0]$9185 + end + attribute \src "libresoc.v:158389.3-158390.39" + process $proc$libresoc.v:158389$9186 + assign { } { } + assign $0\cr_a_ok$22[0:0]$9187 \cr_a_ok$22$next + sync posedge \coresync_clk + update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9187 + end + attribute \src "libresoc.v:158391.3-158392.27" + process $proc$libresoc.v:158391$9188 + assign { } { } + assign $0\o$19[63:0]$9189 \o$19$next + sync posedge \coresync_clk + update \o$19 $0\o$19[63:0]$9189 + end + attribute \src "libresoc.v:158393.3-158394.33" + process $proc$libresoc.v:158393$9190 + assign { } { } + assign $0\o_ok$20[0:0]$9191 \o_ok$20$next + sync posedge \coresync_clk + update \o_ok$20 $0\o_ok$20[0:0]$9191 + end + attribute \src "libresoc.v:158395.3-158396.55" + process $proc$libresoc.v:158395$9192 + assign { } { } + assign $0\sr_op__insn_type$2[6:0]$9193 \sr_op__insn_type$2$next + sync posedge \coresync_clk + update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9193 + end + attribute \src "libresoc.v:158397.3-158398.51" + process $proc$libresoc.v:158397$9194 + assign { } { } + assign $0\sr_op__fn_unit$3[11:0]$9195 \sr_op__fn_unit$3$next + sync posedge \coresync_clk + update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[11:0]$9195 + end + attribute \src "libresoc.v:158399.3-158400.65" + process $proc$libresoc.v:158399$9196 + assign { } { } + assign $0\sr_op__imm_data__data$4[63:0]$9197 \sr_op__imm_data__data$4$next + sync posedge \coresync_clk + update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9197 + end + attribute \src "libresoc.v:158401.3-158402.61" + process $proc$libresoc.v:158401$9198 + assign { } { } + assign $0\sr_op__imm_data__ok$5[0:0]$9199 \sr_op__imm_data__ok$5$next + sync posedge \coresync_clk + update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9199 + end + attribute \src "libresoc.v:158403.3-158404.49" + process $proc$libresoc.v:158403$9200 + assign { } { } + assign $0\sr_op__rc__rc$6[0:0]$9201 \sr_op__rc__rc$6$next + sync posedge \coresync_clk + update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9201 + end + attribute \src "libresoc.v:158405.3-158406.49" + process $proc$libresoc.v:158405$9202 + assign { } { } + assign $0\sr_op__rc__ok$7[0:0]$9203 \sr_op__rc__ok$7$next + sync posedge \coresync_clk + update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9203 + end + attribute \src "libresoc.v:158407.3-158408.49" + process $proc$libresoc.v:158407$9204 + assign { } { } + assign $0\sr_op__oe__oe$8[0:0]$9205 \sr_op__oe__oe$8$next + sync posedge \coresync_clk + update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9205 + end + attribute \src "libresoc.v:158409.3-158410.49" + process $proc$libresoc.v:158409$9206 + assign { } { } + assign $0\sr_op__oe__ok$9[0:0]$9207 \sr_op__oe__ok$9$next + sync posedge \coresync_clk + update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9207 + end + attribute \src "libresoc.v:158411.3-158412.57" + process $proc$libresoc.v:158411$9208 + assign { } { } + assign $0\sr_op__write_cr0$10[0:0]$9209 \sr_op__write_cr0$10$next + sync posedge \coresync_clk + update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9209 + end + attribute \src "libresoc.v:158413.3-158414.57" + process $proc$libresoc.v:158413$9210 + assign { } { } + assign $0\sr_op__invert_in$11[0:0]$9211 \sr_op__invert_in$11$next + sync posedge \coresync_clk + update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9211 + end + attribute \src "libresoc.v:158415.3-158416.61" + process $proc$libresoc.v:158415$9212 + assign { } { } + assign $0\sr_op__input_carry$12[1:0]$9213 \sr_op__input_carry$12$next + sync posedge \coresync_clk + update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9213 + end + attribute \src "libresoc.v:158417.3-158418.63" + process $proc$libresoc.v:158417$9214 + assign { } { } + assign $0\sr_op__output_carry$13[0:0]$9215 \sr_op__output_carry$13$next + sync posedge \coresync_clk + update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9215 + end + attribute \src "libresoc.v:158419.3-158420.55" + process $proc$libresoc.v:158419$9216 + assign { } { } + assign $0\sr_op__input_cr$14[0:0]$9217 \sr_op__input_cr$14$next + sync posedge \coresync_clk + update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9217 + end + attribute \src "libresoc.v:158421.3-158422.57" + process $proc$libresoc.v:158421$9218 + assign { } { } + assign $0\sr_op__output_cr$15[0:0]$9219 \sr_op__output_cr$15$next + sync posedge \coresync_clk + update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9219 + end + attribute \src "libresoc.v:158423.3-158424.55" + process $proc$libresoc.v:158423$9220 + assign { } { } + assign $0\sr_op__is_32bit$16[0:0]$9221 \sr_op__is_32bit$16$next + sync posedge \coresync_clk + update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9221 + end + attribute \src "libresoc.v:158425.3-158426.57" + process $proc$libresoc.v:158425$9222 + assign { } { } + assign $0\sr_op__is_signed$17[0:0]$9223 \sr_op__is_signed$17$next + sync posedge \coresync_clk + update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9223 + end + attribute \src "libresoc.v:158427.3-158428.47" + process $proc$libresoc.v:158427$9224 + assign { } { } + assign $0\sr_op__insn$18[31:0]$9225 \sr_op__insn$18$next + sync posedge \coresync_clk + update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9225 + end + attribute \src "libresoc.v:158429.3-158430.33" + process $proc$libresoc.v:158429$9226 + assign { } { } + assign $0\muxid$1[1:0]$9227 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$9227 + end + attribute \src "libresoc.v:158431.3-158432.29" + process $proc$libresoc.v:158431$9228 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:158490.3-158507.6" + process $proc$libresoc.v:158490$9229 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$9230 $2\r_busy$next[0:0]$9232 + attribute \src "libresoc.v:158491.5-158491.29" + switch \initial + attribute \src "libresoc.v:158491.9-158491.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$9231 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$9231 1'0 + case + assign $1\r_busy$next[0:0]$9231 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$9232 1'0 + case + assign $2\r_busy$next[0:0]$9232 $1\r_busy$next[0:0]$9231 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$9230 + end + attribute \src "libresoc.v:158508.3-158520.6" + process $proc$libresoc.v:158508$9233 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$9234 $1\muxid$1$next[1:0]$9235 + attribute \src "libresoc.v:158509.5-158509.29" + switch \initial + attribute \src "libresoc.v:158509.9-158509.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$9235 \muxid$53 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$9235 \muxid$53 + case + assign $1\muxid$1$next[1:0]$9235 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$9234 + end + attribute \src "libresoc.v:158521.3-158561.6" + process $proc$libresoc.v:158521$9236 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sr_op__fn_unit$3$next[11:0]$9237 $1\sr_op__fn_unit$3$next[11:0]$9254 + assign { } { } + assign { } { } + assign $0\sr_op__input_carry$12$next[1:0]$9240 $1\sr_op__input_carry$12$next[1:0]$9257 + assign $0\sr_op__input_cr$14$next[0:0]$9241 $1\sr_op__input_cr$14$next[0:0]$9258 + assign $0\sr_op__insn$18$next[31:0]$9242 $1\sr_op__insn$18$next[31:0]$9259 + assign $0\sr_op__insn_type$2$next[6:0]$9243 $1\sr_op__insn_type$2$next[6:0]$9260 + assign $0\sr_op__invert_in$11$next[0:0]$9244 $1\sr_op__invert_in$11$next[0:0]$9261 + assign $0\sr_op__is_32bit$16$next[0:0]$9245 $1\sr_op__is_32bit$16$next[0:0]$9262 + assign $0\sr_op__is_signed$17$next[0:0]$9246 $1\sr_op__is_signed$17$next[0:0]$9263 + assign { } { } + assign { } { } + assign $0\sr_op__output_carry$13$next[0:0]$9249 $1\sr_op__output_carry$13$next[0:0]$9266 + assign $0\sr_op__output_cr$15$next[0:0]$9250 $1\sr_op__output_cr$15$next[0:0]$9267 + assign { } { } + assign { } { } + assign $0\sr_op__write_cr0$10$next[0:0]$9253 $1\sr_op__write_cr0$10$next[0:0]$9270 + assign $0\sr_op__imm_data__data$4$next[63:0]$9238 $2\sr_op__imm_data__data$4$next[63:0]$9271 + assign $0\sr_op__imm_data__ok$5$next[0:0]$9239 $2\sr_op__imm_data__ok$5$next[0:0]$9272 + assign $0\sr_op__oe__oe$8$next[0:0]$9247 $2\sr_op__oe__oe$8$next[0:0]$9273 + assign $0\sr_op__oe__ok$9$next[0:0]$9248 $2\sr_op__oe__ok$9$next[0:0]$9274 + assign $0\sr_op__rc__ok$7$next[0:0]$9251 $2\sr_op__rc__ok$7$next[0:0]$9275 + assign $0\sr_op__rc__rc$6$next[0:0]$9252 $2\sr_op__rc__rc$6$next[0:0]$9276 + attribute \src "libresoc.v:158522.5-158522.29" + switch \initial + attribute \src "libresoc.v:158522.9-158522.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\sr_op__insn$18$next[31:0]$9259 $1\sr_op__is_signed$17$next[0:0]$9263 $1\sr_op__is_32bit$16$next[0:0]$9262 $1\sr_op__output_cr$15$next[0:0]$9267 $1\sr_op__input_cr$14$next[0:0]$9258 $1\sr_op__output_carry$13$next[0:0]$9266 $1\sr_op__input_carry$12$next[1:0]$9257 $1\sr_op__invert_in$11$next[0:0]$9261 $1\sr_op__write_cr0$10$next[0:0]$9270 $1\sr_op__oe__ok$9$next[0:0]$9265 $1\sr_op__oe__oe$8$next[0:0]$9264 $1\sr_op__rc__ok$7$next[0:0]$9268 $1\sr_op__rc__rc$6$next[0:0]$9269 $1\sr_op__imm_data__ok$5$next[0:0]$9256 $1\sr_op__imm_data__data$4$next[63:0]$9255 $1\sr_op__fn_unit$3$next[11:0]$9254 $1\sr_op__insn_type$2$next[6:0]$9260 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\sr_op__insn$18$next[31:0]$9259 $1\sr_op__is_signed$17$next[0:0]$9263 $1\sr_op__is_32bit$16$next[0:0]$9262 $1\sr_op__output_cr$15$next[0:0]$9267 $1\sr_op__input_cr$14$next[0:0]$9258 $1\sr_op__output_carry$13$next[0:0]$9266 $1\sr_op__input_carry$12$next[1:0]$9257 $1\sr_op__invert_in$11$next[0:0]$9261 $1\sr_op__write_cr0$10$next[0:0]$9270 $1\sr_op__oe__ok$9$next[0:0]$9265 $1\sr_op__oe__oe$8$next[0:0]$9264 $1\sr_op__rc__ok$7$next[0:0]$9268 $1\sr_op__rc__rc$6$next[0:0]$9269 $1\sr_op__imm_data__ok$5$next[0:0]$9256 $1\sr_op__imm_data__data$4$next[63:0]$9255 $1\sr_op__fn_unit$3$next[11:0]$9254 $1\sr_op__insn_type$2$next[6:0]$9260 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } + case + assign $1\sr_op__fn_unit$3$next[11:0]$9254 \sr_op__fn_unit$3 + assign $1\sr_op__imm_data__data$4$next[63:0]$9255 \sr_op__imm_data__data$4 + assign $1\sr_op__imm_data__ok$5$next[0:0]$9256 \sr_op__imm_data__ok$5 + assign $1\sr_op__input_carry$12$next[1:0]$9257 \sr_op__input_carry$12 + assign $1\sr_op__input_cr$14$next[0:0]$9258 \sr_op__input_cr$14 + assign $1\sr_op__insn$18$next[31:0]$9259 \sr_op__insn$18 + assign $1\sr_op__insn_type$2$next[6:0]$9260 \sr_op__insn_type$2 + assign $1\sr_op__invert_in$11$next[0:0]$9261 \sr_op__invert_in$11 + assign $1\sr_op__is_32bit$16$next[0:0]$9262 \sr_op__is_32bit$16 + assign $1\sr_op__is_signed$17$next[0:0]$9263 \sr_op__is_signed$17 + assign $1\sr_op__oe__oe$8$next[0:0]$9264 \sr_op__oe__oe$8 + assign $1\sr_op__oe__ok$9$next[0:0]$9265 \sr_op__oe__ok$9 + assign $1\sr_op__output_carry$13$next[0:0]$9266 \sr_op__output_carry$13 + assign $1\sr_op__output_cr$15$next[0:0]$9267 \sr_op__output_cr$15 + assign $1\sr_op__rc__ok$7$next[0:0]$9268 \sr_op__rc__ok$7 + assign $1\sr_op__rc__rc$6$next[0:0]$9269 \sr_op__rc__rc$6 + assign $1\sr_op__write_cr0$10$next[0:0]$9270 \sr_op__write_cr0$10 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\sr_op__imm_data__data$4$next[63:0]$9271 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sr_op__imm_data__ok$5$next[0:0]$9272 1'0 + assign $2\sr_op__rc__rc$6$next[0:0]$9276 1'0 + assign $2\sr_op__rc__ok$7$next[0:0]$9275 1'0 + assign $2\sr_op__oe__oe$8$next[0:0]$9273 1'0 + assign $2\sr_op__oe__ok$9$next[0:0]$9274 1'0 + case + assign $2\sr_op__imm_data__data$4$next[63:0]$9271 $1\sr_op__imm_data__data$4$next[63:0]$9255 + assign $2\sr_op__imm_data__ok$5$next[0:0]$9272 $1\sr_op__imm_data__ok$5$next[0:0]$9256 + assign $2\sr_op__oe__oe$8$next[0:0]$9273 $1\sr_op__oe__oe$8$next[0:0]$9264 + assign $2\sr_op__oe__ok$9$next[0:0]$9274 $1\sr_op__oe__ok$9$next[0:0]$9265 + assign $2\sr_op__rc__ok$7$next[0:0]$9275 $1\sr_op__rc__ok$7$next[0:0]$9268 + assign $2\sr_op__rc__rc$6$next[0:0]$9276 $1\sr_op__rc__rc$6$next[0:0]$9269 + end + sync always + update \sr_op__fn_unit$3$next $0\sr_op__fn_unit$3$next[11:0]$9237 + update \sr_op__imm_data__data$4$next $0\sr_op__imm_data__data$4$next[63:0]$9238 + update \sr_op__imm_data__ok$5$next $0\sr_op__imm_data__ok$5$next[0:0]$9239 + update \sr_op__input_carry$12$next $0\sr_op__input_carry$12$next[1:0]$9240 + update \sr_op__input_cr$14$next $0\sr_op__input_cr$14$next[0:0]$9241 + update \sr_op__insn$18$next $0\sr_op__insn$18$next[31:0]$9242 + update \sr_op__insn_type$2$next $0\sr_op__insn_type$2$next[6:0]$9243 + update \sr_op__invert_in$11$next $0\sr_op__invert_in$11$next[0:0]$9244 + update \sr_op__is_32bit$16$next $0\sr_op__is_32bit$16$next[0:0]$9245 + update \sr_op__is_signed$17$next $0\sr_op__is_signed$17$next[0:0]$9246 + update \sr_op__oe__oe$8$next $0\sr_op__oe__oe$8$next[0:0]$9247 + update \sr_op__oe__ok$9$next $0\sr_op__oe__ok$9$next[0:0]$9248 + update \sr_op__output_carry$13$next $0\sr_op__output_carry$13$next[0:0]$9249 + update \sr_op__output_cr$15$next $0\sr_op__output_cr$15$next[0:0]$9250 + update \sr_op__rc__ok$7$next $0\sr_op__rc__ok$7$next[0:0]$9251 + update \sr_op__rc__rc$6$next $0\sr_op__rc__rc$6$next[0:0]$9252 + update \sr_op__write_cr0$10$next $0\sr_op__write_cr0$10$next[0:0]$9253 + end + attribute \src "libresoc.v:158562.3-158580.6" + process $proc$libresoc.v:158562$9277 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$19$next[63:0]$9278 $1\o$19$next[63:0]$9280 + assign { } { } + assign $0\o_ok$20$next[0:0]$9279 $2\o_ok$20$next[0:0]$9282 + attribute \src "libresoc.v:158563.5-158563.29" + switch \initial + attribute \src "libresoc.v:158563.9-158563.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$20$next[0:0]$9281 $1\o$19$next[63:0]$9280 } { \o_ok$72 \o$71 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$20$next[0:0]$9281 $1\o$19$next[63:0]$9280 } { \o_ok$72 \o$71 } + case + assign $1\o$19$next[63:0]$9280 \o$19 + assign $1\o_ok$20$next[0:0]$9281 \o_ok$20 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$20$next[0:0]$9282 1'0 + case + assign $2\o_ok$20$next[0:0]$9282 $1\o_ok$20$next[0:0]$9281 + end + sync always + update \o$19$next $0\o$19$next[63:0]$9278 + update \o_ok$20$next $0\o_ok$20$next[0:0]$9279 + end + attribute \src "libresoc.v:158581.3-158599.6" + process $proc$libresoc.v:158581$9283 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$21$next[3:0]$9284 $1\cr_a$21$next[3:0]$9286 + assign { } { } + assign $0\cr_a_ok$22$next[0:0]$9285 $2\cr_a_ok$22$next[0:0]$9288 + attribute \src "libresoc.v:158582.5-158582.29" + switch \initial + attribute \src "libresoc.v:158582.9-158582.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$22$next[0:0]$9287 $1\cr_a$21$next[3:0]$9286 } { \cr_a_ok$74 \cr_a$73 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$22$next[0:0]$9287 $1\cr_a$21$next[3:0]$9286 } { \cr_a_ok$74 \cr_a$73 } + case + assign $1\cr_a$21$next[3:0]$9286 \cr_a$21 + assign $1\cr_a_ok$22$next[0:0]$9287 \cr_a_ok$22 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$22$next[0:0]$9288 1'0 + case + assign $2\cr_a_ok$22$next[0:0]$9288 $1\cr_a_ok$22$next[0:0]$9287 + end + sync always + update \cr_a$21$next $0\cr_a$21$next[3:0]$9284 + update \cr_a_ok$22$next $0\cr_a_ok$22$next[0:0]$9285 + end + attribute \src "libresoc.v:158600.3-158618.6" + process $proc$libresoc.v:158600$9289 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ca$23$next[1:0]$9290 $1\xer_ca$23$next[1:0]$9292 + assign { } { } + assign $0\xer_ca_ok$24$next[0:0]$9291 $2\xer_ca_ok$24$next[0:0]$9294 + attribute \src "libresoc.v:158601.5-158601.29" + switch \initial + attribute \src "libresoc.v:158601.9-158601.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$24$next[0:0]$9293 $1\xer_ca$23$next[1:0]$9292 } { \xer_ca_ok$76 \xer_ca$75 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$24$next[0:0]$9293 $1\xer_ca$23$next[1:0]$9292 } { \xer_ca_ok$76 \xer_ca$75 } + case + assign $1\xer_ca$23$next[1:0]$9292 \xer_ca$23 + assign $1\xer_ca_ok$24$next[0:0]$9293 \xer_ca_ok$24 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ca_ok$24$next[0:0]$9294 1'0 + case + assign $2\xer_ca_ok$24$next[0:0]$9294 $1\xer_ca_ok$24$next[0:0]$9293 + end + sync always + update \xer_ca$23$next $0\xer_ca$23$next[1:0]$9290 + update \xer_ca_ok$24$next $0\xer_ca_ok$24$next[0:0]$9291 + end + connect \$51 $and$libresoc.v:158382$9179_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_ca_ok$76 \xer_ca$75 } { \output_xer_ca_ok \output_xer_ca$46 } + connect { \cr_a_ok$74 \cr_a$73 } { \output_cr_a_ok \output_cr_a$45 } + connect { \o_ok$72 \o$71 } { \output_o_ok$44 \output_o$43 } + connect { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } { \output_sr_op__insn$42 \output_sr_op__is_signed$41 \output_sr_op__is_32bit$40 \output_sr_op__output_cr$39 \output_sr_op__input_cr$38 \output_sr_op__output_carry$37 \output_sr_op__input_carry$36 \output_sr_op__invert_in$35 \output_sr_op__write_cr0$34 \output_sr_op__oe__ok$33 \output_sr_op__oe__oe$32 \output_sr_op__rc__ok$31 \output_sr_op__rc__rc$30 \output_sr_op__imm_data__ok$29 \output_sr_op__imm_data__data$28 \output_sr_op__fn_unit$27 \output_sr_op__insn_type$26 } + connect \muxid$53 \output_muxid$25 + connect \p_valid_i_p_ready_o \$51 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$50 \p_valid_i + connect { \xer_ca_ok$49 \output_xer_ca } { \xer_ca_ok \xer_ca } + connect { \xer_so_ok$48 \output_xer_so } { \xer_so_ok \xer_so } + connect { \cr_a_ok$47 \output_cr_a } { \cr_a_ok \cr_a } + connect { \output_o_ok \output_o } { \o_ok \o } + connect { \output_sr_op__insn \output_sr_op__is_signed \output_sr_op__is_32bit \output_sr_op__output_cr \output_sr_op__input_cr \output_sr_op__output_carry \output_sr_op__input_carry \output_sr_op__invert_in \output_sr_op__write_cr0 \output_sr_op__oe__ok \output_sr_op__oe__oe \output_sr_op__rc__ok \output_sr_op__rc__rc \output_sr_op__imm_data__ok \output_sr_op__imm_data__data \output_sr_op__fn_unit \output_sr_op__insn_type } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } + connect \output_muxid \muxid +end +attribute \src "libresoc.v:158639.1-159588.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2" +attribute \generator "nMigen" +module \pipe2$35 + attribute \src "libresoc.v:159494.3-159512.6" + wire width 64 $0\fast1$11$next[63:0]$9413 + attribute \src "libresoc.v:159349.3-159350.35" + wire width 64 $0\fast1$11[63:0]$9354 + attribute \src "libresoc.v:158651.14-158651.47" + wire width 64 $0\fast1$11[63:0]$9437 + attribute \src "libresoc.v:159494.3-159512.6" + wire $0\fast1_ok$next[0:0]$9412 + attribute \src "libresoc.v:159351.3-159352.33" + wire $0\fast1_ok[0:0] + attribute \src "libresoc.v:159513.3-159531.6" + wire width 64 $0\fast2$12$next[63:0]$9419 + attribute \src "libresoc.v:159345.3-159346.35" + wire width 64 $0\fast2$12[63:0]$9351 + attribute \src "libresoc.v:158667.14-158667.47" + wire width 64 $0\fast2$12[63:0]$9440 + attribute \src "libresoc.v:159513.3-159531.6" + wire $0\fast2_ok$next[0:0]$9418 + attribute \src "libresoc.v:159347.3-159348.33" + wire $0\fast2_ok[0:0] + attribute \src "libresoc.v:158640.7-158640.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:159551.3-159569.6" + wire width 64 $0\msr$next[63:0]$9430 + attribute \src "libresoc.v:159337.3-159338.23" + wire width 64 $0\msr[63:0] + attribute \src "libresoc.v:159551.3-159569.6" + wire $0\msr_ok$next[0:0]$9431 + attribute \src "libresoc.v:159339.3-159340.29" + wire $0\msr_ok[0:0] + attribute \src "libresoc.v:159441.3-159453.6" + wire width 2 $0\muxid$1$next[1:0]$9384 + attribute \src "libresoc.v:159375.3-159376.33" + wire width 2 $0\muxid$1[1:0]$9377 + attribute \src "libresoc.v:158939.13-158939.29" + wire width 2 $0\muxid$1[1:0]$9445 + attribute \src "libresoc.v:159532.3-159550.6" + wire width 64 $0\nia$next[63:0]$9424 + attribute \src "libresoc.v:159341.3-159342.23" + wire width 64 $0\nia[63:0] + attribute \src "libresoc.v:159532.3-159550.6" + wire $0\nia_ok$next[0:0]$9425 + attribute \src "libresoc.v:159343.3-159344.29" + wire $0\nia_ok[0:0] + attribute \src "libresoc.v:159475.3-159493.6" + wire width 64 $0\o$next[63:0]$9406 + attribute \src "libresoc.v:159353.3-159354.19" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:159475.3-159493.6" + wire $0\o_ok$next[0:0]$9407 + attribute \src "libresoc.v:159355.3-159356.25" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:159423.3-159440.6" + wire $0\r_busy$next[0:0]$9380 + attribute \src "libresoc.v:159377.3-159378.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:159454.3-159474.6" + wire width 64 $0\trap_op__cia$6$next[63:0]$9387 + attribute \src "libresoc.v:159365.3-159366.47" + wire width 64 $0\trap_op__cia$6[63:0]$9367 + attribute \src "libresoc.v:159000.14-159000.53" + wire width 64 $0\trap_op__cia$6[63:0]$9452 + attribute \src "libresoc.v:159454.3-159474.6" + wire width 12 $0\trap_op__fn_unit$3$next[11:0]$9388 + attribute \src "libresoc.v:159359.3-159360.55" + wire width 12 $0\trap_op__fn_unit$3[11:0]$9361 + attribute \src "libresoc.v:159033.14-159033.44" + wire width 12 $0\trap_op__fn_unit$3[11:0]$9454 + attribute \src "libresoc.v:159454.3-159474.6" + wire width 32 $0\trap_op__insn$4$next[31:0]$9389 + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \main_trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \main_trap_op__trapaddr$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \main_trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \main_trap_op__traptype$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 38 \msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \msr$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \msr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 39 \msr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \msr_ok$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \msr_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 20 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 19 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 18 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 36 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \nia$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \nia$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 37 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \nia_ok$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \nia_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 30 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 31 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 15 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 9 \trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__cia$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 25 \trap_op__cia$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__cia$6$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 6 \trap_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 22 \trap_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \trap_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \trap_op__fn_unit$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 7 \trap_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \trap_op__insn$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 23 \trap_op__insn$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \trap_op__insn$4$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \trap_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 21 \trap_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \trap_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \trap_op__insn_type$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \trap_op__is_32bit$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \trap_op__is_32bit$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \trap_op__is_32bit$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 13 \trap_op__ldst_exc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 output 29 \trap_op__ldst_exc$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \trap_op__ldst_exc$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \trap_op__ldst_exc$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 8 \trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__msr$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 24 \trap_op__msr$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__msr$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 12 \trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \trap_op__trapaddr$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 28 \trap_op__trapaddr$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \trap_op__trapaddr$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 11 \trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \trap_op__traptype$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 output 27 \trap_op__traptype$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \trap_op__traptype$8$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$libresoc.v:159336$9345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$25 + connect \B \p_ready_o + connect \Y $and$libresoc.v:159336$9345_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:159379.13-159414.4" + cell \main$38 \main + connect \fast1 \main_fast1 + connect \fast1$11 \main_fast1$23 + connect \fast1_ok \main_fast1_ok + connect \fast2 \main_fast2 + connect \fast2$12 \main_fast2$24 + connect \fast2_ok \main_fast2_ok + connect \msr \main_msr + connect \msr_ok \main_msr_ok + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$13 + connect \nia \main_nia + connect \nia_ok \main_nia_ok + connect \o \main_o + connect \o_ok \main_o_ok + connect \ra \main_ra + connect \rb \main_rb + connect \trap_op__cia \main_trap_op__cia + connect \trap_op__cia$6 \main_trap_op__cia$18 + connect \trap_op__fn_unit \main_trap_op__fn_unit + connect \trap_op__fn_unit$3 \main_trap_op__fn_unit$15 + connect \trap_op__insn \main_trap_op__insn + connect \trap_op__insn$4 \main_trap_op__insn$16 + connect \trap_op__insn_type \main_trap_op__insn_type + connect \trap_op__insn_type$2 \main_trap_op__insn_type$14 + connect \trap_op__is_32bit \main_trap_op__is_32bit + connect \trap_op__is_32bit$7 \main_trap_op__is_32bit$19 + connect \trap_op__ldst_exc \main_trap_op__ldst_exc + connect \trap_op__ldst_exc$10 \main_trap_op__ldst_exc$22 + connect \trap_op__msr \main_trap_op__msr + connect \trap_op__msr$5 \main_trap_op__msr$17 + connect \trap_op__trapaddr \main_trap_op__trapaddr + connect \trap_op__trapaddr$9 \main_trap_op__trapaddr$21 + connect \trap_op__traptype \main_trap_op__traptype + connect \trap_op__traptype$8 \main_trap_op__traptype$20 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:159415.10-159418.4" + cell \n$37 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:159419.10-159422.4" + cell \p$36 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:158640.7-158640.20" + process $proc$libresoc.v:158640$9435 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:158651.14-158651.47" + process $proc$libresoc.v:158651$9436 + assign { } { } + assign $0\fast1$11[63:0]$9437 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \fast1$11 $0\fast1$11[63:0]$9437 + end + attribute \src "libresoc.v:158658.7-158658.22" + process $proc$libresoc.v:158658$9438 + assign { } { } + assign $1\fast1_ok[0:0] 1'0 + sync always + sync init + update \fast1_ok $1\fast1_ok[0:0] + end + attribute \src "libresoc.v:158667.14-158667.47" + process $proc$libresoc.v:158667$9439 + assign { } { } + assign $0\fast2$12[63:0]$9440 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \fast2$12 $0\fast2$12[63:0]$9440 + end + attribute \src "libresoc.v:158674.7-158674.22" + process $proc$libresoc.v:158674$9441 + assign { } { } + assign $1\fast2_ok[0:0] 1'0 + sync always + sync init + update \fast2_ok $1\fast2_ok[0:0] + end + attribute \src "libresoc.v:158923.14-158923.40" + process $proc$libresoc.v:158923$9442 + assign { } { } + assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \msr $1\msr[63:0] + end + attribute \src "libresoc.v:158930.7-158930.20" + process $proc$libresoc.v:158930$9443 + assign { } { } + assign $1\msr_ok[0:0] 1'0 + sync always + sync init + update \msr_ok $1\msr_ok[0:0] + end + attribute \src "libresoc.v:158939.13-158939.29" + process $proc$libresoc.v:158939$9444 + assign { } { } + assign $0\muxid$1[1:0]$9445 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$9445 + end + attribute \src "libresoc.v:158952.14-158952.40" + process $proc$libresoc.v:158952$9446 + assign { } { } + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \nia $1\nia[63:0] + end + attribute \src "libresoc.v:158959.7-158959.20" + process $proc$libresoc.v:158959$9447 + assign { } { } + assign $1\nia_ok[0:0] 1'0 + sync always + sync init + update \nia_ok $1\nia_ok[0:0] + end + attribute \src "libresoc.v:158966.14-158966.38" + process $proc$libresoc.v:158966$9448 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "libresoc.v:158973.7-158973.18" + process $proc$libresoc.v:158973$9449 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "libresoc.v:158987.7-158987.20" + process $proc$libresoc.v:158987$9450 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:159000.14-159000.53" + process $proc$libresoc.v:159000$9451 + assign { } { } + assign $0\trap_op__cia$6[63:0]$9452 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9452 + end + attribute \src "libresoc.v:159033.14-159033.44" + process $proc$libresoc.v:159033$9453 + assign { } { } + assign $0\trap_op__fn_unit$3[11:0]$9454 12'000000000000 + sync always + sync init + update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[11:0]$9454 + end + attribute \src "libresoc.v:159057.14-159057.39" + process $proc$libresoc.v:159057$9455 + assign { } { } + assign $0\trap_op__insn$4[31:0]$9456 0 + sync always + sync init + update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9456 + end + attribute \src "libresoc.v:159212.13-159212.43" + process $proc$libresoc.v:159212$9457 + assign { } { } + assign $0\trap_op__insn_type$2[6:0]$9458 7'0000000 + sync always + sync init + update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9458 + end + attribute \src "libresoc.v:159297.7-159297.35" + process $proc$libresoc.v:159297$9459 + assign { } { } + assign $0\trap_op__is_32bit$7[0:0]$9460 1'0 + sync always + sync init + update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9460 + end + attribute \src "libresoc.v:159304.13-159304.43" + process $proc$libresoc.v:159304$9461 + assign { } { } + assign $0\trap_op__ldst_exc$10[7:0]$9462 8'00000000 + sync always + sync init + update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9462 + end + attribute \src "libresoc.v:159315.14-159315.53" + process $proc$libresoc.v:159315$9463 + assign { } { } + assign $0\trap_op__msr$5[63:0]$9464 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9464 + end + attribute \src "libresoc.v:159324.14-159324.46" + process $proc$libresoc.v:159324$9465 + assign { } { } + assign $0\trap_op__trapaddr$9[12:0]$9466 13'0000000000000 + sync always + sync init + update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9466 + end + attribute \src "libresoc.v:159333.13-159333.42" + process $proc$libresoc.v:159333$9467 + assign { } { } + assign $0\trap_op__traptype$8[7:0]$9468 8'00000000 + sync always + sync init + update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9468 + end + attribute \src "libresoc.v:159337.3-159338.23" + process $proc$libresoc.v:159337$9346 + assign { } { } + assign $0\msr[63:0] \msr$next + sync posedge \coresync_clk + update \msr $0\msr[63:0] + end + attribute \src "libresoc.v:159339.3-159340.29" + process $proc$libresoc.v:159339$9347 + assign { } { } + assign $0\msr_ok[0:0] \msr_ok$next + sync posedge \coresync_clk + update \msr_ok $0\msr_ok[0:0] + end + attribute \src "libresoc.v:159341.3-159342.23" + process $proc$libresoc.v:159341$9348 + assign { } { } + assign $0\nia[63:0] \nia$next + sync posedge \coresync_clk + update \nia $0\nia[63:0] + end + attribute \src "libresoc.v:159343.3-159344.29" + process $proc$libresoc.v:159343$9349 + assign { } { } + assign $0\nia_ok[0:0] \nia_ok$next + sync posedge \coresync_clk + update \nia_ok $0\nia_ok[0:0] + end + attribute \src "libresoc.v:159345.3-159346.35" + process $proc$libresoc.v:159345$9350 + assign { } { } + assign $0\fast2$12[63:0]$9351 \fast2$12$next + sync posedge \coresync_clk + update \fast2$12 $0\fast2$12[63:0]$9351 + end + attribute \src "libresoc.v:159347.3-159348.33" + process $proc$libresoc.v:159347$9352 + assign { } { } + assign $0\fast2_ok[0:0] \fast2_ok$next + sync posedge \coresync_clk + update \fast2_ok $0\fast2_ok[0:0] + end + attribute \src "libresoc.v:159349.3-159350.35" + process $proc$libresoc.v:159349$9353 + assign { } { } + assign $0\fast1$11[63:0]$9354 \fast1$11$next + sync posedge \coresync_clk + update \fast1$11 $0\fast1$11[63:0]$9354 + end + attribute \src "libresoc.v:159351.3-159352.33" + process $proc$libresoc.v:159351$9355 + assign { } { } + assign $0\fast1_ok[0:0] \fast1_ok$next + sync posedge \coresync_clk + update \fast1_ok $0\fast1_ok[0:0] + end + attribute \src "libresoc.v:159353.3-159354.19" + process $proc$libresoc.v:159353$9356 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] + end + attribute \src "libresoc.v:159355.3-159356.25" + process $proc$libresoc.v:159355$9357 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:159357.3-159358.59" + process $proc$libresoc.v:159357$9358 + assign { } { } + assign $0\trap_op__insn_type$2[6:0]$9359 \trap_op__insn_type$2$next + sync posedge \coresync_clk + update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9359 + end + attribute \src "libresoc.v:159359.3-159360.55" + process $proc$libresoc.v:159359$9360 + assign { } { } + assign $0\trap_op__fn_unit$3[11:0]$9361 \trap_op__fn_unit$3$next + sync posedge \coresync_clk + update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[11:0]$9361 + end + attribute \src "libresoc.v:159361.3-159362.49" + process $proc$libresoc.v:159361$9362 + assign { } { } + assign $0\trap_op__insn$4[31:0]$9363 \trap_op__insn$4$next + sync posedge \coresync_clk + update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9363 + end + attribute \src "libresoc.v:159363.3-159364.47" + process $proc$libresoc.v:159363$9364 + assign { } { } + assign $0\trap_op__msr$5[63:0]$9365 \trap_op__msr$5$next + sync posedge \coresync_clk + update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9365 + end + attribute \src "libresoc.v:159365.3-159366.47" + process $proc$libresoc.v:159365$9366 + assign { } { } + assign $0\trap_op__cia$6[63:0]$9367 \trap_op__cia$6$next + sync posedge \coresync_clk + update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9367 + end + attribute \src "libresoc.v:159367.3-159368.57" + process $proc$libresoc.v:159367$9368 + assign { } { } + assign $0\trap_op__is_32bit$7[0:0]$9369 \trap_op__is_32bit$7$next + sync posedge \coresync_clk + update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9369 + end + attribute \src "libresoc.v:159369.3-159370.57" + process $proc$libresoc.v:159369$9370 + assign { } { } + assign $0\trap_op__traptype$8[7:0]$9371 \trap_op__traptype$8$next + sync posedge \coresync_clk + update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9371 + end + attribute \src "libresoc.v:159371.3-159372.57" + process $proc$libresoc.v:159371$9372 + assign { } { } + assign $0\trap_op__trapaddr$9[12:0]$9373 \trap_op__trapaddr$9$next + sync posedge \coresync_clk + update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9373 + end + attribute \src "libresoc.v:159373.3-159374.59" + process $proc$libresoc.v:159373$9374 + assign { } { } + assign $0\trap_op__ldst_exc$10[7:0]$9375 \trap_op__ldst_exc$10$next + sync posedge \coresync_clk + update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9375 + end + attribute \src "libresoc.v:159375.3-159376.33" + process $proc$libresoc.v:159375$9376 + assign { } { } + assign $0\muxid$1[1:0]$9377 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$9377 + end + attribute \src "libresoc.v:159377.3-159378.29" + process $proc$libresoc.v:159377$9378 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:159423.3-159440.6" + process $proc$libresoc.v:159423$9379 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$9380 $2\r_busy$next[0:0]$9382 + attribute \src "libresoc.v:159424.5-159424.29" + switch \initial + attribute \src "libresoc.v:159424.9-159424.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$9381 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$9381 1'0 + case + assign $1\r_busy$next[0:0]$9381 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$9382 1'0 + case + assign $2\r_busy$next[0:0]$9382 $1\r_busy$next[0:0]$9381 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$9380 + end + attribute \src "libresoc.v:159441.3-159453.6" + process $proc$libresoc.v:159441$9383 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$9384 $1\muxid$1$next[1:0]$9385 + attribute \src "libresoc.v:159442.5-159442.29" + switch \initial + attribute \src "libresoc.v:159442.9-159442.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$9385 \muxid$28 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$9385 \muxid$28 + case + assign $1\muxid$1$next[1:0]$9385 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$9384 + end + attribute \src "libresoc.v:159454.3-159474.6" + process $proc$libresoc.v:159454$9386 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\trap_op__cia$6$next[63:0]$9387 $1\trap_op__cia$6$next[63:0]$9396 + assign $0\trap_op__fn_unit$3$next[11:0]$9388 $1\trap_op__fn_unit$3$next[11:0]$9397 + assign $0\trap_op__insn$4$next[31:0]$9389 $1\trap_op__insn$4$next[31:0]$9398 + assign $0\trap_op__insn_type$2$next[6:0]$9390 $1\trap_op__insn_type$2$next[6:0]$9399 + assign $0\trap_op__is_32bit$7$next[0:0]$9391 $1\trap_op__is_32bit$7$next[0:0]$9400 + assign $0\trap_op__ldst_exc$10$next[7:0]$9392 $1\trap_op__ldst_exc$10$next[7:0]$9401 + assign $0\trap_op__msr$5$next[63:0]$9393 $1\trap_op__msr$5$next[63:0]$9402 + assign $0\trap_op__trapaddr$9$next[12:0]$9394 $1\trap_op__trapaddr$9$next[12:0]$9403 + assign $0\trap_op__traptype$8$next[7:0]$9395 $1\trap_op__traptype$8$next[7:0]$9404 + attribute \src "libresoc.v:159455.5-159455.29" + switch \initial + attribute \src "libresoc.v:159455.9-159455.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\trap_op__ldst_exc$10$next[7:0]$9401 $1\trap_op__trapaddr$9$next[12:0]$9403 $1\trap_op__traptype$8$next[7:0]$9404 $1\trap_op__is_32bit$7$next[0:0]$9400 $1\trap_op__cia$6$next[63:0]$9396 $1\trap_op__msr$5$next[63:0]$9402 $1\trap_op__insn$4$next[31:0]$9398 $1\trap_op__fn_unit$3$next[11:0]$9397 $1\trap_op__insn_type$2$next[6:0]$9399 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\trap_op__ldst_exc$10$next[7:0]$9401 $1\trap_op__trapaddr$9$next[12:0]$9403 $1\trap_op__traptype$8$next[7:0]$9404 $1\trap_op__is_32bit$7$next[0:0]$9400 $1\trap_op__cia$6$next[63:0]$9396 $1\trap_op__msr$5$next[63:0]$9402 $1\trap_op__insn$4$next[31:0]$9398 $1\trap_op__fn_unit$3$next[11:0]$9397 $1\trap_op__insn_type$2$next[6:0]$9399 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } + case + assign $1\trap_op__cia$6$next[63:0]$9396 \trap_op__cia$6 + assign $1\trap_op__fn_unit$3$next[11:0]$9397 \trap_op__fn_unit$3 + assign $1\trap_op__insn$4$next[31:0]$9398 \trap_op__insn$4 + assign $1\trap_op__insn_type$2$next[6:0]$9399 \trap_op__insn_type$2 + assign $1\trap_op__is_32bit$7$next[0:0]$9400 \trap_op__is_32bit$7 + assign $1\trap_op__ldst_exc$10$next[7:0]$9401 \trap_op__ldst_exc$10 + assign $1\trap_op__msr$5$next[63:0]$9402 \trap_op__msr$5 + assign $1\trap_op__trapaddr$9$next[12:0]$9403 \trap_op__trapaddr$9 + assign $1\trap_op__traptype$8$next[7:0]$9404 \trap_op__traptype$8 + end + sync always + update \trap_op__cia$6$next $0\trap_op__cia$6$next[63:0]$9387 + update \trap_op__fn_unit$3$next $0\trap_op__fn_unit$3$next[11:0]$9388 + update \trap_op__insn$4$next $0\trap_op__insn$4$next[31:0]$9389 + update \trap_op__insn_type$2$next $0\trap_op__insn_type$2$next[6:0]$9390 + update \trap_op__is_32bit$7$next $0\trap_op__is_32bit$7$next[0:0]$9391 + update \trap_op__ldst_exc$10$next $0\trap_op__ldst_exc$10$next[7:0]$9392 + update \trap_op__msr$5$next $0\trap_op__msr$5$next[63:0]$9393 + update \trap_op__trapaddr$9$next $0\trap_op__trapaddr$9$next[12:0]$9394 + update \trap_op__traptype$8$next $0\trap_op__traptype$8$next[7:0]$9395 + end + attribute \src "libresoc.v:159475.3-159493.6" + process $proc$libresoc.v:159475$9405 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$9406 $1\o$next[63:0]$9408 + assign { } { } + assign $0\o_ok$next[0:0]$9407 $2\o_ok$next[0:0]$9410 + attribute \src "libresoc.v:159476.5-159476.29" + switch \initial + attribute \src "libresoc.v:159476.9-159476.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$9409 $1\o$next[63:0]$9408 } { \o_ok$39 \o$38 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$9409 $1\o$next[63:0]$9408 } { \o_ok$39 \o$38 } + case + assign $1\o$next[63:0]$9408 \o + assign $1\o_ok$next[0:0]$9409 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$9410 1'0 + case + assign $2\o_ok$next[0:0]$9410 $1\o_ok$next[0:0]$9409 + end + sync always + update \o$next $0\o$next[63:0]$9406 + update \o_ok$next $0\o_ok$next[0:0]$9407 + end + attribute \src "libresoc.v:159494.3-159512.6" + process $proc$libresoc.v:159494$9411 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast1$11$next[63:0]$9413 $1\fast1$11$next[63:0]$9415 + assign $0\fast1_ok$next[0:0]$9412 $2\fast1_ok$next[0:0]$9416 + attribute \src "libresoc.v:159495.5-159495.29" + switch \initial + attribute \src "libresoc.v:159495.9-159495.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\fast1_ok$next[0:0]$9414 $1\fast1$11$next[63:0]$9415 } { \fast1_ok$41 \fast1$40 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\fast1_ok$next[0:0]$9414 $1\fast1$11$next[63:0]$9415 } { \fast1_ok$41 \fast1$40 } + case + assign $1\fast1_ok$next[0:0]$9414 \fast1_ok + assign $1\fast1$11$next[63:0]$9415 \fast1$11 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast1_ok$next[0:0]$9416 1'0 + case + assign $2\fast1_ok$next[0:0]$9416 $1\fast1_ok$next[0:0]$9414 + end + sync always + update \fast1_ok$next $0\fast1_ok$next[0:0]$9412 + update \fast1$11$next $0\fast1$11$next[63:0]$9413 + end + attribute \src "libresoc.v:159513.3-159531.6" + process $proc$libresoc.v:159513$9417 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast2$12$next[63:0]$9419 $1\fast2$12$next[63:0]$9421 + assign $0\fast2_ok$next[0:0]$9418 $2\fast2_ok$next[0:0]$9422 + attribute \src "libresoc.v:159514.5-159514.29" + switch \initial + attribute \src "libresoc.v:159514.9-159514.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\fast2_ok$next[0:0]$9420 $1\fast2$12$next[63:0]$9421 } { \fast2_ok$43 \fast2$42 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\fast2_ok$next[0:0]$9420 $1\fast2$12$next[63:0]$9421 } { \fast2_ok$43 \fast2$42 } + case + assign $1\fast2_ok$next[0:0]$9420 \fast2_ok + assign $1\fast2$12$next[63:0]$9421 \fast2$12 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast2_ok$next[0:0]$9422 1'0 + case + assign $2\fast2_ok$next[0:0]$9422 $1\fast2_ok$next[0:0]$9420 + end + sync always + update \fast2_ok$next $0\fast2_ok$next[0:0]$9418 + update \fast2$12$next $0\fast2$12$next[63:0]$9419 + end + attribute \src "libresoc.v:159532.3-159550.6" + process $proc$libresoc.v:159532$9423 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\nia$next[63:0]$9424 $1\nia$next[63:0]$9426 + assign { } { } + assign $0\nia_ok$next[0:0]$9425 $2\nia_ok$next[0:0]$9428 + attribute \src "libresoc.v:159533.5-159533.29" + switch \initial + attribute \src "libresoc.v:159533.9-159533.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\nia_ok$next[0:0]$9427 $1\nia$next[63:0]$9426 } { \nia_ok$45 \nia$44 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\nia_ok$next[0:0]$9427 $1\nia$next[63:0]$9426 } { \nia_ok$45 \nia$44 } + case + assign $1\nia$next[63:0]$9426 \nia + assign $1\nia_ok$next[0:0]$9427 \nia_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\nia_ok$next[0:0]$9428 1'0 + case + assign $2\nia_ok$next[0:0]$9428 $1\nia_ok$next[0:0]$9427 + end + sync always + update \nia$next $0\nia$next[63:0]$9424 + update \nia_ok$next $0\nia_ok$next[0:0]$9425 + end + attribute \src "libresoc.v:159551.3-159569.6" + process $proc$libresoc.v:159551$9429 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\msr$next[63:0]$9430 $1\msr$next[63:0]$9432 + assign { } { } + assign $0\msr_ok$next[0:0]$9431 $2\msr_ok$next[0:0]$9434 + attribute \src "libresoc.v:159552.5-159552.29" + switch \initial + attribute \src "libresoc.v:159552.9-159552.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\msr_ok$next[0:0]$9433 $1\msr$next[63:0]$9432 } { \msr_ok$47 \msr$46 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\msr_ok$next[0:0]$9433 $1\msr$next[63:0]$9432 } { \msr_ok$47 \msr$46 } + case + assign $1\msr$next[63:0]$9432 \msr + assign $1\msr_ok$next[0:0]$9433 \msr_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr_ok$next[0:0]$9434 1'0 + case + assign $2\msr_ok$next[0:0]$9434 $1\msr_ok$next[0:0]$9433 + end + sync always + update \msr$next $0\msr$next[63:0]$9430 + update \msr_ok$next $0\msr_ok$next[0:0]$9431 + end + connect \$26 $and$libresoc.v:159336$9345_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \msr_ok$47 \msr$46 } { \main_msr_ok \main_msr } + connect { \nia_ok$45 \nia$44 } { \main_nia_ok \main_nia } + connect { \fast2_ok$43 \fast2$42 } { \main_fast2_ok \main_fast2$24 } + connect { \fast1_ok$41 \fast1$40 } { \main_fast1_ok \main_fast1$23 } + connect { \o_ok$39 \o$38 } { \main_o_ok \main_o } + connect { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } { \main_trap_op__ldst_exc$22 \main_trap_op__trapaddr$21 \main_trap_op__traptype$20 \main_trap_op__is_32bit$19 \main_trap_op__cia$18 \main_trap_op__msr$17 \main_trap_op__insn$16 \main_trap_op__fn_unit$15 \main_trap_op__insn_type$14 } + connect \muxid$28 \main_muxid$13 + connect \p_valid_i_p_ready_o \$26 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$25 \p_valid_i + connect \main_fast2 \fast2 + connect \main_fast1 \fast1 + connect \main_rb \rb + connect \main_ra \ra + connect { \main_trap_op__ldst_exc \main_trap_op__trapaddr \main_trap_op__traptype \main_trap_op__is_32bit \main_trap_op__cia \main_trap_op__msr \main_trap_op__insn \main_trap_op__fn_unit \main_trap_op__insn_type } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } + connect \main_muxid \muxid +end +attribute \src "libresoc.v:159592.1-161074.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end" +attribute \generator "nMigen" +module \pipe_end + attribute \src "libresoc.v:160912.3-160930.6" + wire width 4 $0\cr_a$next[3:0]$9525 + attribute \src "libresoc.v:160731.3-160732.25" + wire width 4 $0\cr_a[3:0] + attribute \src "libresoc.v:160912.3-160930.6" + wire $0\cr_a_ok$next[0:0]$9526 + attribute \src "libresoc.v:160733.3-160734.31" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:159593.7-159593.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:161000.3-161041.6" + wire width 4 $0\logical_op__data_len$18$next[3:0]$9550 + attribute \src "libresoc.v:160771.3-160772.65" + wire width 4 $0\logical_op__data_len$18[3:0]$9512 + attribute \src "libresoc.v:159634.13-159634.45" + wire width 4 $0\logical_op__data_len$18[3:0]$9596 + attribute \src "libresoc.v:161000.3-161041.6" + wire width 12 $0\logical_op__fn_unit$3$next[11:0]$9551 + attribute \src "libresoc.v:160741.3-160742.61" + wire width 12 $0\logical_op__fn_unit$3[11:0]$9482 + attribute \src "libresoc.v:159669.14-159669.47" + wire width 12 $0\logical_op__fn_unit$3[11:0]$9598 + attribute \src "libresoc.v:161000.3-161041.6" + wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$9552 + attribute \src "libresoc.v:160743.3-160744.75" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$9484 + attribute \src "libresoc.v:159691.14-159691.67" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$9600 + attribute \src "libresoc.v:161000.3-161041.6" + wire $0\logical_op__imm_data__ok$5$next[0:0]$9553 + attribute \src "libresoc.v:160745.3-160746.71" + wire $0\logical_op__imm_data__ok$5[0:0]$9486 + attribute \src "libresoc.v:159700.7-159700.42" + wire $0\logical_op__imm_data__ok$5[0:0]$9602 + attribute \src "libresoc.v:161000.3-161041.6" + wire width 2 $0\logical_op__input_carry$12$next[1:0]$9554 + attribute \src "libresoc.v:160759.3-160760.71" + wire width 2 $0\logical_op__input_carry$12[1:0]$9500 + attribute \src "libresoc.v:159717.13-159717.48" + wire width 2 $0\logical_op__input_carry$12[1:0]$9604 + attribute \src "libresoc.v:161000.3-161041.6" + wire width 32 $0\logical_op__insn$19$next[31:0]$9555 + attribute \src "libresoc.v:160773.3-160774.57" + wire width 32 $0\logical_op__insn$19[31:0]$9514 + attribute \src "libresoc.v:159730.14-159730.43" + wire width 32 $0\logical_op__insn$19[31:0]$9606 + attribute \src "libresoc.v:161000.3-161041.6" + wire width 7 $0\logical_op__insn_type$2$next[6:0]$9556 + attribute \src "libresoc.v:160739.3-160740.65" + wire width 7 $0\logical_op__insn_type$2[6:0]$9480 + attribute \src "libresoc.v:159887.13-159887.46" + wire width 7 $0\logical_op__insn_type$2[6:0]$9608 + attribute \src "libresoc.v:161000.3-161041.6" + wire $0\logical_op__invert_in$10$next[0:0]$9557 + attribute \src "libresoc.v:160755.3-160756.67" + wire $0\logical_op__invert_in$10[0:0]$9496 + attribute \src "libresoc.v:159970.7-159970.40" + wire $0\logical_op__invert_in$10[0:0]$9610 + attribute \src "libresoc.v:161000.3-161041.6" + wire $0\logical_op__invert_out$13$next[0:0]$9558 + attribute \src "libresoc.v:160761.3-160762.69" + wire $0\logical_op__invert_out$13[0:0]$9502 + attribute \src "libresoc.v:159979.7-159979.41" + wire $0\logical_op__invert_out$13[0:0]$9612 + attribute \src "libresoc.v:161000.3-161041.6" + wire $0\logical_op__is_32bit$16$next[0:0]$9559 + attribute \src "libresoc.v:160767.3-160768.65" + wire $0\logical_op__is_32bit$16[0:0]$9508 + attribute \src "libresoc.v:159988.7-159988.39" + wire $0\logical_op__is_32bit$16[0:0]$9614 + attribute \src "libresoc.v:161000.3-161041.6" + wire $0\logical_op__is_signed$17$next[0:0]$9560 + attribute \src "libresoc.v:160769.3-160770.67" + wire $0\logical_op__is_signed$17[0:0]$9510 + attribute \src "libresoc.v:159997.7-159997.40" + wire $0\logical_op__is_signed$17[0:0]$9616 + attribute \src "libresoc.v:161000.3-161041.6" + wire $0\logical_op__oe__oe$8$next[0:0]$9561 + attribute \src "libresoc.v:160751.3-160752.59" + wire $0\logical_op__oe__oe$8[0:0]$9492 + attribute \src "libresoc.v:160006.7-160006.36" + wire $0\logical_op__oe__oe$8[0:0]$9618 + attribute \src "libresoc.v:161000.3-161041.6" + wire $0\logical_op__oe__ok$9$next[0:0]$9562 + attribute \src "libresoc.v:160753.3-160754.59" + wire $0\logical_op__oe__ok$9[0:0]$9494 + attribute \src "libresoc.v:160017.7-160017.36" + wire $0\logical_op__oe__ok$9[0:0]$9620 + attribute \src "libresoc.v:161000.3-161041.6" + wire $0\logical_op__output_carry$15$next[0:0]$9563 + attribute \src "libresoc.v:160765.3-160766.73" + wire $0\logical_op__output_carry$15[0:0]$9506 + attribute \src "libresoc.v:160024.7-160024.43" + wire $0\logical_op__output_carry$15[0:0]$9622 + attribute \src "libresoc.v:161000.3-161041.6" + wire $0\logical_op__rc__ok$7$next[0:0]$9564 + attribute \src "libresoc.v:160749.3-160750.59" + wire $0\logical_op__rc__ok$7[0:0]$9490 + attribute \src "libresoc.v:160033.7-160033.36" + wire $0\logical_op__rc__ok$7[0:0]$9624 + attribute \src "libresoc.v:161000.3-161041.6" + wire $0\logical_op__rc__rc$6$next[0:0]$9565 + attribute \src "libresoc.v:160747.3-160748.59" + wire $0\logical_op__rc__rc$6[0:0]$9488 + attribute \src "libresoc.v:160042.7-160042.36" + wire $0\logical_op__rc__rc$6[0:0]$9626 + attribute \src "libresoc.v:161000.3-161041.6" + wire $0\logical_op__write_cr0$14$next[0:0]$9566 + attribute \src "libresoc.v:160763.3-160764.67" + wire $0\logical_op__write_cr0$14[0:0]$9504 + attribute \src "libresoc.v:160051.7-160051.40" + wire $0\logical_op__write_cr0$14[0:0]$9628 + attribute \src "libresoc.v:161000.3-161041.6" + wire $0\logical_op__zero_a$11$next[0:0]$9567 + attribute \src "libresoc.v:160757.3-160758.61" + wire $0\logical_op__zero_a$11[0:0]$9498 + attribute \src "libresoc.v:160060.7-160060.37" + wire $0\logical_op__zero_a$11[0:0]$9630 + attribute \src "libresoc.v:160987.3-160999.6" + wire width 2 $0\muxid$1$next[1:0]$9547 + attribute \src "libresoc.v:160775.3-160776.33" + wire width 2 $0\muxid$1[1:0]$9516 + attribute \src "libresoc.v:160069.13-160069.29" + wire width 2 $0\muxid$1[1:0]$9632 + attribute \src "libresoc.v:160893.3-160911.6" + wire width 64 $0\o$next[63:0]$9519 + attribute \src "libresoc.v:160735.3-160736.19" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:160893.3-160911.6" + wire $0\o_ok$next[0:0]$9520 + attribute \src "libresoc.v:160737.3-160738.25" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:160969.3-160986.6" + wire $0\r_busy$next[0:0]$9543 + attribute \src "libresoc.v:160777.3-160778.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:160931.3-160949.6" + wire width 2 $0\xer_ov$next[1:0]$9531 + attribute \src "libresoc.v:160727.3-160728.29" + wire width 2 $0\xer_ov[1:0] + attribute \src "libresoc.v:160931.3-160949.6" + wire $0\xer_ov_ok$next[0:0]$9532 + attribute \src "libresoc.v:160729.3-160730.35" + wire $0\xer_ov_ok[0:0] + attribute \src "libresoc.v:160950.3-160968.6" + wire $0\xer_so$20$next[0:0]$9538 + attribute \src "libresoc.v:160723.3-160724.37" + wire $0\xer_so$20[0:0]$9471 + attribute \src "libresoc.v:160708.7-160708.25" + wire $0\xer_so$20[0:0]$9639 + attribute \src "libresoc.v:160950.3-160968.6" + wire $0\xer_so_ok$next[0:0]$9537 + attribute \src "libresoc.v:160725.3-160726.35" + wire $0\xer_so_ok[0:0] + attribute \src "libresoc.v:160912.3-160930.6" + wire width 4 $1\cr_a$next[3:0]$9527 + attribute \src "libresoc.v:159602.13-159602.24" + wire width 4 $1\cr_a[3:0] + attribute \src "libresoc.v:160912.3-160930.6" + wire $1\cr_a_ok$next[0:0]$9528 + attribute \src "libresoc.v:159611.7-159611.21" + wire $1\cr_a_ok[0:0] + attribute \src "libresoc.v:161000.3-161041.6" + wire width 4 $1\logical_op__data_len$18$next[3:0]$9568 + attribute \src "libresoc.v:161000.3-161041.6" + wire width 12 $1\logical_op__fn_unit$3$next[11:0]$9569 + attribute \src "libresoc.v:161000.3-161041.6" + wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$9570 + attribute \src "libresoc.v:161000.3-161041.6" + wire $1\logical_op__imm_data__ok$5$next[0:0]$9571 + attribute \src "libresoc.v:161000.3-161041.6" + wire width 2 $1\logical_op__input_carry$12$next[1:0]$9572 + attribute \src "libresoc.v:161000.3-161041.6" + wire width 32 $1\logical_op__insn$19$next[31:0]$9573 + attribute \src "libresoc.v:161000.3-161041.6" + wire width 7 $1\logical_op__insn_type$2$next[6:0]$9574 + attribute \src "libresoc.v:161000.3-161041.6" + wire $1\logical_op__invert_in$10$next[0:0]$9575 + attribute \src "libresoc.v:161000.3-161041.6" + wire $1\logical_op__invert_out$13$next[0:0]$9576 + attribute \src "libresoc.v:161000.3-161041.6" + wire $1\logical_op__is_32bit$16$next[0:0]$9577 + attribute \src "libresoc.v:161000.3-161041.6" + wire $1\logical_op__is_signed$17$next[0:0]$9578 + attribute \src "libresoc.v:161000.3-161041.6" + wire $1\logical_op__oe__oe$8$next[0:0]$9579 + attribute \src "libresoc.v:161000.3-161041.6" + wire $1\logical_op__oe__ok$9$next[0:0]$9580 + attribute \src "libresoc.v:161000.3-161041.6" + wire $1\logical_op__output_carry$15$next[0:0]$9581 + attribute \src "libresoc.v:161000.3-161041.6" + wire $1\logical_op__rc__ok$7$next[0:0]$9582 + attribute \src "libresoc.v:161000.3-161041.6" + wire $1\logical_op__rc__rc$6$next[0:0]$9583 + attribute \src "libresoc.v:161000.3-161041.6" + wire $1\logical_op__write_cr0$14$next[0:0]$9584 + attribute \src "libresoc.v:161000.3-161041.6" + wire $1\logical_op__zero_a$11$next[0:0]$9585 + attribute \src "libresoc.v:160987.3-160999.6" + wire width 2 $1\muxid$1$next[1:0]$9548 + attribute \src "libresoc.v:160893.3-160911.6" + wire width 64 $1\o$next[63:0]$9521 + attribute \src "libresoc.v:160082.14-160082.38" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:160893.3-160911.6" + wire $1\o_ok$next[0:0]$9522 + attribute \src "libresoc.v:160089.7-160089.18" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:160969.3-160986.6" + wire $1\r_busy$next[0:0]$9544 + attribute \src "libresoc.v:160673.7-160673.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:160931.3-160949.6" + wire width 2 $1\xer_ov$next[1:0]$9533 + attribute \src "libresoc.v:160688.13-160688.26" + wire width 2 $1\xer_ov[1:0] + attribute \src "libresoc.v:160931.3-160949.6" + wire $1\xer_ov_ok$next[0:0]$9534 + attribute \src "libresoc.v:160695.7-160695.23" + wire $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:160950.3-160968.6" + wire $1\xer_so$20$next[0:0]$9540 + attribute \src "libresoc.v:160950.3-160968.6" + wire $1\xer_so_ok$next[0:0]$9539 + attribute \src "libresoc.v:160713.7-160713.23" + wire $1\xer_so_ok[0:0] + attribute \src "libresoc.v:160912.3-160930.6" + wire $2\cr_a_ok$next[0:0]$9529 + attribute \src "libresoc.v:161000.3-161041.6" + wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$9586 + attribute \src "libresoc.v:161000.3-161041.6" + wire $2\logical_op__imm_data__ok$5$next[0:0]$9587 + attribute \src "libresoc.v:161000.3-161041.6" + wire $2\logical_op__oe__oe$8$next[0:0]$9588 + attribute \src "libresoc.v:161000.3-161041.6" + wire $2\logical_op__oe__ok$9$next[0:0]$9589 + attribute \src "libresoc.v:161000.3-161041.6" + wire $2\logical_op__rc__ok$7$next[0:0]$9590 + attribute \src "libresoc.v:161000.3-161041.6" + wire $2\logical_op__rc__rc$6$next[0:0]$9591 + attribute \src "libresoc.v:160893.3-160911.6" + wire $2\o_ok$next[0:0]$9523 + attribute \src "libresoc.v:160969.3-160986.6" + wire $2\r_busy$next[0:0]$9545 + attribute \src "libresoc.v:160931.3-160949.6" + wire $2\xer_ov_ok$next[0:0]$9535 + attribute \src "libresoc.v:160950.3-160968.6" + wire $2\xer_so_ok$next[0:0]$9541 + attribute \src "libresoc.v:160722.18-160722.118" + wire $and$libresoc.v:160722$9469_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 62 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 56 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 57 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire input 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire input 28 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire input 29 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire input 27 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire input 26 \divisor_neg + attribute \src "libresoc.v:159593.7-159593.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 52 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$93 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 6 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 37 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_op__fn_unit$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 38 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \logical_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$80 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 15 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 46 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$12$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 53 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$94 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 36 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 44 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 47 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 50 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 51 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 42 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 43 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 49 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 48 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 45 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$86 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 35 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$76 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 34 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 33 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 54 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 55 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_logical_op__data_len$58 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \output_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \output_logical_op__fn_unit$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_logical_op__imm_data__data$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__imm_data__ok$45 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_logical_op__input_carry$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_logical_op__insn$59 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_logical_op__insn_type$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_in$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_out$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_32bit$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_signed$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__oe$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__ok$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__output_carry$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__ok$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__rc$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__write_cr0$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__zero_a$51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_muxid$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \output_stage_div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \output_stage_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \output_stage_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \output_stage_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \output_stage_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_stage_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_stage_logical_op__data_len$38 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \output_stage_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \output_stage_logical_op__fn_unit$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_stage_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_stage_logical_op__imm_data__data$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__imm_data__ok$25 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_stage_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_stage_logical_op__input_carry$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_stage_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_stage_logical_op__insn$39 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_stage_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute 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\enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src 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\o_ok$21 \output_o_ok$61 + connect \xer_ov \output_xer_ov + connect \xer_ov$23 \output_xer_ov$63 + connect \xer_ov_ok \output_xer_ov_ok + connect \xer_so \output_xer_so + connect \xer_so$24 \output_xer_so$64 + connect \xer_so_ok \output_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:160836.16-160888.4" + cell \output_stage \output_stage + connect \div_by_zero \output_stage_div_by_zero + connect \dive_abs_ov32 \output_stage_dive_abs_ov32 + connect \dive_abs_ov64 \output_stage_dive_abs_ov64 + connect \dividend_neg \output_stage_dividend_neg + connect \divisor_neg \output_stage_divisor_neg + connect \logical_op__data_len \output_stage_logical_op__data_len + connect \logical_op__data_len$18 \output_stage_logical_op__data_len$38 + connect \logical_op__fn_unit \output_stage_logical_op__fn_unit + connect \logical_op__fn_unit$3 \output_stage_logical_op__fn_unit$23 + connect \logical_op__imm_data__data \output_stage_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \output_stage_logical_op__imm_data__data$24 + connect \logical_op__imm_data__ok \output_stage_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \output_stage_logical_op__imm_data__ok$25 + connect \logical_op__input_carry \output_stage_logical_op__input_carry + connect \logical_op__input_carry$12 \output_stage_logical_op__input_carry$32 + connect \logical_op__insn \output_stage_logical_op__insn + connect \logical_op__insn$19 \output_stage_logical_op__insn$39 + connect \logical_op__insn_type \output_stage_logical_op__insn_type + connect \logical_op__insn_type$2 \output_stage_logical_op__insn_type$22 + connect \logical_op__invert_in \output_stage_logical_op__invert_in + connect \logical_op__invert_in$10 \output_stage_logical_op__invert_in$30 + connect \logical_op__invert_out \output_stage_logical_op__invert_out + connect \logical_op__invert_out$13 \output_stage_logical_op__invert_out$33 + connect \logical_op__is_32bit \output_stage_logical_op__is_32bit + connect \logical_op__is_32bit$16 \output_stage_logical_op__is_32bit$36 + connect \logical_op__is_signed \output_stage_logical_op__is_signed + connect \logical_op__is_signed$17 \output_stage_logical_op__is_signed$37 + connect \logical_op__oe__oe \output_stage_logical_op__oe__oe + connect \logical_op__oe__oe$8 \output_stage_logical_op__oe__oe$28 + connect \logical_op__oe__ok \output_stage_logical_op__oe__ok + connect \logical_op__oe__ok$9 \output_stage_logical_op__oe__ok$29 + connect \logical_op__output_carry \output_stage_logical_op__output_carry + connect \logical_op__output_carry$15 \output_stage_logical_op__output_carry$35 + connect \logical_op__rc__ok \output_stage_logical_op__rc__ok + connect \logical_op__rc__ok$7 \output_stage_logical_op__rc__ok$27 + connect \logical_op__rc__rc \output_stage_logical_op__rc__rc + connect \logical_op__rc__rc$6 \output_stage_logical_op__rc__rc$26 + connect \logical_op__write_cr0 \output_stage_logical_op__write_cr0 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attribute \src "libresoc.v:159602.13-159602.24" + process $proc$libresoc.v:159602$9593 + assign { } { } + assign $1\cr_a[3:0] 4'0000 + sync always + sync init + update \cr_a $1\cr_a[3:0] + end + attribute \src "libresoc.v:159611.7-159611.21" + process $proc$libresoc.v:159611$9594 + assign { } { } + assign $1\cr_a_ok[0:0] 1'0 + sync always + sync init + update \cr_a_ok $1\cr_a_ok[0:0] + end + attribute \src "libresoc.v:159634.13-159634.45" + process $proc$libresoc.v:159634$9595 + assign { } { } + assign $0\logical_op__data_len$18[3:0]$9596 4'0000 + sync always + sync init + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9596 + end + attribute \src "libresoc.v:159669.14-159669.47" + process $proc$libresoc.v:159669$9597 + assign { } { } + assign $0\logical_op__fn_unit$3[11:0]$9598 12'000000000000 + sync always + sync init + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[11:0]$9598 + end + attribute \src "libresoc.v:159691.14-159691.67" + process $proc$libresoc.v:159691$9599 + assign { } { } + assign $0\logical_op__imm_data__data$4[63:0]$9600 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9600 + end + attribute \src "libresoc.v:159700.7-159700.42" + process $proc$libresoc.v:159700$9601 + assign { } { } + assign $0\logical_op__imm_data__ok$5[0:0]$9602 1'0 + sync always + sync init + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9602 + end + attribute \src "libresoc.v:159717.13-159717.48" + process $proc$libresoc.v:159717$9603 + assign { } { } + assign $0\logical_op__input_carry$12[1:0]$9604 2'00 + sync always + sync init + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9604 + end + attribute \src "libresoc.v:159730.14-159730.43" + process $proc$libresoc.v:159730$9605 + assign { } { } + assign $0\logical_op__insn$19[31:0]$9606 0 + sync always + sync init + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9606 + end + attribute \src "libresoc.v:159887.13-159887.46" + process $proc$libresoc.v:159887$9607 + assign { } { } + assign $0\logical_op__insn_type$2[6:0]$9608 7'0000000 + sync always + sync init + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9608 + end + attribute \src "libresoc.v:159970.7-159970.40" + process $proc$libresoc.v:159970$9609 + assign { } { } + assign $0\logical_op__invert_in$10[0:0]$9610 1'0 + sync always + sync init + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9610 + end + attribute \src "libresoc.v:159979.7-159979.41" + process $proc$libresoc.v:159979$9611 + assign { } { } + assign $0\logical_op__invert_out$13[0:0]$9612 1'0 + sync always + sync init + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9612 + end + attribute \src "libresoc.v:159988.7-159988.39" + process $proc$libresoc.v:159988$9613 + assign { } { } + assign $0\logical_op__is_32bit$16[0:0]$9614 1'0 + sync always + sync init + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9614 + end + attribute \src "libresoc.v:159997.7-159997.40" + process $proc$libresoc.v:159997$9615 + assign { } { } + assign $0\logical_op__is_signed$17[0:0]$9616 1'0 + sync always + sync init + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9616 + end + attribute \src "libresoc.v:160006.7-160006.36" + process $proc$libresoc.v:160006$9617 + assign { } { } + assign $0\logical_op__oe__oe$8[0:0]$9618 1'0 + sync always + sync init + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9618 + end + attribute \src "libresoc.v:160017.7-160017.36" + process $proc$libresoc.v:160017$9619 + assign { } { } + assign $0\logical_op__oe__ok$9[0:0]$9620 1'0 + sync always + sync init + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9620 + end + attribute \src "libresoc.v:160024.7-160024.43" + process $proc$libresoc.v:160024$9621 + assign { } { } + assign $0\logical_op__output_carry$15[0:0]$9622 1'0 + sync always + sync init + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9622 + end + attribute \src "libresoc.v:160033.7-160033.36" + process $proc$libresoc.v:160033$9623 + assign { } { } + assign $0\logical_op__rc__ok$7[0:0]$9624 1'0 + sync always + sync init + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9624 + end + attribute \src "libresoc.v:160042.7-160042.36" + process $proc$libresoc.v:160042$9625 + assign { } { } + assign $0\logical_op__rc__rc$6[0:0]$9626 1'0 + sync always + sync init + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9626 + end + attribute \src "libresoc.v:160051.7-160051.40" + process $proc$libresoc.v:160051$9627 + assign { } { } + assign $0\logical_op__write_cr0$14[0:0]$9628 1'0 + sync always + sync init + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9628 + end + attribute \src "libresoc.v:160060.7-160060.37" + process $proc$libresoc.v:160060$9629 + assign { } { } + assign $0\logical_op__zero_a$11[0:0]$9630 1'0 + sync always + sync init + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9630 + end + attribute \src "libresoc.v:160069.13-160069.29" + process $proc$libresoc.v:160069$9631 + assign { } { } + assign $0\muxid$1[1:0]$9632 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$9632 + end + attribute \src "libresoc.v:160082.14-160082.38" + process $proc$libresoc.v:160082$9633 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "libresoc.v:160089.7-160089.18" + process $proc$libresoc.v:160089$9634 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "libresoc.v:160673.7-160673.20" + process $proc$libresoc.v:160673$9635 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:160688.13-160688.26" + process $proc$libresoc.v:160688$9636 + assign { } { } + assign $1\xer_ov[1:0] 2'00 + sync always + sync init + update \xer_ov $1\xer_ov[1:0] + end + attribute \src "libresoc.v:160695.7-160695.23" + process $proc$libresoc.v:160695$9637 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'0 + sync always + sync init + update \xer_ov_ok $1\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:160708.7-160708.25" + process $proc$libresoc.v:160708$9638 + assign { } { } + assign $0\xer_so$20[0:0]$9639 1'0 + sync always + sync init + update \xer_so$20 $0\xer_so$20[0:0]$9639 + end + attribute \src "libresoc.v:160713.7-160713.23" + process $proc$libresoc.v:160713$9640 + assign { } { } + assign $1\xer_so_ok[0:0] 1'0 + sync always + sync init + update \xer_so_ok $1\xer_so_ok[0:0] + end + attribute \src "libresoc.v:160723.3-160724.37" + process $proc$libresoc.v:160723$9470 + assign { } { } + assign $0\xer_so$20[0:0]$9471 \xer_so$20$next + sync posedge \coresync_clk + update \xer_so$20 $0\xer_so$20[0:0]$9471 + end + attribute \src "libresoc.v:160725.3-160726.35" + process $proc$libresoc.v:160725$9472 + assign { } { } + assign $0\xer_so_ok[0:0] \xer_so_ok$next + sync posedge \coresync_clk + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:160727.3-160728.29" + process $proc$libresoc.v:160727$9473 + assign { } { } + assign $0\xer_ov[1:0] \xer_ov$next + sync posedge \coresync_clk + update \xer_ov $0\xer_ov[1:0] + end + attribute \src "libresoc.v:160729.3-160730.35" + process $proc$libresoc.v:160729$9474 + assign { } { } + assign $0\xer_ov_ok[0:0] \xer_ov_ok$next + sync posedge \coresync_clk + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:160731.3-160732.25" + process $proc$libresoc.v:160731$9475 + assign { } { } + assign $0\cr_a[3:0] \cr_a$next + sync posedge \coresync_clk + update \cr_a $0\cr_a[3:0] + end + attribute \src "libresoc.v:160733.3-160734.31" + process $proc$libresoc.v:160733$9476 + assign { } { } + assign $0\cr_a_ok[0:0] \cr_a_ok$next + sync posedge \coresync_clk + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "libresoc.v:160735.3-160736.19" + process $proc$libresoc.v:160735$9477 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] + end + attribute \src "libresoc.v:160737.3-160738.25" + process $proc$libresoc.v:160737$9478 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:160739.3-160740.65" + process $proc$libresoc.v:160739$9479 + assign { } { } + assign $0\logical_op__insn_type$2[6:0]$9480 \logical_op__insn_type$2$next + sync posedge \coresync_clk + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9480 + end + attribute \src "libresoc.v:160741.3-160742.61" + process $proc$libresoc.v:160741$9481 + assign { } { } + assign $0\logical_op__fn_unit$3[11:0]$9482 \logical_op__fn_unit$3$next + sync posedge \coresync_clk + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[11:0]$9482 + end + attribute \src "libresoc.v:160743.3-160744.75" + process $proc$libresoc.v:160743$9483 + assign { } { } + assign $0\logical_op__imm_data__data$4[63:0]$9484 \logical_op__imm_data__data$4$next + sync posedge \coresync_clk + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9484 + end + attribute \src "libresoc.v:160745.3-160746.71" + process $proc$libresoc.v:160745$9485 + assign { } { } + assign $0\logical_op__imm_data__ok$5[0:0]$9486 \logical_op__imm_data__ok$5$next + sync posedge \coresync_clk + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9486 + end + attribute \src "libresoc.v:160747.3-160748.59" + process $proc$libresoc.v:160747$9487 + assign { } { } + assign $0\logical_op__rc__rc$6[0:0]$9488 \logical_op__rc__rc$6$next + sync posedge \coresync_clk + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9488 + end + attribute \src "libresoc.v:160749.3-160750.59" + process $proc$libresoc.v:160749$9489 + assign { } { } + assign $0\logical_op__rc__ok$7[0:0]$9490 \logical_op__rc__ok$7$next + sync posedge \coresync_clk + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9490 + end + attribute \src "libresoc.v:160751.3-160752.59" + process $proc$libresoc.v:160751$9491 + assign { } { } + assign $0\logical_op__oe__oe$8[0:0]$9492 \logical_op__oe__oe$8$next + sync posedge \coresync_clk + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9492 + end + attribute \src "libresoc.v:160753.3-160754.59" + process $proc$libresoc.v:160753$9493 + assign { } { } + assign $0\logical_op__oe__ok$9[0:0]$9494 \logical_op__oe__ok$9$next + sync posedge \coresync_clk + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9494 + end + attribute \src "libresoc.v:160755.3-160756.67" + process $proc$libresoc.v:160755$9495 + assign { } { } + assign $0\logical_op__invert_in$10[0:0]$9496 \logical_op__invert_in$10$next + sync posedge \coresync_clk + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9496 + end + attribute \src "libresoc.v:160757.3-160758.61" + process $proc$libresoc.v:160757$9497 + assign { } { } + assign $0\logical_op__zero_a$11[0:0]$9498 \logical_op__zero_a$11$next + sync posedge \coresync_clk + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9498 + end + attribute \src "libresoc.v:160759.3-160760.71" + process $proc$libresoc.v:160759$9499 + assign { } { } + assign $0\logical_op__input_carry$12[1:0]$9500 \logical_op__input_carry$12$next + sync posedge \coresync_clk + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9500 + end + attribute \src "libresoc.v:160761.3-160762.69" + process $proc$libresoc.v:160761$9501 + assign { } { } + assign $0\logical_op__invert_out$13[0:0]$9502 \logical_op__invert_out$13$next + sync posedge \coresync_clk + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9502 + end + attribute \src "libresoc.v:160763.3-160764.67" + process $proc$libresoc.v:160763$9503 + assign { } { } + assign $0\logical_op__write_cr0$14[0:0]$9504 \logical_op__write_cr0$14$next + sync posedge \coresync_clk + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9504 + end + attribute \src "libresoc.v:160765.3-160766.73" + process $proc$libresoc.v:160765$9505 + assign { } { } + assign $0\logical_op__output_carry$15[0:0]$9506 \logical_op__output_carry$15$next + sync posedge \coresync_clk + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9506 + end + attribute \src "libresoc.v:160767.3-160768.65" + process $proc$libresoc.v:160767$9507 + assign { } { } + assign $0\logical_op__is_32bit$16[0:0]$9508 \logical_op__is_32bit$16$next + sync posedge \coresync_clk + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9508 + end + attribute \src "libresoc.v:160769.3-160770.67" + process $proc$libresoc.v:160769$9509 + assign { } { } + assign $0\logical_op__is_signed$17[0:0]$9510 \logical_op__is_signed$17$next + sync posedge \coresync_clk + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9510 + end + attribute \src "libresoc.v:160771.3-160772.65" + process $proc$libresoc.v:160771$9511 + assign { } { } + assign $0\logical_op__data_len$18[3:0]$9512 \logical_op__data_len$18$next + sync posedge \coresync_clk + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9512 + end + attribute \src "libresoc.v:160773.3-160774.57" + process $proc$libresoc.v:160773$9513 + assign { } { } + assign $0\logical_op__insn$19[31:0]$9514 \logical_op__insn$19$next + sync posedge \coresync_clk + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9514 + end + attribute \src "libresoc.v:160775.3-160776.33" + process $proc$libresoc.v:160775$9515 + assign { } { } + assign $0\muxid$1[1:0]$9516 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$9516 + end + attribute \src "libresoc.v:160777.3-160778.29" + process $proc$libresoc.v:160777$9517 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:160893.3-160911.6" + process $proc$libresoc.v:160893$9518 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$9519 $1\o$next[63:0]$9521 + assign { } { } + assign $0\o_ok$next[0:0]$9520 $2\o_ok$next[0:0]$9523 + attribute \src "libresoc.v:160894.5-160894.29" + switch \initial + attribute \src "libresoc.v:160894.9-160894.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$9522 $1\o$next[63:0]$9521 } { \o_ok$96 \o$95 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$9522 $1\o$next[63:0]$9521 } { \o_ok$96 \o$95 } + case + assign $1\o$next[63:0]$9521 \o + assign $1\o_ok$next[0:0]$9522 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$9523 1'0 + case + assign $2\o_ok$next[0:0]$9523 $1\o_ok$next[0:0]$9522 + end + sync always + update \o$next $0\o$next[63:0]$9519 + update \o_ok$next $0\o_ok$next[0:0]$9520 + end + attribute \src "libresoc.v:160912.3-160930.6" + process $proc$libresoc.v:160912$9524 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$next[3:0]$9525 $1\cr_a$next[3:0]$9527 + assign { } { } + assign $0\cr_a_ok$next[0:0]$9526 $2\cr_a_ok$next[0:0]$9529 + attribute \src "libresoc.v:160913.5-160913.29" + switch \initial + attribute \src "libresoc.v:160913.9-160913.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$9528 $1\cr_a$next[3:0]$9527 } { \cr_a_ok$98 \cr_a$97 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$9528 $1\cr_a$next[3:0]$9527 } { \cr_a_ok$98 \cr_a$97 } + case + assign $1\cr_a$next[3:0]$9527 \cr_a + assign $1\cr_a_ok$next[0:0]$9528 \cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$next[0:0]$9529 1'0 + case + assign $2\cr_a_ok$next[0:0]$9529 $1\cr_a_ok$next[0:0]$9528 + end + sync always + update \cr_a$next $0\cr_a$next[3:0]$9525 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9526 + end + attribute \src "libresoc.v:160931.3-160949.6" + process $proc$libresoc.v:160931$9530 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ov$next[1:0]$9531 $1\xer_ov$next[1:0]$9533 + assign { } { } + assign $0\xer_ov_ok$next[0:0]$9532 $2\xer_ov_ok$next[0:0]$9535 + attribute \src "libresoc.v:160932.5-160932.29" + switch \initial + attribute \src "libresoc.v:160932.9-160932.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$9534 $1\xer_ov$next[1:0]$9533 } { \xer_ov_ok$100 \xer_ov$99 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$9534 $1\xer_ov$next[1:0]$9533 } { \xer_ov_ok$100 \xer_ov$99 } + case + assign $1\xer_ov$next[1:0]$9533 \xer_ov + assign $1\xer_ov_ok$next[0:0]$9534 \xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ov_ok$next[0:0]$9535 1'0 + case + assign $2\xer_ov_ok$next[0:0]$9535 $1\xer_ov_ok$next[0:0]$9534 + end + sync always + update \xer_ov$next $0\xer_ov$next[1:0]$9531 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9532 + end + attribute \src "libresoc.v:160950.3-160968.6" + process $proc$libresoc.v:160950$9536 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$20$next[0:0]$9538 $1\xer_so$20$next[0:0]$9540 + assign $0\xer_so_ok$next[0:0]$9537 $2\xer_so_ok$next[0:0]$9541 + attribute \src "libresoc.v:160951.5-160951.29" + switch \initial + attribute \src "libresoc.v:160951.9-160951.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$9539 $1\xer_so$20$next[0:0]$9540 } { \xer_so_ok$102 \xer_so$101 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$9539 $1\xer_so$20$next[0:0]$9540 } { \xer_so_ok$102 \xer_so$101 } + case + assign $1\xer_so_ok$next[0:0]$9539 \xer_so_ok + assign $1\xer_so$20$next[0:0]$9540 \xer_so$20 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$next[0:0]$9541 1'0 + case + assign $2\xer_so_ok$next[0:0]$9541 $1\xer_so_ok$next[0:0]$9539 + end + sync always + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9537 + update \xer_so$20$next $0\xer_so$20$next[0:0]$9538 + end + attribute \src "libresoc.v:160969.3-160986.6" + process $proc$libresoc.v:160969$9542 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$9543 $2\r_busy$next[0:0]$9545 + attribute \src "libresoc.v:160970.5-160970.29" + switch \initial + attribute \src "libresoc.v:160970.9-160970.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$9544 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$9544 1'0 + case + assign $1\r_busy$next[0:0]$9544 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$9545 1'0 + case + assign $2\r_busy$next[0:0]$9545 $1\r_busy$next[0:0]$9544 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$9543 + end + attribute \src "libresoc.v:160987.3-160999.6" + process $proc$libresoc.v:160987$9546 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$9547 $1\muxid$1$next[1:0]$9548 + attribute \src "libresoc.v:160988.5-160988.29" + switch \initial + attribute \src "libresoc.v:160988.9-160988.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$9548 \muxid$76 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$9548 \muxid$76 + case + assign $1\muxid$1$next[1:0]$9548 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$9547 + end + attribute \src "libresoc.v:161000.3-161041.6" + process $proc$libresoc.v:161000$9549 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\logical_op__data_len$18$next[3:0]$9550 $1\logical_op__data_len$18$next[3:0]$9568 + assign $0\logical_op__fn_unit$3$next[11:0]$9551 $1\logical_op__fn_unit$3$next[11:0]$9569 + assign { } { } + assign { } { } + assign $0\logical_op__input_carry$12$next[1:0]$9554 $1\logical_op__input_carry$12$next[1:0]$9572 + assign $0\logical_op__insn$19$next[31:0]$9555 $1\logical_op__insn$19$next[31:0]$9573 + assign $0\logical_op__insn_type$2$next[6:0]$9556 $1\logical_op__insn_type$2$next[6:0]$9574 + assign $0\logical_op__invert_in$10$next[0:0]$9557 $1\logical_op__invert_in$10$next[0:0]$9575 + assign $0\logical_op__invert_out$13$next[0:0]$9558 $1\logical_op__invert_out$13$next[0:0]$9576 + assign $0\logical_op__is_32bit$16$next[0:0]$9559 $1\logical_op__is_32bit$16$next[0:0]$9577 + assign $0\logical_op__is_signed$17$next[0:0]$9560 $1\logical_op__is_signed$17$next[0:0]$9578 + assign { } { } + assign { } { } + assign $0\logical_op__output_carry$15$next[0:0]$9563 $1\logical_op__output_carry$15$next[0:0]$9581 + assign { } { } + assign { } { } + assign $0\logical_op__write_cr0$14$next[0:0]$9566 $1\logical_op__write_cr0$14$next[0:0]$9584 + assign $0\logical_op__zero_a$11$next[0:0]$9567 $1\logical_op__zero_a$11$next[0:0]$9585 + assign $0\logical_op__imm_data__data$4$next[63:0]$9552 $2\logical_op__imm_data__data$4$next[63:0]$9586 + assign $0\logical_op__imm_data__ok$5$next[0:0]$9553 $2\logical_op__imm_data__ok$5$next[0:0]$9587 + assign $0\logical_op__oe__oe$8$next[0:0]$9561 $2\logical_op__oe__oe$8$next[0:0]$9588 + assign $0\logical_op__oe__ok$9$next[0:0]$9562 $2\logical_op__oe__ok$9$next[0:0]$9589 + assign $0\logical_op__rc__ok$7$next[0:0]$9564 $2\logical_op__rc__ok$7$next[0:0]$9590 + assign $0\logical_op__rc__rc$6$next[0:0]$9565 $2\logical_op__rc__rc$6$next[0:0]$9591 + attribute \src "libresoc.v:161001.5-161001.29" + switch \initial + attribute \src "libresoc.v:161001.9-161001.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$19$next[31:0]$9573 $1\logical_op__data_len$18$next[3:0]$9568 $1\logical_op__is_signed$17$next[0:0]$9578 $1\logical_op__is_32bit$16$next[0:0]$9577 $1\logical_op__output_carry$15$next[0:0]$9581 $1\logical_op__write_cr0$14$next[0:0]$9584 $1\logical_op__invert_out$13$next[0:0]$9576 $1\logical_op__input_carry$12$next[1:0]$9572 $1\logical_op__zero_a$11$next[0:0]$9585 $1\logical_op__invert_in$10$next[0:0]$9575 $1\logical_op__oe__ok$9$next[0:0]$9580 $1\logical_op__oe__oe$8$next[0:0]$9579 $1\logical_op__rc__ok$7$next[0:0]$9582 $1\logical_op__rc__rc$6$next[0:0]$9583 $1\logical_op__imm_data__ok$5$next[0:0]$9571 $1\logical_op__imm_data__data$4$next[63:0]$9570 $1\logical_op__fn_unit$3$next[11:0]$9569 $1\logical_op__insn_type$2$next[6:0]$9574 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$19$next[31:0]$9573 $1\logical_op__data_len$18$next[3:0]$9568 $1\logical_op__is_signed$17$next[0:0]$9578 $1\logical_op__is_32bit$16$next[0:0]$9577 $1\logical_op__output_carry$15$next[0:0]$9581 $1\logical_op__write_cr0$14$next[0:0]$9584 $1\logical_op__invert_out$13$next[0:0]$9576 $1\logical_op__input_carry$12$next[1:0]$9572 $1\logical_op__zero_a$11$next[0:0]$9585 $1\logical_op__invert_in$10$next[0:0]$9575 $1\logical_op__oe__ok$9$next[0:0]$9580 $1\logical_op__oe__oe$8$next[0:0]$9579 $1\logical_op__rc__ok$7$next[0:0]$9582 $1\logical_op__rc__rc$6$next[0:0]$9583 $1\logical_op__imm_data__ok$5$next[0:0]$9571 $1\logical_op__imm_data__data$4$next[63:0]$9570 $1\logical_op__fn_unit$3$next[11:0]$9569 $1\logical_op__insn_type$2$next[6:0]$9574 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } + case + assign $1\logical_op__data_len$18$next[3:0]$9568 \logical_op__data_len$18 + assign $1\logical_op__fn_unit$3$next[11:0]$9569 \logical_op__fn_unit$3 + assign $1\logical_op__imm_data__data$4$next[63:0]$9570 \logical_op__imm_data__data$4 + assign $1\logical_op__imm_data__ok$5$next[0:0]$9571 \logical_op__imm_data__ok$5 + assign $1\logical_op__input_carry$12$next[1:0]$9572 \logical_op__input_carry$12 + assign $1\logical_op__insn$19$next[31:0]$9573 \logical_op__insn$19 + assign $1\logical_op__insn_type$2$next[6:0]$9574 \logical_op__insn_type$2 + assign $1\logical_op__invert_in$10$next[0:0]$9575 \logical_op__invert_in$10 + assign $1\logical_op__invert_out$13$next[0:0]$9576 \logical_op__invert_out$13 + assign $1\logical_op__is_32bit$16$next[0:0]$9577 \logical_op__is_32bit$16 + assign $1\logical_op__is_signed$17$next[0:0]$9578 \logical_op__is_signed$17 + assign $1\logical_op__oe__oe$8$next[0:0]$9579 \logical_op__oe__oe$8 + assign $1\logical_op__oe__ok$9$next[0:0]$9580 \logical_op__oe__ok$9 + assign $1\logical_op__output_carry$15$next[0:0]$9581 \logical_op__output_carry$15 + assign $1\logical_op__rc__ok$7$next[0:0]$9582 \logical_op__rc__ok$7 + assign $1\logical_op__rc__rc$6$next[0:0]$9583 \logical_op__rc__rc$6 + assign $1\logical_op__write_cr0$14$next[0:0]$9584 \logical_op__write_cr0$14 + assign $1\logical_op__zero_a$11$next[0:0]$9585 \logical_op__zero_a$11 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\logical_op__imm_data__data$4$next[63:0]$9586 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$5$next[0:0]$9587 1'0 + assign $2\logical_op__rc__rc$6$next[0:0]$9591 1'0 + assign $2\logical_op__rc__ok$7$next[0:0]$9590 1'0 + assign $2\logical_op__oe__oe$8$next[0:0]$9588 1'0 + assign $2\logical_op__oe__ok$9$next[0:0]$9589 1'0 + case + assign $2\logical_op__imm_data__data$4$next[63:0]$9586 $1\logical_op__imm_data__data$4$next[63:0]$9570 + assign $2\logical_op__imm_data__ok$5$next[0:0]$9587 $1\logical_op__imm_data__ok$5$next[0:0]$9571 + assign $2\logical_op__oe__oe$8$next[0:0]$9588 $1\logical_op__oe__oe$8$next[0:0]$9579 + assign $2\logical_op__oe__ok$9$next[0:0]$9589 $1\logical_op__oe__ok$9$next[0:0]$9580 + assign $2\logical_op__rc__ok$7$next[0:0]$9590 $1\logical_op__rc__ok$7$next[0:0]$9582 + assign $2\logical_op__rc__rc$6$next[0:0]$9591 $1\logical_op__rc__rc$6$next[0:0]$9583 + end + sync always + update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$9550 + update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[11:0]$9551 + update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$9552 + update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$9553 + update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$9554 + update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$9555 + update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$9556 + update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$9557 + update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$9558 + update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$9559 + update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$9560 + update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$9561 + update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$9562 + update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$9563 + update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$9564 + update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$9565 + update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$9566 + update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$9567 + end + connect \$74 $and$libresoc.v:160722$9469_Y + connect \cr_a$68 4'0000 + connect \cr_a_ok$69 1'0 + connect \xer_so_ok$72 1'0 + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_so_ok$102 \xer_so$101 } { \output_xer_so_ok \output_xer_so$64 } + connect { \xer_ov_ok$100 \xer_ov$99 } { \output_xer_ov_ok \output_xer_ov$63 } + connect { \cr_a_ok$98 \cr_a$97 } { \output_cr_a_ok \output_cr_a$62 } + connect { \o_ok$96 \o$95 } { \output_o_ok$61 \output_o$60 } + connect { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } { \output_logical_op__insn$59 \output_logical_op__data_len$58 \output_logical_op__is_signed$57 \output_logical_op__is_32bit$56 \output_logical_op__output_carry$55 \output_logical_op__write_cr0$54 \output_logical_op__invert_out$53 \output_logical_op__input_carry$52 \output_logical_op__zero_a$51 \output_logical_op__invert_in$50 \output_logical_op__oe__ok$49 \output_logical_op__oe__oe$48 \output_logical_op__rc__ok$47 \output_logical_op__rc__rc$46 \output_logical_op__imm_data__ok$45 \output_logical_op__imm_data__data$44 \output_logical_op__fn_unit$43 \output_logical_op__insn_type$42 } + connect \muxid$76 \output_muxid$41 + connect \p_valid_i_p_ready_o \$74 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$73 \p_valid_i + connect { \xer_so_ok$71 \output_xer_so } { 1'0 \output_stage_xer_so$40 } + connect { \xer_ov_ok$70 \output_xer_ov } { \output_stage_xer_ov_ok \output_stage_xer_ov } + connect { \cr_a_ok$67 \output_cr_a } 5'00000 + connect { \output_o_ok \output_o } { \output_stage_o_ok \output_stage_o } + connect { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in \output_logical_op__oe__ok \output_logical_op__oe__oe \output_logical_op__rc__ok \output_logical_op__rc__rc \output_logical_op__imm_data__ok \output_logical_op__imm_data__data \output_logical_op__fn_unit \output_logical_op__insn_type } { \output_stage_logical_op__insn$39 \output_stage_logical_op__data_len$38 \output_stage_logical_op__is_signed$37 \output_stage_logical_op__is_32bit$36 \output_stage_logical_op__output_carry$35 \output_stage_logical_op__write_cr0$34 \output_stage_logical_op__invert_out$33 \output_stage_logical_op__input_carry$32 \output_stage_logical_op__zero_a$31 \output_stage_logical_op__invert_in$30 \output_stage_logical_op__oe__ok$29 \output_stage_logical_op__oe__oe$28 \output_stage_logical_op__rc__ok$27 \output_stage_logical_op__rc__rc$26 \output_stage_logical_op__imm_data__ok$25 \output_stage_logical_op__imm_data__data$24 \output_stage_logical_op__fn_unit$23 \output_stage_logical_op__insn_type$22 } + connect \output_muxid \output_stage_muxid$21 + connect \output_stage_remainder \remainder + connect \output_stage_quotient_root \quotient_root + connect \output_stage_div_by_zero \div_by_zero + connect \output_stage_dive_abs_ov64 \dive_abs_ov64 + connect \output_stage_dive_abs_ov32 \dive_abs_ov32 + connect \output_stage_dividend_neg \dividend_neg + connect \output_stage_divisor_neg \divisor_neg + connect \output_stage_xer_so \xer_so + connect \rb$66 \rb + connect \ra$65 \ra + connect { \output_stage_logical_op__insn \output_stage_logical_op__data_len \output_stage_logical_op__is_signed \output_stage_logical_op__is_32bit \output_stage_logical_op__output_carry \output_stage_logical_op__write_cr0 \output_stage_logical_op__invert_out \output_stage_logical_op__input_carry \output_stage_logical_op__zero_a \output_stage_logical_op__invert_in \output_stage_logical_op__oe__ok \output_stage_logical_op__oe__oe \output_stage_logical_op__rc__ok \output_stage_logical_op__rc__rc \output_stage_logical_op__imm_data__ok \output_stage_logical_op__imm_data__data \output_stage_logical_op__fn_unit \output_stage_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \output_stage_muxid \muxid +end +attribute \src "libresoc.v:161078.1-162056.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0" +attribute \generator "nMigen" +module \pipe_middle_0 + attribute \src "libresoc.v:161981.3-161995.6" + wire $0\div_by_zero$54$next[0:0]$9820 + attribute \src "libresoc.v:161655.3-161656.47" + wire $0\div_by_zero$54[0:0]$9655 + attribute \src "libresoc.v:161101.7-161101.30" + wire $0\div_by_zero$54[0:0]$9837 + attribute \src "libresoc.v:161777.3-161788.6" + wire width 64 $0\div_state_next_divisor[63:0] + attribute \src "libresoc.v:161765.3-161776.6" + wire width 128 $0\div_state_next_i_dividend_quotient[127:0] + attribute \src "libresoc.v:161753.3-161764.6" + wire width 7 $0\div_state_next_i_q_bits_known[6:0] + attribute \src "libresoc.v:161951.3-161965.6" + wire $0\dive_abs_ov32$52$next[0:0]$9812 + attribute \src "libresoc.v:161659.3-161660.51" + wire $0\dive_abs_ov32$52[0:0]$9659 + attribute \src "libresoc.v:161125.7-161125.32" + wire $0\dive_abs_ov32$52[0:0]$9839 + attribute \src "libresoc.v:161966.3-161980.6" + wire $0\dive_abs_ov64$53$next[0:0]$9816 + attribute \src "libresoc.v:161657.3-161658.51" + wire $0\dive_abs_ov64$53[0:0]$9657 + attribute \src "libresoc.v:161133.7-161133.32" + wire $0\dive_abs_ov64$53[0:0]$9841 + attribute \src "libresoc.v:161996.3-162010.6" + wire width 128 $0\dividend$68$next[127:0]$9824 + attribute \src "libresoc.v:161653.3-161654.41" + wire width 128 $0\dividend$68[127:0]$9653 + attribute \src "libresoc.v:161139.15-161139.68" + wire width 128 $0\dividend$68[127:0]$9843 + attribute \src "libresoc.v:161936.3-161950.6" + wire $0\dividend_neg$51$next[0:0]$9808 + attribute \src "libresoc.v:161661.3-161662.49" + wire $0\dividend_neg$51[0:0]$9661 + attribute \src "libresoc.v:161147.7-161147.31" + wire $0\dividend_neg$51[0:0]$9845 + attribute \src "libresoc.v:161921.3-161935.6" + wire $0\divisor_neg$50$next[0:0]$9804 + attribute \src "libresoc.v:161663.3-161664.47" + wire $0\divisor_neg$50[0:0]$9663 + attribute \src "libresoc.v:161155.7-161155.30" + wire $0\divisor_neg$50[0:0]$9847 + attribute \src "libresoc.v:162011.3-162025.6" + wire width 64 $0\divisor_radicand$65$next[63:0]$9828 + attribute \src "libresoc.v:161651.3-161652.57" + wire width 64 $0\divisor_radicand$65[63:0]$9651 + attribute \src "libresoc.v:161161.14-161161.58" + wire width 64 $0\divisor_radicand$65[63:0]$9849 + attribute \src "libresoc.v:161789.3-161816.6" + wire $0\empty$next[0:0]$9721 + attribute \src "libresoc.v:161709.3-161710.27" + wire $0\empty[0:0] + attribute \src "libresoc.v:161079.7-161079.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:161832.3-161875.6" + wire width 4 $0\logical_op__data_len$45$next[3:0]$9731 + attribute \src "libresoc.v:161703.3-161704.65" + wire width 4 $0\logical_op__data_len$45[3:0]$9703 + attribute \src "libresoc.v:161173.13-161173.45" + wire width 4 $0\logical_op__data_len$45[3:0]$9852 + attribute \src "libresoc.v:161832.3-161875.6" + wire width 12 $0\logical_op__fn_unit$30$next[11:0]$9732 + attribute \src "libresoc.v:161673.3-161674.63" + wire width 12 $0\logical_op__fn_unit$30[11:0]$9673 + attribute \src "libresoc.v:161220.14-161220.48" + wire width 12 $0\logical_op__fn_unit$30[11:0]$9854 + attribute \src "libresoc.v:161832.3-161875.6" + wire width 64 $0\logical_op__imm_data__data$31$next[63:0]$9733 + attribute \src "libresoc.v:161675.3-161676.77" + wire width 64 $0\logical_op__imm_data__data$31[63:0]$9675 + attribute \src "libresoc.v:161226.14-161226.68" + wire width 64 $0\logical_op__imm_data__data$31[63:0]$9856 + attribute \src "libresoc.v:161832.3-161875.6" + wire $0\logical_op__imm_data__ok$32$next[0:0]$9734 + attribute \src "libresoc.v:161677.3-161678.73" + wire $0\logical_op__imm_data__ok$32[0:0]$9677 + attribute \src "libresoc.v:161234.7-161234.43" + wire $0\logical_op__imm_data__ok$32[0:0]$9858 + attribute \src "libresoc.v:161832.3-161875.6" + wire width 2 $0\logical_op__input_carry$39$next[1:0]$9735 + attribute \src "libresoc.v:161691.3-161692.71" + wire width 2 $0\logical_op__input_carry$39[1:0]$9691 + attribute \src "libresoc.v:161256.13-161256.48" + wire width 2 $0\logical_op__input_carry$39[1:0]$9860 + attribute \src "libresoc.v:161832.3-161875.6" + wire width 32 $0\logical_op__insn$46$next[31:0]$9736 + attribute \src "libresoc.v:161705.3-161706.57" + wire width 32 $0\logical_op__insn$46[31:0]$9705 + attribute \src "libresoc.v:161264.14-161264.43" + wire width 32 $0\logical_op__insn$46[31:0]$9862 + attribute \src "libresoc.v:161832.3-161875.6" + wire width 7 $0\logical_op__insn_type$29$next[6:0]$9737 + attribute \src "libresoc.v:161671.3-161672.67" + wire width 7 $0\logical_op__insn_type$29[6:0]$9671 + attribute \src "libresoc.v:161494.13-161494.47" + wire width 7 $0\logical_op__insn_type$29[6:0]$9864 + attribute \src "libresoc.v:161832.3-161875.6" + wire $0\logical_op__invert_in$37$next[0:0]$9738 + attribute \src "libresoc.v:161687.3-161688.67" + wire $0\logical_op__invert_in$37[0:0]$9687 + attribute \src "libresoc.v:161502.7-161502.40" + wire $0\logical_op__invert_in$37[0:0]$9866 + attribute \src "libresoc.v:161832.3-161875.6" + wire $0\logical_op__invert_out$40$next[0:0]$9739 + attribute \src "libresoc.v:161693.3-161694.69" + wire $0\logical_op__invert_out$40[0:0]$9693 + attribute \src "libresoc.v:161510.7-161510.41" + wire $0\logical_op__invert_out$40[0:0]$9868 + attribute \src "libresoc.v:161832.3-161875.6" + wire $0\logical_op__is_32bit$43$next[0:0]$9740 + attribute \src "libresoc.v:161699.3-161700.65" + wire $0\logical_op__is_32bit$43[0:0]$9699 + attribute \src "libresoc.v:161518.7-161518.39" + wire $0\logical_op__is_32bit$43[0:0]$9870 + attribute \src "libresoc.v:161832.3-161875.6" + wire $0\logical_op__is_signed$44$next[0:0]$9741 + attribute \src "libresoc.v:161701.3-161702.67" + wire $0\logical_op__is_signed$44[0:0]$9701 + attribute \src "libresoc.v:161526.7-161526.40" + wire $0\logical_op__is_signed$44[0:0]$9872 + attribute \src "libresoc.v:161832.3-161875.6" + wire $0\logical_op__oe__oe$35$next[0:0]$9742 + attribute \src "libresoc.v:161683.3-161684.61" + wire $0\logical_op__oe__oe$35[0:0]$9683 + attribute \src "libresoc.v:161532.7-161532.37" + wire $0\logical_op__oe__oe$35[0:0]$9874 + attribute \src "libresoc.v:161832.3-161875.6" + wire $0\logical_op__oe__ok$36$next[0:0]$9743 + attribute \src "libresoc.v:161685.3-161686.61" + wire $0\logical_op__oe__ok$36[0:0]$9685 + attribute \src "libresoc.v:161540.7-161540.37" + wire $0\logical_op__oe__ok$36[0:0]$9876 + attribute \src "libresoc.v:161832.3-161875.6" + wire $0\logical_op__output_carry$42$next[0:0]$9744 + attribute \src "libresoc.v:161697.3-161698.73" + wire $0\logical_op__output_carry$42[0:0]$9697 + attribute \src "libresoc.v:161550.7-161550.43" + wire $0\logical_op__output_carry$42[0:0]$9878 + attribute \src "libresoc.v:161832.3-161875.6" + wire $0\logical_op__rc__ok$34$next[0:0]$9745 + attribute \src "libresoc.v:161681.3-161682.61" + wire $0\logical_op__rc__ok$34[0:0]$9681 + attribute \src "libresoc.v:161556.7-161556.37" + wire $0\logical_op__rc__ok$34[0:0]$9880 + attribute \src "libresoc.v:161832.3-161875.6" + wire $0\logical_op__rc__rc$33$next[0:0]$9746 + attribute \src "libresoc.v:161679.3-161680.61" + wire $0\logical_op__rc__rc$33[0:0]$9679 + attribute \src "libresoc.v:161564.7-161564.37" + wire $0\logical_op__rc__rc$33[0:0]$9882 + attribute \src "libresoc.v:161832.3-161875.6" + wire $0\logical_op__write_cr0$41$next[0:0]$9747 + attribute \src "libresoc.v:161695.3-161696.67" + wire $0\logical_op__write_cr0$41[0:0]$9695 + attribute \src "libresoc.v:161574.7-161574.40" + wire $0\logical_op__write_cr0$41[0:0]$9884 + attribute \src "libresoc.v:161832.3-161875.6" + wire $0\logical_op__zero_a$38$next[0:0]$9748 + attribute \src "libresoc.v:161689.3-161690.61" + wire $0\logical_op__zero_a$38[0:0]$9689 + attribute \src "libresoc.v:161582.7-161582.37" + wire $0\logical_op__zero_a$38[0:0]$9886 + attribute \src "libresoc.v:161817.3-161831.6" + wire width 2 $0\muxid$28$next[1:0]$9727 + attribute \src "libresoc.v:161707.3-161708.35" + wire width 2 $0\muxid$28[1:0]$9707 + attribute \src "libresoc.v:161590.13-161590.30" + wire width 2 $0\muxid$28[1:0]$9888 + attribute \src "libresoc.v:162026.3-162040.6" + wire width 2 $0\operation$69$next[1:0]$9832 + attribute \src "libresoc.v:161649.3-161650.43" + wire width 2 $0\operation$69[1:0]$9649 + attribute \src "libresoc.v:161600.13-161600.34" + wire width 2 $0\operation$69[1:0]$9890 + attribute \src "libresoc.v:161876.3-161890.6" + wire width 64 $0\ra$47$next[63:0]$9792 + attribute \src "libresoc.v:161669.3-161670.29" + wire width 64 $0\ra$47[63:0]$9669 + attribute \src "libresoc.v:161614.14-161614.44" + wire width 64 $0\ra$47[63:0]$9892 + attribute \src "libresoc.v:161891.3-161905.6" + wire width 64 $0\rb$48$next[63:0]$9796 + attribute \src "libresoc.v:161667.3-161668.29" + wire width 64 $0\rb$48[63:0]$9667 + attribute \src "libresoc.v:161622.14-161622.44" + wire width 64 $0\rb$48[63:0]$9894 + attribute \src "libresoc.v:161744.3-161752.6" + wire width 128 $0\saved_state_dividend_quotient$next[127:0]$9715 + attribute \src "libresoc.v:161711.3-161712.75" + wire width 128 $0\saved_state_dividend_quotient[127:0] + attribute \src "libresoc.v:161735.3-161743.6" + wire width 7 $0\saved_state_q_bits_known$next[6:0]$9712 + attribute \src "libresoc.v:161713.3-161714.65" + wire width 7 $0\saved_state_q_bits_known[6:0] + attribute \src "libresoc.v:161906.3-161920.6" + wire $0\xer_so$49$next[0:0]$9800 + attribute \src "libresoc.v:161665.3-161666.37" + wire $0\xer_so$49[0:0]$9665 + attribute \src "libresoc.v:161640.7-161640.25" + wire $0\xer_so$49[0:0]$9898 + attribute \src "libresoc.v:161981.3-161995.6" + wire $1\div_by_zero$54$next[0:0]$9821 + attribute \src "libresoc.v:161777.3-161788.6" + wire width 64 $1\div_state_next_divisor[63:0] + attribute \src "libresoc.v:161765.3-161776.6" + wire width 128 $1\div_state_next_i_dividend_quotient[127:0] + attribute \src "libresoc.v:161753.3-161764.6" + wire width 7 $1\div_state_next_i_q_bits_known[6:0] + attribute \src "libresoc.v:161951.3-161965.6" + wire $1\dive_abs_ov32$52$next[0:0]$9813 + attribute \src "libresoc.v:161966.3-161980.6" + wire $1\dive_abs_ov64$53$next[0:0]$9817 + attribute \src "libresoc.v:161996.3-162010.6" + wire width 128 $1\dividend$68$next[127:0]$9825 + attribute \src "libresoc.v:161936.3-161950.6" + wire $1\dividend_neg$51$next[0:0]$9809 + attribute \src "libresoc.v:161921.3-161935.6" + wire $1\divisor_neg$50$next[0:0]$9805 + attribute \src "libresoc.v:162011.3-162025.6" + wire width 64 $1\divisor_radicand$65$next[63:0]$9829 + attribute \src "libresoc.v:161789.3-161816.6" + wire $1\empty$next[0:0]$9722 + attribute \src "libresoc.v:161165.7-161165.19" + wire $1\empty[0:0] + attribute \src "libresoc.v:161832.3-161875.6" + wire width 4 $1\logical_op__data_len$45$next[3:0]$9749 + attribute \src "libresoc.v:161832.3-161875.6" + wire width 12 $1\logical_op__fn_unit$30$next[11:0]$9750 + attribute \src "libresoc.v:161832.3-161875.6" + wire width 64 $1\logical_op__imm_data__data$31$next[63:0]$9751 + attribute \src "libresoc.v:161832.3-161875.6" + wire $1\logical_op__imm_data__ok$32$next[0:0]$9752 + attribute \src "libresoc.v:161832.3-161875.6" + wire width 2 $1\logical_op__input_carry$39$next[1:0]$9753 + attribute \src "libresoc.v:161832.3-161875.6" + wire width 32 $1\logical_op__insn$46$next[31:0]$9754 + attribute \src "libresoc.v:161832.3-161875.6" + wire width 7 $1\logical_op__insn_type$29$next[6:0]$9755 + attribute \src "libresoc.v:161832.3-161875.6" + wire $1\logical_op__invert_in$37$next[0:0]$9756 + attribute \src "libresoc.v:161832.3-161875.6" + wire $1\logical_op__invert_out$40$next[0:0]$9757 + attribute \src "libresoc.v:161832.3-161875.6" + wire $1\logical_op__is_32bit$43$next[0:0]$9758 + attribute \src "libresoc.v:161832.3-161875.6" + wire $1\logical_op__is_signed$44$next[0:0]$9759 + attribute \src "libresoc.v:161832.3-161875.6" + wire $1\logical_op__oe__oe$35$next[0:0]$9760 + attribute \src "libresoc.v:161832.3-161875.6" + wire $1\logical_op__oe__ok$36$next[0:0]$9761 + attribute \src "libresoc.v:161832.3-161875.6" + wire $1\logical_op__output_carry$42$next[0:0]$9762 + attribute \src "libresoc.v:161832.3-161875.6" + wire $1\logical_op__rc__ok$34$next[0:0]$9763 + attribute \src "libresoc.v:161832.3-161875.6" + wire $1\logical_op__rc__rc$33$next[0:0]$9764 + attribute \src "libresoc.v:161832.3-161875.6" + wire $1\logical_op__write_cr0$41$next[0:0]$9765 + attribute \src "libresoc.v:161832.3-161875.6" + wire $1\logical_op__zero_a$38$next[0:0]$9766 + attribute \src "libresoc.v:161817.3-161831.6" + wire width 2 $1\muxid$28$next[1:0]$9728 + attribute \src "libresoc.v:162026.3-162040.6" + wire width 2 $1\operation$69$next[1:0]$9833 + attribute \src "libresoc.v:161876.3-161890.6" + wire width 64 $1\ra$47$next[63:0]$9793 + attribute \src "libresoc.v:161891.3-161905.6" + wire width 64 $1\rb$48$next[63:0]$9797 + attribute \src "libresoc.v:161744.3-161752.6" + wire width 128 $1\saved_state_dividend_quotient$next[127:0]$9716 + attribute \src "libresoc.v:161628.15-161628.84" + wire width 128 $1\saved_state_dividend_quotient[127:0] + attribute \src "libresoc.v:161735.3-161743.6" + wire width 7 $1\saved_state_q_bits_known$next[6:0]$9713 + attribute \src "libresoc.v:161632.13-161632.45" + wire width 7 $1\saved_state_q_bits_known[6:0] + attribute \src "libresoc.v:161906.3-161920.6" + wire $1\xer_so$49$next[0:0]$9801 + attribute \src "libresoc.v:161981.3-161995.6" + wire $2\div_by_zero$54$next[0:0]$9822 + attribute \src "libresoc.v:161951.3-161965.6" + wire $2\dive_abs_ov32$52$next[0:0]$9814 + attribute \src "libresoc.v:161966.3-161980.6" + wire $2\dive_abs_ov64$53$next[0:0]$9818 + attribute \src "libresoc.v:161996.3-162010.6" + wire width 128 $2\dividend$68$next[127:0]$9826 + attribute \src "libresoc.v:161936.3-161950.6" + wire $2\dividend_neg$51$next[0:0]$9810 + attribute \src "libresoc.v:161921.3-161935.6" + wire $2\divisor_neg$50$next[0:0]$9806 + attribute \src "libresoc.v:162011.3-162025.6" + wire width 64 $2\divisor_radicand$65$next[63:0]$9830 + attribute \src "libresoc.v:161789.3-161816.6" + wire $2\empty$next[0:0]$9723 + attribute \src "libresoc.v:161832.3-161875.6" + wire width 4 $2\logical_op__data_len$45$next[3:0]$9767 + attribute \src "libresoc.v:161832.3-161875.6" + wire width 12 $2\logical_op__fn_unit$30$next[11:0]$9768 + attribute \src "libresoc.v:161832.3-161875.6" + wire width 64 $2\logical_op__imm_data__data$31$next[63:0]$9769 + attribute \src "libresoc.v:161832.3-161875.6" + wire $2\logical_op__imm_data__ok$32$next[0:0]$9770 + attribute \src "libresoc.v:161832.3-161875.6" + wire width 2 $2\logical_op__input_carry$39$next[1:0]$9771 + attribute \src "libresoc.v:161832.3-161875.6" + wire width 32 $2\logical_op__insn$46$next[31:0]$9772 + attribute \src "libresoc.v:161832.3-161875.6" + wire width 7 $2\logical_op__insn_type$29$next[6:0]$9773 + attribute \src "libresoc.v:161832.3-161875.6" + wire $2\logical_op__invert_in$37$next[0:0]$9774 + attribute \src "libresoc.v:161832.3-161875.6" + wire $2\logical_op__invert_out$40$next[0:0]$9775 + attribute \src "libresoc.v:161832.3-161875.6" + wire $2\logical_op__is_32bit$43$next[0:0]$9776 + attribute \src "libresoc.v:161832.3-161875.6" + wire $2\logical_op__is_signed$44$next[0:0]$9777 + attribute \src "libresoc.v:161832.3-161875.6" + wire $2\logical_op__oe__oe$35$next[0:0]$9778 + attribute \src "libresoc.v:161832.3-161875.6" + wire $2\logical_op__oe__ok$36$next[0:0]$9779 + attribute \src "libresoc.v:161832.3-161875.6" + wire $2\logical_op__output_carry$42$next[0:0]$9780 + attribute \src "libresoc.v:161832.3-161875.6" + wire $2\logical_op__rc__ok$34$next[0:0]$9781 + attribute \src "libresoc.v:161832.3-161875.6" + wire $2\logical_op__rc__rc$33$next[0:0]$9782 + attribute \src "libresoc.v:161832.3-161875.6" + wire $2\logical_op__write_cr0$41$next[0:0]$9783 + attribute \src "libresoc.v:161832.3-161875.6" + wire $2\logical_op__zero_a$38$next[0:0]$9784 + attribute \src "libresoc.v:161817.3-161831.6" + wire width 2 $2\muxid$28$next[1:0]$9729 + attribute \src "libresoc.v:162026.3-162040.6" + wire width 2 $2\operation$69$next[1:0]$9834 + attribute \src "libresoc.v:161876.3-161890.6" + wire width 64 $2\ra$47$next[63:0]$9794 + attribute \src "libresoc.v:161891.3-161905.6" + wire width 64 $2\rb$48$next[63:0]$9798 + attribute \src "libresoc.v:161906.3-161920.6" + wire $2\xer_so$49$next[0:0]$9802 + attribute \src "libresoc.v:161789.3-161816.6" + wire $3\empty$next[0:0]$9724 + attribute \src "libresoc.v:161832.3-161875.6" + wire width 64 $3\logical_op__imm_data__data$31$next[63:0]$9785 + attribute \src "libresoc.v:161832.3-161875.6" + wire $3\logical_op__imm_data__ok$32$next[0:0]$9786 + attribute \src "libresoc.v:161832.3-161875.6" + wire $3\logical_op__oe__oe$35$next[0:0]$9787 + attribute \src "libresoc.v:161832.3-161875.6" + wire $3\logical_op__oe__ok$36$next[0:0]$9788 + attribute \src "libresoc.v:161832.3-161875.6" + wire $3\logical_op__rc__ok$34$next[0:0]$9789 + attribute \src "libresoc.v:161832.3-161875.6" + wire $3\logical_op__rc__rc$33$next[0:0]$9790 + attribute \src "libresoc.v:161789.3-161816.6" + wire $4\empty$next[0:0]$9725 + attribute \src "libresoc.v:161647.18-161647.98" + wire $and$libresoc.v:161647$9646_Y + attribute \src "libresoc.v:161648.18-161648.107" + wire $and$libresoc.v:161648$9647_Y + attribute \src "libresoc.v:161644.18-161644.92" + wire width 192 $extend$libresoc.v:161644$9642_Y + attribute \src "libresoc.v:161646.18-161646.119" + wire $ge$libresoc.v:161646$9645_Y + attribute \src "libresoc.v:161645.18-161645.93" + wire $not$libresoc.v:161645$9644_Y + attribute \src "libresoc.v:161644.18-161644.92" + wire width 192 $pos$libresoc.v:161644$9643_Y + attribute \src "libresoc.v:161643.18-161643.138" + wire width 191 $sshl$libresoc.v:161643$9641_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" + wire width 192 \$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" + wire width 191 \$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" + wire \$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" + wire \$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" + wire \$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + wire \$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 65 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire input 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire output 62 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \div_by_zero$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \div_by_zero$54$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:89" + wire width 128 \div_state_init_dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 \div_state_init_o_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 \div_state_init_o_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:59" + wire width 64 \div_state_next_divisor + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 \div_state_next_i_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 \div_state_next_i_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 \div_state_next_o_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 \div_state_next_o_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire input 28 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire output 60 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \dive_abs_ov32$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \dive_abs_ov32$52$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire input 29 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire output 61 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \dive_abs_ov64$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \dive_abs_ov64$53$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 input 31 \dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \dividend$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \dividend$68$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire input 27 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire output 59 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \dividend_neg$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \dividend_neg$51$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire input 26 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire output 58 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \divisor_neg$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \divisor_neg$50$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 input 32 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \divisor_radicand$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \divisor_radicand$65$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:140" + wire \empty + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:140" + wire \empty$next + attribute \src "libresoc.v:161079.7-161079.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 53 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$45$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 6 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 38 \logical_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_op__fn_unit$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_op__fn_unit$30$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$31$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 39 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$32$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 15 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 47 \logical_op__input_carry$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$39$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 54 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$46$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 37 \logical_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$29$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 45 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$37$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 48 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$40$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 51 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$43$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 52 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$44$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$35$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 43 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$36$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 44 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 50 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$42$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$34$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 42 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$33$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 49 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$41$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 46 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$38$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 36 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$28$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 35 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 34 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 input 33 \operation + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \operation$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \operation$69$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 64 output 63 \quotient_root + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 23 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 55 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$47$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 56 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$48$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" + wire width 192 output 64 \remainder + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 \saved_state_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 \saved_state_dividend_quotient$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 \saved_state_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 \saved_state_q_bits_known$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 25 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 57 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$49$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" + cell $and $and$libresoc.v:161647$9646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$59 + connect \B \$61 + connect \Y $and$libresoc.v:161647$9646_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + cell $and $and$libresoc.v:161648$9647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:161648$9647_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" + cell $pos $extend$libresoc.v:161644$9642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 191 + parameter \Y_WIDTH 192 + connect \A \$56 + connect \Y $extend$libresoc.v:161644$9642_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" + cell $ge $ge$libresoc.v:161646$9645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \saved_state_q_bits_known + connect \B 6'111111 + connect \Y $ge$libresoc.v:161646$9645_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" + cell $not $not$libresoc.v:161645$9644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \empty + connect \Y $not$libresoc.v:161645$9644_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" + cell $pos $pos$libresoc.v:161644$9643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $extend$libresoc.v:161644$9642_Y + connect \Y $pos$libresoc.v:161644$9643_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" + cell $sshl $sshl$libresoc.v:161643$9641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 191 + connect \A \div_state_next_o_dividend_quotient [127:64] + connect \B 7'1000000 + connect \Y $sshl$libresoc.v:161643$9641_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:161715.18-161719.4" + cell \div_state_init \div_state_init + connect \dividend \div_state_init_dividend + connect \o_dividend_quotient \div_state_init_o_dividend_quotient + connect \o_q_bits_known \div_state_init_o_q_bits_known + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:161720.18-161726.4" + cell \div_state_next \div_state_next + connect \divisor \div_state_next_divisor + connect \i_dividend_quotient \div_state_next_i_dividend_quotient + connect \i_q_bits_known \div_state_next_i_q_bits_known + connect \o_dividend_quotient \div_state_next_o_dividend_quotient + connect \o_q_bits_known \div_state_next_o_q_bits_known + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:161727.10-161730.4" + cell \n$80 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:161731.10-161734.4" + cell \p$79 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:161079.7-161079.20" + process $proc$libresoc.v:161079$9835 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:161101.7-161101.30" + process $proc$libresoc.v:161101$9836 + assign { } { } + assign $0\div_by_zero$54[0:0]$9837 1'0 + sync always + sync init + update \div_by_zero$54 $0\div_by_zero$54[0:0]$9837 + end + attribute \src "libresoc.v:161125.7-161125.32" + process $proc$libresoc.v:161125$9838 + assign { } { } + assign $0\dive_abs_ov32$52[0:0]$9839 1'0 + sync always + sync init + update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$9839 + end + attribute \src "libresoc.v:161133.7-161133.32" + process $proc$libresoc.v:161133$9840 + assign { } { } + assign $0\dive_abs_ov64$53[0:0]$9841 1'0 + sync always + sync init + update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$9841 + end + attribute \src "libresoc.v:161139.15-161139.68" + process $proc$libresoc.v:161139$9842 + assign { } { } + assign $0\dividend$68[127:0]$9843 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dividend$68 $0\dividend$68[127:0]$9843 + end + attribute \src "libresoc.v:161147.7-161147.31" + process $proc$libresoc.v:161147$9844 + assign { } { } + assign $0\dividend_neg$51[0:0]$9845 1'0 + sync always + sync init + update \dividend_neg$51 $0\dividend_neg$51[0:0]$9845 + end + attribute \src "libresoc.v:161155.7-161155.30" + process $proc$libresoc.v:161155$9846 + assign { } { } + assign $0\divisor_neg$50[0:0]$9847 1'0 + sync always + sync init + update \divisor_neg$50 $0\divisor_neg$50[0:0]$9847 + end + attribute \src "libresoc.v:161161.14-161161.58" + process $proc$libresoc.v:161161$9848 + assign { } { } + assign $0\divisor_radicand$65[63:0]$9849 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$9849 + end + attribute \src "libresoc.v:161165.7-161165.19" + process $proc$libresoc.v:161165$9850 + assign { } { } + assign $1\empty[0:0] 1'1 + sync always + sync init + update \empty $1\empty[0:0] + end + attribute \src "libresoc.v:161173.13-161173.45" + process $proc$libresoc.v:161173$9851 + assign { } { } + assign $0\logical_op__data_len$45[3:0]$9852 4'0000 + sync always + sync init + update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$9852 + end + attribute \src "libresoc.v:161220.14-161220.48" + process $proc$libresoc.v:161220$9853 + assign { } { } + assign $0\logical_op__fn_unit$30[11:0]$9854 12'000000000000 + sync always + sync init + update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[11:0]$9854 + end + attribute \src "libresoc.v:161226.14-161226.68" + process $proc$libresoc.v:161226$9855 + assign { } { } + assign $0\logical_op__imm_data__data$31[63:0]$9856 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$9856 + end + attribute \src "libresoc.v:161234.7-161234.43" + process $proc$libresoc.v:161234$9857 + assign { } { } + assign $0\logical_op__imm_data__ok$32[0:0]$9858 1'0 + sync always + sync init + update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$9858 + end + attribute \src "libresoc.v:161256.13-161256.48" + process $proc$libresoc.v:161256$9859 + assign { } { } + assign $0\logical_op__input_carry$39[1:0]$9860 2'00 + sync always + sync init + update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$9860 + end + attribute \src "libresoc.v:161264.14-161264.43" + process $proc$libresoc.v:161264$9861 + assign { } { } + assign $0\logical_op__insn$46[31:0]$9862 0 + sync always + sync init + update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$9862 + end + attribute \src "libresoc.v:161494.13-161494.47" + process $proc$libresoc.v:161494$9863 + assign { } { } + assign $0\logical_op__insn_type$29[6:0]$9864 7'0000000 + sync always + sync init + update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$9864 + end + attribute \src "libresoc.v:161502.7-161502.40" + process $proc$libresoc.v:161502$9865 + assign { } { } + assign $0\logical_op__invert_in$37[0:0]$9866 1'0 + sync always + sync init + update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$9866 + end + attribute \src "libresoc.v:161510.7-161510.41" + process $proc$libresoc.v:161510$9867 + assign { } { } + assign $0\logical_op__invert_out$40[0:0]$9868 1'0 + sync always + sync init + update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$9868 + end + attribute \src "libresoc.v:161518.7-161518.39" + process $proc$libresoc.v:161518$9869 + assign { } { } + assign $0\logical_op__is_32bit$43[0:0]$9870 1'0 + sync always + sync init + update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$9870 + end + attribute \src "libresoc.v:161526.7-161526.40" + process $proc$libresoc.v:161526$9871 + assign { } { } + assign $0\logical_op__is_signed$44[0:0]$9872 1'0 + sync always + sync init + update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$9872 + end + attribute \src "libresoc.v:161532.7-161532.37" + process $proc$libresoc.v:161532$9873 + assign { } { } + assign $0\logical_op__oe__oe$35[0:0]$9874 1'0 + sync always + sync init + update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$9874 + end + attribute \src "libresoc.v:161540.7-161540.37" + process $proc$libresoc.v:161540$9875 + assign { } { } + assign $0\logical_op__oe__ok$36[0:0]$9876 1'0 + sync always + sync init + update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$9876 + end + attribute \src "libresoc.v:161550.7-161550.43" + process $proc$libresoc.v:161550$9877 + assign { } { } + assign $0\logical_op__output_carry$42[0:0]$9878 1'0 + sync always + sync init + update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$9878 + end + attribute \src "libresoc.v:161556.7-161556.37" + process $proc$libresoc.v:161556$9879 + assign { } { } + assign $0\logical_op__rc__ok$34[0:0]$9880 1'0 + sync always + sync init + update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$9880 + end + attribute \src "libresoc.v:161564.7-161564.37" + process $proc$libresoc.v:161564$9881 + assign { } { } + assign $0\logical_op__rc__rc$33[0:0]$9882 1'0 + sync always + sync init + update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$9882 + end + attribute \src "libresoc.v:161574.7-161574.40" + process $proc$libresoc.v:161574$9883 + assign { } { } + assign $0\logical_op__write_cr0$41[0:0]$9884 1'0 + sync always + sync init + update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$9884 + end + attribute \src "libresoc.v:161582.7-161582.37" + process $proc$libresoc.v:161582$9885 + assign { } { } + assign $0\logical_op__zero_a$38[0:0]$9886 1'0 + sync always + sync init + update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$9886 + end + attribute \src "libresoc.v:161590.13-161590.30" + process $proc$libresoc.v:161590$9887 + assign { } { } + assign $0\muxid$28[1:0]$9888 2'00 + sync always + sync init + update \muxid$28 $0\muxid$28[1:0]$9888 + end + attribute \src "libresoc.v:161600.13-161600.34" + process $proc$libresoc.v:161600$9889 + assign { } { } + assign $0\operation$69[1:0]$9890 2'00 + sync always + sync init + update \operation$69 $0\operation$69[1:0]$9890 + end + attribute \src "libresoc.v:161614.14-161614.44" + process $proc$libresoc.v:161614$9891 + assign { } { } + assign $0\ra$47[63:0]$9892 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ra$47 $0\ra$47[63:0]$9892 + end + attribute \src "libresoc.v:161622.14-161622.44" + process $proc$libresoc.v:161622$9893 + assign { } { } + assign $0\rb$48[63:0]$9894 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \rb$48 $0\rb$48[63:0]$9894 + end + attribute \src "libresoc.v:161628.15-161628.84" + process $proc$libresoc.v:161628$9895 + assign { } { } + assign $1\saved_state_dividend_quotient[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \saved_state_dividend_quotient $1\saved_state_dividend_quotient[127:0] + end + attribute \src "libresoc.v:161632.13-161632.45" + process $proc$libresoc.v:161632$9896 + assign { } { } + assign $1\saved_state_q_bits_known[6:0] 7'0000000 + sync always + sync init + update \saved_state_q_bits_known $1\saved_state_q_bits_known[6:0] + end + attribute \src "libresoc.v:161640.7-161640.25" + process $proc$libresoc.v:161640$9897 + assign { } { } + assign $0\xer_so$49[0:0]$9898 1'0 + sync always + sync init + update \xer_so$49 $0\xer_so$49[0:0]$9898 + end + attribute \src "libresoc.v:161649.3-161650.43" + process $proc$libresoc.v:161649$9648 + assign { } { } + assign $0\operation$69[1:0]$9649 \operation$69$next + sync posedge \coresync_clk + update \operation$69 $0\operation$69[1:0]$9649 + end + attribute \src "libresoc.v:161651.3-161652.57" + process $proc$libresoc.v:161651$9650 + assign { } { } + assign $0\divisor_radicand$65[63:0]$9651 \divisor_radicand$65$next + sync posedge \coresync_clk + update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$9651 + end + attribute \src "libresoc.v:161653.3-161654.41" + process $proc$libresoc.v:161653$9652 + assign { } { } + assign $0\dividend$68[127:0]$9653 \dividend$68$next + sync posedge \coresync_clk + update \dividend$68 $0\dividend$68[127:0]$9653 + end + attribute \src "libresoc.v:161655.3-161656.47" + process $proc$libresoc.v:161655$9654 + assign { } { } + assign $0\div_by_zero$54[0:0]$9655 \div_by_zero$54$next + sync posedge \coresync_clk + update \div_by_zero$54 $0\div_by_zero$54[0:0]$9655 + end + attribute \src "libresoc.v:161657.3-161658.51" + process $proc$libresoc.v:161657$9656 + assign { } { } + assign $0\dive_abs_ov64$53[0:0]$9657 \dive_abs_ov64$53$next + sync posedge \coresync_clk + update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$9657 + end + attribute \src "libresoc.v:161659.3-161660.51" + process $proc$libresoc.v:161659$9658 + assign { } { } + assign $0\dive_abs_ov32$52[0:0]$9659 \dive_abs_ov32$52$next + sync posedge \coresync_clk + update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$9659 + end + attribute \src "libresoc.v:161661.3-161662.49" + process $proc$libresoc.v:161661$9660 + assign { } { } + assign $0\dividend_neg$51[0:0]$9661 \dividend_neg$51$next + sync posedge \coresync_clk + update \dividend_neg$51 $0\dividend_neg$51[0:0]$9661 + end + attribute \src "libresoc.v:161663.3-161664.47" + process $proc$libresoc.v:161663$9662 + assign { } { } + assign $0\divisor_neg$50[0:0]$9663 \divisor_neg$50$next + sync posedge \coresync_clk + update \divisor_neg$50 $0\divisor_neg$50[0:0]$9663 + end + attribute \src "libresoc.v:161665.3-161666.37" + process $proc$libresoc.v:161665$9664 + assign { } { } + assign $0\xer_so$49[0:0]$9665 \xer_so$49$next + sync posedge \coresync_clk + update \xer_so$49 $0\xer_so$49[0:0]$9665 + end + attribute \src "libresoc.v:161667.3-161668.29" + process $proc$libresoc.v:161667$9666 + assign { } { } + assign $0\rb$48[63:0]$9667 \rb$48$next + sync posedge \coresync_clk + update \rb$48 $0\rb$48[63:0]$9667 + end + attribute \src "libresoc.v:161669.3-161670.29" + process $proc$libresoc.v:161669$9668 + assign { } { } + assign $0\ra$47[63:0]$9669 \ra$47$next + sync posedge \coresync_clk + update \ra$47 $0\ra$47[63:0]$9669 + end + attribute \src "libresoc.v:161671.3-161672.67" + process $proc$libresoc.v:161671$9670 + assign { } { } + assign $0\logical_op__insn_type$29[6:0]$9671 \logical_op__insn_type$29$next + sync posedge \coresync_clk + update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$9671 + end + attribute \src "libresoc.v:161673.3-161674.63" + process $proc$libresoc.v:161673$9672 + assign { } { } + assign $0\logical_op__fn_unit$30[11:0]$9673 \logical_op__fn_unit$30$next + sync posedge \coresync_clk + update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[11:0]$9673 + end + attribute \src "libresoc.v:161675.3-161676.77" + process $proc$libresoc.v:161675$9674 + assign { } { } + assign $0\logical_op__imm_data__data$31[63:0]$9675 \logical_op__imm_data__data$31$next + sync posedge \coresync_clk + update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$9675 + end + attribute \src "libresoc.v:161677.3-161678.73" + process $proc$libresoc.v:161677$9676 + assign { } { } + assign $0\logical_op__imm_data__ok$32[0:0]$9677 \logical_op__imm_data__ok$32$next + sync posedge \coresync_clk + update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$9677 + end + attribute \src "libresoc.v:161679.3-161680.61" + process $proc$libresoc.v:161679$9678 + assign { } { } + assign $0\logical_op__rc__rc$33[0:0]$9679 \logical_op__rc__rc$33$next + sync posedge \coresync_clk + update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$9679 + end + attribute \src "libresoc.v:161681.3-161682.61" + process $proc$libresoc.v:161681$9680 + assign { } { } + assign $0\logical_op__rc__ok$34[0:0]$9681 \logical_op__rc__ok$34$next + sync posedge \coresync_clk + update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$9681 + end + attribute \src "libresoc.v:161683.3-161684.61" + process $proc$libresoc.v:161683$9682 + assign { } { } + assign $0\logical_op__oe__oe$35[0:0]$9683 \logical_op__oe__oe$35$next + sync posedge \coresync_clk + update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$9683 + end + attribute \src "libresoc.v:161685.3-161686.61" + process $proc$libresoc.v:161685$9684 + assign { } { } + assign $0\logical_op__oe__ok$36[0:0]$9685 \logical_op__oe__ok$36$next + sync posedge \coresync_clk + update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$9685 + end + attribute \src "libresoc.v:161687.3-161688.67" + process $proc$libresoc.v:161687$9686 + assign { } { } + assign $0\logical_op__invert_in$37[0:0]$9687 \logical_op__invert_in$37$next + sync posedge \coresync_clk + update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$9687 + end + attribute \src "libresoc.v:161689.3-161690.61" + process $proc$libresoc.v:161689$9688 + assign { } { } + assign $0\logical_op__zero_a$38[0:0]$9689 \logical_op__zero_a$38$next + sync posedge \coresync_clk + update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$9689 + end + attribute \src "libresoc.v:161691.3-161692.71" + process $proc$libresoc.v:161691$9690 + assign { } { } + assign $0\logical_op__input_carry$39[1:0]$9691 \logical_op__input_carry$39$next + sync posedge \coresync_clk + update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$9691 + end + attribute \src "libresoc.v:161693.3-161694.69" + process $proc$libresoc.v:161693$9692 + assign { } { } + assign $0\logical_op__invert_out$40[0:0]$9693 \logical_op__invert_out$40$next + sync posedge \coresync_clk + update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$9693 + end + attribute \src "libresoc.v:161695.3-161696.67" + process $proc$libresoc.v:161695$9694 + assign { } { } + assign $0\logical_op__write_cr0$41[0:0]$9695 \logical_op__write_cr0$41$next + sync posedge \coresync_clk + update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$9695 + end + attribute \src "libresoc.v:161697.3-161698.73" + process $proc$libresoc.v:161697$9696 + assign { } { } + assign $0\logical_op__output_carry$42[0:0]$9697 \logical_op__output_carry$42$next + sync posedge \coresync_clk + update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$9697 + end + attribute \src "libresoc.v:161699.3-161700.65" + process $proc$libresoc.v:161699$9698 + assign { } { } + assign $0\logical_op__is_32bit$43[0:0]$9699 \logical_op__is_32bit$43$next + sync posedge \coresync_clk + update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$9699 + end + attribute \src "libresoc.v:161701.3-161702.67" + process $proc$libresoc.v:161701$9700 + assign { } { } + assign $0\logical_op__is_signed$44[0:0]$9701 \logical_op__is_signed$44$next + sync posedge \coresync_clk + update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$9701 + end + attribute \src "libresoc.v:161703.3-161704.65" + process $proc$libresoc.v:161703$9702 + assign { } { } + assign $0\logical_op__data_len$45[3:0]$9703 \logical_op__data_len$45$next + sync posedge \coresync_clk + update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$9703 + end + attribute \src "libresoc.v:161705.3-161706.57" + process $proc$libresoc.v:161705$9704 + assign { } { } + assign $0\logical_op__insn$46[31:0]$9705 \logical_op__insn$46$next + sync posedge \coresync_clk + update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$9705 + end + attribute \src "libresoc.v:161707.3-161708.35" + process $proc$libresoc.v:161707$9706 + assign { } { } + assign $0\muxid$28[1:0]$9707 \muxid$28$next + sync posedge \coresync_clk + update \muxid$28 $0\muxid$28[1:0]$9707 + end + attribute \src "libresoc.v:161709.3-161710.27" + process $proc$libresoc.v:161709$9708 + assign { } { } + assign $0\empty[0:0] \empty$next + sync posedge \coresync_clk + update \empty $0\empty[0:0] + end + attribute \src "libresoc.v:161711.3-161712.75" + process $proc$libresoc.v:161711$9709 + assign { } { } + assign $0\saved_state_dividend_quotient[127:0] \saved_state_dividend_quotient$next + sync posedge \coresync_clk + update \saved_state_dividend_quotient $0\saved_state_dividend_quotient[127:0] + end + attribute \src "libresoc.v:161713.3-161714.65" + process $proc$libresoc.v:161713$9710 + assign { } { } + assign $0\saved_state_q_bits_known[6:0] \saved_state_q_bits_known$next + sync posedge \coresync_clk + update \saved_state_q_bits_known $0\saved_state_q_bits_known[6:0] + end + attribute \src "libresoc.v:161735.3-161743.6" + process $proc$libresoc.v:161735$9711 + assign { } { } + assign { } { } + assign $0\saved_state_q_bits_known$next[6:0]$9712 $1\saved_state_q_bits_known$next[6:0]$9713 + attribute \src "libresoc.v:161736.5-161736.29" + switch \initial + attribute \src "libresoc.v:161736.9-161736.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\saved_state_q_bits_known$next[6:0]$9713 7'0000000 + case + assign $1\saved_state_q_bits_known$next[6:0]$9713 \div_state_next_o_q_bits_known + end + sync always + update \saved_state_q_bits_known$next $0\saved_state_q_bits_known$next[6:0]$9712 + end + attribute \src "libresoc.v:161744.3-161752.6" + process $proc$libresoc.v:161744$9714 + assign { } { } + assign { } { } + assign $0\saved_state_dividend_quotient$next[127:0]$9715 $1\saved_state_dividend_quotient$next[127:0]$9716 + attribute \src "libresoc.v:161745.5-161745.29" + switch \initial + attribute \src "libresoc.v:161745.9-161745.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\saved_state_dividend_quotient$next[127:0]$9716 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $1\saved_state_dividend_quotient$next[127:0]$9716 \div_state_next_o_dividend_quotient + end + sync always + update \saved_state_dividend_quotient$next $0\saved_state_dividend_quotient$next[127:0]$9715 + end + attribute \src "libresoc.v:161753.3-161764.6" + process $proc$libresoc.v:161753$9717 + assign { } { } + assign $0\div_state_next_i_q_bits_known[6:0] $1\div_state_next_i_q_bits_known[6:0] + attribute \src "libresoc.v:161754.5-161754.29" + switch \initial + attribute \src "libresoc.v:161754.9-161754.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\div_state_next_i_q_bits_known[6:0] \div_state_init_o_q_bits_known + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\div_state_next_i_q_bits_known[6:0] \saved_state_q_bits_known + end + sync always + update \div_state_next_i_q_bits_known $0\div_state_next_i_q_bits_known[6:0] + end + attribute \src "libresoc.v:161765.3-161776.6" + process $proc$libresoc.v:161765$9718 + assign { } { } + assign $0\div_state_next_i_dividend_quotient[127:0] $1\div_state_next_i_dividend_quotient[127:0] + attribute \src "libresoc.v:161766.5-161766.29" + switch \initial + attribute \src "libresoc.v:161766.9-161766.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\div_state_next_i_dividend_quotient[127:0] \div_state_init_o_dividend_quotient + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\div_state_next_i_dividend_quotient[127:0] \saved_state_dividend_quotient + end + sync always + update \div_state_next_i_dividend_quotient $0\div_state_next_i_dividend_quotient[127:0] + end + attribute \src "libresoc.v:161777.3-161788.6" + process $proc$libresoc.v:161777$9719 + assign { } { } + assign $0\div_state_next_divisor[63:0] $1\div_state_next_divisor[63:0] + attribute \src "libresoc.v:161778.5-161778.29" + switch \initial + attribute \src "libresoc.v:161778.9-161778.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\div_state_next_divisor[63:0] \divisor_radicand + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\div_state_next_divisor[63:0] \divisor_radicand$65 + end + sync always + update \div_state_next_divisor $0\div_state_next_divisor[63:0] + end + attribute \src "libresoc.v:161789.3-161816.6" + process $proc$libresoc.v:161789$9720 + assign { } { } + assign { } { } + assign { } { } + assign $0\empty$next[0:0]$9721 $4\empty$next[0:0]$9725 + attribute \src "libresoc.v:161790.5-161790.29" + switch \initial + attribute \src "libresoc.v:161790.9-161790.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\empty$next[0:0]$9722 $2\empty$next[0:0]$9723 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\empty$next[0:0]$9723 1'0 + case + assign $2\empty$next[0:0]$9723 \empty + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\empty$next[0:0]$9722 $3\empty$next[0:0]$9724 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + switch \$66 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\empty$next[0:0]$9724 1'1 + case + assign $3\empty$next[0:0]$9724 \empty + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\empty$next[0:0]$9725 1'1 + case + assign $4\empty$next[0:0]$9725 $1\empty$next[0:0]$9722 + end + sync always + update \empty$next $0\empty$next[0:0]$9721 + end + attribute \src "libresoc.v:161817.3-161831.6" + process $proc$libresoc.v:161817$9726 + assign { } { } + assign { } { } + assign $0\muxid$28$next[1:0]$9727 $1\muxid$28$next[1:0]$9728 + attribute \src "libresoc.v:161818.5-161818.29" + switch \initial + attribute \src "libresoc.v:161818.9-161818.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\muxid$28$next[1:0]$9728 $2\muxid$28$next[1:0]$9729 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\muxid$28$next[1:0]$9729 \muxid + case + assign $2\muxid$28$next[1:0]$9729 \muxid$28 + end + case + assign $1\muxid$28$next[1:0]$9728 \muxid$28 + end + sync always + update \muxid$28$next $0\muxid$28$next[1:0]$9727 + end + attribute \src "libresoc.v:161832.3-161875.6" + process $proc$libresoc.v:161832$9730 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\logical_op__data_len$45$next[3:0]$9731 $1\logical_op__data_len$45$next[3:0]$9749 + assign $0\logical_op__fn_unit$30$next[11:0]$9732 $1\logical_op__fn_unit$30$next[11:0]$9750 + assign { } { } + assign { } { } + assign $0\logical_op__input_carry$39$next[1:0]$9735 $1\logical_op__input_carry$39$next[1:0]$9753 + assign $0\logical_op__insn$46$next[31:0]$9736 $1\logical_op__insn$46$next[31:0]$9754 + assign $0\logical_op__insn_type$29$next[6:0]$9737 $1\logical_op__insn_type$29$next[6:0]$9755 + assign $0\logical_op__invert_in$37$next[0:0]$9738 $1\logical_op__invert_in$37$next[0:0]$9756 + assign $0\logical_op__invert_out$40$next[0:0]$9739 $1\logical_op__invert_out$40$next[0:0]$9757 + assign $0\logical_op__is_32bit$43$next[0:0]$9740 $1\logical_op__is_32bit$43$next[0:0]$9758 + assign $0\logical_op__is_signed$44$next[0:0]$9741 $1\logical_op__is_signed$44$next[0:0]$9759 + assign { } { } + assign { } { } + assign $0\logical_op__output_carry$42$next[0:0]$9744 $1\logical_op__output_carry$42$next[0:0]$9762 + assign { } { } + assign { } { } + assign $0\logical_op__write_cr0$41$next[0:0]$9747 $1\logical_op__write_cr0$41$next[0:0]$9765 + assign $0\logical_op__zero_a$38$next[0:0]$9748 $1\logical_op__zero_a$38$next[0:0]$9766 + assign $0\logical_op__imm_data__data$31$next[63:0]$9733 $3\logical_op__imm_data__data$31$next[63:0]$9785 + assign $0\logical_op__imm_data__ok$32$next[0:0]$9734 $3\logical_op__imm_data__ok$32$next[0:0]$9786 + assign $0\logical_op__oe__oe$35$next[0:0]$9742 $3\logical_op__oe__oe$35$next[0:0]$9787 + assign $0\logical_op__oe__ok$36$next[0:0]$9743 $3\logical_op__oe__ok$36$next[0:0]$9788 + assign $0\logical_op__rc__ok$34$next[0:0]$9745 $3\logical_op__rc__ok$34$next[0:0]$9789 + assign $0\logical_op__rc__rc$33$next[0:0]$9746 $3\logical_op__rc__rc$33$next[0:0]$9790 + attribute \src "libresoc.v:161833.5-161833.29" + switch \initial + attribute \src "libresoc.v:161833.9-161833.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\logical_op__data_len$45$next[3:0]$9749 $2\logical_op__data_len$45$next[3:0]$9767 + assign $1\logical_op__fn_unit$30$next[11:0]$9750 $2\logical_op__fn_unit$30$next[11:0]$9768 + assign $1\logical_op__imm_data__data$31$next[63:0]$9751 $2\logical_op__imm_data__data$31$next[63:0]$9769 + assign $1\logical_op__imm_data__ok$32$next[0:0]$9752 $2\logical_op__imm_data__ok$32$next[0:0]$9770 + assign $1\logical_op__input_carry$39$next[1:0]$9753 $2\logical_op__input_carry$39$next[1:0]$9771 + assign $1\logical_op__insn$46$next[31:0]$9754 $2\logical_op__insn$46$next[31:0]$9772 + assign $1\logical_op__insn_type$29$next[6:0]$9755 $2\logical_op__insn_type$29$next[6:0]$9773 + assign $1\logical_op__invert_in$37$next[0:0]$9756 $2\logical_op__invert_in$37$next[0:0]$9774 + assign $1\logical_op__invert_out$40$next[0:0]$9757 $2\logical_op__invert_out$40$next[0:0]$9775 + assign $1\logical_op__is_32bit$43$next[0:0]$9758 $2\logical_op__is_32bit$43$next[0:0]$9776 + assign $1\logical_op__is_signed$44$next[0:0]$9759 $2\logical_op__is_signed$44$next[0:0]$9777 + assign $1\logical_op__oe__oe$35$next[0:0]$9760 $2\logical_op__oe__oe$35$next[0:0]$9778 + assign $1\logical_op__oe__ok$36$next[0:0]$9761 $2\logical_op__oe__ok$36$next[0:0]$9779 + assign $1\logical_op__output_carry$42$next[0:0]$9762 $2\logical_op__output_carry$42$next[0:0]$9780 + assign $1\logical_op__rc__ok$34$next[0:0]$9763 $2\logical_op__rc__ok$34$next[0:0]$9781 + assign $1\logical_op__rc__rc$33$next[0:0]$9764 $2\logical_op__rc__rc$33$next[0:0]$9782 + assign $1\logical_op__write_cr0$41$next[0:0]$9765 $2\logical_op__write_cr0$41$next[0:0]$9783 + assign $1\logical_op__zero_a$38$next[0:0]$9766 $2\logical_op__zero_a$38$next[0:0]$9784 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\logical_op__insn$46$next[31:0]$9772 $2\logical_op__data_len$45$next[3:0]$9767 $2\logical_op__is_signed$44$next[0:0]$9777 $2\logical_op__is_32bit$43$next[0:0]$9776 $2\logical_op__output_carry$42$next[0:0]$9780 $2\logical_op__write_cr0$41$next[0:0]$9783 $2\logical_op__invert_out$40$next[0:0]$9775 $2\logical_op__input_carry$39$next[1:0]$9771 $2\logical_op__zero_a$38$next[0:0]$9784 $2\logical_op__invert_in$37$next[0:0]$9774 $2\logical_op__oe__ok$36$next[0:0]$9779 $2\logical_op__oe__oe$35$next[0:0]$9778 $2\logical_op__rc__ok$34$next[0:0]$9781 $2\logical_op__rc__rc$33$next[0:0]$9782 $2\logical_op__imm_data__ok$32$next[0:0]$9770 $2\logical_op__imm_data__data$31$next[63:0]$9769 $2\logical_op__fn_unit$30$next[11:0]$9768 $2\logical_op__insn_type$29$next[6:0]$9773 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + case + assign $2\logical_op__data_len$45$next[3:0]$9767 \logical_op__data_len$45 + assign $2\logical_op__fn_unit$30$next[11:0]$9768 \logical_op__fn_unit$30 + assign $2\logical_op__imm_data__data$31$next[63:0]$9769 \logical_op__imm_data__data$31 + assign $2\logical_op__imm_data__ok$32$next[0:0]$9770 \logical_op__imm_data__ok$32 + assign $2\logical_op__input_carry$39$next[1:0]$9771 \logical_op__input_carry$39 + assign $2\logical_op__insn$46$next[31:0]$9772 \logical_op__insn$46 + assign $2\logical_op__insn_type$29$next[6:0]$9773 \logical_op__insn_type$29 + assign $2\logical_op__invert_in$37$next[0:0]$9774 \logical_op__invert_in$37 + assign $2\logical_op__invert_out$40$next[0:0]$9775 \logical_op__invert_out$40 + assign $2\logical_op__is_32bit$43$next[0:0]$9776 \logical_op__is_32bit$43 + assign $2\logical_op__is_signed$44$next[0:0]$9777 \logical_op__is_signed$44 + assign $2\logical_op__oe__oe$35$next[0:0]$9778 \logical_op__oe__oe$35 + assign $2\logical_op__oe__ok$36$next[0:0]$9779 \logical_op__oe__ok$36 + assign $2\logical_op__output_carry$42$next[0:0]$9780 \logical_op__output_carry$42 + assign $2\logical_op__rc__ok$34$next[0:0]$9781 \logical_op__rc__ok$34 + assign $2\logical_op__rc__rc$33$next[0:0]$9782 \logical_op__rc__rc$33 + assign $2\logical_op__write_cr0$41$next[0:0]$9783 \logical_op__write_cr0$41 + assign $2\logical_op__zero_a$38$next[0:0]$9784 \logical_op__zero_a$38 + end + case + assign $1\logical_op__data_len$45$next[3:0]$9749 \logical_op__data_len$45 + assign $1\logical_op__fn_unit$30$next[11:0]$9750 \logical_op__fn_unit$30 + assign $1\logical_op__imm_data__data$31$next[63:0]$9751 \logical_op__imm_data__data$31 + assign $1\logical_op__imm_data__ok$32$next[0:0]$9752 \logical_op__imm_data__ok$32 + assign $1\logical_op__input_carry$39$next[1:0]$9753 \logical_op__input_carry$39 + assign $1\logical_op__insn$46$next[31:0]$9754 \logical_op__insn$46 + assign $1\logical_op__insn_type$29$next[6:0]$9755 \logical_op__insn_type$29 + assign $1\logical_op__invert_in$37$next[0:0]$9756 \logical_op__invert_in$37 + assign $1\logical_op__invert_out$40$next[0:0]$9757 \logical_op__invert_out$40 + assign $1\logical_op__is_32bit$43$next[0:0]$9758 \logical_op__is_32bit$43 + assign $1\logical_op__is_signed$44$next[0:0]$9759 \logical_op__is_signed$44 + assign $1\logical_op__oe__oe$35$next[0:0]$9760 \logical_op__oe__oe$35 + assign $1\logical_op__oe__ok$36$next[0:0]$9761 \logical_op__oe__ok$36 + assign $1\logical_op__output_carry$42$next[0:0]$9762 \logical_op__output_carry$42 + assign $1\logical_op__rc__ok$34$next[0:0]$9763 \logical_op__rc__ok$34 + assign $1\logical_op__rc__rc$33$next[0:0]$9764 \logical_op__rc__rc$33 + assign $1\logical_op__write_cr0$41$next[0:0]$9765 \logical_op__write_cr0$41 + assign $1\logical_op__zero_a$38$next[0:0]$9766 \logical_op__zero_a$38 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $3\logical_op__imm_data__data$31$next[63:0]$9785 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\logical_op__imm_data__ok$32$next[0:0]$9786 1'0 + assign $3\logical_op__rc__rc$33$next[0:0]$9790 1'0 + assign $3\logical_op__rc__ok$34$next[0:0]$9789 1'0 + assign $3\logical_op__oe__oe$35$next[0:0]$9787 1'0 + assign $3\logical_op__oe__ok$36$next[0:0]$9788 1'0 + case + assign $3\logical_op__imm_data__data$31$next[63:0]$9785 $1\logical_op__imm_data__data$31$next[63:0]$9751 + assign $3\logical_op__imm_data__ok$32$next[0:0]$9786 $1\logical_op__imm_data__ok$32$next[0:0]$9752 + assign $3\logical_op__oe__oe$35$next[0:0]$9787 $1\logical_op__oe__oe$35$next[0:0]$9760 + assign $3\logical_op__oe__ok$36$next[0:0]$9788 $1\logical_op__oe__ok$36$next[0:0]$9761 + assign $3\logical_op__rc__ok$34$next[0:0]$9789 $1\logical_op__rc__ok$34$next[0:0]$9763 + assign $3\logical_op__rc__rc$33$next[0:0]$9790 $1\logical_op__rc__rc$33$next[0:0]$9764 + end + sync always + update \logical_op__data_len$45$next $0\logical_op__data_len$45$next[3:0]$9731 + update \logical_op__fn_unit$30$next $0\logical_op__fn_unit$30$next[11:0]$9732 + update \logical_op__imm_data__data$31$next $0\logical_op__imm_data__data$31$next[63:0]$9733 + update \logical_op__imm_data__ok$32$next $0\logical_op__imm_data__ok$32$next[0:0]$9734 + update \logical_op__input_carry$39$next $0\logical_op__input_carry$39$next[1:0]$9735 + update \logical_op__insn$46$next $0\logical_op__insn$46$next[31:0]$9736 + update \logical_op__insn_type$29$next $0\logical_op__insn_type$29$next[6:0]$9737 + update \logical_op__invert_in$37$next $0\logical_op__invert_in$37$next[0:0]$9738 + update \logical_op__invert_out$40$next $0\logical_op__invert_out$40$next[0:0]$9739 + update \logical_op__is_32bit$43$next $0\logical_op__is_32bit$43$next[0:0]$9740 + update \logical_op__is_signed$44$next $0\logical_op__is_signed$44$next[0:0]$9741 + update \logical_op__oe__oe$35$next $0\logical_op__oe__oe$35$next[0:0]$9742 + update \logical_op__oe__ok$36$next $0\logical_op__oe__ok$36$next[0:0]$9743 + update \logical_op__output_carry$42$next $0\logical_op__output_carry$42$next[0:0]$9744 + update \logical_op__rc__ok$34$next $0\logical_op__rc__ok$34$next[0:0]$9745 + update \logical_op__rc__rc$33$next $0\logical_op__rc__rc$33$next[0:0]$9746 + update \logical_op__write_cr0$41$next $0\logical_op__write_cr0$41$next[0:0]$9747 + update \logical_op__zero_a$38$next $0\logical_op__zero_a$38$next[0:0]$9748 + end + attribute \src "libresoc.v:161876.3-161890.6" + process $proc$libresoc.v:161876$9791 + assign { } { } + assign { } { } + assign $0\ra$47$next[63:0]$9792 $1\ra$47$next[63:0]$9793 + attribute \src "libresoc.v:161877.5-161877.29" + switch \initial + attribute \src "libresoc.v:161877.9-161877.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ra$47$next[63:0]$9793 $2\ra$47$next[63:0]$9794 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ra$47$next[63:0]$9794 \ra + case + assign $2\ra$47$next[63:0]$9794 \ra$47 + end + case + assign $1\ra$47$next[63:0]$9793 \ra$47 + end + sync always + update \ra$47$next $0\ra$47$next[63:0]$9792 + end + attribute \src "libresoc.v:161891.3-161905.6" + process $proc$libresoc.v:161891$9795 + assign { } { } + assign { } { } + assign $0\rb$48$next[63:0]$9796 $1\rb$48$next[63:0]$9797 + attribute \src "libresoc.v:161892.5-161892.29" + switch \initial + attribute \src "libresoc.v:161892.9-161892.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rb$48$next[63:0]$9797 $2\rb$48$next[63:0]$9798 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\rb$48$next[63:0]$9798 \rb + case + assign $2\rb$48$next[63:0]$9798 \rb$48 + end + case + assign $1\rb$48$next[63:0]$9797 \rb$48 + end + sync always + update \rb$48$next $0\rb$48$next[63:0]$9796 + end + attribute \src "libresoc.v:161906.3-161920.6" + process $proc$libresoc.v:161906$9799 + assign { } { } + assign { } { } + assign $0\xer_so$49$next[0:0]$9800 $1\xer_so$49$next[0:0]$9801 + attribute \src "libresoc.v:161907.5-161907.29" + switch \initial + attribute \src "libresoc.v:161907.9-161907.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_so$49$next[0:0]$9801 $2\xer_so$49$next[0:0]$9802 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so$49$next[0:0]$9802 \xer_so + case + assign $2\xer_so$49$next[0:0]$9802 \xer_so$49 + end + case + assign $1\xer_so$49$next[0:0]$9801 \xer_so$49 + end + sync always + update \xer_so$49$next $0\xer_so$49$next[0:0]$9800 + end + attribute \src "libresoc.v:161921.3-161935.6" + process $proc$libresoc.v:161921$9803 + assign { } { } + assign { } { } + assign $0\divisor_neg$50$next[0:0]$9804 $1\divisor_neg$50$next[0:0]$9805 + attribute \src "libresoc.v:161922.5-161922.29" + switch \initial + attribute \src "libresoc.v:161922.9-161922.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\divisor_neg$50$next[0:0]$9805 $2\divisor_neg$50$next[0:0]$9806 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\divisor_neg$50$next[0:0]$9806 \divisor_neg + case + assign $2\divisor_neg$50$next[0:0]$9806 \divisor_neg$50 + end + case + assign $1\divisor_neg$50$next[0:0]$9805 \divisor_neg$50 + end + sync always + update \divisor_neg$50$next $0\divisor_neg$50$next[0:0]$9804 + end + attribute \src "libresoc.v:161936.3-161950.6" + process $proc$libresoc.v:161936$9807 + assign { } { } + assign { } { } + assign $0\dividend_neg$51$next[0:0]$9808 $1\dividend_neg$51$next[0:0]$9809 + attribute \src "libresoc.v:161937.5-161937.29" + switch \initial + attribute \src "libresoc.v:161937.9-161937.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dividend_neg$51$next[0:0]$9809 $2\dividend_neg$51$next[0:0]$9810 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dividend_neg$51$next[0:0]$9810 \dividend_neg + case + assign $2\dividend_neg$51$next[0:0]$9810 \dividend_neg$51 + end + case + assign $1\dividend_neg$51$next[0:0]$9809 \dividend_neg$51 + end + sync always + update \dividend_neg$51$next $0\dividend_neg$51$next[0:0]$9808 + end + attribute \src "libresoc.v:161951.3-161965.6" + process $proc$libresoc.v:161951$9811 + assign { } { } + assign { } { } + assign $0\dive_abs_ov32$52$next[0:0]$9812 $1\dive_abs_ov32$52$next[0:0]$9813 + attribute \src "libresoc.v:161952.5-161952.29" + switch \initial + attribute \src "libresoc.v:161952.9-161952.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dive_abs_ov32$52$next[0:0]$9813 $2\dive_abs_ov32$52$next[0:0]$9814 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dive_abs_ov32$52$next[0:0]$9814 \dive_abs_ov32 + case + assign $2\dive_abs_ov32$52$next[0:0]$9814 \dive_abs_ov32$52 + end + case + assign $1\dive_abs_ov32$52$next[0:0]$9813 \dive_abs_ov32$52 + end + sync always + update \dive_abs_ov32$52$next $0\dive_abs_ov32$52$next[0:0]$9812 + end + attribute \src "libresoc.v:161966.3-161980.6" + process $proc$libresoc.v:161966$9815 + assign { } { } + assign { } { } + assign $0\dive_abs_ov64$53$next[0:0]$9816 $1\dive_abs_ov64$53$next[0:0]$9817 + attribute \src "libresoc.v:161967.5-161967.29" + switch \initial + attribute \src "libresoc.v:161967.9-161967.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dive_abs_ov64$53$next[0:0]$9817 $2\dive_abs_ov64$53$next[0:0]$9818 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dive_abs_ov64$53$next[0:0]$9818 \dive_abs_ov64 + case + assign $2\dive_abs_ov64$53$next[0:0]$9818 \dive_abs_ov64$53 + end + case + assign $1\dive_abs_ov64$53$next[0:0]$9817 \dive_abs_ov64$53 + end + sync always + update \dive_abs_ov64$53$next $0\dive_abs_ov64$53$next[0:0]$9816 + end + attribute \src "libresoc.v:161981.3-161995.6" + process $proc$libresoc.v:161981$9819 + assign { } { } + assign { } { } + assign $0\div_by_zero$54$next[0:0]$9820 $1\div_by_zero$54$next[0:0]$9821 + attribute \src "libresoc.v:161982.5-161982.29" + switch \initial + attribute \src "libresoc.v:161982.9-161982.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\div_by_zero$54$next[0:0]$9821 $2\div_by_zero$54$next[0:0]$9822 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\div_by_zero$54$next[0:0]$9822 \div_by_zero + case + assign $2\div_by_zero$54$next[0:0]$9822 \div_by_zero$54 + end + case + assign $1\div_by_zero$54$next[0:0]$9821 \div_by_zero$54 + end + sync always + update \div_by_zero$54$next $0\div_by_zero$54$next[0:0]$9820 + end + attribute \src "libresoc.v:161996.3-162010.6" + process $proc$libresoc.v:161996$9823 + assign { } { } + assign { } { } + assign $0\dividend$68$next[127:0]$9824 $1\dividend$68$next[127:0]$9825 + attribute \src "libresoc.v:161997.5-161997.29" + switch \initial + attribute \src "libresoc.v:161997.9-161997.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dividend$68$next[127:0]$9825 $2\dividend$68$next[127:0]$9826 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dividend$68$next[127:0]$9826 \dividend + case + assign $2\dividend$68$next[127:0]$9826 \dividend$68 + end + case + assign $1\dividend$68$next[127:0]$9825 \dividend$68 + end + sync always + update \dividend$68$next $0\dividend$68$next[127:0]$9824 + end + attribute \src "libresoc.v:162011.3-162025.6" + process $proc$libresoc.v:162011$9827 + assign { } { } + assign { } { } + assign $0\divisor_radicand$65$next[63:0]$9828 $1\divisor_radicand$65$next[63:0]$9829 + attribute \src "libresoc.v:162012.5-162012.29" + switch \initial + attribute \src "libresoc.v:162012.9-162012.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\divisor_radicand$65$next[63:0]$9829 $2\divisor_radicand$65$next[63:0]$9830 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\divisor_radicand$65$next[63:0]$9830 \divisor_radicand + case + assign $2\divisor_radicand$65$next[63:0]$9830 \divisor_radicand$65 + end + case + assign $1\divisor_radicand$65$next[63:0]$9829 \divisor_radicand$65 + end + sync always + update \divisor_radicand$65$next $0\divisor_radicand$65$next[63:0]$9828 + end + attribute \src "libresoc.v:162026.3-162040.6" + process $proc$libresoc.v:162026$9831 + assign { } { } + assign { } { } + assign $0\operation$69$next[1:0]$9832 $1\operation$69$next[1:0]$9833 + attribute \src "libresoc.v:162027.5-162027.29" + switch \initial + attribute \src "libresoc.v:162027.9-162027.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\operation$69$next[1:0]$9833 $2\operation$69$next[1:0]$9834 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\operation$69$next[1:0]$9834 \operation + case + assign $2\operation$69$next[1:0]$9834 \operation$69 + end + case + assign $1\operation$69$next[1:0]$9833 \operation$69 + end + sync always + update \operation$69$next $0\operation$69$next[1:0]$9832 + end + connect \$56 $sshl$libresoc.v:161643$9641_Y + connect \$55 $pos$libresoc.v:161644$9643_Y + connect \$59 $not$libresoc.v:161645$9644_Y + connect \$61 $ge$libresoc.v:161646$9645_Y + connect \$63 $and$libresoc.v:161647$9646_Y + connect \$66 $and$libresoc.v:161648$9647_Y + connect \p_ready_o \empty + connect \n_valid_o \$63 + connect \remainder \$55 + connect \quotient_root \div_state_next_o_dividend_quotient [63:0] + connect \div_by_zero$27 \div_by_zero$54 + connect \dive_abs_ov64$26 \dive_abs_ov64$53 + connect \dive_abs_ov32$25 \dive_abs_ov32$52 + connect \dividend_neg$24 \dividend_neg$51 + connect \divisor_neg$23 \divisor_neg$50 + connect \xer_so$22 \xer_so$49 + connect \rb$21 \rb$48 + connect \ra$20 \ra$47 + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn$46 \logical_op__data_len$45 \logical_op__is_signed$44 \logical_op__is_32bit$43 \logical_op__output_carry$42 \logical_op__write_cr0$41 \logical_op__invert_out$40 \logical_op__input_carry$39 \logical_op__zero_a$38 \logical_op__invert_in$37 \logical_op__oe__ok$36 \logical_op__oe__oe$35 \logical_op__rc__ok$34 \logical_op__rc__rc$33 \logical_op__imm_data__ok$32 \logical_op__imm_data__data$31 \logical_op__fn_unit$30 \logical_op__insn_type$29 } + connect \muxid$1 \muxid$28 + connect \div_state_init_dividend \dividend +end +attribute \src "libresoc.v:162060.1-163584.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start" +attribute \generator "nMigen" +module \pipe_start + attribute \src "libresoc.v:163390.3-163402.6" + wire $0\div_by_zero$next[0:0]$9944 + attribute \src "libresoc.v:163176.3-163177.39" + wire $0\div_by_zero[0:0] + attribute \src "libresoc.v:163364.3-163376.6" + wire $0\dive_abs_ov32$next[0:0]$9938 + attribute \src "libresoc.v:163180.3-163181.43" + wire $0\dive_abs_ov32[0:0] + attribute \src "libresoc.v:163377.3-163389.6" + wire $0\dive_abs_ov64$next[0:0]$9941 + attribute \src "libresoc.v:163178.3-163179.43" + wire $0\dive_abs_ov64[0:0] + attribute \src "libresoc.v:163403.3-163415.6" + wire width 128 $0\dividend$next[127:0]$9947 + attribute \src "libresoc.v:163174.3-163175.33" + wire width 128 $0\dividend[127:0] + attribute \src "libresoc.v:163351.3-163363.6" + wire $0\dividend_neg$next[0:0]$9935 + attribute \src "libresoc.v:163182.3-163183.41" + wire $0\dividend_neg[0:0] + attribute \src "libresoc.v:163338.3-163350.6" + wire $0\divisor_neg$next[0:0]$9932 + attribute \src "libresoc.v:163184.3-163185.39" + wire $0\divisor_neg[0:0] + attribute \src "libresoc.v:163416.3-163428.6" + wire width 64 $0\divisor_radicand$next[63:0]$9950 + attribute \src "libresoc.v:163172.3-163173.49" + wire width 64 $0\divisor_radicand[63:0] + attribute \src "libresoc.v:162061.7-162061.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:163473.3-163514.6" + wire width 4 $0\logical_op__data_len$next[3:0]$9963 + attribute \src "libresoc.v:163224.3-163225.57" + wire width 4 $0\logical_op__data_len[3:0] + attribute \src "libresoc.v:163473.3-163514.6" + wire width 12 $0\logical_op__fn_unit$next[11:0]$9964 + attribute \src "libresoc.v:163194.3-163195.55" + wire width 12 $0\logical_op__fn_unit[11:0] + attribute \src "libresoc.v:163473.3-163514.6" + wire width 64 $0\logical_op__imm_data__data$next[63:0]$9965 + attribute \src "libresoc.v:163196.3-163197.69" + wire width 64 $0\logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:163473.3-163514.6" + wire $0\logical_op__imm_data__ok$next[0:0]$9966 + attribute \src "libresoc.v:163198.3-163199.65" + wire $0\logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:163473.3-163514.6" + wire width 2 $0\logical_op__input_carry$next[1:0]$9967 + attribute \src "libresoc.v:163212.3-163213.63" + wire width 2 $0\logical_op__input_carry[1:0] + attribute \src "libresoc.v:163473.3-163514.6" + wire width 32 $0\logical_op__insn$next[31:0]$9968 + attribute \src "libresoc.v:163226.3-163227.49" + wire width 32 $0\logical_op__insn[31:0] + attribute \src "libresoc.v:163473.3-163514.6" + wire width 7 $0\logical_op__insn_type$next[6:0]$9969 + attribute \src "libresoc.v:163192.3-163193.59" + wire width 7 $0\logical_op__insn_type[6:0] + attribute \src "libresoc.v:163473.3-163514.6" + wire $0\logical_op__invert_in$next[0:0]$9970 + attribute \src "libresoc.v:163208.3-163209.59" + wire $0\logical_op__invert_in[0:0] + attribute \src "libresoc.v:163473.3-163514.6" + wire $0\logical_op__invert_out$next[0:0]$9971 + attribute \src "libresoc.v:163214.3-163215.61" + wire $0\logical_op__invert_out[0:0] + attribute \src "libresoc.v:163473.3-163514.6" + wire $0\logical_op__is_32bit$next[0:0]$9972 + attribute \src "libresoc.v:163220.3-163221.57" + wire $0\logical_op__is_32bit[0:0] + attribute \src "libresoc.v:163473.3-163514.6" + wire $0\logical_op__is_signed$next[0:0]$9973 + attribute \src "libresoc.v:163222.3-163223.59" + wire $0\logical_op__is_signed[0:0] + attribute \src "libresoc.v:163473.3-163514.6" + wire $0\logical_op__oe__oe$next[0:0]$9974 + attribute \src "libresoc.v:163204.3-163205.53" + wire $0\logical_op__oe__oe[0:0] + attribute \src "libresoc.v:163473.3-163514.6" + wire $0\logical_op__oe__ok$next[0:0]$9975 + attribute \src "libresoc.v:163206.3-163207.53" + wire $0\logical_op__oe__ok[0:0] + attribute \src "libresoc.v:163473.3-163514.6" + wire $0\logical_op__output_carry$next[0:0]$9976 + attribute \src "libresoc.v:163218.3-163219.65" + wire $0\logical_op__output_carry[0:0] + attribute \src "libresoc.v:163473.3-163514.6" + wire $0\logical_op__rc__ok$next[0:0]$9977 + attribute \src "libresoc.v:163202.3-163203.53" + wire $0\logical_op__rc__ok[0:0] + attribute \src "libresoc.v:163473.3-163514.6" + wire $0\logical_op__rc__rc$next[0:0]$9978 + attribute \src "libresoc.v:163200.3-163201.53" + wire $0\logical_op__rc__rc[0:0] + attribute \src "libresoc.v:163473.3-163514.6" + wire $0\logical_op__write_cr0$next[0:0]$9979 + attribute \src "libresoc.v:163216.3-163217.59" + wire $0\logical_op__write_cr0[0:0] + attribute \src "libresoc.v:163473.3-163514.6" + wire $0\logical_op__zero_a$next[0:0]$9980 + attribute \src "libresoc.v:163210.3-163211.53" + wire $0\logical_op__zero_a[0:0] + attribute \src "libresoc.v:163460.3-163472.6" + wire width 2 $0\muxid$next[1:0]$9960 + attribute \src "libresoc.v:163228.3-163229.27" + wire width 2 $0\muxid[1:0] + attribute \src "libresoc.v:163429.3-163441.6" + wire width 2 $0\operation$next[1:0]$9953 + attribute \src "libresoc.v:163170.3-163171.35" + wire width 2 $0\operation[1:0] + attribute \src "libresoc.v:163442.3-163459.6" + wire $0\r_busy$next[0:0]$9956 + attribute \src "libresoc.v:163230.3-163231.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:163515.3-163527.6" + wire width 64 $0\ra$next[63:0]$10006 + attribute \src "libresoc.v:163190.3-163191.21" + wire width 64 $0\ra[63:0] + attribute \src "libresoc.v:163528.3-163540.6" + wire width 64 $0\rb$next[63:0]$10009 + attribute \src "libresoc.v:163188.3-163189.21" + wire width 64 $0\rb[63:0] + attribute \src "libresoc.v:163541.3-163553.6" + wire $0\xer_so$next[0:0]$10012 + attribute \src "libresoc.v:163186.3-163187.29" + wire $0\xer_so[0:0] + attribute \src "libresoc.v:163390.3-163402.6" + wire $1\div_by_zero$next[0:0]$9945 + attribute \src "libresoc.v:162070.7-162070.25" + wire $1\div_by_zero[0:0] + attribute \src "libresoc.v:163364.3-163376.6" + wire $1\dive_abs_ov32$next[0:0]$9939 + attribute \src "libresoc.v:162077.7-162077.27" + wire $1\dive_abs_ov32[0:0] + attribute \src "libresoc.v:163377.3-163389.6" + wire $1\dive_abs_ov64$next[0:0]$9942 + attribute \src "libresoc.v:162084.7-162084.27" + wire $1\dive_abs_ov64[0:0] + attribute \src "libresoc.v:163403.3-163415.6" + wire width 128 $1\dividend$next[127:0]$9948 + attribute \src "libresoc.v:162091.15-162091.63" + wire width 128 $1\dividend[127:0] + attribute \src "libresoc.v:163351.3-163363.6" + wire $1\dividend_neg$next[0:0]$9936 + attribute \src "libresoc.v:162098.7-162098.26" + wire $1\dividend_neg[0:0] + attribute \src "libresoc.v:163338.3-163350.6" + wire $1\divisor_neg$next[0:0]$9933 + attribute \src "libresoc.v:162105.7-162105.25" + wire $1\divisor_neg[0:0] + attribute \src "libresoc.v:163416.3-163428.6" + wire width 64 $1\divisor_radicand$next[63:0]$9951 + attribute \src "libresoc.v:162112.14-162112.53" + wire width 64 $1\divisor_radicand[63:0] + attribute \src "libresoc.v:163473.3-163514.6" + wire width 4 $1\logical_op__data_len$next[3:0]$9981 + attribute \src "libresoc.v:162389.13-162389.40" + wire width 4 $1\logical_op__data_len[3:0] + attribute \src "libresoc.v:163473.3-163514.6" + wire width 12 $1\logical_op__fn_unit$next[11:0]$9982 + attribute \src "libresoc.v:162411.14-162411.43" + wire width 12 $1\logical_op__fn_unit[11:0] + attribute \src "libresoc.v:163473.3-163514.6" + wire width 64 $1\logical_op__imm_data__data$next[63:0]$9983 + attribute \src "libresoc.v:162446.14-162446.63" + wire width 64 $1\logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:163473.3-163514.6" + wire $1\logical_op__imm_data__ok$next[0:0]$9984 + attribute \src "libresoc.v:162455.7-162455.38" + wire $1\logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:163473.3-163514.6" + wire width 2 $1\logical_op__input_carry$next[1:0]$9985 + attribute \src "libresoc.v:162468.13-162468.43" + wire width 2 $1\logical_op__input_carry[1:0] + attribute \src "libresoc.v:163473.3-163514.6" + wire width 32 $1\logical_op__insn$next[31:0]$9986 + attribute \src "libresoc.v:162485.14-162485.38" + wire width 32 $1\logical_op__insn[31:0] + attribute \src "libresoc.v:163473.3-163514.6" + wire width 7 $1\logical_op__insn_type$next[6:0]$9987 + attribute \src "libresoc.v:162568.13-162568.42" + wire width 7 $1\logical_op__insn_type[6:0] + attribute \src "libresoc.v:163473.3-163514.6" + wire $1\logical_op__invert_in$next[0:0]$9988 + attribute \src "libresoc.v:162725.7-162725.35" + wire $1\logical_op__invert_in[0:0] + attribute \src "libresoc.v:163473.3-163514.6" + wire $1\logical_op__invert_out$next[0:0]$9989 + attribute \src "libresoc.v:162734.7-162734.36" + wire $1\logical_op__invert_out[0:0] + attribute \src "libresoc.v:163473.3-163514.6" + wire $1\logical_op__is_32bit$next[0:0]$9990 + attribute \src "libresoc.v:162743.7-162743.34" + wire $1\logical_op__is_32bit[0:0] + attribute \src "libresoc.v:163473.3-163514.6" + wire $1\logical_op__is_signed$next[0:0]$9991 + attribute \src "libresoc.v:162752.7-162752.35" + wire $1\logical_op__is_signed[0:0] + attribute \src "libresoc.v:163473.3-163514.6" + wire $1\logical_op__oe__oe$next[0:0]$9992 + attribute \src "libresoc.v:162761.7-162761.32" + wire $1\logical_op__oe__oe[0:0] + attribute \src "libresoc.v:163473.3-163514.6" + wire $1\logical_op__oe__ok$next[0:0]$9993 + attribute \src "libresoc.v:162770.7-162770.32" + wire $1\logical_op__oe__ok[0:0] + attribute \src "libresoc.v:163473.3-163514.6" + wire $1\logical_op__output_carry$next[0:0]$9994 + attribute \src "libresoc.v:162779.7-162779.38" + wire $1\logical_op__output_carry[0:0] + attribute \src "libresoc.v:163473.3-163514.6" + wire $1\logical_op__rc__ok$next[0:0]$9995 + attribute \src "libresoc.v:162788.7-162788.32" + wire $1\logical_op__rc__ok[0:0] + attribute \src "libresoc.v:163473.3-163514.6" + wire $1\logical_op__rc__rc$next[0:0]$9996 + attribute \src "libresoc.v:162797.7-162797.32" + wire $1\logical_op__rc__rc[0:0] + attribute \src "libresoc.v:163473.3-163514.6" + wire $1\logical_op__write_cr0$next[0:0]$9997 + attribute \src "libresoc.v:162806.7-162806.35" + wire $1\logical_op__write_cr0[0:0] + attribute \src "libresoc.v:163473.3-163514.6" + wire $1\logical_op__zero_a$next[0:0]$9998 + attribute \src "libresoc.v:162815.7-162815.32" + wire $1\logical_op__zero_a[0:0] + attribute \src "libresoc.v:163460.3-163472.6" + wire width 2 $1\muxid$next[1:0]$9961 + attribute \src "libresoc.v:162824.13-162824.25" + wire width 2 $1\muxid[1:0] + attribute \src "libresoc.v:163429.3-163441.6" + wire width 2 $1\operation$next[1:0]$9954 + attribute \src "libresoc.v:162839.13-162839.29" + wire width 2 $1\operation[1:0] + attribute \src "libresoc.v:163442.3-163459.6" + wire $1\r_busy$next[0:0]$9957 + attribute \src "libresoc.v:162853.7-162853.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:163515.3-163527.6" + wire width 64 $1\ra$next[63:0]$10007 + attribute \src "libresoc.v:162858.14-162858.39" + wire width 64 $1\ra[63:0] + attribute \src "libresoc.v:163528.3-163540.6" + wire width 64 $1\rb$next[63:0]$10010 + attribute \src "libresoc.v:162869.14-162869.39" + wire width 64 $1\rb[63:0] + attribute \src "libresoc.v:163541.3-163553.6" + wire $1\xer_so$next[0:0]$10013 + attribute \src "libresoc.v:163162.7-163162.20" + wire $1\xer_so[0:0] + attribute \src "libresoc.v:163473.3-163514.6" + wire width 64 $2\logical_op__imm_data__data$next[63:0]$9999 + attribute \src "libresoc.v:163473.3-163514.6" + wire $2\logical_op__imm_data__ok$next[0:0]$10000 + attribute \src "libresoc.v:163473.3-163514.6" + wire $2\logical_op__oe__oe$next[0:0]$10001 + attribute \src "libresoc.v:163473.3-163514.6" + wire $2\logical_op__oe__ok$next[0:0]$10002 + attribute \src "libresoc.v:163473.3-163514.6" + wire $2\logical_op__rc__ok$next[0:0]$10003 + attribute \src "libresoc.v:163473.3-163514.6" + wire $2\logical_op__rc__rc$next[0:0]$10004 + attribute \src "libresoc.v:163442.3-163459.6" + wire $2\r_busy$next[0:0]$9958 + attribute \src "libresoc.v:163169.18-163169.118" + wire $and$libresoc.v:163169$9899_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 58 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire output 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \div_by_zero$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \div_by_zero$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire output 28 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \dive_abs_ov32$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \dive_abs_ov32$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire output 29 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \dive_abs_ov64$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \dive_abs_ov64$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 output 31 \dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \dividend$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \dividend$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire output 27 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \dividend_neg$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \dividend_neg$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire output 26 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \divisor_neg$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \divisor_neg$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 output 32 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \divisor_radicand$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \divisor_radicand$next + attribute \src "libresoc.v:162061.7-162061.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_logical_op__data_len$40 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \input_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \input_logical_op__fn_unit$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_logical_op__imm_data__data$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__imm_data__ok$27 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_logical_op__input_carry$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_logical_op__insn$41 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_logical_op__insn_type$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_in$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_out$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_32bit$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_signed$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__oe$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__ok$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__output_carry$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__rc$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__write_cr0$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__zero_a$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 53 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 6 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 38 \logical_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_op__fn_unit$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 39 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 40 \logical_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 15 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 47 \logical_op__input_carry$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 54 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 5 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 37 \logical_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 45 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 48 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 51 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 52 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 43 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 44 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 50 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 42 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 41 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 49 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 46 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 36 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$68 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 output 33 \operation + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \operation$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \operation$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 35 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 34 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$65 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 23 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 55 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 24 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 56 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \setup_stage_div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \setup_stage_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \setup_stage_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \setup_stage_dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \setup_stage_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \setup_stage_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \setup_stage_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \setup_stage_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \setup_stage_logical_op__data_len$62 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute 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\setup_stage_logical_op__rc__ok$51 + connect \logical_op__rc__rc \setup_stage_logical_op__rc__rc + connect \logical_op__rc__rc$6 \setup_stage_logical_op__rc__rc$50 + connect \logical_op__write_cr0 \setup_stage_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \setup_stage_logical_op__write_cr0$58 + connect \logical_op__zero_a \setup_stage_logical_op__zero_a + connect \logical_op__zero_a$11 \setup_stage_logical_op__zero_a$55 + connect \muxid \setup_stage_muxid + connect \muxid$1 \setup_stage_muxid$45 + connect \operation \setup_stage_operation + connect \ra \setup_stage_ra + connect \rb \setup_stage_rb + connect \xer_so \setup_stage_xer_so + connect \xer_so$20 \setup_stage_xer_so$64 + end + attribute \src "libresoc.v:162061.7-162061.20" + process $proc$libresoc.v:162061$10014 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:162070.7-162070.25" + process $proc$libresoc.v:162070$10015 + assign { } { } + assign $1\div_by_zero[0:0] 1'0 + sync always + sync init + update \div_by_zero $1\div_by_zero[0:0] + end + attribute \src "libresoc.v:162077.7-162077.27" + process $proc$libresoc.v:162077$10016 + assign { } { } + assign $1\dive_abs_ov32[0:0] 1'0 + sync always + sync init + update \dive_abs_ov32 $1\dive_abs_ov32[0:0] + end + attribute \src "libresoc.v:162084.7-162084.27" + process $proc$libresoc.v:162084$10017 + assign { } { } + assign $1\dive_abs_ov64[0:0] 1'0 + sync always + sync init + update \dive_abs_ov64 $1\dive_abs_ov64[0:0] + end + attribute \src "libresoc.v:162091.15-162091.63" + process $proc$libresoc.v:162091$10018 + assign { } { } + assign $1\dividend[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dividend $1\dividend[127:0] + end + attribute \src "libresoc.v:162098.7-162098.26" + process $proc$libresoc.v:162098$10019 + assign { } { } + assign $1\dividend_neg[0:0] 1'0 + sync always + sync init + update \dividend_neg $1\dividend_neg[0:0] + end + attribute \src "libresoc.v:162105.7-162105.25" + process $proc$libresoc.v:162105$10020 + assign { } { } + assign $1\divisor_neg[0:0] 1'0 + sync always + sync init + update \divisor_neg $1\divisor_neg[0:0] + end + attribute \src "libresoc.v:162112.14-162112.53" + process $proc$libresoc.v:162112$10021 + assign { } { } + assign $1\divisor_radicand[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \divisor_radicand $1\divisor_radicand[63:0] + end + attribute \src "libresoc.v:162389.13-162389.40" + process $proc$libresoc.v:162389$10022 + assign { } { } + assign $1\logical_op__data_len[3:0] 4'0000 + sync always + sync init + update \logical_op__data_len $1\logical_op__data_len[3:0] + end + attribute \src "libresoc.v:162411.14-162411.43" + process $proc$libresoc.v:162411$10023 + assign { } { } + assign $1\logical_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \logical_op__fn_unit $1\logical_op__fn_unit[11:0] + end + attribute \src "libresoc.v:162446.14-162446.63" + process $proc$libresoc.v:162446$10024 + assign { } { } + assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:162455.7-162455.38" + process $proc$libresoc.v:162455$10025 + assign { } { } + assign $1\logical_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:162468.13-162468.43" + process $proc$libresoc.v:162468$10026 + assign { } { } + assign $1\logical_op__input_carry[1:0] 2'00 + sync always + sync init + update \logical_op__input_carry $1\logical_op__input_carry[1:0] + end + attribute \src "libresoc.v:162485.14-162485.38" + process $proc$libresoc.v:162485$10027 + assign { } { } + assign $1\logical_op__insn[31:0] 0 + sync always + sync init + update \logical_op__insn $1\logical_op__insn[31:0] + end + attribute \src "libresoc.v:162568.13-162568.42" + process $proc$libresoc.v:162568$10028 + assign { } { } + assign $1\logical_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \logical_op__insn_type $1\logical_op__insn_type[6:0] + end + attribute \src "libresoc.v:162725.7-162725.35" + process $proc$libresoc.v:162725$10029 + assign { } { } + assign $1\logical_op__invert_in[0:0] 1'0 + sync always + sync init + update \logical_op__invert_in $1\logical_op__invert_in[0:0] + end + attribute \src "libresoc.v:162734.7-162734.36" + process $proc$libresoc.v:162734$10030 + assign { } { } + assign $1\logical_op__invert_out[0:0] 1'0 + sync always + sync init + update \logical_op__invert_out $1\logical_op__invert_out[0:0] + end + attribute \src "libresoc.v:162743.7-162743.34" + process $proc$libresoc.v:162743$10031 + assign { } { } + assign $1\logical_op__is_32bit[0:0] 1'0 + sync always + sync init + update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] + end + attribute \src "libresoc.v:162752.7-162752.35" + process $proc$libresoc.v:162752$10032 + assign { } { } + assign $1\logical_op__is_signed[0:0] 1'0 + sync always + sync init + update \logical_op__is_signed $1\logical_op__is_signed[0:0] + end + attribute \src "libresoc.v:162761.7-162761.32" + process $proc$libresoc.v:162761$10033 + assign { } { } + assign $1\logical_op__oe__oe[0:0] 1'0 + sync always + sync init + update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] + end + attribute \src "libresoc.v:162770.7-162770.32" + process $proc$libresoc.v:162770$10034 + assign { } { } + assign $1\logical_op__oe__ok[0:0] 1'0 + sync always + sync init + update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] + end + attribute \src "libresoc.v:162779.7-162779.38" + process $proc$libresoc.v:162779$10035 + assign { } { } + assign $1\logical_op__output_carry[0:0] 1'0 + sync always + sync init + update \logical_op__output_carry $1\logical_op__output_carry[0:0] + end + attribute \src "libresoc.v:162788.7-162788.32" + process $proc$libresoc.v:162788$10036 + assign { } { } + assign $1\logical_op__rc__ok[0:0] 1'0 + sync always + sync init + update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] + end + attribute \src "libresoc.v:162797.7-162797.32" + process $proc$libresoc.v:162797$10037 + assign { } { } + assign $1\logical_op__rc__rc[0:0] 1'0 + sync always + sync init + update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] + end + attribute \src "libresoc.v:162806.7-162806.35" + process $proc$libresoc.v:162806$10038 + assign { } { } + assign $1\logical_op__write_cr0[0:0] 1'0 + sync always + sync init + update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] + end + attribute \src "libresoc.v:162815.7-162815.32" + process $proc$libresoc.v:162815$10039 + assign { } { } + assign $1\logical_op__zero_a[0:0] 1'0 + sync always + sync init + update \logical_op__zero_a $1\logical_op__zero_a[0:0] + end + attribute \src "libresoc.v:162824.13-162824.25" + process $proc$libresoc.v:162824$10040 + assign { } { } + assign $1\muxid[1:0] 2'00 + sync always + sync init + update \muxid $1\muxid[1:0] + end + attribute \src "libresoc.v:162839.13-162839.29" + process $proc$libresoc.v:162839$10041 + assign { } { } + assign $1\operation[1:0] 2'00 + sync always + sync init + update \operation $1\operation[1:0] + end + attribute \src "libresoc.v:162853.7-162853.20" + process $proc$libresoc.v:162853$10042 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:162858.14-162858.39" + process $proc$libresoc.v:162858$10043 + assign { } { } + assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ra $1\ra[63:0] + end + attribute \src "libresoc.v:162869.14-162869.39" + process $proc$libresoc.v:162869$10044 + assign { } { } + assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \rb $1\rb[63:0] + end + attribute \src "libresoc.v:163162.7-163162.20" + process $proc$libresoc.v:163162$10045 + assign { } { } + assign $1\xer_so[0:0] 1'0 + sync always + sync init + update \xer_so $1\xer_so[0:0] + end + attribute \src "libresoc.v:163170.3-163171.35" + process $proc$libresoc.v:163170$9900 + assign { } { } + assign $0\operation[1:0] \operation$next + sync posedge \coresync_clk + update \operation $0\operation[1:0] + end + attribute \src "libresoc.v:163172.3-163173.49" + process $proc$libresoc.v:163172$9901 + assign { } { } + assign $0\divisor_radicand[63:0] \divisor_radicand$next + sync posedge \coresync_clk + update \divisor_radicand $0\divisor_radicand[63:0] + end + attribute \src "libresoc.v:163174.3-163175.33" + process $proc$libresoc.v:163174$9902 + assign { } { } + assign $0\dividend[127:0] \dividend$next + sync posedge \coresync_clk + update \dividend $0\dividend[127:0] + end + attribute \src "libresoc.v:163176.3-163177.39" + process $proc$libresoc.v:163176$9903 + assign { } { } + assign $0\div_by_zero[0:0] \div_by_zero$next + sync posedge \coresync_clk + update \div_by_zero $0\div_by_zero[0:0] + end + attribute \src "libresoc.v:163178.3-163179.43" + process $proc$libresoc.v:163178$9904 + assign { } { } + assign $0\dive_abs_ov64[0:0] \dive_abs_ov64$next + sync posedge \coresync_clk + update \dive_abs_ov64 $0\dive_abs_ov64[0:0] + end + attribute \src "libresoc.v:163180.3-163181.43" + process $proc$libresoc.v:163180$9905 + assign { } { } + assign $0\dive_abs_ov32[0:0] \dive_abs_ov32$next + sync posedge \coresync_clk + update \dive_abs_ov32 $0\dive_abs_ov32[0:0] + end + attribute \src "libresoc.v:163182.3-163183.41" + process $proc$libresoc.v:163182$9906 + assign { } { } + assign $0\dividend_neg[0:0] \dividend_neg$next + sync posedge \coresync_clk + update \dividend_neg $0\dividend_neg[0:0] + end + attribute \src "libresoc.v:163184.3-163185.39" + process $proc$libresoc.v:163184$9907 + assign { } { } + assign $0\divisor_neg[0:0] \divisor_neg$next + sync posedge \coresync_clk + update \divisor_neg $0\divisor_neg[0:0] + end + attribute \src "libresoc.v:163186.3-163187.29" + process $proc$libresoc.v:163186$9908 + assign { } { } + assign $0\xer_so[0:0] \xer_so$next + sync posedge \coresync_clk + update \xer_so $0\xer_so[0:0] + end + attribute \src "libresoc.v:163188.3-163189.21" + process $proc$libresoc.v:163188$9909 + assign { } { } + assign $0\rb[63:0] \rb$next + sync posedge \coresync_clk + update \rb $0\rb[63:0] + end + attribute \src "libresoc.v:163190.3-163191.21" + process $proc$libresoc.v:163190$9910 + assign { } { } + assign $0\ra[63:0] \ra$next + sync posedge \coresync_clk + update \ra $0\ra[63:0] + end + attribute \src "libresoc.v:163192.3-163193.59" + process $proc$libresoc.v:163192$9911 + assign { } { } + assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next + sync posedge \coresync_clk + update \logical_op__insn_type $0\logical_op__insn_type[6:0] + end + attribute \src "libresoc.v:163194.3-163195.55" + process $proc$libresoc.v:163194$9912 + assign { } { } + assign $0\logical_op__fn_unit[11:0] \logical_op__fn_unit$next + sync posedge \coresync_clk + update \logical_op__fn_unit $0\logical_op__fn_unit[11:0] + end + attribute \src "libresoc.v:163196.3-163197.69" + process $proc$libresoc.v:163196$9913 + assign { } { } + assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next + sync posedge \coresync_clk + update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:163198.3-163199.65" + process $proc$libresoc.v:163198$9914 + assign { } { } + assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next + sync posedge \coresync_clk + update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:163200.3-163201.53" + process $proc$libresoc.v:163200$9915 + assign { } { } + assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next + sync posedge \coresync_clk + update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] + end + attribute \src "libresoc.v:163202.3-163203.53" + process $proc$libresoc.v:163202$9916 + assign { } { } + assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next + sync posedge \coresync_clk + update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] + end + attribute \src "libresoc.v:163204.3-163205.53" + process $proc$libresoc.v:163204$9917 + assign { } { } + assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next + sync posedge \coresync_clk + update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] + end + attribute \src "libresoc.v:163206.3-163207.53" + process $proc$libresoc.v:163206$9918 + assign { } { } + assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next + sync posedge \coresync_clk + update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] + end + attribute \src "libresoc.v:163208.3-163209.59" + process $proc$libresoc.v:163208$9919 + assign { } { } + assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next + sync posedge \coresync_clk + update \logical_op__invert_in $0\logical_op__invert_in[0:0] + end + attribute \src "libresoc.v:163210.3-163211.53" + process $proc$libresoc.v:163210$9920 + assign { } { } + assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next + sync posedge \coresync_clk + update \logical_op__zero_a $0\logical_op__zero_a[0:0] + end + attribute \src "libresoc.v:163212.3-163213.63" + process $proc$libresoc.v:163212$9921 + assign { } { } + assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next + sync posedge \coresync_clk + update \logical_op__input_carry $0\logical_op__input_carry[1:0] + end + attribute \src "libresoc.v:163214.3-163215.61" + process $proc$libresoc.v:163214$9922 + assign { } { } + assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next + sync posedge \coresync_clk + update \logical_op__invert_out $0\logical_op__invert_out[0:0] + end + attribute \src "libresoc.v:163216.3-163217.59" + process $proc$libresoc.v:163216$9923 + assign { } { } + assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next + sync posedge \coresync_clk + update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] + end + attribute \src "libresoc.v:163218.3-163219.65" + process $proc$libresoc.v:163218$9924 + assign { } { } + assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next + sync posedge \coresync_clk + update \logical_op__output_carry $0\logical_op__output_carry[0:0] + end + attribute \src "libresoc.v:163220.3-163221.57" + process $proc$libresoc.v:163220$9925 + assign { } { } + assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next + sync posedge \coresync_clk + update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] + end + attribute \src "libresoc.v:163222.3-163223.59" + process $proc$libresoc.v:163222$9926 + assign { } { } + assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next + sync posedge \coresync_clk + update \logical_op__is_signed $0\logical_op__is_signed[0:0] + end + attribute \src "libresoc.v:163224.3-163225.57" + process $proc$libresoc.v:163224$9927 + assign { } { } + assign $0\logical_op__data_len[3:0] \logical_op__data_len$next + sync posedge \coresync_clk + update \logical_op__data_len $0\logical_op__data_len[3:0] + end + attribute \src "libresoc.v:163226.3-163227.49" + process $proc$libresoc.v:163226$9928 + assign { } { } + assign $0\logical_op__insn[31:0] \logical_op__insn$next + sync posedge \coresync_clk + update \logical_op__insn $0\logical_op__insn[31:0] + end + attribute \src "libresoc.v:163228.3-163229.27" + process $proc$libresoc.v:163228$9929 + assign { } { } + assign $0\muxid[1:0] \muxid$next + sync posedge \coresync_clk + update \muxid $0\muxid[1:0] + end + attribute \src "libresoc.v:163230.3-163231.29" + process $proc$libresoc.v:163230$9930 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:163338.3-163350.6" + process $proc$libresoc.v:163338$9931 + assign { } { } + assign { } { } + assign $0\divisor_neg$next[0:0]$9932 $1\divisor_neg$next[0:0]$9933 + attribute \src "libresoc.v:163339.5-163339.29" + switch \initial + attribute \src "libresoc.v:163339.9-163339.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\divisor_neg$next[0:0]$9933 \divisor_neg$92 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\divisor_neg$next[0:0]$9933 \divisor_neg$92 + case + assign $1\divisor_neg$next[0:0]$9933 \divisor_neg + end + sync always + update \divisor_neg$next $0\divisor_neg$next[0:0]$9932 + end + attribute \src "libresoc.v:163351.3-163363.6" + process $proc$libresoc.v:163351$9934 + assign { } { } + assign { } { } + assign $0\dividend_neg$next[0:0]$9935 $1\dividend_neg$next[0:0]$9936 + attribute \src "libresoc.v:163352.5-163352.29" + switch \initial + attribute \src "libresoc.v:163352.9-163352.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\dividend_neg$next[0:0]$9936 \dividend_neg$93 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dividend_neg$next[0:0]$9936 \dividend_neg$93 + case + assign $1\dividend_neg$next[0:0]$9936 \dividend_neg + end + sync always + update \dividend_neg$next $0\dividend_neg$next[0:0]$9935 + end + attribute \src "libresoc.v:163364.3-163376.6" + process $proc$libresoc.v:163364$9937 + assign { } { } + assign { } { } + assign $0\dive_abs_ov32$next[0:0]$9938 $1\dive_abs_ov32$next[0:0]$9939 + attribute \src "libresoc.v:163365.5-163365.29" + switch \initial + attribute \src "libresoc.v:163365.9-163365.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\dive_abs_ov32$next[0:0]$9939 \dive_abs_ov32$94 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dive_abs_ov32$next[0:0]$9939 \dive_abs_ov32$94 + case + assign $1\dive_abs_ov32$next[0:0]$9939 \dive_abs_ov32 + end + sync always + update \dive_abs_ov32$next $0\dive_abs_ov32$next[0:0]$9938 + end + attribute \src "libresoc.v:163377.3-163389.6" + process $proc$libresoc.v:163377$9940 + assign { } { } + assign { } { } + assign $0\dive_abs_ov64$next[0:0]$9941 $1\dive_abs_ov64$next[0:0]$9942 + attribute \src "libresoc.v:163378.5-163378.29" + switch \initial + attribute \src "libresoc.v:163378.9-163378.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\dive_abs_ov64$next[0:0]$9942 \dive_abs_ov64$95 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dive_abs_ov64$next[0:0]$9942 \dive_abs_ov64$95 + case + assign $1\dive_abs_ov64$next[0:0]$9942 \dive_abs_ov64 + end + sync always + update \dive_abs_ov64$next $0\dive_abs_ov64$next[0:0]$9941 + end + attribute \src "libresoc.v:163390.3-163402.6" + process $proc$libresoc.v:163390$9943 + assign { } { } + assign { } { } + assign $0\div_by_zero$next[0:0]$9944 $1\div_by_zero$next[0:0]$9945 + attribute \src "libresoc.v:163391.5-163391.29" + switch \initial + attribute \src "libresoc.v:163391.9-163391.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\div_by_zero$next[0:0]$9945 \div_by_zero$96 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\div_by_zero$next[0:0]$9945 \div_by_zero$96 + case + assign $1\div_by_zero$next[0:0]$9945 \div_by_zero + end + sync always + update \div_by_zero$next $0\div_by_zero$next[0:0]$9944 + end + attribute \src "libresoc.v:163403.3-163415.6" + process $proc$libresoc.v:163403$9946 + assign { } { } + assign { } { } + assign $0\dividend$next[127:0]$9947 $1\dividend$next[127:0]$9948 + attribute \src "libresoc.v:163404.5-163404.29" + switch \initial + attribute \src "libresoc.v:163404.9-163404.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\dividend$next[127:0]$9948 \dividend$97 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dividend$next[127:0]$9948 \dividend$97 + case + assign $1\dividend$next[127:0]$9948 \dividend + end + sync always + update \dividend$next $0\dividend$next[127:0]$9947 + end + attribute \src "libresoc.v:163416.3-163428.6" + process $proc$libresoc.v:163416$9949 + assign { } { } + assign { } { } + assign $0\divisor_radicand$next[63:0]$9950 $1\divisor_radicand$next[63:0]$9951 + attribute \src "libresoc.v:163417.5-163417.29" + switch \initial + attribute \src "libresoc.v:163417.9-163417.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\divisor_radicand$next[63:0]$9951 \divisor_radicand$98 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\divisor_radicand$next[63:0]$9951 \divisor_radicand$98 + case + assign $1\divisor_radicand$next[63:0]$9951 \divisor_radicand + end + sync always + update \divisor_radicand$next $0\divisor_radicand$next[63:0]$9950 + end + attribute \src "libresoc.v:163429.3-163441.6" + process $proc$libresoc.v:163429$9952 + assign { } { } + assign { } { } + assign $0\operation$next[1:0]$9953 $1\operation$next[1:0]$9954 + attribute \src "libresoc.v:163430.5-163430.29" + switch \initial + attribute \src "libresoc.v:163430.9-163430.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\operation$next[1:0]$9954 \operation$99 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\operation$next[1:0]$9954 \operation$99 + case + assign $1\operation$next[1:0]$9954 \operation + end + sync always + update \operation$next $0\operation$next[1:0]$9953 + end + attribute \src "libresoc.v:163442.3-163459.6" + process $proc$libresoc.v:163442$9955 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$9956 $2\r_busy$next[0:0]$9958 + attribute \src "libresoc.v:163443.5-163443.29" + switch \initial + attribute \src "libresoc.v:163443.9-163443.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$9957 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$9957 1'0 + case + assign $1\r_busy$next[0:0]$9957 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$9958 1'0 + case + assign $2\r_busy$next[0:0]$9958 $1\r_busy$next[0:0]$9957 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$9956 + end + attribute \src "libresoc.v:163460.3-163472.6" + process $proc$libresoc.v:163460$9959 + assign { } { } + assign { } { } + assign $0\muxid$next[1:0]$9960 $1\muxid$next[1:0]$9961 + attribute \src "libresoc.v:163461.5-163461.29" + switch \initial + attribute \src "libresoc.v:163461.9-163461.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$next[1:0]$9961 \muxid$68 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$next[1:0]$9961 \muxid$68 + case + assign $1\muxid$next[1:0]$9961 \muxid + end + sync always + update \muxid$next $0\muxid$next[1:0]$9960 + end + attribute \src "libresoc.v:163473.3-163514.6" + process $proc$libresoc.v:163473$9962 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\logical_op__data_len$next[3:0]$9963 $1\logical_op__data_len$next[3:0]$9981 + assign $0\logical_op__fn_unit$next[11:0]$9964 $1\logical_op__fn_unit$next[11:0]$9982 + assign { } { } + assign { } { } + assign $0\logical_op__input_carry$next[1:0]$9967 $1\logical_op__input_carry$next[1:0]$9985 + assign $0\logical_op__insn$next[31:0]$9968 $1\logical_op__insn$next[31:0]$9986 + assign $0\logical_op__insn_type$next[6:0]$9969 $1\logical_op__insn_type$next[6:0]$9987 + assign $0\logical_op__invert_in$next[0:0]$9970 $1\logical_op__invert_in$next[0:0]$9988 + assign $0\logical_op__invert_out$next[0:0]$9971 $1\logical_op__invert_out$next[0:0]$9989 + assign $0\logical_op__is_32bit$next[0:0]$9972 $1\logical_op__is_32bit$next[0:0]$9990 + assign $0\logical_op__is_signed$next[0:0]$9973 $1\logical_op__is_signed$next[0:0]$9991 + assign { } { } + assign { } { } + assign $0\logical_op__output_carry$next[0:0]$9976 $1\logical_op__output_carry$next[0:0]$9994 + assign { } { } + assign { } { } + assign $0\logical_op__write_cr0$next[0:0]$9979 $1\logical_op__write_cr0$next[0:0]$9997 + assign $0\logical_op__zero_a$next[0:0]$9980 $1\logical_op__zero_a$next[0:0]$9998 + assign $0\logical_op__imm_data__data$next[63:0]$9965 $2\logical_op__imm_data__data$next[63:0]$9999 + assign $0\logical_op__imm_data__ok$next[0:0]$9966 $2\logical_op__imm_data__ok$next[0:0]$10000 + assign $0\logical_op__oe__oe$next[0:0]$9974 $2\logical_op__oe__oe$next[0:0]$10001 + assign $0\logical_op__oe__ok$next[0:0]$9975 $2\logical_op__oe__ok$next[0:0]$10002 + assign $0\logical_op__rc__ok$next[0:0]$9977 $2\logical_op__rc__ok$next[0:0]$10003 + assign $0\logical_op__rc__rc$next[0:0]$9978 $2\logical_op__rc__rc$next[0:0]$10004 + attribute \src "libresoc.v:163474.5-163474.29" + switch \initial + attribute \src "libresoc.v:163474.9-163474.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$next[31:0]$9986 $1\logical_op__data_len$next[3:0]$9981 $1\logical_op__is_signed$next[0:0]$9991 $1\logical_op__is_32bit$next[0:0]$9990 $1\logical_op__output_carry$next[0:0]$9994 $1\logical_op__write_cr0$next[0:0]$9997 $1\logical_op__invert_out$next[0:0]$9989 $1\logical_op__input_carry$next[1:0]$9985 $1\logical_op__zero_a$next[0:0]$9998 $1\logical_op__invert_in$next[0:0]$9988 $1\logical_op__oe__ok$next[0:0]$9993 $1\logical_op__oe__oe$next[0:0]$9992 $1\logical_op__rc__ok$next[0:0]$9995 $1\logical_op__rc__rc$next[0:0]$9996 $1\logical_op__imm_data__ok$next[0:0]$9984 $1\logical_op__imm_data__data$next[63:0]$9983 $1\logical_op__fn_unit$next[11:0]$9982 $1\logical_op__insn_type$next[6:0]$9987 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$next[31:0]$9986 $1\logical_op__data_len$next[3:0]$9981 $1\logical_op__is_signed$next[0:0]$9991 $1\logical_op__is_32bit$next[0:0]$9990 $1\logical_op__output_carry$next[0:0]$9994 $1\logical_op__write_cr0$next[0:0]$9997 $1\logical_op__invert_out$next[0:0]$9989 $1\logical_op__input_carry$next[1:0]$9985 $1\logical_op__zero_a$next[0:0]$9998 $1\logical_op__invert_in$next[0:0]$9988 $1\logical_op__oe__ok$next[0:0]$9993 $1\logical_op__oe__oe$next[0:0]$9992 $1\logical_op__rc__ok$next[0:0]$9995 $1\logical_op__rc__rc$next[0:0]$9996 $1\logical_op__imm_data__ok$next[0:0]$9984 $1\logical_op__imm_data__data$next[63:0]$9983 $1\logical_op__fn_unit$next[11:0]$9982 $1\logical_op__insn_type$next[6:0]$9987 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } + case + assign $1\logical_op__data_len$next[3:0]$9981 \logical_op__data_len + assign $1\logical_op__fn_unit$next[11:0]$9982 \logical_op__fn_unit + assign $1\logical_op__imm_data__data$next[63:0]$9983 \logical_op__imm_data__data + assign $1\logical_op__imm_data__ok$next[0:0]$9984 \logical_op__imm_data__ok + assign $1\logical_op__input_carry$next[1:0]$9985 \logical_op__input_carry + assign $1\logical_op__insn$next[31:0]$9986 \logical_op__insn + assign $1\logical_op__insn_type$next[6:0]$9987 \logical_op__insn_type + assign $1\logical_op__invert_in$next[0:0]$9988 \logical_op__invert_in + assign $1\logical_op__invert_out$next[0:0]$9989 \logical_op__invert_out + assign $1\logical_op__is_32bit$next[0:0]$9990 \logical_op__is_32bit + assign $1\logical_op__is_signed$next[0:0]$9991 \logical_op__is_signed + assign $1\logical_op__oe__oe$next[0:0]$9992 \logical_op__oe__oe + assign $1\logical_op__oe__ok$next[0:0]$9993 \logical_op__oe__ok + assign $1\logical_op__output_carry$next[0:0]$9994 \logical_op__output_carry + assign $1\logical_op__rc__ok$next[0:0]$9995 \logical_op__rc__ok + assign $1\logical_op__rc__rc$next[0:0]$9996 \logical_op__rc__rc + assign $1\logical_op__write_cr0$next[0:0]$9997 \logical_op__write_cr0 + assign $1\logical_op__zero_a$next[0:0]$9998 \logical_op__zero_a + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\logical_op__imm_data__data$next[63:0]$9999 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$next[0:0]$10000 1'0 + assign $2\logical_op__rc__rc$next[0:0]$10004 1'0 + assign $2\logical_op__rc__ok$next[0:0]$10003 1'0 + assign $2\logical_op__oe__oe$next[0:0]$10001 1'0 + assign $2\logical_op__oe__ok$next[0:0]$10002 1'0 + case + assign $2\logical_op__imm_data__data$next[63:0]$9999 $1\logical_op__imm_data__data$next[63:0]$9983 + assign $2\logical_op__imm_data__ok$next[0:0]$10000 $1\logical_op__imm_data__ok$next[0:0]$9984 + assign $2\logical_op__oe__oe$next[0:0]$10001 $1\logical_op__oe__oe$next[0:0]$9992 + assign $2\logical_op__oe__ok$next[0:0]$10002 $1\logical_op__oe__ok$next[0:0]$9993 + assign $2\logical_op__rc__ok$next[0:0]$10003 $1\logical_op__rc__ok$next[0:0]$9995 + assign $2\logical_op__rc__rc$next[0:0]$10004 $1\logical_op__rc__rc$next[0:0]$9996 + end + sync always + update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$9963 + update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[11:0]$9964 + update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$9965 + update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$9966 + update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$9967 + update \logical_op__insn$next $0\logical_op__insn$next[31:0]$9968 + update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$9969 + update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$9970 + update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$9971 + update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$9972 + update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$9973 + update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$9974 + update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$9975 + update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$9976 + update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$9977 + update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$9978 + update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$9979 + update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$9980 + end + attribute \src "libresoc.v:163515.3-163527.6" + process $proc$libresoc.v:163515$10005 + assign { } { } + assign { } { } + assign $0\ra$next[63:0]$10006 $1\ra$next[63:0]$10007 + attribute \src "libresoc.v:163516.5-163516.29" + switch \initial + attribute \src "libresoc.v:163516.9-163516.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\ra$next[63:0]$10007 \ra$87 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\ra$next[63:0]$10007 \ra$87 + case + assign $1\ra$next[63:0]$10007 \ra + end + sync always + update \ra$next $0\ra$next[63:0]$10006 + end + attribute \src "libresoc.v:163528.3-163540.6" + process $proc$libresoc.v:163528$10008 + assign { } { } + assign { } { } + assign $0\rb$next[63:0]$10009 $1\rb$next[63:0]$10010 + attribute \src "libresoc.v:163529.5-163529.29" + switch \initial + attribute \src "libresoc.v:163529.9-163529.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\rb$next[63:0]$10010 \rb$89 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\rb$next[63:0]$10010 \rb$89 + case + assign $1\rb$next[63:0]$10010 \rb + end + sync always + update \rb$next $0\rb$next[63:0]$10009 + end + attribute \src "libresoc.v:163541.3-163553.6" + process $proc$libresoc.v:163541$10011 + assign { } { } + assign { } { } + assign $0\xer_so$next[0:0]$10012 $1\xer_so$next[0:0]$10013 + attribute \src "libresoc.v:163542.5-163542.29" + switch \initial + attribute \src "libresoc.v:163542.9-163542.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\xer_so$next[0:0]$10013 \xer_so$91 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\xer_so$next[0:0]$10013 \xer_so$91 + case + assign $1\xer_so$next[0:0]$10013 \xer_so + end + sync always + update \xer_so$next $0\xer_so$next[0:0]$10012 + end + connect \$66 $and$libresoc.v:163169$9899_Y + connect \ra$88 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \rb$90 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect \operation$99 \setup_stage_operation + connect \divisor_radicand$98 \setup_stage_divisor_radicand + connect \dividend$97 \setup_stage_dividend + connect \div_by_zero$96 \setup_stage_div_by_zero + connect \dive_abs_ov64$95 \setup_stage_dive_abs_ov64 + connect \dive_abs_ov32$94 \setup_stage_dive_abs_ov32 + connect \dividend_neg$93 \setup_stage_dividend_neg + connect \divisor_neg$92 \setup_stage_divisor_neg + connect \xer_so$91 \setup_stage_xer_so$64 + connect \rb$89 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \ra$87 64'0000000000000000000000000000000000000000000000000000000000000000 + connect { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } { \setup_stage_logical_op__insn$63 \setup_stage_logical_op__data_len$62 \setup_stage_logical_op__is_signed$61 \setup_stage_logical_op__is_32bit$60 \setup_stage_logical_op__output_carry$59 \setup_stage_logical_op__write_cr0$58 \setup_stage_logical_op__invert_out$57 \setup_stage_logical_op__input_carry$56 \setup_stage_logical_op__zero_a$55 \setup_stage_logical_op__invert_in$54 \setup_stage_logical_op__oe__ok$53 \setup_stage_logical_op__oe__oe$52 \setup_stage_logical_op__rc__ok$51 \setup_stage_logical_op__rc__rc$50 \setup_stage_logical_op__imm_data__ok$49 \setup_stage_logical_op__imm_data__data$48 \setup_stage_logical_op__fn_unit$47 \setup_stage_logical_op__insn_type$46 } + connect \muxid$68 \setup_stage_muxid$45 + connect \p_valid_i_p_ready_o \$66 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$65 \p_valid_i + connect \setup_stage_xer_so \input_xer_so$44 + connect \setup_stage_rb \input_rb$43 + connect \setup_stage_ra \input_ra$42 + connect { \setup_stage_logical_op__insn \setup_stage_logical_op__data_len \setup_stage_logical_op__is_signed \setup_stage_logical_op__is_32bit \setup_stage_logical_op__output_carry \setup_stage_logical_op__write_cr0 \setup_stage_logical_op__invert_out \setup_stage_logical_op__input_carry \setup_stage_logical_op__zero_a \setup_stage_logical_op__invert_in \setup_stage_logical_op__oe__ok \setup_stage_logical_op__oe__oe \setup_stage_logical_op__rc__ok \setup_stage_logical_op__rc__rc \setup_stage_logical_op__imm_data__ok \setup_stage_logical_op__imm_data__data \setup_stage_logical_op__fn_unit \setup_stage_logical_op__insn_type } { \input_logical_op__insn$41 \input_logical_op__data_len$40 \input_logical_op__is_signed$39 \input_logical_op__is_32bit$38 \input_logical_op__output_carry$37 \input_logical_op__write_cr0$36 \input_logical_op__invert_out$35 \input_logical_op__input_carry$34 \input_logical_op__zero_a$33 \input_logical_op__invert_in$32 \input_logical_op__oe__ok$31 \input_logical_op__oe__oe$30 \input_logical_op__rc__ok$29 \input_logical_op__rc__rc$28 \input_logical_op__imm_data__ok$27 \input_logical_op__imm_data__data$26 \input_logical_op__fn_unit$25 \input_logical_op__insn_type$24 } + connect \setup_stage_muxid \input_muxid$23 + connect \input_xer_so \xer_so$22 + connect \input_rb \rb$21 + connect \input_ra \ra$20 + connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } + connect \input_muxid \muxid$1 +end +attribute \src "libresoc.v:163588.1-163632.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.pll" +attribute \generator "nMigen" +module \pll + attribute \src "libresoc.v:163589.7-163589.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:163621.3-163630.6" + wire $0\pll_18_o[0:0] + attribute \src "libresoc.v:163611.3-163620.6" + wire $0\pll_lck_o[0:0] + attribute \src "libresoc.v:163621.3-163630.6" + wire $1\pll_18_o[0:0] + attribute \src "libresoc.v:163611.3-163620.6" + wire $1\pll_lck_o[0:0] + attribute \src "libresoc.v:163608.17-163608.105" + wire $eq$libresoc.v:163608$10046_Y + attribute \src "libresoc.v:163609.17-163609.105" + wire $eq$libresoc.v:163609$10047_Y + attribute \src "libresoc.v:163610.17-163610.98" + wire $not$libresoc.v:163610$10048_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9" + wire input 1 \clk_24_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" + wire output 5 \clk_pll_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" + wire width 2 input 3 \clk_sel_i + attribute \src "libresoc.v:163589.7-163589.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" + wire output 2 \pll_18_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" + wire output 4 \pll_lck_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + cell $eq $eq$libresoc.v:163608$10046 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \clk_sel_i + connect \B 2'00 + connect \Y $eq$libresoc.v:163608$10046_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + cell $eq $eq$libresoc.v:163609$10047 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \clk_sel_i + connect \B 2'00 + connect \Y $eq$libresoc.v:163609$10047_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" + cell $not $not$libresoc.v:163610$10048 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \clk_24_i + connect \Y $not$libresoc.v:163610$10048_Y + end + attribute \src "libresoc.v:163589.7-163589.20" + process $proc$libresoc.v:163589$10051 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:163611.3-163620.6" + process $proc$libresoc.v:163611$10049 + assign { } { } + assign { } { } + assign $0\pll_lck_o[0:0] $1\pll_lck_o[0:0] + attribute \src "libresoc.v:163612.5-163612.29" + switch \initial + attribute \src "libresoc.v:163612.9-163612.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pll_lck_o[0:0] \clk_24_i + case + assign $1\pll_lck_o[0:0] 1'0 + end + sync always + update \pll_lck_o $0\pll_lck_o[0:0] + end + attribute \src "libresoc.v:163621.3-163630.6" + process $proc$libresoc.v:163621$10050 + assign { } { } + assign { } { } + assign $0\pll_18_o[0:0] $1\pll_18_o[0:0] + attribute \src "libresoc.v:163622.5-163622.29" + switch \initial + attribute \src "libresoc.v:163622.9-163622.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pll_18_o[0:0] \$5 + case + assign $1\pll_18_o[0:0] 1'0 + end + sync always + update \pll_18_o $0\pll_18_o[0:0] + end + connect \$1 $eq$libresoc.v:163608$10046_Y + connect \$3 $eq$libresoc.v:163609$10047_Y + connect \$5 $not$libresoc.v:163610$10048_Y + connect \clk_pll_o \clk_24_i +end +attribute \src "libresoc.v:163636.1-164278.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.popcount" +attribute \generator "nMigen" +module \popcount + attribute \src "libresoc.v:163637.7-163637.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:164125.3-164151.6" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:164125.3-164151.6" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:164049.19-164049.132" + wire width 4 $add$libresoc.v:164049$10052_Y + attribute \src "libresoc.v:164050.19-164050.132" + wire width 4 $add$libresoc.v:164050$10053_Y + attribute \src "libresoc.v:164051.19-164051.132" + wire width 4 $add$libresoc.v:164051$10054_Y + attribute \src "libresoc.v:164052.19-164052.132" + wire width 4 $add$libresoc.v:164052$10055_Y + attribute \src "libresoc.v:164053.19-164053.134" + wire width 4 $add$libresoc.v:164053$10056_Y + attribute \src "libresoc.v:164054.19-164054.134" + wire width 4 $add$libresoc.v:164054$10057_Y + attribute \src "libresoc.v:164055.18-164055.125" + wire width 3 $add$libresoc.v:164055$10058_Y + attribute \src "libresoc.v:164056.19-164056.134" + wire width 4 $add$libresoc.v:164056$10059_Y + attribute \src "libresoc.v:164057.19-164057.134" + wire width 4 $add$libresoc.v:164057$10060_Y + attribute \src "libresoc.v:164058.19-164058.134" + wire width 4 $add$libresoc.v:164058$10061_Y + attribute \src "libresoc.v:164059.19-164059.134" + wire width 4 $add$libresoc.v:164059$10062_Y + attribute \src "libresoc.v:164060.19-164060.134" + wire width 4 $add$libresoc.v:164060$10063_Y + attribute \src "libresoc.v:164061.19-164061.134" + wire width 4 $add$libresoc.v:164061$10064_Y + attribute \src "libresoc.v:164062.19-164062.134" + wire width 4 $add$libresoc.v:164062$10065_Y + attribute \src "libresoc.v:164063.19-164063.134" + wire width 4 $add$libresoc.v:164063$10066_Y + attribute \src "libresoc.v:164064.19-164064.134" + wire width 4 $add$libresoc.v:164064$10067_Y + attribute \src "libresoc.v:164065.19-164065.132" + wire width 5 $add$libresoc.v:164065$10068_Y + attribute \src "libresoc.v:164066.18-164066.125" + wire width 3 $add$libresoc.v:164066$10069_Y + attribute \src "libresoc.v:164067.19-164067.132" + wire width 5 $add$libresoc.v:164067$10070_Y + attribute \src "libresoc.v:164068.19-164068.132" + wire width 5 $add$libresoc.v:164068$10071_Y + attribute \src "libresoc.v:164069.19-164069.132" + wire width 5 $add$libresoc.v:164069$10072_Y + attribute \src "libresoc.v:164070.19-164070.132" + wire width 5 $add$libresoc.v:164070$10073_Y + attribute \src "libresoc.v:164071.19-164071.134" + wire width 5 $add$libresoc.v:164071$10074_Y + attribute \src "libresoc.v:164072.19-164072.134" + wire width 5 $add$libresoc.v:164072$10075_Y + attribute \src "libresoc.v:164073.19-164073.134" + wire width 5 $add$libresoc.v:164073$10076_Y + attribute \src "libresoc.v:164074.19-164074.132" + wire width 6 $add$libresoc.v:164074$10077_Y + attribute \src "libresoc.v:164075.19-164075.132" + wire width 6 $add$libresoc.v:164075$10078_Y + attribute \src "libresoc.v:164076.19-164076.132" + wire width 6 $add$libresoc.v:164076$10079_Y + attribute \src "libresoc.v:164077.18-164077.127" + wire width 3 $add$libresoc.v:164077$10080_Y + attribute \src "libresoc.v:164078.19-164078.132" + wire width 6 $add$libresoc.v:164078$10081_Y + attribute \src "libresoc.v:164079.19-164079.132" + wire width 7 $add$libresoc.v:164079$10082_Y + attribute \src "libresoc.v:164080.19-164080.132" + wire width 7 $add$libresoc.v:164080$10083_Y + attribute \src "libresoc.v:164081.19-164081.132" + wire width 8 $add$libresoc.v:164081$10084_Y + attribute \src "libresoc.v:164092.18-164092.127" + wire width 3 $add$libresoc.v:164092$10103_Y + attribute \src "libresoc.v:164096.18-164096.127" + wire width 3 $add$libresoc.v:164096$10110_Y + attribute \src "libresoc.v:164097.18-164097.127" + wire width 3 $add$libresoc.v:164097$10111_Y + attribute \src "libresoc.v:164098.17-164098.124" + wire width 3 $add$libresoc.v:164098$10112_Y + attribute \src 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$add$libresoc.v:164077$10080_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:164078$10081 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { 2'00 \pop_4_6 } + connect \B { 2'00 \pop_4_7 } + connect \Y $add$libresoc.v:164078$10081_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:164079$10082 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A { 2'00 \pop_5_0 } + connect \B { 2'00 \pop_5_1 } + connect \Y $add$libresoc.v:164079$10082_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:164080$10083 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A { 2'00 \pop_5_2 } + connect \B { 2'00 \pop_5_3 } + connect \Y $add$libresoc.v:164080$10083_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:164081$10084 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { 2'00 \pop_6_0 } + connect \B { 2'00 \pop_6_1 } + connect \Y $add$libresoc.v:164081$10084_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:164092$10103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [12] } + connect \B { 2'00 \a [13] } + connect \Y $add$libresoc.v:164092$10103_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:164096$10110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [14] } + connect \B { 2'00 \a [15] } + connect \Y $add$libresoc.v:164096$10110_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:164097$10111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [16] } + connect \B { 2'00 \a [17] } + connect \Y $add$libresoc.v:164097$10111_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:164098$10112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [0] } + connect \B { 2'00 \a [1] } + connect \Y $add$libresoc.v:164098$10112_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:164099$10113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [18] } + connect \B { 2'00 \a [19] } + connect \Y $add$libresoc.v:164099$10113_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:164100$10114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [20] } + connect \B { 2'00 \a [21] } + connect \Y $add$libresoc.v:164100$10114_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:164101$10115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [22] } + connect \B { 2'00 \a [23] } + connect \Y $add$libresoc.v:164101$10115_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:164102$10116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [24] } + connect \B { 2'00 \a [25] } + connect \Y $add$libresoc.v:164102$10116_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:164103$10117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [26] } + connect \B { 2'00 \a [27] } + connect \Y $add$libresoc.v:164103$10117_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:164104$10118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [28] } + connect \B { 2'00 \a [29] } + connect \Y $add$libresoc.v:164104$10118_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:164105$10119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [30] } + connect \B { 2'00 \a [31] } + connect \Y $add$libresoc.v:164105$10119_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:164106$10120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [32] } + connect \B { 2'00 \a [33] } + connect \Y $add$libresoc.v:164106$10120_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:164107$10121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [34] } + connect \B { 2'00 \a [35] } + connect \Y $add$libresoc.v:164107$10121_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:164108$10122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [36] } + connect \B { 2'00 \a [37] } + connect \Y $add$libresoc.v:164108$10122_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:164109$10123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [2] } + connect \B { 2'00 \a [3] } + connect \Y $add$libresoc.v:164109$10123_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:164110$10124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [38] } + connect \B { 2'00 \a [39] } + connect \Y $add$libresoc.v:164110$10124_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:164111$10125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [40] } + connect \B { 2'00 \a [41] } + connect \Y $add$libresoc.v:164111$10125_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:164112$10126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [42] } + connect \B { 2'00 \a [43] } + connect \Y $add$libresoc.v:164112$10126_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:164113$10127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [44] } + connect \B { 2'00 \a [45] } + connect \Y $add$libresoc.v:164113$10127_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:164114$10128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [46] } + connect \B { 2'00 \a [47] } + connect \Y $add$libresoc.v:164114$10128_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:164115$10129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [48] } + connect \B { 2'00 \a [49] } + connect \Y $add$libresoc.v:164115$10129_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:164116$10130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [50] } + connect \B { 2'00 \a [51] } + connect \Y $add$libresoc.v:164116$10130_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:164117$10131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [52] } + connect \B { 2'00 \a [53] } + connect \Y $add$libresoc.v:164117$10131_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:164118$10132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [54] } + connect \B { 2'00 \a [55] } + connect \Y $add$libresoc.v:164118$10132_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:164119$10133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [56] } + connect \B { 2'00 \a [57] } + connect \Y $add$libresoc.v:164119$10133_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:164120$10134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [4] } + connect \B { 2'00 \a [5] } + connect \Y $add$libresoc.v:164120$10134_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:164121$10135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [58] } + connect \B { 2'00 \a [59] } + connect \Y $add$libresoc.v:164121$10135_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:164122$10136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [60] } + connect \B { 2'00 \a [61] } + connect \Y $add$libresoc.v:164122$10136_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:164123$10137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [62] } + connect \B { 2'00 \a [63] } + connect \Y $add$libresoc.v:164123$10137_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:164124$10138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_0 } + connect \B { 2'00 \pop_2_1 } + connect \Y $add$libresoc.v:164124$10138_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" + cell $eq $eq$libresoc.v:164082$10085 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \data_len + connect \B 1'1 + connect \Y $eq$libresoc.v:164082$10085_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59" + cell $eq $eq$libresoc.v:164083$10086 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \data_len + connect \B 3'100 + connect \Y $eq$libresoc.v:164083$10086_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:164084$10087 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_0 + connect \Y $extend$libresoc.v:164084$10087_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:164085$10089 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_1 + connect \Y $extend$libresoc.v:164085$10089_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:164086$10091 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_2 + connect \Y $extend$libresoc.v:164086$10091_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:164087$10093 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_3 + connect \Y $extend$libresoc.v:164087$10093_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:164088$10095 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_4 + connect \Y $extend$libresoc.v:164088$10095_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:164089$10097 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_5 + connect \Y $extend$libresoc.v:164089$10097_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:164090$10099 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_6 + connect \Y $extend$libresoc.v:164090$10099_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:164091$10101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_7 + connect \Y $extend$libresoc.v:164091$10101_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:164093$10104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 32 + connect \A \pop_6_0 + connect \Y $extend$libresoc.v:164093$10104_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:164094$10106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 32 + connect \A \pop_6_1 + connect \Y $extend$libresoc.v:164094$10106_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:164095$10108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 64 + connect \A \pop_7_0 + connect \Y $extend$libresoc.v:164095$10108_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:164084$10088 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:164084$10087_Y + connect \Y $pos$libresoc.v:164084$10088_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:164085$10090 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:164085$10089_Y + connect \Y $pos$libresoc.v:164085$10090_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:164086$10092 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:164086$10091_Y + connect \Y $pos$libresoc.v:164086$10092_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:164087$10094 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:164087$10093_Y + connect \Y $pos$libresoc.v:164087$10094_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:164088$10096 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:164088$10095_Y + connect \Y $pos$libresoc.v:164088$10096_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:164089$10098 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:164089$10097_Y + connect \Y $pos$libresoc.v:164089$10098_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:164090$10100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:164090$10099_Y + connect \Y $pos$libresoc.v:164090$10100_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:164091$10102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:164091$10101_Y + connect \Y $pos$libresoc.v:164091$10102_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:164093$10105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $extend$libresoc.v:164093$10104_Y + connect \Y $pos$libresoc.v:164093$10105_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:164094$10107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $extend$libresoc.v:164094$10106_Y + connect \Y $pos$libresoc.v:164094$10107_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:164095$10109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:164095$10108_Y + connect \Y $pos$libresoc.v:164095$10109_Y + end + attribute \src "libresoc.v:163637.7-163637.20" + process $proc$libresoc.v:163637$10140 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:164125.3-164151.6" + process $proc$libresoc.v:164125$10139 + assign { } { } + assign $0\o[63:0] $1\o[63:0] + attribute \src "libresoc.v:164126.5-164126.29" + switch \initial + attribute \src "libresoc.v:164126.9-164126.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" + switch { \$192 \$190 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\o[63:0] [7:0] \$194 + assign $1\o[63:0] [15:8] \$196 + assign $1\o[63:0] [23:16] \$198 + assign $1\o[63:0] [31:24] \$200 + assign $1\o[63:0] [39:32] \$202 + assign $1\o[63:0] [47:40] \$204 + assign $1\o[63:0] [55:48] \$206 + assign $1\o[63:0] [63:56] \$208 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\o[63:0] [31:0] \$210 + assign $1\o[63:0] [63:32] \$212 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\o[63:0] \$214 + end + sync always + update \o $0\o[63:0] + end + connect \$101 $add$libresoc.v:164049$10052_Y + connect \$104 $add$libresoc.v:164050$10053_Y + connect \$107 $add$libresoc.v:164051$10054_Y + connect \$110 $add$libresoc.v:164052$10055_Y + connect \$113 $add$libresoc.v:164053$10056_Y + connect \$116 $add$libresoc.v:164054$10057_Y + connect \$11 $add$libresoc.v:164055$10058_Y + connect \$119 $add$libresoc.v:164056$10059_Y + connect \$122 $add$libresoc.v:164057$10060_Y + connect \$125 $add$libresoc.v:164058$10061_Y + connect \$128 $add$libresoc.v:164059$10062_Y + connect \$131 $add$libresoc.v:164060$10063_Y + connect \$134 $add$libresoc.v:164061$10064_Y + connect \$137 $add$libresoc.v:164062$10065_Y + connect \$140 $add$libresoc.v:164063$10066_Y + connect \$143 $add$libresoc.v:164064$10067_Y + connect \$146 $add$libresoc.v:164065$10068_Y + connect \$14 $add$libresoc.v:164066$10069_Y + connect \$149 $add$libresoc.v:164067$10070_Y + connect \$152 $add$libresoc.v:164068$10071_Y + connect \$155 $add$libresoc.v:164069$10072_Y + connect \$158 $add$libresoc.v:164070$10073_Y + connect \$161 $add$libresoc.v:164071$10074_Y + connect \$164 $add$libresoc.v:164072$10075_Y + connect \$167 $add$libresoc.v:164073$10076_Y + connect \$170 $add$libresoc.v:164074$10077_Y + connect \$173 $add$libresoc.v:164075$10078_Y + connect \$176 $add$libresoc.v:164076$10079_Y + connect \$17 $add$libresoc.v:164077$10080_Y + connect \$179 $add$libresoc.v:164078$10081_Y + connect \$182 $add$libresoc.v:164079$10082_Y + connect \$185 $add$libresoc.v:164080$10083_Y + connect \$188 $add$libresoc.v:164081$10084_Y + connect \$190 $eq$libresoc.v:164082$10085_Y + connect \$192 $eq$libresoc.v:164083$10086_Y + connect \$194 $pos$libresoc.v:164084$10088_Y + connect \$196 $pos$libresoc.v:164085$10090_Y + connect \$198 $pos$libresoc.v:164086$10092_Y + connect \$200 $pos$libresoc.v:164087$10094_Y + connect \$202 $pos$libresoc.v:164088$10096_Y + connect \$204 $pos$libresoc.v:164089$10098_Y + connect \$206 $pos$libresoc.v:164090$10100_Y + connect \$208 $pos$libresoc.v:164091$10102_Y + connect \$20 $add$libresoc.v:164092$10103_Y + connect \$210 $pos$libresoc.v:164093$10105_Y + connect \$212 $pos$libresoc.v:164094$10107_Y + connect \$214 $pos$libresoc.v:164095$10109_Y + connect \$23 $add$libresoc.v:164096$10110_Y + connect \$26 $add$libresoc.v:164097$10111_Y + connect \$2 $add$libresoc.v:164098$10112_Y + connect \$29 $add$libresoc.v:164099$10113_Y + connect \$32 $add$libresoc.v:164100$10114_Y + connect \$35 $add$libresoc.v:164101$10115_Y + connect \$38 $add$libresoc.v:164102$10116_Y + connect \$41 $add$libresoc.v:164103$10117_Y + connect \$44 $add$libresoc.v:164104$10118_Y + connect \$47 $add$libresoc.v:164105$10119_Y + connect \$50 $add$libresoc.v:164106$10120_Y + connect \$53 $add$libresoc.v:164107$10121_Y + connect \$56 $add$libresoc.v:164108$10122_Y + connect \$5 $add$libresoc.v:164109$10123_Y + connect \$59 $add$libresoc.v:164110$10124_Y + connect \$62 $add$libresoc.v:164111$10125_Y + connect \$65 $add$libresoc.v:164112$10126_Y + connect \$68 $add$libresoc.v:164113$10127_Y + connect \$71 $add$libresoc.v:164114$10128_Y + connect \$74 $add$libresoc.v:164115$10129_Y + connect \$77 $add$libresoc.v:164116$10130_Y + connect \$80 $add$libresoc.v:164117$10131_Y + connect \$83 $add$libresoc.v:164118$10132_Y + connect \$86 $add$libresoc.v:164119$10133_Y + connect \$8 $add$libresoc.v:164120$10134_Y + connect \$89 $add$libresoc.v:164121$10135_Y + connect \$92 $add$libresoc.v:164122$10136_Y + connect \$95 $add$libresoc.v:164123$10137_Y + connect \$98 $add$libresoc.v:164124$10138_Y + connect \$1 \$2 + connect \$4 \$5 + connect \$7 \$8 + connect \$10 \$11 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 + connect \$25 \$26 + connect \$28 \$29 + connect \$31 \$32 + connect \$34 \$35 + connect \$37 \$38 + connect \$40 \$41 + connect \$43 \$44 + connect \$46 \$47 + connect \$49 \$50 + connect \$52 \$53 + connect \$55 \$56 + connect \$58 \$59 + connect \$61 \$62 + connect \$64 \$65 + connect \$67 \$68 + connect \$70 \$71 + connect \$73 \$74 + connect \$76 \$77 + connect \$79 \$80 + connect \$82 \$83 + connect \$85 \$86 + connect \$88 \$89 + connect \$91 \$92 + connect \$94 \$95 + connect \$97 \$98 + connect \$100 \$101 + connect \$103 \$104 + connect \$106 \$107 + connect \$109 \$110 + connect \$112 \$113 + connect \$115 \$116 + connect \$118 \$119 + connect \$121 \$122 + connect \$124 \$125 + connect \$127 \$128 + connect \$130 \$131 + connect \$133 \$134 + connect \$136 \$137 + connect \$139 \$140 + connect \$142 \$143 + connect \$145 \$146 + connect \$148 \$149 + connect \$151 \$152 + connect \$154 \$155 + connect \$157 \$158 + connect \$160 \$161 + connect \$163 \$164 + connect \$166 \$167 + connect \$169 \$170 + connect \$172 \$173 + connect \$175 \$176 + connect \$178 \$179 + connect \$181 \$182 + connect \$184 \$185 + connect \$187 \$188 + connect \pop_7_0 \$188 [6:0] + connect \pop_6_1 \$185 [5:0] + connect \pop_6_0 \$182 [5:0] + connect \pop_5_3 \$179 [4:0] + connect \pop_5_2 \$176 [4:0] + connect \pop_5_1 \$173 [4:0] + connect \pop_5_0 \$170 [4:0] + connect \pop_4_7 \$167 [3:0] + connect \pop_4_6 \$164 [3:0] + connect \pop_4_5 \$161 [3:0] + connect \pop_4_4 \$158 [3:0] + connect \pop_4_3 \$155 [3:0] + connect \pop_4_2 \$152 [3:0] + connect \pop_4_1 \$149 [3:0] + connect \pop_4_0 \$146 [3:0] + connect \pop_3_15 \$143 [2:0] + connect \pop_3_14 \$140 [2:0] + connect \pop_3_13 \$137 [2:0] + connect \pop_3_12 \$134 [2:0] + connect \pop_3_11 \$131 [2:0] + connect \pop_3_10 \$128 [2:0] + connect \pop_3_9 \$125 [2:0] + connect \pop_3_8 \$122 [2:0] + connect \pop_3_7 \$119 [2:0] + connect \pop_3_6 \$116 [2:0] + connect \pop_3_5 \$113 [2:0] + connect \pop_3_4 \$110 [2:0] + connect \pop_3_3 \$107 [2:0] + connect \pop_3_2 \$104 [2:0] + connect \pop_3_1 \$101 [2:0] + connect \pop_3_0 \$98 [2:0] + connect \pop_2_31 \$95 [1:0] + connect \pop_2_30 \$92 [1:0] + connect \pop_2_29 \$89 [1:0] + connect \pop_2_28 \$86 [1:0] + connect \pop_2_27 \$83 [1:0] + connect \pop_2_26 \$80 [1:0] + connect \pop_2_25 \$77 [1:0] + connect \pop_2_24 \$74 [1:0] + connect \pop_2_23 \$71 [1:0] + connect \pop_2_22 \$68 [1:0] + connect \pop_2_21 \$65 [1:0] + connect \pop_2_20 \$62 [1:0] + connect \pop_2_19 \$59 [1:0] + connect \pop_2_18 \$56 [1:0] + connect \pop_2_17 \$53 [1:0] + connect \pop_2_16 \$50 [1:0] + connect \pop_2_15 \$47 [1:0] + connect \pop_2_14 \$44 [1:0] + connect \pop_2_13 \$41 [1:0] + connect \pop_2_12 \$38 [1:0] + connect \pop_2_11 \$35 [1:0] + connect \pop_2_10 \$32 [1:0] + connect \pop_2_9 \$29 [1:0] + connect \pop_2_8 \$26 [1:0] + connect \pop_2_7 \$23 [1:0] + connect \pop_2_6 \$20 [1:0] + connect \pop_2_5 \$17 [1:0] + connect \pop_2_4 \$14 [1:0] + connect \pop_2_3 \$11 [1:0] + connect \pop_2_2 \$8 [1:0] + connect \pop_2_1 \$5 [1:0] + connect \pop_2_0 \$2 [1:0] +end +attribute \src "libresoc.v:164282.1-164366.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick + attribute \src "libresoc.v:164339.17-164339.91" + wire $not$libresoc.v:164339$10141_Y + attribute \src "libresoc.v:164341.18-164341.93" + wire $not$libresoc.v:164341$10143_Y + attribute \src "libresoc.v:164343.18-164343.93" + wire $not$libresoc.v:164343$10145_Y + attribute \src "libresoc.v:164344.17-164344.138" + wire width 8 $not$libresoc.v:164344$10146_Y + attribute \src "libresoc.v:164346.18-164346.93" + wire $not$libresoc.v:164346$10148_Y + attribute \src "libresoc.v:164348.18-164348.93" + wire $not$libresoc.v:164348$10150_Y + attribute \src "libresoc.v:164350.18-164350.93" + wire $not$libresoc.v:164350$10152_Y + attribute \src "libresoc.v:164353.17-164353.91" + wire $not$libresoc.v:164353$10155_Y + attribute \src "libresoc.v:164340.18-164340.116" + wire $reduce_or$libresoc.v:164340$10142_Y + attribute \src "libresoc.v:164342.18-164342.122" + wire $reduce_or$libresoc.v:164342$10144_Y + attribute \src "libresoc.v:164345.18-164345.128" + wire $reduce_or$libresoc.v:164345$10147_Y + attribute \src "libresoc.v:164347.18-164347.134" + wire $reduce_or$libresoc.v:164347$10149_Y + attribute \src "libresoc.v:164349.18-164349.140" + wire $reduce_or$libresoc.v:164349$10151_Y + attribute \src "libresoc.v:164351.18-164351.90" + wire $reduce_or$libresoc.v:164351$10153_Y + attribute \src "libresoc.v:164352.17-164352.103" + wire $reduce_or$libresoc.v:164352$10154_Y + attribute \src "libresoc.v:164354.17-164354.109" + wire $reduce_or$libresoc.v:164354$10156_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164339$10141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:164339$10141_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164341$10143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:164341$10143_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164343$10145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:164343$10145_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:164344$10146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:164344$10146_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164346$10148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:164346$10148_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164348$10150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:164348$10150_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164350$10152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:164350$10152_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164353$10155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:164353$10155_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164340$10142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:164340$10142_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164342$10144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:164342$10144_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164345$10147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:164345$10147_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164347$10149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:164347$10149_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164349$10151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:164349$10151_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:164351$10153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:164351$10153_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164352$10154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:164352$10154_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164354$10156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:164354$10156_Y + end + connect \$7 $not$libresoc.v:164339$10141_Y + connect \$12 $reduce_or$libresoc.v:164340$10142_Y + connect \$11 $not$libresoc.v:164341$10143_Y + connect \$16 $reduce_or$libresoc.v:164342$10144_Y + connect \$15 $not$libresoc.v:164343$10145_Y + connect \$1 $not$libresoc.v:164344$10146_Y + connect \$20 $reduce_or$libresoc.v:164345$10147_Y + connect \$19 $not$libresoc.v:164346$10148_Y + connect \$24 $reduce_or$libresoc.v:164347$10149_Y + connect \$23 $not$libresoc.v:164348$10150_Y + connect \$28 $reduce_or$libresoc.v:164349$10151_Y + connect \$27 $not$libresoc.v:164350$10152_Y + connect \$31 $reduce_or$libresoc.v:164351$10153_Y + connect \$4 $reduce_or$libresoc.v:164352$10154_Y + connect \$3 $not$libresoc.v:164353$10155_Y + connect \$8 $reduce_or$libresoc.v:164354$10156_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:164370.1-164454.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$139 + attribute \src "libresoc.v:164427.17-164427.91" + wire $not$libresoc.v:164427$10157_Y + attribute \src "libresoc.v:164429.18-164429.93" + wire $not$libresoc.v:164429$10159_Y + attribute \src "libresoc.v:164431.18-164431.93" + wire $not$libresoc.v:164431$10161_Y + attribute \src "libresoc.v:164432.17-164432.138" + wire width 8 $not$libresoc.v:164432$10162_Y + attribute \src "libresoc.v:164434.18-164434.93" + wire $not$libresoc.v:164434$10164_Y + attribute \src "libresoc.v:164436.18-164436.93" + wire $not$libresoc.v:164436$10166_Y + attribute \src "libresoc.v:164438.18-164438.93" + wire $not$libresoc.v:164438$10168_Y + attribute \src "libresoc.v:164441.17-164441.91" + wire $not$libresoc.v:164441$10171_Y + attribute \src "libresoc.v:164428.18-164428.116" + wire $reduce_or$libresoc.v:164428$10158_Y + attribute \src "libresoc.v:164430.18-164430.122" + wire $reduce_or$libresoc.v:164430$10160_Y + attribute \src "libresoc.v:164433.18-164433.128" + wire $reduce_or$libresoc.v:164433$10163_Y + attribute \src "libresoc.v:164435.18-164435.134" + wire $reduce_or$libresoc.v:164435$10165_Y + attribute \src "libresoc.v:164437.18-164437.140" + wire $reduce_or$libresoc.v:164437$10167_Y + attribute \src "libresoc.v:164439.18-164439.90" + wire $reduce_or$libresoc.v:164439$10169_Y + attribute \src "libresoc.v:164440.17-164440.103" + wire $reduce_or$libresoc.v:164440$10170_Y + attribute \src "libresoc.v:164442.17-164442.109" + wire $reduce_or$libresoc.v:164442$10172_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164427$10157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:164427$10157_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164429$10159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:164429$10159_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164431$10161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:164431$10161_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:164432$10162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:164432$10162_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164434$10164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:164434$10164_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164436$10166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:164436$10166_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164438$10168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:164438$10168_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164441$10171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:164441$10171_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164428$10158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:164428$10158_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164430$10160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:164430$10160_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164433$10163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:164433$10163_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164435$10165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:164435$10165_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164437$10167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:164437$10167_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:164439$10169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:164439$10169_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164440$10170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:164440$10170_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164442$10172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:164442$10172_Y + end + connect \$7 $not$libresoc.v:164427$10157_Y + connect \$12 $reduce_or$libresoc.v:164428$10158_Y + connect \$11 $not$libresoc.v:164429$10159_Y + connect \$16 $reduce_or$libresoc.v:164430$10160_Y + connect \$15 $not$libresoc.v:164431$10161_Y + connect \$1 $not$libresoc.v:164432$10162_Y + connect \$20 $reduce_or$libresoc.v:164433$10163_Y + connect \$19 $not$libresoc.v:164434$10164_Y + connect \$24 $reduce_or$libresoc.v:164435$10165_Y + connect \$23 $not$libresoc.v:164436$10166_Y + connect \$28 $reduce_or$libresoc.v:164437$10167_Y + connect \$27 $not$libresoc.v:164438$10168_Y + connect \$31 $reduce_or$libresoc.v:164439$10169_Y + connect \$4 $reduce_or$libresoc.v:164440$10170_Y + connect \$3 $not$libresoc.v:164441$10171_Y + connect \$8 $reduce_or$libresoc.v:164442$10172_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:164458.1-164542.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick$144 + attribute \src "libresoc.v:164515.17-164515.91" + wire $not$libresoc.v:164515$10173_Y + attribute \src "libresoc.v:164517.18-164517.93" + wire $not$libresoc.v:164517$10175_Y + attribute \src "libresoc.v:164519.18-164519.93" + wire $not$libresoc.v:164519$10177_Y + attribute \src "libresoc.v:164520.17-164520.138" + wire width 8 $not$libresoc.v:164520$10178_Y + attribute \src "libresoc.v:164522.18-164522.93" + wire $not$libresoc.v:164522$10180_Y + attribute \src "libresoc.v:164524.18-164524.93" + wire $not$libresoc.v:164524$10182_Y + attribute \src "libresoc.v:164526.18-164526.93" + wire $not$libresoc.v:164526$10184_Y + attribute \src "libresoc.v:164529.17-164529.91" + wire $not$libresoc.v:164529$10187_Y + attribute \src "libresoc.v:164516.18-164516.116" + wire $reduce_or$libresoc.v:164516$10174_Y + attribute \src "libresoc.v:164518.18-164518.122" + wire $reduce_or$libresoc.v:164518$10176_Y + attribute \src "libresoc.v:164521.18-164521.128" + wire $reduce_or$libresoc.v:164521$10179_Y + attribute \src "libresoc.v:164523.18-164523.134" + wire $reduce_or$libresoc.v:164523$10181_Y + attribute \src "libresoc.v:164525.18-164525.140" + wire $reduce_or$libresoc.v:164525$10183_Y + attribute \src "libresoc.v:164527.18-164527.90" + wire $reduce_or$libresoc.v:164527$10185_Y + attribute \src "libresoc.v:164528.17-164528.103" + wire $reduce_or$libresoc.v:164528$10186_Y + attribute \src "libresoc.v:164530.17-164530.109" + wire $reduce_or$libresoc.v:164530$10188_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164515$10173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:164515$10173_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164517$10175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:164517$10175_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164519$10177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:164519$10177_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:164520$10178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:164520$10178_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164522$10180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:164522$10180_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164524$10182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:164524$10182_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164526$10184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:164526$10184_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164529$10187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:164529$10187_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164516$10174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:164516$10174_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164518$10176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:164518$10176_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164521$10179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:164521$10179_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164523$10181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:164523$10181_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164525$10183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:164525$10183_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:164527$10185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:164527$10185_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164528$10186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:164528$10186_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164530$10188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:164530$10188_Y + end + connect \$7 $not$libresoc.v:164515$10173_Y + connect \$12 $reduce_or$libresoc.v:164516$10174_Y + connect \$11 $not$libresoc.v:164517$10175_Y + connect \$16 $reduce_or$libresoc.v:164518$10176_Y + connect \$15 $not$libresoc.v:164519$10177_Y + connect \$1 $not$libresoc.v:164520$10178_Y + connect \$20 $reduce_or$libresoc.v:164521$10179_Y + connect \$19 $not$libresoc.v:164522$10180_Y + connect \$24 $reduce_or$libresoc.v:164523$10181_Y + connect \$23 $not$libresoc.v:164524$10182_Y + connect \$28 $reduce_or$libresoc.v:164525$10183_Y + connect \$27 $not$libresoc.v:164526$10184_Y + connect \$31 $reduce_or$libresoc.v:164527$10185_Y + connect \$4 $reduce_or$libresoc.v:164528$10186_Y + connect \$3 $not$libresoc.v:164529$10187_Y + connect \$8 $reduce_or$libresoc.v:164530$10188_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:164546.1-164630.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$146 + attribute \src "libresoc.v:164603.17-164603.91" + wire $not$libresoc.v:164603$10189_Y + attribute \src "libresoc.v:164605.18-164605.93" + wire $not$libresoc.v:164605$10191_Y + attribute \src "libresoc.v:164607.18-164607.93" + wire $not$libresoc.v:164607$10193_Y + attribute \src "libresoc.v:164608.17-164608.138" + wire width 8 $not$libresoc.v:164608$10194_Y + attribute \src "libresoc.v:164610.18-164610.93" + wire $not$libresoc.v:164610$10196_Y + attribute \src "libresoc.v:164612.18-164612.93" + wire $not$libresoc.v:164612$10198_Y + attribute \src "libresoc.v:164614.18-164614.93" + wire $not$libresoc.v:164614$10200_Y + attribute \src "libresoc.v:164617.17-164617.91" + wire $not$libresoc.v:164617$10203_Y + attribute \src "libresoc.v:164604.18-164604.116" + wire $reduce_or$libresoc.v:164604$10190_Y + attribute \src "libresoc.v:164606.18-164606.122" + wire $reduce_or$libresoc.v:164606$10192_Y + attribute \src "libresoc.v:164609.18-164609.128" + wire $reduce_or$libresoc.v:164609$10195_Y + attribute \src "libresoc.v:164611.18-164611.134" + wire $reduce_or$libresoc.v:164611$10197_Y + attribute \src "libresoc.v:164613.18-164613.140" + wire $reduce_or$libresoc.v:164613$10199_Y + attribute \src "libresoc.v:164615.18-164615.90" + wire $reduce_or$libresoc.v:164615$10201_Y + attribute \src "libresoc.v:164616.17-164616.103" + wire $reduce_or$libresoc.v:164616$10202_Y + attribute \src "libresoc.v:164618.17-164618.109" + wire $reduce_or$libresoc.v:164618$10204_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164603$10189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:164603$10189_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164605$10191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:164605$10191_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164607$10193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:164607$10193_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:164608$10194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:164608$10194_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164610$10196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:164610$10196_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164612$10198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:164612$10198_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164614$10200 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:164614$10200_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164617$10203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:164617$10203_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164604$10190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:164604$10190_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164606$10192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:164606$10192_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164609$10195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:164609$10195_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164611$10197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:164611$10197_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164613$10199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:164613$10199_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:164615$10201 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:164615$10201_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164616$10202 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:164616$10202_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164618$10204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:164618$10204_Y + end + connect \$7 $not$libresoc.v:164603$10189_Y + connect \$12 $reduce_or$libresoc.v:164604$10190_Y + connect \$11 $not$libresoc.v:164605$10191_Y + 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"test_issuer.ti.core.dec_BRANCH.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick$151 + attribute \src "libresoc.v:164691.17-164691.91" + wire $not$libresoc.v:164691$10205_Y + attribute \src "libresoc.v:164693.18-164693.93" + wire $not$libresoc.v:164693$10207_Y + attribute \src "libresoc.v:164695.18-164695.93" + wire $not$libresoc.v:164695$10209_Y + attribute \src "libresoc.v:164696.17-164696.138" + wire width 8 $not$libresoc.v:164696$10210_Y + attribute \src "libresoc.v:164698.18-164698.93" + wire $not$libresoc.v:164698$10212_Y + attribute \src "libresoc.v:164700.18-164700.93" + wire $not$libresoc.v:164700$10214_Y + attribute \src "libresoc.v:164702.18-164702.93" + wire $not$libresoc.v:164702$10216_Y + attribute \src "libresoc.v:164705.17-164705.91" + wire $not$libresoc.v:164705$10219_Y + attribute \src "libresoc.v:164692.18-164692.116" + wire $reduce_or$libresoc.v:164692$10206_Y + attribute \src "libresoc.v:164694.18-164694.122" + wire $reduce_or$libresoc.v:164694$10208_Y + attribute \src "libresoc.v:164697.18-164697.128" + wire $reduce_or$libresoc.v:164697$10211_Y + attribute \src "libresoc.v:164699.18-164699.134" + wire $reduce_or$libresoc.v:164699$10213_Y + attribute \src "libresoc.v:164701.18-164701.140" + wire $reduce_or$libresoc.v:164701$10215_Y + attribute \src "libresoc.v:164703.18-164703.90" + wire $reduce_or$libresoc.v:164703$10217_Y + attribute \src "libresoc.v:164704.17-164704.103" + wire $reduce_or$libresoc.v:164704$10218_Y + attribute \src "libresoc.v:164706.17-164706.109" + wire $reduce_or$libresoc.v:164706$10220_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164691$10205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:164691$10205_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164693$10207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:164693$10207_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164695$10209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:164695$10209_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:164696$10210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:164696$10210_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164698$10212 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:164698$10212_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164700$10214 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:164700$10214_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164702$10216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:164702$10216_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164705$10219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:164705$10219_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164692$10206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:164692$10206_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164694$10208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:164694$10208_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164697$10211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:164697$10211_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164699$10213 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:164699$10213_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164701$10215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:164701$10215_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:164703$10217 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:164703$10217_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164704$10218 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:164704$10218_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164706$10220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:164706$10220_Y + end + connect \$7 $not$libresoc.v:164691$10205_Y + connect \$12 $reduce_or$libresoc.v:164692$10206_Y + connect \$11 $not$libresoc.v:164693$10207_Y + connect \$16 $reduce_or$libresoc.v:164694$10208_Y + connect \$15 $not$libresoc.v:164695$10209_Y + connect \$1 $not$libresoc.v:164696$10210_Y + connect \$20 $reduce_or$libresoc.v:164697$10211_Y + connect \$19 $not$libresoc.v:164698$10212_Y + connect \$24 $reduce_or$libresoc.v:164699$10213_Y + connect \$23 $not$libresoc.v:164700$10214_Y + connect \$28 $reduce_or$libresoc.v:164701$10215_Y + connect \$27 $not$libresoc.v:164702$10216_Y + connect \$31 $reduce_or$libresoc.v:164703$10217_Y + connect \$4 $reduce_or$libresoc.v:164704$10218_Y + connect \$3 $not$libresoc.v:164705$10219_Y + connect \$8 $reduce_or$libresoc.v:164706$10220_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:164722.1-164806.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$153 + attribute \src "libresoc.v:164779.17-164779.91" + wire $not$libresoc.v:164779$10221_Y + attribute \src "libresoc.v:164781.18-164781.93" + wire $not$libresoc.v:164781$10223_Y + attribute \src "libresoc.v:164783.18-164783.93" + wire $not$libresoc.v:164783$10225_Y + attribute \src "libresoc.v:164784.17-164784.138" + wire width 8 $not$libresoc.v:164784$10226_Y + attribute \src "libresoc.v:164786.18-164786.93" + wire $not$libresoc.v:164786$10228_Y + attribute \src "libresoc.v:164788.18-164788.93" + wire $not$libresoc.v:164788$10230_Y + attribute \src "libresoc.v:164790.18-164790.93" + wire $not$libresoc.v:164790$10232_Y + attribute \src "libresoc.v:164793.17-164793.91" + wire $not$libresoc.v:164793$10235_Y + attribute \src "libresoc.v:164780.18-164780.116" + wire $reduce_or$libresoc.v:164780$10222_Y + attribute \src "libresoc.v:164782.18-164782.122" + wire $reduce_or$libresoc.v:164782$10224_Y + attribute \src "libresoc.v:164785.18-164785.128" + wire $reduce_or$libresoc.v:164785$10227_Y + attribute \src "libresoc.v:164787.18-164787.134" + wire $reduce_or$libresoc.v:164787$10229_Y + attribute \src "libresoc.v:164789.18-164789.140" + wire $reduce_or$libresoc.v:164789$10231_Y + attribute \src "libresoc.v:164791.18-164791.90" + wire $reduce_or$libresoc.v:164791$10233_Y + attribute \src "libresoc.v:164792.17-164792.103" + wire $reduce_or$libresoc.v:164792$10234_Y + attribute \src "libresoc.v:164794.17-164794.109" + wire $reduce_or$libresoc.v:164794$10236_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164779$10221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:164779$10221_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164781$10223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:164781$10223_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164783$10225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:164783$10225_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:164784$10226 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:164784$10226_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164786$10228 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:164786$10228_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164788$10230 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:164788$10230_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164790$10232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:164790$10232_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164793$10235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:164793$10235_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164780$10222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:164780$10222_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164782$10224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:164782$10224_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164785$10227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:164785$10227_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164787$10229 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:164787$10229_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164789$10231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:164789$10231_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:164791$10233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:164791$10233_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164792$10234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:164792$10234_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164794$10236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:164794$10236_Y + end + connect \$7 $not$libresoc.v:164779$10221_Y + connect \$12 $reduce_or$libresoc.v:164780$10222_Y + connect \$11 $not$libresoc.v:164781$10223_Y + connect \$16 $reduce_or$libresoc.v:164782$10224_Y + connect \$15 $not$libresoc.v:164783$10225_Y + connect \$1 $not$libresoc.v:164784$10226_Y + connect \$20 $reduce_or$libresoc.v:164785$10227_Y + connect \$19 $not$libresoc.v:164786$10228_Y + connect \$24 $reduce_or$libresoc.v:164787$10229_Y + connect \$23 $not$libresoc.v:164788$10230_Y + connect \$28 $reduce_or$libresoc.v:164789$10231_Y + connect \$27 $not$libresoc.v:164790$10232_Y + connect \$31 $reduce_or$libresoc.v:164791$10233_Y + connect \$4 $reduce_or$libresoc.v:164792$10234_Y + connect \$3 $not$libresoc.v:164793$10235_Y + connect \$8 $reduce_or$libresoc.v:164794$10236_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:164810.1-164894.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick$159 + attribute \src "libresoc.v:164867.17-164867.91" + wire $not$libresoc.v:164867$10237_Y + attribute \src "libresoc.v:164869.18-164869.93" + wire $not$libresoc.v:164869$10239_Y + attribute \src "libresoc.v:164871.18-164871.93" + wire $not$libresoc.v:164871$10241_Y + attribute \src "libresoc.v:164872.17-164872.138" + wire width 8 $not$libresoc.v:164872$10242_Y + attribute \src "libresoc.v:164874.18-164874.93" + wire $not$libresoc.v:164874$10244_Y + attribute \src "libresoc.v:164876.18-164876.93" + wire $not$libresoc.v:164876$10246_Y + attribute \src "libresoc.v:164878.18-164878.93" + wire $not$libresoc.v:164878$10248_Y + attribute \src "libresoc.v:164881.17-164881.91" + wire $not$libresoc.v:164881$10251_Y + attribute \src "libresoc.v:164868.18-164868.116" + wire $reduce_or$libresoc.v:164868$10238_Y + attribute \src "libresoc.v:164870.18-164870.122" + wire $reduce_or$libresoc.v:164870$10240_Y + attribute \src "libresoc.v:164873.18-164873.128" + wire $reduce_or$libresoc.v:164873$10243_Y + attribute \src "libresoc.v:164875.18-164875.134" + wire $reduce_or$libresoc.v:164875$10245_Y + attribute \src "libresoc.v:164877.18-164877.140" + wire $reduce_or$libresoc.v:164877$10247_Y + attribute \src "libresoc.v:164879.18-164879.90" + wire $reduce_or$libresoc.v:164879$10249_Y + attribute \src "libresoc.v:164880.17-164880.103" + wire $reduce_or$libresoc.v:164880$10250_Y + attribute \src "libresoc.v:164882.17-164882.109" + wire $reduce_or$libresoc.v:164882$10252_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164867$10237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:164867$10237_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164869$10239 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:164869$10239_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164871$10241 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:164871$10241_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:164872$10242 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:164872$10242_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164874$10244 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:164874$10244_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164876$10246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:164876$10246_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164878$10248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:164878$10248_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164881$10251 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:164881$10251_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164868$10238 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:164868$10238_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164870$10240 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:164870$10240_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164873$10243 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:164873$10243_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164875$10245 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:164875$10245_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164877$10247 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:164877$10247_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:164879$10249 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:164879$10249_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164880$10250 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:164880$10250_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164882$10252 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:164882$10252_Y + end + connect \$7 $not$libresoc.v:164867$10237_Y + connect \$12 $reduce_or$libresoc.v:164868$10238_Y + connect \$11 $not$libresoc.v:164869$10239_Y + connect \$16 $reduce_or$libresoc.v:164870$10240_Y + connect \$15 $not$libresoc.v:164871$10241_Y + connect \$1 $not$libresoc.v:164872$10242_Y + connect \$20 $reduce_or$libresoc.v:164873$10243_Y + connect \$19 $not$libresoc.v:164874$10244_Y + connect \$24 $reduce_or$libresoc.v:164875$10245_Y + connect \$23 $not$libresoc.v:164876$10246_Y + connect \$28 $reduce_or$libresoc.v:164877$10247_Y + connect \$27 $not$libresoc.v:164878$10248_Y + connect \$31 $reduce_or$libresoc.v:164879$10249_Y + connect \$4 $reduce_or$libresoc.v:164880$10250_Y + connect \$3 $not$libresoc.v:164881$10251_Y + connect \$8 $reduce_or$libresoc.v:164882$10252_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:164898.1-164982.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$161 + attribute \src "libresoc.v:164955.17-164955.91" + wire $not$libresoc.v:164955$10253_Y + attribute \src "libresoc.v:164957.18-164957.93" + wire $not$libresoc.v:164957$10255_Y + attribute \src "libresoc.v:164959.18-164959.93" + wire $not$libresoc.v:164959$10257_Y + attribute \src "libresoc.v:164960.17-164960.138" + wire width 8 $not$libresoc.v:164960$10258_Y + attribute \src "libresoc.v:164962.18-164962.93" + wire $not$libresoc.v:164962$10260_Y + attribute \src "libresoc.v:164964.18-164964.93" + wire $not$libresoc.v:164964$10262_Y + attribute \src "libresoc.v:164966.18-164966.93" + wire $not$libresoc.v:164966$10264_Y + attribute \src "libresoc.v:164969.17-164969.91" + wire $not$libresoc.v:164969$10267_Y + attribute \src "libresoc.v:164956.18-164956.116" + wire $reduce_or$libresoc.v:164956$10254_Y + attribute \src "libresoc.v:164958.18-164958.122" + wire $reduce_or$libresoc.v:164958$10256_Y + attribute \src "libresoc.v:164961.18-164961.128" + wire $reduce_or$libresoc.v:164961$10259_Y + attribute \src "libresoc.v:164963.18-164963.134" + wire $reduce_or$libresoc.v:164963$10261_Y + attribute \src "libresoc.v:164965.18-164965.140" + wire $reduce_or$libresoc.v:164965$10263_Y + attribute \src "libresoc.v:164967.18-164967.90" + wire $reduce_or$libresoc.v:164967$10265_Y + attribute \src "libresoc.v:164968.17-164968.103" + wire $reduce_or$libresoc.v:164968$10266_Y + attribute \src "libresoc.v:164970.17-164970.109" + wire $reduce_or$libresoc.v:164970$10268_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164955$10253 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:164955$10253_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164957$10255 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:164957$10255_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164959$10257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:164959$10257_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:164960$10258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:164960$10258_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164962$10260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:164962$10260_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164964$10262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:164964$10262_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164966$10264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:164966$10264_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:164969$10267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:164969$10267_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164956$10254 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:164956$10254_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164958$10256 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:164958$10256_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164961$10259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:164961$10259_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164963$10261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:164963$10261_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164965$10263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:164965$10263_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:164967$10265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:164967$10265_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164968$10266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:164968$10266_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:164970$10268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:164970$10268_Y + end + connect \$7 $not$libresoc.v:164955$10253_Y + connect \$12 $reduce_or$libresoc.v:164956$10254_Y + connect \$11 $not$libresoc.v:164957$10255_Y + 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attribute \src "libresoc.v:165049.18-165049.128" + wire $reduce_or$libresoc.v:165049$10275_Y + attribute \src "libresoc.v:165051.18-165051.134" + wire $reduce_or$libresoc.v:165051$10277_Y + attribute \src "libresoc.v:165053.18-165053.140" + wire $reduce_or$libresoc.v:165053$10279_Y + attribute \src "libresoc.v:165055.18-165055.90" + wire $reduce_or$libresoc.v:165055$10281_Y + attribute \src "libresoc.v:165056.17-165056.103" + wire $reduce_or$libresoc.v:165056$10282_Y + attribute \src "libresoc.v:165058.17-165058.109" + wire $reduce_or$libresoc.v:165058$10284_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165043$10269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:165043$10269_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165045$10271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:165045$10271_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165047$10273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:165047$10273_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:165048$10274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:165048$10274_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165050$10276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:165050$10276_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165052$10278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:165052$10278_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165054$10280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:165054$10280_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165057$10283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:165057$10283_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165044$10270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:165044$10270_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165046$10272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:165046$10272_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165049$10275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:165049$10275_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165051$10277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:165051$10277_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165053$10279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:165053$10279_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:165055$10281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:165055$10281_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165056$10282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:165056$10282_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165058$10284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:165058$10284_Y + end + connect \$7 $not$libresoc.v:165043$10269_Y + connect \$12 $reduce_or$libresoc.v:165044$10270_Y + connect \$11 $not$libresoc.v:165045$10271_Y + connect \$16 $reduce_or$libresoc.v:165046$10272_Y + connect \$15 $not$libresoc.v:165047$10273_Y + connect \$1 $not$libresoc.v:165048$10274_Y + connect \$20 $reduce_or$libresoc.v:165049$10275_Y + connect \$19 $not$libresoc.v:165050$10276_Y + connect \$24 $reduce_or$libresoc.v:165051$10277_Y + connect \$23 $not$libresoc.v:165052$10278_Y + connect \$28 $reduce_or$libresoc.v:165053$10279_Y + connect \$27 $not$libresoc.v:165054$10280_Y + connect \$31 $reduce_or$libresoc.v:165055$10281_Y + connect \$4 $reduce_or$libresoc.v:165056$10282_Y + connect \$3 $not$libresoc.v:165057$10283_Y + connect \$8 $reduce_or$libresoc.v:165058$10284_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:165074.1-165158.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$170 + attribute \src "libresoc.v:165131.17-165131.91" + wire $not$libresoc.v:165131$10285_Y + attribute \src "libresoc.v:165133.18-165133.93" + wire $not$libresoc.v:165133$10287_Y + attribute \src "libresoc.v:165135.18-165135.93" + wire $not$libresoc.v:165135$10289_Y + attribute \src "libresoc.v:165136.17-165136.138" + wire width 8 $not$libresoc.v:165136$10290_Y + attribute \src "libresoc.v:165138.18-165138.93" + wire $not$libresoc.v:165138$10292_Y + attribute \src "libresoc.v:165140.18-165140.93" + wire $not$libresoc.v:165140$10294_Y + attribute \src "libresoc.v:165142.18-165142.93" + wire $not$libresoc.v:165142$10296_Y + attribute \src "libresoc.v:165145.17-165145.91" + wire $not$libresoc.v:165145$10299_Y + attribute \src "libresoc.v:165132.18-165132.116" + wire $reduce_or$libresoc.v:165132$10286_Y + attribute \src "libresoc.v:165134.18-165134.122" + wire $reduce_or$libresoc.v:165134$10288_Y + attribute \src "libresoc.v:165137.18-165137.128" + wire $reduce_or$libresoc.v:165137$10291_Y + attribute \src "libresoc.v:165139.18-165139.134" + wire $reduce_or$libresoc.v:165139$10293_Y + attribute \src "libresoc.v:165141.18-165141.140" + wire $reduce_or$libresoc.v:165141$10295_Y + attribute \src "libresoc.v:165143.18-165143.90" + wire $reduce_or$libresoc.v:165143$10297_Y + attribute \src "libresoc.v:165144.17-165144.103" + wire $reduce_or$libresoc.v:165144$10298_Y + attribute \src "libresoc.v:165146.17-165146.109" + wire $reduce_or$libresoc.v:165146$10300_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165131$10285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:165131$10285_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165133$10287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:165133$10287_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165135$10289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:165135$10289_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:165136$10290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:165136$10290_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165138$10292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:165138$10292_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165140$10294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:165140$10294_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165142$10296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:165142$10296_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165145$10299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:165145$10299_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165132$10286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:165132$10286_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165134$10288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:165134$10288_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165137$10291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:165137$10291_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165139$10293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:165139$10293_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165141$10295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:165141$10295_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:165143$10297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:165143$10297_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165144$10298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:165144$10298_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165146$10300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:165146$10300_Y + end + connect \$7 $not$libresoc.v:165131$10285_Y + connect \$12 $reduce_or$libresoc.v:165132$10286_Y + connect \$11 $not$libresoc.v:165133$10287_Y + connect \$16 $reduce_or$libresoc.v:165134$10288_Y + connect \$15 $not$libresoc.v:165135$10289_Y + connect \$1 $not$libresoc.v:165136$10290_Y + connect \$20 $reduce_or$libresoc.v:165137$10291_Y + connect \$19 $not$libresoc.v:165138$10292_Y + connect \$24 $reduce_or$libresoc.v:165139$10293_Y + connect \$23 $not$libresoc.v:165140$10294_Y + connect \$28 $reduce_or$libresoc.v:165141$10295_Y + connect \$27 $not$libresoc.v:165142$10296_Y + connect \$31 $reduce_or$libresoc.v:165143$10297_Y + connect \$4 $reduce_or$libresoc.v:165144$10298_Y + connect \$3 $not$libresoc.v:165145$10299_Y + connect \$8 $reduce_or$libresoc.v:165146$10300_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:165162.1-165246.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick$175 + attribute \src "libresoc.v:165219.17-165219.91" + wire $not$libresoc.v:165219$10301_Y + attribute \src "libresoc.v:165221.18-165221.93" + wire $not$libresoc.v:165221$10303_Y + attribute \src "libresoc.v:165223.18-165223.93" + wire $not$libresoc.v:165223$10305_Y + attribute \src "libresoc.v:165224.17-165224.138" + wire width 8 $not$libresoc.v:165224$10306_Y + attribute \src "libresoc.v:165226.18-165226.93" + wire $not$libresoc.v:165226$10308_Y + attribute \src "libresoc.v:165228.18-165228.93" + wire $not$libresoc.v:165228$10310_Y + attribute \src "libresoc.v:165230.18-165230.93" + wire $not$libresoc.v:165230$10312_Y + attribute \src "libresoc.v:165233.17-165233.91" + wire $not$libresoc.v:165233$10315_Y + attribute \src "libresoc.v:165220.18-165220.116" + wire $reduce_or$libresoc.v:165220$10302_Y + attribute \src "libresoc.v:165222.18-165222.122" + wire $reduce_or$libresoc.v:165222$10304_Y + attribute \src "libresoc.v:165225.18-165225.128" + wire $reduce_or$libresoc.v:165225$10307_Y + attribute \src "libresoc.v:165227.18-165227.134" + wire $reduce_or$libresoc.v:165227$10309_Y + attribute \src "libresoc.v:165229.18-165229.140" + wire $reduce_or$libresoc.v:165229$10311_Y + attribute \src "libresoc.v:165231.18-165231.90" + wire $reduce_or$libresoc.v:165231$10313_Y + attribute \src "libresoc.v:165232.17-165232.103" + wire $reduce_or$libresoc.v:165232$10314_Y + attribute \src "libresoc.v:165234.17-165234.109" + wire $reduce_or$libresoc.v:165234$10316_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165219$10301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:165219$10301_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165221$10303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:165221$10303_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165223$10305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:165223$10305_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:165224$10306 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:165224$10306_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165226$10308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:165226$10308_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165228$10310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:165228$10310_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165230$10312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:165230$10312_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165233$10315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:165233$10315_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165220$10302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:165220$10302_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165222$10304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:165222$10304_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165225$10307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:165225$10307_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165227$10309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:165227$10309_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165229$10311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:165229$10311_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:165231$10313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:165231$10313_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165232$10314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:165232$10314_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165234$10316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:165234$10316_Y + end + connect \$7 $not$libresoc.v:165219$10301_Y + connect \$12 $reduce_or$libresoc.v:165220$10302_Y + connect \$11 $not$libresoc.v:165221$10303_Y + connect \$16 $reduce_or$libresoc.v:165222$10304_Y + connect \$15 $not$libresoc.v:165223$10305_Y + connect \$1 $not$libresoc.v:165224$10306_Y + connect \$20 $reduce_or$libresoc.v:165225$10307_Y + connect \$19 $not$libresoc.v:165226$10308_Y + connect \$24 $reduce_or$libresoc.v:165227$10309_Y + connect \$23 $not$libresoc.v:165228$10310_Y + connect \$28 $reduce_or$libresoc.v:165229$10311_Y + connect \$27 $not$libresoc.v:165230$10312_Y + connect \$31 $reduce_or$libresoc.v:165231$10313_Y + connect \$4 $reduce_or$libresoc.v:165232$10314_Y + connect \$3 $not$libresoc.v:165233$10315_Y + connect \$8 $reduce_or$libresoc.v:165234$10316_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:165250.1-165334.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$177 + attribute \src "libresoc.v:165307.17-165307.91" + wire $not$libresoc.v:165307$10317_Y + attribute \src "libresoc.v:165309.18-165309.93" + wire $not$libresoc.v:165309$10319_Y + attribute \src "libresoc.v:165311.18-165311.93" + wire $not$libresoc.v:165311$10321_Y + attribute \src "libresoc.v:165312.17-165312.138" + wire width 8 $not$libresoc.v:165312$10322_Y + attribute \src "libresoc.v:165314.18-165314.93" + wire $not$libresoc.v:165314$10324_Y + attribute \src "libresoc.v:165316.18-165316.93" + wire $not$libresoc.v:165316$10326_Y + attribute \src "libresoc.v:165318.18-165318.93" + wire $not$libresoc.v:165318$10328_Y + attribute \src "libresoc.v:165321.17-165321.91" + wire $not$libresoc.v:165321$10331_Y + attribute \src "libresoc.v:165308.18-165308.116" + wire $reduce_or$libresoc.v:165308$10318_Y + attribute \src "libresoc.v:165310.18-165310.122" + wire $reduce_or$libresoc.v:165310$10320_Y + attribute \src "libresoc.v:165313.18-165313.128" + wire $reduce_or$libresoc.v:165313$10323_Y + attribute \src "libresoc.v:165315.18-165315.134" + wire $reduce_or$libresoc.v:165315$10325_Y + attribute \src "libresoc.v:165317.18-165317.140" + wire $reduce_or$libresoc.v:165317$10327_Y + attribute \src "libresoc.v:165319.18-165319.90" + wire $reduce_or$libresoc.v:165319$10329_Y + attribute \src "libresoc.v:165320.17-165320.103" + wire $reduce_or$libresoc.v:165320$10330_Y + attribute \src "libresoc.v:165322.17-165322.109" + wire $reduce_or$libresoc.v:165322$10332_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165307$10317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:165307$10317_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165309$10319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:165309$10319_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165311$10321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:165311$10321_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:165312$10322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:165312$10322_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165314$10324 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:165314$10324_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165316$10326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:165316$10326_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165318$10328 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:165318$10328_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165321$10331 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:165321$10331_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165308$10318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:165308$10318_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165310$10320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:165310$10320_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165313$10323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:165313$10323_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165315$10325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:165315$10325_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165317$10327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:165317$10327_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:165319$10329 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:165319$10329_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165320$10330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:165320$10330_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165322$10332 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:165322$10332_Y + end + connect \$7 $not$libresoc.v:165307$10317_Y + connect \$12 $reduce_or$libresoc.v:165308$10318_Y + connect \$11 $not$libresoc.v:165309$10319_Y + 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"test_issuer.ti.core.dec_MUL.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick$184 + attribute \src "libresoc.v:165395.17-165395.91" + wire $not$libresoc.v:165395$10333_Y + attribute \src "libresoc.v:165397.18-165397.93" + wire $not$libresoc.v:165397$10335_Y + attribute \src "libresoc.v:165399.18-165399.93" + wire $not$libresoc.v:165399$10337_Y + attribute \src "libresoc.v:165400.17-165400.138" + wire width 8 $not$libresoc.v:165400$10338_Y + attribute \src "libresoc.v:165402.18-165402.93" + wire $not$libresoc.v:165402$10340_Y + attribute \src "libresoc.v:165404.18-165404.93" + wire $not$libresoc.v:165404$10342_Y + attribute \src "libresoc.v:165406.18-165406.93" + wire $not$libresoc.v:165406$10344_Y + attribute \src "libresoc.v:165409.17-165409.91" + wire $not$libresoc.v:165409$10347_Y + attribute \src "libresoc.v:165396.18-165396.116" + wire $reduce_or$libresoc.v:165396$10334_Y + attribute \src "libresoc.v:165398.18-165398.122" + wire $reduce_or$libresoc.v:165398$10336_Y + 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\$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165395$10333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:165395$10333_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165397$10335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:165397$10335_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165399$10337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:165399$10337_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:165400$10338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:165400$10338_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165402$10340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:165402$10340_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165404$10342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:165404$10342_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165406$10344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:165406$10344_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165409$10347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:165409$10347_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165396$10334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:165396$10334_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165398$10336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:165398$10336_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165401$10339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:165401$10339_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165403$10341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:165403$10341_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165405$10343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:165405$10343_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:165407$10345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:165407$10345_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165408$10346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:165408$10346_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165410$10348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:165410$10348_Y + end + connect \$7 $not$libresoc.v:165395$10333_Y + connect \$12 $reduce_or$libresoc.v:165396$10334_Y + connect \$11 $not$libresoc.v:165397$10335_Y + connect \$16 $reduce_or$libresoc.v:165398$10336_Y + connect \$15 $not$libresoc.v:165399$10337_Y + connect \$1 $not$libresoc.v:165400$10338_Y + connect \$20 $reduce_or$libresoc.v:165401$10339_Y + connect \$19 $not$libresoc.v:165402$10340_Y + connect \$24 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$not$libresoc.v:165485$10351_Y + attribute \src "libresoc.v:165487.18-165487.93" + wire $not$libresoc.v:165487$10353_Y + attribute \src "libresoc.v:165488.17-165488.138" + wire width 8 $not$libresoc.v:165488$10354_Y + attribute \src "libresoc.v:165490.18-165490.93" + wire $not$libresoc.v:165490$10356_Y + attribute \src "libresoc.v:165492.18-165492.93" + wire $not$libresoc.v:165492$10358_Y + attribute \src "libresoc.v:165494.18-165494.93" + wire $not$libresoc.v:165494$10360_Y + attribute \src "libresoc.v:165497.17-165497.91" + wire $not$libresoc.v:165497$10363_Y + attribute \src "libresoc.v:165484.18-165484.116" + wire $reduce_or$libresoc.v:165484$10350_Y + attribute \src "libresoc.v:165486.18-165486.122" + wire $reduce_or$libresoc.v:165486$10352_Y + attribute \src "libresoc.v:165489.18-165489.128" + wire $reduce_or$libresoc.v:165489$10355_Y + attribute \src "libresoc.v:165491.18-165491.134" + wire $reduce_or$libresoc.v:165491$10357_Y + attribute \src "libresoc.v:165493.18-165493.140" + wire $reduce_or$libresoc.v:165493$10359_Y + attribute \src "libresoc.v:165495.18-165495.90" + wire $reduce_or$libresoc.v:165495$10361_Y + attribute \src "libresoc.v:165496.17-165496.103" + wire $reduce_or$libresoc.v:165496$10362_Y + attribute \src "libresoc.v:165498.17-165498.109" + wire $reduce_or$libresoc.v:165498$10364_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165483$10349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:165483$10349_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165485$10351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:165485$10351_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165487$10353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:165487$10353_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:165488$10354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:165488$10354_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165490$10356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:165490$10356_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165492$10358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:165492$10358_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165494$10360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:165494$10360_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165497$10363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:165497$10363_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165484$10350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:165484$10350_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165486$10352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:165486$10352_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165489$10355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:165489$10355_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165491$10357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:165491$10357_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165493$10359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:165493$10359_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:165495$10361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:165495$10361_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165496$10362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:165496$10362_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165498$10364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:165498$10364_Y + end + connect \$7 $not$libresoc.v:165483$10349_Y + connect \$12 $reduce_or$libresoc.v:165484$10350_Y + connect \$11 $not$libresoc.v:165485$10351_Y + connect \$16 $reduce_or$libresoc.v:165486$10352_Y + connect \$15 $not$libresoc.v:165487$10353_Y + connect \$1 $not$libresoc.v:165488$10354_Y + connect \$20 $reduce_or$libresoc.v:165489$10355_Y + connect \$19 $not$libresoc.v:165490$10356_Y + connect \$24 $reduce_or$libresoc.v:165491$10357_Y + connect \$23 $not$libresoc.v:165492$10358_Y + connect \$28 $reduce_or$libresoc.v:165493$10359_Y + connect \$27 $not$libresoc.v:165494$10360_Y + connect \$31 $reduce_or$libresoc.v:165495$10361_Y + connect \$4 $reduce_or$libresoc.v:165496$10362_Y + connect \$3 $not$libresoc.v:165497$10363_Y + connect \$8 $reduce_or$libresoc.v:165498$10364_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:165514.1-165598.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick$192 + attribute \src "libresoc.v:165571.17-165571.91" + wire $not$libresoc.v:165571$10365_Y + attribute \src "libresoc.v:165573.18-165573.93" + wire $not$libresoc.v:165573$10367_Y + attribute \src "libresoc.v:165575.18-165575.93" + wire $not$libresoc.v:165575$10369_Y + attribute \src "libresoc.v:165576.17-165576.138" + wire width 8 $not$libresoc.v:165576$10370_Y + attribute \src "libresoc.v:165578.18-165578.93" + wire $not$libresoc.v:165578$10372_Y + attribute \src "libresoc.v:165580.18-165580.93" + wire $not$libresoc.v:165580$10374_Y + attribute \src "libresoc.v:165582.18-165582.93" + wire $not$libresoc.v:165582$10376_Y + attribute \src "libresoc.v:165585.17-165585.91" + wire $not$libresoc.v:165585$10379_Y + attribute \src "libresoc.v:165572.18-165572.116" + wire $reduce_or$libresoc.v:165572$10366_Y + attribute \src "libresoc.v:165574.18-165574.122" + wire $reduce_or$libresoc.v:165574$10368_Y + attribute \src "libresoc.v:165577.18-165577.128" + wire $reduce_or$libresoc.v:165577$10371_Y + attribute \src "libresoc.v:165579.18-165579.134" + wire $reduce_or$libresoc.v:165579$10373_Y + attribute \src "libresoc.v:165581.18-165581.140" + wire $reduce_or$libresoc.v:165581$10375_Y + attribute \src "libresoc.v:165583.18-165583.90" + wire $reduce_or$libresoc.v:165583$10377_Y + attribute \src "libresoc.v:165584.17-165584.103" + wire $reduce_or$libresoc.v:165584$10378_Y + attribute \src "libresoc.v:165586.17-165586.109" + wire $reduce_or$libresoc.v:165586$10380_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165571$10365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:165571$10365_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165573$10367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:165573$10367_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165575$10369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:165575$10369_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:165576$10370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:165576$10370_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165578$10372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:165578$10372_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165580$10374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:165580$10374_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165582$10376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:165582$10376_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165585$10379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:165585$10379_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165572$10366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:165572$10366_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165574$10368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:165574$10368_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165577$10371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:165577$10371_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165579$10373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:165579$10373_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165581$10375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:165581$10375_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:165583$10377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:165583$10377_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165584$10378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:165584$10378_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165586$10380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:165586$10380_Y + end + connect \$7 $not$libresoc.v:165571$10365_Y + connect \$12 $reduce_or$libresoc.v:165572$10366_Y + connect \$11 $not$libresoc.v:165573$10367_Y + connect \$16 $reduce_or$libresoc.v:165574$10368_Y + connect \$15 $not$libresoc.v:165575$10369_Y + connect \$1 $not$libresoc.v:165576$10370_Y + connect \$20 $reduce_or$libresoc.v:165577$10371_Y + connect \$19 $not$libresoc.v:165578$10372_Y + connect \$24 $reduce_or$libresoc.v:165579$10373_Y + connect \$23 $not$libresoc.v:165580$10374_Y + connect \$28 $reduce_or$libresoc.v:165581$10375_Y + connect \$27 $not$libresoc.v:165582$10376_Y + connect \$31 $reduce_or$libresoc.v:165583$10377_Y + connect \$4 $reduce_or$libresoc.v:165584$10378_Y + connect \$3 $not$libresoc.v:165585$10379_Y + connect \$8 $reduce_or$libresoc.v:165586$10380_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:165602.1-165686.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$194 + attribute \src "libresoc.v:165659.17-165659.91" + wire $not$libresoc.v:165659$10381_Y + attribute \src "libresoc.v:165661.18-165661.93" + wire $not$libresoc.v:165661$10383_Y + attribute \src "libresoc.v:165663.18-165663.93" + wire $not$libresoc.v:165663$10385_Y + attribute \src "libresoc.v:165664.17-165664.138" + wire width 8 $not$libresoc.v:165664$10386_Y + attribute \src "libresoc.v:165666.18-165666.93" + wire $not$libresoc.v:165666$10388_Y + attribute \src "libresoc.v:165668.18-165668.93" + wire $not$libresoc.v:165668$10390_Y + attribute \src "libresoc.v:165670.18-165670.93" + wire $not$libresoc.v:165670$10392_Y + attribute \src "libresoc.v:165673.17-165673.91" + wire $not$libresoc.v:165673$10395_Y + attribute \src "libresoc.v:165660.18-165660.116" + wire $reduce_or$libresoc.v:165660$10382_Y + attribute \src "libresoc.v:165662.18-165662.122" + wire $reduce_or$libresoc.v:165662$10384_Y + attribute \src "libresoc.v:165665.18-165665.128" + wire $reduce_or$libresoc.v:165665$10387_Y + attribute \src "libresoc.v:165667.18-165667.134" + wire $reduce_or$libresoc.v:165667$10389_Y + attribute \src "libresoc.v:165669.18-165669.140" + wire $reduce_or$libresoc.v:165669$10391_Y + attribute \src "libresoc.v:165671.18-165671.90" + wire $reduce_or$libresoc.v:165671$10393_Y + attribute \src "libresoc.v:165672.17-165672.103" + wire $reduce_or$libresoc.v:165672$10394_Y + attribute \src "libresoc.v:165674.17-165674.109" + wire $reduce_or$libresoc.v:165674$10396_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165659$10381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:165659$10381_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165661$10383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:165661$10383_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165663$10385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:165663$10385_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:165664$10386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:165664$10386_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165666$10388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:165666$10388_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165668$10390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:165668$10390_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165670$10392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:165670$10392_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165673$10395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:165673$10395_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165660$10382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:165660$10382_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165662$10384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:165662$10384_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165665$10387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:165665$10387_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165667$10389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:165667$10389_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165669$10391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:165669$10391_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:165671$10393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:165671$10393_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165672$10394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:165672$10394_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165674$10396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:165674$10396_Y + end + connect \$7 $not$libresoc.v:165659$10381_Y + connect \$12 $reduce_or$libresoc.v:165660$10382_Y + connect \$11 $not$libresoc.v:165661$10383_Y + connect \$16 $reduce_or$libresoc.v:165662$10384_Y + connect \$15 $not$libresoc.v:165663$10385_Y + connect \$1 $not$libresoc.v:165664$10386_Y + connect \$20 $reduce_or$libresoc.v:165665$10387_Y + connect \$19 $not$libresoc.v:165666$10388_Y + connect \$24 $reduce_or$libresoc.v:165667$10389_Y + connect \$23 $not$libresoc.v:165668$10390_Y + connect \$28 $reduce_or$libresoc.v:165669$10391_Y + connect \$27 $not$libresoc.v:165670$10392_Y + connect \$31 $reduce_or$libresoc.v:165671$10393_Y + connect \$4 $reduce_or$libresoc.v:165672$10394_Y + connect \$3 $not$libresoc.v:165673$10395_Y + connect \$8 $reduce_or$libresoc.v:165674$10396_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:165690.1-165774.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick$200 + attribute \src "libresoc.v:165747.17-165747.91" + wire $not$libresoc.v:165747$10397_Y + attribute \src "libresoc.v:165749.18-165749.93" + wire $not$libresoc.v:165749$10399_Y + attribute \src "libresoc.v:165751.18-165751.93" + wire $not$libresoc.v:165751$10401_Y + attribute \src "libresoc.v:165752.17-165752.138" + wire width 8 $not$libresoc.v:165752$10402_Y + attribute \src "libresoc.v:165754.18-165754.93" + wire $not$libresoc.v:165754$10404_Y + attribute \src "libresoc.v:165756.18-165756.93" + wire $not$libresoc.v:165756$10406_Y + attribute \src "libresoc.v:165758.18-165758.93" + wire $not$libresoc.v:165758$10408_Y + attribute \src "libresoc.v:165761.17-165761.91" + wire $not$libresoc.v:165761$10411_Y + attribute \src "libresoc.v:165748.18-165748.116" + wire $reduce_or$libresoc.v:165748$10398_Y + attribute \src "libresoc.v:165750.18-165750.122" + wire $reduce_or$libresoc.v:165750$10400_Y + attribute \src "libresoc.v:165753.18-165753.128" + wire $reduce_or$libresoc.v:165753$10403_Y + attribute \src "libresoc.v:165755.18-165755.134" + wire $reduce_or$libresoc.v:165755$10405_Y + attribute \src "libresoc.v:165757.18-165757.140" + wire $reduce_or$libresoc.v:165757$10407_Y + attribute \src "libresoc.v:165759.18-165759.90" + wire $reduce_or$libresoc.v:165759$10409_Y + attribute \src "libresoc.v:165760.17-165760.103" + wire $reduce_or$libresoc.v:165760$10410_Y + attribute \src "libresoc.v:165762.17-165762.109" + wire $reduce_or$libresoc.v:165762$10412_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165747$10397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:165747$10397_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165749$10399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:165749$10399_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165751$10401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:165751$10401_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:165752$10402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:165752$10402_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165754$10404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:165754$10404_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165756$10406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:165756$10406_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165758$10408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:165758$10408_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165761$10411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:165761$10411_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165748$10398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:165748$10398_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165750$10400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:165750$10400_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165753$10403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:165753$10403_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165755$10405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:165755$10405_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165757$10407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:165757$10407_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:165759$10409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:165759$10409_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165760$10410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:165760$10410_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165762$10412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:165762$10412_Y + end + connect \$7 $not$libresoc.v:165747$10397_Y + connect \$12 $reduce_or$libresoc.v:165748$10398_Y + connect \$11 $not$libresoc.v:165749$10399_Y + connect \$16 $reduce_or$libresoc.v:165750$10400_Y + connect \$15 $not$libresoc.v:165751$10401_Y + connect \$1 $not$libresoc.v:165752$10402_Y + connect \$20 $reduce_or$libresoc.v:165753$10403_Y + connect \$19 $not$libresoc.v:165754$10404_Y + connect \$24 $reduce_or$libresoc.v:165755$10405_Y + connect \$23 $not$libresoc.v:165756$10406_Y + connect \$28 $reduce_or$libresoc.v:165757$10407_Y + connect \$27 $not$libresoc.v:165758$10408_Y + connect \$31 $reduce_or$libresoc.v:165759$10409_Y + connect \$4 $reduce_or$libresoc.v:165760$10410_Y + connect \$3 $not$libresoc.v:165761$10411_Y + connect \$8 $reduce_or$libresoc.v:165762$10412_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:165778.1-165862.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$202 + attribute \src "libresoc.v:165835.17-165835.91" + wire $not$libresoc.v:165835$10413_Y + attribute \src "libresoc.v:165837.18-165837.93" + wire $not$libresoc.v:165837$10415_Y + attribute \src "libresoc.v:165839.18-165839.93" + wire $not$libresoc.v:165839$10417_Y + attribute \src "libresoc.v:165840.17-165840.138" + wire width 8 $not$libresoc.v:165840$10418_Y + attribute \src "libresoc.v:165842.18-165842.93" + wire $not$libresoc.v:165842$10420_Y + attribute \src "libresoc.v:165844.18-165844.93" + wire $not$libresoc.v:165844$10422_Y + attribute \src "libresoc.v:165846.18-165846.93" + wire $not$libresoc.v:165846$10424_Y + attribute \src "libresoc.v:165849.17-165849.91" + wire $not$libresoc.v:165849$10427_Y + attribute \src "libresoc.v:165836.18-165836.116" + wire $reduce_or$libresoc.v:165836$10414_Y + attribute \src "libresoc.v:165838.18-165838.122" + wire $reduce_or$libresoc.v:165838$10416_Y + attribute \src "libresoc.v:165841.18-165841.128" + wire $reduce_or$libresoc.v:165841$10419_Y + attribute \src "libresoc.v:165843.18-165843.134" + wire $reduce_or$libresoc.v:165843$10421_Y + attribute \src "libresoc.v:165845.18-165845.140" + wire $reduce_or$libresoc.v:165845$10423_Y + attribute \src "libresoc.v:165847.18-165847.90" + wire $reduce_or$libresoc.v:165847$10425_Y + attribute \src "libresoc.v:165848.17-165848.103" + wire $reduce_or$libresoc.v:165848$10426_Y + attribute \src "libresoc.v:165850.17-165850.109" + wire $reduce_or$libresoc.v:165850$10428_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165835$10413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:165835$10413_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165837$10415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:165837$10415_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165839$10417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:165839$10417_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:165840$10418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:165840$10418_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165842$10420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:165842$10420_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165844$10422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:165844$10422_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165846$10424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:165846$10424_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165849$10427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:165849$10427_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165836$10414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:165836$10414_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165838$10416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:165838$10416_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165841$10419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:165841$10419_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165843$10421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:165843$10421_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165845$10423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:165845$10423_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:165847$10425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:165847$10425_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165848$10426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:165848$10426_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165850$10428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:165850$10428_Y + end + connect \$7 $not$libresoc.v:165835$10413_Y + connect \$12 $reduce_or$libresoc.v:165836$10414_Y + connect \$11 $not$libresoc.v:165837$10415_Y + connect \$16 $reduce_or$libresoc.v:165838$10416_Y + connect \$15 $not$libresoc.v:165839$10417_Y + connect \$1 $not$libresoc.v:165840$10418_Y + connect \$20 $reduce_or$libresoc.v:165841$10419_Y + connect \$19 $not$libresoc.v:165842$10420_Y + connect \$24 $reduce_or$libresoc.v:165843$10421_Y + connect \$23 $not$libresoc.v:165844$10422_Y + connect \$28 $reduce_or$libresoc.v:165845$10423_Y + connect \$27 $not$libresoc.v:165846$10424_Y + connect \$31 $reduce_or$libresoc.v:165847$10425_Y + connect \$4 $reduce_or$libresoc.v:165848$10426_Y + connect \$3 $not$libresoc.v:165849$10427_Y + connect \$8 $reduce_or$libresoc.v:165850$10428_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:165866.1-165950.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick$209 + attribute \src "libresoc.v:165923.17-165923.91" + wire $not$libresoc.v:165923$10429_Y + attribute \src "libresoc.v:165925.18-165925.93" + wire $not$libresoc.v:165925$10431_Y + attribute \src "libresoc.v:165927.18-165927.93" + wire $not$libresoc.v:165927$10433_Y + attribute \src "libresoc.v:165928.17-165928.138" + wire width 8 $not$libresoc.v:165928$10434_Y + attribute \src "libresoc.v:165930.18-165930.93" + wire $not$libresoc.v:165930$10436_Y + attribute \src "libresoc.v:165932.18-165932.93" + wire $not$libresoc.v:165932$10438_Y + attribute \src "libresoc.v:165934.18-165934.93" + wire $not$libresoc.v:165934$10440_Y + attribute \src "libresoc.v:165937.17-165937.91" + wire $not$libresoc.v:165937$10443_Y + attribute \src "libresoc.v:165924.18-165924.116" + wire $reduce_or$libresoc.v:165924$10430_Y + attribute \src "libresoc.v:165926.18-165926.122" + wire $reduce_or$libresoc.v:165926$10432_Y + attribute \src "libresoc.v:165929.18-165929.128" + wire $reduce_or$libresoc.v:165929$10435_Y + attribute \src "libresoc.v:165931.18-165931.134" + wire $reduce_or$libresoc.v:165931$10437_Y + attribute \src "libresoc.v:165933.18-165933.140" + wire $reduce_or$libresoc.v:165933$10439_Y + attribute \src "libresoc.v:165935.18-165935.90" + wire $reduce_or$libresoc.v:165935$10441_Y + attribute \src "libresoc.v:165936.17-165936.103" + wire $reduce_or$libresoc.v:165936$10442_Y + attribute \src "libresoc.v:165938.17-165938.109" + wire $reduce_or$libresoc.v:165938$10444_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165923$10429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:165923$10429_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165925$10431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:165925$10431_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165927$10433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:165927$10433_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:165928$10434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:165928$10434_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165930$10436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:165930$10436_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165932$10438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:165932$10438_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165934$10440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:165934$10440_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:165937$10443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:165937$10443_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165924$10430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:165924$10430_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165926$10432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:165926$10432_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165929$10435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:165929$10435_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165931$10437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:165931$10437_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165933$10439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:165933$10439_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:165935$10441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:165935$10441_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165936$10442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:165936$10442_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:165938$10444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:165938$10444_Y + end + connect \$7 $not$libresoc.v:165923$10429_Y + connect \$12 $reduce_or$libresoc.v:165924$10430_Y + connect \$11 $not$libresoc.v:165925$10431_Y + connect \$16 $reduce_or$libresoc.v:165926$10432_Y + connect \$15 $not$libresoc.v:165927$10433_Y + connect \$1 $not$libresoc.v:165928$10434_Y + connect \$20 $reduce_or$libresoc.v:165929$10435_Y + connect \$19 $not$libresoc.v:165930$10436_Y + connect \$24 $reduce_or$libresoc.v:165931$10437_Y + connect \$23 $not$libresoc.v:165932$10438_Y + connect \$28 $reduce_or$libresoc.v:165933$10439_Y + connect \$27 $not$libresoc.v:165934$10440_Y + connect \$31 $reduce_or$libresoc.v:165935$10441_Y + connect \$4 $reduce_or$libresoc.v:165936$10442_Y + connect \$3 $not$libresoc.v:165937$10443_Y + connect \$8 $reduce_or$libresoc.v:165938$10444_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:165954.1-166038.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$211 + attribute \src "libresoc.v:166011.17-166011.91" + wire $not$libresoc.v:166011$10445_Y + attribute \src "libresoc.v:166013.18-166013.93" + wire $not$libresoc.v:166013$10447_Y + attribute \src "libresoc.v:166015.18-166015.93" + wire $not$libresoc.v:166015$10449_Y + attribute \src "libresoc.v:166016.17-166016.138" + wire width 8 $not$libresoc.v:166016$10450_Y + attribute \src "libresoc.v:166018.18-166018.93" + wire $not$libresoc.v:166018$10452_Y + attribute \src "libresoc.v:166020.18-166020.93" + wire $not$libresoc.v:166020$10454_Y + attribute \src "libresoc.v:166022.18-166022.93" + wire $not$libresoc.v:166022$10456_Y + attribute \src "libresoc.v:166025.17-166025.91" + wire $not$libresoc.v:166025$10459_Y + attribute \src "libresoc.v:166012.18-166012.116" + wire $reduce_or$libresoc.v:166012$10446_Y + attribute \src "libresoc.v:166014.18-166014.122" + wire $reduce_or$libresoc.v:166014$10448_Y + attribute \src "libresoc.v:166017.18-166017.128" + wire $reduce_or$libresoc.v:166017$10451_Y + attribute \src "libresoc.v:166019.18-166019.134" + wire $reduce_or$libresoc.v:166019$10453_Y + attribute \src "libresoc.v:166021.18-166021.140" + wire $reduce_or$libresoc.v:166021$10455_Y + attribute \src "libresoc.v:166023.18-166023.90" + wire $reduce_or$libresoc.v:166023$10457_Y + attribute \src "libresoc.v:166024.17-166024.103" + wire $reduce_or$libresoc.v:166024$10458_Y + attribute \src "libresoc.v:166026.17-166026.109" + wire $reduce_or$libresoc.v:166026$10460_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:166011$10445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:166011$10445_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:166013$10447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:166013$10447_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:166015$10449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:166015$10449_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:166016$10450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:166016$10450_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:166018$10452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:166018$10452_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:166020$10454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:166020$10454_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:166022$10456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:166022$10456_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:166025$10459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:166025$10459_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:166012$10446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:166012$10446_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:166014$10448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:166014$10448_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:166017$10451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:166017$10451_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:166019$10453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:166019$10453_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:166021$10455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:166021$10455_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:166023$10457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:166023$10457_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:166024$10458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:166024$10458_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:166026$10460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:166026$10460_Y + end + connect \$7 $not$libresoc.v:166011$10445_Y + connect \$12 $reduce_or$libresoc.v:166012$10446_Y + connect \$11 $not$libresoc.v:166013$10447_Y + connect \$16 $reduce_or$libresoc.v:166014$10448_Y + connect \$15 $not$libresoc.v:166015$10449_Y + connect \$1 $not$libresoc.v:166016$10450_Y + connect \$20 $reduce_or$libresoc.v:166017$10451_Y + connect \$19 $not$libresoc.v:166018$10452_Y + connect \$24 $reduce_or$libresoc.v:166019$10453_Y + connect \$23 $not$libresoc.v:166020$10454_Y + connect \$28 $reduce_or$libresoc.v:166021$10455_Y + connect \$27 $not$libresoc.v:166022$10456_Y + connect \$31 $reduce_or$libresoc.v:166023$10457_Y + connect \$4 $reduce_or$libresoc.v:166024$10458_Y + connect \$3 $not$libresoc.v:166025$10459_Y + connect \$8 $reduce_or$libresoc.v:166026$10460_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:166042.1-166072.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_a" +attribute \generator "nMigen" +module \rdpick_CR_cr_a + attribute \src "libresoc.v:166063.17-166063.89" + wire width 2 $not$libresoc.v:166063$10461_Y + attribute \src "libresoc.v:166065.17-166065.91" + wire $not$libresoc.v:166065$10463_Y + attribute \src "libresoc.v:166064.17-166064.103" + wire $reduce_or$libresoc.v:166064$10462_Y + attribute \src "libresoc.v:166066.17-166066.89" + wire $reduce_or$libresoc.v:166066$10464_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 2 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 2 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 2 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 2 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:166063$10461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \i + connect \Y $not$libresoc.v:166063$10461_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:166065$10463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:166065$10463_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:166064$10462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:166064$10462_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:166066$10464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:166066$10464_Y + end + connect \$1 $not$libresoc.v:166063$10461_Y + connect \$4 $reduce_or$libresoc.v:166064$10462_Y + connect \$3 $not$libresoc.v:166065$10463_Y + connect \$7 $reduce_or$libresoc.v:166066$10464_Y + connect \en_o \$7 + connect \o { \t1 \t0 } + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:166076.1-166097.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_b" +attribute \generator "nMigen" +module \rdpick_CR_cr_b + attribute \src "libresoc.v:166091.17-166091.89" + wire $not$libresoc.v:166091$10465_Y + attribute \src "libresoc.v:166092.17-166092.89" + wire $reduce_or$libresoc.v:166092$10466_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:166091$10465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $not$libresoc.v:166091$10465_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:166092$10466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:166092$10466_Y + end + connect \$1 $not$libresoc.v:166091$10465_Y + connect \$3 $reduce_or$libresoc.v:166092$10466_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "libresoc.v:166101.1-166122.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_c" +attribute \generator "nMigen" +module \rdpick_CR_cr_c + attribute \src "libresoc.v:166116.17-166116.89" + wire $not$libresoc.v:166116$10467_Y + attribute \src "libresoc.v:166117.17-166117.89" + wire $reduce_or$libresoc.v:166117$10468_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:166116$10467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $not$libresoc.v:166116$10467_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:166117$10468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:166117$10468_Y + end + connect \$1 $not$libresoc.v:166116$10467_Y + connect \$3 $reduce_or$libresoc.v:166117$10468_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "libresoc.v:166126.1-166147.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_full_cr" +attribute \generator "nMigen" +module \rdpick_CR_full_cr + attribute \src "libresoc.v:166141.17-166141.89" + wire $not$libresoc.v:166141$10469_Y + attribute \src "libresoc.v:166142.17-166142.89" + wire $reduce_or$libresoc.v:166142$10470_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:166141$10469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $not$libresoc.v:166141$10469_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:166142$10470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:166142$10470_Y + end + connect \$1 $not$libresoc.v:166141$10469_Y + connect \$3 $reduce_or$libresoc.v:166142$10470_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "libresoc.v:166151.1-166190.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_FAST_fast1" +attribute \generator "nMigen" +module \rdpick_FAST_fast1 + attribute \src "libresoc.v:166178.17-166178.91" + wire $not$libresoc.v:166178$10471_Y + attribute \src "libresoc.v:166180.17-166180.89" + wire width 3 $not$libresoc.v:166180$10473_Y + attribute \src "libresoc.v:166182.17-166182.91" + wire $not$libresoc.v:166182$10475_Y + attribute \src "libresoc.v:166179.18-166179.90" + wire $reduce_or$libresoc.v:166179$10472_Y + attribute \src "libresoc.v:166181.17-166181.103" + wire $reduce_or$libresoc.v:166181$10474_Y + attribute \src "libresoc.v:166183.17-166183.105" + wire $reduce_or$libresoc.v:166183$10476_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 3 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 3 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 3 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:166178$10471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:166178$10471_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:166180$10473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \i + connect \Y $not$libresoc.v:166180$10473_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:166182$10475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:166182$10475_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:166179$10472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:166179$10472_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:166181$10474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:166181$10474_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:166183$10476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:166183$10476_Y + end + connect \$7 $not$libresoc.v:166178$10471_Y + connect \$11 $reduce_or$libresoc.v:166179$10472_Y + connect \$1 $not$libresoc.v:166180$10473_Y + connect \$4 $reduce_or$libresoc.v:166181$10474_Y + connect \$3 $not$libresoc.v:166182$10475_Y + connect \$8 $reduce_or$libresoc.v:166183$10476_Y + connect \en_o \$11 + connect \o { \t2 \t1 \t0 } + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:166194.1-166224.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_FAST_fast2" +attribute \generator "nMigen" +module \rdpick_FAST_fast2 + attribute \src "libresoc.v:166215.17-166215.89" + wire width 2 $not$libresoc.v:166215$10477_Y + attribute \src "libresoc.v:166217.17-166217.91" + wire $not$libresoc.v:166217$10479_Y + attribute \src "libresoc.v:166216.17-166216.103" + wire $reduce_or$libresoc.v:166216$10478_Y + attribute \src "libresoc.v:166218.17-166218.89" + wire $reduce_or$libresoc.v:166218$10480_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 2 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 2 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 2 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 2 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:166215$10477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \i + connect \Y $not$libresoc.v:166215$10477_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:166217$10479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:166217$10479_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:166216$10478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:166216$10478_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:166218$10480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:166218$10480_Y + end + connect \$1 $not$libresoc.v:166215$10477_Y + connect \$4 $reduce_or$libresoc.v:166216$10478_Y + connect \$3 $not$libresoc.v:166217$10479_Y + connect \$7 $reduce_or$libresoc.v:166218$10480_Y + connect \en_o \$7 + connect \o { \t1 \t0 } + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:166228.1-166321.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_ra" +attribute \generator "nMigen" +module \rdpick_INT_ra + attribute \src "libresoc.v:166291.17-166291.91" + wire $not$libresoc.v:166291$10481_Y + attribute \src "libresoc.v:166293.18-166293.93" + wire $not$libresoc.v:166293$10483_Y + attribute \src "libresoc.v:166295.18-166295.93" + wire $not$libresoc.v:166295$10485_Y + attribute \src "libresoc.v:166296.17-166296.89" + wire width 9 $not$libresoc.v:166296$10486_Y + attribute \src "libresoc.v:166298.18-166298.93" + wire $not$libresoc.v:166298$10488_Y + attribute \src "libresoc.v:166300.18-166300.93" + wire $not$libresoc.v:166300$10490_Y + attribute \src "libresoc.v:166302.18-166302.93" + wire $not$libresoc.v:166302$10492_Y + attribute \src "libresoc.v:166304.18-166304.93" + wire $not$libresoc.v:166304$10494_Y + attribute \src "libresoc.v:166307.17-166307.91" + wire $not$libresoc.v:166307$10497_Y + attribute \src "libresoc.v:166292.18-166292.106" + wire $reduce_or$libresoc.v:166292$10482_Y + attribute \src "libresoc.v:166294.18-166294.106" + wire $reduce_or$libresoc.v:166294$10484_Y + attribute \src "libresoc.v:166297.18-166297.106" + wire $reduce_or$libresoc.v:166297$10487_Y + attribute \src "libresoc.v:166299.18-166299.106" + wire $reduce_or$libresoc.v:166299$10489_Y + attribute \src "libresoc.v:166301.18-166301.106" + wire $reduce_or$libresoc.v:166301$10491_Y + attribute \src "libresoc.v:166303.18-166303.106" + wire $reduce_or$libresoc.v:166303$10493_Y + attribute \src "libresoc.v:166305.18-166305.90" + wire $reduce_or$libresoc.v:166305$10495_Y + attribute \src "libresoc.v:166306.17-166306.103" + wire $reduce_or$libresoc.v:166306$10496_Y + attribute \src "libresoc.v:166308.17-166308.105" + wire $reduce_or$libresoc.v:166308$10498_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 9 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 9 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 9 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 9 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:166291$10481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:166291$10481_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:166293$10483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:166293$10483_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:166295$10485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:166295$10485_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:166296$10486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 9 + parameter \Y_WIDTH 9 + connect \A \i + connect \Y $not$libresoc.v:166296$10486_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:166298$10488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:166298$10488_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:166300$10490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:166300$10490_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:166302$10492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:166302$10492_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:166304$10494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$32 + connect \Y $not$libresoc.v:166304$10494_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:166307$10497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:166307$10497_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:166292$10482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] \ni [3] } + connect \Y $reduce_or$libresoc.v:166292$10482_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:166294$10484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3:0] \ni [4] } + connect \Y $reduce_or$libresoc.v:166294$10484_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:166297$10487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [4:0] \ni [5] } + connect \Y $reduce_or$libresoc.v:166297$10487_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:166299$10489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [5:0] \ni [6] } + connect \Y $reduce_or$libresoc.v:166299$10489_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:166301$10491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [6:0] \ni [7] } + connect \Y $reduce_or$libresoc.v:166301$10491_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:166303$10493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 9 + parameter \Y_WIDTH 1 + connect \A { \i [7:0] \ni [8] } + connect \Y $reduce_or$libresoc.v:166303$10493_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:166305$10495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 9 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:166305$10495_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:166306$10496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:166306$10496_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:166308$10498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:166308$10498_Y + end + connect \$7 $not$libresoc.v:166291$10481_Y + connect \$12 $reduce_or$libresoc.v:166292$10482_Y + connect \$11 $not$libresoc.v:166293$10483_Y + connect \$16 $reduce_or$libresoc.v:166294$10484_Y + connect \$15 $not$libresoc.v:166295$10485_Y + connect \$1 $not$libresoc.v:166296$10486_Y + connect \$20 $reduce_or$libresoc.v:166297$10487_Y + connect \$19 $not$libresoc.v:166298$10488_Y + connect \$24 $reduce_or$libresoc.v:166299$10489_Y + connect \$23 $not$libresoc.v:166300$10490_Y + connect \$28 $reduce_or$libresoc.v:166301$10491_Y + connect \$27 $not$libresoc.v:166302$10492_Y + connect \$32 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$not$libresoc.v:166386$10503_Y + attribute \src "libresoc.v:166387.17-166387.89" + wire width 8 $not$libresoc.v:166387$10504_Y + attribute \src "libresoc.v:166389.18-166389.93" + wire $not$libresoc.v:166389$10506_Y + attribute \src "libresoc.v:166391.18-166391.93" + wire $not$libresoc.v:166391$10508_Y + attribute \src "libresoc.v:166393.18-166393.93" + wire $not$libresoc.v:166393$10510_Y + attribute \src "libresoc.v:166396.17-166396.91" + wire $not$libresoc.v:166396$10513_Y + attribute \src "libresoc.v:166383.18-166383.106" + wire $reduce_or$libresoc.v:166383$10500_Y + attribute \src "libresoc.v:166385.18-166385.106" + wire $reduce_or$libresoc.v:166385$10502_Y + attribute \src "libresoc.v:166388.18-166388.106" + wire $reduce_or$libresoc.v:166388$10505_Y + attribute \src "libresoc.v:166390.18-166390.106" + wire $reduce_or$libresoc.v:166390$10507_Y + attribute \src "libresoc.v:166392.18-166392.106" + wire $reduce_or$libresoc.v:166392$10509_Y + attribute \src "libresoc.v:166394.18-166394.90" + wire $reduce_or$libresoc.v:166394$10511_Y + attribute \src "libresoc.v:166395.17-166395.103" + wire $reduce_or$libresoc.v:166395$10512_Y + attribute \src "libresoc.v:166397.17-166397.105" + wire $reduce_or$libresoc.v:166397$10514_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:166382$10499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:166382$10499_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:166384$10501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:166384$10501_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:166386$10503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:166386$10503_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:166387$10504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \i + connect \Y $not$libresoc.v:166387$10504_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:166389$10506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:166389$10506_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:166391$10508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:166391$10508_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:166393$10510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:166393$10510_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:166396$10513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:166396$10513_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:166383$10500 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] \ni [3] } + connect \Y $reduce_or$libresoc.v:166383$10500_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:166385$10502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3:0] \ni [4] } + connect \Y $reduce_or$libresoc.v:166385$10502_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:166388$10505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [4:0] \ni [5] } + connect \Y $reduce_or$libresoc.v:166388$10505_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:166390$10507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [5:0] \ni [6] } + connect \Y $reduce_or$libresoc.v:166390$10507_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:166392$10509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [6:0] \ni [7] } + connect \Y $reduce_or$libresoc.v:166392$10509_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:166394$10511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:166394$10511_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:166395$10512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:166395$10512_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:166397$10514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:166397$10514_Y + end + connect \$7 $not$libresoc.v:166382$10499_Y + connect \$12 $reduce_or$libresoc.v:166383$10500_Y + connect \$11 $not$libresoc.v:166384$10501_Y + connect \$16 $reduce_or$libresoc.v:166385$10502_Y + connect \$15 $not$libresoc.v:166386$10503_Y + connect \$1 $not$libresoc.v:166387$10504_Y + connect \$20 $reduce_or$libresoc.v:166388$10505_Y + connect \$19 $not$libresoc.v:166389$10506_Y + connect \$24 $reduce_or$libresoc.v:166390$10507_Y + connect \$23 $not$libresoc.v:166391$10508_Y + connect \$28 $reduce_or$libresoc.v:166392$10509_Y + connect \$27 $not$libresoc.v:166393$10510_Y + connect \$31 $reduce_or$libresoc.v:166394$10511_Y + connect \$4 $reduce_or$libresoc.v:166395$10512_Y + connect \$3 $not$libresoc.v:166396$10513_Y + connect \$8 $reduce_or$libresoc.v:166397$10514_Y + connect \en_o \$31 + connect \o { \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:166413.1-166443.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_rc" +attribute \generator "nMigen" +module \rdpick_INT_rc + attribute \src "libresoc.v:166434.17-166434.89" + wire width 2 $not$libresoc.v:166434$10515_Y + attribute \src "libresoc.v:166436.17-166436.91" + wire $not$libresoc.v:166436$10517_Y + attribute \src "libresoc.v:166435.17-166435.103" + wire $reduce_or$libresoc.v:166435$10516_Y + attribute \src "libresoc.v:166437.17-166437.89" + wire $reduce_or$libresoc.v:166437$10518_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 2 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 2 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 2 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 2 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:166434$10515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \i + connect \Y $not$libresoc.v:166434$10515_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:166436$10517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:166436$10517_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:166435$10516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:166435$10516_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:166437$10518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:166437$10518_Y + end + connect \$1 $not$libresoc.v:166434$10515_Y + connect \$4 $reduce_or$libresoc.v:166435$10516_Y + connect \$3 $not$libresoc.v:166436$10517_Y + connect \$7 $reduce_or$libresoc.v:166437$10518_Y + connect \en_o \$7 + connect \o { \t1 \t0 } + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:166447.1-166468.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_SPR_spr1" +attribute \generator "nMigen" +module \rdpick_SPR_spr1 + attribute \src "libresoc.v:166462.17-166462.89" + wire $not$libresoc.v:166462$10519_Y + attribute \src "libresoc.v:166463.17-166463.89" + wire $reduce_or$libresoc.v:166463$10520_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:166462$10519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $not$libresoc.v:166462$10519_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:166463$10520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:166463$10520_Y + end + connect \$1 $not$libresoc.v:166462$10519_Y + connect \$3 $reduce_or$libresoc.v:166463$10520_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "libresoc.v:166472.1-166511.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_ca" +attribute \generator "nMigen" +module \rdpick_XER_xer_ca + attribute \src "libresoc.v:166499.17-166499.91" + wire $not$libresoc.v:166499$10521_Y + attribute \src "libresoc.v:166501.17-166501.89" + wire width 3 $not$libresoc.v:166501$10523_Y + attribute \src "libresoc.v:166503.17-166503.91" + wire $not$libresoc.v:166503$10525_Y + attribute \src "libresoc.v:166500.18-166500.90" + wire $reduce_or$libresoc.v:166500$10522_Y + attribute \src "libresoc.v:166502.17-166502.103" + wire $reduce_or$libresoc.v:166502$10524_Y + attribute \src "libresoc.v:166504.17-166504.105" + wire $reduce_or$libresoc.v:166504$10526_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 3 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 3 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 3 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:166499$10521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:166499$10521_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:166501$10523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \i + connect \Y $not$libresoc.v:166501$10523_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:166503$10525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:166503$10525_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:166500$10522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:166500$10522_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:166502$10524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:166502$10524_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:166504$10526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:166504$10526_Y + end + connect \$7 $not$libresoc.v:166499$10521_Y + connect \$11 $reduce_or$libresoc.v:166500$10522_Y + connect \$1 $not$libresoc.v:166501$10523_Y + connect \$4 $reduce_or$libresoc.v:166502$10524_Y + connect \$3 $not$libresoc.v:166503$10525_Y + connect \$8 $reduce_or$libresoc.v:166504$10526_Y + connect \en_o \$11 + connect \o { \t2 \t1 \t0 } + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:166515.1-166536.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_ov" +attribute \generator "nMigen" +module \rdpick_XER_xer_ov + attribute \src "libresoc.v:166530.17-166530.89" + wire $not$libresoc.v:166530$10527_Y + attribute \src "libresoc.v:166531.17-166531.89" + wire $reduce_or$libresoc.v:166531$10528_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:166530$10527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $not$libresoc.v:166530$10527_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:166531$10528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:166531$10528_Y + end + connect \$1 $not$libresoc.v:166530$10527_Y + connect \$3 $reduce_or$libresoc.v:166531$10528_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "libresoc.v:166540.1-166606.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_so" +attribute \generator "nMigen" +module \rdpick_XER_xer_so + attribute \src "libresoc.v:166585.17-166585.91" + wire $not$libresoc.v:166585$10529_Y + attribute \src "libresoc.v:166587.18-166587.93" + wire $not$libresoc.v:166587$10531_Y + attribute \src "libresoc.v:166589.18-166589.93" + wire $not$libresoc.v:166589$10533_Y + attribute \src "libresoc.v:166590.17-166590.89" + wire width 6 $not$libresoc.v:166590$10534_Y + attribute \src "libresoc.v:166592.18-166592.93" + wire $not$libresoc.v:166592$10536_Y + attribute \src "libresoc.v:166595.17-166595.91" + wire $not$libresoc.v:166595$10539_Y + attribute \src "libresoc.v:166586.18-166586.106" + wire $reduce_or$libresoc.v:166586$10530_Y + attribute \src "libresoc.v:166588.18-166588.106" + wire $reduce_or$libresoc.v:166588$10532_Y + attribute \src "libresoc.v:166591.18-166591.106" + wire $reduce_or$libresoc.v:166591$10535_Y + attribute \src "libresoc.v:166593.18-166593.90" + wire $reduce_or$libresoc.v:166593$10537_Y + attribute \src "libresoc.v:166594.17-166594.103" + wire $reduce_or$libresoc.v:166594$10538_Y + attribute \src "libresoc.v:166596.17-166596.105" + wire $reduce_or$libresoc.v:166596$10540_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 6 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 6 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 6 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 6 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:166585$10529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:166585$10529_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:166587$10531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:166587$10531_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:166589$10533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:166589$10533_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:166590$10534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \i + connect \Y $not$libresoc.v:166590$10534_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:166592$10536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:166592$10536_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:166595$10539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:166595$10539_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:166586$10530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] \ni [3] } + connect \Y $reduce_or$libresoc.v:166586$10530_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:166588$10532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3:0] \ni [4] } + connect \Y $reduce_or$libresoc.v:166588$10532_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:166591$10535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [4:0] \ni [5] } + connect \Y $reduce_or$libresoc.v:166591$10535_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:166593$10537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:166593$10537_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:166594$10538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:166594$10538_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:166596$10540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:166596$10540_Y + end + connect \$7 $not$libresoc.v:166585$10529_Y + connect \$12 $reduce_or$libresoc.v:166586$10530_Y + connect \$11 $not$libresoc.v:166587$10531_Y + connect \$16 $reduce_or$libresoc.v:166588$10532_Y + connect \$15 $not$libresoc.v:166589$10533_Y + connect \$1 $not$libresoc.v:166590$10534_Y + connect \$20 $reduce_or$libresoc.v:166591$10535_Y + connect \$19 $not$libresoc.v:166592$10536_Y + connect \$23 $reduce_or$libresoc.v:166593$10537_Y + connect \$4 $reduce_or$libresoc.v:166594$10538_Y + connect \$3 $not$libresoc.v:166595$10539_Y + connect \$8 $reduce_or$libresoc.v:166596$10540_Y + connect \en_o \$23 + connect \o { \t5 \t4 \t3 \t2 \t1 \t0 } + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:166610.1-167081.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_0" +attribute \generator "nMigen" +module \reg_0 + attribute \src "libresoc.v:166611.7-166611.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:166941.3-166980.6" + wire width 4 $0\r0__data_o$next[3:0]$10596 + attribute \src "libresoc.v:166696.3-166697.37" + wire width 4 $0\r0__data_o[3:0] + attribute \src "libresoc.v:167011.3-167050.6" + wire width 4 $0\r20__data_o$next[3:0]$10610 + attribute \src "libresoc.v:166694.3-166695.39" + wire width 4 $0\r20__data_o[3:0] + attribute \src "libresoc.v:166774.3-166800.6" + wire width 4 $0\reg$next[3:0]$10562 + attribute \src "libresoc.v:166692.3-166693.25" + wire width 4 $0\reg[3:0] + attribute \src "libresoc.v:166704.3-166743.6" + wire width 4 $0\src10__data_o$next[3:0]$10553 + attribute \src "libresoc.v:166702.3-166703.43" + wire width 4 $0\src10__data_o[3:0] + attribute \src "libresoc.v:166801.3-166840.6" + wire width 4 $0\src20__data_o$next[3:0]$10568 + attribute \src "libresoc.v:166700.3-166701.43" + wire width 4 $0\src20__data_o[3:0] + attribute \src "libresoc.v:166871.3-166910.6" + wire width 4 $0\src30__data_o$next[3:0]$10582 + attribute \src "libresoc.v:166698.3-166699.43" + wire width 4 $0\src30__data_o[3:0] + attribute \src "libresoc.v:166981.3-167010.6" + wire $0\wr_detect$10[0:0]$10604 + attribute \src "libresoc.v:167051.3-167080.6" + wire $0\wr_detect$13[0:0]$10618 + attribute \src "libresoc.v:166841.3-166870.6" + wire $0\wr_detect$4[0:0]$10576 + attribute \src "libresoc.v:166911.3-166940.6" + wire $0\wr_detect$7[0:0]$10590 + attribute \src "libresoc.v:166744.3-166773.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:166941.3-166980.6" + wire width 4 $1\r0__data_o$next[3:0]$10597 + attribute \src "libresoc.v:166636.13-166636.30" + wire width 4 $1\r0__data_o[3:0] + attribute \src "libresoc.v:167011.3-167050.6" + wire width 4 $1\r20__data_o$next[3:0]$10611 + attribute \src "libresoc.v:166643.13-166643.31" + wire width 4 $1\r20__data_o[3:0] + attribute \src "libresoc.v:166774.3-166800.6" + wire width 4 $1\reg$next[3:0]$10563 + attribute \src "libresoc.v:166649.13-166649.25" + wire width 4 $1\reg[3:0] + attribute \src "libresoc.v:166704.3-166743.6" + wire width 4 $1\src10__data_o$next[3:0]$10554 + attribute \src "libresoc.v:166654.13-166654.33" + wire width 4 $1\src10__data_o[3:0] + attribute \src "libresoc.v:166801.3-166840.6" + wire width 4 $1\src20__data_o$next[3:0]$10569 + attribute \src "libresoc.v:166661.13-166661.33" + wire width 4 $1\src20__data_o[3:0] + attribute \src "libresoc.v:166871.3-166910.6" + wire width 4 $1\src30__data_o$next[3:0]$10583 + attribute \src "libresoc.v:166668.13-166668.33" + wire width 4 $1\src30__data_o[3:0] + attribute \src "libresoc.v:166981.3-167010.6" + wire $1\wr_detect$10[0:0]$10605 + attribute \src "libresoc.v:167051.3-167080.6" + wire $1\wr_detect$13[0:0]$10619 + attribute \src "libresoc.v:166841.3-166870.6" + wire $1\wr_detect$4[0:0]$10577 + attribute \src "libresoc.v:166911.3-166940.6" + wire $1\wr_detect$7[0:0]$10591 + attribute \src "libresoc.v:166744.3-166773.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:166941.3-166980.6" + wire width 4 $2\r0__data_o$next[3:0]$10598 + attribute \src "libresoc.v:167011.3-167050.6" + wire width 4 $2\r20__data_o$next[3:0]$10612 + attribute \src "libresoc.v:166774.3-166800.6" + wire width 4 $2\reg$next[3:0]$10564 + attribute \src "libresoc.v:166704.3-166743.6" + wire width 4 $2\src10__data_o$next[3:0]$10555 + attribute \src "libresoc.v:166801.3-166840.6" + wire width 4 $2\src20__data_o$next[3:0]$10570 + attribute \src "libresoc.v:166871.3-166910.6" + wire width 4 $2\src30__data_o$next[3:0]$10584 + attribute \src "libresoc.v:166981.3-167010.6" + wire $2\wr_detect$10[0:0]$10606 + attribute \src "libresoc.v:167051.3-167080.6" + wire $2\wr_detect$13[0:0]$10620 + attribute \src "libresoc.v:166841.3-166870.6" + wire $2\wr_detect$4[0:0]$10578 + attribute \src "libresoc.v:166911.3-166940.6" + wire $2\wr_detect$7[0:0]$10592 + attribute \src "libresoc.v:166744.3-166773.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:166941.3-166980.6" + wire width 4 $3\r0__data_o$next[3:0]$10599 + attribute \src "libresoc.v:167011.3-167050.6" + wire width 4 $3\r20__data_o$next[3:0]$10613 + attribute \src "libresoc.v:166774.3-166800.6" + wire width 4 $3\reg$next[3:0]$10565 + attribute \src "libresoc.v:166704.3-166743.6" + wire width 4 $3\src10__data_o$next[3:0]$10556 + attribute \src "libresoc.v:166801.3-166840.6" + wire width 4 $3\src20__data_o$next[3:0]$10571 + attribute \src "libresoc.v:166871.3-166910.6" + wire width 4 $3\src30__data_o$next[3:0]$10585 + attribute \src "libresoc.v:166981.3-167010.6" + wire $3\wr_detect$10[0:0]$10607 + attribute \src "libresoc.v:167051.3-167080.6" + wire $3\wr_detect$13[0:0]$10621 + attribute \src "libresoc.v:166841.3-166870.6" + wire $3\wr_detect$4[0:0]$10579 + attribute \src "libresoc.v:166911.3-166940.6" + wire $3\wr_detect$7[0:0]$10593 + attribute \src "libresoc.v:166744.3-166773.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:166941.3-166980.6" + wire width 4 $4\r0__data_o$next[3:0]$10600 + attribute \src "libresoc.v:167011.3-167050.6" + wire width 4 $4\r20__data_o$next[3:0]$10614 + attribute \src "libresoc.v:166774.3-166800.6" + wire width 4 $4\reg$next[3:0]$10566 + attribute \src "libresoc.v:166704.3-166743.6" + wire width 4 $4\src10__data_o$next[3:0]$10557 + attribute \src "libresoc.v:166801.3-166840.6" + wire width 4 $4\src20__data_o$next[3:0]$10572 + attribute \src "libresoc.v:166871.3-166910.6" + wire width 4 $4\src30__data_o$next[3:0]$10586 + attribute \src "libresoc.v:166981.3-167010.6" + wire $4\wr_detect$10[0:0]$10608 + attribute \src "libresoc.v:167051.3-167080.6" + wire $4\wr_detect$13[0:0]$10622 + attribute \src "libresoc.v:166841.3-166870.6" + wire $4\wr_detect$4[0:0]$10580 + attribute \src "libresoc.v:166911.3-166940.6" + wire $4\wr_detect$7[0:0]$10594 + attribute \src "libresoc.v:166744.3-166773.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:166941.3-166980.6" + wire width 4 $5\r0__data_o$next[3:0]$10601 + attribute \src "libresoc.v:167011.3-167050.6" + wire width 4 $5\r20__data_o$next[3:0]$10615 + attribute \src "libresoc.v:166704.3-166743.6" + wire width 4 $5\src10__data_o$next[3:0]$10558 + attribute \src "libresoc.v:166801.3-166840.6" + wire width 4 $5\src20__data_o$next[3:0]$10573 + attribute \src "libresoc.v:166871.3-166910.6" + wire width 4 $5\src30__data_o$next[3:0]$10587 + attribute \src "libresoc.v:166941.3-166980.6" + wire width 4 $6\r0__data_o$next[3:0]$10602 + attribute \src "libresoc.v:167011.3-167050.6" + wire width 4 $6\r20__data_o$next[3:0]$10616 + attribute \src "libresoc.v:166704.3-166743.6" + wire width 4 $6\src10__data_o$next[3:0]$10559 + attribute \src "libresoc.v:166801.3-166840.6" + wire width 4 $6\src20__data_o$next[3:0]$10574 + attribute \src "libresoc.v:166871.3-166910.6" + wire width 4 $6\src30__data_o$next[3:0]$10588 + attribute \src "libresoc.v:166687.17-166687.104" + wire $not$libresoc.v:166687$10541_Y + attribute \src "libresoc.v:166688.18-166688.105" + wire $not$libresoc.v:166688$10542_Y + attribute \src "libresoc.v:166689.17-166689.100" + wire $not$libresoc.v:166689$10543_Y + attribute \src "libresoc.v:166690.17-166690.103" + wire $not$libresoc.v:166690$10544_Y + attribute \src "libresoc.v:166691.17-166691.103" + wire $not$libresoc.v:166691$10545_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 9 \dest10__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \dest10__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 11 \dest20__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \dest20__wen + attribute \src "libresoc.v:166611.7-166611.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 12 \r0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r0__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 13 \r0__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 14 \r20__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r20__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 15 \r20__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 3 \src10__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src10__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \src10__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 5 \src20__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src20__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \src20__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 7 \src30__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src30__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \src30__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 16 \w0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 17 \w0__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:166687$10541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:166687$10541_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:166688$10542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$libresoc.v:166688$10542_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:166689$10543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:166689$10543_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:166690$10544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:166690$10544_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:166691$10545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:166691$10545_Y + end + attribute \src "libresoc.v:166611.7-166611.20" + process $proc$libresoc.v:166611$10623 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:166636.13-166636.30" + process $proc$libresoc.v:166636$10624 + assign { } { } + assign $1\r0__data_o[3:0] 4'0000 + sync always + sync init + update \r0__data_o $1\r0__data_o[3:0] + end + attribute \src "libresoc.v:166643.13-166643.31" + process $proc$libresoc.v:166643$10625 + assign { } { } + assign $1\r20__data_o[3:0] 4'0000 + sync always + sync init + update \r20__data_o $1\r20__data_o[3:0] + end + attribute \src "libresoc.v:166649.13-166649.25" + process $proc$libresoc.v:166649$10626 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "libresoc.v:166654.13-166654.33" + process $proc$libresoc.v:166654$10627 + assign { } { } + assign $1\src10__data_o[3:0] 4'0000 + sync always + sync init + update \src10__data_o $1\src10__data_o[3:0] + end + attribute \src "libresoc.v:166661.13-166661.33" + process $proc$libresoc.v:166661$10628 + assign { } { } + assign $1\src20__data_o[3:0] 4'0000 + sync always + sync init + update \src20__data_o $1\src20__data_o[3:0] + end + attribute \src "libresoc.v:166668.13-166668.33" + process $proc$libresoc.v:166668$10629 + assign { } { } + assign $1\src30__data_o[3:0] 4'0000 + sync always + sync init + update \src30__data_o $1\src30__data_o[3:0] + end + attribute \src "libresoc.v:166692.3-166693.25" + process $proc$libresoc.v:166692$10546 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "libresoc.v:166694.3-166695.39" + process $proc$libresoc.v:166694$10547 + assign { } { } + assign $0\r20__data_o[3:0] \r20__data_o$next + sync posedge \coresync_clk + update \r20__data_o $0\r20__data_o[3:0] + end + attribute \src "libresoc.v:166696.3-166697.37" + process $proc$libresoc.v:166696$10548 + assign { } { } + assign $0\r0__data_o[3:0] \r0__data_o$next + sync posedge \coresync_clk + update \r0__data_o $0\r0__data_o[3:0] + end + attribute \src "libresoc.v:166698.3-166699.43" + process $proc$libresoc.v:166698$10549 + assign { } { } + assign $0\src30__data_o[3:0] \src30__data_o$next + sync posedge \coresync_clk + update \src30__data_o $0\src30__data_o[3:0] + end + attribute \src "libresoc.v:166700.3-166701.43" + process $proc$libresoc.v:166700$10550 + assign { } { } + assign $0\src20__data_o[3:0] \src20__data_o$next + sync posedge \coresync_clk + update \src20__data_o $0\src20__data_o[3:0] + end + attribute \src "libresoc.v:166702.3-166703.43" + process $proc$libresoc.v:166702$10551 + assign { } { } + assign $0\src10__data_o[3:0] \src10__data_o$next + sync posedge \coresync_clk + update \src10__data_o $0\src10__data_o[3:0] + end + attribute \src "libresoc.v:166704.3-166743.6" + process $proc$libresoc.v:166704$10552 + assign { } { } + assign { } { } + assign { } { } + assign $0\src10__data_o$next[3:0]$10553 $6\src10__data_o$next[3:0]$10559 + attribute \src "libresoc.v:166705.5-166705.29" + switch \initial + attribute \src "libresoc.v:166705.9-166705.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src10__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src10__data_o$next[3:0]$10554 $5\src10__data_o$next[3:0]$10558 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src10__data_o$next[3:0]$10555 \dest10__data_i + case + assign $2\src10__data_o$next[3:0]$10555 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src10__data_o$next[3:0]$10556 \dest20__data_i + case + assign $3\src10__data_o$next[3:0]$10556 $2\src10__data_o$next[3:0]$10555 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src10__data_o$next[3:0]$10557 \w0__data_i + case + assign $4\src10__data_o$next[3:0]$10557 $3\src10__data_o$next[3:0]$10556 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src10__data_o$next[3:0]$10558 \reg + case + assign $5\src10__data_o$next[3:0]$10558 $4\src10__data_o$next[3:0]$10557 + end + case + assign $1\src10__data_o$next[3:0]$10554 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src10__data_o$next[3:0]$10559 4'0000 + case + assign $6\src10__data_o$next[3:0]$10559 $1\src10__data_o$next[3:0]$10554 + end + sync always + update \src10__data_o$next $0\src10__data_o$next[3:0]$10553 + end + attribute \src "libresoc.v:166744.3-166773.6" + process $proc$libresoc.v:166744$10560 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:166745.5-166745.29" + switch \initial + attribute \src "libresoc.v:166745.9-166745.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src10__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:166774.3-166800.6" + process $proc$libresoc.v:166774$10561 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$10562 $4\reg$next[3:0]$10566 + attribute \src "libresoc.v:166775.5-166775.29" + switch \initial + attribute \src "libresoc.v:166775.9-166775.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$10563 \dest10__data_i + case + assign $1\reg$next[3:0]$10563 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$10564 \dest20__data_i + case + assign $2\reg$next[3:0]$10564 $1\reg$next[3:0]$10563 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$10565 \w0__data_i + case + assign $3\reg$next[3:0]$10565 $2\reg$next[3:0]$10564 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$10566 4'0000 + case + assign $4\reg$next[3:0]$10566 $3\reg$next[3:0]$10565 + end + sync always + update \reg$next $0\reg$next[3:0]$10562 + end + attribute \src "libresoc.v:166801.3-166840.6" + process $proc$libresoc.v:166801$10567 + assign { } { } + assign { } { } + assign { } { } + assign $0\src20__data_o$next[3:0]$10568 $6\src20__data_o$next[3:0]$10574 + attribute \src "libresoc.v:166802.5-166802.29" + switch \initial + attribute \src "libresoc.v:166802.9-166802.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src20__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src20__data_o$next[3:0]$10569 $5\src20__data_o$next[3:0]$10573 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src20__data_o$next[3:0]$10570 \dest10__data_i + case + assign $2\src20__data_o$next[3:0]$10570 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src20__data_o$next[3:0]$10571 \dest20__data_i + case + assign $3\src20__data_o$next[3:0]$10571 $2\src20__data_o$next[3:0]$10570 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src20__data_o$next[3:0]$10572 \w0__data_i + case + assign $4\src20__data_o$next[3:0]$10572 $3\src20__data_o$next[3:0]$10571 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src20__data_o$next[3:0]$10573 \reg + case + assign $5\src20__data_o$next[3:0]$10573 $4\src20__data_o$next[3:0]$10572 + end + case + assign $1\src20__data_o$next[3:0]$10569 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src20__data_o$next[3:0]$10574 4'0000 + case + assign $6\src20__data_o$next[3:0]$10574 $1\src20__data_o$next[3:0]$10569 + end + sync always + update \src20__data_o$next $0\src20__data_o$next[3:0]$10568 + end + attribute \src "libresoc.v:166841.3-166870.6" + process $proc$libresoc.v:166841$10575 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$10576 $1\wr_detect$4[0:0]$10577 + attribute \src "libresoc.v:166842.5-166842.29" + switch \initial + attribute \src "libresoc.v:166842.9-166842.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src20__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$10577 $4\wr_detect$4[0:0]$10580 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$10578 1'1 + case + assign $2\wr_detect$4[0:0]$10578 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$10579 1'1 + case + assign $3\wr_detect$4[0:0]$10579 $2\wr_detect$4[0:0]$10578 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$10580 1'1 + case + assign $4\wr_detect$4[0:0]$10580 $3\wr_detect$4[0:0]$10579 + end + case + assign $1\wr_detect$4[0:0]$10577 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$10576 + end + attribute \src "libresoc.v:166871.3-166910.6" + process $proc$libresoc.v:166871$10581 + assign { } { } + assign { } { } + assign { } { } + assign $0\src30__data_o$next[3:0]$10582 $6\src30__data_o$next[3:0]$10588 + attribute \src "libresoc.v:166872.5-166872.29" + switch \initial + attribute \src "libresoc.v:166872.9-166872.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src30__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src30__data_o$next[3:0]$10583 $5\src30__data_o$next[3:0]$10587 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src30__data_o$next[3:0]$10584 \dest10__data_i + case + assign $2\src30__data_o$next[3:0]$10584 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src30__data_o$next[3:0]$10585 \dest20__data_i + case + assign $3\src30__data_o$next[3:0]$10585 $2\src30__data_o$next[3:0]$10584 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src30__data_o$next[3:0]$10586 \w0__data_i + case + assign $4\src30__data_o$next[3:0]$10586 $3\src30__data_o$next[3:0]$10585 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src30__data_o$next[3:0]$10587 \reg + case + assign $5\src30__data_o$next[3:0]$10587 $4\src30__data_o$next[3:0]$10586 + end + case + assign $1\src30__data_o$next[3:0]$10583 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src30__data_o$next[3:0]$10588 4'0000 + case + assign $6\src30__data_o$next[3:0]$10588 $1\src30__data_o$next[3:0]$10583 + end + sync always + update \src30__data_o$next $0\src30__data_o$next[3:0]$10582 + end + attribute \src "libresoc.v:166911.3-166940.6" + process $proc$libresoc.v:166911$10589 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$10590 $1\wr_detect$7[0:0]$10591 + attribute \src "libresoc.v:166912.5-166912.29" + switch \initial + attribute \src "libresoc.v:166912.9-166912.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src30__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$10591 $4\wr_detect$7[0:0]$10594 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$10592 1'1 + case + assign $2\wr_detect$7[0:0]$10592 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$10593 1'1 + case + assign $3\wr_detect$7[0:0]$10593 $2\wr_detect$7[0:0]$10592 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$10594 1'1 + case + assign $4\wr_detect$7[0:0]$10594 $3\wr_detect$7[0:0]$10593 + end + case + assign $1\wr_detect$7[0:0]$10591 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$10590 + end + attribute \src "libresoc.v:166941.3-166980.6" + process $proc$libresoc.v:166941$10595 + assign { } { } + assign { } { } + assign { } { } + assign $0\r0__data_o$next[3:0]$10596 $6\r0__data_o$next[3:0]$10602 + attribute \src "libresoc.v:166942.5-166942.29" + switch \initial + attribute \src "libresoc.v:166942.9-166942.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r0__data_o$next[3:0]$10597 $5\r0__data_o$next[3:0]$10601 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r0__data_o$next[3:0]$10598 \dest10__data_i + case + assign $2\r0__data_o$next[3:0]$10598 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r0__data_o$next[3:0]$10599 \dest20__data_i + case + assign $3\r0__data_o$next[3:0]$10599 $2\r0__data_o$next[3:0]$10598 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r0__data_o$next[3:0]$10600 \w0__data_i + case + assign $4\r0__data_o$next[3:0]$10600 $3\r0__data_o$next[3:0]$10599 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r0__data_o$next[3:0]$10601 \reg + case + assign $5\r0__data_o$next[3:0]$10601 $4\r0__data_o$next[3:0]$10600 + end + case + assign $1\r0__data_o$next[3:0]$10597 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r0__data_o$next[3:0]$10602 4'0000 + case + assign $6\r0__data_o$next[3:0]$10602 $1\r0__data_o$next[3:0]$10597 + end + sync always + update \r0__data_o$next $0\r0__data_o$next[3:0]$10596 + end + attribute \src "libresoc.v:166981.3-167010.6" + process $proc$libresoc.v:166981$10603 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$10604 $1\wr_detect$10[0:0]$10605 + attribute \src "libresoc.v:166982.5-166982.29" + switch \initial + attribute \src "libresoc.v:166982.9-166982.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$10605 $4\wr_detect$10[0:0]$10608 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$10606 1'1 + case + assign $2\wr_detect$10[0:0]$10606 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$10607 1'1 + case + assign $3\wr_detect$10[0:0]$10607 $2\wr_detect$10[0:0]$10606 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$10608 1'1 + case + assign $4\wr_detect$10[0:0]$10608 $3\wr_detect$10[0:0]$10607 + end + case + assign $1\wr_detect$10[0:0]$10605 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$10604 + end + attribute \src "libresoc.v:167011.3-167050.6" + process $proc$libresoc.v:167011$10609 + assign { } { } + assign { } { } + assign { } { } + assign $0\r20__data_o$next[3:0]$10610 $6\r20__data_o$next[3:0]$10616 + attribute \src "libresoc.v:167012.5-167012.29" + switch \initial + attribute \src "libresoc.v:167012.9-167012.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r20__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r20__data_o$next[3:0]$10611 $5\r20__data_o$next[3:0]$10615 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r20__data_o$next[3:0]$10612 \dest10__data_i + case + assign $2\r20__data_o$next[3:0]$10612 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r20__data_o$next[3:0]$10613 \dest20__data_i + case + assign $3\r20__data_o$next[3:0]$10613 $2\r20__data_o$next[3:0]$10612 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r20__data_o$next[3:0]$10614 \w0__data_i + case + assign $4\r20__data_o$next[3:0]$10614 $3\r20__data_o$next[3:0]$10613 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r20__data_o$next[3:0]$10615 \reg + case + assign $5\r20__data_o$next[3:0]$10615 $4\r20__data_o$next[3:0]$10614 + end + case + assign $1\r20__data_o$next[3:0]$10611 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r20__data_o$next[3:0]$10616 4'0000 + case + assign $6\r20__data_o$next[3:0]$10616 $1\r20__data_o$next[3:0]$10611 + end + sync always + update \r20__data_o$next $0\r20__data_o$next[3:0]$10610 + end + attribute \src "libresoc.v:167051.3-167080.6" + process $proc$libresoc.v:167051$10617 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$10618 $1\wr_detect$13[0:0]$10619 + attribute \src "libresoc.v:167052.5-167052.29" + switch \initial + attribute \src "libresoc.v:167052.9-167052.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r20__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$10619 $4\wr_detect$13[0:0]$10622 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$10620 1'1 + case + assign $2\wr_detect$13[0:0]$10620 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$10621 1'1 + case + assign $3\wr_detect$13[0:0]$10621 $2\wr_detect$13[0:0]$10620 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$10622 1'1 + case + assign $4\wr_detect$13[0:0]$10622 $3\wr_detect$13[0:0]$10621 + end + case + assign $1\wr_detect$13[0:0]$10619 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$10618 + end + connect \$9 $not$libresoc.v:166687$10541_Y + connect \$12 $not$libresoc.v:166688$10542_Y + connect \$1 $not$libresoc.v:166689$10543_Y + connect \$3 $not$libresoc.v:166690$10544_Y + connect \$6 $not$libresoc.v:166691$10545_Y +end +attribute \src "libresoc.v:167085.1-167530.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_0" +attribute \generator "nMigen" +module \reg_0$132 + attribute \src "libresoc.v:167086.7-167086.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:167415.3-167460.6" + wire width 2 $0\r0__data_o$next[1:0]$10682 + attribute \src "libresoc.v:167161.3-167162.37" + wire width 2 $0\r0__data_o[1:0] + attribute \src "libresoc.v:167497.3-167529.6" + wire width 2 $0\reg$next[1:0]$10698 + attribute \src "libresoc.v:167159.3-167160.25" + wire width 2 $0\reg[1:0] + attribute \src "libresoc.v:167169.3-167214.6" + wire width 2 $0\src10__data_o$next[1:0]$10640 + attribute \src "libresoc.v:167167.3-167168.43" + wire width 2 $0\src10__data_o[1:0] + attribute \src "libresoc.v:167251.3-167296.6" + wire width 2 $0\src20__data_o$next[1:0]$10650 + attribute \src "libresoc.v:167165.3-167166.43" + wire width 2 $0\src20__data_o[1:0] + attribute \src "libresoc.v:167333.3-167378.6" + wire width 2 $0\src30__data_o$next[1:0]$10666 + attribute \src "libresoc.v:167163.3-167164.43" + wire width 2 $0\src30__data_o[1:0] + attribute \src "libresoc.v:167461.3-167496.6" + wire $0\wr_detect$10[0:0]$10691 + attribute \src "libresoc.v:167297.3-167332.6" + wire $0\wr_detect$4[0:0]$10659 + attribute \src "libresoc.v:167379.3-167414.6" + wire $0\wr_detect$7[0:0]$10675 + attribute \src "libresoc.v:167215.3-167250.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:167415.3-167460.6" + wire width 2 $1\r0__data_o$next[1:0]$10683 + attribute \src "libresoc.v:167113.13-167113.30" + wire width 2 $1\r0__data_o[1:0] + attribute \src "libresoc.v:167497.3-167529.6" + wire width 2 $1\reg$next[1:0]$10699 + attribute \src "libresoc.v:167119.13-167119.25" + wire width 2 $1\reg[1:0] + attribute \src "libresoc.v:167169.3-167214.6" + wire width 2 $1\src10__data_o$next[1:0]$10641 + attribute \src "libresoc.v:167124.13-167124.33" + wire width 2 $1\src10__data_o[1:0] + attribute \src "libresoc.v:167251.3-167296.6" + wire width 2 $1\src20__data_o$next[1:0]$10651 + attribute \src "libresoc.v:167131.13-167131.33" + wire width 2 $1\src20__data_o[1:0] + attribute \src "libresoc.v:167333.3-167378.6" + wire width 2 $1\src30__data_o$next[1:0]$10667 + attribute \src "libresoc.v:167138.13-167138.33" + wire width 2 $1\src30__data_o[1:0] + attribute \src "libresoc.v:167461.3-167496.6" + wire $1\wr_detect$10[0:0]$10692 + attribute \src "libresoc.v:167297.3-167332.6" + wire $1\wr_detect$4[0:0]$10660 + attribute \src "libresoc.v:167379.3-167414.6" + wire $1\wr_detect$7[0:0]$10676 + attribute \src "libresoc.v:167215.3-167250.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:167415.3-167460.6" + wire width 2 $2\r0__data_o$next[1:0]$10684 + attribute \src "libresoc.v:167497.3-167529.6" + wire width 2 $2\reg$next[1:0]$10700 + attribute \src "libresoc.v:167169.3-167214.6" + wire width 2 $2\src10__data_o$next[1:0]$10642 + attribute \src "libresoc.v:167251.3-167296.6" + wire width 2 $2\src20__data_o$next[1:0]$10652 + attribute \src "libresoc.v:167333.3-167378.6" + wire width 2 $2\src30__data_o$next[1:0]$10668 + attribute \src "libresoc.v:167461.3-167496.6" + wire $2\wr_detect$10[0:0]$10693 + attribute \src "libresoc.v:167297.3-167332.6" + wire $2\wr_detect$4[0:0]$10661 + attribute \src "libresoc.v:167379.3-167414.6" + wire $2\wr_detect$7[0:0]$10677 + attribute \src "libresoc.v:167215.3-167250.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:167415.3-167460.6" + wire width 2 $3\r0__data_o$next[1:0]$10685 + attribute \src "libresoc.v:167497.3-167529.6" + wire width 2 $3\reg$next[1:0]$10701 + attribute \src "libresoc.v:167169.3-167214.6" + wire width 2 $3\src10__data_o$next[1:0]$10643 + attribute \src "libresoc.v:167251.3-167296.6" + wire width 2 $3\src20__data_o$next[1:0]$10653 + attribute \src "libresoc.v:167333.3-167378.6" + wire width 2 $3\src30__data_o$next[1:0]$10669 + attribute \src "libresoc.v:167461.3-167496.6" + wire $3\wr_detect$10[0:0]$10694 + attribute \src "libresoc.v:167297.3-167332.6" + wire $3\wr_detect$4[0:0]$10662 + attribute \src "libresoc.v:167379.3-167414.6" + wire $3\wr_detect$7[0:0]$10678 + attribute \src "libresoc.v:167215.3-167250.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:167415.3-167460.6" + wire width 2 $4\r0__data_o$next[1:0]$10686 + attribute \src "libresoc.v:167497.3-167529.6" + wire width 2 $4\reg$next[1:0]$10702 + attribute \src "libresoc.v:167169.3-167214.6" + wire width 2 $4\src10__data_o$next[1:0]$10644 + attribute \src "libresoc.v:167251.3-167296.6" + wire width 2 $4\src20__data_o$next[1:0]$10654 + attribute \src "libresoc.v:167333.3-167378.6" + wire width 2 $4\src30__data_o$next[1:0]$10670 + attribute \src "libresoc.v:167461.3-167496.6" + wire $4\wr_detect$10[0:0]$10695 + attribute \src "libresoc.v:167297.3-167332.6" + wire $4\wr_detect$4[0:0]$10663 + attribute \src "libresoc.v:167379.3-167414.6" + wire $4\wr_detect$7[0:0]$10679 + attribute \src "libresoc.v:167215.3-167250.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:167415.3-167460.6" + wire width 2 $5\r0__data_o$next[1:0]$10687 + attribute \src "libresoc.v:167497.3-167529.6" + wire width 2 $5\reg$next[1:0]$10703 + attribute \src "libresoc.v:167169.3-167214.6" + wire width 2 $5\src10__data_o$next[1:0]$10645 + attribute \src "libresoc.v:167251.3-167296.6" + wire width 2 $5\src20__data_o$next[1:0]$10655 + attribute \src "libresoc.v:167333.3-167378.6" + wire width 2 $5\src30__data_o$next[1:0]$10671 + attribute \src "libresoc.v:167461.3-167496.6" + wire $5\wr_detect$10[0:0]$10696 + attribute \src "libresoc.v:167297.3-167332.6" + wire $5\wr_detect$4[0:0]$10664 + attribute \src "libresoc.v:167379.3-167414.6" + wire $5\wr_detect$7[0:0]$10680 + attribute \src "libresoc.v:167215.3-167250.6" + wire $5\wr_detect[0:0] + attribute \src "libresoc.v:167415.3-167460.6" + wire width 2 $6\r0__data_o$next[1:0]$10688 + attribute \src "libresoc.v:167169.3-167214.6" + wire width 2 $6\src10__data_o$next[1:0]$10646 + attribute \src "libresoc.v:167251.3-167296.6" + wire width 2 $6\src20__data_o$next[1:0]$10656 + attribute \src "libresoc.v:167333.3-167378.6" + wire width 2 $6\src30__data_o$next[1:0]$10672 + attribute \src "libresoc.v:167415.3-167460.6" + wire width 2 $7\r0__data_o$next[1:0]$10689 + attribute \src "libresoc.v:167169.3-167214.6" + wire width 2 $7\src10__data_o$next[1:0]$10647 + attribute \src "libresoc.v:167251.3-167296.6" + wire width 2 $7\src20__data_o$next[1:0]$10657 + attribute \src "libresoc.v:167333.3-167378.6" + wire width 2 $7\src30__data_o$next[1:0]$10673 + attribute \src "libresoc.v:167155.17-167155.104" + wire $not$libresoc.v:167155$10630_Y + attribute \src "libresoc.v:167156.17-167156.100" + wire $not$libresoc.v:167156$10631_Y + attribute \src "libresoc.v:167157.17-167157.103" + wire $not$libresoc.v:167157$10632_Y + attribute \src "libresoc.v:167158.17-167158.103" + wire $not$libresoc.v:167158$10633_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 9 \dest10__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \dest10__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 11 \dest20__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \dest20__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 13 \dest30__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 12 \dest30__wen + attribute \src "libresoc.v:167086.7-167086.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 14 \r0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \r0__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 15 \r0__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 2 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 2 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 3 \src10__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \src10__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \src10__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 5 \src20__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \src20__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \src20__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 7 \src30__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \src30__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \src30__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 16 \w0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 17 \w0__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:167155$10630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:167155$10630_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:167156$10631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:167156$10631_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:167157$10632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:167157$10632_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:167158$10633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:167158$10633_Y + end + attribute \src "libresoc.v:167086.7-167086.20" + process $proc$libresoc.v:167086$10704 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:167113.13-167113.30" + process $proc$libresoc.v:167113$10705 + assign { } { } + assign $1\r0__data_o[1:0] 2'00 + sync always + sync init + update \r0__data_o $1\r0__data_o[1:0] + end + attribute \src "libresoc.v:167119.13-167119.25" + process $proc$libresoc.v:167119$10706 + assign { } { } + assign $1\reg[1:0] 2'00 + sync always + sync init + update \reg $1\reg[1:0] + end + attribute \src "libresoc.v:167124.13-167124.33" + process $proc$libresoc.v:167124$10707 + assign { } { } + assign $1\src10__data_o[1:0] 2'00 + sync always + sync init + update \src10__data_o $1\src10__data_o[1:0] + end + attribute \src "libresoc.v:167131.13-167131.33" + process $proc$libresoc.v:167131$10708 + assign { } { } + assign $1\src20__data_o[1:0] 2'00 + sync always + sync init + update \src20__data_o $1\src20__data_o[1:0] + end + attribute \src "libresoc.v:167138.13-167138.33" + process $proc$libresoc.v:167138$10709 + assign { } { } + assign $1\src30__data_o[1:0] 2'00 + sync always + sync init + update \src30__data_o $1\src30__data_o[1:0] + end + attribute \src "libresoc.v:167159.3-167160.25" + process $proc$libresoc.v:167159$10634 + assign { } { } + assign $0\reg[1:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[1:0] + end + attribute \src "libresoc.v:167161.3-167162.37" + process $proc$libresoc.v:167161$10635 + assign { } { } + assign $0\r0__data_o[1:0] \r0__data_o$next + sync posedge \coresync_clk + update \r0__data_o $0\r0__data_o[1:0] + end + attribute \src "libresoc.v:167163.3-167164.43" + process $proc$libresoc.v:167163$10636 + assign { } { } + assign $0\src30__data_o[1:0] \src30__data_o$next + sync posedge \coresync_clk + update \src30__data_o $0\src30__data_o[1:0] + end + attribute \src "libresoc.v:167165.3-167166.43" + process $proc$libresoc.v:167165$10637 + assign { } { } + assign $0\src20__data_o[1:0] \src20__data_o$next + sync posedge \coresync_clk + update \src20__data_o $0\src20__data_o[1:0] + end + attribute \src "libresoc.v:167167.3-167168.43" + process $proc$libresoc.v:167167$10638 + assign { } { } + assign $0\src10__data_o[1:0] \src10__data_o$next + sync posedge \coresync_clk + update \src10__data_o $0\src10__data_o[1:0] + end + attribute \src "libresoc.v:167169.3-167214.6" + process $proc$libresoc.v:167169$10639 + assign { } { } + assign { } { } + assign { } { } + assign $0\src10__data_o$next[1:0]$10640 $7\src10__data_o$next[1:0]$10647 + attribute \src "libresoc.v:167170.5-167170.29" + switch \initial + attribute \src "libresoc.v:167170.9-167170.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src10__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src10__data_o$next[1:0]$10641 $6\src10__data_o$next[1:0]$10646 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src10__data_o$next[1:0]$10642 \dest10__data_i + case + assign $2\src10__data_o$next[1:0]$10642 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src10__data_o$next[1:0]$10643 \dest20__data_i + case + assign $3\src10__data_o$next[1:0]$10643 $2\src10__data_o$next[1:0]$10642 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src10__data_o$next[1:0]$10644 \dest30__data_i + case + assign $4\src10__data_o$next[1:0]$10644 $3\src10__data_o$next[1:0]$10643 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src10__data_o$next[1:0]$10645 \w0__data_i + case + assign $5\src10__data_o$next[1:0]$10645 $4\src10__data_o$next[1:0]$10644 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src10__data_o$next[1:0]$10646 \reg + case + assign $6\src10__data_o$next[1:0]$10646 $5\src10__data_o$next[1:0]$10645 + end + case + assign $1\src10__data_o$next[1:0]$10641 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src10__data_o$next[1:0]$10647 2'00 + case + assign $7\src10__data_o$next[1:0]$10647 $1\src10__data_o$next[1:0]$10641 + end + sync always + update \src10__data_o$next $0\src10__data_o$next[1:0]$10640 + end + attribute \src "libresoc.v:167215.3-167250.6" + process $proc$libresoc.v:167215$10648 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:167216.5-167216.29" + switch \initial + attribute \src "libresoc.v:167216.9-167216.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src10__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $5\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect[0:0] 1'1 + case + assign $5\wr_detect[0:0] $4\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:167251.3-167296.6" + process $proc$libresoc.v:167251$10649 + assign { } { } + assign { } { } + assign { } { } + assign $0\src20__data_o$next[1:0]$10650 $7\src20__data_o$next[1:0]$10657 + attribute \src "libresoc.v:167252.5-167252.29" + switch \initial + attribute \src "libresoc.v:167252.9-167252.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src20__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src20__data_o$next[1:0]$10651 $6\src20__data_o$next[1:0]$10656 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src20__data_o$next[1:0]$10652 \dest10__data_i + case + assign $2\src20__data_o$next[1:0]$10652 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src20__data_o$next[1:0]$10653 \dest20__data_i + case + assign $3\src20__data_o$next[1:0]$10653 $2\src20__data_o$next[1:0]$10652 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src20__data_o$next[1:0]$10654 \dest30__data_i + case + assign $4\src20__data_o$next[1:0]$10654 $3\src20__data_o$next[1:0]$10653 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src20__data_o$next[1:0]$10655 \w0__data_i + case + assign $5\src20__data_o$next[1:0]$10655 $4\src20__data_o$next[1:0]$10654 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src20__data_o$next[1:0]$10656 \reg + case + assign $6\src20__data_o$next[1:0]$10656 $5\src20__data_o$next[1:0]$10655 + end + case + assign $1\src20__data_o$next[1:0]$10651 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src20__data_o$next[1:0]$10657 2'00 + case + assign $7\src20__data_o$next[1:0]$10657 $1\src20__data_o$next[1:0]$10651 + end + sync always + update \src20__data_o$next $0\src20__data_o$next[1:0]$10650 + end + attribute \src "libresoc.v:167297.3-167332.6" + process $proc$libresoc.v:167297$10658 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$10659 $1\wr_detect$4[0:0]$10660 + attribute \src "libresoc.v:167298.5-167298.29" + switch \initial + attribute \src "libresoc.v:167298.9-167298.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src20__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$10660 $5\wr_detect$4[0:0]$10664 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$10661 1'1 + case + assign $2\wr_detect$4[0:0]$10661 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$10662 1'1 + case + assign $3\wr_detect$4[0:0]$10662 $2\wr_detect$4[0:0]$10661 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$10663 1'1 + case + assign $4\wr_detect$4[0:0]$10663 $3\wr_detect$4[0:0]$10662 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$4[0:0]$10664 1'1 + case + assign $5\wr_detect$4[0:0]$10664 $4\wr_detect$4[0:0]$10663 + end + case + assign $1\wr_detect$4[0:0]$10660 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$10659 + end + attribute \src "libresoc.v:167333.3-167378.6" + process $proc$libresoc.v:167333$10665 + assign { } { } + assign { } { } + assign { } { } + assign $0\src30__data_o$next[1:0]$10666 $7\src30__data_o$next[1:0]$10673 + attribute \src "libresoc.v:167334.5-167334.29" + switch \initial + attribute \src "libresoc.v:167334.9-167334.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src30__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src30__data_o$next[1:0]$10667 $6\src30__data_o$next[1:0]$10672 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src30__data_o$next[1:0]$10668 \dest10__data_i + case + assign $2\src30__data_o$next[1:0]$10668 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src30__data_o$next[1:0]$10669 \dest20__data_i + case + assign $3\src30__data_o$next[1:0]$10669 $2\src30__data_o$next[1:0]$10668 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src30__data_o$next[1:0]$10670 \dest30__data_i + case + assign $4\src30__data_o$next[1:0]$10670 $3\src30__data_o$next[1:0]$10669 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src30__data_o$next[1:0]$10671 \w0__data_i + case + assign $5\src30__data_o$next[1:0]$10671 $4\src30__data_o$next[1:0]$10670 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src30__data_o$next[1:0]$10672 \reg + case + assign $6\src30__data_o$next[1:0]$10672 $5\src30__data_o$next[1:0]$10671 + end + case + assign $1\src30__data_o$next[1:0]$10667 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src30__data_o$next[1:0]$10673 2'00 + case + assign $7\src30__data_o$next[1:0]$10673 $1\src30__data_o$next[1:0]$10667 + end + sync always + update \src30__data_o$next $0\src30__data_o$next[1:0]$10666 + end + attribute \src "libresoc.v:167379.3-167414.6" + process $proc$libresoc.v:167379$10674 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$10675 $1\wr_detect$7[0:0]$10676 + attribute \src "libresoc.v:167380.5-167380.29" + switch \initial + attribute \src "libresoc.v:167380.9-167380.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src30__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$10676 $5\wr_detect$7[0:0]$10680 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$10677 1'1 + case + assign $2\wr_detect$7[0:0]$10677 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$10678 1'1 + case + assign $3\wr_detect$7[0:0]$10678 $2\wr_detect$7[0:0]$10677 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$10679 1'1 + case + assign $4\wr_detect$7[0:0]$10679 $3\wr_detect$7[0:0]$10678 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$7[0:0]$10680 1'1 + case + assign $5\wr_detect$7[0:0]$10680 $4\wr_detect$7[0:0]$10679 + end + case + assign $1\wr_detect$7[0:0]$10676 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$10675 + end + attribute \src "libresoc.v:167415.3-167460.6" + process $proc$libresoc.v:167415$10681 + assign { } { } + assign { } { } + assign { } { } + assign $0\r0__data_o$next[1:0]$10682 $7\r0__data_o$next[1:0]$10689 + attribute \src "libresoc.v:167416.5-167416.29" + switch \initial + attribute \src "libresoc.v:167416.9-167416.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r0__data_o$next[1:0]$10683 $6\r0__data_o$next[1:0]$10688 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r0__data_o$next[1:0]$10684 \dest10__data_i + case + assign $2\r0__data_o$next[1:0]$10684 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r0__data_o$next[1:0]$10685 \dest20__data_i + case + assign $3\r0__data_o$next[1:0]$10685 $2\r0__data_o$next[1:0]$10684 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r0__data_o$next[1:0]$10686 \dest30__data_i + case + assign $4\r0__data_o$next[1:0]$10686 $3\r0__data_o$next[1:0]$10685 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r0__data_o$next[1:0]$10687 \w0__data_i + case + assign $5\r0__data_o$next[1:0]$10687 $4\r0__data_o$next[1:0]$10686 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r0__data_o$next[1:0]$10688 \reg + case + assign $6\r0__data_o$next[1:0]$10688 $5\r0__data_o$next[1:0]$10687 + end + case + assign $1\r0__data_o$next[1:0]$10683 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\r0__data_o$next[1:0]$10689 2'00 + case + assign $7\r0__data_o$next[1:0]$10689 $1\r0__data_o$next[1:0]$10683 + end + sync always + update \r0__data_o$next $0\r0__data_o$next[1:0]$10682 + end + attribute \src "libresoc.v:167461.3-167496.6" + process $proc$libresoc.v:167461$10690 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$10691 $1\wr_detect$10[0:0]$10692 + attribute \src "libresoc.v:167462.5-167462.29" + switch \initial + attribute \src "libresoc.v:167462.9-167462.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$10692 $5\wr_detect$10[0:0]$10696 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$10693 1'1 + case + assign $2\wr_detect$10[0:0]$10693 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$10694 1'1 + case + assign $3\wr_detect$10[0:0]$10694 $2\wr_detect$10[0:0]$10693 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$10695 1'1 + case + assign $4\wr_detect$10[0:0]$10695 $3\wr_detect$10[0:0]$10694 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$10[0:0]$10696 1'1 + case + assign $5\wr_detect$10[0:0]$10696 $4\wr_detect$10[0:0]$10695 + end + case + assign $1\wr_detect$10[0:0]$10692 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$10691 + end + attribute \src "libresoc.v:167497.3-167529.6" + process $proc$libresoc.v:167497$10697 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[1:0]$10698 $5\reg$next[1:0]$10703 + attribute \src "libresoc.v:167498.5-167498.29" + switch \initial + attribute \src "libresoc.v:167498.9-167498.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[1:0]$10699 \dest10__data_i + case + assign $1\reg$next[1:0]$10699 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[1:0]$10700 \dest20__data_i + case + assign $2\reg$next[1:0]$10700 $1\reg$next[1:0]$10699 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest30__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[1:0]$10701 \dest30__data_i + case + assign $3\reg$next[1:0]$10701 $2\reg$next[1:0]$10700 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[1:0]$10702 \w0__data_i + case + assign $4\reg$next[1:0]$10702 $3\reg$next[1:0]$10701 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\reg$next[1:0]$10703 2'00 + case + assign $5\reg$next[1:0]$10703 $4\reg$next[1:0]$10702 + end + sync always + update \reg$next $0\reg$next[1:0]$10698 + end + connect \$9 $not$libresoc.v:167155$10630_Y + connect \$1 $not$libresoc.v:167156$10631_Y + connect \$3 $not$libresoc.v:167157$10632_Y + connect \$6 $not$libresoc.v:167158$10633_Y +end +attribute \src "libresoc.v:167534.1-167753.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_0" +attribute \generator "nMigen" +module \reg_0$135 + attribute \src "libresoc.v:167586.3-167625.6" + wire width 64 $0\cia0__data_o$next[63:0]$10716 + attribute \src "libresoc.v:167584.3-167585.41" + wire width 64 $0\cia0__data_o[63:0] + attribute \src "libresoc.v:167535.7-167535.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:167656.3-167695.6" + wire width 64 $0\msr0__data_o$next[63:0]$10725 + attribute \src "libresoc.v:167582.3-167583.41" + wire width 64 $0\msr0__data_o[63:0] + attribute \src "libresoc.v:167726.3-167752.6" + wire width 64 $0\reg$next[63:0]$10739 + attribute \src "libresoc.v:167580.3-167581.25" + wire width 64 $0\reg[63:0] + attribute \src "libresoc.v:167696.3-167725.6" + wire $0\wr_detect$4[0:0]$10733 + attribute \src "libresoc.v:167626.3-167655.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:167586.3-167625.6" + wire width 64 $1\cia0__data_o$next[63:0]$10717 + attribute \src "libresoc.v:167542.14-167542.49" + wire width 64 $1\cia0__data_o[63:0] + attribute \src "libresoc.v:167656.3-167695.6" + wire width 64 $1\msr0__data_o$next[63:0]$10726 + attribute \src "libresoc.v:167559.14-167559.49" + wire width 64 $1\msr0__data_o[63:0] + attribute \src "libresoc.v:167726.3-167752.6" + wire width 64 $1\reg$next[63:0]$10740 + attribute \src "libresoc.v:167571.14-167571.42" + wire width 64 $1\reg[63:0] + attribute \src "libresoc.v:167696.3-167725.6" + wire $1\wr_detect$4[0:0]$10734 + attribute \src "libresoc.v:167626.3-167655.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:167586.3-167625.6" + wire width 64 $2\cia0__data_o$next[63:0]$10718 + attribute \src "libresoc.v:167656.3-167695.6" + wire width 64 $2\msr0__data_o$next[63:0]$10727 + attribute \src "libresoc.v:167726.3-167752.6" + wire width 64 $2\reg$next[63:0]$10741 + attribute \src "libresoc.v:167696.3-167725.6" + wire $2\wr_detect$4[0:0]$10735 + attribute \src "libresoc.v:167626.3-167655.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:167586.3-167625.6" + wire width 64 $3\cia0__data_o$next[63:0]$10719 + attribute \src "libresoc.v:167656.3-167695.6" + wire width 64 $3\msr0__data_o$next[63:0]$10728 + attribute \src "libresoc.v:167726.3-167752.6" + wire width 64 $3\reg$next[63:0]$10742 + attribute \src "libresoc.v:167696.3-167725.6" + wire $3\wr_detect$4[0:0]$10736 + attribute \src "libresoc.v:167626.3-167655.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:167586.3-167625.6" + wire width 64 $4\cia0__data_o$next[63:0]$10720 + attribute \src "libresoc.v:167656.3-167695.6" + wire width 64 $4\msr0__data_o$next[63:0]$10729 + attribute \src "libresoc.v:167726.3-167752.6" + wire width 64 $4\reg$next[63:0]$10743 + attribute \src "libresoc.v:167696.3-167725.6" + wire $4\wr_detect$4[0:0]$10737 + attribute \src "libresoc.v:167626.3-167655.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:167586.3-167625.6" + wire width 64 $5\cia0__data_o$next[63:0]$10721 + attribute \src "libresoc.v:167656.3-167695.6" + wire width 64 $5\msr0__data_o$next[63:0]$10730 + attribute \src "libresoc.v:167586.3-167625.6" + wire width 64 $6\cia0__data_o$next[63:0]$10722 + attribute \src "libresoc.v:167656.3-167695.6" + wire width 64 $6\msr0__data_o$next[63:0]$10731 + attribute \src "libresoc.v:167578.17-167578.100" + wire $not$libresoc.v:167578$10710_Y + attribute \src "libresoc.v:167579.17-167579.103" + wire $not$libresoc.v:167579$10711_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 3 \cia0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \cia0__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \cia0__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 12 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 11 \d_wr10__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \d_wr10__wen + attribute \src "libresoc.v:167535.7-167535.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 9 \msr0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 5 \msr0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \msr0__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \msr0__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \msr0__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 7 \nia0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \nia0__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:167578$10710 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:167578$10710_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:167579$10711 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:167579$10711_Y + end + attribute \src "libresoc.v:167535.7-167535.20" + process $proc$libresoc.v:167535$10744 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:167542.14-167542.49" + process $proc$libresoc.v:167542$10745 + assign { } { } + assign $1\cia0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \cia0__data_o $1\cia0__data_o[63:0] + end + attribute \src "libresoc.v:167559.14-167559.49" + process $proc$libresoc.v:167559$10746 + assign { } { } + assign $1\msr0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \msr0__data_o $1\msr0__data_o[63:0] + end + attribute \src "libresoc.v:167571.14-167571.42" + process $proc$libresoc.v:167571$10747 + assign { } { } + assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \reg $1\reg[63:0] + end + attribute \src "libresoc.v:167580.3-167581.25" + process $proc$libresoc.v:167580$10712 + assign { } { } + assign $0\reg[63:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[63:0] + end + attribute \src "libresoc.v:167582.3-167583.41" + process $proc$libresoc.v:167582$10713 + assign { } { } + assign $0\msr0__data_o[63:0] \msr0__data_o$next + sync posedge \coresync_clk + update \msr0__data_o $0\msr0__data_o[63:0] + end + attribute \src "libresoc.v:167584.3-167585.41" + process $proc$libresoc.v:167584$10714 + assign { } { } + assign $0\cia0__data_o[63:0] \cia0__data_o$next + sync posedge \coresync_clk + update \cia0__data_o $0\cia0__data_o[63:0] + end + attribute \src "libresoc.v:167586.3-167625.6" + process $proc$libresoc.v:167586$10715 + assign { } { } + assign { } { } + assign { } { } + assign $0\cia0__data_o$next[63:0]$10716 $6\cia0__data_o$next[63:0]$10722 + attribute \src "libresoc.v:167587.5-167587.29" + switch \initial + attribute \src "libresoc.v:167587.9-167587.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\cia0__data_o$next[63:0]$10717 $5\cia0__data_o$next[63:0]$10721 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cia0__data_o$next[63:0]$10718 \nia0__data_i + case + assign $2\cia0__data_o$next[63:0]$10718 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cia0__data_o$next[63:0]$10719 \msr0__data_i + case + assign $3\cia0__data_o$next[63:0]$10719 $2\cia0__data_o$next[63:0]$10718 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cia0__data_o$next[63:0]$10720 \d_wr10__data_i + case + assign $4\cia0__data_o$next[63:0]$10720 $3\cia0__data_o$next[63:0]$10719 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\cia0__data_o$next[63:0]$10721 \reg + case + assign $5\cia0__data_o$next[63:0]$10721 $4\cia0__data_o$next[63:0]$10720 + end + case + assign $1\cia0__data_o$next[63:0]$10717 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\cia0__data_o$next[63:0]$10722 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $6\cia0__data_o$next[63:0]$10722 $1\cia0__data_o$next[63:0]$10717 + end + sync always + update \cia0__data_o$next $0\cia0__data_o$next[63:0]$10716 + end + attribute \src "libresoc.v:167626.3-167655.6" + process $proc$libresoc.v:167626$10723 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:167627.5-167627.29" + switch \initial + attribute \src "libresoc.v:167627.9-167627.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:167656.3-167695.6" + process $proc$libresoc.v:167656$10724 + assign { } { } + assign { } { } + assign { } { } + assign $0\msr0__data_o$next[63:0]$10725 $6\msr0__data_o$next[63:0]$10731 + attribute \src "libresoc.v:167657.5-167657.29" + switch \initial + attribute \src "libresoc.v:167657.9-167657.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \msr0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\msr0__data_o$next[63:0]$10726 $5\msr0__data_o$next[63:0]$10730 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr0__data_o$next[63:0]$10727 \nia0__data_i + case + assign $2\msr0__data_o$next[63:0]$10727 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\msr0__data_o$next[63:0]$10728 \msr0__data_i + case + assign $3\msr0__data_o$next[63:0]$10728 $2\msr0__data_o$next[63:0]$10727 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\msr0__data_o$next[63:0]$10729 \d_wr10__data_i + case + assign $4\msr0__data_o$next[63:0]$10729 $3\msr0__data_o$next[63:0]$10728 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\msr0__data_o$next[63:0]$10730 \reg + case + assign $5\msr0__data_o$next[63:0]$10730 $4\msr0__data_o$next[63:0]$10729 + end + case + assign $1\msr0__data_o$next[63:0]$10726 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\msr0__data_o$next[63:0]$10731 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $6\msr0__data_o$next[63:0]$10731 $1\msr0__data_o$next[63:0]$10726 + end + sync always + update \msr0__data_o$next $0\msr0__data_o$next[63:0]$10725 + end + attribute \src "libresoc.v:167696.3-167725.6" + process $proc$libresoc.v:167696$10732 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$10733 $1\wr_detect$4[0:0]$10734 + attribute \src "libresoc.v:167697.5-167697.29" + switch \initial + attribute \src "libresoc.v:167697.9-167697.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \msr0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$10734 $4\wr_detect$4[0:0]$10737 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$10735 1'1 + case + assign $2\wr_detect$4[0:0]$10735 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$10736 1'1 + case + assign $3\wr_detect$4[0:0]$10736 $2\wr_detect$4[0:0]$10735 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$10737 1'1 + case + assign $4\wr_detect$4[0:0]$10737 $3\wr_detect$4[0:0]$10736 + end + case + assign $1\wr_detect$4[0:0]$10734 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$10733 + end + attribute \src "libresoc.v:167726.3-167752.6" + process $proc$libresoc.v:167726$10738 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[63:0]$10739 $4\reg$next[63:0]$10743 + attribute \src "libresoc.v:167727.5-167727.29" + switch \initial + attribute \src "libresoc.v:167727.9-167727.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \nia0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[63:0]$10740 \nia0__data_i + case + assign $1\reg$next[63:0]$10740 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \msr0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[63:0]$10741 \msr0__data_i + case + assign $2\reg$next[63:0]$10741 $1\reg$next[63:0]$10740 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \d_wr10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[63:0]$10742 \d_wr10__data_i + case + assign $3\reg$next[63:0]$10742 $2\reg$next[63:0]$10741 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[63:0]$10743 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $4\reg$next[63:0]$10743 $3\reg$next[63:0]$10742 + end + sync always + update \reg$next $0\reg$next[63:0]$10739 + end + connect \$1 $not$libresoc.v:167578$10710_Y + connect \$3 $not$libresoc.v:167579$10711_Y +end +attribute \src "libresoc.v:167757.1-168228.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_1" +attribute \generator "nMigen" +module \reg_1 + attribute \src "libresoc.v:167758.7-167758.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:168088.3-168127.6" + wire width 4 $0\r1__data_o$next[3:0]$10803 + attribute \src "libresoc.v:167843.3-167844.37" + wire width 4 $0\r1__data_o[3:0] + attribute \src "libresoc.v:168158.3-168197.6" + wire width 4 $0\r21__data_o$next[3:0]$10817 + attribute \src "libresoc.v:167841.3-167842.39" + wire width 4 $0\r21__data_o[3:0] + attribute \src "libresoc.v:167921.3-167947.6" + wire width 4 $0\reg$next[3:0]$10769 + attribute \src "libresoc.v:167839.3-167840.25" + wire width 4 $0\reg[3:0] + attribute \src "libresoc.v:167851.3-167890.6" + wire width 4 $0\src11__data_o$next[3:0]$10760 + attribute \src "libresoc.v:167849.3-167850.43" + wire width 4 $0\src11__data_o[3:0] + attribute \src "libresoc.v:167948.3-167987.6" + wire width 4 $0\src21__data_o$next[3:0]$10775 + attribute \src "libresoc.v:167847.3-167848.43" + wire width 4 $0\src21__data_o[3:0] + attribute \src "libresoc.v:168018.3-168057.6" + wire width 4 $0\src31__data_o$next[3:0]$10789 + attribute \src "libresoc.v:167845.3-167846.43" + wire width 4 $0\src31__data_o[3:0] + attribute \src "libresoc.v:168128.3-168157.6" + wire $0\wr_detect$10[0:0]$10811 + attribute \src "libresoc.v:168198.3-168227.6" + wire $0\wr_detect$13[0:0]$10825 + attribute \src "libresoc.v:167988.3-168017.6" + wire $0\wr_detect$4[0:0]$10783 + attribute \src "libresoc.v:168058.3-168087.6" + wire $0\wr_detect$7[0:0]$10797 + attribute \src "libresoc.v:167891.3-167920.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:168088.3-168127.6" + wire width 4 $1\r1__data_o$next[3:0]$10804 + attribute \src "libresoc.v:167783.13-167783.30" + wire width 4 $1\r1__data_o[3:0] + attribute \src "libresoc.v:168158.3-168197.6" + wire width 4 $1\r21__data_o$next[3:0]$10818 + attribute \src "libresoc.v:167790.13-167790.31" + wire width 4 $1\r21__data_o[3:0] + attribute \src "libresoc.v:167921.3-167947.6" + wire width 4 $1\reg$next[3:0]$10770 + attribute \src "libresoc.v:167796.13-167796.25" + wire width 4 $1\reg[3:0] + attribute \src "libresoc.v:167851.3-167890.6" + wire width 4 $1\src11__data_o$next[3:0]$10761 + attribute \src "libresoc.v:167801.13-167801.33" + wire width 4 $1\src11__data_o[3:0] + attribute \src "libresoc.v:167948.3-167987.6" + wire width 4 $1\src21__data_o$next[3:0]$10776 + attribute \src "libresoc.v:167808.13-167808.33" + wire width 4 $1\src21__data_o[3:0] + attribute \src "libresoc.v:168018.3-168057.6" + wire width 4 $1\src31__data_o$next[3:0]$10790 + attribute \src "libresoc.v:167815.13-167815.33" + wire width 4 $1\src31__data_o[3:0] + attribute \src "libresoc.v:168128.3-168157.6" + wire $1\wr_detect$10[0:0]$10812 + attribute \src "libresoc.v:168198.3-168227.6" + wire $1\wr_detect$13[0:0]$10826 + attribute \src "libresoc.v:167988.3-168017.6" + wire $1\wr_detect$4[0:0]$10784 + attribute \src "libresoc.v:168058.3-168087.6" + wire $1\wr_detect$7[0:0]$10798 + attribute \src "libresoc.v:167891.3-167920.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:168088.3-168127.6" + wire width 4 $2\r1__data_o$next[3:0]$10805 + attribute \src "libresoc.v:168158.3-168197.6" + wire width 4 $2\r21__data_o$next[3:0]$10819 + attribute \src "libresoc.v:167921.3-167947.6" + wire width 4 $2\reg$next[3:0]$10771 + attribute \src "libresoc.v:167851.3-167890.6" + wire width 4 $2\src11__data_o$next[3:0]$10762 + attribute \src "libresoc.v:167948.3-167987.6" + wire width 4 $2\src21__data_o$next[3:0]$10777 + attribute \src "libresoc.v:168018.3-168057.6" + wire width 4 $2\src31__data_o$next[3:0]$10791 + attribute \src "libresoc.v:168128.3-168157.6" + wire $2\wr_detect$10[0:0]$10813 + attribute \src "libresoc.v:168198.3-168227.6" + wire $2\wr_detect$13[0:0]$10827 + attribute \src "libresoc.v:167988.3-168017.6" + wire $2\wr_detect$4[0:0]$10785 + attribute \src "libresoc.v:168058.3-168087.6" + wire $2\wr_detect$7[0:0]$10799 + attribute \src "libresoc.v:167891.3-167920.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:168088.3-168127.6" + wire width 4 $3\r1__data_o$next[3:0]$10806 + attribute \src "libresoc.v:168158.3-168197.6" + wire width 4 $3\r21__data_o$next[3:0]$10820 + attribute \src "libresoc.v:167921.3-167947.6" + wire width 4 $3\reg$next[3:0]$10772 + attribute \src "libresoc.v:167851.3-167890.6" + wire width 4 $3\src11__data_o$next[3:0]$10763 + attribute \src "libresoc.v:167948.3-167987.6" + wire width 4 $3\src21__data_o$next[3:0]$10778 + attribute \src "libresoc.v:168018.3-168057.6" + wire width 4 $3\src31__data_o$next[3:0]$10792 + attribute \src "libresoc.v:168128.3-168157.6" + wire $3\wr_detect$10[0:0]$10814 + attribute \src "libresoc.v:168198.3-168227.6" + wire $3\wr_detect$13[0:0]$10828 + attribute \src "libresoc.v:167988.3-168017.6" + wire $3\wr_detect$4[0:0]$10786 + attribute \src "libresoc.v:168058.3-168087.6" + wire $3\wr_detect$7[0:0]$10800 + attribute \src "libresoc.v:167891.3-167920.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:168088.3-168127.6" + wire width 4 $4\r1__data_o$next[3:0]$10807 + attribute \src "libresoc.v:168158.3-168197.6" + wire width 4 $4\r21__data_o$next[3:0]$10821 + attribute \src "libresoc.v:167921.3-167947.6" + wire width 4 $4\reg$next[3:0]$10773 + attribute \src "libresoc.v:167851.3-167890.6" + wire width 4 $4\src11__data_o$next[3:0]$10764 + attribute \src "libresoc.v:167948.3-167987.6" + wire width 4 $4\src21__data_o$next[3:0]$10779 + attribute \src "libresoc.v:168018.3-168057.6" + wire width 4 $4\src31__data_o$next[3:0]$10793 + attribute \src "libresoc.v:168128.3-168157.6" + wire $4\wr_detect$10[0:0]$10815 + attribute \src "libresoc.v:168198.3-168227.6" + wire $4\wr_detect$13[0:0]$10829 + attribute \src "libresoc.v:167988.3-168017.6" + wire $4\wr_detect$4[0:0]$10787 + attribute \src "libresoc.v:168058.3-168087.6" + wire $4\wr_detect$7[0:0]$10801 + attribute \src "libresoc.v:167891.3-167920.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:168088.3-168127.6" + wire width 4 $5\r1__data_o$next[3:0]$10808 + attribute \src "libresoc.v:168158.3-168197.6" + wire width 4 $5\r21__data_o$next[3:0]$10822 + attribute \src "libresoc.v:167851.3-167890.6" + wire width 4 $5\src11__data_o$next[3:0]$10765 + attribute \src "libresoc.v:167948.3-167987.6" + wire width 4 $5\src21__data_o$next[3:0]$10780 + attribute \src "libresoc.v:168018.3-168057.6" + wire width 4 $5\src31__data_o$next[3:0]$10794 + attribute \src "libresoc.v:168088.3-168127.6" + wire width 4 $6\r1__data_o$next[3:0]$10809 + attribute \src "libresoc.v:168158.3-168197.6" + wire width 4 $6\r21__data_o$next[3:0]$10823 + attribute \src "libresoc.v:167851.3-167890.6" + wire width 4 $6\src11__data_o$next[3:0]$10766 + attribute \src "libresoc.v:167948.3-167987.6" + wire width 4 $6\src21__data_o$next[3:0]$10781 + attribute \src "libresoc.v:168018.3-168057.6" + wire width 4 $6\src31__data_o$next[3:0]$10795 + attribute \src "libresoc.v:167834.17-167834.104" + wire $not$libresoc.v:167834$10748_Y + attribute \src "libresoc.v:167835.18-167835.105" + wire $not$libresoc.v:167835$10749_Y + attribute \src "libresoc.v:167836.17-167836.100" + wire $not$libresoc.v:167836$10750_Y + attribute \src "libresoc.v:167837.17-167837.103" + wire $not$libresoc.v:167837$10751_Y + attribute \src "libresoc.v:167838.17-167838.103" + wire $not$libresoc.v:167838$10752_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 9 \dest11__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \dest11__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 11 \dest21__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \dest21__wen + attribute \src "libresoc.v:167758.7-167758.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 12 \r1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r1__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 13 \r1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 14 \r21__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r21__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 15 \r21__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 3 \src11__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src11__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \src11__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 5 \src21__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src21__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \src21__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 7 \src31__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src31__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \src31__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 16 \w1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 17 \w1__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:167834$10748 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:167834$10748_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:167835$10749 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$libresoc.v:167835$10749_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:167836$10750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:167836$10750_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:167837$10751 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:167837$10751_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:167838$10752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:167838$10752_Y + end + attribute \src "libresoc.v:167758.7-167758.20" + process $proc$libresoc.v:167758$10830 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:167783.13-167783.30" + process $proc$libresoc.v:167783$10831 + assign { } { } + assign $1\r1__data_o[3:0] 4'0000 + sync always + sync init + update \r1__data_o $1\r1__data_o[3:0] + end + attribute \src "libresoc.v:167790.13-167790.31" + process $proc$libresoc.v:167790$10832 + assign { } { } + assign $1\r21__data_o[3:0] 4'0000 + sync always + sync init + update \r21__data_o $1\r21__data_o[3:0] + end + attribute \src "libresoc.v:167796.13-167796.25" + process $proc$libresoc.v:167796$10833 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "libresoc.v:167801.13-167801.33" + process $proc$libresoc.v:167801$10834 + assign { } { } + assign $1\src11__data_o[3:0] 4'0000 + sync always + sync init + update \src11__data_o $1\src11__data_o[3:0] + end + attribute \src "libresoc.v:167808.13-167808.33" + process $proc$libresoc.v:167808$10835 + assign { } { } + assign $1\src21__data_o[3:0] 4'0000 + sync always + sync init + update \src21__data_o $1\src21__data_o[3:0] + end + attribute \src "libresoc.v:167815.13-167815.33" + process $proc$libresoc.v:167815$10836 + assign { } { } + assign $1\src31__data_o[3:0] 4'0000 + sync always + sync init + update \src31__data_o $1\src31__data_o[3:0] + end + attribute \src "libresoc.v:167839.3-167840.25" + process $proc$libresoc.v:167839$10753 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "libresoc.v:167841.3-167842.39" + process $proc$libresoc.v:167841$10754 + assign { } { } + assign $0\r21__data_o[3:0] \r21__data_o$next + sync posedge \coresync_clk + update \r21__data_o $0\r21__data_o[3:0] + end + attribute \src "libresoc.v:167843.3-167844.37" + process $proc$libresoc.v:167843$10755 + assign { } { } + assign $0\r1__data_o[3:0] \r1__data_o$next + sync posedge \coresync_clk + update \r1__data_o $0\r1__data_o[3:0] + end + attribute \src "libresoc.v:167845.3-167846.43" + process $proc$libresoc.v:167845$10756 + assign { } { } + assign $0\src31__data_o[3:0] \src31__data_o$next + sync posedge \coresync_clk + update \src31__data_o $0\src31__data_o[3:0] + end + attribute \src "libresoc.v:167847.3-167848.43" + process $proc$libresoc.v:167847$10757 + assign { } { } + assign $0\src21__data_o[3:0] \src21__data_o$next + sync posedge \coresync_clk + update \src21__data_o $0\src21__data_o[3:0] + end + attribute \src "libresoc.v:167849.3-167850.43" + process $proc$libresoc.v:167849$10758 + assign { } { } + assign $0\src11__data_o[3:0] \src11__data_o$next + sync posedge \coresync_clk + update \src11__data_o $0\src11__data_o[3:0] + end + attribute \src "libresoc.v:167851.3-167890.6" + process $proc$libresoc.v:167851$10759 + assign { } { } + assign { } { } + assign { } { } + assign $0\src11__data_o$next[3:0]$10760 $6\src11__data_o$next[3:0]$10766 + attribute \src "libresoc.v:167852.5-167852.29" + switch \initial + attribute \src "libresoc.v:167852.9-167852.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src11__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src11__data_o$next[3:0]$10761 $5\src11__data_o$next[3:0]$10765 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src11__data_o$next[3:0]$10762 \dest11__data_i + case + assign $2\src11__data_o$next[3:0]$10762 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src11__data_o$next[3:0]$10763 \dest21__data_i + case + assign $3\src11__data_o$next[3:0]$10763 $2\src11__data_o$next[3:0]$10762 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src11__data_o$next[3:0]$10764 \w1__data_i + case + assign $4\src11__data_o$next[3:0]$10764 $3\src11__data_o$next[3:0]$10763 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src11__data_o$next[3:0]$10765 \reg + case + assign $5\src11__data_o$next[3:0]$10765 $4\src11__data_o$next[3:0]$10764 + end + case + assign $1\src11__data_o$next[3:0]$10761 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src11__data_o$next[3:0]$10766 4'0000 + case + assign $6\src11__data_o$next[3:0]$10766 $1\src11__data_o$next[3:0]$10761 + end + sync always + update \src11__data_o$next $0\src11__data_o$next[3:0]$10760 + end + attribute \src "libresoc.v:167891.3-167920.6" + process $proc$libresoc.v:167891$10767 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:167892.5-167892.29" + switch \initial + attribute \src "libresoc.v:167892.9-167892.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src11__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:167921.3-167947.6" + process $proc$libresoc.v:167921$10768 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$10769 $4\reg$next[3:0]$10773 + attribute \src "libresoc.v:167922.5-167922.29" + switch \initial + attribute \src "libresoc.v:167922.9-167922.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$10770 \dest11__data_i + case + assign $1\reg$next[3:0]$10770 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$10771 \dest21__data_i + case + assign $2\reg$next[3:0]$10771 $1\reg$next[3:0]$10770 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$10772 \w1__data_i + case + assign $3\reg$next[3:0]$10772 $2\reg$next[3:0]$10771 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$10773 4'0000 + case + assign $4\reg$next[3:0]$10773 $3\reg$next[3:0]$10772 + end + sync always + update \reg$next $0\reg$next[3:0]$10769 + end + attribute \src "libresoc.v:167948.3-167987.6" + process $proc$libresoc.v:167948$10774 + assign { } { } + assign { } { } + assign { } { } + assign $0\src21__data_o$next[3:0]$10775 $6\src21__data_o$next[3:0]$10781 + attribute \src "libresoc.v:167949.5-167949.29" + switch \initial + attribute \src "libresoc.v:167949.9-167949.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src21__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src21__data_o$next[3:0]$10776 $5\src21__data_o$next[3:0]$10780 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src21__data_o$next[3:0]$10777 \dest11__data_i + case + assign $2\src21__data_o$next[3:0]$10777 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src21__data_o$next[3:0]$10778 \dest21__data_i + case + assign $3\src21__data_o$next[3:0]$10778 $2\src21__data_o$next[3:0]$10777 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src21__data_o$next[3:0]$10779 \w1__data_i + case + assign $4\src21__data_o$next[3:0]$10779 $3\src21__data_o$next[3:0]$10778 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src21__data_o$next[3:0]$10780 \reg + case + assign $5\src21__data_o$next[3:0]$10780 $4\src21__data_o$next[3:0]$10779 + end + case + assign $1\src21__data_o$next[3:0]$10776 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src21__data_o$next[3:0]$10781 4'0000 + case + assign $6\src21__data_o$next[3:0]$10781 $1\src21__data_o$next[3:0]$10776 + end + sync always + update \src21__data_o$next $0\src21__data_o$next[3:0]$10775 + end + attribute \src "libresoc.v:167988.3-168017.6" + process $proc$libresoc.v:167988$10782 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$10783 $1\wr_detect$4[0:0]$10784 + attribute \src "libresoc.v:167989.5-167989.29" + switch \initial + attribute \src "libresoc.v:167989.9-167989.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src21__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$10784 $4\wr_detect$4[0:0]$10787 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$10785 1'1 + case + assign $2\wr_detect$4[0:0]$10785 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$10786 1'1 + case + assign $3\wr_detect$4[0:0]$10786 $2\wr_detect$4[0:0]$10785 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$10787 1'1 + case + assign $4\wr_detect$4[0:0]$10787 $3\wr_detect$4[0:0]$10786 + end + case + assign $1\wr_detect$4[0:0]$10784 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$10783 + end + attribute \src "libresoc.v:168018.3-168057.6" + process $proc$libresoc.v:168018$10788 + assign { } { } + assign { } { } + assign { } { } + assign $0\src31__data_o$next[3:0]$10789 $6\src31__data_o$next[3:0]$10795 + attribute \src "libresoc.v:168019.5-168019.29" + switch \initial + attribute \src "libresoc.v:168019.9-168019.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src31__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src31__data_o$next[3:0]$10790 $5\src31__data_o$next[3:0]$10794 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src31__data_o$next[3:0]$10791 \dest11__data_i + case + assign $2\src31__data_o$next[3:0]$10791 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src31__data_o$next[3:0]$10792 \dest21__data_i + case + assign $3\src31__data_o$next[3:0]$10792 $2\src31__data_o$next[3:0]$10791 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src31__data_o$next[3:0]$10793 \w1__data_i + case + assign $4\src31__data_o$next[3:0]$10793 $3\src31__data_o$next[3:0]$10792 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src31__data_o$next[3:0]$10794 \reg + case + assign $5\src31__data_o$next[3:0]$10794 $4\src31__data_o$next[3:0]$10793 + end + case + assign $1\src31__data_o$next[3:0]$10790 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src31__data_o$next[3:0]$10795 4'0000 + case + assign $6\src31__data_o$next[3:0]$10795 $1\src31__data_o$next[3:0]$10790 + end + sync always + update \src31__data_o$next $0\src31__data_o$next[3:0]$10789 + end + attribute \src "libresoc.v:168058.3-168087.6" + process $proc$libresoc.v:168058$10796 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$10797 $1\wr_detect$7[0:0]$10798 + attribute \src "libresoc.v:168059.5-168059.29" + switch \initial + attribute \src "libresoc.v:168059.9-168059.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src31__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$10798 $4\wr_detect$7[0:0]$10801 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$10799 1'1 + case + assign $2\wr_detect$7[0:0]$10799 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$10800 1'1 + case + assign $3\wr_detect$7[0:0]$10800 $2\wr_detect$7[0:0]$10799 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$10801 1'1 + case + assign $4\wr_detect$7[0:0]$10801 $3\wr_detect$7[0:0]$10800 + end + case + assign $1\wr_detect$7[0:0]$10798 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$10797 + end + attribute \src "libresoc.v:168088.3-168127.6" + process $proc$libresoc.v:168088$10802 + assign { } { } + assign { } { } + assign { } { } + assign $0\r1__data_o$next[3:0]$10803 $6\r1__data_o$next[3:0]$10809 + attribute \src "libresoc.v:168089.5-168089.29" + switch \initial + attribute \src "libresoc.v:168089.9-168089.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r1__data_o$next[3:0]$10804 $5\r1__data_o$next[3:0]$10808 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r1__data_o$next[3:0]$10805 \dest11__data_i + case + assign $2\r1__data_o$next[3:0]$10805 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r1__data_o$next[3:0]$10806 \dest21__data_i + case + assign $3\r1__data_o$next[3:0]$10806 $2\r1__data_o$next[3:0]$10805 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r1__data_o$next[3:0]$10807 \w1__data_i + case + assign $4\r1__data_o$next[3:0]$10807 $3\r1__data_o$next[3:0]$10806 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r1__data_o$next[3:0]$10808 \reg + case + assign $5\r1__data_o$next[3:0]$10808 $4\r1__data_o$next[3:0]$10807 + end + case + assign $1\r1__data_o$next[3:0]$10804 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r1__data_o$next[3:0]$10809 4'0000 + case + assign $6\r1__data_o$next[3:0]$10809 $1\r1__data_o$next[3:0]$10804 + end + sync always + update \r1__data_o$next $0\r1__data_o$next[3:0]$10803 + end + attribute \src "libresoc.v:168128.3-168157.6" + process $proc$libresoc.v:168128$10810 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$10811 $1\wr_detect$10[0:0]$10812 + attribute \src "libresoc.v:168129.5-168129.29" + switch \initial + attribute \src "libresoc.v:168129.9-168129.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$10812 $4\wr_detect$10[0:0]$10815 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$10813 1'1 + case + assign $2\wr_detect$10[0:0]$10813 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$10814 1'1 + case + assign $3\wr_detect$10[0:0]$10814 $2\wr_detect$10[0:0]$10813 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$10815 1'1 + case + assign $4\wr_detect$10[0:0]$10815 $3\wr_detect$10[0:0]$10814 + end + case + assign $1\wr_detect$10[0:0]$10812 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$10811 + end + attribute \src "libresoc.v:168158.3-168197.6" + process $proc$libresoc.v:168158$10816 + assign { } { } + assign { } { } + assign { } { } + assign $0\r21__data_o$next[3:0]$10817 $6\r21__data_o$next[3:0]$10823 + attribute \src "libresoc.v:168159.5-168159.29" + switch \initial + attribute \src "libresoc.v:168159.9-168159.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r21__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r21__data_o$next[3:0]$10818 $5\r21__data_o$next[3:0]$10822 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r21__data_o$next[3:0]$10819 \dest11__data_i + case + assign $2\r21__data_o$next[3:0]$10819 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r21__data_o$next[3:0]$10820 \dest21__data_i + case + assign $3\r21__data_o$next[3:0]$10820 $2\r21__data_o$next[3:0]$10819 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r21__data_o$next[3:0]$10821 \w1__data_i + case + assign $4\r21__data_o$next[3:0]$10821 $3\r21__data_o$next[3:0]$10820 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r21__data_o$next[3:0]$10822 \reg + case + assign $5\r21__data_o$next[3:0]$10822 $4\r21__data_o$next[3:0]$10821 + end + case + assign $1\r21__data_o$next[3:0]$10818 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r21__data_o$next[3:0]$10823 4'0000 + case + assign $6\r21__data_o$next[3:0]$10823 $1\r21__data_o$next[3:0]$10818 + end + sync always + update \r21__data_o$next $0\r21__data_o$next[3:0]$10817 + end + attribute \src "libresoc.v:168198.3-168227.6" + process $proc$libresoc.v:168198$10824 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$10825 $1\wr_detect$13[0:0]$10826 + attribute \src "libresoc.v:168199.5-168199.29" + switch \initial + attribute \src "libresoc.v:168199.9-168199.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r21__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$10826 $4\wr_detect$13[0:0]$10829 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$10827 1'1 + case + assign $2\wr_detect$13[0:0]$10827 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$10828 1'1 + case + assign $3\wr_detect$13[0:0]$10828 $2\wr_detect$13[0:0]$10827 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$10829 1'1 + case + assign $4\wr_detect$13[0:0]$10829 $3\wr_detect$13[0:0]$10828 + end + case + assign $1\wr_detect$13[0:0]$10826 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$10825 + end + connect \$9 $not$libresoc.v:167834$10748_Y + connect \$12 $not$libresoc.v:167835$10749_Y + connect \$1 $not$libresoc.v:167836$10750_Y + connect \$3 $not$libresoc.v:167837$10751_Y + connect \$6 $not$libresoc.v:167838$10752_Y +end +attribute \src "libresoc.v:168232.1-168677.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_1" +attribute \generator "nMigen" +module \reg_1$133 + attribute \src "libresoc.v:168233.7-168233.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:168562.3-168607.6" + wire width 2 $0\r1__data_o$next[1:0]$10889 + attribute \src "libresoc.v:168308.3-168309.37" + wire width 2 $0\r1__data_o[1:0] + attribute \src "libresoc.v:168644.3-168676.6" + wire width 2 $0\reg$next[1:0]$10905 + attribute \src "libresoc.v:168306.3-168307.25" + wire width 2 $0\reg[1:0] + attribute \src "libresoc.v:168316.3-168361.6" + wire width 2 $0\src11__data_o$next[1:0]$10847 + attribute \src "libresoc.v:168314.3-168315.43" + wire width 2 $0\src11__data_o[1:0] + attribute \src "libresoc.v:168398.3-168443.6" + wire width 2 $0\src21__data_o$next[1:0]$10857 + attribute \src "libresoc.v:168312.3-168313.43" + wire width 2 $0\src21__data_o[1:0] + attribute \src "libresoc.v:168480.3-168525.6" + wire width 2 $0\src31__data_o$next[1:0]$10873 + attribute \src "libresoc.v:168310.3-168311.43" + wire width 2 $0\src31__data_o[1:0] + attribute \src "libresoc.v:168608.3-168643.6" + wire $0\wr_detect$10[0:0]$10898 + attribute \src "libresoc.v:168444.3-168479.6" + wire $0\wr_detect$4[0:0]$10866 + attribute \src "libresoc.v:168526.3-168561.6" + wire $0\wr_detect$7[0:0]$10882 + attribute \src "libresoc.v:168362.3-168397.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:168562.3-168607.6" + wire width 2 $1\r1__data_o$next[1:0]$10890 + attribute \src "libresoc.v:168260.13-168260.30" + wire width 2 $1\r1__data_o[1:0] + attribute \src "libresoc.v:168644.3-168676.6" + wire width 2 $1\reg$next[1:0]$10906 + attribute \src "libresoc.v:168266.13-168266.25" + wire width 2 $1\reg[1:0] + attribute \src "libresoc.v:168316.3-168361.6" + wire width 2 $1\src11__data_o$next[1:0]$10848 + attribute \src "libresoc.v:168271.13-168271.33" + wire width 2 $1\src11__data_o[1:0] + attribute \src "libresoc.v:168398.3-168443.6" + wire width 2 $1\src21__data_o$next[1:0]$10858 + attribute \src "libresoc.v:168278.13-168278.33" + wire width 2 $1\src21__data_o[1:0] + attribute \src "libresoc.v:168480.3-168525.6" + wire width 2 $1\src31__data_o$next[1:0]$10874 + attribute \src "libresoc.v:168285.13-168285.33" + wire width 2 $1\src31__data_o[1:0] + attribute \src "libresoc.v:168608.3-168643.6" + wire $1\wr_detect$10[0:0]$10899 + attribute \src "libresoc.v:168444.3-168479.6" + wire $1\wr_detect$4[0:0]$10867 + attribute \src "libresoc.v:168526.3-168561.6" + wire $1\wr_detect$7[0:0]$10883 + attribute \src "libresoc.v:168362.3-168397.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:168562.3-168607.6" + wire width 2 $2\r1__data_o$next[1:0]$10891 + attribute \src "libresoc.v:168644.3-168676.6" + wire width 2 $2\reg$next[1:0]$10907 + attribute \src "libresoc.v:168316.3-168361.6" + wire width 2 $2\src11__data_o$next[1:0]$10849 + attribute \src "libresoc.v:168398.3-168443.6" + wire width 2 $2\src21__data_o$next[1:0]$10859 + attribute \src "libresoc.v:168480.3-168525.6" + wire width 2 $2\src31__data_o$next[1:0]$10875 + attribute \src "libresoc.v:168608.3-168643.6" + wire $2\wr_detect$10[0:0]$10900 + attribute \src "libresoc.v:168444.3-168479.6" + wire $2\wr_detect$4[0:0]$10868 + attribute \src "libresoc.v:168526.3-168561.6" + wire $2\wr_detect$7[0:0]$10884 + attribute \src "libresoc.v:168362.3-168397.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:168562.3-168607.6" + wire width 2 $3\r1__data_o$next[1:0]$10892 + attribute \src "libresoc.v:168644.3-168676.6" + wire width 2 $3\reg$next[1:0]$10908 + attribute \src "libresoc.v:168316.3-168361.6" + wire width 2 $3\src11__data_o$next[1:0]$10850 + attribute \src "libresoc.v:168398.3-168443.6" + wire width 2 $3\src21__data_o$next[1:0]$10860 + attribute \src "libresoc.v:168480.3-168525.6" + wire width 2 $3\src31__data_o$next[1:0]$10876 + attribute \src "libresoc.v:168608.3-168643.6" + wire $3\wr_detect$10[0:0]$10901 + attribute \src "libresoc.v:168444.3-168479.6" + wire $3\wr_detect$4[0:0]$10869 + attribute \src "libresoc.v:168526.3-168561.6" + wire $3\wr_detect$7[0:0]$10885 + attribute \src "libresoc.v:168362.3-168397.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:168562.3-168607.6" + wire width 2 $4\r1__data_o$next[1:0]$10893 + attribute \src "libresoc.v:168644.3-168676.6" + wire width 2 $4\reg$next[1:0]$10909 + attribute \src "libresoc.v:168316.3-168361.6" + wire width 2 $4\src11__data_o$next[1:0]$10851 + attribute \src "libresoc.v:168398.3-168443.6" + wire width 2 $4\src21__data_o$next[1:0]$10861 + attribute \src "libresoc.v:168480.3-168525.6" + wire width 2 $4\src31__data_o$next[1:0]$10877 + attribute \src "libresoc.v:168608.3-168643.6" + wire $4\wr_detect$10[0:0]$10902 + attribute \src "libresoc.v:168444.3-168479.6" + wire $4\wr_detect$4[0:0]$10870 + attribute \src "libresoc.v:168526.3-168561.6" + wire $4\wr_detect$7[0:0]$10886 + attribute \src "libresoc.v:168362.3-168397.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:168562.3-168607.6" + wire width 2 $5\r1__data_o$next[1:0]$10894 + attribute \src "libresoc.v:168644.3-168676.6" + wire width 2 $5\reg$next[1:0]$10910 + attribute \src "libresoc.v:168316.3-168361.6" + wire width 2 $5\src11__data_o$next[1:0]$10852 + attribute \src "libresoc.v:168398.3-168443.6" + wire width 2 $5\src21__data_o$next[1:0]$10862 + attribute \src "libresoc.v:168480.3-168525.6" + wire width 2 $5\src31__data_o$next[1:0]$10878 + attribute \src "libresoc.v:168608.3-168643.6" + wire $5\wr_detect$10[0:0]$10903 + attribute \src "libresoc.v:168444.3-168479.6" + wire $5\wr_detect$4[0:0]$10871 + attribute \src "libresoc.v:168526.3-168561.6" + wire $5\wr_detect$7[0:0]$10887 + attribute \src "libresoc.v:168362.3-168397.6" + wire $5\wr_detect[0:0] + attribute \src "libresoc.v:168562.3-168607.6" + wire width 2 $6\r1__data_o$next[1:0]$10895 + attribute \src "libresoc.v:168316.3-168361.6" + wire width 2 $6\src11__data_o$next[1:0]$10853 + attribute \src "libresoc.v:168398.3-168443.6" + wire width 2 $6\src21__data_o$next[1:0]$10863 + attribute \src "libresoc.v:168480.3-168525.6" + wire width 2 $6\src31__data_o$next[1:0]$10879 + attribute \src "libresoc.v:168562.3-168607.6" + wire width 2 $7\r1__data_o$next[1:0]$10896 + attribute \src "libresoc.v:168316.3-168361.6" + wire width 2 $7\src11__data_o$next[1:0]$10854 + attribute \src "libresoc.v:168398.3-168443.6" + wire width 2 $7\src21__data_o$next[1:0]$10864 + attribute \src "libresoc.v:168480.3-168525.6" + wire width 2 $7\src31__data_o$next[1:0]$10880 + attribute \src "libresoc.v:168302.17-168302.104" + wire $not$libresoc.v:168302$10837_Y + attribute \src "libresoc.v:168303.17-168303.100" + wire $not$libresoc.v:168303$10838_Y + attribute \src "libresoc.v:168304.17-168304.103" + wire $not$libresoc.v:168304$10839_Y + attribute \src "libresoc.v:168305.17-168305.103" + wire $not$libresoc.v:168305$10840_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 9 \dest11__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \dest11__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 11 \dest21__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \dest21__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 13 \dest31__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 12 \dest31__wen + attribute \src "libresoc.v:168233.7-168233.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 14 \r1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \r1__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 15 \r1__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 2 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 2 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 3 \src11__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \src11__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \src11__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 5 \src21__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \src21__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \src21__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 7 \src31__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \src31__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \src31__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 16 \w1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 17 \w1__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:168302$10837 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:168302$10837_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:168303$10838 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:168303$10838_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:168304$10839 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:168304$10839_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:168305$10840 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:168305$10840_Y + end + attribute \src "libresoc.v:168233.7-168233.20" + process $proc$libresoc.v:168233$10911 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:168260.13-168260.30" + process $proc$libresoc.v:168260$10912 + assign { } { } + assign $1\r1__data_o[1:0] 2'00 + sync always + sync init + update \r1__data_o $1\r1__data_o[1:0] + end + attribute \src "libresoc.v:168266.13-168266.25" + process $proc$libresoc.v:168266$10913 + assign { } { } + assign $1\reg[1:0] 2'00 + sync always + sync init + update \reg $1\reg[1:0] + end + attribute \src "libresoc.v:168271.13-168271.33" + process $proc$libresoc.v:168271$10914 + assign { } { } + assign $1\src11__data_o[1:0] 2'00 + sync always + sync init + update \src11__data_o $1\src11__data_o[1:0] + end + attribute \src "libresoc.v:168278.13-168278.33" + process $proc$libresoc.v:168278$10915 + assign { } { } + assign $1\src21__data_o[1:0] 2'00 + sync always + sync init + update \src21__data_o $1\src21__data_o[1:0] + end + attribute \src "libresoc.v:168285.13-168285.33" + process $proc$libresoc.v:168285$10916 + assign { } { } + assign $1\src31__data_o[1:0] 2'00 + sync always + sync init + update \src31__data_o $1\src31__data_o[1:0] + end + attribute \src "libresoc.v:168306.3-168307.25" + process $proc$libresoc.v:168306$10841 + assign { } { } + assign $0\reg[1:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[1:0] + end + attribute \src "libresoc.v:168308.3-168309.37" + process $proc$libresoc.v:168308$10842 + assign { } { } + assign $0\r1__data_o[1:0] \r1__data_o$next + sync posedge \coresync_clk + update \r1__data_o $0\r1__data_o[1:0] + end + attribute \src "libresoc.v:168310.3-168311.43" + process $proc$libresoc.v:168310$10843 + assign { } { } + assign $0\src31__data_o[1:0] \src31__data_o$next + sync posedge \coresync_clk + update \src31__data_o $0\src31__data_o[1:0] + end + attribute \src "libresoc.v:168312.3-168313.43" + process $proc$libresoc.v:168312$10844 + assign { } { } + assign $0\src21__data_o[1:0] \src21__data_o$next + sync posedge \coresync_clk + update \src21__data_o $0\src21__data_o[1:0] + end + attribute \src "libresoc.v:168314.3-168315.43" + process $proc$libresoc.v:168314$10845 + assign { } { } + assign $0\src11__data_o[1:0] \src11__data_o$next + sync posedge \coresync_clk + update \src11__data_o $0\src11__data_o[1:0] + end + attribute \src "libresoc.v:168316.3-168361.6" + process $proc$libresoc.v:168316$10846 + assign { } { } + assign { } { } + assign { } { } + assign $0\src11__data_o$next[1:0]$10847 $7\src11__data_o$next[1:0]$10854 + attribute \src "libresoc.v:168317.5-168317.29" + switch \initial + attribute \src "libresoc.v:168317.9-168317.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src11__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src11__data_o$next[1:0]$10848 $6\src11__data_o$next[1:0]$10853 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src11__data_o$next[1:0]$10849 \dest11__data_i + case + assign $2\src11__data_o$next[1:0]$10849 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src11__data_o$next[1:0]$10850 \dest21__data_i + case + assign $3\src11__data_o$next[1:0]$10850 $2\src11__data_o$next[1:0]$10849 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src11__data_o$next[1:0]$10851 \dest31__data_i + case + assign $4\src11__data_o$next[1:0]$10851 $3\src11__data_o$next[1:0]$10850 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src11__data_o$next[1:0]$10852 \w1__data_i + case + assign $5\src11__data_o$next[1:0]$10852 $4\src11__data_o$next[1:0]$10851 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src11__data_o$next[1:0]$10853 \reg + case + assign $6\src11__data_o$next[1:0]$10853 $5\src11__data_o$next[1:0]$10852 + end + case + assign $1\src11__data_o$next[1:0]$10848 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src11__data_o$next[1:0]$10854 2'00 + case + assign $7\src11__data_o$next[1:0]$10854 $1\src11__data_o$next[1:0]$10848 + end + sync always + update \src11__data_o$next $0\src11__data_o$next[1:0]$10847 + end + attribute \src "libresoc.v:168362.3-168397.6" + process $proc$libresoc.v:168362$10855 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:168363.5-168363.29" + switch \initial + attribute \src "libresoc.v:168363.9-168363.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src11__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $5\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect[0:0] 1'1 + case + assign $5\wr_detect[0:0] $4\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:168398.3-168443.6" + process $proc$libresoc.v:168398$10856 + assign { } { } + assign { } { } + assign { } { } + assign $0\src21__data_o$next[1:0]$10857 $7\src21__data_o$next[1:0]$10864 + attribute \src "libresoc.v:168399.5-168399.29" + switch \initial + attribute \src "libresoc.v:168399.9-168399.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src21__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src21__data_o$next[1:0]$10858 $6\src21__data_o$next[1:0]$10863 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src21__data_o$next[1:0]$10859 \dest11__data_i + case + assign $2\src21__data_o$next[1:0]$10859 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src21__data_o$next[1:0]$10860 \dest21__data_i + case + assign $3\src21__data_o$next[1:0]$10860 $2\src21__data_o$next[1:0]$10859 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src21__data_o$next[1:0]$10861 \dest31__data_i + case + assign $4\src21__data_o$next[1:0]$10861 $3\src21__data_o$next[1:0]$10860 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src21__data_o$next[1:0]$10862 \w1__data_i + case + assign $5\src21__data_o$next[1:0]$10862 $4\src21__data_o$next[1:0]$10861 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src21__data_o$next[1:0]$10863 \reg + case + assign $6\src21__data_o$next[1:0]$10863 $5\src21__data_o$next[1:0]$10862 + end + case + assign $1\src21__data_o$next[1:0]$10858 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src21__data_o$next[1:0]$10864 2'00 + case + assign $7\src21__data_o$next[1:0]$10864 $1\src21__data_o$next[1:0]$10858 + end + sync always + update \src21__data_o$next $0\src21__data_o$next[1:0]$10857 + end + attribute \src "libresoc.v:168444.3-168479.6" + process $proc$libresoc.v:168444$10865 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$10866 $1\wr_detect$4[0:0]$10867 + attribute \src "libresoc.v:168445.5-168445.29" + switch \initial + attribute \src "libresoc.v:168445.9-168445.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src21__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$10867 $5\wr_detect$4[0:0]$10871 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$10868 1'1 + case + assign $2\wr_detect$4[0:0]$10868 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$10869 1'1 + case + assign $3\wr_detect$4[0:0]$10869 $2\wr_detect$4[0:0]$10868 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$10870 1'1 + case + assign $4\wr_detect$4[0:0]$10870 $3\wr_detect$4[0:0]$10869 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$4[0:0]$10871 1'1 + case + assign $5\wr_detect$4[0:0]$10871 $4\wr_detect$4[0:0]$10870 + end + case + assign $1\wr_detect$4[0:0]$10867 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$10866 + end + attribute \src "libresoc.v:168480.3-168525.6" + process $proc$libresoc.v:168480$10872 + assign { } { } + assign { } { } + assign { } { } + assign $0\src31__data_o$next[1:0]$10873 $7\src31__data_o$next[1:0]$10880 + attribute \src "libresoc.v:168481.5-168481.29" + switch \initial + attribute \src "libresoc.v:168481.9-168481.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src31__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src31__data_o$next[1:0]$10874 $6\src31__data_o$next[1:0]$10879 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src31__data_o$next[1:0]$10875 \dest11__data_i + case + assign $2\src31__data_o$next[1:0]$10875 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src31__data_o$next[1:0]$10876 \dest21__data_i + case + assign $3\src31__data_o$next[1:0]$10876 $2\src31__data_o$next[1:0]$10875 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src31__data_o$next[1:0]$10877 \dest31__data_i + case + assign $4\src31__data_o$next[1:0]$10877 $3\src31__data_o$next[1:0]$10876 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src31__data_o$next[1:0]$10878 \w1__data_i + case + assign $5\src31__data_o$next[1:0]$10878 $4\src31__data_o$next[1:0]$10877 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src31__data_o$next[1:0]$10879 \reg + case + assign $6\src31__data_o$next[1:0]$10879 $5\src31__data_o$next[1:0]$10878 + end + case + assign $1\src31__data_o$next[1:0]$10874 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src31__data_o$next[1:0]$10880 2'00 + case + assign $7\src31__data_o$next[1:0]$10880 $1\src31__data_o$next[1:0]$10874 + end + sync always + update \src31__data_o$next $0\src31__data_o$next[1:0]$10873 + end + attribute \src "libresoc.v:168526.3-168561.6" + process $proc$libresoc.v:168526$10881 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$10882 $1\wr_detect$7[0:0]$10883 + attribute \src "libresoc.v:168527.5-168527.29" + switch \initial + attribute \src "libresoc.v:168527.9-168527.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src31__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$10883 $5\wr_detect$7[0:0]$10887 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$10884 1'1 + case + assign $2\wr_detect$7[0:0]$10884 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$10885 1'1 + case + assign $3\wr_detect$7[0:0]$10885 $2\wr_detect$7[0:0]$10884 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$10886 1'1 + case + assign $4\wr_detect$7[0:0]$10886 $3\wr_detect$7[0:0]$10885 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$7[0:0]$10887 1'1 + case + assign $5\wr_detect$7[0:0]$10887 $4\wr_detect$7[0:0]$10886 + end + case + assign $1\wr_detect$7[0:0]$10883 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$10882 + end + attribute \src "libresoc.v:168562.3-168607.6" + process $proc$libresoc.v:168562$10888 + assign { } { } + assign { } { } + assign { } { } + assign $0\r1__data_o$next[1:0]$10889 $7\r1__data_o$next[1:0]$10896 + attribute \src "libresoc.v:168563.5-168563.29" + switch \initial + attribute \src "libresoc.v:168563.9-168563.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r1__data_o$next[1:0]$10890 $6\r1__data_o$next[1:0]$10895 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r1__data_o$next[1:0]$10891 \dest11__data_i + case + assign $2\r1__data_o$next[1:0]$10891 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r1__data_o$next[1:0]$10892 \dest21__data_i + case + assign $3\r1__data_o$next[1:0]$10892 $2\r1__data_o$next[1:0]$10891 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r1__data_o$next[1:0]$10893 \dest31__data_i + case + assign $4\r1__data_o$next[1:0]$10893 $3\r1__data_o$next[1:0]$10892 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r1__data_o$next[1:0]$10894 \w1__data_i + case + assign $5\r1__data_o$next[1:0]$10894 $4\r1__data_o$next[1:0]$10893 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r1__data_o$next[1:0]$10895 \reg + case + assign $6\r1__data_o$next[1:0]$10895 $5\r1__data_o$next[1:0]$10894 + end + case + assign $1\r1__data_o$next[1:0]$10890 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\r1__data_o$next[1:0]$10896 2'00 + case + assign $7\r1__data_o$next[1:0]$10896 $1\r1__data_o$next[1:0]$10890 + end + sync always + update \r1__data_o$next $0\r1__data_o$next[1:0]$10889 + end + attribute \src "libresoc.v:168608.3-168643.6" + process $proc$libresoc.v:168608$10897 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$10898 $1\wr_detect$10[0:0]$10899 + attribute \src "libresoc.v:168609.5-168609.29" + switch \initial + attribute \src "libresoc.v:168609.9-168609.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$10899 $5\wr_detect$10[0:0]$10903 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$10900 1'1 + case + assign $2\wr_detect$10[0:0]$10900 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$10901 1'1 + case + assign $3\wr_detect$10[0:0]$10901 $2\wr_detect$10[0:0]$10900 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$10902 1'1 + case + assign $4\wr_detect$10[0:0]$10902 $3\wr_detect$10[0:0]$10901 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$10[0:0]$10903 1'1 + case + assign $5\wr_detect$10[0:0]$10903 $4\wr_detect$10[0:0]$10902 + end + case + assign $1\wr_detect$10[0:0]$10899 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$10898 + end + attribute \src "libresoc.v:168644.3-168676.6" + process $proc$libresoc.v:168644$10904 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[1:0]$10905 $5\reg$next[1:0]$10910 + attribute \src "libresoc.v:168645.5-168645.29" + switch \initial + attribute \src "libresoc.v:168645.9-168645.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[1:0]$10906 \dest11__data_i + case + assign $1\reg$next[1:0]$10906 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[1:0]$10907 \dest21__data_i + case + assign $2\reg$next[1:0]$10907 $1\reg$next[1:0]$10906 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest31__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[1:0]$10908 \dest31__data_i + case + assign $3\reg$next[1:0]$10908 $2\reg$next[1:0]$10907 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[1:0]$10909 \w1__data_i + case + assign $4\reg$next[1:0]$10909 $3\reg$next[1:0]$10908 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\reg$next[1:0]$10910 2'00 + case + assign $5\reg$next[1:0]$10910 $4\reg$next[1:0]$10909 + end + sync always + update \reg$next $0\reg$next[1:0]$10905 + end + connect \$9 $not$libresoc.v:168302$10837_Y + connect \$1 $not$libresoc.v:168303$10838_Y + connect \$3 $not$libresoc.v:168304$10839_Y + connect \$6 $not$libresoc.v:168305$10840_Y +end +attribute \src "libresoc.v:168681.1-168900.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_1" +attribute \generator "nMigen" +module \reg_1$136 + attribute \src "libresoc.v:168733.3-168772.6" + wire width 64 $0\cia1__data_o$next[63:0]$10923 + attribute \src "libresoc.v:168731.3-168732.41" + wire width 64 $0\cia1__data_o[63:0] + attribute \src "libresoc.v:168682.7-168682.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:168803.3-168842.6" + wire width 64 $0\msr1__data_o$next[63:0]$10932 + attribute \src "libresoc.v:168729.3-168730.41" + wire width 64 $0\msr1__data_o[63:0] + attribute \src "libresoc.v:168873.3-168899.6" + wire width 64 $0\reg$next[63:0]$10946 + attribute \src "libresoc.v:168727.3-168728.25" + wire width 64 $0\reg[63:0] + attribute \src "libresoc.v:168843.3-168872.6" + wire $0\wr_detect$4[0:0]$10940 + attribute \src "libresoc.v:168773.3-168802.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:168733.3-168772.6" + wire width 64 $1\cia1__data_o$next[63:0]$10924 + attribute \src "libresoc.v:168689.14-168689.49" + wire width 64 $1\cia1__data_o[63:0] + attribute \src "libresoc.v:168803.3-168842.6" + wire width 64 $1\msr1__data_o$next[63:0]$10933 + attribute \src "libresoc.v:168706.14-168706.49" + wire width 64 $1\msr1__data_o[63:0] + attribute \src "libresoc.v:168873.3-168899.6" + wire width 64 $1\reg$next[63:0]$10947 + attribute \src "libresoc.v:168718.14-168718.42" + wire width 64 $1\reg[63:0] + attribute \src "libresoc.v:168843.3-168872.6" + wire $1\wr_detect$4[0:0]$10941 + attribute \src "libresoc.v:168773.3-168802.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:168733.3-168772.6" + wire width 64 $2\cia1__data_o$next[63:0]$10925 + attribute \src "libresoc.v:168803.3-168842.6" + wire width 64 $2\msr1__data_o$next[63:0]$10934 + attribute \src "libresoc.v:168873.3-168899.6" + wire width 64 $2\reg$next[63:0]$10948 + attribute \src "libresoc.v:168843.3-168872.6" + wire $2\wr_detect$4[0:0]$10942 + attribute \src "libresoc.v:168773.3-168802.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:168733.3-168772.6" + wire width 64 $3\cia1__data_o$next[63:0]$10926 + attribute \src "libresoc.v:168803.3-168842.6" + wire width 64 $3\msr1__data_o$next[63:0]$10935 + attribute \src "libresoc.v:168873.3-168899.6" + wire width 64 $3\reg$next[63:0]$10949 + attribute \src "libresoc.v:168843.3-168872.6" + wire $3\wr_detect$4[0:0]$10943 + attribute \src "libresoc.v:168773.3-168802.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:168733.3-168772.6" + wire width 64 $4\cia1__data_o$next[63:0]$10927 + attribute \src "libresoc.v:168803.3-168842.6" + wire width 64 $4\msr1__data_o$next[63:0]$10936 + attribute \src "libresoc.v:168873.3-168899.6" + wire width 64 $4\reg$next[63:0]$10950 + attribute \src "libresoc.v:168843.3-168872.6" + wire $4\wr_detect$4[0:0]$10944 + attribute \src "libresoc.v:168773.3-168802.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:168733.3-168772.6" + wire width 64 $5\cia1__data_o$next[63:0]$10928 + attribute \src "libresoc.v:168803.3-168842.6" + wire width 64 $5\msr1__data_o$next[63:0]$10937 + attribute \src "libresoc.v:168733.3-168772.6" + wire width 64 $6\cia1__data_o$next[63:0]$10929 + attribute \src "libresoc.v:168803.3-168842.6" + wire width 64 $6\msr1__data_o$next[63:0]$10938 + attribute \src "libresoc.v:168725.17-168725.100" + wire $not$libresoc.v:168725$10917_Y + attribute \src "libresoc.v:168726.17-168726.103" + wire $not$libresoc.v:168726$10918_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 3 \cia1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \cia1__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \cia1__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 12 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 11 \d_wr11__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \d_wr11__wen + attribute \src "libresoc.v:168682.7-168682.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 9 \msr1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 5 \msr1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \msr1__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \msr1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \msr1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 7 \nia1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \nia1__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:168725$10917 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:168725$10917_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:168726$10918 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:168726$10918_Y + end + attribute \src "libresoc.v:168682.7-168682.20" + process $proc$libresoc.v:168682$10951 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:168689.14-168689.49" + process $proc$libresoc.v:168689$10952 + assign { } { } + assign $1\cia1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \cia1__data_o $1\cia1__data_o[63:0] + end + attribute \src "libresoc.v:168706.14-168706.49" + process $proc$libresoc.v:168706$10953 + assign { } { } + assign $1\msr1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \msr1__data_o $1\msr1__data_o[63:0] + end + attribute \src "libresoc.v:168718.14-168718.42" + process $proc$libresoc.v:168718$10954 + assign { } { } + assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \reg $1\reg[63:0] + end + attribute \src "libresoc.v:168727.3-168728.25" + process $proc$libresoc.v:168727$10919 + assign { } { } + assign $0\reg[63:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[63:0] + end + attribute \src "libresoc.v:168729.3-168730.41" + process $proc$libresoc.v:168729$10920 + assign { } { } + assign $0\msr1__data_o[63:0] \msr1__data_o$next + sync posedge \coresync_clk + update \msr1__data_o $0\msr1__data_o[63:0] + end + attribute \src "libresoc.v:168731.3-168732.41" + process $proc$libresoc.v:168731$10921 + assign { } { } + assign $0\cia1__data_o[63:0] \cia1__data_o$next + sync posedge \coresync_clk + update \cia1__data_o $0\cia1__data_o[63:0] + end + attribute \src "libresoc.v:168733.3-168772.6" + process $proc$libresoc.v:168733$10922 + assign { } { } + assign { } { } + assign { } { } + assign $0\cia1__data_o$next[63:0]$10923 $6\cia1__data_o$next[63:0]$10929 + attribute \src "libresoc.v:168734.5-168734.29" + switch \initial + attribute \src "libresoc.v:168734.9-168734.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\cia1__data_o$next[63:0]$10924 $5\cia1__data_o$next[63:0]$10928 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cia1__data_o$next[63:0]$10925 \nia1__data_i + case + assign $2\cia1__data_o$next[63:0]$10925 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cia1__data_o$next[63:0]$10926 \msr1__data_i + case + assign $3\cia1__data_o$next[63:0]$10926 $2\cia1__data_o$next[63:0]$10925 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cia1__data_o$next[63:0]$10927 \d_wr11__data_i + case + assign $4\cia1__data_o$next[63:0]$10927 $3\cia1__data_o$next[63:0]$10926 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\cia1__data_o$next[63:0]$10928 \reg + case + assign $5\cia1__data_o$next[63:0]$10928 $4\cia1__data_o$next[63:0]$10927 + end + case + assign $1\cia1__data_o$next[63:0]$10924 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\cia1__data_o$next[63:0]$10929 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $6\cia1__data_o$next[63:0]$10929 $1\cia1__data_o$next[63:0]$10924 + end + sync always + update \cia1__data_o$next $0\cia1__data_o$next[63:0]$10923 + end + attribute \src "libresoc.v:168773.3-168802.6" + process $proc$libresoc.v:168773$10930 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:168774.5-168774.29" + switch \initial + attribute \src "libresoc.v:168774.9-168774.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:168803.3-168842.6" + process $proc$libresoc.v:168803$10931 + assign { } { } + assign { } { } + assign { } { } + assign $0\msr1__data_o$next[63:0]$10932 $6\msr1__data_o$next[63:0]$10938 + attribute \src "libresoc.v:168804.5-168804.29" + switch \initial + attribute \src "libresoc.v:168804.9-168804.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \msr1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\msr1__data_o$next[63:0]$10933 $5\msr1__data_o$next[63:0]$10937 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr1__data_o$next[63:0]$10934 \nia1__data_i + case + assign $2\msr1__data_o$next[63:0]$10934 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\msr1__data_o$next[63:0]$10935 \msr1__data_i + case + assign $3\msr1__data_o$next[63:0]$10935 $2\msr1__data_o$next[63:0]$10934 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\msr1__data_o$next[63:0]$10936 \d_wr11__data_i + case + assign $4\msr1__data_o$next[63:0]$10936 $3\msr1__data_o$next[63:0]$10935 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\msr1__data_o$next[63:0]$10937 \reg + case + assign $5\msr1__data_o$next[63:0]$10937 $4\msr1__data_o$next[63:0]$10936 + end + case + assign $1\msr1__data_o$next[63:0]$10933 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\msr1__data_o$next[63:0]$10938 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $6\msr1__data_o$next[63:0]$10938 $1\msr1__data_o$next[63:0]$10933 + end + sync always + update \msr1__data_o$next $0\msr1__data_o$next[63:0]$10932 + end + attribute \src "libresoc.v:168843.3-168872.6" + process $proc$libresoc.v:168843$10939 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$10940 $1\wr_detect$4[0:0]$10941 + attribute \src "libresoc.v:168844.5-168844.29" + switch \initial + attribute \src "libresoc.v:168844.9-168844.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \msr1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$10941 $4\wr_detect$4[0:0]$10944 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$10942 1'1 + case + assign $2\wr_detect$4[0:0]$10942 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$10943 1'1 + case + assign $3\wr_detect$4[0:0]$10943 $2\wr_detect$4[0:0]$10942 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$10944 1'1 + case + assign $4\wr_detect$4[0:0]$10944 $3\wr_detect$4[0:0]$10943 + end + case + assign $1\wr_detect$4[0:0]$10941 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$10940 + end + attribute \src "libresoc.v:168873.3-168899.6" + process $proc$libresoc.v:168873$10945 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[63:0]$10946 $4\reg$next[63:0]$10950 + attribute \src "libresoc.v:168874.5-168874.29" + switch \initial + attribute \src "libresoc.v:168874.9-168874.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \nia1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[63:0]$10947 \nia1__data_i + case + assign $1\reg$next[63:0]$10947 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \msr1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[63:0]$10948 \msr1__data_i + case + assign $2\reg$next[63:0]$10948 $1\reg$next[63:0]$10947 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \d_wr11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[63:0]$10949 \d_wr11__data_i + case + assign $3\reg$next[63:0]$10949 $2\reg$next[63:0]$10948 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[63:0]$10950 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $4\reg$next[63:0]$10950 $3\reg$next[63:0]$10949 + end + sync always + update \reg$next $0\reg$next[63:0]$10946 + end + connect \$1 $not$libresoc.v:168725$10917_Y + connect \$3 $not$libresoc.v:168726$10918_Y +end +attribute \src "libresoc.v:168904.1-169375.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_2" +attribute \generator "nMigen" +module \reg_2 + attribute \src "libresoc.v:168905.7-168905.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:169305.3-169344.6" + wire width 4 $0\r22__data_o$next[3:0]$11024 + attribute \src "libresoc.v:168988.3-168989.39" + wire width 4 $0\r22__data_o[3:0] + attribute \src "libresoc.v:169235.3-169274.6" + wire width 4 $0\r2__data_o$next[3:0]$11010 + attribute \src "libresoc.v:168990.3-168991.37" + wire width 4 $0\r2__data_o[3:0] + attribute \src "libresoc.v:169068.3-169094.6" + wire width 4 $0\reg$next[3:0]$10976 + attribute \src "libresoc.v:168986.3-168987.25" + wire width 4 $0\reg[3:0] + attribute \src "libresoc.v:168998.3-169037.6" + wire width 4 $0\src12__data_o$next[3:0]$10967 + attribute \src "libresoc.v:168996.3-168997.43" + wire width 4 $0\src12__data_o[3:0] + attribute \src "libresoc.v:169095.3-169134.6" + wire width 4 $0\src22__data_o$next[3:0]$10982 + attribute \src "libresoc.v:168994.3-168995.43" + wire width 4 $0\src22__data_o[3:0] + attribute \src "libresoc.v:169165.3-169204.6" + wire width 4 $0\src32__data_o$next[3:0]$10996 + attribute \src "libresoc.v:168992.3-168993.43" + wire width 4 $0\src32__data_o[3:0] + attribute \src "libresoc.v:169275.3-169304.6" + wire $0\wr_detect$10[0:0]$11018 + attribute \src "libresoc.v:169345.3-169374.6" + wire $0\wr_detect$13[0:0]$11032 + attribute \src "libresoc.v:169135.3-169164.6" + wire $0\wr_detect$4[0:0]$10990 + attribute \src "libresoc.v:169205.3-169234.6" + wire $0\wr_detect$7[0:0]$11004 + attribute \src "libresoc.v:169038.3-169067.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:169305.3-169344.6" + wire width 4 $1\r22__data_o$next[3:0]$11025 + attribute \src "libresoc.v:168930.13-168930.31" + wire width 4 $1\r22__data_o[3:0] + attribute \src "libresoc.v:169235.3-169274.6" + wire width 4 $1\r2__data_o$next[3:0]$11011 + attribute \src "libresoc.v:168937.13-168937.30" + wire width 4 $1\r2__data_o[3:0] + attribute \src "libresoc.v:169068.3-169094.6" + wire width 4 $1\reg$next[3:0]$10977 + attribute \src "libresoc.v:168943.13-168943.25" + wire width 4 $1\reg[3:0] + attribute \src "libresoc.v:168998.3-169037.6" + wire width 4 $1\src12__data_o$next[3:0]$10968 + attribute \src "libresoc.v:168948.13-168948.33" + wire width 4 $1\src12__data_o[3:0] + attribute \src "libresoc.v:169095.3-169134.6" + wire width 4 $1\src22__data_o$next[3:0]$10983 + attribute \src "libresoc.v:168955.13-168955.33" + wire width 4 $1\src22__data_o[3:0] + attribute \src "libresoc.v:169165.3-169204.6" + wire width 4 $1\src32__data_o$next[3:0]$10997 + attribute \src "libresoc.v:168962.13-168962.33" + wire width 4 $1\src32__data_o[3:0] + attribute \src "libresoc.v:169275.3-169304.6" + wire $1\wr_detect$10[0:0]$11019 + attribute \src "libresoc.v:169345.3-169374.6" + wire $1\wr_detect$13[0:0]$11033 + attribute \src "libresoc.v:169135.3-169164.6" + wire $1\wr_detect$4[0:0]$10991 + attribute \src "libresoc.v:169205.3-169234.6" + wire $1\wr_detect$7[0:0]$11005 + attribute \src "libresoc.v:169038.3-169067.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:169305.3-169344.6" + wire width 4 $2\r22__data_o$next[3:0]$11026 + attribute \src "libresoc.v:169235.3-169274.6" + wire width 4 $2\r2__data_o$next[3:0]$11012 + attribute \src "libresoc.v:169068.3-169094.6" + wire width 4 $2\reg$next[3:0]$10978 + attribute \src "libresoc.v:168998.3-169037.6" + wire width 4 $2\src12__data_o$next[3:0]$10969 + attribute \src "libresoc.v:169095.3-169134.6" + wire width 4 $2\src22__data_o$next[3:0]$10984 + attribute \src "libresoc.v:169165.3-169204.6" + wire width 4 $2\src32__data_o$next[3:0]$10998 + attribute \src "libresoc.v:169275.3-169304.6" + wire $2\wr_detect$10[0:0]$11020 + attribute \src "libresoc.v:169345.3-169374.6" + wire $2\wr_detect$13[0:0]$11034 + attribute \src "libresoc.v:169135.3-169164.6" + wire $2\wr_detect$4[0:0]$10992 + attribute \src "libresoc.v:169205.3-169234.6" + wire $2\wr_detect$7[0:0]$11006 + attribute \src "libresoc.v:169038.3-169067.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:169305.3-169344.6" + wire width 4 $3\r22__data_o$next[3:0]$11027 + attribute \src "libresoc.v:169235.3-169274.6" + wire width 4 $3\r2__data_o$next[3:0]$11013 + attribute \src "libresoc.v:169068.3-169094.6" + wire width 4 $3\reg$next[3:0]$10979 + attribute \src "libresoc.v:168998.3-169037.6" + wire width 4 $3\src12__data_o$next[3:0]$10970 + attribute \src "libresoc.v:169095.3-169134.6" + wire width 4 $3\src22__data_o$next[3:0]$10985 + attribute \src "libresoc.v:169165.3-169204.6" + wire width 4 $3\src32__data_o$next[3:0]$10999 + attribute \src "libresoc.v:169275.3-169304.6" + wire $3\wr_detect$10[0:0]$11021 + attribute \src "libresoc.v:169345.3-169374.6" + wire $3\wr_detect$13[0:0]$11035 + attribute \src "libresoc.v:169135.3-169164.6" + wire $3\wr_detect$4[0:0]$10993 + attribute \src "libresoc.v:169205.3-169234.6" + wire $3\wr_detect$7[0:0]$11007 + attribute \src "libresoc.v:169038.3-169067.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:169305.3-169344.6" + wire width 4 $4\r22__data_o$next[3:0]$11028 + attribute \src "libresoc.v:169235.3-169274.6" + wire width 4 $4\r2__data_o$next[3:0]$11014 + attribute \src "libresoc.v:169068.3-169094.6" + wire width 4 $4\reg$next[3:0]$10980 + attribute \src "libresoc.v:168998.3-169037.6" + wire width 4 $4\src12__data_o$next[3:0]$10971 + attribute \src "libresoc.v:169095.3-169134.6" + wire width 4 $4\src22__data_o$next[3:0]$10986 + attribute \src "libresoc.v:169165.3-169204.6" + wire width 4 $4\src32__data_o$next[3:0]$11000 + attribute \src "libresoc.v:169275.3-169304.6" + wire $4\wr_detect$10[0:0]$11022 + attribute \src "libresoc.v:169345.3-169374.6" + wire $4\wr_detect$13[0:0]$11036 + attribute \src "libresoc.v:169135.3-169164.6" + wire $4\wr_detect$4[0:0]$10994 + attribute \src "libresoc.v:169205.3-169234.6" + wire $4\wr_detect$7[0:0]$11008 + attribute \src "libresoc.v:169038.3-169067.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:169305.3-169344.6" + wire width 4 $5\r22__data_o$next[3:0]$11029 + attribute \src "libresoc.v:169235.3-169274.6" + wire width 4 $5\r2__data_o$next[3:0]$11015 + attribute \src "libresoc.v:168998.3-169037.6" + wire width 4 $5\src12__data_o$next[3:0]$10972 + attribute \src "libresoc.v:169095.3-169134.6" + wire width 4 $5\src22__data_o$next[3:0]$10987 + attribute \src "libresoc.v:169165.3-169204.6" + wire width 4 $5\src32__data_o$next[3:0]$11001 + attribute \src "libresoc.v:169305.3-169344.6" + wire width 4 $6\r22__data_o$next[3:0]$11030 + attribute \src "libresoc.v:169235.3-169274.6" + wire width 4 $6\r2__data_o$next[3:0]$11016 + attribute \src "libresoc.v:168998.3-169037.6" + wire width 4 $6\src12__data_o$next[3:0]$10973 + attribute \src "libresoc.v:169095.3-169134.6" + wire width 4 $6\src22__data_o$next[3:0]$10988 + attribute \src "libresoc.v:169165.3-169204.6" + wire width 4 $6\src32__data_o$next[3:0]$11002 + attribute \src "libresoc.v:168981.17-168981.104" + wire $not$libresoc.v:168981$10955_Y + attribute \src "libresoc.v:168982.18-168982.105" + wire $not$libresoc.v:168982$10956_Y + attribute \src "libresoc.v:168983.17-168983.100" + wire $not$libresoc.v:168983$10957_Y + attribute \src "libresoc.v:168984.17-168984.103" + wire $not$libresoc.v:168984$10958_Y + attribute \src "libresoc.v:168985.17-168985.103" + wire $not$libresoc.v:168985$10959_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 9 \dest12__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \dest12__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 11 \dest22__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \dest22__wen + attribute \src "libresoc.v:168905.7-168905.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 14 \r22__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r22__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 15 \r22__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 12 \r2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r2__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 13 \r2__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 3 \src12__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src12__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \src12__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 5 \src22__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src22__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \src22__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 7 \src32__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src32__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \src32__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 16 \w2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 17 \w2__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:168981$10955 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:168981$10955_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:168982$10956 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$libresoc.v:168982$10956_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:168983$10957 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:168983$10957_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:168984$10958 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:168984$10958_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:168985$10959 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:168985$10959_Y + end + attribute \src "libresoc.v:168905.7-168905.20" + process $proc$libresoc.v:168905$11037 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:168930.13-168930.31" + process $proc$libresoc.v:168930$11038 + assign { } { } + assign $1\r22__data_o[3:0] 4'0000 + sync always + sync init + update \r22__data_o $1\r22__data_o[3:0] + end + attribute \src "libresoc.v:168937.13-168937.30" + process $proc$libresoc.v:168937$11039 + assign { } { } + assign $1\r2__data_o[3:0] 4'0000 + sync always + sync init + update \r2__data_o $1\r2__data_o[3:0] + end + attribute \src "libresoc.v:168943.13-168943.25" + process $proc$libresoc.v:168943$11040 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "libresoc.v:168948.13-168948.33" + process $proc$libresoc.v:168948$11041 + assign { } { } + assign $1\src12__data_o[3:0] 4'0000 + sync always + sync init + update \src12__data_o $1\src12__data_o[3:0] + end + attribute \src "libresoc.v:168955.13-168955.33" + process $proc$libresoc.v:168955$11042 + assign { } { } + assign $1\src22__data_o[3:0] 4'0000 + sync always + sync init + update \src22__data_o $1\src22__data_o[3:0] + end + attribute \src "libresoc.v:168962.13-168962.33" + process $proc$libresoc.v:168962$11043 + assign { } { } + assign $1\src32__data_o[3:0] 4'0000 + sync always + sync init + update \src32__data_o $1\src32__data_o[3:0] + end + attribute \src "libresoc.v:168986.3-168987.25" + process $proc$libresoc.v:168986$10960 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "libresoc.v:168988.3-168989.39" + process $proc$libresoc.v:168988$10961 + assign { } { } + assign $0\r22__data_o[3:0] \r22__data_o$next + sync posedge \coresync_clk + update \r22__data_o $0\r22__data_o[3:0] + end + attribute \src "libresoc.v:168990.3-168991.37" + process $proc$libresoc.v:168990$10962 + assign { } { } + assign $0\r2__data_o[3:0] \r2__data_o$next + sync posedge \coresync_clk + update \r2__data_o $0\r2__data_o[3:0] + end + attribute \src "libresoc.v:168992.3-168993.43" + process $proc$libresoc.v:168992$10963 + assign { } { } + assign $0\src32__data_o[3:0] \src32__data_o$next + sync posedge \coresync_clk + update \src32__data_o $0\src32__data_o[3:0] + end + attribute \src "libresoc.v:168994.3-168995.43" + process $proc$libresoc.v:168994$10964 + assign { } { } + assign $0\src22__data_o[3:0] \src22__data_o$next + sync posedge \coresync_clk + update \src22__data_o $0\src22__data_o[3:0] + end + attribute \src "libresoc.v:168996.3-168997.43" + process $proc$libresoc.v:168996$10965 + assign { } { } + assign $0\src12__data_o[3:0] \src12__data_o$next + sync posedge \coresync_clk + update \src12__data_o $0\src12__data_o[3:0] + end + attribute \src "libresoc.v:168998.3-169037.6" + process $proc$libresoc.v:168998$10966 + assign { } { } + assign { } { } + assign { } { } + assign $0\src12__data_o$next[3:0]$10967 $6\src12__data_o$next[3:0]$10973 + attribute \src "libresoc.v:168999.5-168999.29" + switch \initial + attribute \src "libresoc.v:168999.9-168999.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src12__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src12__data_o$next[3:0]$10968 $5\src12__data_o$next[3:0]$10972 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src12__data_o$next[3:0]$10969 \dest12__data_i + case + assign $2\src12__data_o$next[3:0]$10969 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src12__data_o$next[3:0]$10970 \dest22__data_i + case + assign $3\src12__data_o$next[3:0]$10970 $2\src12__data_o$next[3:0]$10969 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src12__data_o$next[3:0]$10971 \w2__data_i + case + assign $4\src12__data_o$next[3:0]$10971 $3\src12__data_o$next[3:0]$10970 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src12__data_o$next[3:0]$10972 \reg + case + assign $5\src12__data_o$next[3:0]$10972 $4\src12__data_o$next[3:0]$10971 + end + case + assign $1\src12__data_o$next[3:0]$10968 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src12__data_o$next[3:0]$10973 4'0000 + case + assign $6\src12__data_o$next[3:0]$10973 $1\src12__data_o$next[3:0]$10968 + end + sync always + update \src12__data_o$next $0\src12__data_o$next[3:0]$10967 + end + attribute \src "libresoc.v:169038.3-169067.6" + process $proc$libresoc.v:169038$10974 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:169039.5-169039.29" + switch \initial + attribute \src "libresoc.v:169039.9-169039.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src12__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:169068.3-169094.6" + process $proc$libresoc.v:169068$10975 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$10976 $4\reg$next[3:0]$10980 + attribute \src "libresoc.v:169069.5-169069.29" + switch \initial + attribute \src "libresoc.v:169069.9-169069.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$10977 \dest12__data_i + case + assign $1\reg$next[3:0]$10977 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$10978 \dest22__data_i + case + assign $2\reg$next[3:0]$10978 $1\reg$next[3:0]$10977 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$10979 \w2__data_i + case + assign $3\reg$next[3:0]$10979 $2\reg$next[3:0]$10978 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$10980 4'0000 + case + assign $4\reg$next[3:0]$10980 $3\reg$next[3:0]$10979 + end + sync always + update \reg$next $0\reg$next[3:0]$10976 + end + attribute \src "libresoc.v:169095.3-169134.6" + process $proc$libresoc.v:169095$10981 + assign { } { } + assign { } { } + assign { } { } + assign $0\src22__data_o$next[3:0]$10982 $6\src22__data_o$next[3:0]$10988 + attribute \src "libresoc.v:169096.5-169096.29" + switch \initial + attribute \src "libresoc.v:169096.9-169096.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src22__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src22__data_o$next[3:0]$10983 $5\src22__data_o$next[3:0]$10987 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src22__data_o$next[3:0]$10984 \dest12__data_i + case + assign $2\src22__data_o$next[3:0]$10984 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src22__data_o$next[3:0]$10985 \dest22__data_i + case + assign $3\src22__data_o$next[3:0]$10985 $2\src22__data_o$next[3:0]$10984 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src22__data_o$next[3:0]$10986 \w2__data_i + case + assign $4\src22__data_o$next[3:0]$10986 $3\src22__data_o$next[3:0]$10985 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src22__data_o$next[3:0]$10987 \reg + case + assign $5\src22__data_o$next[3:0]$10987 $4\src22__data_o$next[3:0]$10986 + end + case + assign $1\src22__data_o$next[3:0]$10983 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src22__data_o$next[3:0]$10988 4'0000 + case + assign $6\src22__data_o$next[3:0]$10988 $1\src22__data_o$next[3:0]$10983 + end + sync always + update \src22__data_o$next $0\src22__data_o$next[3:0]$10982 + end + attribute \src "libresoc.v:169135.3-169164.6" + process $proc$libresoc.v:169135$10989 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$10990 $1\wr_detect$4[0:0]$10991 + attribute \src "libresoc.v:169136.5-169136.29" + switch \initial + attribute \src "libresoc.v:169136.9-169136.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src22__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$10991 $4\wr_detect$4[0:0]$10994 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$10992 1'1 + case + assign $2\wr_detect$4[0:0]$10992 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$10993 1'1 + case + assign $3\wr_detect$4[0:0]$10993 $2\wr_detect$4[0:0]$10992 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$10994 1'1 + case + assign $4\wr_detect$4[0:0]$10994 $3\wr_detect$4[0:0]$10993 + end + case + assign $1\wr_detect$4[0:0]$10991 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$10990 + end + attribute \src "libresoc.v:169165.3-169204.6" + process $proc$libresoc.v:169165$10995 + assign { } { } + assign { } { } + assign { } { } + assign $0\src32__data_o$next[3:0]$10996 $6\src32__data_o$next[3:0]$11002 + attribute \src "libresoc.v:169166.5-169166.29" + switch \initial + attribute \src "libresoc.v:169166.9-169166.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src32__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src32__data_o$next[3:0]$10997 $5\src32__data_o$next[3:0]$11001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src32__data_o$next[3:0]$10998 \dest12__data_i + case + assign $2\src32__data_o$next[3:0]$10998 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src32__data_o$next[3:0]$10999 \dest22__data_i + case + assign $3\src32__data_o$next[3:0]$10999 $2\src32__data_o$next[3:0]$10998 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src32__data_o$next[3:0]$11000 \w2__data_i + case + assign $4\src32__data_o$next[3:0]$11000 $3\src32__data_o$next[3:0]$10999 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src32__data_o$next[3:0]$11001 \reg + case + assign $5\src32__data_o$next[3:0]$11001 $4\src32__data_o$next[3:0]$11000 + end + case + assign $1\src32__data_o$next[3:0]$10997 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src32__data_o$next[3:0]$11002 4'0000 + case + assign $6\src32__data_o$next[3:0]$11002 $1\src32__data_o$next[3:0]$10997 + end + sync always + update \src32__data_o$next $0\src32__data_o$next[3:0]$10996 + end + attribute \src "libresoc.v:169205.3-169234.6" + process $proc$libresoc.v:169205$11003 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$11004 $1\wr_detect$7[0:0]$11005 + attribute \src "libresoc.v:169206.5-169206.29" + switch \initial + attribute \src "libresoc.v:169206.9-169206.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src32__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$11005 $4\wr_detect$7[0:0]$11008 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$11006 1'1 + case + assign $2\wr_detect$7[0:0]$11006 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$11007 1'1 + case + assign $3\wr_detect$7[0:0]$11007 $2\wr_detect$7[0:0]$11006 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$11008 1'1 + case + assign $4\wr_detect$7[0:0]$11008 $3\wr_detect$7[0:0]$11007 + end + case + assign $1\wr_detect$7[0:0]$11005 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$11004 + end + attribute \src "libresoc.v:169235.3-169274.6" + process $proc$libresoc.v:169235$11009 + assign { } { } + assign { } { } + assign { } { } + assign $0\r2__data_o$next[3:0]$11010 $6\r2__data_o$next[3:0]$11016 + attribute \src "libresoc.v:169236.5-169236.29" + switch \initial + attribute \src "libresoc.v:169236.9-169236.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r2__data_o$next[3:0]$11011 $5\r2__data_o$next[3:0]$11015 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r2__data_o$next[3:0]$11012 \dest12__data_i + case + assign $2\r2__data_o$next[3:0]$11012 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r2__data_o$next[3:0]$11013 \dest22__data_i + case + assign $3\r2__data_o$next[3:0]$11013 $2\r2__data_o$next[3:0]$11012 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r2__data_o$next[3:0]$11014 \w2__data_i + case + assign $4\r2__data_o$next[3:0]$11014 $3\r2__data_o$next[3:0]$11013 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r2__data_o$next[3:0]$11015 \reg + case + assign $5\r2__data_o$next[3:0]$11015 $4\r2__data_o$next[3:0]$11014 + end + case + assign $1\r2__data_o$next[3:0]$11011 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r2__data_o$next[3:0]$11016 4'0000 + case + assign $6\r2__data_o$next[3:0]$11016 $1\r2__data_o$next[3:0]$11011 + end + sync always + update \r2__data_o$next $0\r2__data_o$next[3:0]$11010 + end + attribute \src "libresoc.v:169275.3-169304.6" + process $proc$libresoc.v:169275$11017 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$11018 $1\wr_detect$10[0:0]$11019 + attribute \src "libresoc.v:169276.5-169276.29" + switch \initial + attribute \src "libresoc.v:169276.9-169276.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$11019 $4\wr_detect$10[0:0]$11022 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$11020 1'1 + case + assign $2\wr_detect$10[0:0]$11020 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$11021 1'1 + case + assign $3\wr_detect$10[0:0]$11021 $2\wr_detect$10[0:0]$11020 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$11022 1'1 + case + assign $4\wr_detect$10[0:0]$11022 $3\wr_detect$10[0:0]$11021 + end + case + assign $1\wr_detect$10[0:0]$11019 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$11018 + end + attribute \src "libresoc.v:169305.3-169344.6" + process $proc$libresoc.v:169305$11023 + assign { } { } + assign { } { } + assign { } { } + assign $0\r22__data_o$next[3:0]$11024 $6\r22__data_o$next[3:0]$11030 + attribute \src "libresoc.v:169306.5-169306.29" + switch \initial + attribute \src "libresoc.v:169306.9-169306.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r22__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r22__data_o$next[3:0]$11025 $5\r22__data_o$next[3:0]$11029 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r22__data_o$next[3:0]$11026 \dest12__data_i + case + assign $2\r22__data_o$next[3:0]$11026 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r22__data_o$next[3:0]$11027 \dest22__data_i + case + assign $3\r22__data_o$next[3:0]$11027 $2\r22__data_o$next[3:0]$11026 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r22__data_o$next[3:0]$11028 \w2__data_i + case + assign $4\r22__data_o$next[3:0]$11028 $3\r22__data_o$next[3:0]$11027 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r22__data_o$next[3:0]$11029 \reg + case + assign $5\r22__data_o$next[3:0]$11029 $4\r22__data_o$next[3:0]$11028 + end + case + assign $1\r22__data_o$next[3:0]$11025 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r22__data_o$next[3:0]$11030 4'0000 + case + assign $6\r22__data_o$next[3:0]$11030 $1\r22__data_o$next[3:0]$11025 + end + sync always + update \r22__data_o$next $0\r22__data_o$next[3:0]$11024 + end + attribute \src "libresoc.v:169345.3-169374.6" + process $proc$libresoc.v:169345$11031 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$11032 $1\wr_detect$13[0:0]$11033 + attribute \src "libresoc.v:169346.5-169346.29" + switch \initial + attribute \src "libresoc.v:169346.9-169346.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r22__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$11033 $4\wr_detect$13[0:0]$11036 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$11034 1'1 + case + assign $2\wr_detect$13[0:0]$11034 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$11035 1'1 + case + assign $3\wr_detect$13[0:0]$11035 $2\wr_detect$13[0:0]$11034 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$11036 1'1 + case + assign $4\wr_detect$13[0:0]$11036 $3\wr_detect$13[0:0]$11035 + end + case + assign $1\wr_detect$13[0:0]$11033 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$11032 + end + connect \$9 $not$libresoc.v:168981$10955_Y + connect \$12 $not$libresoc.v:168982$10956_Y + connect \$1 $not$libresoc.v:168983$10957_Y + connect \$3 $not$libresoc.v:168984$10958_Y + connect \$6 $not$libresoc.v:168985$10959_Y +end +attribute \src "libresoc.v:169379.1-169824.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_2" +attribute \generator "nMigen" +module \reg_2$134 + attribute \src "libresoc.v:169380.7-169380.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:169709.3-169754.6" + wire width 2 $0\r2__data_o$next[1:0]$11096 + attribute \src "libresoc.v:169455.3-169456.37" + wire width 2 $0\r2__data_o[1:0] + attribute \src "libresoc.v:169791.3-169823.6" + wire width 2 $0\reg$next[1:0]$11112 + attribute \src "libresoc.v:169453.3-169454.25" + wire width 2 $0\reg[1:0] + attribute \src "libresoc.v:169463.3-169508.6" + wire width 2 $0\src12__data_o$next[1:0]$11054 + attribute \src "libresoc.v:169461.3-169462.43" + wire width 2 $0\src12__data_o[1:0] + attribute \src "libresoc.v:169545.3-169590.6" + wire width 2 $0\src22__data_o$next[1:0]$11064 + attribute \src "libresoc.v:169459.3-169460.43" + wire width 2 $0\src22__data_o[1:0] + attribute \src "libresoc.v:169627.3-169672.6" + wire width 2 $0\src32__data_o$next[1:0]$11080 + attribute \src "libresoc.v:169457.3-169458.43" + wire width 2 $0\src32__data_o[1:0] + attribute \src "libresoc.v:169755.3-169790.6" + wire $0\wr_detect$10[0:0]$11105 + attribute \src "libresoc.v:169591.3-169626.6" + wire $0\wr_detect$4[0:0]$11073 + attribute \src "libresoc.v:169673.3-169708.6" + wire $0\wr_detect$7[0:0]$11089 + attribute \src "libresoc.v:169509.3-169544.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:169709.3-169754.6" + wire width 2 $1\r2__data_o$next[1:0]$11097 + attribute \src "libresoc.v:169407.13-169407.30" + wire width 2 $1\r2__data_o[1:0] + attribute \src "libresoc.v:169791.3-169823.6" + wire width 2 $1\reg$next[1:0]$11113 + attribute \src "libresoc.v:169413.13-169413.25" + wire width 2 $1\reg[1:0] + attribute \src "libresoc.v:169463.3-169508.6" + wire width 2 $1\src12__data_o$next[1:0]$11055 + attribute \src "libresoc.v:169418.13-169418.33" + wire width 2 $1\src12__data_o[1:0] + attribute \src "libresoc.v:169545.3-169590.6" + wire width 2 $1\src22__data_o$next[1:0]$11065 + attribute \src "libresoc.v:169425.13-169425.33" + wire width 2 $1\src22__data_o[1:0] + attribute \src "libresoc.v:169627.3-169672.6" + wire width 2 $1\src32__data_o$next[1:0]$11081 + attribute \src "libresoc.v:169432.13-169432.33" + wire width 2 $1\src32__data_o[1:0] + attribute \src "libresoc.v:169755.3-169790.6" + wire $1\wr_detect$10[0:0]$11106 + attribute \src "libresoc.v:169591.3-169626.6" + wire $1\wr_detect$4[0:0]$11074 + attribute \src "libresoc.v:169673.3-169708.6" + wire $1\wr_detect$7[0:0]$11090 + attribute \src "libresoc.v:169509.3-169544.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:169709.3-169754.6" + wire width 2 $2\r2__data_o$next[1:0]$11098 + attribute \src "libresoc.v:169791.3-169823.6" + wire width 2 $2\reg$next[1:0]$11114 + attribute \src "libresoc.v:169463.3-169508.6" + wire width 2 $2\src12__data_o$next[1:0]$11056 + attribute \src "libresoc.v:169545.3-169590.6" + wire width 2 $2\src22__data_o$next[1:0]$11066 + attribute \src "libresoc.v:169627.3-169672.6" + wire width 2 $2\src32__data_o$next[1:0]$11082 + attribute \src "libresoc.v:169755.3-169790.6" + wire $2\wr_detect$10[0:0]$11107 + attribute \src "libresoc.v:169591.3-169626.6" + wire $2\wr_detect$4[0:0]$11075 + attribute \src "libresoc.v:169673.3-169708.6" + wire $2\wr_detect$7[0:0]$11091 + attribute \src "libresoc.v:169509.3-169544.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:169709.3-169754.6" + wire width 2 $3\r2__data_o$next[1:0]$11099 + attribute \src "libresoc.v:169791.3-169823.6" + wire width 2 $3\reg$next[1:0]$11115 + attribute \src "libresoc.v:169463.3-169508.6" + wire width 2 $3\src12__data_o$next[1:0]$11057 + attribute \src "libresoc.v:169545.3-169590.6" + wire width 2 $3\src22__data_o$next[1:0]$11067 + attribute \src "libresoc.v:169627.3-169672.6" + wire width 2 $3\src32__data_o$next[1:0]$11083 + attribute \src "libresoc.v:169755.3-169790.6" + wire $3\wr_detect$10[0:0]$11108 + attribute \src "libresoc.v:169591.3-169626.6" + wire $3\wr_detect$4[0:0]$11076 + attribute \src "libresoc.v:169673.3-169708.6" + wire $3\wr_detect$7[0:0]$11092 + attribute \src "libresoc.v:169509.3-169544.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:169709.3-169754.6" + wire width 2 $4\r2__data_o$next[1:0]$11100 + attribute \src "libresoc.v:169791.3-169823.6" + wire width 2 $4\reg$next[1:0]$11116 + attribute \src "libresoc.v:169463.3-169508.6" + wire width 2 $4\src12__data_o$next[1:0]$11058 + attribute \src "libresoc.v:169545.3-169590.6" + wire width 2 $4\src22__data_o$next[1:0]$11068 + attribute \src "libresoc.v:169627.3-169672.6" + wire width 2 $4\src32__data_o$next[1:0]$11084 + attribute \src "libresoc.v:169755.3-169790.6" + wire $4\wr_detect$10[0:0]$11109 + attribute \src "libresoc.v:169591.3-169626.6" + wire $4\wr_detect$4[0:0]$11077 + attribute \src "libresoc.v:169673.3-169708.6" + wire $4\wr_detect$7[0:0]$11093 + attribute \src "libresoc.v:169509.3-169544.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:169709.3-169754.6" + wire width 2 $5\r2__data_o$next[1:0]$11101 + attribute \src "libresoc.v:169791.3-169823.6" + wire width 2 $5\reg$next[1:0]$11117 + attribute \src "libresoc.v:169463.3-169508.6" + wire width 2 $5\src12__data_o$next[1:0]$11059 + attribute \src "libresoc.v:169545.3-169590.6" + wire width 2 $5\src22__data_o$next[1:0]$11069 + attribute \src "libresoc.v:169627.3-169672.6" + wire width 2 $5\src32__data_o$next[1:0]$11085 + attribute \src "libresoc.v:169755.3-169790.6" + wire $5\wr_detect$10[0:0]$11110 + attribute \src "libresoc.v:169591.3-169626.6" + wire $5\wr_detect$4[0:0]$11078 + attribute \src "libresoc.v:169673.3-169708.6" + wire $5\wr_detect$7[0:0]$11094 + attribute \src "libresoc.v:169509.3-169544.6" + wire $5\wr_detect[0:0] + attribute \src "libresoc.v:169709.3-169754.6" + wire width 2 $6\r2__data_o$next[1:0]$11102 + attribute \src "libresoc.v:169463.3-169508.6" + wire width 2 $6\src12__data_o$next[1:0]$11060 + attribute \src "libresoc.v:169545.3-169590.6" + wire width 2 $6\src22__data_o$next[1:0]$11070 + attribute \src "libresoc.v:169627.3-169672.6" + wire width 2 $6\src32__data_o$next[1:0]$11086 + attribute \src "libresoc.v:169709.3-169754.6" + wire width 2 $7\r2__data_o$next[1:0]$11103 + attribute \src "libresoc.v:169463.3-169508.6" + wire width 2 $7\src12__data_o$next[1:0]$11061 + attribute \src "libresoc.v:169545.3-169590.6" + wire width 2 $7\src22__data_o$next[1:0]$11071 + attribute \src "libresoc.v:169627.3-169672.6" + wire width 2 $7\src32__data_o$next[1:0]$11087 + attribute \src "libresoc.v:169449.17-169449.104" + wire $not$libresoc.v:169449$11044_Y + attribute \src "libresoc.v:169450.17-169450.100" + wire $not$libresoc.v:169450$11045_Y + attribute \src "libresoc.v:169451.17-169451.103" + wire $not$libresoc.v:169451$11046_Y + attribute \src "libresoc.v:169452.17-169452.103" + wire $not$libresoc.v:169452$11047_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 9 \dest12__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \dest12__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 11 \dest22__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \dest22__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 13 \dest32__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 12 \dest32__wen + attribute \src "libresoc.v:169380.7-169380.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 14 \r2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \r2__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 15 \r2__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 2 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 2 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 3 \src12__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \src12__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \src12__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 5 \src22__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \src22__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \src22__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 7 \src32__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \src32__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \src32__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 16 \w2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 17 \w2__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:169449$11044 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:169449$11044_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:169450$11045 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:169450$11045_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:169451$11046 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:169451$11046_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:169452$11047 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:169452$11047_Y + end + attribute \src "libresoc.v:169380.7-169380.20" + process $proc$libresoc.v:169380$11118 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:169407.13-169407.30" + process $proc$libresoc.v:169407$11119 + assign { } { } + assign $1\r2__data_o[1:0] 2'00 + sync always + sync init + update \r2__data_o $1\r2__data_o[1:0] + end + attribute \src "libresoc.v:169413.13-169413.25" + process $proc$libresoc.v:169413$11120 + assign { } { } + assign $1\reg[1:0] 2'00 + sync always + sync init + update \reg $1\reg[1:0] + end + attribute \src "libresoc.v:169418.13-169418.33" + process $proc$libresoc.v:169418$11121 + assign { } { } + assign $1\src12__data_o[1:0] 2'00 + sync always + sync init + update \src12__data_o $1\src12__data_o[1:0] + end + attribute \src "libresoc.v:169425.13-169425.33" + process $proc$libresoc.v:169425$11122 + assign { } { } + assign $1\src22__data_o[1:0] 2'00 + sync always + sync init + update \src22__data_o $1\src22__data_o[1:0] + end + attribute \src "libresoc.v:169432.13-169432.33" + process $proc$libresoc.v:169432$11123 + assign { } { } + assign $1\src32__data_o[1:0] 2'00 + sync always + sync init + update \src32__data_o $1\src32__data_o[1:0] + end + attribute \src "libresoc.v:169453.3-169454.25" + process $proc$libresoc.v:169453$11048 + assign { } { } + assign $0\reg[1:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[1:0] + end + attribute \src "libresoc.v:169455.3-169456.37" + process $proc$libresoc.v:169455$11049 + assign { } { } + assign $0\r2__data_o[1:0] \r2__data_o$next + sync posedge \coresync_clk + update \r2__data_o $0\r2__data_o[1:0] + end + attribute \src "libresoc.v:169457.3-169458.43" + process $proc$libresoc.v:169457$11050 + assign { } { } + assign $0\src32__data_o[1:0] \src32__data_o$next + sync posedge \coresync_clk + update \src32__data_o $0\src32__data_o[1:0] + end + attribute \src "libresoc.v:169459.3-169460.43" + process $proc$libresoc.v:169459$11051 + assign { } { } + assign $0\src22__data_o[1:0] \src22__data_o$next + sync posedge \coresync_clk + update \src22__data_o $0\src22__data_o[1:0] + end + attribute \src "libresoc.v:169461.3-169462.43" + process $proc$libresoc.v:169461$11052 + assign { } { } + assign $0\src12__data_o[1:0] \src12__data_o$next + sync posedge \coresync_clk + update \src12__data_o $0\src12__data_o[1:0] + end + attribute \src "libresoc.v:169463.3-169508.6" + process $proc$libresoc.v:169463$11053 + assign { } { } + assign { } { } + assign { } { } + assign $0\src12__data_o$next[1:0]$11054 $7\src12__data_o$next[1:0]$11061 + attribute \src "libresoc.v:169464.5-169464.29" + switch \initial + attribute \src "libresoc.v:169464.9-169464.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src12__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src12__data_o$next[1:0]$11055 $6\src12__data_o$next[1:0]$11060 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src12__data_o$next[1:0]$11056 \dest12__data_i + case + assign $2\src12__data_o$next[1:0]$11056 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src12__data_o$next[1:0]$11057 \dest22__data_i + case + assign $3\src12__data_o$next[1:0]$11057 $2\src12__data_o$next[1:0]$11056 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src12__data_o$next[1:0]$11058 \dest32__data_i + case + assign $4\src12__data_o$next[1:0]$11058 $3\src12__data_o$next[1:0]$11057 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src12__data_o$next[1:0]$11059 \w2__data_i + case + assign $5\src12__data_o$next[1:0]$11059 $4\src12__data_o$next[1:0]$11058 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src12__data_o$next[1:0]$11060 \reg + case + assign $6\src12__data_o$next[1:0]$11060 $5\src12__data_o$next[1:0]$11059 + end + case + assign $1\src12__data_o$next[1:0]$11055 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src12__data_o$next[1:0]$11061 2'00 + case + assign $7\src12__data_o$next[1:0]$11061 $1\src12__data_o$next[1:0]$11055 + end + sync always + update \src12__data_o$next $0\src12__data_o$next[1:0]$11054 + end + attribute \src "libresoc.v:169509.3-169544.6" + process $proc$libresoc.v:169509$11062 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:169510.5-169510.29" + switch \initial + attribute \src "libresoc.v:169510.9-169510.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src12__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $5\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect[0:0] 1'1 + case + assign $5\wr_detect[0:0] $4\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:169545.3-169590.6" + process $proc$libresoc.v:169545$11063 + assign { } { } + assign { } { } + assign { } { } + assign $0\src22__data_o$next[1:0]$11064 $7\src22__data_o$next[1:0]$11071 + attribute \src "libresoc.v:169546.5-169546.29" + switch \initial + attribute \src "libresoc.v:169546.9-169546.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src22__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src22__data_o$next[1:0]$11065 $6\src22__data_o$next[1:0]$11070 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src22__data_o$next[1:0]$11066 \dest12__data_i + case + assign $2\src22__data_o$next[1:0]$11066 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src22__data_o$next[1:0]$11067 \dest22__data_i + case + assign $3\src22__data_o$next[1:0]$11067 $2\src22__data_o$next[1:0]$11066 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src22__data_o$next[1:0]$11068 \dest32__data_i + case + assign $4\src22__data_o$next[1:0]$11068 $3\src22__data_o$next[1:0]$11067 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src22__data_o$next[1:0]$11069 \w2__data_i + case + assign $5\src22__data_o$next[1:0]$11069 $4\src22__data_o$next[1:0]$11068 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src22__data_o$next[1:0]$11070 \reg + case + assign $6\src22__data_o$next[1:0]$11070 $5\src22__data_o$next[1:0]$11069 + end + case + assign $1\src22__data_o$next[1:0]$11065 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src22__data_o$next[1:0]$11071 2'00 + case + assign $7\src22__data_o$next[1:0]$11071 $1\src22__data_o$next[1:0]$11065 + end + sync always + update \src22__data_o$next $0\src22__data_o$next[1:0]$11064 + end + attribute \src "libresoc.v:169591.3-169626.6" + process $proc$libresoc.v:169591$11072 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$11073 $1\wr_detect$4[0:0]$11074 + attribute \src "libresoc.v:169592.5-169592.29" + switch \initial + attribute \src "libresoc.v:169592.9-169592.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src22__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$11074 $5\wr_detect$4[0:0]$11078 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$11075 1'1 + case + assign $2\wr_detect$4[0:0]$11075 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$11076 1'1 + case + assign $3\wr_detect$4[0:0]$11076 $2\wr_detect$4[0:0]$11075 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$11077 1'1 + case + assign $4\wr_detect$4[0:0]$11077 $3\wr_detect$4[0:0]$11076 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$4[0:0]$11078 1'1 + case + assign $5\wr_detect$4[0:0]$11078 $4\wr_detect$4[0:0]$11077 + end + case + assign $1\wr_detect$4[0:0]$11074 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$11073 + end + attribute \src "libresoc.v:169627.3-169672.6" + process $proc$libresoc.v:169627$11079 + assign { } { } + assign { } { } + assign { } { } + assign $0\src32__data_o$next[1:0]$11080 $7\src32__data_o$next[1:0]$11087 + attribute \src "libresoc.v:169628.5-169628.29" + switch \initial + attribute \src "libresoc.v:169628.9-169628.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src32__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src32__data_o$next[1:0]$11081 $6\src32__data_o$next[1:0]$11086 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src32__data_o$next[1:0]$11082 \dest12__data_i + case + assign $2\src32__data_o$next[1:0]$11082 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src32__data_o$next[1:0]$11083 \dest22__data_i + case + assign $3\src32__data_o$next[1:0]$11083 $2\src32__data_o$next[1:0]$11082 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src32__data_o$next[1:0]$11084 \dest32__data_i + case + assign $4\src32__data_o$next[1:0]$11084 $3\src32__data_o$next[1:0]$11083 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src32__data_o$next[1:0]$11085 \w2__data_i + case + assign $5\src32__data_o$next[1:0]$11085 $4\src32__data_o$next[1:0]$11084 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src32__data_o$next[1:0]$11086 \reg + case + assign $6\src32__data_o$next[1:0]$11086 $5\src32__data_o$next[1:0]$11085 + end + case + assign $1\src32__data_o$next[1:0]$11081 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src32__data_o$next[1:0]$11087 2'00 + case + assign $7\src32__data_o$next[1:0]$11087 $1\src32__data_o$next[1:0]$11081 + end + sync always + update \src32__data_o$next $0\src32__data_o$next[1:0]$11080 + end + attribute \src "libresoc.v:169673.3-169708.6" + process $proc$libresoc.v:169673$11088 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$11089 $1\wr_detect$7[0:0]$11090 + attribute \src "libresoc.v:169674.5-169674.29" + switch \initial + attribute \src "libresoc.v:169674.9-169674.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src32__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$11090 $5\wr_detect$7[0:0]$11094 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$11091 1'1 + case + assign $2\wr_detect$7[0:0]$11091 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$11092 1'1 + case + assign $3\wr_detect$7[0:0]$11092 $2\wr_detect$7[0:0]$11091 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$11093 1'1 + case + assign $4\wr_detect$7[0:0]$11093 $3\wr_detect$7[0:0]$11092 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$7[0:0]$11094 1'1 + case + assign $5\wr_detect$7[0:0]$11094 $4\wr_detect$7[0:0]$11093 + end + case + assign $1\wr_detect$7[0:0]$11090 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$11089 + end + attribute \src "libresoc.v:169709.3-169754.6" + process $proc$libresoc.v:169709$11095 + assign { } { } + assign { } { } + assign { } { } + assign $0\r2__data_o$next[1:0]$11096 $7\r2__data_o$next[1:0]$11103 + attribute \src "libresoc.v:169710.5-169710.29" + switch \initial + attribute \src "libresoc.v:169710.9-169710.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r2__data_o$next[1:0]$11097 $6\r2__data_o$next[1:0]$11102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r2__data_o$next[1:0]$11098 \dest12__data_i + case + assign $2\r2__data_o$next[1:0]$11098 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r2__data_o$next[1:0]$11099 \dest22__data_i + case + assign $3\r2__data_o$next[1:0]$11099 $2\r2__data_o$next[1:0]$11098 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r2__data_o$next[1:0]$11100 \dest32__data_i + case + assign $4\r2__data_o$next[1:0]$11100 $3\r2__data_o$next[1:0]$11099 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r2__data_o$next[1:0]$11101 \w2__data_i + case + assign $5\r2__data_o$next[1:0]$11101 $4\r2__data_o$next[1:0]$11100 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r2__data_o$next[1:0]$11102 \reg + case + assign $6\r2__data_o$next[1:0]$11102 $5\r2__data_o$next[1:0]$11101 + end + case + assign $1\r2__data_o$next[1:0]$11097 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\r2__data_o$next[1:0]$11103 2'00 + case + assign $7\r2__data_o$next[1:0]$11103 $1\r2__data_o$next[1:0]$11097 + end + sync always + update \r2__data_o$next $0\r2__data_o$next[1:0]$11096 + end + attribute \src "libresoc.v:169755.3-169790.6" + process $proc$libresoc.v:169755$11104 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$11105 $1\wr_detect$10[0:0]$11106 + attribute \src "libresoc.v:169756.5-169756.29" + switch \initial + attribute \src "libresoc.v:169756.9-169756.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$11106 $5\wr_detect$10[0:0]$11110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$11107 1'1 + case + assign $2\wr_detect$10[0:0]$11107 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$11108 1'1 + case + assign $3\wr_detect$10[0:0]$11108 $2\wr_detect$10[0:0]$11107 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$11109 1'1 + case + assign $4\wr_detect$10[0:0]$11109 $3\wr_detect$10[0:0]$11108 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$10[0:0]$11110 1'1 + case + assign $5\wr_detect$10[0:0]$11110 $4\wr_detect$10[0:0]$11109 + end + case + assign $1\wr_detect$10[0:0]$11106 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$11105 + end + attribute \src "libresoc.v:169791.3-169823.6" + process $proc$libresoc.v:169791$11111 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[1:0]$11112 $5\reg$next[1:0]$11117 + attribute \src "libresoc.v:169792.5-169792.29" + switch \initial + attribute \src "libresoc.v:169792.9-169792.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[1:0]$11113 \dest12__data_i + case + assign $1\reg$next[1:0]$11113 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[1:0]$11114 \dest22__data_i + case + assign $2\reg$next[1:0]$11114 $1\reg$next[1:0]$11113 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[1:0]$11115 \dest32__data_i + case + assign $3\reg$next[1:0]$11115 $2\reg$next[1:0]$11114 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[1:0]$11116 \w2__data_i + case + assign $4\reg$next[1:0]$11116 $3\reg$next[1:0]$11115 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\reg$next[1:0]$11117 2'00 + case + assign $5\reg$next[1:0]$11117 $4\reg$next[1:0]$11116 + end + sync always + update \reg$next $0\reg$next[1:0]$11112 + end + connect \$9 $not$libresoc.v:169449$11044_Y + connect \$1 $not$libresoc.v:169450$11045_Y + connect \$3 $not$libresoc.v:169451$11046_Y + connect \$6 $not$libresoc.v:169452$11047_Y +end +attribute \src "libresoc.v:169828.1-170047.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_2" +attribute \generator "nMigen" +module \reg_2$137 + attribute \src "libresoc.v:169880.3-169919.6" + wire width 64 $0\cia2__data_o$next[63:0]$11130 + attribute \src "libresoc.v:169878.3-169879.41" + wire width 64 $0\cia2__data_o[63:0] + attribute \src "libresoc.v:169829.7-169829.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:169950.3-169989.6" + wire width 64 $0\msr2__data_o$next[63:0]$11139 + attribute \src "libresoc.v:169876.3-169877.41" + wire width 64 $0\msr2__data_o[63:0] + attribute \src "libresoc.v:170020.3-170046.6" + wire width 64 $0\reg$next[63:0]$11153 + attribute \src "libresoc.v:169874.3-169875.25" + wire width 64 $0\reg[63:0] + attribute \src "libresoc.v:169990.3-170019.6" + wire $0\wr_detect$4[0:0]$11147 + attribute \src "libresoc.v:169920.3-169949.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:169880.3-169919.6" + wire width 64 $1\cia2__data_o$next[63:0]$11131 + attribute \src "libresoc.v:169836.14-169836.49" + wire width 64 $1\cia2__data_o[63:0] + attribute \src "libresoc.v:169950.3-169989.6" + wire width 64 $1\msr2__data_o$next[63:0]$11140 + attribute \src "libresoc.v:169853.14-169853.49" + wire width 64 $1\msr2__data_o[63:0] + attribute \src "libresoc.v:170020.3-170046.6" + wire width 64 $1\reg$next[63:0]$11154 + attribute \src "libresoc.v:169865.14-169865.42" + wire width 64 $1\reg[63:0] + attribute \src "libresoc.v:169990.3-170019.6" + wire $1\wr_detect$4[0:0]$11148 + attribute \src "libresoc.v:169920.3-169949.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:169880.3-169919.6" + wire width 64 $2\cia2__data_o$next[63:0]$11132 + attribute \src "libresoc.v:169950.3-169989.6" + wire width 64 $2\msr2__data_o$next[63:0]$11141 + attribute \src "libresoc.v:170020.3-170046.6" + wire width 64 $2\reg$next[63:0]$11155 + attribute \src "libresoc.v:169990.3-170019.6" + wire $2\wr_detect$4[0:0]$11149 + attribute \src "libresoc.v:169920.3-169949.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:169880.3-169919.6" + wire width 64 $3\cia2__data_o$next[63:0]$11133 + attribute \src "libresoc.v:169950.3-169989.6" + wire width 64 $3\msr2__data_o$next[63:0]$11142 + attribute \src "libresoc.v:170020.3-170046.6" + wire width 64 $3\reg$next[63:0]$11156 + attribute \src "libresoc.v:169990.3-170019.6" + wire $3\wr_detect$4[0:0]$11150 + attribute \src "libresoc.v:169920.3-169949.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:169880.3-169919.6" + wire width 64 $4\cia2__data_o$next[63:0]$11134 + attribute \src "libresoc.v:169950.3-169989.6" + wire width 64 $4\msr2__data_o$next[63:0]$11143 + attribute \src "libresoc.v:170020.3-170046.6" + wire width 64 $4\reg$next[63:0]$11157 + attribute \src "libresoc.v:169990.3-170019.6" + wire $4\wr_detect$4[0:0]$11151 + attribute \src "libresoc.v:169920.3-169949.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:169880.3-169919.6" + wire width 64 $5\cia2__data_o$next[63:0]$11135 + attribute \src "libresoc.v:169950.3-169989.6" + wire width 64 $5\msr2__data_o$next[63:0]$11144 + attribute \src "libresoc.v:169880.3-169919.6" + wire width 64 $6\cia2__data_o$next[63:0]$11136 + attribute \src "libresoc.v:169950.3-169989.6" + wire width 64 $6\msr2__data_o$next[63:0]$11145 + attribute \src "libresoc.v:169872.17-169872.100" + wire $not$libresoc.v:169872$11124_Y + attribute \src "libresoc.v:169873.17-169873.103" + wire $not$libresoc.v:169873$11125_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 3 \cia2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \cia2__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \cia2__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 12 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 11 \d_wr12__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \d_wr12__wen + attribute \src "libresoc.v:169829.7-169829.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 9 \msr2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 5 \msr2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \msr2__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \msr2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \msr2__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 7 \nia2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \nia2__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:169872$11124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:169872$11124_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:169873$11125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:169873$11125_Y + end + attribute \src "libresoc.v:169829.7-169829.20" + process $proc$libresoc.v:169829$11158 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:169836.14-169836.49" + process $proc$libresoc.v:169836$11159 + assign { } { } + assign $1\cia2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \cia2__data_o $1\cia2__data_o[63:0] + end + attribute \src "libresoc.v:169853.14-169853.49" + process $proc$libresoc.v:169853$11160 + assign { } { } + assign $1\msr2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \msr2__data_o $1\msr2__data_o[63:0] + end + attribute \src "libresoc.v:169865.14-169865.42" + process $proc$libresoc.v:169865$11161 + assign { } { } + assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \reg $1\reg[63:0] + end + attribute \src "libresoc.v:169874.3-169875.25" + process $proc$libresoc.v:169874$11126 + assign { } { } + assign $0\reg[63:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[63:0] + end + attribute \src "libresoc.v:169876.3-169877.41" + process $proc$libresoc.v:169876$11127 + assign { } { } + assign $0\msr2__data_o[63:0] \msr2__data_o$next + sync posedge \coresync_clk + update \msr2__data_o $0\msr2__data_o[63:0] + end + attribute \src "libresoc.v:169878.3-169879.41" + process $proc$libresoc.v:169878$11128 + assign { } { } + assign $0\cia2__data_o[63:0] \cia2__data_o$next + sync posedge \coresync_clk + update \cia2__data_o $0\cia2__data_o[63:0] + end + attribute \src "libresoc.v:169880.3-169919.6" + process $proc$libresoc.v:169880$11129 + assign { } { } + assign { } { } + assign { } { } + assign $0\cia2__data_o$next[63:0]$11130 $6\cia2__data_o$next[63:0]$11136 + attribute \src "libresoc.v:169881.5-169881.29" + switch \initial + attribute \src "libresoc.v:169881.9-169881.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\cia2__data_o$next[63:0]$11131 $5\cia2__data_o$next[63:0]$11135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cia2__data_o$next[63:0]$11132 \nia2__data_i + case + assign $2\cia2__data_o$next[63:0]$11132 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cia2__data_o$next[63:0]$11133 \msr2__data_i + case + assign $3\cia2__data_o$next[63:0]$11133 $2\cia2__data_o$next[63:0]$11132 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cia2__data_o$next[63:0]$11134 \d_wr12__data_i + case + assign $4\cia2__data_o$next[63:0]$11134 $3\cia2__data_o$next[63:0]$11133 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\cia2__data_o$next[63:0]$11135 \reg + case + assign $5\cia2__data_o$next[63:0]$11135 $4\cia2__data_o$next[63:0]$11134 + end + case + assign $1\cia2__data_o$next[63:0]$11131 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\cia2__data_o$next[63:0]$11136 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $6\cia2__data_o$next[63:0]$11136 $1\cia2__data_o$next[63:0]$11131 + end + sync always + update \cia2__data_o$next $0\cia2__data_o$next[63:0]$11130 + end + attribute \src "libresoc.v:169920.3-169949.6" + process $proc$libresoc.v:169920$11137 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:169921.5-169921.29" + switch \initial + attribute \src "libresoc.v:169921.9-169921.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:169950.3-169989.6" + process $proc$libresoc.v:169950$11138 + assign { } { } + assign { } { } + assign { } { } + assign $0\msr2__data_o$next[63:0]$11139 $6\msr2__data_o$next[63:0]$11145 + attribute \src "libresoc.v:169951.5-169951.29" + switch \initial + attribute \src "libresoc.v:169951.9-169951.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \msr2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\msr2__data_o$next[63:0]$11140 $5\msr2__data_o$next[63:0]$11144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr2__data_o$next[63:0]$11141 \nia2__data_i + case + assign $2\msr2__data_o$next[63:0]$11141 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\msr2__data_o$next[63:0]$11142 \msr2__data_i + case + assign $3\msr2__data_o$next[63:0]$11142 $2\msr2__data_o$next[63:0]$11141 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\msr2__data_o$next[63:0]$11143 \d_wr12__data_i + case + assign $4\msr2__data_o$next[63:0]$11143 $3\msr2__data_o$next[63:0]$11142 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\msr2__data_o$next[63:0]$11144 \reg + case + assign $5\msr2__data_o$next[63:0]$11144 $4\msr2__data_o$next[63:0]$11143 + end + case + assign $1\msr2__data_o$next[63:0]$11140 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\msr2__data_o$next[63:0]$11145 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $6\msr2__data_o$next[63:0]$11145 $1\msr2__data_o$next[63:0]$11140 + end + sync always + update \msr2__data_o$next $0\msr2__data_o$next[63:0]$11139 + end + attribute \src "libresoc.v:169990.3-170019.6" + process $proc$libresoc.v:169990$11146 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$11147 $1\wr_detect$4[0:0]$11148 + attribute \src "libresoc.v:169991.5-169991.29" + switch \initial + attribute \src "libresoc.v:169991.9-169991.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \msr2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$11148 $4\wr_detect$4[0:0]$11151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$11149 1'1 + case + assign $2\wr_detect$4[0:0]$11149 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$11150 1'1 + case + assign $3\wr_detect$4[0:0]$11150 $2\wr_detect$4[0:0]$11149 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$11151 1'1 + case + assign $4\wr_detect$4[0:0]$11151 $3\wr_detect$4[0:0]$11150 + end + case + assign $1\wr_detect$4[0:0]$11148 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$11147 + end + attribute \src "libresoc.v:170020.3-170046.6" + process $proc$libresoc.v:170020$11152 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[63:0]$11153 $4\reg$next[63:0]$11157 + attribute \src "libresoc.v:170021.5-170021.29" + switch \initial + attribute \src "libresoc.v:170021.9-170021.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \nia2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[63:0]$11154 \nia2__data_i + case + assign $1\reg$next[63:0]$11154 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \msr2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[63:0]$11155 \msr2__data_i + case + assign $2\reg$next[63:0]$11155 $1\reg$next[63:0]$11154 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \d_wr12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[63:0]$11156 \d_wr12__data_i + case + assign $3\reg$next[63:0]$11156 $2\reg$next[63:0]$11155 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[63:0]$11157 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $4\reg$next[63:0]$11157 $3\reg$next[63:0]$11156 + end + sync always + update \reg$next $0\reg$next[63:0]$11153 + end + connect \$1 $not$libresoc.v:169872$11124_Y + connect \$3 $not$libresoc.v:169873$11125_Y +end +attribute \src "libresoc.v:170051.1-170522.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_3" +attribute \generator "nMigen" +module \reg_3 + attribute \src "libresoc.v:170052.7-170052.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:170452.3-170491.6" + wire width 4 $0\r23__data_o$next[3:0]$11231 + attribute \src "libresoc.v:170135.3-170136.39" + wire width 4 $0\r23__data_o[3:0] + attribute \src "libresoc.v:170382.3-170421.6" + wire width 4 $0\r3__data_o$next[3:0]$11217 + attribute \src "libresoc.v:170137.3-170138.37" + wire width 4 $0\r3__data_o[3:0] + attribute \src "libresoc.v:170215.3-170241.6" + wire width 4 $0\reg$next[3:0]$11183 + attribute \src "libresoc.v:170133.3-170134.25" + wire width 4 $0\reg[3:0] + attribute \src "libresoc.v:170145.3-170184.6" + wire width 4 $0\src13__data_o$next[3:0]$11174 + attribute \src "libresoc.v:170143.3-170144.43" + wire width 4 $0\src13__data_o[3:0] + attribute \src "libresoc.v:170242.3-170281.6" + wire width 4 $0\src23__data_o$next[3:0]$11189 + attribute \src "libresoc.v:170141.3-170142.43" + wire width 4 $0\src23__data_o[3:0] + attribute \src "libresoc.v:170312.3-170351.6" + wire width 4 $0\src33__data_o$next[3:0]$11203 + attribute \src "libresoc.v:170139.3-170140.43" + wire width 4 $0\src33__data_o[3:0] + attribute \src "libresoc.v:170422.3-170451.6" + wire $0\wr_detect$10[0:0]$11225 + attribute \src "libresoc.v:170492.3-170521.6" + wire $0\wr_detect$13[0:0]$11239 + attribute \src "libresoc.v:170282.3-170311.6" + wire $0\wr_detect$4[0:0]$11197 + attribute \src "libresoc.v:170352.3-170381.6" + wire $0\wr_detect$7[0:0]$11211 + attribute \src "libresoc.v:170185.3-170214.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:170452.3-170491.6" + wire width 4 $1\r23__data_o$next[3:0]$11232 + attribute \src "libresoc.v:170077.13-170077.31" + wire width 4 $1\r23__data_o[3:0] + attribute \src "libresoc.v:170382.3-170421.6" + wire width 4 $1\r3__data_o$next[3:0]$11218 + attribute \src "libresoc.v:170084.13-170084.30" + wire width 4 $1\r3__data_o[3:0] + attribute \src "libresoc.v:170215.3-170241.6" + wire width 4 $1\reg$next[3:0]$11184 + attribute \src "libresoc.v:170090.13-170090.25" + wire width 4 $1\reg[3:0] + attribute \src "libresoc.v:170145.3-170184.6" + wire width 4 $1\src13__data_o$next[3:0]$11175 + attribute \src "libresoc.v:170095.13-170095.33" + wire width 4 $1\src13__data_o[3:0] + attribute \src "libresoc.v:170242.3-170281.6" + wire width 4 $1\src23__data_o$next[3:0]$11190 + attribute \src "libresoc.v:170102.13-170102.33" + wire width 4 $1\src23__data_o[3:0] + attribute \src "libresoc.v:170312.3-170351.6" + wire width 4 $1\src33__data_o$next[3:0]$11204 + attribute \src "libresoc.v:170109.13-170109.33" + wire width 4 $1\src33__data_o[3:0] + attribute \src "libresoc.v:170422.3-170451.6" + wire $1\wr_detect$10[0:0]$11226 + attribute \src "libresoc.v:170492.3-170521.6" + wire $1\wr_detect$13[0:0]$11240 + attribute \src "libresoc.v:170282.3-170311.6" + wire $1\wr_detect$4[0:0]$11198 + attribute \src "libresoc.v:170352.3-170381.6" + wire $1\wr_detect$7[0:0]$11212 + attribute \src "libresoc.v:170185.3-170214.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:170452.3-170491.6" + wire width 4 $2\r23__data_o$next[3:0]$11233 + attribute \src "libresoc.v:170382.3-170421.6" + wire width 4 $2\r3__data_o$next[3:0]$11219 + attribute \src "libresoc.v:170215.3-170241.6" + wire width 4 $2\reg$next[3:0]$11185 + attribute \src "libresoc.v:170145.3-170184.6" + wire width 4 $2\src13__data_o$next[3:0]$11176 + attribute \src "libresoc.v:170242.3-170281.6" + wire width 4 $2\src23__data_o$next[3:0]$11191 + attribute \src "libresoc.v:170312.3-170351.6" + wire width 4 $2\src33__data_o$next[3:0]$11205 + attribute \src "libresoc.v:170422.3-170451.6" + wire $2\wr_detect$10[0:0]$11227 + attribute \src "libresoc.v:170492.3-170521.6" + wire $2\wr_detect$13[0:0]$11241 + attribute \src "libresoc.v:170282.3-170311.6" + wire $2\wr_detect$4[0:0]$11199 + attribute \src "libresoc.v:170352.3-170381.6" + wire $2\wr_detect$7[0:0]$11213 + attribute \src "libresoc.v:170185.3-170214.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:170452.3-170491.6" + wire width 4 $3\r23__data_o$next[3:0]$11234 + attribute \src "libresoc.v:170382.3-170421.6" + wire width 4 $3\r3__data_o$next[3:0]$11220 + attribute \src "libresoc.v:170215.3-170241.6" + wire width 4 $3\reg$next[3:0]$11186 + attribute \src "libresoc.v:170145.3-170184.6" + wire width 4 $3\src13__data_o$next[3:0]$11177 + attribute \src "libresoc.v:170242.3-170281.6" + wire width 4 $3\src23__data_o$next[3:0]$11192 + attribute \src "libresoc.v:170312.3-170351.6" + wire width 4 $3\src33__data_o$next[3:0]$11206 + attribute \src "libresoc.v:170422.3-170451.6" + wire $3\wr_detect$10[0:0]$11228 + attribute \src "libresoc.v:170492.3-170521.6" + wire $3\wr_detect$13[0:0]$11242 + attribute \src "libresoc.v:170282.3-170311.6" + wire $3\wr_detect$4[0:0]$11200 + attribute \src "libresoc.v:170352.3-170381.6" + wire $3\wr_detect$7[0:0]$11214 + attribute \src "libresoc.v:170185.3-170214.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:170452.3-170491.6" + wire width 4 $4\r23__data_o$next[3:0]$11235 + attribute \src "libresoc.v:170382.3-170421.6" + wire width 4 $4\r3__data_o$next[3:0]$11221 + attribute \src "libresoc.v:170215.3-170241.6" + wire width 4 $4\reg$next[3:0]$11187 + attribute \src "libresoc.v:170145.3-170184.6" + wire width 4 $4\src13__data_o$next[3:0]$11178 + attribute \src "libresoc.v:170242.3-170281.6" + wire width 4 $4\src23__data_o$next[3:0]$11193 + attribute \src "libresoc.v:170312.3-170351.6" + wire width 4 $4\src33__data_o$next[3:0]$11207 + attribute \src "libresoc.v:170422.3-170451.6" + wire $4\wr_detect$10[0:0]$11229 + attribute \src "libresoc.v:170492.3-170521.6" + wire $4\wr_detect$13[0:0]$11243 + attribute \src "libresoc.v:170282.3-170311.6" + wire $4\wr_detect$4[0:0]$11201 + attribute \src "libresoc.v:170352.3-170381.6" + wire $4\wr_detect$7[0:0]$11215 + attribute \src "libresoc.v:170185.3-170214.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:170452.3-170491.6" + wire width 4 $5\r23__data_o$next[3:0]$11236 + attribute \src "libresoc.v:170382.3-170421.6" + wire width 4 $5\r3__data_o$next[3:0]$11222 + attribute \src "libresoc.v:170145.3-170184.6" + wire width 4 $5\src13__data_o$next[3:0]$11179 + attribute \src "libresoc.v:170242.3-170281.6" + wire width 4 $5\src23__data_o$next[3:0]$11194 + attribute \src "libresoc.v:170312.3-170351.6" + wire width 4 $5\src33__data_o$next[3:0]$11208 + attribute \src "libresoc.v:170452.3-170491.6" + wire width 4 $6\r23__data_o$next[3:0]$11237 + attribute \src "libresoc.v:170382.3-170421.6" + wire width 4 $6\r3__data_o$next[3:0]$11223 + attribute \src "libresoc.v:170145.3-170184.6" + wire width 4 $6\src13__data_o$next[3:0]$11180 + attribute \src "libresoc.v:170242.3-170281.6" + wire width 4 $6\src23__data_o$next[3:0]$11195 + attribute \src "libresoc.v:170312.3-170351.6" + wire width 4 $6\src33__data_o$next[3:0]$11209 + attribute \src "libresoc.v:170128.17-170128.104" + wire $not$libresoc.v:170128$11162_Y + attribute \src "libresoc.v:170129.18-170129.105" + wire $not$libresoc.v:170129$11163_Y + attribute \src "libresoc.v:170130.17-170130.100" + wire $not$libresoc.v:170130$11164_Y + attribute \src "libresoc.v:170131.17-170131.103" + wire $not$libresoc.v:170131$11165_Y + attribute \src "libresoc.v:170132.17-170132.103" + wire $not$libresoc.v:170132$11166_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 9 \dest13__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \dest13__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 11 \dest23__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \dest23__wen + attribute \src "libresoc.v:170052.7-170052.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 14 \r23__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r23__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 15 \r23__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 12 \r3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r3__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 13 \r3__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 3 \src13__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src13__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \src13__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 5 \src23__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src23__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \src23__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 7 \src33__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src33__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \src33__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 16 \w3__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 17 \w3__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:170128$11162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:170128$11162_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:170129$11163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$libresoc.v:170129$11163_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:170130$11164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:170130$11164_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:170131$11165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:170131$11165_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:170132$11166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:170132$11166_Y + end + attribute \src "libresoc.v:170052.7-170052.20" + process $proc$libresoc.v:170052$11244 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:170077.13-170077.31" + process $proc$libresoc.v:170077$11245 + assign { } { } + assign $1\r23__data_o[3:0] 4'0000 + sync always + sync init + update \r23__data_o $1\r23__data_o[3:0] + end + attribute \src "libresoc.v:170084.13-170084.30" + process $proc$libresoc.v:170084$11246 + assign { } { } + assign $1\r3__data_o[3:0] 4'0000 + sync always + sync init + update \r3__data_o $1\r3__data_o[3:0] + end + attribute \src "libresoc.v:170090.13-170090.25" + process $proc$libresoc.v:170090$11247 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "libresoc.v:170095.13-170095.33" + process $proc$libresoc.v:170095$11248 + assign { } { } + assign $1\src13__data_o[3:0] 4'0000 + sync always + sync init + update \src13__data_o $1\src13__data_o[3:0] + end + attribute \src "libresoc.v:170102.13-170102.33" + process $proc$libresoc.v:170102$11249 + assign { } { } + assign $1\src23__data_o[3:0] 4'0000 + sync always + sync init + update \src23__data_o $1\src23__data_o[3:0] + end + attribute \src "libresoc.v:170109.13-170109.33" + process $proc$libresoc.v:170109$11250 + assign { } { } + assign $1\src33__data_o[3:0] 4'0000 + sync always + sync init + update \src33__data_o $1\src33__data_o[3:0] + end + attribute \src "libresoc.v:170133.3-170134.25" + process $proc$libresoc.v:170133$11167 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "libresoc.v:170135.3-170136.39" + process $proc$libresoc.v:170135$11168 + assign { } { } + assign $0\r23__data_o[3:0] \r23__data_o$next + sync posedge \coresync_clk + update \r23__data_o $0\r23__data_o[3:0] + end + attribute \src "libresoc.v:170137.3-170138.37" + process $proc$libresoc.v:170137$11169 + assign { } { } + assign $0\r3__data_o[3:0] \r3__data_o$next + sync posedge \coresync_clk + update \r3__data_o $0\r3__data_o[3:0] + end + attribute \src "libresoc.v:170139.3-170140.43" + process $proc$libresoc.v:170139$11170 + assign { } { } + assign $0\src33__data_o[3:0] \src33__data_o$next + sync posedge \coresync_clk + update \src33__data_o $0\src33__data_o[3:0] + end + attribute \src "libresoc.v:170141.3-170142.43" + process $proc$libresoc.v:170141$11171 + assign { } { } + assign $0\src23__data_o[3:0] \src23__data_o$next + sync posedge \coresync_clk + update \src23__data_o $0\src23__data_o[3:0] + end + attribute \src "libresoc.v:170143.3-170144.43" + process $proc$libresoc.v:170143$11172 + assign { } { } + assign $0\src13__data_o[3:0] \src13__data_o$next + sync posedge \coresync_clk + update \src13__data_o $0\src13__data_o[3:0] + end + attribute \src "libresoc.v:170145.3-170184.6" + process $proc$libresoc.v:170145$11173 + assign { } { } + assign { } { } + assign { } { } + assign $0\src13__data_o$next[3:0]$11174 $6\src13__data_o$next[3:0]$11180 + attribute \src "libresoc.v:170146.5-170146.29" + switch \initial + attribute \src "libresoc.v:170146.9-170146.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src13__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src13__data_o$next[3:0]$11175 $5\src13__data_o$next[3:0]$11179 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src13__data_o$next[3:0]$11176 \dest13__data_i + case + assign $2\src13__data_o$next[3:0]$11176 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src13__data_o$next[3:0]$11177 \dest23__data_i + case + assign $3\src13__data_o$next[3:0]$11177 $2\src13__data_o$next[3:0]$11176 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src13__data_o$next[3:0]$11178 \w3__data_i + case + assign $4\src13__data_o$next[3:0]$11178 $3\src13__data_o$next[3:0]$11177 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src13__data_o$next[3:0]$11179 \reg + case + assign $5\src13__data_o$next[3:0]$11179 $4\src13__data_o$next[3:0]$11178 + end + case + assign $1\src13__data_o$next[3:0]$11175 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src13__data_o$next[3:0]$11180 4'0000 + case + assign $6\src13__data_o$next[3:0]$11180 $1\src13__data_o$next[3:0]$11175 + end + sync always + update \src13__data_o$next $0\src13__data_o$next[3:0]$11174 + end + attribute \src "libresoc.v:170185.3-170214.6" + process $proc$libresoc.v:170185$11181 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:170186.5-170186.29" + switch \initial + attribute \src "libresoc.v:170186.9-170186.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src13__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:170215.3-170241.6" + process $proc$libresoc.v:170215$11182 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$11183 $4\reg$next[3:0]$11187 + attribute \src "libresoc.v:170216.5-170216.29" + switch \initial + attribute \src "libresoc.v:170216.9-170216.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$11184 \dest13__data_i + case + assign $1\reg$next[3:0]$11184 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$11185 \dest23__data_i + case + assign $2\reg$next[3:0]$11185 $1\reg$next[3:0]$11184 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$11186 \w3__data_i + case + assign $3\reg$next[3:0]$11186 $2\reg$next[3:0]$11185 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$11187 4'0000 + case + assign $4\reg$next[3:0]$11187 $3\reg$next[3:0]$11186 + end + sync always + update \reg$next $0\reg$next[3:0]$11183 + end + attribute \src "libresoc.v:170242.3-170281.6" + process $proc$libresoc.v:170242$11188 + assign { } { } + assign { } { } + assign { } { } + assign $0\src23__data_o$next[3:0]$11189 $6\src23__data_o$next[3:0]$11195 + attribute \src "libresoc.v:170243.5-170243.29" + switch \initial + attribute \src "libresoc.v:170243.9-170243.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src23__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src23__data_o$next[3:0]$11190 $5\src23__data_o$next[3:0]$11194 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src23__data_o$next[3:0]$11191 \dest13__data_i + case + assign $2\src23__data_o$next[3:0]$11191 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src23__data_o$next[3:0]$11192 \dest23__data_i + case + assign $3\src23__data_o$next[3:0]$11192 $2\src23__data_o$next[3:0]$11191 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src23__data_o$next[3:0]$11193 \w3__data_i + case + assign $4\src23__data_o$next[3:0]$11193 $3\src23__data_o$next[3:0]$11192 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src23__data_o$next[3:0]$11194 \reg + case + assign $5\src23__data_o$next[3:0]$11194 $4\src23__data_o$next[3:0]$11193 + end + case + assign $1\src23__data_o$next[3:0]$11190 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src23__data_o$next[3:0]$11195 4'0000 + case + assign $6\src23__data_o$next[3:0]$11195 $1\src23__data_o$next[3:0]$11190 + end + sync always + update \src23__data_o$next $0\src23__data_o$next[3:0]$11189 + end + attribute \src "libresoc.v:170282.3-170311.6" + process $proc$libresoc.v:170282$11196 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$11197 $1\wr_detect$4[0:0]$11198 + attribute \src "libresoc.v:170283.5-170283.29" + switch \initial + attribute \src "libresoc.v:170283.9-170283.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src23__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$11198 $4\wr_detect$4[0:0]$11201 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$11199 1'1 + case + assign $2\wr_detect$4[0:0]$11199 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$11200 1'1 + case + assign $3\wr_detect$4[0:0]$11200 $2\wr_detect$4[0:0]$11199 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$11201 1'1 + case + assign $4\wr_detect$4[0:0]$11201 $3\wr_detect$4[0:0]$11200 + end + case + assign $1\wr_detect$4[0:0]$11198 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$11197 + end + attribute \src "libresoc.v:170312.3-170351.6" + process $proc$libresoc.v:170312$11202 + assign { } { } + assign { } { } + assign { } { } + assign $0\src33__data_o$next[3:0]$11203 $6\src33__data_o$next[3:0]$11209 + attribute \src "libresoc.v:170313.5-170313.29" + switch \initial + attribute \src "libresoc.v:170313.9-170313.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src33__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src33__data_o$next[3:0]$11204 $5\src33__data_o$next[3:0]$11208 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src33__data_o$next[3:0]$11205 \dest13__data_i + case + assign $2\src33__data_o$next[3:0]$11205 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src33__data_o$next[3:0]$11206 \dest23__data_i + case + assign $3\src33__data_o$next[3:0]$11206 $2\src33__data_o$next[3:0]$11205 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src33__data_o$next[3:0]$11207 \w3__data_i + case + assign $4\src33__data_o$next[3:0]$11207 $3\src33__data_o$next[3:0]$11206 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src33__data_o$next[3:0]$11208 \reg + case + assign $5\src33__data_o$next[3:0]$11208 $4\src33__data_o$next[3:0]$11207 + end + case + assign $1\src33__data_o$next[3:0]$11204 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src33__data_o$next[3:0]$11209 4'0000 + case + assign $6\src33__data_o$next[3:0]$11209 $1\src33__data_o$next[3:0]$11204 + end + sync always + update \src33__data_o$next $0\src33__data_o$next[3:0]$11203 + end + attribute \src "libresoc.v:170352.3-170381.6" + process $proc$libresoc.v:170352$11210 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$11211 $1\wr_detect$7[0:0]$11212 + attribute \src "libresoc.v:170353.5-170353.29" + switch \initial + attribute \src "libresoc.v:170353.9-170353.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src33__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$11212 $4\wr_detect$7[0:0]$11215 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$11213 1'1 + case + assign $2\wr_detect$7[0:0]$11213 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$11214 1'1 + case + assign $3\wr_detect$7[0:0]$11214 $2\wr_detect$7[0:0]$11213 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$11215 1'1 + case + assign $4\wr_detect$7[0:0]$11215 $3\wr_detect$7[0:0]$11214 + end + case + assign $1\wr_detect$7[0:0]$11212 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$11211 + end + attribute \src "libresoc.v:170382.3-170421.6" + process $proc$libresoc.v:170382$11216 + assign { } { } + assign { } { } + assign { } { } + assign $0\r3__data_o$next[3:0]$11217 $6\r3__data_o$next[3:0]$11223 + attribute \src "libresoc.v:170383.5-170383.29" + switch \initial + attribute \src "libresoc.v:170383.9-170383.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r3__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r3__data_o$next[3:0]$11218 $5\r3__data_o$next[3:0]$11222 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r3__data_o$next[3:0]$11219 \dest13__data_i + case + assign $2\r3__data_o$next[3:0]$11219 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r3__data_o$next[3:0]$11220 \dest23__data_i + case + assign $3\r3__data_o$next[3:0]$11220 $2\r3__data_o$next[3:0]$11219 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r3__data_o$next[3:0]$11221 \w3__data_i + case + assign $4\r3__data_o$next[3:0]$11221 $3\r3__data_o$next[3:0]$11220 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r3__data_o$next[3:0]$11222 \reg + case + assign $5\r3__data_o$next[3:0]$11222 $4\r3__data_o$next[3:0]$11221 + end + case + assign $1\r3__data_o$next[3:0]$11218 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r3__data_o$next[3:0]$11223 4'0000 + case + assign $6\r3__data_o$next[3:0]$11223 $1\r3__data_o$next[3:0]$11218 + end + sync always + update \r3__data_o$next $0\r3__data_o$next[3:0]$11217 + end + attribute \src "libresoc.v:170422.3-170451.6" + process $proc$libresoc.v:170422$11224 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$11225 $1\wr_detect$10[0:0]$11226 + attribute \src "libresoc.v:170423.5-170423.29" + switch \initial + attribute \src "libresoc.v:170423.9-170423.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r3__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$11226 $4\wr_detect$10[0:0]$11229 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$11227 1'1 + case + assign $2\wr_detect$10[0:0]$11227 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$11228 1'1 + case + assign $3\wr_detect$10[0:0]$11228 $2\wr_detect$10[0:0]$11227 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$11229 1'1 + case + assign $4\wr_detect$10[0:0]$11229 $3\wr_detect$10[0:0]$11228 + end + case + assign $1\wr_detect$10[0:0]$11226 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$11225 + end + attribute \src "libresoc.v:170452.3-170491.6" + process $proc$libresoc.v:170452$11230 + assign { } { } + assign { } { } + assign { } { } + assign $0\r23__data_o$next[3:0]$11231 $6\r23__data_o$next[3:0]$11237 + attribute \src "libresoc.v:170453.5-170453.29" + switch \initial + attribute \src "libresoc.v:170453.9-170453.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r23__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r23__data_o$next[3:0]$11232 $5\r23__data_o$next[3:0]$11236 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r23__data_o$next[3:0]$11233 \dest13__data_i + case + assign $2\r23__data_o$next[3:0]$11233 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r23__data_o$next[3:0]$11234 \dest23__data_i + case + assign $3\r23__data_o$next[3:0]$11234 $2\r23__data_o$next[3:0]$11233 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r23__data_o$next[3:0]$11235 \w3__data_i + case + assign $4\r23__data_o$next[3:0]$11235 $3\r23__data_o$next[3:0]$11234 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r23__data_o$next[3:0]$11236 \reg + case + assign $5\r23__data_o$next[3:0]$11236 $4\r23__data_o$next[3:0]$11235 + end + case + assign $1\r23__data_o$next[3:0]$11232 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r23__data_o$next[3:0]$11237 4'0000 + case + assign $6\r23__data_o$next[3:0]$11237 $1\r23__data_o$next[3:0]$11232 + end + sync always + update \r23__data_o$next $0\r23__data_o$next[3:0]$11231 + end + attribute \src "libresoc.v:170492.3-170521.6" + process $proc$libresoc.v:170492$11238 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$11239 $1\wr_detect$13[0:0]$11240 + attribute \src "libresoc.v:170493.5-170493.29" + switch \initial + attribute \src "libresoc.v:170493.9-170493.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r23__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$11240 $4\wr_detect$13[0:0]$11243 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$11241 1'1 + case + assign $2\wr_detect$13[0:0]$11241 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$11242 1'1 + case + assign $3\wr_detect$13[0:0]$11242 $2\wr_detect$13[0:0]$11241 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$11243 1'1 + case + assign $4\wr_detect$13[0:0]$11243 $3\wr_detect$13[0:0]$11242 + end + case + assign $1\wr_detect$13[0:0]$11240 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$11239 + end + connect \$9 $not$libresoc.v:170128$11162_Y + connect \$12 $not$libresoc.v:170129$11163_Y + connect \$1 $not$libresoc.v:170130$11164_Y + connect \$3 $not$libresoc.v:170131$11165_Y + connect \$6 $not$libresoc.v:170132$11166_Y +end +attribute \src "libresoc.v:170526.1-170745.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_3" +attribute \generator "nMigen" +module \reg_3$138 + attribute \src "libresoc.v:170578.3-170617.6" + wire width 64 $0\cia3__data_o$next[63:0]$11257 + attribute \src "libresoc.v:170576.3-170577.41" + wire width 64 $0\cia3__data_o[63:0] + attribute \src "libresoc.v:170527.7-170527.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:170648.3-170687.6" + wire width 64 $0\msr3__data_o$next[63:0]$11266 + attribute \src "libresoc.v:170574.3-170575.41" + wire width 64 $0\msr3__data_o[63:0] + attribute \src "libresoc.v:170718.3-170744.6" + wire width 64 $0\reg$next[63:0]$11280 + attribute \src "libresoc.v:170572.3-170573.25" + wire width 64 $0\reg[63:0] + attribute \src "libresoc.v:170688.3-170717.6" + wire $0\wr_detect$4[0:0]$11274 + attribute \src "libresoc.v:170618.3-170647.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:170578.3-170617.6" + wire width 64 $1\cia3__data_o$next[63:0]$11258 + attribute \src "libresoc.v:170534.14-170534.49" + wire width 64 $1\cia3__data_o[63:0] + attribute \src "libresoc.v:170648.3-170687.6" + wire width 64 $1\msr3__data_o$next[63:0]$11267 + attribute \src "libresoc.v:170551.14-170551.49" + wire width 64 $1\msr3__data_o[63:0] + attribute \src "libresoc.v:170718.3-170744.6" + wire width 64 $1\reg$next[63:0]$11281 + attribute \src "libresoc.v:170563.14-170563.42" + wire width 64 $1\reg[63:0] + attribute \src "libresoc.v:170688.3-170717.6" + wire $1\wr_detect$4[0:0]$11275 + attribute \src "libresoc.v:170618.3-170647.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:170578.3-170617.6" + wire width 64 $2\cia3__data_o$next[63:0]$11259 + attribute \src "libresoc.v:170648.3-170687.6" + wire width 64 $2\msr3__data_o$next[63:0]$11268 + attribute \src "libresoc.v:170718.3-170744.6" + wire width 64 $2\reg$next[63:0]$11282 + attribute \src "libresoc.v:170688.3-170717.6" + wire $2\wr_detect$4[0:0]$11276 + attribute \src "libresoc.v:170618.3-170647.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:170578.3-170617.6" + wire width 64 $3\cia3__data_o$next[63:0]$11260 + attribute \src "libresoc.v:170648.3-170687.6" + wire width 64 $3\msr3__data_o$next[63:0]$11269 + attribute \src "libresoc.v:170718.3-170744.6" + wire width 64 $3\reg$next[63:0]$11283 + attribute \src "libresoc.v:170688.3-170717.6" + wire $3\wr_detect$4[0:0]$11277 + attribute \src "libresoc.v:170618.3-170647.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:170578.3-170617.6" + wire width 64 $4\cia3__data_o$next[63:0]$11261 + attribute \src "libresoc.v:170648.3-170687.6" + wire width 64 $4\msr3__data_o$next[63:0]$11270 + attribute \src "libresoc.v:170718.3-170744.6" + wire width 64 $4\reg$next[63:0]$11284 + attribute \src "libresoc.v:170688.3-170717.6" + wire $4\wr_detect$4[0:0]$11278 + attribute \src "libresoc.v:170618.3-170647.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:170578.3-170617.6" + wire width 64 $5\cia3__data_o$next[63:0]$11262 + attribute \src "libresoc.v:170648.3-170687.6" + wire width 64 $5\msr3__data_o$next[63:0]$11271 + attribute \src "libresoc.v:170578.3-170617.6" + wire width 64 $6\cia3__data_o$next[63:0]$11263 + attribute \src "libresoc.v:170648.3-170687.6" + wire width 64 $6\msr3__data_o$next[63:0]$11272 + attribute \src "libresoc.v:170570.17-170570.100" + wire $not$libresoc.v:170570$11251_Y + attribute \src "libresoc.v:170571.17-170571.103" + wire $not$libresoc.v:170571$11252_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 3 \cia3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \cia3__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \cia3__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 12 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 11 \d_wr13__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \d_wr13__wen + attribute \src "libresoc.v:170527.7-170527.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 9 \msr3__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 5 \msr3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \msr3__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \msr3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \msr3__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 7 \nia3__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \nia3__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:170570$11251 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:170570$11251_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:170571$11252 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:170571$11252_Y + end + attribute \src "libresoc.v:170527.7-170527.20" + process $proc$libresoc.v:170527$11285 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:170534.14-170534.49" + process $proc$libresoc.v:170534$11286 + assign { } { } + assign $1\cia3__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \cia3__data_o $1\cia3__data_o[63:0] + end + attribute \src "libresoc.v:170551.14-170551.49" + process $proc$libresoc.v:170551$11287 + assign { } { } + assign $1\msr3__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \msr3__data_o $1\msr3__data_o[63:0] + end + attribute \src "libresoc.v:170563.14-170563.42" + process $proc$libresoc.v:170563$11288 + assign { } { } + assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \reg $1\reg[63:0] + end + attribute \src "libresoc.v:170572.3-170573.25" + process $proc$libresoc.v:170572$11253 + assign { } { } + assign $0\reg[63:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[63:0] + end + attribute \src "libresoc.v:170574.3-170575.41" + process $proc$libresoc.v:170574$11254 + assign { } { } + assign $0\msr3__data_o[63:0] \msr3__data_o$next + sync posedge \coresync_clk + update \msr3__data_o $0\msr3__data_o[63:0] + end + attribute \src "libresoc.v:170576.3-170577.41" + process $proc$libresoc.v:170576$11255 + assign { } { } + assign $0\cia3__data_o[63:0] \cia3__data_o$next + sync posedge \coresync_clk + update \cia3__data_o $0\cia3__data_o[63:0] + end + attribute \src "libresoc.v:170578.3-170617.6" + process $proc$libresoc.v:170578$11256 + assign { } { } + assign { } { } + assign { } { } + assign $0\cia3__data_o$next[63:0]$11257 $6\cia3__data_o$next[63:0]$11263 + attribute \src "libresoc.v:170579.5-170579.29" + switch \initial + attribute \src "libresoc.v:170579.9-170579.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia3__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\cia3__data_o$next[63:0]$11258 $5\cia3__data_o$next[63:0]$11262 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cia3__data_o$next[63:0]$11259 \nia3__data_i + case + assign $2\cia3__data_o$next[63:0]$11259 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cia3__data_o$next[63:0]$11260 \msr3__data_i + case + assign $3\cia3__data_o$next[63:0]$11260 $2\cia3__data_o$next[63:0]$11259 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cia3__data_o$next[63:0]$11261 \d_wr13__data_i + case + assign $4\cia3__data_o$next[63:0]$11261 $3\cia3__data_o$next[63:0]$11260 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\cia3__data_o$next[63:0]$11262 \reg + case + assign $5\cia3__data_o$next[63:0]$11262 $4\cia3__data_o$next[63:0]$11261 + end + case + assign $1\cia3__data_o$next[63:0]$11258 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\cia3__data_o$next[63:0]$11263 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $6\cia3__data_o$next[63:0]$11263 $1\cia3__data_o$next[63:0]$11258 + end + sync always + update \cia3__data_o$next $0\cia3__data_o$next[63:0]$11257 + end + attribute \src "libresoc.v:170618.3-170647.6" + process $proc$libresoc.v:170618$11264 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:170619.5-170619.29" + switch \initial + attribute \src "libresoc.v:170619.9-170619.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia3__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:170648.3-170687.6" + process $proc$libresoc.v:170648$11265 + assign { } { } + assign { } { } + assign { } { } + assign $0\msr3__data_o$next[63:0]$11266 $6\msr3__data_o$next[63:0]$11272 + attribute \src "libresoc.v:170649.5-170649.29" + switch \initial + attribute \src "libresoc.v:170649.9-170649.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \msr3__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\msr3__data_o$next[63:0]$11267 $5\msr3__data_o$next[63:0]$11271 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr3__data_o$next[63:0]$11268 \nia3__data_i + case + assign $2\msr3__data_o$next[63:0]$11268 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\msr3__data_o$next[63:0]$11269 \msr3__data_i + case + assign $3\msr3__data_o$next[63:0]$11269 $2\msr3__data_o$next[63:0]$11268 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\msr3__data_o$next[63:0]$11270 \d_wr13__data_i + case + assign $4\msr3__data_o$next[63:0]$11270 $3\msr3__data_o$next[63:0]$11269 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\msr3__data_o$next[63:0]$11271 \reg + case + assign $5\msr3__data_o$next[63:0]$11271 $4\msr3__data_o$next[63:0]$11270 + end + case + assign $1\msr3__data_o$next[63:0]$11267 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\msr3__data_o$next[63:0]$11272 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $6\msr3__data_o$next[63:0]$11272 $1\msr3__data_o$next[63:0]$11267 + end + sync always + update \msr3__data_o$next $0\msr3__data_o$next[63:0]$11266 + end + attribute \src "libresoc.v:170688.3-170717.6" + process $proc$libresoc.v:170688$11273 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$11274 $1\wr_detect$4[0:0]$11275 + attribute \src "libresoc.v:170689.5-170689.29" + switch \initial + attribute \src "libresoc.v:170689.9-170689.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \msr3__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$11275 $4\wr_detect$4[0:0]$11278 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$11276 1'1 + case + assign $2\wr_detect$4[0:0]$11276 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$11277 1'1 + case + assign $3\wr_detect$4[0:0]$11277 $2\wr_detect$4[0:0]$11276 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$11278 1'1 + case + assign $4\wr_detect$4[0:0]$11278 $3\wr_detect$4[0:0]$11277 + end + case + assign $1\wr_detect$4[0:0]$11275 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$11274 + end + attribute \src "libresoc.v:170718.3-170744.6" + process $proc$libresoc.v:170718$11279 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[63:0]$11280 $4\reg$next[63:0]$11284 + attribute \src "libresoc.v:170719.5-170719.29" + switch \initial + attribute \src "libresoc.v:170719.9-170719.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \nia3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[63:0]$11281 \nia3__data_i + case + assign $1\reg$next[63:0]$11281 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \msr3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[63:0]$11282 \msr3__data_i + case + assign $2\reg$next[63:0]$11282 $1\reg$next[63:0]$11281 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \d_wr13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[63:0]$11283 \d_wr13__data_i + case + assign $3\reg$next[63:0]$11283 $2\reg$next[63:0]$11282 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[63:0]$11284 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $4\reg$next[63:0]$11284 $3\reg$next[63:0]$11283 + end + sync always + update \reg$next $0\reg$next[63:0]$11280 + end + connect \$1 $not$libresoc.v:170570$11251_Y + connect \$3 $not$libresoc.v:170571$11252_Y +end +attribute \src "libresoc.v:170749.1-171220.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_4" +attribute \generator "nMigen" +module \reg_4 + attribute \src "libresoc.v:170750.7-170750.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:171150.3-171189.6" + wire width 4 $0\r24__data_o$next[3:0]$11358 + attribute \src "libresoc.v:170833.3-170834.39" + wire width 4 $0\r24__data_o[3:0] + attribute \src "libresoc.v:171080.3-171119.6" + wire width 4 $0\r4__data_o$next[3:0]$11344 + attribute \src "libresoc.v:170835.3-170836.37" + wire width 4 $0\r4__data_o[3:0] + attribute \src "libresoc.v:170913.3-170939.6" + wire width 4 $0\reg$next[3:0]$11310 + attribute \src "libresoc.v:170831.3-170832.25" + wire width 4 $0\reg[3:0] + attribute \src "libresoc.v:170843.3-170882.6" + wire width 4 $0\src14__data_o$next[3:0]$11301 + attribute \src "libresoc.v:170841.3-170842.43" + wire width 4 $0\src14__data_o[3:0] + attribute \src "libresoc.v:170940.3-170979.6" + wire width 4 $0\src24__data_o$next[3:0]$11316 + attribute \src "libresoc.v:170839.3-170840.43" + wire width 4 $0\src24__data_o[3:0] + attribute \src "libresoc.v:171010.3-171049.6" + wire width 4 $0\src34__data_o$next[3:0]$11330 + attribute \src "libresoc.v:170837.3-170838.43" + wire width 4 $0\src34__data_o[3:0] + attribute \src "libresoc.v:171120.3-171149.6" + wire $0\wr_detect$10[0:0]$11352 + attribute \src "libresoc.v:171190.3-171219.6" + wire $0\wr_detect$13[0:0]$11366 + attribute \src "libresoc.v:170980.3-171009.6" + wire $0\wr_detect$4[0:0]$11324 + attribute \src "libresoc.v:171050.3-171079.6" + wire $0\wr_detect$7[0:0]$11338 + attribute \src "libresoc.v:170883.3-170912.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:171150.3-171189.6" + wire width 4 $1\r24__data_o$next[3:0]$11359 + attribute \src "libresoc.v:170775.13-170775.31" + wire width 4 $1\r24__data_o[3:0] + attribute \src "libresoc.v:171080.3-171119.6" + wire width 4 $1\r4__data_o$next[3:0]$11345 + attribute \src "libresoc.v:170782.13-170782.30" + wire width 4 $1\r4__data_o[3:0] + attribute \src "libresoc.v:170913.3-170939.6" + wire width 4 $1\reg$next[3:0]$11311 + attribute \src "libresoc.v:170788.13-170788.25" + wire width 4 $1\reg[3:0] + attribute \src "libresoc.v:170843.3-170882.6" + wire width 4 $1\src14__data_o$next[3:0]$11302 + attribute \src "libresoc.v:170793.13-170793.33" + wire width 4 $1\src14__data_o[3:0] + attribute \src "libresoc.v:170940.3-170979.6" + wire width 4 $1\src24__data_o$next[3:0]$11317 + attribute \src "libresoc.v:170800.13-170800.33" + wire width 4 $1\src24__data_o[3:0] + attribute \src "libresoc.v:171010.3-171049.6" + wire width 4 $1\src34__data_o$next[3:0]$11331 + attribute \src "libresoc.v:170807.13-170807.33" + wire width 4 $1\src34__data_o[3:0] + attribute \src "libresoc.v:171120.3-171149.6" + wire $1\wr_detect$10[0:0]$11353 + attribute \src "libresoc.v:171190.3-171219.6" + wire $1\wr_detect$13[0:0]$11367 + attribute \src "libresoc.v:170980.3-171009.6" + wire $1\wr_detect$4[0:0]$11325 + attribute \src "libresoc.v:171050.3-171079.6" + wire $1\wr_detect$7[0:0]$11339 + attribute \src "libresoc.v:170883.3-170912.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:171150.3-171189.6" + wire width 4 $2\r24__data_o$next[3:0]$11360 + attribute \src "libresoc.v:171080.3-171119.6" + wire width 4 $2\r4__data_o$next[3:0]$11346 + attribute \src "libresoc.v:170913.3-170939.6" + wire width 4 $2\reg$next[3:0]$11312 + attribute \src "libresoc.v:170843.3-170882.6" + wire width 4 $2\src14__data_o$next[3:0]$11303 + attribute \src "libresoc.v:170940.3-170979.6" + wire width 4 $2\src24__data_o$next[3:0]$11318 + attribute \src "libresoc.v:171010.3-171049.6" + wire width 4 $2\src34__data_o$next[3:0]$11332 + attribute \src "libresoc.v:171120.3-171149.6" + wire $2\wr_detect$10[0:0]$11354 + attribute \src "libresoc.v:171190.3-171219.6" + wire $2\wr_detect$13[0:0]$11368 + attribute \src "libresoc.v:170980.3-171009.6" + wire $2\wr_detect$4[0:0]$11326 + attribute \src "libresoc.v:171050.3-171079.6" + wire $2\wr_detect$7[0:0]$11340 + attribute \src "libresoc.v:170883.3-170912.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:171150.3-171189.6" + wire width 4 $3\r24__data_o$next[3:0]$11361 + attribute \src "libresoc.v:171080.3-171119.6" + wire width 4 $3\r4__data_o$next[3:0]$11347 + attribute \src "libresoc.v:170913.3-170939.6" + wire width 4 $3\reg$next[3:0]$11313 + attribute \src "libresoc.v:170843.3-170882.6" + wire width 4 $3\src14__data_o$next[3:0]$11304 + attribute \src "libresoc.v:170940.3-170979.6" + wire width 4 $3\src24__data_o$next[3:0]$11319 + attribute \src "libresoc.v:171010.3-171049.6" + wire width 4 $3\src34__data_o$next[3:0]$11333 + attribute \src "libresoc.v:171120.3-171149.6" + wire $3\wr_detect$10[0:0]$11355 + attribute \src "libresoc.v:171190.3-171219.6" + wire $3\wr_detect$13[0:0]$11369 + attribute \src "libresoc.v:170980.3-171009.6" + wire $3\wr_detect$4[0:0]$11327 + attribute \src "libresoc.v:171050.3-171079.6" + wire $3\wr_detect$7[0:0]$11341 + attribute \src "libresoc.v:170883.3-170912.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:171150.3-171189.6" + wire width 4 $4\r24__data_o$next[3:0]$11362 + attribute \src "libresoc.v:171080.3-171119.6" + wire width 4 $4\r4__data_o$next[3:0]$11348 + attribute \src "libresoc.v:170913.3-170939.6" + wire width 4 $4\reg$next[3:0]$11314 + attribute \src "libresoc.v:170843.3-170882.6" + wire width 4 $4\src14__data_o$next[3:0]$11305 + attribute \src "libresoc.v:170940.3-170979.6" + wire width 4 $4\src24__data_o$next[3:0]$11320 + attribute \src "libresoc.v:171010.3-171049.6" + wire width 4 $4\src34__data_o$next[3:0]$11334 + attribute \src "libresoc.v:171120.3-171149.6" + wire $4\wr_detect$10[0:0]$11356 + attribute \src "libresoc.v:171190.3-171219.6" + wire $4\wr_detect$13[0:0]$11370 + attribute \src "libresoc.v:170980.3-171009.6" + wire $4\wr_detect$4[0:0]$11328 + attribute \src "libresoc.v:171050.3-171079.6" + wire $4\wr_detect$7[0:0]$11342 + attribute \src "libresoc.v:170883.3-170912.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:171150.3-171189.6" + wire width 4 $5\r24__data_o$next[3:0]$11363 + attribute \src "libresoc.v:171080.3-171119.6" + wire width 4 $5\r4__data_o$next[3:0]$11349 + attribute \src "libresoc.v:170843.3-170882.6" + wire width 4 $5\src14__data_o$next[3:0]$11306 + attribute \src "libresoc.v:170940.3-170979.6" + wire width 4 $5\src24__data_o$next[3:0]$11321 + attribute \src "libresoc.v:171010.3-171049.6" + wire width 4 $5\src34__data_o$next[3:0]$11335 + attribute \src "libresoc.v:171150.3-171189.6" + wire width 4 $6\r24__data_o$next[3:0]$11364 + attribute \src "libresoc.v:171080.3-171119.6" + wire width 4 $6\r4__data_o$next[3:0]$11350 + attribute \src "libresoc.v:170843.3-170882.6" + wire width 4 $6\src14__data_o$next[3:0]$11307 + attribute \src "libresoc.v:170940.3-170979.6" + wire width 4 $6\src24__data_o$next[3:0]$11322 + attribute \src "libresoc.v:171010.3-171049.6" + wire width 4 $6\src34__data_o$next[3:0]$11336 + attribute \src "libresoc.v:170826.17-170826.104" + wire $not$libresoc.v:170826$11289_Y + attribute \src "libresoc.v:170827.18-170827.105" + wire $not$libresoc.v:170827$11290_Y + attribute \src "libresoc.v:170828.17-170828.100" + wire $not$libresoc.v:170828$11291_Y + attribute \src "libresoc.v:170829.17-170829.103" + wire $not$libresoc.v:170829$11292_Y + attribute \src "libresoc.v:170830.17-170830.103" + wire $not$libresoc.v:170830$11293_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 9 \dest14__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \dest14__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 11 \dest24__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \dest24__wen + attribute \src "libresoc.v:170750.7-170750.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 14 \r24__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r24__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 15 \r24__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 12 \r4__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r4__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 13 \r4__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 3 \src14__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src14__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \src14__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 5 \src24__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src24__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \src24__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 7 \src34__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src34__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \src34__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 16 \w4__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 17 \w4__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:170826$11289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:170826$11289_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:170827$11290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$libresoc.v:170827$11290_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:170828$11291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:170828$11291_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:170829$11292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:170829$11292_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:170830$11293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:170830$11293_Y + end + attribute \src "libresoc.v:170750.7-170750.20" + process $proc$libresoc.v:170750$11371 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:170775.13-170775.31" + process $proc$libresoc.v:170775$11372 + assign { } { } + assign $1\r24__data_o[3:0] 4'0000 + sync always + sync init + update \r24__data_o $1\r24__data_o[3:0] + end + attribute \src "libresoc.v:170782.13-170782.30" + process $proc$libresoc.v:170782$11373 + assign { } { } + assign $1\r4__data_o[3:0] 4'0000 + sync always + sync init + update \r4__data_o $1\r4__data_o[3:0] + end + attribute \src "libresoc.v:170788.13-170788.25" + process $proc$libresoc.v:170788$11374 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "libresoc.v:170793.13-170793.33" + process $proc$libresoc.v:170793$11375 + assign { } { } + assign $1\src14__data_o[3:0] 4'0000 + sync always + sync init + update \src14__data_o $1\src14__data_o[3:0] + end + attribute \src "libresoc.v:170800.13-170800.33" + process $proc$libresoc.v:170800$11376 + assign { } { } + assign $1\src24__data_o[3:0] 4'0000 + sync always + sync init + update \src24__data_o $1\src24__data_o[3:0] + end + attribute \src "libresoc.v:170807.13-170807.33" + process $proc$libresoc.v:170807$11377 + assign { } { } + assign $1\src34__data_o[3:0] 4'0000 + sync always + sync init + update \src34__data_o $1\src34__data_o[3:0] + end + attribute \src "libresoc.v:170831.3-170832.25" + process $proc$libresoc.v:170831$11294 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "libresoc.v:170833.3-170834.39" + process $proc$libresoc.v:170833$11295 + assign { } { } + assign $0\r24__data_o[3:0] \r24__data_o$next + sync posedge \coresync_clk + update \r24__data_o $0\r24__data_o[3:0] + end + attribute \src "libresoc.v:170835.3-170836.37" + process $proc$libresoc.v:170835$11296 + assign { } { } + assign $0\r4__data_o[3:0] \r4__data_o$next + sync posedge \coresync_clk + update \r4__data_o $0\r4__data_o[3:0] + end + attribute \src "libresoc.v:170837.3-170838.43" + process $proc$libresoc.v:170837$11297 + assign { } { } + assign $0\src34__data_o[3:0] \src34__data_o$next + sync posedge \coresync_clk + update \src34__data_o $0\src34__data_o[3:0] + end + attribute \src "libresoc.v:170839.3-170840.43" + process $proc$libresoc.v:170839$11298 + assign { } { } + assign $0\src24__data_o[3:0] \src24__data_o$next + sync posedge \coresync_clk + update \src24__data_o $0\src24__data_o[3:0] + end + attribute \src "libresoc.v:170841.3-170842.43" + process $proc$libresoc.v:170841$11299 + assign { } { } + assign $0\src14__data_o[3:0] \src14__data_o$next + sync posedge \coresync_clk + update \src14__data_o $0\src14__data_o[3:0] + end + attribute \src "libresoc.v:170843.3-170882.6" + process $proc$libresoc.v:170843$11300 + assign { } { } + assign { } { } + assign { } { } + assign $0\src14__data_o$next[3:0]$11301 $6\src14__data_o$next[3:0]$11307 + attribute \src "libresoc.v:170844.5-170844.29" + switch \initial + attribute \src "libresoc.v:170844.9-170844.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src14__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src14__data_o$next[3:0]$11302 $5\src14__data_o$next[3:0]$11306 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src14__data_o$next[3:0]$11303 \dest14__data_i + case + assign $2\src14__data_o$next[3:0]$11303 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src14__data_o$next[3:0]$11304 \dest24__data_i + case + assign $3\src14__data_o$next[3:0]$11304 $2\src14__data_o$next[3:0]$11303 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src14__data_o$next[3:0]$11305 \w4__data_i + case + assign $4\src14__data_o$next[3:0]$11305 $3\src14__data_o$next[3:0]$11304 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src14__data_o$next[3:0]$11306 \reg + case + assign $5\src14__data_o$next[3:0]$11306 $4\src14__data_o$next[3:0]$11305 + end + case + assign $1\src14__data_o$next[3:0]$11302 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src14__data_o$next[3:0]$11307 4'0000 + case + assign $6\src14__data_o$next[3:0]$11307 $1\src14__data_o$next[3:0]$11302 + end + sync always + update \src14__data_o$next $0\src14__data_o$next[3:0]$11301 + end + attribute \src "libresoc.v:170883.3-170912.6" + process $proc$libresoc.v:170883$11308 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:170884.5-170884.29" + switch \initial + attribute \src "libresoc.v:170884.9-170884.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src14__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:170913.3-170939.6" + process $proc$libresoc.v:170913$11309 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$11310 $4\reg$next[3:0]$11314 + attribute \src "libresoc.v:170914.5-170914.29" + switch \initial + attribute \src "libresoc.v:170914.9-170914.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$11311 \dest14__data_i + case + assign $1\reg$next[3:0]$11311 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$11312 \dest24__data_i + case + assign $2\reg$next[3:0]$11312 $1\reg$next[3:0]$11311 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$11313 \w4__data_i + case + assign $3\reg$next[3:0]$11313 $2\reg$next[3:0]$11312 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$11314 4'0000 + case + assign $4\reg$next[3:0]$11314 $3\reg$next[3:0]$11313 + end + sync always + update \reg$next $0\reg$next[3:0]$11310 + end + attribute \src "libresoc.v:170940.3-170979.6" + process $proc$libresoc.v:170940$11315 + assign { } { } + assign { } { } + assign { } { } + assign $0\src24__data_o$next[3:0]$11316 $6\src24__data_o$next[3:0]$11322 + attribute \src "libresoc.v:170941.5-170941.29" + switch \initial + attribute \src "libresoc.v:170941.9-170941.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src24__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src24__data_o$next[3:0]$11317 $5\src24__data_o$next[3:0]$11321 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src24__data_o$next[3:0]$11318 \dest14__data_i + case + assign $2\src24__data_o$next[3:0]$11318 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src24__data_o$next[3:0]$11319 \dest24__data_i + case + assign $3\src24__data_o$next[3:0]$11319 $2\src24__data_o$next[3:0]$11318 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src24__data_o$next[3:0]$11320 \w4__data_i + case + assign $4\src24__data_o$next[3:0]$11320 $3\src24__data_o$next[3:0]$11319 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src24__data_o$next[3:0]$11321 \reg + case + assign $5\src24__data_o$next[3:0]$11321 $4\src24__data_o$next[3:0]$11320 + end + case + assign $1\src24__data_o$next[3:0]$11317 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src24__data_o$next[3:0]$11322 4'0000 + case + assign $6\src24__data_o$next[3:0]$11322 $1\src24__data_o$next[3:0]$11317 + end + sync always + update \src24__data_o$next $0\src24__data_o$next[3:0]$11316 + end + attribute \src "libresoc.v:170980.3-171009.6" + process $proc$libresoc.v:170980$11323 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$11324 $1\wr_detect$4[0:0]$11325 + attribute \src "libresoc.v:170981.5-170981.29" + switch \initial + attribute \src "libresoc.v:170981.9-170981.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src24__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$11325 $4\wr_detect$4[0:0]$11328 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$11326 1'1 + case + assign $2\wr_detect$4[0:0]$11326 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$11327 1'1 + case + assign $3\wr_detect$4[0:0]$11327 $2\wr_detect$4[0:0]$11326 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$11328 1'1 + case + assign $4\wr_detect$4[0:0]$11328 $3\wr_detect$4[0:0]$11327 + end + case + assign $1\wr_detect$4[0:0]$11325 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$11324 + end + attribute \src "libresoc.v:171010.3-171049.6" + process $proc$libresoc.v:171010$11329 + assign { } { } + assign { } { } + assign { } { } + assign $0\src34__data_o$next[3:0]$11330 $6\src34__data_o$next[3:0]$11336 + attribute \src "libresoc.v:171011.5-171011.29" + switch \initial + attribute \src "libresoc.v:171011.9-171011.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src34__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src34__data_o$next[3:0]$11331 $5\src34__data_o$next[3:0]$11335 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src34__data_o$next[3:0]$11332 \dest14__data_i + case + assign $2\src34__data_o$next[3:0]$11332 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src34__data_o$next[3:0]$11333 \dest24__data_i + case + assign $3\src34__data_o$next[3:0]$11333 $2\src34__data_o$next[3:0]$11332 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src34__data_o$next[3:0]$11334 \w4__data_i + case + assign $4\src34__data_o$next[3:0]$11334 $3\src34__data_o$next[3:0]$11333 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src34__data_o$next[3:0]$11335 \reg + case + assign $5\src34__data_o$next[3:0]$11335 $4\src34__data_o$next[3:0]$11334 + end + case + assign $1\src34__data_o$next[3:0]$11331 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src34__data_o$next[3:0]$11336 4'0000 + case + assign $6\src34__data_o$next[3:0]$11336 $1\src34__data_o$next[3:0]$11331 + end + sync always + update \src34__data_o$next $0\src34__data_o$next[3:0]$11330 + end + attribute \src "libresoc.v:171050.3-171079.6" + process $proc$libresoc.v:171050$11337 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$11338 $1\wr_detect$7[0:0]$11339 + attribute \src "libresoc.v:171051.5-171051.29" + switch \initial + attribute \src "libresoc.v:171051.9-171051.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src34__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$11339 $4\wr_detect$7[0:0]$11342 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$11340 1'1 + case + assign $2\wr_detect$7[0:0]$11340 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$11341 1'1 + case + assign $3\wr_detect$7[0:0]$11341 $2\wr_detect$7[0:0]$11340 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$11342 1'1 + case + assign $4\wr_detect$7[0:0]$11342 $3\wr_detect$7[0:0]$11341 + end + case + assign $1\wr_detect$7[0:0]$11339 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$11338 + end + attribute \src "libresoc.v:171080.3-171119.6" + process $proc$libresoc.v:171080$11343 + assign { } { } + assign { } { } + assign { } { } + assign $0\r4__data_o$next[3:0]$11344 $6\r4__data_o$next[3:0]$11350 + attribute \src "libresoc.v:171081.5-171081.29" + switch \initial + attribute \src "libresoc.v:171081.9-171081.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r4__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r4__data_o$next[3:0]$11345 $5\r4__data_o$next[3:0]$11349 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r4__data_o$next[3:0]$11346 \dest14__data_i + case + assign $2\r4__data_o$next[3:0]$11346 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r4__data_o$next[3:0]$11347 \dest24__data_i + case + assign $3\r4__data_o$next[3:0]$11347 $2\r4__data_o$next[3:0]$11346 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r4__data_o$next[3:0]$11348 \w4__data_i + case + assign $4\r4__data_o$next[3:0]$11348 $3\r4__data_o$next[3:0]$11347 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r4__data_o$next[3:0]$11349 \reg + case + assign $5\r4__data_o$next[3:0]$11349 $4\r4__data_o$next[3:0]$11348 + end + case + assign $1\r4__data_o$next[3:0]$11345 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r4__data_o$next[3:0]$11350 4'0000 + case + assign $6\r4__data_o$next[3:0]$11350 $1\r4__data_o$next[3:0]$11345 + end + sync always + update \r4__data_o$next $0\r4__data_o$next[3:0]$11344 + end + attribute \src "libresoc.v:171120.3-171149.6" + process $proc$libresoc.v:171120$11351 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$11352 $1\wr_detect$10[0:0]$11353 + attribute \src "libresoc.v:171121.5-171121.29" + switch \initial + attribute \src "libresoc.v:171121.9-171121.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r4__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$11353 $4\wr_detect$10[0:0]$11356 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$11354 1'1 + case + assign $2\wr_detect$10[0:0]$11354 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$11355 1'1 + case + assign $3\wr_detect$10[0:0]$11355 $2\wr_detect$10[0:0]$11354 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$11356 1'1 + case + assign $4\wr_detect$10[0:0]$11356 $3\wr_detect$10[0:0]$11355 + end + case + assign $1\wr_detect$10[0:0]$11353 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$11352 + end + attribute \src "libresoc.v:171150.3-171189.6" + process $proc$libresoc.v:171150$11357 + assign { } { } + assign { } { } + assign { } { } + assign $0\r24__data_o$next[3:0]$11358 $6\r24__data_o$next[3:0]$11364 + attribute \src "libresoc.v:171151.5-171151.29" + switch \initial + attribute \src "libresoc.v:171151.9-171151.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r24__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r24__data_o$next[3:0]$11359 $5\r24__data_o$next[3:0]$11363 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r24__data_o$next[3:0]$11360 \dest14__data_i + case + assign $2\r24__data_o$next[3:0]$11360 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r24__data_o$next[3:0]$11361 \dest24__data_i + case + assign $3\r24__data_o$next[3:0]$11361 $2\r24__data_o$next[3:0]$11360 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r24__data_o$next[3:0]$11362 \w4__data_i + case + assign $4\r24__data_o$next[3:0]$11362 $3\r24__data_o$next[3:0]$11361 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r24__data_o$next[3:0]$11363 \reg + case + assign $5\r24__data_o$next[3:0]$11363 $4\r24__data_o$next[3:0]$11362 + end + case + assign $1\r24__data_o$next[3:0]$11359 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r24__data_o$next[3:0]$11364 4'0000 + case + assign $6\r24__data_o$next[3:0]$11364 $1\r24__data_o$next[3:0]$11359 + end + sync always + update \r24__data_o$next $0\r24__data_o$next[3:0]$11358 + end + attribute \src "libresoc.v:171190.3-171219.6" + process $proc$libresoc.v:171190$11365 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$11366 $1\wr_detect$13[0:0]$11367 + attribute \src "libresoc.v:171191.5-171191.29" + switch \initial + attribute \src "libresoc.v:171191.9-171191.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r24__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$11367 $4\wr_detect$13[0:0]$11370 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$11368 1'1 + case + assign $2\wr_detect$13[0:0]$11368 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$11369 1'1 + case + assign $3\wr_detect$13[0:0]$11369 $2\wr_detect$13[0:0]$11368 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$11370 1'1 + case + assign $4\wr_detect$13[0:0]$11370 $3\wr_detect$13[0:0]$11369 + end + case + assign $1\wr_detect$13[0:0]$11367 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$11366 + end + connect \$9 $not$libresoc.v:170826$11289_Y + connect \$12 $not$libresoc.v:170827$11290_Y + connect \$1 $not$libresoc.v:170828$11291_Y + connect \$3 $not$libresoc.v:170829$11292_Y + connect \$6 $not$libresoc.v:170830$11293_Y +end +attribute \src "libresoc.v:171224.1-171695.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_5" +attribute \generator "nMigen" +module \reg_5 + attribute \src "libresoc.v:171225.7-171225.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:171625.3-171664.6" + wire width 4 $0\r25__data_o$next[3:0]$11447 + attribute \src "libresoc.v:171308.3-171309.39" + wire width 4 $0\r25__data_o[3:0] + attribute \src "libresoc.v:171555.3-171594.6" + wire width 4 $0\r5__data_o$next[3:0]$11433 + attribute \src "libresoc.v:171310.3-171311.37" + wire width 4 $0\r5__data_o[3:0] + attribute \src "libresoc.v:171388.3-171414.6" + wire width 4 $0\reg$next[3:0]$11399 + attribute \src "libresoc.v:171306.3-171307.25" + wire width 4 $0\reg[3:0] + attribute \src "libresoc.v:171318.3-171357.6" + wire width 4 $0\src15__data_o$next[3:0]$11390 + attribute \src "libresoc.v:171316.3-171317.43" + wire width 4 $0\src15__data_o[3:0] + attribute \src "libresoc.v:171415.3-171454.6" + wire width 4 $0\src25__data_o$next[3:0]$11405 + attribute \src "libresoc.v:171314.3-171315.43" + wire width 4 $0\src25__data_o[3:0] + attribute \src "libresoc.v:171485.3-171524.6" + wire width 4 $0\src35__data_o$next[3:0]$11419 + attribute \src "libresoc.v:171312.3-171313.43" + wire width 4 $0\src35__data_o[3:0] + attribute \src "libresoc.v:171595.3-171624.6" + wire $0\wr_detect$10[0:0]$11441 + attribute \src "libresoc.v:171665.3-171694.6" + wire $0\wr_detect$13[0:0]$11455 + attribute \src "libresoc.v:171455.3-171484.6" + wire $0\wr_detect$4[0:0]$11413 + attribute \src "libresoc.v:171525.3-171554.6" + wire $0\wr_detect$7[0:0]$11427 + attribute \src "libresoc.v:171358.3-171387.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:171625.3-171664.6" + wire width 4 $1\r25__data_o$next[3:0]$11448 + attribute \src "libresoc.v:171250.13-171250.31" + wire width 4 $1\r25__data_o[3:0] + attribute \src "libresoc.v:171555.3-171594.6" + wire width 4 $1\r5__data_o$next[3:0]$11434 + attribute \src "libresoc.v:171257.13-171257.30" + wire width 4 $1\r5__data_o[3:0] + attribute \src "libresoc.v:171388.3-171414.6" + wire width 4 $1\reg$next[3:0]$11400 + attribute \src "libresoc.v:171263.13-171263.25" + wire width 4 $1\reg[3:0] + attribute \src "libresoc.v:171318.3-171357.6" + wire width 4 $1\src15__data_o$next[3:0]$11391 + attribute \src "libresoc.v:171268.13-171268.33" + wire width 4 $1\src15__data_o[3:0] + attribute \src "libresoc.v:171415.3-171454.6" + wire width 4 $1\src25__data_o$next[3:0]$11406 + attribute \src "libresoc.v:171275.13-171275.33" + wire width 4 $1\src25__data_o[3:0] + attribute \src "libresoc.v:171485.3-171524.6" + wire width 4 $1\src35__data_o$next[3:0]$11420 + attribute \src "libresoc.v:171282.13-171282.33" + wire width 4 $1\src35__data_o[3:0] + attribute \src "libresoc.v:171595.3-171624.6" + wire $1\wr_detect$10[0:0]$11442 + attribute \src "libresoc.v:171665.3-171694.6" + wire $1\wr_detect$13[0:0]$11456 + attribute \src "libresoc.v:171455.3-171484.6" + wire $1\wr_detect$4[0:0]$11414 + attribute \src "libresoc.v:171525.3-171554.6" + wire $1\wr_detect$7[0:0]$11428 + attribute \src "libresoc.v:171358.3-171387.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:171625.3-171664.6" + wire width 4 $2\r25__data_o$next[3:0]$11449 + attribute \src "libresoc.v:171555.3-171594.6" + wire width 4 $2\r5__data_o$next[3:0]$11435 + attribute \src "libresoc.v:171388.3-171414.6" + wire width 4 $2\reg$next[3:0]$11401 + attribute \src "libresoc.v:171318.3-171357.6" + wire width 4 $2\src15__data_o$next[3:0]$11392 + attribute \src "libresoc.v:171415.3-171454.6" + wire width 4 $2\src25__data_o$next[3:0]$11407 + attribute \src "libresoc.v:171485.3-171524.6" + wire width 4 $2\src35__data_o$next[3:0]$11421 + attribute \src "libresoc.v:171595.3-171624.6" + wire $2\wr_detect$10[0:0]$11443 + attribute \src "libresoc.v:171665.3-171694.6" + wire $2\wr_detect$13[0:0]$11457 + attribute \src "libresoc.v:171455.3-171484.6" + wire $2\wr_detect$4[0:0]$11415 + attribute \src "libresoc.v:171525.3-171554.6" + wire $2\wr_detect$7[0:0]$11429 + attribute \src "libresoc.v:171358.3-171387.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:171625.3-171664.6" + wire width 4 $3\r25__data_o$next[3:0]$11450 + attribute \src "libresoc.v:171555.3-171594.6" + wire width 4 $3\r5__data_o$next[3:0]$11436 + attribute \src "libresoc.v:171388.3-171414.6" + wire width 4 $3\reg$next[3:0]$11402 + attribute \src "libresoc.v:171318.3-171357.6" + wire width 4 $3\src15__data_o$next[3:0]$11393 + attribute \src "libresoc.v:171415.3-171454.6" + wire width 4 $3\src25__data_o$next[3:0]$11408 + attribute \src "libresoc.v:171485.3-171524.6" + wire width 4 $3\src35__data_o$next[3:0]$11422 + attribute \src "libresoc.v:171595.3-171624.6" + wire $3\wr_detect$10[0:0]$11444 + attribute \src "libresoc.v:171665.3-171694.6" + wire $3\wr_detect$13[0:0]$11458 + attribute \src "libresoc.v:171455.3-171484.6" + wire $3\wr_detect$4[0:0]$11416 + attribute \src "libresoc.v:171525.3-171554.6" + wire $3\wr_detect$7[0:0]$11430 + attribute \src "libresoc.v:171358.3-171387.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:171625.3-171664.6" + wire width 4 $4\r25__data_o$next[3:0]$11451 + attribute \src "libresoc.v:171555.3-171594.6" + wire width 4 $4\r5__data_o$next[3:0]$11437 + attribute \src "libresoc.v:171388.3-171414.6" + wire width 4 $4\reg$next[3:0]$11403 + attribute \src "libresoc.v:171318.3-171357.6" + wire width 4 $4\src15__data_o$next[3:0]$11394 + attribute \src "libresoc.v:171415.3-171454.6" + wire width 4 $4\src25__data_o$next[3:0]$11409 + attribute \src "libresoc.v:171485.3-171524.6" + wire width 4 $4\src35__data_o$next[3:0]$11423 + attribute \src "libresoc.v:171595.3-171624.6" + wire $4\wr_detect$10[0:0]$11445 + attribute \src "libresoc.v:171665.3-171694.6" + wire $4\wr_detect$13[0:0]$11459 + attribute \src "libresoc.v:171455.3-171484.6" + wire $4\wr_detect$4[0:0]$11417 + attribute \src "libresoc.v:171525.3-171554.6" + wire $4\wr_detect$7[0:0]$11431 + attribute \src "libresoc.v:171358.3-171387.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:171625.3-171664.6" + wire width 4 $5\r25__data_o$next[3:0]$11452 + attribute \src "libresoc.v:171555.3-171594.6" + wire width 4 $5\r5__data_o$next[3:0]$11438 + attribute \src "libresoc.v:171318.3-171357.6" + wire width 4 $5\src15__data_o$next[3:0]$11395 + attribute \src "libresoc.v:171415.3-171454.6" + wire width 4 $5\src25__data_o$next[3:0]$11410 + attribute \src "libresoc.v:171485.3-171524.6" + wire width 4 $5\src35__data_o$next[3:0]$11424 + attribute \src "libresoc.v:171625.3-171664.6" + wire width 4 $6\r25__data_o$next[3:0]$11453 + attribute \src "libresoc.v:171555.3-171594.6" + wire width 4 $6\r5__data_o$next[3:0]$11439 + attribute \src "libresoc.v:171318.3-171357.6" + wire width 4 $6\src15__data_o$next[3:0]$11396 + attribute \src "libresoc.v:171415.3-171454.6" + wire width 4 $6\src25__data_o$next[3:0]$11411 + attribute \src "libresoc.v:171485.3-171524.6" + wire width 4 $6\src35__data_o$next[3:0]$11425 + attribute \src "libresoc.v:171301.17-171301.104" + wire $not$libresoc.v:171301$11378_Y + attribute \src "libresoc.v:171302.18-171302.105" + wire $not$libresoc.v:171302$11379_Y + attribute \src "libresoc.v:171303.17-171303.100" + wire $not$libresoc.v:171303$11380_Y + attribute \src "libresoc.v:171304.17-171304.103" + wire $not$libresoc.v:171304$11381_Y + attribute \src "libresoc.v:171305.17-171305.103" + wire $not$libresoc.v:171305$11382_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 9 \dest15__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \dest15__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 11 \dest25__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \dest25__wen + attribute \src "libresoc.v:171225.7-171225.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 14 \r25__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r25__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 15 \r25__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 12 \r5__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r5__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 13 \r5__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 3 \src15__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src15__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \src15__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 5 \src25__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src25__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \src25__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 7 \src35__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src35__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \src35__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 16 \w5__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 17 \w5__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:171301$11378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:171301$11378_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:171302$11379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$libresoc.v:171302$11379_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:171303$11380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:171303$11380_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:171304$11381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:171304$11381_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:171305$11382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:171305$11382_Y + end + attribute \src "libresoc.v:171225.7-171225.20" + process $proc$libresoc.v:171225$11460 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:171250.13-171250.31" + process $proc$libresoc.v:171250$11461 + assign { } { } + assign $1\r25__data_o[3:0] 4'0000 + sync always + sync init + update \r25__data_o $1\r25__data_o[3:0] + end + attribute \src "libresoc.v:171257.13-171257.30" + process $proc$libresoc.v:171257$11462 + assign { } { } + assign $1\r5__data_o[3:0] 4'0000 + sync always + sync init + update \r5__data_o $1\r5__data_o[3:0] + end + attribute \src "libresoc.v:171263.13-171263.25" + process $proc$libresoc.v:171263$11463 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "libresoc.v:171268.13-171268.33" + process $proc$libresoc.v:171268$11464 + assign { } { } + assign $1\src15__data_o[3:0] 4'0000 + sync always + sync init + update \src15__data_o $1\src15__data_o[3:0] + end + attribute \src "libresoc.v:171275.13-171275.33" + process $proc$libresoc.v:171275$11465 + assign { } { } + assign $1\src25__data_o[3:0] 4'0000 + sync always + sync init + update \src25__data_o $1\src25__data_o[3:0] + end + attribute \src "libresoc.v:171282.13-171282.33" + process $proc$libresoc.v:171282$11466 + assign { } { } + assign $1\src35__data_o[3:0] 4'0000 + sync always + sync init + update \src35__data_o $1\src35__data_o[3:0] + end + attribute \src "libresoc.v:171306.3-171307.25" + process $proc$libresoc.v:171306$11383 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "libresoc.v:171308.3-171309.39" + process $proc$libresoc.v:171308$11384 + assign { } { } + assign $0\r25__data_o[3:0] \r25__data_o$next + sync posedge \coresync_clk + update \r25__data_o $0\r25__data_o[3:0] + end + attribute \src "libresoc.v:171310.3-171311.37" + process $proc$libresoc.v:171310$11385 + assign { } { } + assign $0\r5__data_o[3:0] \r5__data_o$next + sync posedge \coresync_clk + update \r5__data_o $0\r5__data_o[3:0] + end + attribute \src "libresoc.v:171312.3-171313.43" + process $proc$libresoc.v:171312$11386 + assign { } { } + assign $0\src35__data_o[3:0] \src35__data_o$next + sync posedge \coresync_clk + update \src35__data_o $0\src35__data_o[3:0] + end + attribute \src "libresoc.v:171314.3-171315.43" + process $proc$libresoc.v:171314$11387 + assign { } { } + assign $0\src25__data_o[3:0] \src25__data_o$next + sync posedge \coresync_clk + update \src25__data_o $0\src25__data_o[3:0] + end + attribute \src "libresoc.v:171316.3-171317.43" + process $proc$libresoc.v:171316$11388 + assign { } { } + assign $0\src15__data_o[3:0] \src15__data_o$next + sync posedge \coresync_clk + update \src15__data_o $0\src15__data_o[3:0] + end + attribute \src "libresoc.v:171318.3-171357.6" + process $proc$libresoc.v:171318$11389 + assign { } { } + assign { } { } + assign { } { } + assign $0\src15__data_o$next[3:0]$11390 $6\src15__data_o$next[3:0]$11396 + attribute \src "libresoc.v:171319.5-171319.29" + switch \initial + attribute \src "libresoc.v:171319.9-171319.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src15__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src15__data_o$next[3:0]$11391 $5\src15__data_o$next[3:0]$11395 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src15__data_o$next[3:0]$11392 \dest15__data_i + case + assign $2\src15__data_o$next[3:0]$11392 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src15__data_o$next[3:0]$11393 \dest25__data_i + case + assign $3\src15__data_o$next[3:0]$11393 $2\src15__data_o$next[3:0]$11392 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src15__data_o$next[3:0]$11394 \w5__data_i + case + assign $4\src15__data_o$next[3:0]$11394 $3\src15__data_o$next[3:0]$11393 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src15__data_o$next[3:0]$11395 \reg + case + assign $5\src15__data_o$next[3:0]$11395 $4\src15__data_o$next[3:0]$11394 + end + case + assign $1\src15__data_o$next[3:0]$11391 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src15__data_o$next[3:0]$11396 4'0000 + case + assign $6\src15__data_o$next[3:0]$11396 $1\src15__data_o$next[3:0]$11391 + end + sync always + update \src15__data_o$next $0\src15__data_o$next[3:0]$11390 + end + attribute \src "libresoc.v:171358.3-171387.6" + process $proc$libresoc.v:171358$11397 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:171359.5-171359.29" + switch \initial + attribute \src "libresoc.v:171359.9-171359.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src15__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:171388.3-171414.6" + process $proc$libresoc.v:171388$11398 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$11399 $4\reg$next[3:0]$11403 + attribute \src "libresoc.v:171389.5-171389.29" + switch \initial + attribute \src "libresoc.v:171389.9-171389.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$11400 \dest15__data_i + case + assign $1\reg$next[3:0]$11400 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$11401 \dest25__data_i + case + assign $2\reg$next[3:0]$11401 $1\reg$next[3:0]$11400 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$11402 \w5__data_i + case + assign $3\reg$next[3:0]$11402 $2\reg$next[3:0]$11401 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$11403 4'0000 + case + assign $4\reg$next[3:0]$11403 $3\reg$next[3:0]$11402 + end + sync always + update \reg$next $0\reg$next[3:0]$11399 + end + attribute \src "libresoc.v:171415.3-171454.6" + process $proc$libresoc.v:171415$11404 + assign { } { } + assign { } { } + assign { } { } + assign $0\src25__data_o$next[3:0]$11405 $6\src25__data_o$next[3:0]$11411 + attribute \src "libresoc.v:171416.5-171416.29" + switch \initial + attribute \src "libresoc.v:171416.9-171416.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src25__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src25__data_o$next[3:0]$11406 $5\src25__data_o$next[3:0]$11410 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src25__data_o$next[3:0]$11407 \dest15__data_i + case + assign $2\src25__data_o$next[3:0]$11407 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src25__data_o$next[3:0]$11408 \dest25__data_i + case + assign $3\src25__data_o$next[3:0]$11408 $2\src25__data_o$next[3:0]$11407 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src25__data_o$next[3:0]$11409 \w5__data_i + case + assign $4\src25__data_o$next[3:0]$11409 $3\src25__data_o$next[3:0]$11408 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src25__data_o$next[3:0]$11410 \reg + case + assign $5\src25__data_o$next[3:0]$11410 $4\src25__data_o$next[3:0]$11409 + end + case + assign $1\src25__data_o$next[3:0]$11406 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src25__data_o$next[3:0]$11411 4'0000 + case + assign $6\src25__data_o$next[3:0]$11411 $1\src25__data_o$next[3:0]$11406 + end + sync always + update \src25__data_o$next $0\src25__data_o$next[3:0]$11405 + end + attribute \src "libresoc.v:171455.3-171484.6" + process $proc$libresoc.v:171455$11412 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$11413 $1\wr_detect$4[0:0]$11414 + attribute \src "libresoc.v:171456.5-171456.29" + switch \initial + attribute \src "libresoc.v:171456.9-171456.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src25__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$11414 $4\wr_detect$4[0:0]$11417 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$11415 1'1 + case + assign $2\wr_detect$4[0:0]$11415 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$11416 1'1 + case + assign $3\wr_detect$4[0:0]$11416 $2\wr_detect$4[0:0]$11415 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$11417 1'1 + case + assign $4\wr_detect$4[0:0]$11417 $3\wr_detect$4[0:0]$11416 + end + case + assign $1\wr_detect$4[0:0]$11414 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$11413 + end + attribute \src "libresoc.v:171485.3-171524.6" + process $proc$libresoc.v:171485$11418 + assign { } { } + assign { } { } + assign { } { } + assign $0\src35__data_o$next[3:0]$11419 $6\src35__data_o$next[3:0]$11425 + attribute \src "libresoc.v:171486.5-171486.29" + switch \initial + attribute \src "libresoc.v:171486.9-171486.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src35__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src35__data_o$next[3:0]$11420 $5\src35__data_o$next[3:0]$11424 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src35__data_o$next[3:0]$11421 \dest15__data_i + case + assign $2\src35__data_o$next[3:0]$11421 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src35__data_o$next[3:0]$11422 \dest25__data_i + case + assign $3\src35__data_o$next[3:0]$11422 $2\src35__data_o$next[3:0]$11421 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src35__data_o$next[3:0]$11423 \w5__data_i + case + assign $4\src35__data_o$next[3:0]$11423 $3\src35__data_o$next[3:0]$11422 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src35__data_o$next[3:0]$11424 \reg + case + assign $5\src35__data_o$next[3:0]$11424 $4\src35__data_o$next[3:0]$11423 + end + case + assign $1\src35__data_o$next[3:0]$11420 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src35__data_o$next[3:0]$11425 4'0000 + case + assign $6\src35__data_o$next[3:0]$11425 $1\src35__data_o$next[3:0]$11420 + end + sync always + update \src35__data_o$next $0\src35__data_o$next[3:0]$11419 + end + attribute \src "libresoc.v:171525.3-171554.6" + process $proc$libresoc.v:171525$11426 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$11427 $1\wr_detect$7[0:0]$11428 + attribute \src "libresoc.v:171526.5-171526.29" + switch \initial + attribute \src "libresoc.v:171526.9-171526.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src35__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$11428 $4\wr_detect$7[0:0]$11431 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$11429 1'1 + case + assign $2\wr_detect$7[0:0]$11429 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$11430 1'1 + case + assign $3\wr_detect$7[0:0]$11430 $2\wr_detect$7[0:0]$11429 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$11431 1'1 + case + assign $4\wr_detect$7[0:0]$11431 $3\wr_detect$7[0:0]$11430 + end + case + assign $1\wr_detect$7[0:0]$11428 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$11427 + end + attribute \src "libresoc.v:171555.3-171594.6" + process $proc$libresoc.v:171555$11432 + assign { } { } + assign { } { } + assign { } { } + assign $0\r5__data_o$next[3:0]$11433 $6\r5__data_o$next[3:0]$11439 + attribute \src "libresoc.v:171556.5-171556.29" + switch \initial + attribute \src "libresoc.v:171556.9-171556.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r5__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r5__data_o$next[3:0]$11434 $5\r5__data_o$next[3:0]$11438 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r5__data_o$next[3:0]$11435 \dest15__data_i + case + assign $2\r5__data_o$next[3:0]$11435 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r5__data_o$next[3:0]$11436 \dest25__data_i + case + assign $3\r5__data_o$next[3:0]$11436 $2\r5__data_o$next[3:0]$11435 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r5__data_o$next[3:0]$11437 \w5__data_i + case + assign $4\r5__data_o$next[3:0]$11437 $3\r5__data_o$next[3:0]$11436 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r5__data_o$next[3:0]$11438 \reg + case + assign $5\r5__data_o$next[3:0]$11438 $4\r5__data_o$next[3:0]$11437 + end + case + assign $1\r5__data_o$next[3:0]$11434 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r5__data_o$next[3:0]$11439 4'0000 + case + assign $6\r5__data_o$next[3:0]$11439 $1\r5__data_o$next[3:0]$11434 + end + sync always + update \r5__data_o$next $0\r5__data_o$next[3:0]$11433 + end + attribute \src "libresoc.v:171595.3-171624.6" + process $proc$libresoc.v:171595$11440 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$11441 $1\wr_detect$10[0:0]$11442 + attribute \src "libresoc.v:171596.5-171596.29" + switch \initial + attribute \src "libresoc.v:171596.9-171596.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r5__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$11442 $4\wr_detect$10[0:0]$11445 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$11443 1'1 + case + assign $2\wr_detect$10[0:0]$11443 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$11444 1'1 + case + assign $3\wr_detect$10[0:0]$11444 $2\wr_detect$10[0:0]$11443 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$11445 1'1 + case + assign $4\wr_detect$10[0:0]$11445 $3\wr_detect$10[0:0]$11444 + end + case + assign $1\wr_detect$10[0:0]$11442 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$11441 + end + attribute \src "libresoc.v:171625.3-171664.6" + process $proc$libresoc.v:171625$11446 + assign { } { } + assign { } { } + assign { } { } + assign $0\r25__data_o$next[3:0]$11447 $6\r25__data_o$next[3:0]$11453 + attribute \src "libresoc.v:171626.5-171626.29" + switch \initial + attribute \src "libresoc.v:171626.9-171626.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r25__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r25__data_o$next[3:0]$11448 $5\r25__data_o$next[3:0]$11452 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r25__data_o$next[3:0]$11449 \dest15__data_i + case + assign $2\r25__data_o$next[3:0]$11449 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r25__data_o$next[3:0]$11450 \dest25__data_i + case + assign $3\r25__data_o$next[3:0]$11450 $2\r25__data_o$next[3:0]$11449 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r25__data_o$next[3:0]$11451 \w5__data_i + case + assign $4\r25__data_o$next[3:0]$11451 $3\r25__data_o$next[3:0]$11450 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r25__data_o$next[3:0]$11452 \reg + case + assign $5\r25__data_o$next[3:0]$11452 $4\r25__data_o$next[3:0]$11451 + end + case + assign $1\r25__data_o$next[3:0]$11448 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r25__data_o$next[3:0]$11453 4'0000 + case + assign $6\r25__data_o$next[3:0]$11453 $1\r25__data_o$next[3:0]$11448 + end + sync always + update \r25__data_o$next $0\r25__data_o$next[3:0]$11447 + end + attribute \src "libresoc.v:171665.3-171694.6" + process $proc$libresoc.v:171665$11454 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$11455 $1\wr_detect$13[0:0]$11456 + attribute \src "libresoc.v:171666.5-171666.29" + switch \initial + attribute \src "libresoc.v:171666.9-171666.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r25__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$11456 $4\wr_detect$13[0:0]$11459 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$11457 1'1 + case + assign $2\wr_detect$13[0:0]$11457 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$11458 1'1 + case + assign $3\wr_detect$13[0:0]$11458 $2\wr_detect$13[0:0]$11457 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$11459 1'1 + case + assign $4\wr_detect$13[0:0]$11459 $3\wr_detect$13[0:0]$11458 + end + case + assign $1\wr_detect$13[0:0]$11456 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$11455 + end + connect \$9 $not$libresoc.v:171301$11378_Y + connect \$12 $not$libresoc.v:171302$11379_Y + connect \$1 $not$libresoc.v:171303$11380_Y + connect \$3 $not$libresoc.v:171304$11381_Y + connect \$6 $not$libresoc.v:171305$11382_Y +end +attribute \src "libresoc.v:171699.1-172170.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_6" +attribute \generator "nMigen" +module \reg_6 + attribute \src "libresoc.v:171700.7-171700.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:172100.3-172139.6" + wire width 4 $0\r26__data_o$next[3:0]$11536 + attribute \src "libresoc.v:171783.3-171784.39" + wire width 4 $0\r26__data_o[3:0] + attribute \src "libresoc.v:172030.3-172069.6" + wire width 4 $0\r6__data_o$next[3:0]$11522 + attribute \src "libresoc.v:171785.3-171786.37" + wire width 4 $0\r6__data_o[3:0] + attribute \src "libresoc.v:171863.3-171889.6" + wire width 4 $0\reg$next[3:0]$11488 + attribute \src "libresoc.v:171781.3-171782.25" + wire width 4 $0\reg[3:0] + attribute \src "libresoc.v:171793.3-171832.6" + wire width 4 $0\src16__data_o$next[3:0]$11479 + attribute \src "libresoc.v:171791.3-171792.43" + wire width 4 $0\src16__data_o[3:0] + attribute \src "libresoc.v:171890.3-171929.6" + wire width 4 $0\src26__data_o$next[3:0]$11494 + attribute \src "libresoc.v:171789.3-171790.43" + wire width 4 $0\src26__data_o[3:0] + attribute \src "libresoc.v:171960.3-171999.6" + wire width 4 $0\src36__data_o$next[3:0]$11508 + attribute \src "libresoc.v:171787.3-171788.43" + wire width 4 $0\src36__data_o[3:0] + attribute \src "libresoc.v:172070.3-172099.6" + wire $0\wr_detect$10[0:0]$11530 + attribute \src "libresoc.v:172140.3-172169.6" + wire $0\wr_detect$13[0:0]$11544 + attribute \src "libresoc.v:171930.3-171959.6" + wire $0\wr_detect$4[0:0]$11502 + attribute \src "libresoc.v:172000.3-172029.6" + wire $0\wr_detect$7[0:0]$11516 + attribute \src "libresoc.v:171833.3-171862.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:172100.3-172139.6" + wire width 4 $1\r26__data_o$next[3:0]$11537 + attribute \src "libresoc.v:171725.13-171725.31" + wire width 4 $1\r26__data_o[3:0] + attribute \src "libresoc.v:172030.3-172069.6" + wire width 4 $1\r6__data_o$next[3:0]$11523 + attribute \src "libresoc.v:171732.13-171732.30" + wire width 4 $1\r6__data_o[3:0] + attribute \src "libresoc.v:171863.3-171889.6" + wire width 4 $1\reg$next[3:0]$11489 + attribute \src "libresoc.v:171738.13-171738.25" + wire width 4 $1\reg[3:0] + attribute \src "libresoc.v:171793.3-171832.6" + wire width 4 $1\src16__data_o$next[3:0]$11480 + attribute \src "libresoc.v:171743.13-171743.33" + wire width 4 $1\src16__data_o[3:0] + attribute \src "libresoc.v:171890.3-171929.6" + wire width 4 $1\src26__data_o$next[3:0]$11495 + attribute \src "libresoc.v:171750.13-171750.33" + wire width 4 $1\src26__data_o[3:0] + attribute \src "libresoc.v:171960.3-171999.6" + wire width 4 $1\src36__data_o$next[3:0]$11509 + attribute \src "libresoc.v:171757.13-171757.33" + wire width 4 $1\src36__data_o[3:0] + attribute \src "libresoc.v:172070.3-172099.6" + wire $1\wr_detect$10[0:0]$11531 + attribute \src "libresoc.v:172140.3-172169.6" + wire $1\wr_detect$13[0:0]$11545 + attribute \src "libresoc.v:171930.3-171959.6" + wire $1\wr_detect$4[0:0]$11503 + attribute \src "libresoc.v:172000.3-172029.6" + wire $1\wr_detect$7[0:0]$11517 + attribute \src "libresoc.v:171833.3-171862.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:172100.3-172139.6" + wire width 4 $2\r26__data_o$next[3:0]$11538 + attribute \src "libresoc.v:172030.3-172069.6" + wire width 4 $2\r6__data_o$next[3:0]$11524 + attribute \src "libresoc.v:171863.3-171889.6" + wire width 4 $2\reg$next[3:0]$11490 + attribute \src "libresoc.v:171793.3-171832.6" + wire width 4 $2\src16__data_o$next[3:0]$11481 + attribute \src "libresoc.v:171890.3-171929.6" + wire width 4 $2\src26__data_o$next[3:0]$11496 + attribute \src "libresoc.v:171960.3-171999.6" + wire width 4 $2\src36__data_o$next[3:0]$11510 + attribute \src "libresoc.v:172070.3-172099.6" + wire $2\wr_detect$10[0:0]$11532 + attribute \src "libresoc.v:172140.3-172169.6" + wire $2\wr_detect$13[0:0]$11546 + attribute \src "libresoc.v:171930.3-171959.6" + wire $2\wr_detect$4[0:0]$11504 + attribute \src "libresoc.v:172000.3-172029.6" + wire $2\wr_detect$7[0:0]$11518 + attribute \src "libresoc.v:171833.3-171862.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:172100.3-172139.6" + wire width 4 $3\r26__data_o$next[3:0]$11539 + attribute \src "libresoc.v:172030.3-172069.6" + wire width 4 $3\r6__data_o$next[3:0]$11525 + attribute \src "libresoc.v:171863.3-171889.6" + wire width 4 $3\reg$next[3:0]$11491 + attribute \src "libresoc.v:171793.3-171832.6" + wire width 4 $3\src16__data_o$next[3:0]$11482 + attribute \src "libresoc.v:171890.3-171929.6" + wire width 4 $3\src26__data_o$next[3:0]$11497 + attribute \src "libresoc.v:171960.3-171999.6" + wire width 4 $3\src36__data_o$next[3:0]$11511 + attribute \src "libresoc.v:172070.3-172099.6" + wire $3\wr_detect$10[0:0]$11533 + attribute \src "libresoc.v:172140.3-172169.6" + wire $3\wr_detect$13[0:0]$11547 + attribute \src "libresoc.v:171930.3-171959.6" + wire $3\wr_detect$4[0:0]$11505 + attribute \src "libresoc.v:172000.3-172029.6" + wire $3\wr_detect$7[0:0]$11519 + attribute \src "libresoc.v:171833.3-171862.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:172100.3-172139.6" + wire width 4 $4\r26__data_o$next[3:0]$11540 + attribute \src "libresoc.v:172030.3-172069.6" + wire width 4 $4\r6__data_o$next[3:0]$11526 + attribute \src "libresoc.v:171863.3-171889.6" + wire width 4 $4\reg$next[3:0]$11492 + attribute \src "libresoc.v:171793.3-171832.6" + wire width 4 $4\src16__data_o$next[3:0]$11483 + attribute \src "libresoc.v:171890.3-171929.6" + wire width 4 $4\src26__data_o$next[3:0]$11498 + attribute \src "libresoc.v:171960.3-171999.6" + wire width 4 $4\src36__data_o$next[3:0]$11512 + attribute \src "libresoc.v:172070.3-172099.6" + wire $4\wr_detect$10[0:0]$11534 + attribute \src "libresoc.v:172140.3-172169.6" + wire $4\wr_detect$13[0:0]$11548 + attribute \src "libresoc.v:171930.3-171959.6" + wire $4\wr_detect$4[0:0]$11506 + attribute \src "libresoc.v:172000.3-172029.6" + wire $4\wr_detect$7[0:0]$11520 + attribute \src "libresoc.v:171833.3-171862.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:172100.3-172139.6" + wire width 4 $5\r26__data_o$next[3:0]$11541 + attribute \src "libresoc.v:172030.3-172069.6" + wire width 4 $5\r6__data_o$next[3:0]$11527 + attribute \src "libresoc.v:171793.3-171832.6" + wire width 4 $5\src16__data_o$next[3:0]$11484 + attribute \src "libresoc.v:171890.3-171929.6" + wire width 4 $5\src26__data_o$next[3:0]$11499 + attribute \src "libresoc.v:171960.3-171999.6" + wire width 4 $5\src36__data_o$next[3:0]$11513 + attribute \src "libresoc.v:172100.3-172139.6" + wire width 4 $6\r26__data_o$next[3:0]$11542 + attribute \src "libresoc.v:172030.3-172069.6" + wire width 4 $6\r6__data_o$next[3:0]$11528 + attribute \src "libresoc.v:171793.3-171832.6" + wire width 4 $6\src16__data_o$next[3:0]$11485 + attribute \src "libresoc.v:171890.3-171929.6" + wire width 4 $6\src26__data_o$next[3:0]$11500 + attribute \src "libresoc.v:171960.3-171999.6" + wire width 4 $6\src36__data_o$next[3:0]$11514 + attribute \src "libresoc.v:171776.17-171776.104" + wire $not$libresoc.v:171776$11467_Y + attribute \src "libresoc.v:171777.18-171777.105" + wire $not$libresoc.v:171777$11468_Y + attribute \src "libresoc.v:171778.17-171778.100" + wire $not$libresoc.v:171778$11469_Y + attribute \src "libresoc.v:171779.17-171779.103" + wire $not$libresoc.v:171779$11470_Y + attribute \src "libresoc.v:171780.17-171780.103" + wire $not$libresoc.v:171780$11471_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 9 \dest16__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \dest16__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 11 \dest26__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \dest26__wen + attribute \src "libresoc.v:171700.7-171700.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 14 \r26__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r26__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 15 \r26__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 12 \r6__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r6__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 13 \r6__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 3 \src16__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src16__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \src16__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 5 \src26__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src26__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \src26__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 7 \src36__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src36__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \src36__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 16 \w6__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 17 \w6__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:171776$11467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:171776$11467_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:171777$11468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$libresoc.v:171777$11468_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:171778$11469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:171778$11469_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:171779$11470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:171779$11470_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:171780$11471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:171780$11471_Y + end + attribute \src "libresoc.v:171700.7-171700.20" + process $proc$libresoc.v:171700$11549 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:171725.13-171725.31" + process $proc$libresoc.v:171725$11550 + assign { } { } + assign $1\r26__data_o[3:0] 4'0000 + sync always + sync init + update \r26__data_o $1\r26__data_o[3:0] + end + attribute \src "libresoc.v:171732.13-171732.30" + process $proc$libresoc.v:171732$11551 + assign { } { } + assign $1\r6__data_o[3:0] 4'0000 + sync always + sync init + update \r6__data_o $1\r6__data_o[3:0] + end + attribute \src "libresoc.v:171738.13-171738.25" + process $proc$libresoc.v:171738$11552 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "libresoc.v:171743.13-171743.33" + process $proc$libresoc.v:171743$11553 + assign { } { } + assign $1\src16__data_o[3:0] 4'0000 + sync always + sync init + update \src16__data_o $1\src16__data_o[3:0] + end + attribute \src "libresoc.v:171750.13-171750.33" + process $proc$libresoc.v:171750$11554 + assign { } { } + assign $1\src26__data_o[3:0] 4'0000 + sync always + sync init + update \src26__data_o $1\src26__data_o[3:0] + end + attribute \src "libresoc.v:171757.13-171757.33" + process $proc$libresoc.v:171757$11555 + assign { } { } + assign $1\src36__data_o[3:0] 4'0000 + sync always + sync init + update \src36__data_o $1\src36__data_o[3:0] + end + attribute \src "libresoc.v:171781.3-171782.25" + process $proc$libresoc.v:171781$11472 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "libresoc.v:171783.3-171784.39" + process $proc$libresoc.v:171783$11473 + assign { } { } + assign $0\r26__data_o[3:0] \r26__data_o$next + sync posedge \coresync_clk + update \r26__data_o $0\r26__data_o[3:0] + end + attribute \src "libresoc.v:171785.3-171786.37" + process $proc$libresoc.v:171785$11474 + assign { } { } + assign $0\r6__data_o[3:0] \r6__data_o$next + sync posedge \coresync_clk + update \r6__data_o $0\r6__data_o[3:0] + end + attribute \src "libresoc.v:171787.3-171788.43" + process $proc$libresoc.v:171787$11475 + assign { } { } + assign $0\src36__data_o[3:0] \src36__data_o$next + sync posedge \coresync_clk + update \src36__data_o $0\src36__data_o[3:0] + end + attribute \src "libresoc.v:171789.3-171790.43" + process $proc$libresoc.v:171789$11476 + assign { } { } + assign $0\src26__data_o[3:0] \src26__data_o$next + sync posedge \coresync_clk + update \src26__data_o $0\src26__data_o[3:0] + end + attribute \src "libresoc.v:171791.3-171792.43" + process $proc$libresoc.v:171791$11477 + assign { } { } + assign $0\src16__data_o[3:0] \src16__data_o$next + sync posedge \coresync_clk + update \src16__data_o $0\src16__data_o[3:0] + end + attribute \src "libresoc.v:171793.3-171832.6" + process $proc$libresoc.v:171793$11478 + assign { } { } + assign { } { } + assign { } { } + assign $0\src16__data_o$next[3:0]$11479 $6\src16__data_o$next[3:0]$11485 + attribute \src "libresoc.v:171794.5-171794.29" + switch \initial + attribute \src "libresoc.v:171794.9-171794.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src16__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src16__data_o$next[3:0]$11480 $5\src16__data_o$next[3:0]$11484 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src16__data_o$next[3:0]$11481 \dest16__data_i + case + assign $2\src16__data_o$next[3:0]$11481 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src16__data_o$next[3:0]$11482 \dest26__data_i + case + assign $3\src16__data_o$next[3:0]$11482 $2\src16__data_o$next[3:0]$11481 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src16__data_o$next[3:0]$11483 \w6__data_i + case + assign $4\src16__data_o$next[3:0]$11483 $3\src16__data_o$next[3:0]$11482 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src16__data_o$next[3:0]$11484 \reg + case + assign $5\src16__data_o$next[3:0]$11484 $4\src16__data_o$next[3:0]$11483 + end + case + assign $1\src16__data_o$next[3:0]$11480 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src16__data_o$next[3:0]$11485 4'0000 + case + assign $6\src16__data_o$next[3:0]$11485 $1\src16__data_o$next[3:0]$11480 + end + sync always + update \src16__data_o$next $0\src16__data_o$next[3:0]$11479 + end + attribute \src "libresoc.v:171833.3-171862.6" + process $proc$libresoc.v:171833$11486 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:171834.5-171834.29" + switch \initial + attribute \src "libresoc.v:171834.9-171834.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src16__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:171863.3-171889.6" + process $proc$libresoc.v:171863$11487 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$11488 $4\reg$next[3:0]$11492 + attribute \src "libresoc.v:171864.5-171864.29" + switch \initial + attribute \src "libresoc.v:171864.9-171864.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$11489 \dest16__data_i + case + assign $1\reg$next[3:0]$11489 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$11490 \dest26__data_i + case + assign $2\reg$next[3:0]$11490 $1\reg$next[3:0]$11489 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$11491 \w6__data_i + case + assign $3\reg$next[3:0]$11491 $2\reg$next[3:0]$11490 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$11492 4'0000 + case + assign $4\reg$next[3:0]$11492 $3\reg$next[3:0]$11491 + end + sync always + update \reg$next $0\reg$next[3:0]$11488 + end + attribute \src "libresoc.v:171890.3-171929.6" + process $proc$libresoc.v:171890$11493 + assign { } { } + assign { } { } + assign { } { } + assign $0\src26__data_o$next[3:0]$11494 $6\src26__data_o$next[3:0]$11500 + attribute \src "libresoc.v:171891.5-171891.29" + switch \initial + attribute \src "libresoc.v:171891.9-171891.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src26__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src26__data_o$next[3:0]$11495 $5\src26__data_o$next[3:0]$11499 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src26__data_o$next[3:0]$11496 \dest16__data_i + case + assign $2\src26__data_o$next[3:0]$11496 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src26__data_o$next[3:0]$11497 \dest26__data_i + case + assign $3\src26__data_o$next[3:0]$11497 $2\src26__data_o$next[3:0]$11496 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src26__data_o$next[3:0]$11498 \w6__data_i + case + assign $4\src26__data_o$next[3:0]$11498 $3\src26__data_o$next[3:0]$11497 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src26__data_o$next[3:0]$11499 \reg + case + assign $5\src26__data_o$next[3:0]$11499 $4\src26__data_o$next[3:0]$11498 + end + case + assign $1\src26__data_o$next[3:0]$11495 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src26__data_o$next[3:0]$11500 4'0000 + case + assign $6\src26__data_o$next[3:0]$11500 $1\src26__data_o$next[3:0]$11495 + end + sync always + update \src26__data_o$next $0\src26__data_o$next[3:0]$11494 + end + attribute \src "libresoc.v:171930.3-171959.6" + process $proc$libresoc.v:171930$11501 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$11502 $1\wr_detect$4[0:0]$11503 + attribute \src "libresoc.v:171931.5-171931.29" + switch \initial + attribute \src "libresoc.v:171931.9-171931.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src26__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$11503 $4\wr_detect$4[0:0]$11506 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$11504 1'1 + case + assign $2\wr_detect$4[0:0]$11504 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$11505 1'1 + case + assign $3\wr_detect$4[0:0]$11505 $2\wr_detect$4[0:0]$11504 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$11506 1'1 + case + assign $4\wr_detect$4[0:0]$11506 $3\wr_detect$4[0:0]$11505 + end + case + assign $1\wr_detect$4[0:0]$11503 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$11502 + end + attribute \src "libresoc.v:171960.3-171999.6" + process $proc$libresoc.v:171960$11507 + assign { } { } + assign { } { } + assign { } { } + assign $0\src36__data_o$next[3:0]$11508 $6\src36__data_o$next[3:0]$11514 + attribute \src "libresoc.v:171961.5-171961.29" + switch \initial + attribute \src "libresoc.v:171961.9-171961.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src36__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src36__data_o$next[3:0]$11509 $5\src36__data_o$next[3:0]$11513 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src36__data_o$next[3:0]$11510 \dest16__data_i + case + assign $2\src36__data_o$next[3:0]$11510 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src36__data_o$next[3:0]$11511 \dest26__data_i + case + assign $3\src36__data_o$next[3:0]$11511 $2\src36__data_o$next[3:0]$11510 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src36__data_o$next[3:0]$11512 \w6__data_i + case + assign $4\src36__data_o$next[3:0]$11512 $3\src36__data_o$next[3:0]$11511 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src36__data_o$next[3:0]$11513 \reg + case + assign $5\src36__data_o$next[3:0]$11513 $4\src36__data_o$next[3:0]$11512 + end + case + assign $1\src36__data_o$next[3:0]$11509 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src36__data_o$next[3:0]$11514 4'0000 + case + assign $6\src36__data_o$next[3:0]$11514 $1\src36__data_o$next[3:0]$11509 + end + sync always + update \src36__data_o$next $0\src36__data_o$next[3:0]$11508 + end + attribute \src "libresoc.v:172000.3-172029.6" + process $proc$libresoc.v:172000$11515 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$11516 $1\wr_detect$7[0:0]$11517 + attribute \src "libresoc.v:172001.5-172001.29" + switch \initial + attribute \src "libresoc.v:172001.9-172001.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src36__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$11517 $4\wr_detect$7[0:0]$11520 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$11518 1'1 + case + assign $2\wr_detect$7[0:0]$11518 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$11519 1'1 + case + assign $3\wr_detect$7[0:0]$11519 $2\wr_detect$7[0:0]$11518 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$11520 1'1 + case + assign $4\wr_detect$7[0:0]$11520 $3\wr_detect$7[0:0]$11519 + end + case + assign $1\wr_detect$7[0:0]$11517 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$11516 + end + attribute \src "libresoc.v:172030.3-172069.6" + process $proc$libresoc.v:172030$11521 + assign { } { } + assign { } { } + assign { } { } + assign $0\r6__data_o$next[3:0]$11522 $6\r6__data_o$next[3:0]$11528 + attribute \src "libresoc.v:172031.5-172031.29" + switch \initial + attribute \src "libresoc.v:172031.9-172031.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r6__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r6__data_o$next[3:0]$11523 $5\r6__data_o$next[3:0]$11527 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r6__data_o$next[3:0]$11524 \dest16__data_i + case + assign $2\r6__data_o$next[3:0]$11524 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r6__data_o$next[3:0]$11525 \dest26__data_i + case + assign $3\r6__data_o$next[3:0]$11525 $2\r6__data_o$next[3:0]$11524 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r6__data_o$next[3:0]$11526 \w6__data_i + case + assign $4\r6__data_o$next[3:0]$11526 $3\r6__data_o$next[3:0]$11525 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r6__data_o$next[3:0]$11527 \reg + case + assign $5\r6__data_o$next[3:0]$11527 $4\r6__data_o$next[3:0]$11526 + end + case + assign $1\r6__data_o$next[3:0]$11523 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r6__data_o$next[3:0]$11528 4'0000 + case + assign $6\r6__data_o$next[3:0]$11528 $1\r6__data_o$next[3:0]$11523 + end + sync always + update \r6__data_o$next $0\r6__data_o$next[3:0]$11522 + end + attribute \src "libresoc.v:172070.3-172099.6" + process $proc$libresoc.v:172070$11529 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$11530 $1\wr_detect$10[0:0]$11531 + attribute \src "libresoc.v:172071.5-172071.29" + switch \initial + attribute \src "libresoc.v:172071.9-172071.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r6__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$11531 $4\wr_detect$10[0:0]$11534 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$11532 1'1 + case + assign $2\wr_detect$10[0:0]$11532 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$11533 1'1 + case + assign $3\wr_detect$10[0:0]$11533 $2\wr_detect$10[0:0]$11532 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$11534 1'1 + case + assign $4\wr_detect$10[0:0]$11534 $3\wr_detect$10[0:0]$11533 + end + case + assign $1\wr_detect$10[0:0]$11531 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$11530 + end + attribute \src "libresoc.v:172100.3-172139.6" + process $proc$libresoc.v:172100$11535 + assign { } { } + assign { } { } + assign { } { } + assign $0\r26__data_o$next[3:0]$11536 $6\r26__data_o$next[3:0]$11542 + attribute \src "libresoc.v:172101.5-172101.29" + switch \initial + attribute \src "libresoc.v:172101.9-172101.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r26__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r26__data_o$next[3:0]$11537 $5\r26__data_o$next[3:0]$11541 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r26__data_o$next[3:0]$11538 \dest16__data_i + case + assign $2\r26__data_o$next[3:0]$11538 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r26__data_o$next[3:0]$11539 \dest26__data_i + case + assign $3\r26__data_o$next[3:0]$11539 $2\r26__data_o$next[3:0]$11538 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r26__data_o$next[3:0]$11540 \w6__data_i + case + assign $4\r26__data_o$next[3:0]$11540 $3\r26__data_o$next[3:0]$11539 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r26__data_o$next[3:0]$11541 \reg + case + assign $5\r26__data_o$next[3:0]$11541 $4\r26__data_o$next[3:0]$11540 + end + case + assign $1\r26__data_o$next[3:0]$11537 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r26__data_o$next[3:0]$11542 4'0000 + case + assign $6\r26__data_o$next[3:0]$11542 $1\r26__data_o$next[3:0]$11537 + end + sync always + update \r26__data_o$next $0\r26__data_o$next[3:0]$11536 + end + attribute \src "libresoc.v:172140.3-172169.6" + process $proc$libresoc.v:172140$11543 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$11544 $1\wr_detect$13[0:0]$11545 + attribute \src "libresoc.v:172141.5-172141.29" + switch \initial + attribute \src "libresoc.v:172141.9-172141.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r26__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$11545 $4\wr_detect$13[0:0]$11548 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$11546 1'1 + case + assign $2\wr_detect$13[0:0]$11546 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$11547 1'1 + case + assign $3\wr_detect$13[0:0]$11547 $2\wr_detect$13[0:0]$11546 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$11548 1'1 + case + assign $4\wr_detect$13[0:0]$11548 $3\wr_detect$13[0:0]$11547 + end + case + assign $1\wr_detect$13[0:0]$11545 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$11544 + end + connect \$9 $not$libresoc.v:171776$11467_Y + connect \$12 $not$libresoc.v:171777$11468_Y + connect \$1 $not$libresoc.v:171778$11469_Y + connect \$3 $not$libresoc.v:171779$11470_Y + connect \$6 $not$libresoc.v:171780$11471_Y +end +attribute \src "libresoc.v:172174.1-172645.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_7" +attribute \generator "nMigen" +module \reg_7 + attribute \src "libresoc.v:172175.7-172175.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:172575.3-172614.6" + wire width 4 $0\r27__data_o$next[3:0]$11625 + attribute \src "libresoc.v:172258.3-172259.39" + wire width 4 $0\r27__data_o[3:0] + attribute \src "libresoc.v:172505.3-172544.6" + wire width 4 $0\r7__data_o$next[3:0]$11611 + attribute \src "libresoc.v:172260.3-172261.37" + wire width 4 $0\r7__data_o[3:0] + attribute \src "libresoc.v:172338.3-172364.6" + wire width 4 $0\reg$next[3:0]$11577 + attribute \src "libresoc.v:172256.3-172257.25" + wire width 4 $0\reg[3:0] + attribute \src "libresoc.v:172268.3-172307.6" + wire width 4 $0\src17__data_o$next[3:0]$11568 + attribute \src "libresoc.v:172266.3-172267.43" + wire width 4 $0\src17__data_o[3:0] + attribute \src "libresoc.v:172365.3-172404.6" + wire width 4 $0\src27__data_o$next[3:0]$11583 + attribute \src "libresoc.v:172264.3-172265.43" + wire width 4 $0\src27__data_o[3:0] + attribute \src "libresoc.v:172435.3-172474.6" + wire width 4 $0\src37__data_o$next[3:0]$11597 + attribute \src "libresoc.v:172262.3-172263.43" + wire width 4 $0\src37__data_o[3:0] + attribute \src "libresoc.v:172545.3-172574.6" + wire $0\wr_detect$10[0:0]$11619 + attribute \src "libresoc.v:172615.3-172644.6" + wire $0\wr_detect$13[0:0]$11633 + attribute \src "libresoc.v:172405.3-172434.6" + wire $0\wr_detect$4[0:0]$11591 + attribute \src "libresoc.v:172475.3-172504.6" + wire $0\wr_detect$7[0:0]$11605 + attribute \src "libresoc.v:172308.3-172337.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:172575.3-172614.6" + wire width 4 $1\r27__data_o$next[3:0]$11626 + attribute \src "libresoc.v:172200.13-172200.31" + wire width 4 $1\r27__data_o[3:0] + attribute \src "libresoc.v:172505.3-172544.6" + wire width 4 $1\r7__data_o$next[3:0]$11612 + attribute \src "libresoc.v:172207.13-172207.30" + wire width 4 $1\r7__data_o[3:0] + attribute \src "libresoc.v:172338.3-172364.6" + wire width 4 $1\reg$next[3:0]$11578 + attribute \src "libresoc.v:172213.13-172213.25" + wire width 4 $1\reg[3:0] + attribute \src "libresoc.v:172268.3-172307.6" + wire width 4 $1\src17__data_o$next[3:0]$11569 + attribute \src "libresoc.v:172218.13-172218.33" + wire width 4 $1\src17__data_o[3:0] + attribute \src "libresoc.v:172365.3-172404.6" + wire width 4 $1\src27__data_o$next[3:0]$11584 + attribute \src "libresoc.v:172225.13-172225.33" + wire width 4 $1\src27__data_o[3:0] + attribute \src "libresoc.v:172435.3-172474.6" + wire width 4 $1\src37__data_o$next[3:0]$11598 + attribute \src "libresoc.v:172232.13-172232.33" + wire width 4 $1\src37__data_o[3:0] + attribute \src "libresoc.v:172545.3-172574.6" + wire $1\wr_detect$10[0:0]$11620 + attribute \src "libresoc.v:172615.3-172644.6" + wire $1\wr_detect$13[0:0]$11634 + attribute \src "libresoc.v:172405.3-172434.6" + wire $1\wr_detect$4[0:0]$11592 + attribute \src "libresoc.v:172475.3-172504.6" + wire $1\wr_detect$7[0:0]$11606 + attribute \src "libresoc.v:172308.3-172337.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:172575.3-172614.6" + wire width 4 $2\r27__data_o$next[3:0]$11627 + attribute \src "libresoc.v:172505.3-172544.6" + wire width 4 $2\r7__data_o$next[3:0]$11613 + attribute \src "libresoc.v:172338.3-172364.6" + wire width 4 $2\reg$next[3:0]$11579 + attribute \src "libresoc.v:172268.3-172307.6" + wire width 4 $2\src17__data_o$next[3:0]$11570 + attribute \src "libresoc.v:172365.3-172404.6" + wire width 4 $2\src27__data_o$next[3:0]$11585 + attribute \src "libresoc.v:172435.3-172474.6" + wire width 4 $2\src37__data_o$next[3:0]$11599 + attribute \src "libresoc.v:172545.3-172574.6" + wire $2\wr_detect$10[0:0]$11621 + attribute \src "libresoc.v:172615.3-172644.6" + wire $2\wr_detect$13[0:0]$11635 + attribute \src "libresoc.v:172405.3-172434.6" + wire $2\wr_detect$4[0:0]$11593 + attribute \src "libresoc.v:172475.3-172504.6" + wire $2\wr_detect$7[0:0]$11607 + attribute \src "libresoc.v:172308.3-172337.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:172575.3-172614.6" + wire width 4 $3\r27__data_o$next[3:0]$11628 + attribute \src "libresoc.v:172505.3-172544.6" + wire width 4 $3\r7__data_o$next[3:0]$11614 + attribute \src "libresoc.v:172338.3-172364.6" + wire width 4 $3\reg$next[3:0]$11580 + attribute \src "libresoc.v:172268.3-172307.6" + wire width 4 $3\src17__data_o$next[3:0]$11571 + attribute \src "libresoc.v:172365.3-172404.6" + wire width 4 $3\src27__data_o$next[3:0]$11586 + attribute \src "libresoc.v:172435.3-172474.6" + wire width 4 $3\src37__data_o$next[3:0]$11600 + attribute \src "libresoc.v:172545.3-172574.6" + wire $3\wr_detect$10[0:0]$11622 + attribute \src "libresoc.v:172615.3-172644.6" + wire $3\wr_detect$13[0:0]$11636 + attribute \src "libresoc.v:172405.3-172434.6" + wire $3\wr_detect$4[0:0]$11594 + attribute \src "libresoc.v:172475.3-172504.6" + wire $3\wr_detect$7[0:0]$11608 + attribute \src "libresoc.v:172308.3-172337.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:172575.3-172614.6" + wire width 4 $4\r27__data_o$next[3:0]$11629 + attribute \src "libresoc.v:172505.3-172544.6" + wire width 4 $4\r7__data_o$next[3:0]$11615 + attribute \src "libresoc.v:172338.3-172364.6" + wire width 4 $4\reg$next[3:0]$11581 + attribute \src "libresoc.v:172268.3-172307.6" + wire width 4 $4\src17__data_o$next[3:0]$11572 + attribute \src "libresoc.v:172365.3-172404.6" + wire width 4 $4\src27__data_o$next[3:0]$11587 + attribute \src "libresoc.v:172435.3-172474.6" + wire width 4 $4\src37__data_o$next[3:0]$11601 + attribute \src "libresoc.v:172545.3-172574.6" + wire $4\wr_detect$10[0:0]$11623 + attribute \src "libresoc.v:172615.3-172644.6" + wire $4\wr_detect$13[0:0]$11637 + attribute \src "libresoc.v:172405.3-172434.6" + wire $4\wr_detect$4[0:0]$11595 + attribute \src "libresoc.v:172475.3-172504.6" + wire $4\wr_detect$7[0:0]$11609 + attribute \src "libresoc.v:172308.3-172337.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:172575.3-172614.6" + wire width 4 $5\r27__data_o$next[3:0]$11630 + attribute \src "libresoc.v:172505.3-172544.6" + wire width 4 $5\r7__data_o$next[3:0]$11616 + attribute \src "libresoc.v:172268.3-172307.6" + wire width 4 $5\src17__data_o$next[3:0]$11573 + attribute \src "libresoc.v:172365.3-172404.6" + wire width 4 $5\src27__data_o$next[3:0]$11588 + attribute \src "libresoc.v:172435.3-172474.6" + wire width 4 $5\src37__data_o$next[3:0]$11602 + attribute \src "libresoc.v:172575.3-172614.6" + wire width 4 $6\r27__data_o$next[3:0]$11631 + attribute \src "libresoc.v:172505.3-172544.6" + wire width 4 $6\r7__data_o$next[3:0]$11617 + attribute \src "libresoc.v:172268.3-172307.6" + wire width 4 $6\src17__data_o$next[3:0]$11574 + attribute \src "libresoc.v:172365.3-172404.6" + wire width 4 $6\src27__data_o$next[3:0]$11589 + attribute \src "libresoc.v:172435.3-172474.6" + wire width 4 $6\src37__data_o$next[3:0]$11603 + attribute \src "libresoc.v:172251.17-172251.104" + wire $not$libresoc.v:172251$11556_Y + attribute \src "libresoc.v:172252.18-172252.105" + wire $not$libresoc.v:172252$11557_Y + attribute \src "libresoc.v:172253.17-172253.100" + wire $not$libresoc.v:172253$11558_Y + attribute \src "libresoc.v:172254.17-172254.103" + wire $not$libresoc.v:172254$11559_Y + attribute \src "libresoc.v:172255.17-172255.103" + wire $not$libresoc.v:172255$11560_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 9 \dest17__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \dest17__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 11 \dest27__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \dest27__wen + attribute \src "libresoc.v:172175.7-172175.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 14 \r27__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r27__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 15 \r27__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 12 \r7__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r7__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 13 \r7__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 3 \src17__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src17__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \src17__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 5 \src27__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src27__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \src27__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 7 \src37__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src37__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \src37__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 16 \w7__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 17 \w7__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:172251$11556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:172251$11556_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:172252$11557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$libresoc.v:172252$11557_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:172253$11558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:172253$11558_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:172254$11559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:172254$11559_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:172255$11560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:172255$11560_Y + end + attribute \src "libresoc.v:172175.7-172175.20" + process $proc$libresoc.v:172175$11638 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:172200.13-172200.31" + process $proc$libresoc.v:172200$11639 + assign { } { } + assign $1\r27__data_o[3:0] 4'0000 + sync always + sync init + update \r27__data_o $1\r27__data_o[3:0] + end + attribute \src "libresoc.v:172207.13-172207.30" + process $proc$libresoc.v:172207$11640 + assign { } { } + assign $1\r7__data_o[3:0] 4'0000 + sync always + sync init + update \r7__data_o $1\r7__data_o[3:0] + end + attribute \src "libresoc.v:172213.13-172213.25" + process $proc$libresoc.v:172213$11641 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "libresoc.v:172218.13-172218.33" + process $proc$libresoc.v:172218$11642 + assign { } { } + assign $1\src17__data_o[3:0] 4'0000 + sync always + sync init + update \src17__data_o $1\src17__data_o[3:0] + end + attribute \src "libresoc.v:172225.13-172225.33" + process $proc$libresoc.v:172225$11643 + assign { } { } + assign $1\src27__data_o[3:0] 4'0000 + sync always + sync init + update \src27__data_o $1\src27__data_o[3:0] + end + attribute \src "libresoc.v:172232.13-172232.33" + process $proc$libresoc.v:172232$11644 + assign { } { } + assign $1\src37__data_o[3:0] 4'0000 + sync always + sync init + update \src37__data_o $1\src37__data_o[3:0] + end + attribute \src "libresoc.v:172256.3-172257.25" + process $proc$libresoc.v:172256$11561 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "libresoc.v:172258.3-172259.39" + process $proc$libresoc.v:172258$11562 + assign { } { } + assign $0\r27__data_o[3:0] \r27__data_o$next + sync posedge \coresync_clk + update \r27__data_o $0\r27__data_o[3:0] + end + attribute \src "libresoc.v:172260.3-172261.37" + process $proc$libresoc.v:172260$11563 + assign { } { } + assign $0\r7__data_o[3:0] \r7__data_o$next + sync posedge \coresync_clk + update \r7__data_o $0\r7__data_o[3:0] + end + attribute \src "libresoc.v:172262.3-172263.43" + process $proc$libresoc.v:172262$11564 + assign { } { } + assign $0\src37__data_o[3:0] \src37__data_o$next + sync posedge \coresync_clk + update \src37__data_o $0\src37__data_o[3:0] + end + attribute \src "libresoc.v:172264.3-172265.43" + process $proc$libresoc.v:172264$11565 + assign { } { } + assign $0\src27__data_o[3:0] \src27__data_o$next + sync posedge \coresync_clk + update \src27__data_o $0\src27__data_o[3:0] + end + attribute \src "libresoc.v:172266.3-172267.43" + process $proc$libresoc.v:172266$11566 + assign { } { } + assign $0\src17__data_o[3:0] \src17__data_o$next + sync posedge \coresync_clk + update \src17__data_o $0\src17__data_o[3:0] + end + attribute \src "libresoc.v:172268.3-172307.6" + process $proc$libresoc.v:172268$11567 + assign { } { } + assign { } { } + assign { } { } + assign $0\src17__data_o$next[3:0]$11568 $6\src17__data_o$next[3:0]$11574 + attribute \src "libresoc.v:172269.5-172269.29" + switch \initial + attribute \src "libresoc.v:172269.9-172269.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src17__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src17__data_o$next[3:0]$11569 $5\src17__data_o$next[3:0]$11573 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src17__data_o$next[3:0]$11570 \dest17__data_i + case + assign $2\src17__data_o$next[3:0]$11570 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src17__data_o$next[3:0]$11571 \dest27__data_i + case + assign $3\src17__data_o$next[3:0]$11571 $2\src17__data_o$next[3:0]$11570 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src17__data_o$next[3:0]$11572 \w7__data_i + case + assign $4\src17__data_o$next[3:0]$11572 $3\src17__data_o$next[3:0]$11571 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src17__data_o$next[3:0]$11573 \reg + case + assign $5\src17__data_o$next[3:0]$11573 $4\src17__data_o$next[3:0]$11572 + end + case + assign $1\src17__data_o$next[3:0]$11569 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src17__data_o$next[3:0]$11574 4'0000 + case + assign $6\src17__data_o$next[3:0]$11574 $1\src17__data_o$next[3:0]$11569 + end + sync always + update \src17__data_o$next $0\src17__data_o$next[3:0]$11568 + end + attribute \src "libresoc.v:172308.3-172337.6" + process $proc$libresoc.v:172308$11575 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:172309.5-172309.29" + switch \initial + attribute \src "libresoc.v:172309.9-172309.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src17__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:172338.3-172364.6" + process $proc$libresoc.v:172338$11576 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$11577 $4\reg$next[3:0]$11581 + attribute \src "libresoc.v:172339.5-172339.29" + switch \initial + attribute \src "libresoc.v:172339.9-172339.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$11578 \dest17__data_i + case + assign $1\reg$next[3:0]$11578 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$11579 \dest27__data_i + case + assign $2\reg$next[3:0]$11579 $1\reg$next[3:0]$11578 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$11580 \w7__data_i + case + assign $3\reg$next[3:0]$11580 $2\reg$next[3:0]$11579 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$11581 4'0000 + case + assign $4\reg$next[3:0]$11581 $3\reg$next[3:0]$11580 + end + sync always + update \reg$next $0\reg$next[3:0]$11577 + end + attribute \src "libresoc.v:172365.3-172404.6" + process $proc$libresoc.v:172365$11582 + assign { } { } + assign { } { } + assign { } { } + assign $0\src27__data_o$next[3:0]$11583 $6\src27__data_o$next[3:0]$11589 + attribute \src "libresoc.v:172366.5-172366.29" + switch \initial + attribute \src "libresoc.v:172366.9-172366.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src27__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src27__data_o$next[3:0]$11584 $5\src27__data_o$next[3:0]$11588 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src27__data_o$next[3:0]$11585 \dest17__data_i + case + assign $2\src27__data_o$next[3:0]$11585 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src27__data_o$next[3:0]$11586 \dest27__data_i + case + assign $3\src27__data_o$next[3:0]$11586 $2\src27__data_o$next[3:0]$11585 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src27__data_o$next[3:0]$11587 \w7__data_i + case + assign $4\src27__data_o$next[3:0]$11587 $3\src27__data_o$next[3:0]$11586 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src27__data_o$next[3:0]$11588 \reg + case + assign $5\src27__data_o$next[3:0]$11588 $4\src27__data_o$next[3:0]$11587 + end + case + assign $1\src27__data_o$next[3:0]$11584 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src27__data_o$next[3:0]$11589 4'0000 + case + assign $6\src27__data_o$next[3:0]$11589 $1\src27__data_o$next[3:0]$11584 + end + sync always + update \src27__data_o$next $0\src27__data_o$next[3:0]$11583 + end + attribute \src "libresoc.v:172405.3-172434.6" + process $proc$libresoc.v:172405$11590 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$11591 $1\wr_detect$4[0:0]$11592 + attribute \src "libresoc.v:172406.5-172406.29" + switch \initial + attribute \src "libresoc.v:172406.9-172406.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src27__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$11592 $4\wr_detect$4[0:0]$11595 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$11593 1'1 + case + assign $2\wr_detect$4[0:0]$11593 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$11594 1'1 + case + assign $3\wr_detect$4[0:0]$11594 $2\wr_detect$4[0:0]$11593 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$11595 1'1 + case + assign $4\wr_detect$4[0:0]$11595 $3\wr_detect$4[0:0]$11594 + end + case + assign $1\wr_detect$4[0:0]$11592 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$11591 + end + attribute \src "libresoc.v:172435.3-172474.6" + process $proc$libresoc.v:172435$11596 + assign { } { } + assign { } { } + assign { } { } + assign $0\src37__data_o$next[3:0]$11597 $6\src37__data_o$next[3:0]$11603 + attribute \src "libresoc.v:172436.5-172436.29" + switch \initial + attribute \src "libresoc.v:172436.9-172436.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src37__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src37__data_o$next[3:0]$11598 $5\src37__data_o$next[3:0]$11602 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src37__data_o$next[3:0]$11599 \dest17__data_i + case + assign $2\src37__data_o$next[3:0]$11599 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src37__data_o$next[3:0]$11600 \dest27__data_i + case + assign $3\src37__data_o$next[3:0]$11600 $2\src37__data_o$next[3:0]$11599 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src37__data_o$next[3:0]$11601 \w7__data_i + case + assign $4\src37__data_o$next[3:0]$11601 $3\src37__data_o$next[3:0]$11600 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src37__data_o$next[3:0]$11602 \reg + case + assign $5\src37__data_o$next[3:0]$11602 $4\src37__data_o$next[3:0]$11601 + end + case + assign $1\src37__data_o$next[3:0]$11598 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src37__data_o$next[3:0]$11603 4'0000 + case + assign $6\src37__data_o$next[3:0]$11603 $1\src37__data_o$next[3:0]$11598 + end + sync always + update \src37__data_o$next $0\src37__data_o$next[3:0]$11597 + end + attribute \src "libresoc.v:172475.3-172504.6" + process $proc$libresoc.v:172475$11604 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$11605 $1\wr_detect$7[0:0]$11606 + attribute \src "libresoc.v:172476.5-172476.29" + switch \initial + attribute \src "libresoc.v:172476.9-172476.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src37__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$11606 $4\wr_detect$7[0:0]$11609 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$11607 1'1 + case + assign $2\wr_detect$7[0:0]$11607 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$11608 1'1 + case + assign $3\wr_detect$7[0:0]$11608 $2\wr_detect$7[0:0]$11607 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$11609 1'1 + case + assign $4\wr_detect$7[0:0]$11609 $3\wr_detect$7[0:0]$11608 + end + case + assign $1\wr_detect$7[0:0]$11606 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$11605 + end + attribute \src "libresoc.v:172505.3-172544.6" + process $proc$libresoc.v:172505$11610 + assign { } { } + assign { } { } + assign { } { } + assign $0\r7__data_o$next[3:0]$11611 $6\r7__data_o$next[3:0]$11617 + attribute \src "libresoc.v:172506.5-172506.29" + switch \initial + attribute \src "libresoc.v:172506.9-172506.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r7__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r7__data_o$next[3:0]$11612 $5\r7__data_o$next[3:0]$11616 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r7__data_o$next[3:0]$11613 \dest17__data_i + case + assign $2\r7__data_o$next[3:0]$11613 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r7__data_o$next[3:0]$11614 \dest27__data_i + case + assign $3\r7__data_o$next[3:0]$11614 $2\r7__data_o$next[3:0]$11613 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r7__data_o$next[3:0]$11615 \w7__data_i + case + assign $4\r7__data_o$next[3:0]$11615 $3\r7__data_o$next[3:0]$11614 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r7__data_o$next[3:0]$11616 \reg + case + assign $5\r7__data_o$next[3:0]$11616 $4\r7__data_o$next[3:0]$11615 + end + case + assign $1\r7__data_o$next[3:0]$11612 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r7__data_o$next[3:0]$11617 4'0000 + case + assign $6\r7__data_o$next[3:0]$11617 $1\r7__data_o$next[3:0]$11612 + end + sync always + update \r7__data_o$next $0\r7__data_o$next[3:0]$11611 + end + attribute \src "libresoc.v:172545.3-172574.6" + process $proc$libresoc.v:172545$11618 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$11619 $1\wr_detect$10[0:0]$11620 + attribute \src "libresoc.v:172546.5-172546.29" + switch \initial + attribute \src "libresoc.v:172546.9-172546.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r7__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$11620 $4\wr_detect$10[0:0]$11623 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$11621 1'1 + case + assign $2\wr_detect$10[0:0]$11621 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$11622 1'1 + case + assign $3\wr_detect$10[0:0]$11622 $2\wr_detect$10[0:0]$11621 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$11623 1'1 + case + assign $4\wr_detect$10[0:0]$11623 $3\wr_detect$10[0:0]$11622 + end + case + assign $1\wr_detect$10[0:0]$11620 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$11619 + end + attribute \src "libresoc.v:172575.3-172614.6" + process $proc$libresoc.v:172575$11624 + assign { } { } + assign { } { } + assign { } { } + assign $0\r27__data_o$next[3:0]$11625 $6\r27__data_o$next[3:0]$11631 + attribute \src "libresoc.v:172576.5-172576.29" + switch \initial + attribute \src "libresoc.v:172576.9-172576.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r27__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r27__data_o$next[3:0]$11626 $5\r27__data_o$next[3:0]$11630 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r27__data_o$next[3:0]$11627 \dest17__data_i + case + assign $2\r27__data_o$next[3:0]$11627 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r27__data_o$next[3:0]$11628 \dest27__data_i + case + assign $3\r27__data_o$next[3:0]$11628 $2\r27__data_o$next[3:0]$11627 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r27__data_o$next[3:0]$11629 \w7__data_i + case + assign $4\r27__data_o$next[3:0]$11629 $3\r27__data_o$next[3:0]$11628 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r27__data_o$next[3:0]$11630 \reg + case + assign $5\r27__data_o$next[3:0]$11630 $4\r27__data_o$next[3:0]$11629 + end + case + assign $1\r27__data_o$next[3:0]$11626 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r27__data_o$next[3:0]$11631 4'0000 + case + assign $6\r27__data_o$next[3:0]$11631 $1\r27__data_o$next[3:0]$11626 + end + sync always + update \r27__data_o$next $0\r27__data_o$next[3:0]$11625 + end + attribute \src "libresoc.v:172615.3-172644.6" + process $proc$libresoc.v:172615$11632 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$11633 $1\wr_detect$13[0:0]$11634 + attribute \src "libresoc.v:172616.5-172616.29" + switch \initial + attribute \src "libresoc.v:172616.9-172616.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r27__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$11634 $4\wr_detect$13[0:0]$11637 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$11635 1'1 + case + assign $2\wr_detect$13[0:0]$11635 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$11636 1'1 + case + assign $3\wr_detect$13[0:0]$11636 $2\wr_detect$13[0:0]$11635 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$11637 1'1 + case + assign $4\wr_detect$13[0:0]$11637 $3\wr_detect$13[0:0]$11636 + end + case + assign $1\wr_detect$13[0:0]$11634 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$11633 + end + connect \$9 $not$libresoc.v:172251$11556_Y + connect \$12 $not$libresoc.v:172252$11557_Y + connect \$1 $not$libresoc.v:172253$11558_Y + connect \$3 $not$libresoc.v:172254$11559_Y + connect \$6 $not$libresoc.v:172255$11560_Y +end +attribute \src "libresoc.v:172649.1-172707.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.req_l" +attribute \generator "nMigen" +module \req_l + attribute \src "libresoc.v:172650.7-172650.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:172695.3-172703.6" + wire width 5 $0\q_int$next[4:0]$11655 + attribute \src "libresoc.v:172693.3-172694.27" + wire width 5 $0\q_int[4:0] + attribute \src "libresoc.v:172695.3-172703.6" + wire width 5 $1\q_int$next[4:0]$11656 + attribute \src "libresoc.v:172672.13-172672.26" + wire width 5 $1\q_int[4:0] + attribute \src "libresoc.v:172685.17-172685.96" + wire width 5 $and$libresoc.v:172685$11645_Y + attribute \src "libresoc.v:172690.17-172690.96" + wire width 5 $and$libresoc.v:172690$11650_Y + attribute \src "libresoc.v:172687.18-172687.93" + wire width 5 $not$libresoc.v:172687$11647_Y + attribute \src "libresoc.v:172689.17-172689.92" + wire width 5 $not$libresoc.v:172689$11649_Y + attribute \src "libresoc.v:172692.17-172692.92" + wire width 5 $not$libresoc.v:172692$11652_Y + attribute \src "libresoc.v:172686.18-172686.98" + wire width 5 $or$libresoc.v:172686$11646_Y + attribute \src "libresoc.v:172688.18-172688.99" + wire width 5 $or$libresoc.v:172688$11648_Y + attribute \src "libresoc.v:172691.17-172691.97" + wire width 5 $or$libresoc.v:172691$11651_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 5 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 5 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 5 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 5 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 5 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 5 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 5 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 5 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:172650.7-172650.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 5 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 5 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 5 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 5 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 5 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 5 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 5 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:172685$11645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:172685$11645_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:172690$11650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:172690$11650_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:172687$11647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_req + connect \Y $not$libresoc.v:172687$11647_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:172689$11649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \r_req + connect \Y $not$libresoc.v:172689$11649_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:172692$11652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \r_req + connect \Y $not$libresoc.v:172692$11652_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:172686$11646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$9 + connect \B \s_req + connect \Y $or$libresoc.v:172686$11646_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:172688$11648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_req + connect \B \q_int + connect \Y $or$libresoc.v:172688$11648_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:172691$11651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$3 + connect \B \s_req + connect \Y $or$libresoc.v:172691$11651_Y + end + attribute \src "libresoc.v:172650.7-172650.20" + process $proc$libresoc.v:172650$11657 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:172672.13-172672.26" + process $proc$libresoc.v:172672$11658 + assign { } { } + assign $1\q_int[4:0] 5'00000 + sync always + sync init + update \q_int $1\q_int[4:0] + end + attribute \src "libresoc.v:172693.3-172694.27" + process $proc$libresoc.v:172693$11653 + assign { } { } + assign $0\q_int[4:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[4:0] + end + attribute \src "libresoc.v:172695.3-172703.6" + process $proc$libresoc.v:172695$11654 + assign { } { } + assign { } { } + assign $0\q_int$next[4:0]$11655 $1\q_int$next[4:0]$11656 + attribute \src "libresoc.v:172696.5-172696.29" + switch \initial + attribute \src "libresoc.v:172696.9-172696.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[4:0]$11656 5'00000 + case + assign $1\q_int$next[4:0]$11656 \$5 + end + sync always + update \q_int$next $0\q_int$next[4:0]$11655 + end + connect \$9 $and$libresoc.v:172685$11645_Y + connect \$11 $or$libresoc.v:172686$11646_Y + connect \$13 $not$libresoc.v:172687$11647_Y + connect \$15 $or$libresoc.v:172688$11648_Y + connect \$1 $not$libresoc.v:172689$11649_Y + connect \$3 $and$libresoc.v:172690$11650_Y + connect \$5 $or$libresoc.v:172691$11651_Y + connect \$7 $not$libresoc.v:172692$11652_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "libresoc.v:172711.1-172769.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.req_l" +attribute \generator "nMigen" +module \req_l$103 + attribute \src "libresoc.v:172712.7-172712.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:172757.3-172765.6" + wire width 4 $0\q_int$next[3:0]$11669 + attribute \src "libresoc.v:172755.3-172756.27" + wire width 4 $0\q_int[3:0] + attribute \src "libresoc.v:172757.3-172765.6" + wire width 4 $1\q_int$next[3:0]$11670 + attribute \src "libresoc.v:172734.13-172734.25" + wire width 4 $1\q_int[3:0] + attribute \src "libresoc.v:172747.17-172747.96" + wire width 4 $and$libresoc.v:172747$11659_Y + attribute \src "libresoc.v:172752.17-172752.96" + wire width 4 $and$libresoc.v:172752$11664_Y + attribute \src "libresoc.v:172749.18-172749.93" + wire width 4 $not$libresoc.v:172749$11661_Y + attribute \src "libresoc.v:172751.17-172751.92" + wire width 4 $not$libresoc.v:172751$11663_Y + attribute \src "libresoc.v:172754.17-172754.92" + wire width 4 $not$libresoc.v:172754$11666_Y + attribute \src "libresoc.v:172748.18-172748.98" + wire width 4 $or$libresoc.v:172748$11660_Y + attribute \src "libresoc.v:172750.18-172750.99" + wire width 4 $or$libresoc.v:172750$11662_Y + attribute \src "libresoc.v:172753.17-172753.97" + wire width 4 $or$libresoc.v:172753$11665_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 4 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 4 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:172712.7-172712.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 4 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 4 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 4 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:172747$11659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:172747$11659_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:172752$11664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:172752$11664_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:172749$11661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_req + connect \Y $not$libresoc.v:172749$11661_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:172751$11663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_req + connect \Y $not$libresoc.v:172751$11663_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:172754$11666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_req + connect \Y $not$libresoc.v:172754$11666_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:172748$11660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$9 + connect \B \s_req + connect \Y $or$libresoc.v:172748$11660_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:172750$11662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_req + connect \B \q_int + connect \Y $or$libresoc.v:172750$11662_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:172753$11665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$3 + connect \B \s_req + connect \Y $or$libresoc.v:172753$11665_Y + end + attribute \src "libresoc.v:172712.7-172712.20" + process $proc$libresoc.v:172712$11671 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:172734.13-172734.25" + process $proc$libresoc.v:172734$11672 + assign { } { } + assign $1\q_int[3:0] 4'0000 + sync always + sync init + update \q_int $1\q_int[3:0] + end + attribute \src "libresoc.v:172755.3-172756.27" + process $proc$libresoc.v:172755$11667 + assign { } { } + assign $0\q_int[3:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[3:0] + end + attribute \src "libresoc.v:172757.3-172765.6" + process $proc$libresoc.v:172757$11668 + assign { } { } + assign { } { } + assign $0\q_int$next[3:0]$11669 $1\q_int$next[3:0]$11670 + attribute \src "libresoc.v:172758.5-172758.29" + switch \initial + attribute \src "libresoc.v:172758.9-172758.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[3:0]$11670 4'0000 + case + assign $1\q_int$next[3:0]$11670 \$5 + end + sync always + update \q_int$next $0\q_int$next[3:0]$11669 + end + connect \$9 $and$libresoc.v:172747$11659_Y + connect \$11 $or$libresoc.v:172748$11660_Y + connect \$13 $not$libresoc.v:172749$11661_Y + connect \$15 $or$libresoc.v:172750$11662_Y + connect \$1 $not$libresoc.v:172751$11663_Y + connect \$3 $and$libresoc.v:172752$11664_Y + connect \$5 $or$libresoc.v:172753$11665_Y + connect \$7 $not$libresoc.v:172754$11666_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "libresoc.v:172773.1-172831.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.req_l" +attribute \generator "nMigen" +module \req_l$12 + attribute \src "libresoc.v:172774.7-172774.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:172819.3-172827.6" + wire width 3 $0\q_int$next[2:0]$11683 + attribute \src "libresoc.v:172817.3-172818.27" + wire width 3 $0\q_int[2:0] + attribute \src "libresoc.v:172819.3-172827.6" + wire width 3 $1\q_int$next[2:0]$11684 + attribute \src "libresoc.v:172796.13-172796.25" + wire width 3 $1\q_int[2:0] + attribute \src "libresoc.v:172809.17-172809.96" + wire width 3 $and$libresoc.v:172809$11673_Y + attribute \src "libresoc.v:172814.17-172814.96" + wire width 3 $and$libresoc.v:172814$11678_Y + attribute \src "libresoc.v:172811.18-172811.93" + wire width 3 $not$libresoc.v:172811$11675_Y + attribute \src "libresoc.v:172813.17-172813.92" + wire width 3 $not$libresoc.v:172813$11677_Y + attribute \src "libresoc.v:172816.17-172816.92" + wire width 3 $not$libresoc.v:172816$11680_Y + attribute \src "libresoc.v:172810.18-172810.98" + wire width 3 $or$libresoc.v:172810$11674_Y + attribute \src "libresoc.v:172812.18-172812.99" + wire width 3 $or$libresoc.v:172812$11676_Y + attribute \src "libresoc.v:172815.17-172815.97" + wire width 3 $or$libresoc.v:172815$11679_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 3 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:172774.7-172774.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 3 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 3 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:172809$11673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:172809$11673_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:172814$11678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:172814$11678_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:172811$11675 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_req + connect \Y $not$libresoc.v:172811$11675_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:172813$11677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_req + connect \Y $not$libresoc.v:172813$11677_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:172816$11680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_req + connect \Y $not$libresoc.v:172816$11680_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:172810$11674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$9 + connect \B \s_req + connect \Y $or$libresoc.v:172810$11674_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:172812$11676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_req + connect \B \q_int + connect \Y $or$libresoc.v:172812$11676_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:172815$11679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$3 + connect \B \s_req + connect \Y $or$libresoc.v:172815$11679_Y + end + attribute \src "libresoc.v:172774.7-172774.20" + process $proc$libresoc.v:172774$11685 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:172796.13-172796.25" + process $proc$libresoc.v:172796$11686 + assign { } { } + assign $1\q_int[2:0] 3'000 + sync always + sync init + update \q_int $1\q_int[2:0] + end + attribute \src "libresoc.v:172817.3-172818.27" + process $proc$libresoc.v:172817$11681 + assign { } { } + assign $0\q_int[2:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[2:0] + end + attribute \src "libresoc.v:172819.3-172827.6" + process $proc$libresoc.v:172819$11682 + assign { } { } + assign { } { } + assign $0\q_int$next[2:0]$11683 $1\q_int$next[2:0]$11684 + attribute \src "libresoc.v:172820.5-172820.29" + switch \initial + attribute \src "libresoc.v:172820.9-172820.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[2:0]$11684 3'000 + case + assign $1\q_int$next[2:0]$11684 \$5 + end + sync always + update \q_int$next $0\q_int$next[2:0]$11683 + end + connect \$9 $and$libresoc.v:172809$11673_Y + connect \$11 $or$libresoc.v:172810$11674_Y + connect \$13 $not$libresoc.v:172811$11675_Y + connect \$15 $or$libresoc.v:172812$11676_Y + connect \$1 $not$libresoc.v:172813$11677_Y + connect \$3 $and$libresoc.v:172814$11678_Y + connect \$5 $or$libresoc.v:172815$11679_Y + connect \$7 $not$libresoc.v:172816$11680_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "libresoc.v:172835.1-172893.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.req_l" +attribute \generator "nMigen" +module \req_l$121 + attribute \src "libresoc.v:172836.7-172836.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:172881.3-172889.6" + wire width 3 $0\q_int$next[2:0]$11697 + attribute \src "libresoc.v:172879.3-172880.27" + wire width 3 $0\q_int[2:0] + attribute \src "libresoc.v:172881.3-172889.6" + wire width 3 $1\q_int$next[2:0]$11698 + attribute \src "libresoc.v:172858.13-172858.25" + wire width 3 $1\q_int[2:0] + attribute \src "libresoc.v:172871.17-172871.96" + wire width 3 $and$libresoc.v:172871$11687_Y + attribute \src "libresoc.v:172876.17-172876.96" + wire width 3 $and$libresoc.v:172876$11692_Y + attribute \src "libresoc.v:172873.18-172873.93" + wire width 3 $not$libresoc.v:172873$11689_Y + attribute \src "libresoc.v:172875.17-172875.92" + wire width 3 $not$libresoc.v:172875$11691_Y + attribute \src "libresoc.v:172878.17-172878.92" + wire width 3 $not$libresoc.v:172878$11694_Y + attribute \src "libresoc.v:172872.18-172872.98" + wire width 3 $or$libresoc.v:172872$11688_Y + attribute \src "libresoc.v:172874.18-172874.99" + wire width 3 $or$libresoc.v:172874$11690_Y + attribute \src "libresoc.v:172877.17-172877.97" + wire width 3 $or$libresoc.v:172877$11693_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 3 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:172836.7-172836.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 3 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 3 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:172871$11687 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:172871$11687_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:172876$11692 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:172876$11692_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:172873$11689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_req + connect \Y $not$libresoc.v:172873$11689_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:172875$11691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_req + connect \Y $not$libresoc.v:172875$11691_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:172878$11694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_req + connect \Y $not$libresoc.v:172878$11694_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:172872$11688 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$9 + connect \B \s_req + connect \Y $or$libresoc.v:172872$11688_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:172874$11690 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_req + connect \B \q_int + connect \Y $or$libresoc.v:172874$11690_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:172877$11693 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$3 + connect \B \s_req + connect \Y $or$libresoc.v:172877$11693_Y + end + attribute \src "libresoc.v:172836.7-172836.20" + process $proc$libresoc.v:172836$11699 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:172858.13-172858.25" + process $proc$libresoc.v:172858$11700 + assign { } { } + assign $1\q_int[2:0] 3'000 + sync always + sync init + update \q_int $1\q_int[2:0] + end + attribute \src "libresoc.v:172879.3-172880.27" + process $proc$libresoc.v:172879$11695 + assign { } { } + assign $0\q_int[2:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[2:0] + end + attribute \src "libresoc.v:172881.3-172889.6" + process $proc$libresoc.v:172881$11696 + assign { } { } + assign { } { } + assign $0\q_int$next[2:0]$11697 $1\q_int$next[2:0]$11698 + attribute \src "libresoc.v:172882.5-172882.29" + switch \initial + attribute \src "libresoc.v:172882.9-172882.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[2:0]$11698 3'000 + case + assign $1\q_int$next[2:0]$11698 \$5 + end + sync always + update \q_int$next $0\q_int$next[2:0]$11697 + end + connect \$9 $and$libresoc.v:172871$11687_Y + connect \$11 $or$libresoc.v:172872$11688_Y + connect \$13 $not$libresoc.v:172873$11689_Y + connect \$15 $or$libresoc.v:172874$11690_Y + connect \$1 $not$libresoc.v:172875$11691_Y + connect \$3 $and$libresoc.v:172876$11692_Y + connect \$5 $or$libresoc.v:172877$11693_Y + connect \$7 $not$libresoc.v:172878$11694_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "libresoc.v:172897.1-172955.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.req_l" +attribute \generator "nMigen" +module \req_l$25 + attribute \src "libresoc.v:172898.7-172898.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:172943.3-172951.6" + wire width 3 $0\q_int$next[2:0]$11711 + attribute \src "libresoc.v:172941.3-172942.27" + wire width 3 $0\q_int[2:0] + attribute \src "libresoc.v:172943.3-172951.6" + wire width 3 $1\q_int$next[2:0]$11712 + attribute \src "libresoc.v:172920.13-172920.25" + wire width 3 $1\q_int[2:0] + attribute \src "libresoc.v:172933.17-172933.96" + wire width 3 $and$libresoc.v:172933$11701_Y + attribute \src "libresoc.v:172938.17-172938.96" + wire width 3 $and$libresoc.v:172938$11706_Y + attribute \src "libresoc.v:172935.18-172935.93" + wire width 3 $not$libresoc.v:172935$11703_Y + attribute \src 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\q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 2 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 2 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 2 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 2 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 2 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:173057$11729 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:173057$11729_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:173062$11734 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:173062$11734_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:173059$11731 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \q_req + connect \Y $not$libresoc.v:173059$11731_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:173061$11733 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \r_req + connect \Y $not$libresoc.v:173061$11733_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:173064$11736 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \r_req + connect \Y $not$libresoc.v:173064$11736_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:173058$11730 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \$9 + connect \B \s_req + connect \Y $or$libresoc.v:173058$11730_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:173060$11732 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \q_req + connect \B \q_int + connect \Y $or$libresoc.v:173060$11732_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:173063$11735 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \$3 + connect \B \s_req + connect \Y $or$libresoc.v:173063$11735_Y + end + attribute \src "libresoc.v:173022.7-173022.20" + process $proc$libresoc.v:173022$11741 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:173044.13-173044.25" + process $proc$libresoc.v:173044$11742 + assign { } { } + assign $1\q_int[1:0] 2'00 + sync always + sync init + update \q_int $1\q_int[1:0] + end + attribute \src "libresoc.v:173065.3-173066.27" + process $proc$libresoc.v:173065$11737 + assign { } { } + assign $0\q_int[1:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[1:0] + end + attribute \src "libresoc.v:173067.3-173075.6" + process $proc$libresoc.v:173067$11738 + assign { } { } + assign { } { } + assign $0\q_int$next[1:0]$11739 $1\q_int$next[1:0]$11740 + attribute \src "libresoc.v:173068.5-173068.29" + switch \initial + attribute \src "libresoc.v:173068.9-173068.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[1:0]$11740 2'00 + case + assign $1\q_int$next[1:0]$11740 \$5 + end + sync always + update \q_int$next $0\q_int$next[1:0]$11739 + end + connect \$9 $and$libresoc.v:173057$11729_Y + connect \$11 $or$libresoc.v:173058$11730_Y + connect \$13 $not$libresoc.v:173059$11731_Y + connect \$15 $or$libresoc.v:173060$11732_Y + connect \$1 $not$libresoc.v:173061$11733_Y + connect \$3 $and$libresoc.v:173062$11734_Y + connect \$5 $or$libresoc.v:173063$11735_Y + connect \$7 $not$libresoc.v:173064$11736_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "libresoc.v:173083.1-173141.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.req_l" +attribute \generator "nMigen" +module \req_l$69 + attribute \src "libresoc.v:173084.7-173084.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:173129.3-173137.6" + wire width 6 $0\q_int$next[5:0]$11753 + attribute \src "libresoc.v:173127.3-173128.27" + wire width 6 $0\q_int[5:0] + attribute \src "libresoc.v:173129.3-173137.6" + wire width 6 $1\q_int$next[5:0]$11754 + attribute \src "libresoc.v:173106.13-173106.26" + wire width 6 $1\q_int[5:0] + attribute \src "libresoc.v:173119.17-173119.96" + wire width 6 $and$libresoc.v:173119$11743_Y + attribute \src "libresoc.v:173124.17-173124.96" + wire width 6 $and$libresoc.v:173124$11748_Y + attribute \src "libresoc.v:173121.18-173121.93" + wire width 6 $not$libresoc.v:173121$11745_Y + attribute \src "libresoc.v:173123.17-173123.92" + wire width 6 $not$libresoc.v:173123$11747_Y + attribute \src "libresoc.v:173126.17-173126.92" + wire width 6 $not$libresoc.v:173126$11750_Y + attribute \src "libresoc.v:173120.18-173120.98" + wire width 6 $or$libresoc.v:173120$11744_Y + attribute \src "libresoc.v:173122.18-173122.99" + wire width 6 $or$libresoc.v:173122$11746_Y + attribute \src "libresoc.v:173125.17-173125.97" + wire width 6 $or$libresoc.v:173125$11749_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 6 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 6 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 6 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 6 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 6 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 6 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 6 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 6 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:173084.7-173084.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 6 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 6 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 6 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 6 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 6 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 6 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 6 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:173119$11743 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:173119$11743_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:173124$11748 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:173124$11748_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:173121$11745 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_req + connect \Y $not$libresoc.v:173121$11745_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:173123$11747 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \r_req + connect \Y $not$libresoc.v:173123$11747_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:173126$11750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \r_req + connect \Y $not$libresoc.v:173126$11750_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:173120$11744 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$9 + connect \B \s_req + connect \Y $or$libresoc.v:173120$11744_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:173122$11746 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_req + connect \B \q_int + connect \Y $or$libresoc.v:173122$11746_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:173125$11749 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$3 + connect \B \s_req + connect \Y $or$libresoc.v:173125$11749_Y + end + attribute \src "libresoc.v:173084.7-173084.20" + process $proc$libresoc.v:173084$11755 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:173106.13-173106.26" + process $proc$libresoc.v:173106$11756 + assign { } { } + assign $1\q_int[5:0] 6'000000 + sync always + sync init + update \q_int $1\q_int[5:0] + end + attribute \src "libresoc.v:173127.3-173128.27" + process $proc$libresoc.v:173127$11751 + assign { } { } + assign $0\q_int[5:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[5:0] + end + attribute \src "libresoc.v:173129.3-173137.6" + process $proc$libresoc.v:173129$11752 + assign { } { } + assign { } { } + assign $0\q_int$next[5:0]$11753 $1\q_int$next[5:0]$11754 + attribute \src "libresoc.v:173130.5-173130.29" + switch \initial + attribute \src "libresoc.v:173130.9-173130.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[5:0]$11754 6'000000 + case + assign $1\q_int$next[5:0]$11754 \$5 + end + sync always + update \q_int$next $0\q_int$next[5:0]$11753 + end + connect \$9 $and$libresoc.v:173119$11743_Y + connect \$11 $or$libresoc.v:173120$11744_Y + connect \$13 $not$libresoc.v:173121$11745_Y + connect \$15 $or$libresoc.v:173122$11746_Y + connect \$1 $not$libresoc.v:173123$11747_Y + connect \$3 $and$libresoc.v:173124$11748_Y + connect \$5 $or$libresoc.v:173125$11749_Y + connect \$7 $not$libresoc.v:173126$11750_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "libresoc.v:173145.1-173203.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.req_l" +attribute \generator "nMigen" +module \req_l$86 + attribute \src "libresoc.v:173146.7-173146.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:173191.3-173199.6" + wire width 4 $0\q_int$next[3:0]$11767 + attribute \src "libresoc.v:173189.3-173190.27" + wire width 4 $0\q_int[3:0] + attribute \src "libresoc.v:173191.3-173199.6" + wire width 4 $1\q_int$next[3:0]$11768 + attribute \src "libresoc.v:173168.13-173168.25" + wire width 4 $1\q_int[3:0] + attribute \src "libresoc.v:173181.17-173181.96" + wire width 4 $and$libresoc.v:173181$11757_Y + attribute \src "libresoc.v:173186.17-173186.96" + wire width 4 $and$libresoc.v:173186$11762_Y + attribute \src "libresoc.v:173183.18-173183.93" + wire width 4 $not$libresoc.v:173183$11759_Y + attribute \src "libresoc.v:173185.17-173185.92" + wire width 4 $not$libresoc.v:173185$11761_Y + attribute \src "libresoc.v:173188.17-173188.92" + wire width 4 $not$libresoc.v:173188$11764_Y + attribute \src "libresoc.v:173182.18-173182.98" + wire width 4 $or$libresoc.v:173182$11758_Y + attribute \src "libresoc.v:173184.18-173184.99" + wire width 4 $or$libresoc.v:173184$11760_Y + attribute \src "libresoc.v:173187.17-173187.97" + wire width 4 $or$libresoc.v:173187$11763_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 4 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 4 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:173146.7-173146.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 4 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 4 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 4 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:173181$11757 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:173181$11757_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:173186$11762 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:173186$11762_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:173183$11759 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_req + connect \Y $not$libresoc.v:173183$11759_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:173185$11761 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_req + connect \Y $not$libresoc.v:173185$11761_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:173188$11764 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_req + connect \Y $not$libresoc.v:173188$11764_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:173182$11758 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$9 + connect \B \s_req + connect \Y $or$libresoc.v:173182$11758_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:173184$11760 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_req + connect \B \q_int + connect \Y $or$libresoc.v:173184$11760_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:173187$11763 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$3 + connect \B \s_req + connect \Y $or$libresoc.v:173187$11763_Y + end + attribute \src "libresoc.v:173146.7-173146.20" + process $proc$libresoc.v:173146$11769 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:173168.13-173168.25" + process $proc$libresoc.v:173168$11770 + assign { } { } + assign $1\q_int[3:0] 4'0000 + sync always + sync init + update \q_int $1\q_int[3:0] + end + attribute \src "libresoc.v:173189.3-173190.27" + process $proc$libresoc.v:173189$11765 + assign { } { } + assign $0\q_int[3:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[3:0] + end + attribute \src "libresoc.v:173191.3-173199.6" + process $proc$libresoc.v:173191$11766 + assign { } { } + assign { } { } + assign $0\q_int$next[3:0]$11767 $1\q_int$next[3:0]$11768 + attribute \src "libresoc.v:173192.5-173192.29" + switch \initial + attribute \src "libresoc.v:173192.9-173192.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[3:0]$11768 4'0000 + case + assign $1\q_int$next[3:0]$11768 \$5 + end + sync always + update \q_int$next $0\q_int$next[3:0]$11767 + end + connect \$9 $and$libresoc.v:173181$11757_Y + connect \$11 $or$libresoc.v:173182$11758_Y + connect \$13 $not$libresoc.v:173183$11759_Y + connect \$15 $or$libresoc.v:173184$11760_Y + connect \$1 $not$libresoc.v:173185$11761_Y + connect \$3 $and$libresoc.v:173186$11762_Y + connect \$5 $or$libresoc.v:173187$11763_Y + connect \$7 $not$libresoc.v:173188$11764_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "libresoc.v:173207.1-173256.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.reset_l" +attribute \generator "nMigen" +module \reset_l + attribute \src "libresoc.v:173208.7-173208.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:173244.3-173252.6" + wire $0\q_int$next[0:0]$11778 + attribute \src "libresoc.v:173242.3-173243.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:173244.3-173252.6" + wire $1\q_int$next[0:0]$11779 + attribute \src "libresoc.v:173224.7-173224.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:173239.17-173239.96" + wire $and$libresoc.v:173239$11773_Y + attribute \src "libresoc.v:173238.17-173238.94" + wire $not$libresoc.v:173238$11772_Y + attribute \src "libresoc.v:173241.17-173241.94" + wire $not$libresoc.v:173241$11775_Y + attribute \src "libresoc.v:173237.17-173237.100" + wire $or$libresoc.v:173237$11771_Y + attribute \src "libresoc.v:173240.17-173240.99" + wire $or$libresoc.v:173240$11774_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:173208.7-173208.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:173239$11773 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:173239$11773_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:173238$11772 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_reset + connect \Y $not$libresoc.v:173238$11772_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:173241$11775 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_reset + connect \Y $not$libresoc.v:173241$11775_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:173237$11771 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_reset + connect \B \q_int + connect \Y $or$libresoc.v:173237$11771_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:173240$11774 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_reset + connect \Y $or$libresoc.v:173240$11774_Y + end + attribute \src "libresoc.v:173208.7-173208.20" + process $proc$libresoc.v:173208$11780 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:173224.7-173224.19" + process $proc$libresoc.v:173224$11781 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:173242.3-173243.27" + process $proc$libresoc.v:173242$11776 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:173244.3-173252.6" + process $proc$libresoc.v:173244$11777 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11778 $1\q_int$next[0:0]$11779 + attribute \src "libresoc.v:173245.5-173245.29" + switch \initial + attribute \src "libresoc.v:173245.9-173245.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11779 1'0 + case + assign $1\q_int$next[0:0]$11779 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11778 + end + connect \$9 $or$libresoc.v:173237$11771_Y + connect \$1 $not$libresoc.v:173238$11772_Y + connect \$3 $and$libresoc.v:173239$11773_Y + connect \$5 $or$libresoc.v:173240$11774_Y + connect \$7 $not$libresoc.v:173241$11775_Y + connect \qlq_reset \$9 + connect \qn_reset \$7 + connect \q_reset \q_int +end +attribute \src "libresoc.v:173260.1-173309.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.reset_l" +attribute \generator "nMigen" +module \reset_l$131 + attribute \src "libresoc.v:173261.7-173261.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:173297.3-173305.6" + wire $0\q_int$next[0:0]$11789 + attribute \src "libresoc.v:173295.3-173296.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:173297.3-173305.6" + wire $1\q_int$next[0:0]$11790 + attribute \src "libresoc.v:173277.7-173277.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:173292.17-173292.96" + wire $and$libresoc.v:173292$11784_Y + attribute \src "libresoc.v:173291.17-173291.94" + wire $not$libresoc.v:173291$11783_Y + attribute \src "libresoc.v:173294.17-173294.94" + wire $not$libresoc.v:173294$11786_Y + attribute \src "libresoc.v:173290.17-173290.100" + wire $or$libresoc.v:173290$11782_Y + attribute \src "libresoc.v:173293.17-173293.99" + wire $or$libresoc.v:173293$11785_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:173261.7-173261.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:173292$11784 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:173292$11784_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:173291$11783 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_reset + connect \Y $not$libresoc.v:173291$11783_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:173294$11786 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_reset + connect \Y $not$libresoc.v:173294$11786_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:173290$11782 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_reset + connect \B \q_int + connect \Y $or$libresoc.v:173290$11782_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:173293$11785 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_reset + connect \Y $or$libresoc.v:173293$11785_Y + end + attribute \src "libresoc.v:173261.7-173261.20" + process $proc$libresoc.v:173261$11791 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:173277.7-173277.19" + process $proc$libresoc.v:173277$11792 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:173295.3-173296.27" + process $proc$libresoc.v:173295$11787 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:173297.3-173305.6" + process $proc$libresoc.v:173297$11788 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11789 $1\q_int$next[0:0]$11790 + attribute \src "libresoc.v:173298.5-173298.29" + switch \initial + attribute \src "libresoc.v:173298.9-173298.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11790 1'0 + case + assign $1\q_int$next[0:0]$11790 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11789 + end + connect \$9 $or$libresoc.v:173290$11782_Y + connect \$1 $not$libresoc.v:173291$11783_Y + connect \$3 $and$libresoc.v:173292$11784_Y + connect \$5 $or$libresoc.v:173293$11785_Y + connect \$7 $not$libresoc.v:173294$11786_Y + connect \qlq_reset \$9 + connect \qn_reset \$7 + connect \q_reset \q_int +end +attribute \src "libresoc.v:173313.1-173900.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.right_mask" +attribute \generator "nMigen" +module \right_mask + attribute \src "libresoc.v:173314.7-173314.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:173512.3-173899.6" + wire width 64 $0\mask[63:0] + attribute \src "libresoc.v:173512.3-173899.6" + wire $10\mask[9:9] + attribute \src "libresoc.v:173512.3-173899.6" + wire $11\mask[10:10] + attribute \src "libresoc.v:173512.3-173899.6" + wire $12\mask[11:11] + attribute \src "libresoc.v:173512.3-173899.6" + wire $13\mask[12:12] + attribute \src "libresoc.v:173512.3-173899.6" + wire $14\mask[13:13] + attribute \src "libresoc.v:173512.3-173899.6" + wire $15\mask[14:14] + attribute \src "libresoc.v:173512.3-173899.6" + wire $16\mask[15:15] + attribute \src "libresoc.v:173512.3-173899.6" + wire $17\mask[16:16] + attribute \src "libresoc.v:173512.3-173899.6" + wire $18\mask[17:17] + attribute \src "libresoc.v:173512.3-173899.6" + wire $19\mask[18:18] + attribute \src "libresoc.v:173512.3-173899.6" + wire $1\mask[0:0] + attribute \src "libresoc.v:173512.3-173899.6" + wire $20\mask[19:19] + attribute \src "libresoc.v:173512.3-173899.6" + wire $21\mask[20:20] + attribute \src "libresoc.v:173512.3-173899.6" + wire $22\mask[21:21] + attribute \src "libresoc.v:173512.3-173899.6" + wire $23\mask[22:22] + attribute \src "libresoc.v:173512.3-173899.6" + wire $24\mask[23:23] + attribute \src "libresoc.v:173512.3-173899.6" + wire $25\mask[24:24] + attribute \src "libresoc.v:173512.3-173899.6" + wire $26\mask[25:25] + attribute \src "libresoc.v:173512.3-173899.6" + wire $27\mask[26:26] + attribute \src "libresoc.v:173512.3-173899.6" + wire $28\mask[27:27] + attribute \src "libresoc.v:173512.3-173899.6" + wire $29\mask[28:28] + attribute \src "libresoc.v:173512.3-173899.6" + wire $2\mask[1:1] + attribute \src "libresoc.v:173512.3-173899.6" + wire $30\mask[29:29] + attribute \src "libresoc.v:173512.3-173899.6" + wire $31\mask[30:30] + attribute \src "libresoc.v:173512.3-173899.6" + wire $32\mask[31:31] + attribute \src "libresoc.v:173512.3-173899.6" + wire $33\mask[32:32] + attribute \src "libresoc.v:173512.3-173899.6" + wire $34\mask[33:33] + attribute \src "libresoc.v:173512.3-173899.6" + wire $35\mask[34:34] + attribute \src "libresoc.v:173512.3-173899.6" + wire $36\mask[35:35] + attribute \src "libresoc.v:173512.3-173899.6" + wire $37\mask[36:36] + attribute \src "libresoc.v:173512.3-173899.6" + wire $38\mask[37:37] + attribute \src "libresoc.v:173512.3-173899.6" + wire $39\mask[38:38] + attribute \src "libresoc.v:173512.3-173899.6" + wire $3\mask[2:2] + attribute \src "libresoc.v:173512.3-173899.6" + wire $40\mask[39:39] + attribute \src "libresoc.v:173512.3-173899.6" + wire $41\mask[40:40] + attribute \src "libresoc.v:173512.3-173899.6" + wire $42\mask[41:41] + attribute \src "libresoc.v:173512.3-173899.6" + wire $43\mask[42:42] + attribute \src "libresoc.v:173512.3-173899.6" + wire $44\mask[43:43] + attribute \src "libresoc.v:173512.3-173899.6" + wire $45\mask[44:44] + attribute \src "libresoc.v:173512.3-173899.6" + wire $46\mask[45:45] + attribute \src "libresoc.v:173512.3-173899.6" + wire $47\mask[46:46] + attribute \src "libresoc.v:173512.3-173899.6" + wire $48\mask[47:47] + attribute \src "libresoc.v:173512.3-173899.6" + wire $49\mask[48:48] + attribute \src "libresoc.v:173512.3-173899.6" + wire $4\mask[3:3] + attribute \src "libresoc.v:173512.3-173899.6" + wire $50\mask[49:49] + attribute \src "libresoc.v:173512.3-173899.6" + wire $51\mask[50:50] + attribute \src "libresoc.v:173512.3-173899.6" + wire $52\mask[51:51] + attribute \src "libresoc.v:173512.3-173899.6" + wire $53\mask[52:52] + attribute \src "libresoc.v:173512.3-173899.6" + wire $54\mask[53:53] + attribute \src "libresoc.v:173512.3-173899.6" + wire $55\mask[54:54] + attribute \src "libresoc.v:173512.3-173899.6" + wire $56\mask[55:55] + attribute \src "libresoc.v:173512.3-173899.6" + wire $57\mask[56:56] + attribute \src "libresoc.v:173512.3-173899.6" + wire $58\mask[57:57] + attribute \src "libresoc.v:173512.3-173899.6" + wire $59\mask[58:58] + attribute \src "libresoc.v:173512.3-173899.6" + wire $5\mask[4:4] + attribute \src "libresoc.v:173512.3-173899.6" + wire $60\mask[59:59] + attribute \src "libresoc.v:173512.3-173899.6" + wire $61\mask[60:60] + attribute \src "libresoc.v:173512.3-173899.6" + wire $62\mask[61:61] + attribute \src "libresoc.v:173512.3-173899.6" + wire $63\mask[62:62] + attribute \src "libresoc.v:173512.3-173899.6" + wire $64\mask[63:63] + attribute \src "libresoc.v:173512.3-173899.6" + wire $6\mask[5:5] + attribute \src "libresoc.v:173512.3-173899.6" + wire $7\mask[6:6] + attribute \src "libresoc.v:173512.3-173899.6" + wire $8\mask[7:7] + attribute \src "libresoc.v:173512.3-173899.6" + wire $9\mask[8:8] + attribute \src "libresoc.v:173448.17-173448.96" + wire $gt$libresoc.v:173448$11793_Y + attribute \src "libresoc.v:173449.18-173449.98" + wire $gt$libresoc.v:173449$11794_Y + attribute \src "libresoc.v:173450.19-173450.99" + wire $gt$libresoc.v:173450$11795_Y + attribute \src "libresoc.v:173451.19-173451.99" + wire $gt$libresoc.v:173451$11796_Y + attribute \src "libresoc.v:173452.19-173452.99" + wire $gt$libresoc.v:173452$11797_Y + attribute \src "libresoc.v:173453.19-173453.99" + wire $gt$libresoc.v:173453$11798_Y + attribute \src "libresoc.v:173454.19-173454.99" + wire $gt$libresoc.v:173454$11799_Y + attribute \src "libresoc.v:173455.19-173455.99" + wire $gt$libresoc.v:173455$11800_Y + attribute \src "libresoc.v:173456.19-173456.99" + wire $gt$libresoc.v:173456$11801_Y + attribute \src "libresoc.v:173457.19-173457.99" + wire $gt$libresoc.v:173457$11802_Y + attribute \src "libresoc.v:173458.19-173458.99" + wire $gt$libresoc.v:173458$11803_Y + attribute \src "libresoc.v:173459.18-173459.97" + wire $gt$libresoc.v:173459$11804_Y + attribute \src "libresoc.v:173460.19-173460.99" + wire $gt$libresoc.v:173460$11805_Y + attribute \src "libresoc.v:173461.19-173461.99" + wire $gt$libresoc.v:173461$11806_Y + attribute \src "libresoc.v:173462.19-173462.99" + wire $gt$libresoc.v:173462$11807_Y + attribute \src "libresoc.v:173463.19-173463.99" + wire $gt$libresoc.v:173463$11808_Y + attribute \src "libresoc.v:173464.19-173464.99" + wire $gt$libresoc.v:173464$11809_Y + attribute \src "libresoc.v:173465.18-173465.97" + wire $gt$libresoc.v:173465$11810_Y + attribute \src "libresoc.v:173466.18-173466.97" + wire $gt$libresoc.v:173466$11811_Y + attribute \src "libresoc.v:173467.18-173467.97" + wire $gt$libresoc.v:173467$11812_Y + attribute \src "libresoc.v:173468.17-173468.96" + wire $gt$libresoc.v:173468$11813_Y + attribute \src "libresoc.v:173469.18-173469.97" + wire $gt$libresoc.v:173469$11814_Y + attribute \src "libresoc.v:173470.18-173470.97" + wire $gt$libresoc.v:173470$11815_Y + attribute \src "libresoc.v:173471.18-173471.97" + wire $gt$libresoc.v:173471$11816_Y + attribute \src "libresoc.v:173472.18-173472.97" + wire $gt$libresoc.v:173472$11817_Y + attribute \src "libresoc.v:173473.18-173473.97" + wire $gt$libresoc.v:173473$11818_Y + attribute \src "libresoc.v:173474.18-173474.97" + wire $gt$libresoc.v:173474$11819_Y + attribute \src "libresoc.v:173475.18-173475.97" + wire $gt$libresoc.v:173475$11820_Y + attribute \src "libresoc.v:173476.18-173476.98" + wire $gt$libresoc.v:173476$11821_Y + attribute \src "libresoc.v:173477.18-173477.98" + wire $gt$libresoc.v:173477$11822_Y + attribute \src "libresoc.v:173478.18-173478.98" + wire $gt$libresoc.v:173478$11823_Y + attribute \src "libresoc.v:173479.17-173479.96" + wire $gt$libresoc.v:173479$11824_Y + attribute \src "libresoc.v:173480.18-173480.98" + wire $gt$libresoc.v:173480$11825_Y + attribute \src "libresoc.v:173481.18-173481.98" + wire $gt$libresoc.v:173481$11826_Y + attribute \src "libresoc.v:173482.18-173482.98" + wire $gt$libresoc.v:173482$11827_Y + attribute \src "libresoc.v:173483.18-173483.98" + wire $gt$libresoc.v:173483$11828_Y + attribute \src "libresoc.v:173484.18-173484.98" + wire $gt$libresoc.v:173484$11829_Y + attribute \src "libresoc.v:173485.18-173485.98" + wire $gt$libresoc.v:173485$11830_Y + attribute \src "libresoc.v:173486.18-173486.98" + wire $gt$libresoc.v:173486$11831_Y + attribute \src "libresoc.v:173487.18-173487.98" + wire $gt$libresoc.v:173487$11832_Y + attribute \src "libresoc.v:173488.18-173488.98" + wire $gt$libresoc.v:173488$11833_Y + attribute \src "libresoc.v:173489.18-173489.98" + wire $gt$libresoc.v:173489$11834_Y + attribute \src "libresoc.v:173490.17-173490.96" + wire $gt$libresoc.v:173490$11835_Y + attribute \src "libresoc.v:173491.18-173491.98" + wire $gt$libresoc.v:173491$11836_Y + attribute \src "libresoc.v:173492.18-173492.98" + wire $gt$libresoc.v:173492$11837_Y + attribute \src "libresoc.v:173493.18-173493.98" + wire $gt$libresoc.v:173493$11838_Y + attribute \src "libresoc.v:173494.18-173494.98" + wire $gt$libresoc.v:173494$11839_Y + attribute \src "libresoc.v:173495.18-173495.98" + wire $gt$libresoc.v:173495$11840_Y + attribute \src "libresoc.v:173496.18-173496.98" + wire $gt$libresoc.v:173496$11841_Y + attribute \src "libresoc.v:173497.18-173497.98" + wire $gt$libresoc.v:173497$11842_Y + attribute \src "libresoc.v:173498.18-173498.98" + wire $gt$libresoc.v:173498$11843_Y + attribute \src "libresoc.v:173499.18-173499.98" + wire $gt$libresoc.v:173499$11844_Y + attribute \src "libresoc.v:173500.18-173500.98" + wire $gt$libresoc.v:173500$11845_Y + attribute \src "libresoc.v:173501.17-173501.96" + wire $gt$libresoc.v:173501$11846_Y + attribute \src "libresoc.v:173502.18-173502.98" + wire $gt$libresoc.v:173502$11847_Y + attribute \src "libresoc.v:173503.18-173503.98" + wire $gt$libresoc.v:173503$11848_Y + attribute \src "libresoc.v:173504.18-173504.98" + wire $gt$libresoc.v:173504$11849_Y + attribute \src "libresoc.v:173505.18-173505.98" + wire $gt$libresoc.v:173505$11850_Y + attribute \src "libresoc.v:173506.18-173506.98" + wire $gt$libresoc.v:173506$11851_Y + attribute \src "libresoc.v:173507.18-173507.98" + wire $gt$libresoc.v:173507$11852_Y + attribute \src "libresoc.v:173508.18-173508.98" + wire $gt$libresoc.v:173508$11853_Y + attribute \src "libresoc.v:173509.18-173509.98" + wire $gt$libresoc.v:173509$11854_Y + attribute \src "libresoc.v:173510.18-173510.98" + wire $gt$libresoc.v:173510$11855_Y + attribute \src "libresoc.v:173511.18-173511.98" + wire $gt$libresoc.v:173511$11856_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$101 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$103 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$105 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$107 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$109 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$111 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$113 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$115 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$117 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$119 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$121 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$123 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$125 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$127 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$41 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$43 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$45 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$53 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$55 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$57 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$59 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$61 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$63 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$65 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$67 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$69 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$71 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$73 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$75 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$77 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$79 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$81 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$83 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$85 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$87 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$89 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$95 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$99 + attribute \src "libresoc.v:173314.7-173314.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:12" + wire width 64 output 1 \mask + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:11" + wire width 7 input 2 \shift + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:173448$11793 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'100 + connect \Y $gt$libresoc.v:173448$11793_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:173449$11794 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110001 + connect \Y $gt$libresoc.v:173449$11794_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:173450$11795 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110010 + connect \Y $gt$libresoc.v:173450$11795_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:173451$11796 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110011 + connect \Y $gt$libresoc.v:173451$11796_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:173452$11797 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110100 + connect \Y $gt$libresoc.v:173452$11797_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:173453$11798 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110101 + connect \Y $gt$libresoc.v:173453$11798_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:173454$11799 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110110 + connect \Y $gt$libresoc.v:173454$11799_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:173455$11800 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110111 + connect \Y $gt$libresoc.v:173455$11800_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:173456$11801 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111000 + connect \Y $gt$libresoc.v:173456$11801_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:173457$11802 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111001 + connect \Y $gt$libresoc.v:173457$11802_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:173458$11803 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111010 + connect \Y $gt$libresoc.v:173458$11803_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:173459$11804 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'101 + connect \Y $gt$libresoc.v:173459$11804_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:173460$11805 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111011 + connect \Y $gt$libresoc.v:173460$11805_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:173461$11806 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111100 + connect \Y $gt$libresoc.v:173461$11806_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:173462$11807 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111101 + connect \Y $gt$libresoc.v:173462$11807_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:173463$11808 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111110 + connect \Y $gt$libresoc.v:173463$11808_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:173464$11809 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111111 + connect \Y $gt$libresoc.v:173464$11809_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:173465$11810 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'110 + connect \Y $gt$libresoc.v:173465$11810_Y + end + attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:173505$11850 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101010 + connect \Y $gt$libresoc.v:173505$11850_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:173506$11851 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101011 + connect \Y $gt$libresoc.v:173506$11851_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:173507$11852 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101100 + connect \Y $gt$libresoc.v:173507$11852_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:173508$11853 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101101 + connect \Y $gt$libresoc.v:173508$11853_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:173509$11854 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101110 + connect \Y $gt$libresoc.v:173509$11854_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:173510$11855 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101111 + connect \Y $gt$libresoc.v:173510$11855_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:173511$11856 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110000 + connect \Y $gt$libresoc.v:173511$11856_Y + end + attribute \src "libresoc.v:173314.7-173314.20" + process $proc$libresoc.v:173314$11858 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:173512.3-173899.6" + process $proc$libresoc.v:173512$11857 + assign { } { } + assign { } { } + assign $0\mask[63:0] [0] $1\mask[0:0] + assign $0\mask[63:0] [1] $2\mask[1:1] + assign $0\mask[63:0] [2] $3\mask[2:2] + assign $0\mask[63:0] [3] $4\mask[3:3] + assign $0\mask[63:0] [4] $5\mask[4:4] + assign $0\mask[63:0] [5] $6\mask[5:5] + assign $0\mask[63:0] [6] $7\mask[6:6] + assign $0\mask[63:0] [7] $8\mask[7:7] + assign $0\mask[63:0] [8] $9\mask[8:8] + assign $0\mask[63:0] [9] $10\mask[9:9] + assign $0\mask[63:0] [10] $11\mask[10:10] + assign $0\mask[63:0] [11] $12\mask[11:11] + assign $0\mask[63:0] [12] $13\mask[12:12] + assign $0\mask[63:0] [13] $14\mask[13:13] + assign $0\mask[63:0] [14] $15\mask[14:14] + assign $0\mask[63:0] [15] $16\mask[15:15] + assign $0\mask[63:0] [16] $17\mask[16:16] + assign $0\mask[63:0] [17] $18\mask[17:17] + assign $0\mask[63:0] [18] $19\mask[18:18] + assign $0\mask[63:0] [19] $20\mask[19:19] + assign $0\mask[63:0] [20] $21\mask[20:20] + assign $0\mask[63:0] [21] $22\mask[21:21] + assign $0\mask[63:0] [22] $23\mask[22:22] + assign $0\mask[63:0] [23] $24\mask[23:23] + assign $0\mask[63:0] [24] $25\mask[24:24] + assign $0\mask[63:0] [25] $26\mask[25:25] + assign $0\mask[63:0] [26] $27\mask[26:26] + assign $0\mask[63:0] [27] $28\mask[27:27] + assign $0\mask[63:0] [28] $29\mask[28:28] + assign $0\mask[63:0] [29] $30\mask[29:29] + assign $0\mask[63:0] [30] $31\mask[30:30] + assign $0\mask[63:0] [31] $32\mask[31:31] + assign $0\mask[63:0] [32] $33\mask[32:32] + assign $0\mask[63:0] [33] $34\mask[33:33] + assign $0\mask[63:0] [34] $35\mask[34:34] + assign $0\mask[63:0] [35] $36\mask[35:35] + assign $0\mask[63:0] [36] $37\mask[36:36] + assign $0\mask[63:0] [37] $38\mask[37:37] + assign $0\mask[63:0] [38] $39\mask[38:38] + assign $0\mask[63:0] [39] $40\mask[39:39] + assign $0\mask[63:0] [40] $41\mask[40:40] + assign $0\mask[63:0] [41] $42\mask[41:41] + assign $0\mask[63:0] [42] $43\mask[42:42] + assign $0\mask[63:0] [43] $44\mask[43:43] + assign $0\mask[63:0] [44] $45\mask[44:44] + assign $0\mask[63:0] [45] $46\mask[45:45] + assign $0\mask[63:0] [46] $47\mask[46:46] + assign $0\mask[63:0] [47] $48\mask[47:47] + assign $0\mask[63:0] [48] $49\mask[48:48] + assign $0\mask[63:0] [49] $50\mask[49:49] + assign $0\mask[63:0] [50] $51\mask[50:50] + assign $0\mask[63:0] [51] $52\mask[51:51] + assign $0\mask[63:0] [52] $53\mask[52:52] + assign $0\mask[63:0] [53] $54\mask[53:53] + assign $0\mask[63:0] [54] $55\mask[54:54] + assign $0\mask[63:0] [55] $56\mask[55:55] + assign $0\mask[63:0] [56] $57\mask[56:56] + assign $0\mask[63:0] [57] $58\mask[57:57] + assign $0\mask[63:0] [58] $59\mask[58:58] + assign $0\mask[63:0] [59] $60\mask[59:59] + assign $0\mask[63:0] [60] $61\mask[60:60] + assign $0\mask[63:0] [61] $62\mask[61:61] + assign $0\mask[63:0] [62] $63\mask[62:62] + assign $0\mask[63:0] [63] $64\mask[63:63] + attribute \src "libresoc.v:173513.5-173513.29" + switch \initial + attribute \src "libresoc.v:173513.9-173513.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\mask[0:0] 1'1 + case + assign $1\mask[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\mask[1:1] 1'1 + case + assign $2\mask[1:1] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\mask[2:2] 1'1 + case + assign $3\mask[2:2] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\mask[3:3] 1'1 + case + assign $4\mask[3:3] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\mask[4:4] 1'1 + case + assign $5\mask[4:4] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$11 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\mask[5:5] 1'1 + case + assign $6\mask[5:5] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\mask[6:6] 1'1 + case + assign $7\mask[6:6] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\mask[7:7] 1'1 + case + assign $8\mask[7:7] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$17 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\mask[8:8] 1'1 + case + assign $9\mask[8:8] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $10\mask[9:9] 1'1 + case + assign $10\mask[9:9] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$21 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $11\mask[10:10] 1'1 + case + assign $11\mask[10:10] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$23 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $12\mask[11:11] 1'1 + case + assign $12\mask[11:11] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $13\mask[12:12] 1'1 + case + assign $13\mask[12:12] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $14\mask[13:13] 1'1 + case + assign $14\mask[13:13] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $15\mask[14:14] 1'1 + case + assign $15\mask[14:14] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$31 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $16\mask[15:15] 1'1 + case + assign $16\mask[15:15] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$33 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $17\mask[16:16] 1'1 + case + assign $17\mask[16:16] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$35 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $18\mask[17:17] 1'1 + case + assign $18\mask[17:17] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$37 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $19\mask[18:18] 1'1 + case + assign $19\mask[18:18] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$39 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $20\mask[19:19] 1'1 + case + assign $20\mask[19:19] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$41 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $21\mask[20:20] 1'1 + case + assign $21\mask[20:20] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$43 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $22\mask[21:21] 1'1 + case + assign $22\mask[21:21] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$45 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $23\mask[22:22] 1'1 + case + assign $23\mask[22:22] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$47 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $24\mask[23:23] 1'1 + case + assign $24\mask[23:23] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$49 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $25\mask[24:24] 1'1 + case + assign $25\mask[24:24] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$51 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $26\mask[25:25] 1'1 + case + assign $26\mask[25:25] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$53 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $27\mask[26:26] 1'1 + case + assign $27\mask[26:26] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$55 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $28\mask[27:27] 1'1 + case + assign $28\mask[27:27] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$57 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $29\mask[28:28] 1'1 + case + assign $29\mask[28:28] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$59 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $30\mask[29:29] 1'1 + case + assign $30\mask[29:29] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$61 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $31\mask[30:30] 1'1 + case + assign $31\mask[30:30] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$63 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $32\mask[31:31] 1'1 + case + assign $32\mask[31:31] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$65 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $33\mask[32:32] 1'1 + case + assign $33\mask[32:32] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$67 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $34\mask[33:33] 1'1 + case + assign $34\mask[33:33] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$69 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $35\mask[34:34] 1'1 + case + assign $35\mask[34:34] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$71 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $36\mask[35:35] 1'1 + case + assign $36\mask[35:35] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$73 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $37\mask[36:36] 1'1 + case + assign $37\mask[36:36] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$75 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $38\mask[37:37] 1'1 + case + assign $38\mask[37:37] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$77 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $39\mask[38:38] 1'1 + case + assign $39\mask[38:38] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$79 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $40\mask[39:39] 1'1 + case + assign $40\mask[39:39] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$81 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $41\mask[40:40] 1'1 + case + assign $41\mask[40:40] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$83 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $42\mask[41:41] 1'1 + case + assign $42\mask[41:41] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$85 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $43\mask[42:42] 1'1 + case + assign $43\mask[42:42] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$87 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $44\mask[43:43] 1'1 + case + assign $44\mask[43:43] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$89 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $45\mask[44:44] 1'1 + case + assign $45\mask[44:44] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$91 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $46\mask[45:45] 1'1 + case + assign $46\mask[45:45] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$93 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $47\mask[46:46] 1'1 + case + assign $47\mask[46:46] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$95 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $48\mask[47:47] 1'1 + case + assign $48\mask[47:47] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$97 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $49\mask[48:48] 1'1 + case + assign $49\mask[48:48] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$99 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $50\mask[49:49] 1'1 + case + assign $50\mask[49:49] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$101 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $51\mask[50:50] 1'1 + case + assign $51\mask[50:50] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$103 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $52\mask[51:51] 1'1 + case + assign $52\mask[51:51] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$105 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $53\mask[52:52] 1'1 + case + assign $53\mask[52:52] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$107 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $54\mask[53:53] 1'1 + case + assign $54\mask[53:53] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$109 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $55\mask[54:54] 1'1 + case + assign $55\mask[54:54] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$111 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $56\mask[55:55] 1'1 + case + assign $56\mask[55:55] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$113 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $57\mask[56:56] 1'1 + case + assign $57\mask[56:56] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$115 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $58\mask[57:57] 1'1 + case + assign $58\mask[57:57] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$117 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $59\mask[58:58] 1'1 + case + assign $59\mask[58:58] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$119 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $60\mask[59:59] 1'1 + case + assign $60\mask[59:59] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$121 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $61\mask[60:60] 1'1 + case + assign $61\mask[60:60] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$123 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $62\mask[61:61] 1'1 + case + assign $62\mask[61:61] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$125 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $63\mask[62:62] 1'1 + case + assign $63\mask[62:62] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$127 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $64\mask[63:63] 1'1 + case + assign $64\mask[63:63] 1'0 + end + sync always + update \mask $0\mask[63:0] + end + connect \$9 $gt$libresoc.v:173448$11793_Y + connect \$99 $gt$libresoc.v:173449$11794_Y + connect \$101 $gt$libresoc.v:173450$11795_Y + connect \$103 $gt$libresoc.v:173451$11796_Y + connect \$105 $gt$libresoc.v:173452$11797_Y + connect \$107 $gt$libresoc.v:173453$11798_Y + connect \$109 $gt$libresoc.v:173454$11799_Y + connect \$111 $gt$libresoc.v:173455$11800_Y + connect \$113 $gt$libresoc.v:173456$11801_Y + connect \$115 $gt$libresoc.v:173457$11802_Y + connect \$117 $gt$libresoc.v:173458$11803_Y + connect \$11 $gt$libresoc.v:173459$11804_Y + connect \$119 $gt$libresoc.v:173460$11805_Y + connect \$121 $gt$libresoc.v:173461$11806_Y + connect \$123 $gt$libresoc.v:173462$11807_Y + connect \$125 $gt$libresoc.v:173463$11808_Y + connect \$127 $gt$libresoc.v:173464$11809_Y + connect \$13 $gt$libresoc.v:173465$11810_Y + connect \$15 $gt$libresoc.v:173466$11811_Y + connect \$17 $gt$libresoc.v:173467$11812_Y + connect \$1 $gt$libresoc.v:173468$11813_Y + connect \$19 $gt$libresoc.v:173469$11814_Y + connect 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$gt$libresoc.v:173492$11837_Y + connect \$63 $gt$libresoc.v:173493$11838_Y + connect \$65 $gt$libresoc.v:173494$11839_Y + connect \$67 $gt$libresoc.v:173495$11840_Y + connect \$69 $gt$libresoc.v:173496$11841_Y + connect \$71 $gt$libresoc.v:173497$11842_Y + connect \$73 $gt$libresoc.v:173498$11843_Y + connect \$75 $gt$libresoc.v:173499$11844_Y + connect \$77 $gt$libresoc.v:173500$11845_Y + connect \$7 $gt$libresoc.v:173501$11846_Y + connect \$79 $gt$libresoc.v:173502$11847_Y + connect \$81 $gt$libresoc.v:173503$11848_Y + connect \$83 $gt$libresoc.v:173504$11849_Y + connect \$85 $gt$libresoc.v:173505$11850_Y + connect \$87 $gt$libresoc.v:173506$11851_Y + connect \$89 $gt$libresoc.v:173507$11852_Y + connect \$91 $gt$libresoc.v:173508$11853_Y + connect \$93 $gt$libresoc.v:173509$11854_Y + connect \$95 $gt$libresoc.v:173510$11855_Y + connect \$97 $gt$libresoc.v:173511$11856_Y +end +attribute \src "libresoc.v:173904.1-173962.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy 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"libresoc.v:173943.18-173943.100" + wire $or$libresoc.v:173943$11862_Y + attribute \src "libresoc.v:173946.17-173946.98" + wire $or$libresoc.v:173946$11865_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:173905.7-173905.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:173940$11859 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:173940$11859_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:173945$11864 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:173945$11864_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:173942$11861 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$libresoc.v:173942$11861_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:173944$11863 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:173944$11863_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:173947$11866 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:173947$11866_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:173941$11860 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$libresoc.v:173941$11860_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:173943$11862 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$libresoc.v:173943$11862_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:173946$11865 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$libresoc.v:173946$11865_Y + end + attribute \src "libresoc.v:173905.7-173905.20" + process $proc$libresoc.v:173905$11871 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:173927.7-173927.19" + process $proc$libresoc.v:173927$11872 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:173948.3-173949.27" + process $proc$libresoc.v:173948$11867 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:173950.3-173958.6" + process $proc$libresoc.v:173950$11868 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11869 $1\q_int$next[0:0]$11870 + attribute \src "libresoc.v:173951.5-173951.29" + switch \initial + attribute \src "libresoc.v:173951.9-173951.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11870 1'0 + case + assign $1\q_int$next[0:0]$11870 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11869 + end + connect \$9 $and$libresoc.v:173940$11859_Y + connect \$11 $or$libresoc.v:173941$11860_Y + connect \$13 $not$libresoc.v:173942$11861_Y + connect \$15 $or$libresoc.v:173943$11862_Y + connect \$1 $not$libresoc.v:173944$11863_Y + connect \$3 $and$libresoc.v:173945$11864_Y + connect \$5 $or$libresoc.v:173946$11865_Y + connect \$7 $not$libresoc.v:173947$11866_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "libresoc.v:173966.1-174024.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.rok_l" +attribute \generator "nMigen" +module \rok_l$105 + attribute \src "libresoc.v:173967.7-173967.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:174012.3-174020.6" + wire $0\q_int$next[0:0]$11883 + attribute \src "libresoc.v:174010.3-174011.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:174012.3-174020.6" + wire $1\q_int$next[0:0]$11884 + attribute \src "libresoc.v:173989.7-173989.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:174002.17-174002.96" + wire $and$libresoc.v:174002$11873_Y + attribute \src "libresoc.v:174007.17-174007.96" + wire $and$libresoc.v:174007$11878_Y + attribute \src "libresoc.v:174004.18-174004.94" + wire $not$libresoc.v:174004$11875_Y + attribute \src "libresoc.v:174006.17-174006.93" + wire $not$libresoc.v:174006$11877_Y + attribute \src "libresoc.v:174009.17-174009.93" + wire $not$libresoc.v:174009$11880_Y + attribute \src "libresoc.v:174003.18-174003.99" + wire $or$libresoc.v:174003$11874_Y + attribute \src "libresoc.v:174005.18-174005.100" + wire $or$libresoc.v:174005$11876_Y + attribute \src "libresoc.v:174008.17-174008.98" + wire $or$libresoc.v:174008$11879_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:173967.7-173967.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:174002$11873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:174002$11873_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:174007$11878 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:174007$11878_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:174004$11875 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$libresoc.v:174004$11875_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:174006$11877 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:174006$11877_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:174009$11880 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:174009$11880_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:174003$11874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$libresoc.v:174003$11874_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:174005$11876 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$libresoc.v:174005$11876_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:174008$11879 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$libresoc.v:174008$11879_Y + end + attribute \src "libresoc.v:173967.7-173967.20" + process $proc$libresoc.v:173967$11885 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:173989.7-173989.19" + process $proc$libresoc.v:173989$11886 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:174010.3-174011.27" + process $proc$libresoc.v:174010$11881 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:174012.3-174020.6" + process $proc$libresoc.v:174012$11882 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11883 $1\q_int$next[0:0]$11884 + attribute \src "libresoc.v:174013.5-174013.29" + switch \initial + attribute \src "libresoc.v:174013.9-174013.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11884 1'0 + case + assign $1\q_int$next[0:0]$11884 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11883 + end + connect \$9 $and$libresoc.v:174002$11873_Y + connect \$11 $or$libresoc.v:174003$11874_Y + connect \$13 $not$libresoc.v:174004$11875_Y + connect \$15 $or$libresoc.v:174005$11876_Y + connect \$1 $not$libresoc.v:174006$11877_Y + connect \$3 $and$libresoc.v:174007$11878_Y + connect \$5 $or$libresoc.v:174008$11879_Y + connect \$7 $not$libresoc.v:174009$11880_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "libresoc.v:174028.1-174086.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.rok_l" +attribute \generator "nMigen" +module \rok_l$123 + attribute \src "libresoc.v:174029.7-174029.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:174074.3-174082.6" + wire $0\q_int$next[0:0]$11897 + attribute \src "libresoc.v:174072.3-174073.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:174074.3-174082.6" + wire $1\q_int$next[0:0]$11898 + attribute \src "libresoc.v:174051.7-174051.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:174064.17-174064.96" + wire $and$libresoc.v:174064$11887_Y + attribute \src "libresoc.v:174069.17-174069.96" + wire $and$libresoc.v:174069$11892_Y + attribute \src "libresoc.v:174066.18-174066.94" + wire $not$libresoc.v:174066$11889_Y + attribute \src "libresoc.v:174068.17-174068.93" + wire $not$libresoc.v:174068$11891_Y + attribute \src "libresoc.v:174071.17-174071.93" + wire $not$libresoc.v:174071$11894_Y + attribute \src "libresoc.v:174065.18-174065.99" + wire $or$libresoc.v:174065$11888_Y + attribute \src "libresoc.v:174067.18-174067.100" + wire $or$libresoc.v:174067$11890_Y + attribute \src "libresoc.v:174070.17-174070.98" + wire $or$libresoc.v:174070$11893_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:174029.7-174029.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:174064$11887 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:174064$11887_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:174069$11892 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:174069$11892_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:174066$11889 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$libresoc.v:174066$11889_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:174068$11891 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:174068$11891_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:174071$11894 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:174071$11894_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:174065$11888 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$libresoc.v:174065$11888_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:174067$11890 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$libresoc.v:174067$11890_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:174070$11893 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$libresoc.v:174070$11893_Y + end + attribute \src "libresoc.v:174029.7-174029.20" + process $proc$libresoc.v:174029$11899 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:174051.7-174051.19" + process $proc$libresoc.v:174051$11900 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:174072.3-174073.27" + process $proc$libresoc.v:174072$11895 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:174074.3-174082.6" + process $proc$libresoc.v:174074$11896 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11897 $1\q_int$next[0:0]$11898 + attribute \src "libresoc.v:174075.5-174075.29" + switch \initial + attribute \src "libresoc.v:174075.9-174075.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11898 1'0 + case + assign $1\q_int$next[0:0]$11898 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11897 + end + connect \$9 $and$libresoc.v:174064$11887_Y + connect \$11 $or$libresoc.v:174065$11888_Y + connect \$13 $not$libresoc.v:174066$11889_Y + connect \$15 $or$libresoc.v:174067$11890_Y + connect \$1 $not$libresoc.v:174068$11891_Y + connect \$3 $and$libresoc.v:174069$11892_Y + connect \$5 $or$libresoc.v:174070$11893_Y + connect \$7 $not$libresoc.v:174071$11894_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "libresoc.v:174090.1-174148.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.rok_l" +attribute \generator "nMigen" +module \rok_l$14 + attribute \src "libresoc.v:174091.7-174091.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:174136.3-174144.6" + wire $0\q_int$next[0:0]$11911 + attribute \src "libresoc.v:174134.3-174135.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:174136.3-174144.6" + wire $1\q_int$next[0:0]$11912 + attribute \src "libresoc.v:174113.7-174113.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:174126.17-174126.96" + wire $and$libresoc.v:174126$11901_Y + attribute \src "libresoc.v:174131.17-174131.96" + wire $and$libresoc.v:174131$11906_Y + attribute \src "libresoc.v:174128.18-174128.94" + wire $not$libresoc.v:174128$11903_Y + attribute \src "libresoc.v:174130.17-174130.93" + wire $not$libresoc.v:174130$11905_Y + attribute \src "libresoc.v:174133.17-174133.93" + wire $not$libresoc.v:174133$11908_Y + attribute \src "libresoc.v:174127.18-174127.99" + wire $or$libresoc.v:174127$11902_Y + attribute \src "libresoc.v:174129.18-174129.100" + wire $or$libresoc.v:174129$11904_Y + attribute \src "libresoc.v:174132.17-174132.98" + wire $or$libresoc.v:174132$11907_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:174091.7-174091.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:174126$11901 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:174126$11901_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:174131$11906 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:174131$11906_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:174128$11903 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$libresoc.v:174128$11903_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:174130$11905 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:174130$11905_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:174133$11908 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:174133$11908_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:174127$11902 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$libresoc.v:174127$11902_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:174129$11904 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$libresoc.v:174129$11904_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:174132$11907 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$libresoc.v:174132$11907_Y + end + attribute \src "libresoc.v:174091.7-174091.20" + process $proc$libresoc.v:174091$11913 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:174113.7-174113.19" + process $proc$libresoc.v:174113$11914 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:174134.3-174135.27" + process $proc$libresoc.v:174134$11909 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:174136.3-174144.6" + process $proc$libresoc.v:174136$11910 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11911 $1\q_int$next[0:0]$11912 + attribute \src "libresoc.v:174137.5-174137.29" + switch \initial + attribute \src "libresoc.v:174137.9-174137.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11912 1'0 + case + assign $1\q_int$next[0:0]$11912 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11911 + end + connect \$9 $and$libresoc.v:174126$11901_Y + connect \$11 $or$libresoc.v:174127$11902_Y + connect \$13 $not$libresoc.v:174128$11903_Y + connect \$15 $or$libresoc.v:174129$11904_Y + connect \$1 $not$libresoc.v:174130$11905_Y + connect \$3 $and$libresoc.v:174131$11906_Y + connect \$5 $or$libresoc.v:174132$11907_Y + connect \$7 $not$libresoc.v:174133$11908_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "libresoc.v:174152.1-174210.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.rok_l" +attribute \generator "nMigen" +module \rok_l$27 + attribute \src "libresoc.v:174153.7-174153.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:174198.3-174206.6" + wire $0\q_int$next[0:0]$11925 + attribute \src "libresoc.v:174196.3-174197.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:174198.3-174206.6" + wire $1\q_int$next[0:0]$11926 + attribute \src "libresoc.v:174175.7-174175.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:174188.17-174188.96" + wire $and$libresoc.v:174188$11915_Y + attribute \src "libresoc.v:174193.17-174193.96" + wire $and$libresoc.v:174193$11920_Y + attribute \src "libresoc.v:174190.18-174190.94" + wire $not$libresoc.v:174190$11917_Y + attribute \src "libresoc.v:174192.17-174192.93" + wire $not$libresoc.v:174192$11919_Y + attribute \src "libresoc.v:174195.17-174195.93" + wire $not$libresoc.v:174195$11922_Y + attribute \src "libresoc.v:174189.18-174189.99" + wire $or$libresoc.v:174189$11916_Y + attribute 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"/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:174153.7-174153.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:174188$11915 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:174188$11915_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:174193$11920 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:174193$11920_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:174190$11917 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$libresoc.v:174190$11917_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:174192$11919 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:174192$11919_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:174195$11922 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:174195$11922_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:174189$11916 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$libresoc.v:174189$11916_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:174191$11918 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$libresoc.v:174191$11918_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:174194$11921 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$libresoc.v:174194$11921_Y + end + attribute \src "libresoc.v:174153.7-174153.20" + process $proc$libresoc.v:174153$11927 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:174175.7-174175.19" + process $proc$libresoc.v:174175$11928 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:174196.3-174197.27" + process $proc$libresoc.v:174196$11923 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:174198.3-174206.6" + process $proc$libresoc.v:174198$11924 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11925 $1\q_int$next[0:0]$11926 + attribute \src "libresoc.v:174199.5-174199.29" + switch \initial + attribute \src "libresoc.v:174199.9-174199.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11926 1'0 + case + assign $1\q_int$next[0:0]$11926 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11925 + end + connect \$9 $and$libresoc.v:174188$11915_Y + connect \$11 $or$libresoc.v:174189$11916_Y + connect \$13 $not$libresoc.v:174190$11917_Y + connect \$15 $or$libresoc.v:174191$11918_Y + connect \$1 $not$libresoc.v:174192$11919_Y + connect \$3 $and$libresoc.v:174193$11920_Y + connect \$5 $or$libresoc.v:174194$11921_Y + connect \$7 $not$libresoc.v:174195$11922_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "libresoc.v:174214.1-174272.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.rok_l" +attribute \generator "nMigen" +module \rok_l$43 + attribute \src "libresoc.v:174215.7-174215.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:174260.3-174268.6" + wire $0\q_int$next[0:0]$11939 + attribute \src "libresoc.v:174258.3-174259.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:174260.3-174268.6" + wire $1\q_int$next[0:0]$11940 + attribute \src "libresoc.v:174237.7-174237.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:174250.17-174250.96" + wire $and$libresoc.v:174250$11929_Y + attribute \src "libresoc.v:174255.17-174255.96" + wire $and$libresoc.v:174255$11934_Y + attribute \src "libresoc.v:174252.18-174252.94" + wire $not$libresoc.v:174252$11931_Y + attribute \src "libresoc.v:174254.17-174254.93" + wire $not$libresoc.v:174254$11933_Y + attribute \src "libresoc.v:174257.17-174257.93" + wire $not$libresoc.v:174257$11936_Y + attribute \src "libresoc.v:174251.18-174251.99" + wire $or$libresoc.v:174251$11930_Y + attribute \src "libresoc.v:174253.18-174253.100" + wire $or$libresoc.v:174253$11932_Y + attribute \src "libresoc.v:174256.17-174256.98" + wire $or$libresoc.v:174256$11935_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:174215.7-174215.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:174250$11929 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:174250$11929_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:174255$11934 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:174255$11934_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:174252$11931 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$libresoc.v:174252$11931_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:174254$11933 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:174254$11933_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:174257$11936 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:174257$11936_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:174251$11930 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$libresoc.v:174251$11930_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:174253$11932 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$libresoc.v:174253$11932_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:174256$11935 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$libresoc.v:174256$11935_Y + end + attribute \src "libresoc.v:174215.7-174215.20" + process $proc$libresoc.v:174215$11941 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:174237.7-174237.19" + process $proc$libresoc.v:174237$11942 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:174258.3-174259.27" + process $proc$libresoc.v:174258$11937 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:174260.3-174268.6" + process $proc$libresoc.v:174260$11938 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11939 $1\q_int$next[0:0]$11940 + attribute \src "libresoc.v:174261.5-174261.29" + switch \initial + attribute \src "libresoc.v:174261.9-174261.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11940 1'0 + case + assign $1\q_int$next[0:0]$11940 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11939 + end + connect \$9 $and$libresoc.v:174250$11929_Y + connect \$11 $or$libresoc.v:174251$11930_Y + connect \$13 $not$libresoc.v:174252$11931_Y + connect \$15 $or$libresoc.v:174253$11932_Y + connect \$1 $not$libresoc.v:174254$11933_Y + connect \$3 $and$libresoc.v:174255$11934_Y + connect \$5 $or$libresoc.v:174256$11935_Y + connect \$7 $not$libresoc.v:174257$11936_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "libresoc.v:174276.1-174334.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.rok_l" +attribute \generator "nMigen" +module \rok_l$59 + attribute \src "libresoc.v:174277.7-174277.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:174322.3-174330.6" + wire $0\q_int$next[0:0]$11953 + attribute \src "libresoc.v:174320.3-174321.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:174322.3-174330.6" + wire $1\q_int$next[0:0]$11954 + attribute \src "libresoc.v:174299.7-174299.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:174312.17-174312.96" + wire $and$libresoc.v:174312$11943_Y + attribute \src "libresoc.v:174317.17-174317.96" + wire $and$libresoc.v:174317$11948_Y + attribute \src "libresoc.v:174314.18-174314.94" + wire $not$libresoc.v:174314$11945_Y + attribute \src "libresoc.v:174316.17-174316.93" + wire $not$libresoc.v:174316$11947_Y + attribute \src "libresoc.v:174319.17-174319.93" + wire $not$libresoc.v:174319$11950_Y + attribute \src "libresoc.v:174313.18-174313.99" + wire $or$libresoc.v:174313$11944_Y + attribute \src "libresoc.v:174315.18-174315.100" + wire $or$libresoc.v:174315$11946_Y + attribute \src "libresoc.v:174318.17-174318.98" + wire $or$libresoc.v:174318$11949_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:174277.7-174277.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:174312$11943 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:174312$11943_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:174317$11948 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:174317$11948_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:174314$11945 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$libresoc.v:174314$11945_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:174316$11947 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:174316$11947_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:174319$11950 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:174319$11950_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:174313$11944 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$libresoc.v:174313$11944_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:174315$11946 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$libresoc.v:174315$11946_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:174318$11949 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$libresoc.v:174318$11949_Y + end + attribute \src "libresoc.v:174277.7-174277.20" + process $proc$libresoc.v:174277$11955 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:174299.7-174299.19" + process $proc$libresoc.v:174299$11956 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:174320.3-174321.27" + process $proc$libresoc.v:174320$11951 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:174322.3-174330.6" + process $proc$libresoc.v:174322$11952 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11953 $1\q_int$next[0:0]$11954 + attribute \src "libresoc.v:174323.5-174323.29" + switch \initial + attribute \src "libresoc.v:174323.9-174323.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11954 1'0 + case + assign $1\q_int$next[0:0]$11954 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11953 + end + connect \$9 $and$libresoc.v:174312$11943_Y + connect \$11 $or$libresoc.v:174313$11944_Y + connect \$13 $not$libresoc.v:174314$11945_Y + connect \$15 $or$libresoc.v:174315$11946_Y + connect \$1 $not$libresoc.v:174316$11947_Y + connect \$3 $and$libresoc.v:174317$11948_Y + connect \$5 $or$libresoc.v:174318$11949_Y + connect \$7 $not$libresoc.v:174319$11950_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "libresoc.v:174338.1-174396.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.rok_l" +attribute \generator "nMigen" +module \rok_l$71 + attribute \src "libresoc.v:174339.7-174339.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:174384.3-174392.6" + wire $0\q_int$next[0:0]$11967 + attribute \src "libresoc.v:174382.3-174383.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:174384.3-174392.6" + wire $1\q_int$next[0:0]$11968 + attribute \src "libresoc.v:174361.7-174361.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:174374.17-174374.96" + wire $and$libresoc.v:174374$11957_Y + attribute \src "libresoc.v:174379.17-174379.96" + wire $and$libresoc.v:174379$11962_Y + attribute \src "libresoc.v:174376.18-174376.94" + wire $not$libresoc.v:174376$11959_Y + attribute \src "libresoc.v:174378.17-174378.93" + wire $not$libresoc.v:174378$11961_Y + attribute \src "libresoc.v:174381.17-174381.93" + wire $not$libresoc.v:174381$11964_Y + attribute \src "libresoc.v:174375.18-174375.99" + wire $or$libresoc.v:174375$11958_Y + attribute \src "libresoc.v:174377.18-174377.100" + wire $or$libresoc.v:174377$11960_Y + attribute \src "libresoc.v:174380.17-174380.98" + wire $or$libresoc.v:174380$11963_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:174339.7-174339.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:174374$11957 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:174374$11957_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:174379$11962 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:174379$11962_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:174376$11959 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$libresoc.v:174376$11959_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:174378$11961 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:174378$11961_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:174381$11964 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:174381$11964_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:174375$11958 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$libresoc.v:174375$11958_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:174377$11960 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$libresoc.v:174377$11960_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:174380$11963 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$libresoc.v:174380$11963_Y + end + attribute \src "libresoc.v:174339.7-174339.20" + process $proc$libresoc.v:174339$11969 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:174361.7-174361.19" + process $proc$libresoc.v:174361$11970 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:174382.3-174383.27" + process $proc$libresoc.v:174382$11965 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:174384.3-174392.6" + process $proc$libresoc.v:174384$11966 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11967 $1\q_int$next[0:0]$11968 + attribute \src "libresoc.v:174385.5-174385.29" + switch \initial + attribute \src "libresoc.v:174385.9-174385.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11968 1'0 + case + assign $1\q_int$next[0:0]$11968 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11967 + end + connect \$9 $and$libresoc.v:174374$11957_Y + connect \$11 $or$libresoc.v:174375$11958_Y + connect \$13 $not$libresoc.v:174376$11959_Y + connect \$15 $or$libresoc.v:174377$11960_Y + connect \$1 $not$libresoc.v:174378$11961_Y + connect \$3 $and$libresoc.v:174379$11962_Y + connect \$5 $or$libresoc.v:174380$11963_Y + connect \$7 $not$libresoc.v:174381$11964_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "libresoc.v:174400.1-174458.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy 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\src "libresoc.v:174439.18-174439.100" + wire $or$libresoc.v:174439$11974_Y + attribute \src "libresoc.v:174442.17-174442.98" + wire $or$libresoc.v:174442$11977_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:174401.7-174401.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:174436$11971 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:174436$11971_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:174441$11976 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:174441$11976_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:174438$11973 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$libresoc.v:174438$11973_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:174440$11975 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:174440$11975_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:174443$11978 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:174443$11978_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:174437$11972 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$libresoc.v:174437$11972_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:174439$11974 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$libresoc.v:174439$11974_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:174442$11977 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$libresoc.v:174442$11977_Y + end + attribute \src "libresoc.v:174401.7-174401.20" + process $proc$libresoc.v:174401$11983 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:174423.7-174423.19" + process $proc$libresoc.v:174423$11984 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:174444.3-174445.27" + process $proc$libresoc.v:174444$11979 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:174446.3-174454.6" + process $proc$libresoc.v:174446$11980 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11981 $1\q_int$next[0:0]$11982 + attribute \src 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$not$libresoc.v:174632$12006 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_32bit + connect \Y $not$libresoc.v:174632$12006_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" + cell $not $not$libresoc.v:174634$12008 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \$51 + connect \Y $not$libresoc.v:174634$12008_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" + cell $not $not$libresoc.v:174640$12014 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \$63 + connect \Y $not$libresoc.v:174640$12014_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" + cell $not $not$libresoc.v:174645$12019 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \mr + connect \Y $not$libresoc.v:174645$12019_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" + cell $not $not$libresoc.v:174647$12021 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ml + connect \Y $not$libresoc.v:174647$12021_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" + cell $or $or$libresoc.v:174626$12000 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$36 + connect \B \right_shift + connect \Y $or$libresoc.v:174626$12000_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" + cell $or $or$libresoc.v:174636$12010 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \$48 + connect \B \$54 + connect \Y $or$libresoc.v:174636$12010_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" + cell $or $or$libresoc.v:174637$12011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \mr + connect \B \ml + connect \Y $or$libresoc.v:174637$12011_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" + cell $or $or$libresoc.v:174639$12013 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \mr + connect \B \ml + connect \Y $or$libresoc.v:174639$12013_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" + cell $or $or$libresoc.v:174642$12016 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \$60 + connect \B \$66 + connect \Y $or$libresoc.v:174642$12016_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" + cell $or $or$libresoc.v:174646$12020 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \rot + connect \B \$72 + connect \Y $or$libresoc.v:174646$12020_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" + cell $pos $pos$libresoc.v:174612$11986 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A $extend$libresoc.v:174612$11985_Y + connect \Y $pos$libresoc.v:174612$11986_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" + cell $reduce_or $reduce_or$libresoc.v:174649$12023 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \$79 + connect \Y $reduce_or$libresoc.v:174649$12023_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144" + cell $sub $sub$libresoc.v:174619$11993 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A 7'1000000 + connect \B \mb$8 + connect \Y $sub$libresoc.v:174619$11993_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151" + cell $sub $sub$libresoc.v:174622$11996 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A 6'111111 + connect \B \me$13 + connect \Y $sub$libresoc.v:174622$11996_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:174650.13-174653.4" + cell \left_mask \left_mask + connect \mask \left_mask_mask + connect \shift \left_mask_shift + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:174654.14-174657.4" + cell \right_mask \right_mask + connect \mask \right_mask_mask + connect \shift \right_mask_shift + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:174658.8-174662.4" + cell \rotl \rotl + connect \a \rotl_a + connect \b \rotl_b + connect \o \rotl_o + end + attribute \src "libresoc.v:174463.7-174463.20" + process $proc$libresoc.v:174463$12039 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:174663.3-174677.6" + process $proc$libresoc.v:174663$12024 + assign { } { } + assign $0\hi32[31:0] $1\hi32[31:0] + attribute \src "libresoc.v:174664.5-174664.29" + switch \initial + attribute \src "libresoc.v:174664.9-174664.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:85" + switch { \sign_ext_rs \is_32bit } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\hi32[31:0] \rs [31:0] + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\hi32[31:0] { \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\hi32[31:0] \rs [63:32] + end + sync always + update \hi32 $0\hi32[31:0] + end + attribute \src "libresoc.v:174678.3-174687.6" + process $proc$libresoc.v:174678$12025 + assign { } { } + assign { } { } + assign $0\right_mask_shift[6:0] $1\right_mask_shift[6:0] + attribute \src "libresoc.v:174679.5-174679.29" + switch \initial + attribute \src "libresoc.v:174679.9-174679.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" + switch \$22 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\right_mask_shift[6:0] \$24 [6:0] + case + assign $1\right_mask_shift[6:0] 7'0000000 + end + sync always + update \right_mask_shift $0\right_mask_shift[6:0] + end + attribute \src "libresoc.v:174688.3-174699.6" + process $proc$libresoc.v:174688$12026 + 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"libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\output_mode[1:0] { 1'1 \$40 } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\output_mode[1:0] { 1'0 \$44 } + end + sync always + update \output_mode $0\output_mode[1:0] + end + attribute \src "libresoc.v:174712.3-174730.6" + process $proc$libresoc.v:174712$12028 + assign { } { } + assign { } { } + assign $0\result_o[63:0] $1\result_o[63:0] + attribute \src "libresoc.v:174713.5-174713.29" + switch \initial + attribute \src "libresoc.v:174713.9-174713.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:168" + switch \output_mode + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\result_o[63:0] \$56 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\result_o[63:0] \$68 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\result_o[63:0] \$70 + attribute \src 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always + update \mb$8 $0\mb$8[6:0]$12032 + end + attribute \src "libresoc.v:174787.3-174801.6" + process $proc$libresoc.v:174787$12036 + assign { } { } + assign $0\me$13[6:0]$12037 $1\me$13[6:0]$12038 + attribute \src "libresoc.v:174788.5-174788.29" + switch \initial + attribute \src "libresoc.v:174788.9-174788.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" + switch { \$18 \$14 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\me$13[6:0]$12038 { 2'01 \me } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\me$13[6:0]$12038 { 1'0 \mb_extra \mb } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\me$13[6:0]$12038 { \sh [6] \$20 } + end + sync always + update \me$13 $0\me$13[6:0]$12037 + end + connect \$9 $pos$libresoc.v:174612$11986_Y + connect \$11 $not$libresoc.v:174613$11987_Y + connect \$14 $and$libresoc.v:174614$11988_Y + connect \$16 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\$58 $or$libresoc.v:174637$12011_Y + connect \$60 $and$libresoc.v:174638$12012_Y + connect \$63 $or$libresoc.v:174639$12013_Y + connect \$62 $not$libresoc.v:174640$12014_Y + connect \$66 $and$libresoc.v:174641$12015_Y + connect \$68 $or$libresoc.v:174642$12016_Y + connect \$6 $and$libresoc.v:174643$12017_Y + connect \$70 $and$libresoc.v:174644$12018_Y + connect \$72 $not$libresoc.v:174645$12019_Y + connect \$74 $or$libresoc.v:174646$12020_Y + connect \$77 $not$libresoc.v:174647$12021_Y + connect \$79 $and$libresoc.v:174648$12022_Y + connect \$76 $reduce_or$libresoc.v:174649$12023_Y + connect \$1 \$2 + connect \$24 \$25 + connect \$29 \$30 + connect \ml \$32 + connect \left_mask_shift \$30 [6:0] + connect \sh { \$6 \shift [5:0] } + connect \rot \rotl_o + connect \rotl_b \rot_count + connect \rotl_a \repl32 + connect \shift_signed \shift [5:0] + connect \repl32 { \hi32 \rs [31:0] } +end +attribute \src "libresoc.v:174817.1-174831.10" +attribute \cells_not_processed 1 +attribute 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\B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 128 + connect \A { \a \a } + connect \B \$2 + connect \Y $shr$libresoc.v:174829$12041_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" + cell $sub $sub$libresoc.v:174828$12040 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 8 + connect \A 7'1000000 + connect \B \b + connect \Y $sub$libresoc.v:174828$12040_Y + end + connect \$2 $sub$libresoc.v:174828$12040_Y + connect \$1 $shr$libresoc.v:174829$12041_Y [63:0] + connect \o \$1 +end +attribute \src "libresoc.v:174835.1-174893.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.rst_l" +attribute \generator "nMigen" +module \rst_l + attribute \src "libresoc.v:174836.7-174836.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:174881.3-174889.6" + wire $0\q_int$next[0:0]$12052 + attribute \src "libresoc.v:174879.3-174880.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:174881.3-174889.6" + wire $1\q_int$next[0:0]$12053 + attribute \src "libresoc.v:174858.7-174858.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:174871.17-174871.96" + wire $and$libresoc.v:174871$12042_Y + attribute \src "libresoc.v:174876.17-174876.96" + wire $and$libresoc.v:174876$12047_Y + attribute \src "libresoc.v:174873.18-174873.93" + wire $not$libresoc.v:174873$12044_Y + attribute \src "libresoc.v:174875.17-174875.92" + wire $not$libresoc.v:174875$12046_Y + attribute \src "libresoc.v:174878.17-174878.92" + wire $not$libresoc.v:174878$12049_Y + attribute \src "libresoc.v:174872.18-174872.98" + wire $or$libresoc.v:174872$12043_Y + attribute \src "libresoc.v:174874.18-174874.99" + wire $or$libresoc.v:174874$12045_Y + attribute \src "libresoc.v:174877.17-174877.97" + wire $or$libresoc.v:174877$12048_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 4 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:174836.7-174836.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:174871$12042 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:174871$12042_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:174876$12047 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:174876$12047_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:174873$12044 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$libresoc.v:174873$12044_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:174875$12046 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:174875$12046_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:174878$12049 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:174878$12049_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:174872$12043 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$libresoc.v:174872$12043_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:174874$12045 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$libresoc.v:174874$12045_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:174877$12048 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$libresoc.v:174877$12048_Y + end + attribute \src "libresoc.v:174836.7-174836.20" + process $proc$libresoc.v:174836$12054 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:174858.7-174858.19" + process $proc$libresoc.v:174858$12055 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:174879.3-174880.27" + process $proc$libresoc.v:174879$12050 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:174881.3-174889.6" + process $proc$libresoc.v:174881$12051 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12052 $1\q_int$next[0:0]$12053 + attribute \src "libresoc.v:174882.5-174882.29" + switch \initial + attribute \src "libresoc.v:174882.9-174882.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12053 1'0 + case + assign $1\q_int$next[0:0]$12053 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12052 + end + connect \$9 $and$libresoc.v:174871$12042_Y + connect \$11 $or$libresoc.v:174872$12043_Y + connect \$13 $not$libresoc.v:174873$12044_Y + connect \$15 $or$libresoc.v:174874$12045_Y + connect \$1 $not$libresoc.v:174875$12046_Y + connect \$3 $and$libresoc.v:174876$12047_Y + connect \$5 $or$libresoc.v:174877$12048_Y + connect \$7 $not$libresoc.v:174878$12049_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "libresoc.v:174897.1-174955.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.rst_l" +attribute \generator "nMigen" +module \rst_l$104 + attribute \src "libresoc.v:174898.7-174898.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:174943.3-174951.6" + wire $0\q_int$next[0:0]$12066 + attribute \src "libresoc.v:174941.3-174942.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:174943.3-174951.6" + wire $1\q_int$next[0:0]$12067 + attribute \src "libresoc.v:174920.7-174920.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:174933.17-174933.96" + wire $and$libresoc.v:174933$12056_Y + attribute \src "libresoc.v:174938.17-174938.96" + wire $and$libresoc.v:174938$12061_Y + attribute \src "libresoc.v:174935.18-174935.93" + wire $not$libresoc.v:174935$12058_Y + attribute \src "libresoc.v:174937.17-174937.92" + wire $not$libresoc.v:174937$12060_Y + attribute \src "libresoc.v:174940.17-174940.92" + wire $not$libresoc.v:174940$12063_Y + attribute \src "libresoc.v:174934.18-174934.98" + wire $or$libresoc.v:174934$12057_Y + attribute \src "libresoc.v:174936.18-174936.99" + wire $or$libresoc.v:174936$12059_Y + attribute \src "libresoc.v:174939.17-174939.97" + wire $or$libresoc.v:174939$12062_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 4 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:174898.7-174898.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:174933$12056 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:174933$12056_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:174938$12061 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:174938$12061_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:174935$12058 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$libresoc.v:174935$12058_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:174937$12060 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:174937$12060_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:174940$12063 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:174940$12063_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:174934$12057 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$libresoc.v:174934$12057_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:174936$12059 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$libresoc.v:174936$12059_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:174939$12062 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$libresoc.v:174939$12062_Y + end + attribute \src "libresoc.v:174898.7-174898.20" + process $proc$libresoc.v:174898$12068 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:174920.7-174920.19" + process $proc$libresoc.v:174920$12069 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:174941.3-174942.27" + process $proc$libresoc.v:174941$12064 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:174943.3-174951.6" + process $proc$libresoc.v:174943$12065 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12066 $1\q_int$next[0:0]$12067 + attribute \src "libresoc.v:174944.5-174944.29" + switch \initial + attribute \src "libresoc.v:174944.9-174944.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12067 1'0 + case + assign $1\q_int$next[0:0]$12067 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12066 + end + connect \$9 $and$libresoc.v:174933$12056_Y + connect \$11 $or$libresoc.v:174934$12057_Y + connect \$13 $not$libresoc.v:174935$12058_Y + connect \$15 $or$libresoc.v:174936$12059_Y + connect \$1 $not$libresoc.v:174937$12060_Y + connect \$3 $and$libresoc.v:174938$12061_Y + connect \$5 $or$libresoc.v:174939$12062_Y + connect \$7 $not$libresoc.v:174940$12063_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "libresoc.v:174959.1-175017.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.rst_l" +attribute \generator "nMigen" +module \rst_l$122 + attribute \src "libresoc.v:174960.7-174960.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:175005.3-175013.6" + wire $0\q_int$next[0:0]$12080 + attribute \src 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\A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:175000$12075_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:174997$12072 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$libresoc.v:174997$12072_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:174999$12074 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:174999$12074_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:175002$12077 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:175002$12077_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:174996$12071 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$libresoc.v:174996$12071_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:174998$12073 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$libresoc.v:174998$12073_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:175001$12076 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$libresoc.v:175001$12076_Y + end + attribute \src "libresoc.v:174960.7-174960.20" + process $proc$libresoc.v:174960$12082 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:174982.7-174982.19" + process $proc$libresoc.v:174982$12083 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:175003.3-175004.27" + process $proc$libresoc.v:175003$12078 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:175005.3-175013.6" + process $proc$libresoc.v:175005$12079 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12080 $1\q_int$next[0:0]$12081 + attribute \src "libresoc.v:175006.5-175006.29" + switch \initial + attribute \src "libresoc.v:175006.9-175006.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12081 1'0 + case + assign $1\q_int$next[0:0]$12081 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12080 + end + connect \$9 $and$libresoc.v:174995$12070_Y + connect \$11 $or$libresoc.v:174996$12071_Y + connect \$13 $not$libresoc.v:174997$12072_Y + connect \$15 $or$libresoc.v:174998$12073_Y + connect \$1 $not$libresoc.v:174999$12074_Y + connect \$3 $and$libresoc.v:175000$12075_Y + connect \$5 $or$libresoc.v:175001$12076_Y + connect \$7 $not$libresoc.v:175002$12077_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "libresoc.v:175021.1-175079.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.rst_l" +attribute \generator "nMigen" +module \rst_l$129 + attribute \src "libresoc.v:175022.7-175022.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:175067.3-175075.6" + wire $0\q_int$next[0:0]$12094 + attribute \src "libresoc.v:175065.3-175066.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:175067.3-175075.6" + wire $1\q_int$next[0:0]$12095 + attribute \src "libresoc.v:175044.7-175044.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:175057.17-175057.96" + wire $and$libresoc.v:175057$12084_Y + attribute \src "libresoc.v:175062.17-175062.96" + wire $and$libresoc.v:175062$12089_Y + attribute \src "libresoc.v:175059.18-175059.93" + wire $not$libresoc.v:175059$12086_Y + attribute \src "libresoc.v:175061.17-175061.92" + wire $not$libresoc.v:175061$12088_Y + attribute \src "libresoc.v:175064.17-175064.92" + wire $not$libresoc.v:175064$12091_Y + attribute \src "libresoc.v:175058.18-175058.98" + wire $or$libresoc.v:175058$12085_Y + attribute \src "libresoc.v:175060.18-175060.99" + wire $or$libresoc.v:175060$12087_Y + attribute \src "libresoc.v:175063.17-175063.97" + wire $or$libresoc.v:175063$12090_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:175022.7-175022.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:175057$12084 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:175057$12084_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:175062$12089 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:175062$12089_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:175059$12086 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$libresoc.v:175059$12086_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:175061$12088 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:175061$12088_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:175064$12091 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:175064$12091_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:175058$12085 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$libresoc.v:175058$12085_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:175060$12087 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$libresoc.v:175060$12087_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:175063$12090 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$libresoc.v:175063$12090_Y + end + attribute \src "libresoc.v:175022.7-175022.20" + process $proc$libresoc.v:175022$12096 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:175044.7-175044.19" + process $proc$libresoc.v:175044$12097 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:175065.3-175066.27" + process $proc$libresoc.v:175065$12092 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:175067.3-175075.6" + process $proc$libresoc.v:175067$12093 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12094 $1\q_int$next[0:0]$12095 + attribute \src "libresoc.v:175068.5-175068.29" + switch \initial + attribute \src "libresoc.v:175068.9-175068.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12095 1'0 + case + assign $1\q_int$next[0:0]$12095 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12094 + end + connect \$9 $and$libresoc.v:175057$12084_Y + connect \$11 $or$libresoc.v:175058$12085_Y + connect \$13 $not$libresoc.v:175059$12086_Y + connect \$15 $or$libresoc.v:175060$12087_Y + connect \$1 $not$libresoc.v:175061$12088_Y + connect \$3 $and$libresoc.v:175062$12089_Y + connect \$5 $or$libresoc.v:175063$12090_Y + connect \$7 $not$libresoc.v:175064$12091_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "libresoc.v:175083.1-175141.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.rst_l" +attribute \generator "nMigen" +module \rst_l$13 + attribute \src "libresoc.v:175084.7-175084.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:175129.3-175137.6" + wire $0\q_int$next[0:0]$12108 + attribute \src "libresoc.v:175127.3-175128.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:175129.3-175137.6" + wire $1\q_int$next[0:0]$12109 + attribute \src "libresoc.v:175106.7-175106.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:175119.17-175119.96" + wire $and$libresoc.v:175119$12098_Y + attribute \src "libresoc.v:175124.17-175124.96" + wire $and$libresoc.v:175124$12103_Y + attribute \src "libresoc.v:175121.18-175121.93" + wire $not$libresoc.v:175121$12100_Y + attribute \src "libresoc.v:175123.17-175123.92" + wire $not$libresoc.v:175123$12102_Y + attribute \src "libresoc.v:175126.17-175126.92" + wire $not$libresoc.v:175126$12105_Y + attribute \src "libresoc.v:175120.18-175120.98" + wire $or$libresoc.v:175120$12099_Y + attribute \src "libresoc.v:175122.18-175122.99" + wire $or$libresoc.v:175122$12101_Y + attribute \src "libresoc.v:175125.17-175125.97" + wire $or$libresoc.v:175125$12104_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 4 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:175084.7-175084.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:175119$12098 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:175119$12098_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:175124$12103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:175124$12103_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:175121$12100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$libresoc.v:175121$12100_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:175123$12102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:175123$12102_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:175126$12105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:175126$12105_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:175120$12099 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$libresoc.v:175120$12099_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:175122$12101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$libresoc.v:175122$12101_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:175125$12104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$libresoc.v:175125$12104_Y + end + attribute \src "libresoc.v:175084.7-175084.20" + process $proc$libresoc.v:175084$12110 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:175106.7-175106.19" + process $proc$libresoc.v:175106$12111 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:175127.3-175128.27" + process $proc$libresoc.v:175127$12106 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:175129.3-175137.6" + process $proc$libresoc.v:175129$12107 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12108 $1\q_int$next[0:0]$12109 + attribute \src "libresoc.v:175130.5-175130.29" + switch \initial + attribute \src "libresoc.v:175130.9-175130.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12109 1'0 + case + assign $1\q_int$next[0:0]$12109 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12108 + end + connect \$9 $and$libresoc.v:175119$12098_Y + connect \$11 $or$libresoc.v:175120$12099_Y + connect \$13 $not$libresoc.v:175121$12100_Y + connect \$15 $or$libresoc.v:175122$12101_Y + connect \$1 $not$libresoc.v:175123$12102_Y + connect \$3 $and$libresoc.v:175124$12103_Y + connect \$5 $or$libresoc.v:175125$12104_Y + connect \$7 $not$libresoc.v:175126$12105_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "libresoc.v:175145.1-175203.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.rst_l" +attribute \generator "nMigen" +module \rst_l$26 + attribute \src "libresoc.v:175146.7-175146.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:175191.3-175199.6" + wire $0\q_int$next[0:0]$12122 + attribute \src "libresoc.v:175189.3-175190.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:175191.3-175199.6" + wire $1\q_int$next[0:0]$12123 + attribute \src "libresoc.v:175168.7-175168.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:175181.17-175181.96" + wire $and$libresoc.v:175181$12112_Y + attribute \src "libresoc.v:175186.17-175186.96" + wire $and$libresoc.v:175186$12117_Y + attribute \src "libresoc.v:175183.18-175183.93" + wire $not$libresoc.v:175183$12114_Y + attribute \src "libresoc.v:175185.17-175185.92" + wire $not$libresoc.v:175185$12116_Y + attribute \src "libresoc.v:175188.17-175188.92" + wire $not$libresoc.v:175188$12119_Y + attribute \src "libresoc.v:175182.18-175182.98" + wire $or$libresoc.v:175182$12113_Y + attribute \src "libresoc.v:175184.18-175184.99" + wire $or$libresoc.v:175184$12115_Y + attribute \src "libresoc.v:175187.17-175187.97" + wire $or$libresoc.v:175187$12118_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 4 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:175146.7-175146.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:175181$12112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:175181$12112_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:175186$12117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:175186$12117_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:175183$12114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$libresoc.v:175183$12114_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:175185$12116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:175185$12116_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:175188$12119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:175188$12119_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:175182$12113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$libresoc.v:175182$12113_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:175184$12115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$libresoc.v:175184$12115_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:175187$12118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$libresoc.v:175187$12118_Y + end + attribute \src "libresoc.v:175146.7-175146.20" + process $proc$libresoc.v:175146$12124 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:175168.7-175168.19" + process $proc$libresoc.v:175168$12125 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:175189.3-175190.27" + process $proc$libresoc.v:175189$12120 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:175191.3-175199.6" + process $proc$libresoc.v:175191$12121 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12122 $1\q_int$next[0:0]$12123 + attribute \src "libresoc.v:175192.5-175192.29" + switch \initial + attribute \src "libresoc.v:175192.9-175192.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12123 1'0 + case + assign $1\q_int$next[0:0]$12123 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12122 + end + connect \$9 $and$libresoc.v:175181$12112_Y + connect \$11 $or$libresoc.v:175182$12113_Y + connect \$13 $not$libresoc.v:175183$12114_Y + connect \$15 $or$libresoc.v:175184$12115_Y + connect \$1 $not$libresoc.v:175185$12116_Y + connect \$3 $and$libresoc.v:175186$12117_Y + connect \$5 $or$libresoc.v:175187$12118_Y + connect \$7 $not$libresoc.v:175188$12119_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "libresoc.v:175207.1-175265.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.rst_l" +attribute \generator "nMigen" +module \rst_l$42 + attribute \src "libresoc.v:175208.7-175208.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:175253.3-175261.6" + wire $0\q_int$next[0:0]$12136 + attribute \src "libresoc.v:175251.3-175252.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:175253.3-175261.6" + wire $1\q_int$next[0:0]$12137 + attribute \src "libresoc.v:175230.7-175230.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:175243.17-175243.96" + wire $and$libresoc.v:175243$12126_Y + attribute \src "libresoc.v:175248.17-175248.96" + wire $and$libresoc.v:175248$12131_Y + attribute \src "libresoc.v:175245.18-175245.93" + wire $not$libresoc.v:175245$12128_Y + attribute \src "libresoc.v:175247.17-175247.92" + wire $not$libresoc.v:175247$12130_Y + attribute \src "libresoc.v:175250.17-175250.92" + wire $not$libresoc.v:175250$12133_Y + attribute \src "libresoc.v:175244.18-175244.98" + wire $or$libresoc.v:175244$12127_Y + attribute \src "libresoc.v:175246.18-175246.99" + wire $or$libresoc.v:175246$12129_Y + attribute \src "libresoc.v:175249.17-175249.97" + wire $or$libresoc.v:175249$12132_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 4 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:175208.7-175208.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:175243$12126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:175243$12126_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:175248$12131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:175248$12131_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:175245$12128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$libresoc.v:175245$12128_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:175247$12130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:175247$12130_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:175250$12133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:175250$12133_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:175244$12127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$libresoc.v:175244$12127_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:175246$12129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$libresoc.v:175246$12129_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:175249$12132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$libresoc.v:175249$12132_Y + end + attribute \src "libresoc.v:175208.7-175208.20" + process $proc$libresoc.v:175208$12138 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:175230.7-175230.19" + process $proc$libresoc.v:175230$12139 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:175251.3-175252.27" + process $proc$libresoc.v:175251$12134 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:175253.3-175261.6" + process $proc$libresoc.v:175253$12135 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12136 $1\q_int$next[0:0]$12137 + attribute \src "libresoc.v:175254.5-175254.29" + switch \initial + attribute \src "libresoc.v:175254.9-175254.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12137 1'0 + case + assign $1\q_int$next[0:0]$12137 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12136 + end + connect \$9 $and$libresoc.v:175243$12126_Y + connect \$11 $or$libresoc.v:175244$12127_Y + connect \$13 $not$libresoc.v:175245$12128_Y + connect \$15 $or$libresoc.v:175246$12129_Y + connect \$1 $not$libresoc.v:175247$12130_Y + connect \$3 $and$libresoc.v:175248$12131_Y + connect \$5 $or$libresoc.v:175249$12132_Y + connect \$7 $not$libresoc.v:175250$12133_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "libresoc.v:175269.1-175327.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.rst_l" +attribute \generator "nMigen" +module \rst_l$58 + attribute \src "libresoc.v:175270.7-175270.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:175315.3-175323.6" + wire $0\q_int$next[0:0]$12150 + attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:175305$12140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:175305$12140_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:175310$12145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:175310$12145_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:175307$12142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$libresoc.v:175307$12142_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:175309$12144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:175309$12144_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:175312$12147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:175312$12147_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:175306$12141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$libresoc.v:175306$12141_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:175308$12143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$libresoc.v:175308$12143_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:175311$12146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$libresoc.v:175311$12146_Y + end + attribute \src "libresoc.v:175270.7-175270.20" + process $proc$libresoc.v:175270$12152 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:175292.7-175292.19" + process $proc$libresoc.v:175292$12153 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:175313.3-175314.27" + process $proc$libresoc.v:175313$12148 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:175315.3-175323.6" + process $proc$libresoc.v:175315$12149 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12150 $1\q_int$next[0:0]$12151 + attribute \src "libresoc.v:175316.5-175316.29" + switch \initial + attribute \src "libresoc.v:175316.9-175316.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12151 1'0 + case + assign $1\q_int$next[0:0]$12151 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12150 + end + connect \$9 $and$libresoc.v:175305$12140_Y + connect \$11 $or$libresoc.v:175306$12141_Y + connect \$13 $not$libresoc.v:175307$12142_Y + connect \$15 $or$libresoc.v:175308$12143_Y + connect \$1 $not$libresoc.v:175309$12144_Y + connect \$3 $and$libresoc.v:175310$12145_Y + connect \$5 $or$libresoc.v:175311$12146_Y + connect \$7 $not$libresoc.v:175312$12147_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "libresoc.v:175331.1-175389.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.rst_l" +attribute \generator "nMigen" +module \rst_l$70 + attribute \src "libresoc.v:175332.7-175332.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:175377.3-175385.6" + wire $0\q_int$next[0:0]$12164 + attribute \src "libresoc.v:175375.3-175376.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:175377.3-175385.6" + wire $1\q_int$next[0:0]$12165 + attribute \src "libresoc.v:175354.7-175354.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:175367.17-175367.96" + wire $and$libresoc.v:175367$12154_Y + attribute \src "libresoc.v:175372.17-175372.96" + wire $and$libresoc.v:175372$12159_Y + attribute \src "libresoc.v:175369.18-175369.93" + wire $not$libresoc.v:175369$12156_Y + attribute \src "libresoc.v:175371.17-175371.92" + wire $not$libresoc.v:175371$12158_Y + attribute \src "libresoc.v:175374.17-175374.92" + wire $not$libresoc.v:175374$12161_Y + attribute \src "libresoc.v:175368.18-175368.98" + wire $or$libresoc.v:175368$12155_Y + attribute \src "libresoc.v:175370.18-175370.99" + wire $or$libresoc.v:175370$12157_Y + attribute \src "libresoc.v:175373.17-175373.97" + wire $or$libresoc.v:175373$12160_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 4 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:175332.7-175332.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:175367$12154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:175367$12154_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:175372$12159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:175372$12159_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:175369$12156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$libresoc.v:175369$12156_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:175371$12158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:175371$12158_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:175374$12161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:175374$12161_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:175368$12155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$libresoc.v:175368$12155_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:175370$12157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$libresoc.v:175370$12157_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:175373$12160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$libresoc.v:175373$12160_Y + end + attribute \src "libresoc.v:175332.7-175332.20" + process $proc$libresoc.v:175332$12166 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:175354.7-175354.19" + process $proc$libresoc.v:175354$12167 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:175375.3-175376.27" + process $proc$libresoc.v:175375$12162 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:175377.3-175385.6" + process $proc$libresoc.v:175377$12163 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12164 $1\q_int$next[0:0]$12165 + attribute \src "libresoc.v:175378.5-175378.29" + switch \initial + attribute \src "libresoc.v:175378.9-175378.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12165 1'0 + case + assign $1\q_int$next[0:0]$12165 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12164 + end + connect \$9 $and$libresoc.v:175367$12154_Y + connect \$11 $or$libresoc.v:175368$12155_Y + connect \$13 $not$libresoc.v:175369$12156_Y + connect \$15 $or$libresoc.v:175370$12157_Y + connect \$1 $not$libresoc.v:175371$12158_Y + connect \$3 $and$libresoc.v:175372$12159_Y + connect \$5 $or$libresoc.v:175373$12160_Y + connect \$7 $not$libresoc.v:175374$12161_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "libresoc.v:175393.1-175451.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.rst_l" +attribute \generator "nMigen" +module \rst_l$87 + attribute \src "libresoc.v:175394.7-175394.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:175439.3-175447.6" + wire $0\q_int$next[0:0]$12178 + attribute \src "libresoc.v:175437.3-175438.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:175439.3-175447.6" + wire $1\q_int$next[0:0]$12179 + attribute \src "libresoc.v:175416.7-175416.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:175429.17-175429.96" + wire $and$libresoc.v:175429$12168_Y + attribute \src "libresoc.v:175434.17-175434.96" + wire $and$libresoc.v:175434$12173_Y + attribute \src "libresoc.v:175431.18-175431.93" + wire $not$libresoc.v:175431$12170_Y + attribute \src "libresoc.v:175433.17-175433.92" + wire $not$libresoc.v:175433$12172_Y + attribute \src "libresoc.v:175436.17-175436.92" + wire $not$libresoc.v:175436$12175_Y + attribute \src "libresoc.v:175430.18-175430.98" + wire $or$libresoc.v:175430$12169_Y + attribute \src "libresoc.v:175432.18-175432.99" + wire $or$libresoc.v:175432$12171_Y + attribute \src "libresoc.v:175435.17-175435.97" + wire $or$libresoc.v:175435$12174_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 4 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:175394.7-175394.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:175429$12168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:175429$12168_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:175434$12173 + parameter \A_SIGNED 0 + parameter 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\enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute 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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 50 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 22 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 output 49 \operation + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 41 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" + cell $and $and$libresoc.v:175795$12183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$21 + connect \B \logical_op__is_signed + connect \Y $and$libresoc.v:175795$12183_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" + cell $and $and$libresoc.v:175797$12185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$25 + connect \B \logical_op__is_signed + connect \Y $and$libresoc.v:175797$12185_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" + cell $and $and$libresoc.v:175806$12198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$43 + connect \B \$45 + connect \Y $and$libresoc.v:175806$12198_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" + cell $and $and$libresoc.v:175809$12201 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$49 + connect \B \$51 + connect \Y $and$libresoc.v:175809$12201_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" + cell $eq $eq$libresoc.v:175805$12197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \logical_op__insn_type + connect \B 7'0011110 + connect \Y $eq$libresoc.v:175805$12197_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" + cell $eq $eq$libresoc.v:175808$12200 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \logical_op__insn_type + connect \B 7'0011110 + connect \Y $eq$libresoc.v:175808$12200_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" + cell $eq $eq$libresoc.v:175811$12203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $eq$libresoc.v:175811$12203_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" + cell $pos $extend$libresoc.v:175798$12186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \rb + connect \Y $extend$libresoc.v:175798$12186_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$libresoc.v:175799$12188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \rb + connect \Y $extend$libresoc.v:175799$12188_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" + cell $pos $extend$libresoc.v:175801$12191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \ra + connect \Y $extend$libresoc.v:175801$12191_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$libresoc.v:175802$12193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \ra + connect \Y $extend$libresoc.v:175802$12193_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" + cell $pos $extend$libresoc.v:175814$12206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 95 + parameter \Y_WIDTH 128 + connect \A \$62 + connect \Y $extend$libresoc.v:175814$12206_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" + cell $ge $ge$libresoc.v:175804$12196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \abs_dend + connect \B \abs_dor + connect \Y $ge$libresoc.v:175804$12196_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" + cell $ge $ge$libresoc.v:175807$12199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \abs_dend [31:0] + connect \B \abs_dor [31:0] + connect \Y $ge$libresoc.v:175807$12199_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" + cell $neg $neg$libresoc.v:175798$12187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:175798$12186_Y + connect \Y $neg$libresoc.v:175798$12187_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" + cell $neg $neg$libresoc.v:175801$12192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:175801$12191_Y + connect \Y $neg$libresoc.v:175801$12192_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:175799$12189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:175799$12188_Y + connect \Y $pos$libresoc.v:175799$12189_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:175802$12194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:175802$12193_Y + connect \Y $pos$libresoc.v:175802$12194_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" + cell $pos $pos$libresoc.v:175814$12207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \Y_WIDTH 128 + connect \A $extend$libresoc.v:175814$12206_Y + connect \Y $pos$libresoc.v:175814$12207_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" + cell $sshl $sshl$libresoc.v:175813$12205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 95 + connect \A \abs_dend [31:0] + connect \B 6'100000 + connect \Y $sshl$libresoc.v:175813$12205_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" + cell $sshl $sshl$libresoc.v:175815$12208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 191 + connect \A \abs_dend + connect \B 7'1000000 + connect \Y $sshl$libresoc.v:175815$12208_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" + cell $mux $ternary$libresoc.v:175794$12182 + parameter \WIDTH 1 + connect \A \ra [63] + connect \B \ra [31] + connect \S \logical_op__is_32bit + connect \Y $ternary$libresoc.v:175794$12182_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" + cell $mux $ternary$libresoc.v:175796$12184 + parameter \WIDTH 1 + connect \A \rb [63] + connect \B \rb [31] + connect \S \logical_op__is_32bit + connect \Y $ternary$libresoc.v:175796$12184_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" + cell $mux $ternary$libresoc.v:175800$12190 + parameter \WIDTH 65 + connect \A \$32 + connect \B \$30 + connect \S \divisor_neg + connect \Y $ternary$libresoc.v:175800$12190_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" + cell $mux $ternary$libresoc.v:175803$12195 + parameter \WIDTH 65 + connect \A \$39 + connect \B \$37 + connect \S \dividend_neg + connect \Y $ternary$libresoc.v:175803$12195_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" + cell $mux $ternary$libresoc.v:175810$12202 + parameter \WIDTH 32 + connect \A \abs_dor [63:32] + connect \B 0 + connect \S \logical_op__is_32bit + connect \Y $ternary$libresoc.v:175810$12202_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" + cell $mux $ternary$libresoc.v:175812$12204 + parameter \WIDTH 32 + connect \A \abs_dend [63:32] + connect \B 0 + connect \S \logical_op__is_32bit + connect \Y $ternary$libresoc.v:175812$12204_Y + end + attribute \src "libresoc.v:175456.7-175456.20" + process $proc$libresoc.v:175456$12210 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:175816.3-175841.6" + process $proc$libresoc.v:175816$12209 + assign { } { } + assign { } { } + assign $0\dividend[127:0] $1\dividend[127:0] + attribute \src "libresoc.v:175817.5-175817.29" + switch \initial + attribute \src "libresoc.v:175817.9-175817.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:72" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0011101 , 7'0101111 + assign $1\dividend[127:0] [127:64] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dividend[127:0] [31:0] \abs_dend [31:0] + assign $1\dividend[127:0] [63:32] \$59 + attribute \src "libresoc.v:0.0-0.0" + case 7'0011110 + assign { } { } + assign $1\dividend[127:0] $2\dividend[127:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:78" + switch \logical_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dividend[127:0] \$61 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dividend[127:0] \$65 [127:0] + end + case + assign $1\dividend[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dividend $0\dividend[127:0] + end + connect \$21 $ternary$libresoc.v:175794$12182_Y + connect \$23 $and$libresoc.v:175795$12183_Y + connect \$25 $ternary$libresoc.v:175796$12184_Y + connect \$27 $and$libresoc.v:175797$12185_Y + connect \$30 $neg$libresoc.v:175798$12187_Y + connect \$32 $pos$libresoc.v:175799$12189_Y + connect \$34 $ternary$libresoc.v:175800$12190_Y + connect \$37 $neg$libresoc.v:175801$12192_Y + connect \$39 $pos$libresoc.v:175802$12194_Y + connect \$41 $ternary$libresoc.v:175803$12195_Y + connect \$43 $ge$libresoc.v:175804$12196_Y + connect \$45 $eq$libresoc.v:175805$12197_Y + connect \$47 $and$libresoc.v:175806$12198_Y + connect \$49 $ge$libresoc.v:175807$12199_Y + connect \$51 $eq$libresoc.v:175808$12200_Y + connect \$53 $and$libresoc.v:175809$12201_Y + connect \$55 $ternary$libresoc.v:175810$12202_Y + connect \$57 $eq$libresoc.v:175811$12203_Y + connect \$59 $ternary$libresoc.v:175812$12204_Y + connect \$62 $sshl$libresoc.v:175813$12205_Y + connect \$61 $pos$libresoc.v:175814$12207_Y + connect \$66 $sshl$libresoc.v:175815$12208_Y + connect \$29 \$34 + connect \$36 \$41 + connect \$65 \$66 + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$20 \xer_so + connect \div_by_zero \$57 + connect \divisor_radicand [63:32] \$55 + connect \divisor_radicand [31:0] \abs_dor [31:0] + connect \dive_abs_ov32 \$53 + connect \dive_abs_ov64 \$47 + connect \abs_dend \$41 [63:0] + connect \abs_dor \$34 [63:0] + connect \divisor_neg \$27 + connect \dividend_neg \$23 + connect \operation 2'01 +end +attribute \src "libresoc.v:175862.1-177063.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0" +attribute \generator "nMigen" +module \shiftrot0 + attribute \src "libresoc.v:176634.3-176635.25" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:176632.3-176633.46" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:176983.3-176991.6" + wire $0\alu_l_r_alu$next[0:0]$12428 + attribute \src "libresoc.v:176550.3-176551.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:176820.3-176857.6" + wire width 12 $0\alu_shift_rot0_sr_op__fn_unit$next[11:0]$12345 + attribute \src "libresoc.v:176578.3-176579.75" + wire width 12 $0\alu_shift_rot0_sr_op__fn_unit[11:0] + attribute \src "libresoc.v:176820.3-176857.6" + wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12346 + attribute \src "libresoc.v:176580.3-176581.89" + wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data[63:0] + attribute \src "libresoc.v:176820.3-176857.6" + wire $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12347 + attribute \src "libresoc.v:176582.3-176583.85" + wire $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] + attribute \src "libresoc.v:176820.3-176857.6" + wire width 2 $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12348 + attribute \src "libresoc.v:176596.3-176597.83" + wire width 2 $0\alu_shift_rot0_sr_op__input_carry[1:0] + attribute \src "libresoc.v:176820.3-176857.6" + wire $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12349 + attribute \src "libresoc.v:176600.3-176601.77" + wire $0\alu_shift_rot0_sr_op__input_cr[0:0] + attribute \src "libresoc.v:176820.3-176857.6" + wire width 32 $0\alu_shift_rot0_sr_op__insn$next[31:0]$12350 + attribute \src "libresoc.v:176608.3-176609.69" + wire width 32 $0\alu_shift_rot0_sr_op__insn[31:0] + attribute \src "libresoc.v:176820.3-176857.6" + wire width 7 $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12351 + attribute \src "libresoc.v:176576.3-176577.79" + wire width 7 $0\alu_shift_rot0_sr_op__insn_type[6:0] + attribute \src "libresoc.v:176820.3-176857.6" + wire $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12352 + attribute \src "libresoc.v:176594.3-176595.79" + wire $0\alu_shift_rot0_sr_op__invert_in[0:0] + attribute \src "libresoc.v:176820.3-176857.6" + wire $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12353 + attribute \src "libresoc.v:176604.3-176605.77" + wire $0\alu_shift_rot0_sr_op__is_32bit[0:0] + attribute \src "libresoc.v:176820.3-176857.6" + wire $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12354 + attribute \src "libresoc.v:176606.3-176607.79" + wire $0\alu_shift_rot0_sr_op__is_signed[0:0] + attribute \src "libresoc.v:176820.3-176857.6" + wire $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12355 + attribute \src "libresoc.v:176588.3-176589.73" + wire $0\alu_shift_rot0_sr_op__oe__oe[0:0] + attribute \src "libresoc.v:176820.3-176857.6" + wire $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12356 + attribute \src "libresoc.v:176590.3-176591.73" + wire $0\alu_shift_rot0_sr_op__oe__ok[0:0] + attribute \src "libresoc.v:176820.3-176857.6" + wire $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12357 + attribute \src "libresoc.v:176598.3-176599.85" + wire $0\alu_shift_rot0_sr_op__output_carry[0:0] + attribute \src "libresoc.v:176820.3-176857.6" + wire $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12358 + attribute \src "libresoc.v:176602.3-176603.79" + wire $0\alu_shift_rot0_sr_op__output_cr[0:0] + attribute \src "libresoc.v:176820.3-176857.6" + wire $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12359 + attribute \src "libresoc.v:176586.3-176587.73" + wire $0\alu_shift_rot0_sr_op__rc__ok[0:0] + attribute \src "libresoc.v:176820.3-176857.6" + wire $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12360 + attribute \src "libresoc.v:176584.3-176585.73" + wire $0\alu_shift_rot0_sr_op__rc__rc[0:0] + attribute \src "libresoc.v:176820.3-176857.6" + wire $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12361 + attribute \src "libresoc.v:176592.3-176593.79" + wire $0\alu_shift_rot0_sr_op__write_cr0[0:0] + attribute \src "libresoc.v:176974.3-176982.6" + wire $0\alui_l_r_alui$next[0:0]$12425 + attribute \src "libresoc.v:176552.3-176553.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:176858.3-176879.6" + wire width 64 $0\data_r0__o$next[63:0]$12386 + attribute \src "libresoc.v:176572.3-176573.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "libresoc.v:176858.3-176879.6" + wire $0\data_r0__o_ok$next[0:0]$12387 + attribute \src "libresoc.v:176574.3-176575.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "libresoc.v:176880.3-176901.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$12394 + attribute \src "libresoc.v:176568.3-176569.43" + wire width 4 $0\data_r1__cr_a[3:0] + attribute \src "libresoc.v:176880.3-176901.6" + wire $0\data_r1__cr_a_ok$next[0:0]$12395 + attribute \src "libresoc.v:176570.3-176571.49" + wire $0\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:176902.3-176923.6" + wire width 2 $0\data_r2__xer_ca$next[1:0]$12402 + attribute \src "libresoc.v:176564.3-176565.47" + wire width 2 $0\data_r2__xer_ca[1:0] + attribute \src "libresoc.v:176902.3-176923.6" + wire $0\data_r2__xer_ca_ok$next[0:0]$12403 + attribute \src "libresoc.v:176566.3-176567.53" + wire $0\data_r2__xer_ca_ok[0:0] + attribute \src "libresoc.v:176992.3-177001.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:177002.3-177011.6" + wire width 4 $0\dest2_o[3:0] + attribute \src "libresoc.v:177012.3-177021.6" + wire width 2 $0\dest3_o[1:0] + attribute \src "libresoc.v:175863.7-175863.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:176775.3-176783.6" + wire $0\opc_l_r_opc$next[0:0]$12330 + attribute \src "libresoc.v:176618.3-176619.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:176766.3-176774.6" + wire $0\opc_l_s_opc$next[0:0]$12327 + attribute \src "libresoc.v:176620.3-176621.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:177022.3-177030.6" + wire width 3 $0\prev_wr_go$next[2:0]$12434 + attribute \src "libresoc.v:176630.3-176631.37" + wire width 3 $0\prev_wr_go[2:0] + attribute \src "libresoc.v:176720.3-176729.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:176811.3-176819.6" + wire width 3 $0\req_l_r_req$next[2:0]$12342 + attribute \src "libresoc.v:176610.3-176611.39" + wire width 3 $0\req_l_r_req[2:0] + attribute \src "libresoc.v:176802.3-176810.6" + wire width 3 $0\req_l_s_req$next[2:0]$12339 + attribute \src "libresoc.v:176612.3-176613.39" + wire width 3 $0\req_l_s_req[2:0] + attribute \src "libresoc.v:176739.3-176747.6" + wire $0\rok_l_r_rdok$next[0:0]$12318 + attribute \src "libresoc.v:176626.3-176627.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:176730.3-176738.6" + wire $0\rok_l_s_rdok$next[0:0]$12315 + attribute \src "libresoc.v:176628.3-176629.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:176757.3-176765.6" + wire $0\rst_l_r_rst$next[0:0]$12324 + attribute \src "libresoc.v:176622.3-176623.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:176748.3-176756.6" + wire $0\rst_l_s_rst$next[0:0]$12321 + attribute \src "libresoc.v:176624.3-176625.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:176793.3-176801.6" + wire width 5 $0\src_l_r_src$next[4:0]$12336 + attribute \src "libresoc.v:176614.3-176615.39" + wire width 5 $0\src_l_r_src[4:0] + attribute \src "libresoc.v:176784.3-176792.6" + wire width 5 $0\src_l_s_src$next[4:0]$12333 + attribute \src "libresoc.v:176616.3-176617.39" + wire width 5 $0\src_l_s_src[4:0] + attribute \src "libresoc.v:176924.3-176933.6" + wire width 64 $0\src_r0$next[63:0]$12410 + attribute \src "libresoc.v:176562.3-176563.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:176934.3-176943.6" + wire width 64 $0\src_r1$next[63:0]$12413 + attribute \src "libresoc.v:176560.3-176561.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:176944.3-176953.6" + wire width 64 $0\src_r2$next[63:0]$12416 + attribute \src "libresoc.v:176558.3-176559.29" + wire width 64 $0\src_r2[63:0] + attribute \src "libresoc.v:176954.3-176963.6" + wire $0\src_r3$next[0:0]$12419 + attribute \src "libresoc.v:176556.3-176557.29" + wire $0\src_r3[0:0] + attribute \src "libresoc.v:176964.3-176973.6" + wire width 2 $0\src_r4$next[1:0]$12422 + attribute \src "libresoc.v:176554.3-176555.29" + wire width 2 $0\src_r4[1:0] + attribute \src "libresoc.v:175985.7-175985.24" + wire $1\all_rd_dly[0:0] + attribute \src "libresoc.v:175995.7-175995.26" + wire $1\alu_done_dly[0:0] + attribute \src "libresoc.v:176983.3-176991.6" + wire $1\alu_l_r_alu$next[0:0]$12429 + attribute \src "libresoc.v:176003.7-176003.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "libresoc.v:176820.3-176857.6" + wire width 12 $1\alu_shift_rot0_sr_op__fn_unit$next[11:0]$12362 + attribute \src "libresoc.v:176044.14-176044.53" + wire width 12 $1\alu_shift_rot0_sr_op__fn_unit[11:0] + attribute \src "libresoc.v:176820.3-176857.6" + wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12363 + attribute \src "libresoc.v:176048.14-176048.73" + wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data[63:0] + attribute \src "libresoc.v:176820.3-176857.6" + wire $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12364 + attribute \src "libresoc.v:176052.7-176052.48" + wire $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] + attribute \src "libresoc.v:176820.3-176857.6" + wire width 2 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12365 + attribute \src "libresoc.v:176060.13-176060.53" + wire width 2 $1\alu_shift_rot0_sr_op__input_carry[1:0] + attribute \src "libresoc.v:176820.3-176857.6" + wire $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12366 + attribute \src "libresoc.v:176064.7-176064.44" + wire $1\alu_shift_rot0_sr_op__input_cr[0:0] + attribute \src "libresoc.v:176820.3-176857.6" + wire width 32 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12367 + attribute \src "libresoc.v:176068.14-176068.48" + wire width 32 $1\alu_shift_rot0_sr_op__insn[31:0] + attribute \src "libresoc.v:176820.3-176857.6" + wire width 7 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12368 + attribute \src "libresoc.v:176146.13-176146.52" + wire width 7 $1\alu_shift_rot0_sr_op__insn_type[6:0] + attribute \src "libresoc.v:176820.3-176857.6" + wire $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12369 + attribute \src "libresoc.v:176150.7-176150.45" + wire $1\alu_shift_rot0_sr_op__invert_in[0:0] + attribute \src "libresoc.v:176820.3-176857.6" + wire $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12370 + attribute \src "libresoc.v:176154.7-176154.44" + wire $1\alu_shift_rot0_sr_op__is_32bit[0:0] + attribute \src "libresoc.v:176820.3-176857.6" + wire $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12371 + attribute \src "libresoc.v:176158.7-176158.45" + wire $1\alu_shift_rot0_sr_op__is_signed[0:0] + attribute \src "libresoc.v:176820.3-176857.6" + wire $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12372 + attribute \src "libresoc.v:176162.7-176162.42" + wire $1\alu_shift_rot0_sr_op__oe__oe[0:0] + attribute \src "libresoc.v:176820.3-176857.6" + wire $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12373 + attribute \src "libresoc.v:176166.7-176166.42" + wire $1\alu_shift_rot0_sr_op__oe__ok[0:0] + attribute \src "libresoc.v:176820.3-176857.6" + wire $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12374 + attribute \src "libresoc.v:176170.7-176170.48" + wire $1\alu_shift_rot0_sr_op__output_carry[0:0] + attribute \src "libresoc.v:176820.3-176857.6" + wire $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12375 + attribute \src "libresoc.v:176174.7-176174.45" + wire $1\alu_shift_rot0_sr_op__output_cr[0:0] + attribute \src "libresoc.v:176820.3-176857.6" + wire $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12376 + attribute \src "libresoc.v:176178.7-176178.42" + wire $1\alu_shift_rot0_sr_op__rc__ok[0:0] + attribute \src "libresoc.v:176820.3-176857.6" + wire $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12377 + attribute \src "libresoc.v:176182.7-176182.42" + wire $1\alu_shift_rot0_sr_op__rc__rc[0:0] + attribute \src "libresoc.v:176820.3-176857.6" + wire $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12378 + attribute \src "libresoc.v:176186.7-176186.45" + wire $1\alu_shift_rot0_sr_op__write_cr0[0:0] + attribute \src "libresoc.v:176974.3-176982.6" + wire $1\alui_l_r_alui$next[0:0]$12426 + attribute \src "libresoc.v:176198.7-176198.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "libresoc.v:176858.3-176879.6" + wire width 64 $1\data_r0__o$next[63:0]$12388 + attribute \src "libresoc.v:176232.14-176232.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "libresoc.v:176858.3-176879.6" + wire $1\data_r0__o_ok$next[0:0]$12389 + attribute \src "libresoc.v:176236.7-176236.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "libresoc.v:176880.3-176901.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$12396 + attribute \src "libresoc.v:176240.13-176240.33" + wire width 4 $1\data_r1__cr_a[3:0] + attribute \src "libresoc.v:176880.3-176901.6" + wire $1\data_r1__cr_a_ok$next[0:0]$12397 + attribute \src "libresoc.v:176244.7-176244.30" + wire $1\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:176902.3-176923.6" + wire width 2 $1\data_r2__xer_ca$next[1:0]$12404 + attribute \src "libresoc.v:176248.13-176248.35" + wire width 2 $1\data_r2__xer_ca[1:0] + attribute \src "libresoc.v:176902.3-176923.6" + wire $1\data_r2__xer_ca_ok$next[0:0]$12405 + attribute \src "libresoc.v:176252.7-176252.32" + wire $1\data_r2__xer_ca_ok[0:0] + attribute \src "libresoc.v:176992.3-177001.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "libresoc.v:177002.3-177011.6" + wire width 4 $1\dest2_o[3:0] + attribute \src "libresoc.v:177012.3-177021.6" + wire width 2 $1\dest3_o[1:0] + attribute \src "libresoc.v:176775.3-176783.6" + wire $1\opc_l_r_opc$next[0:0]$12331 + attribute \src "libresoc.v:176269.7-176269.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "libresoc.v:176766.3-176774.6" + wire $1\opc_l_s_opc$next[0:0]$12328 + attribute \src "libresoc.v:176273.7-176273.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "libresoc.v:177022.3-177030.6" + wire width 3 $1\prev_wr_go$next[2:0]$12435 + attribute \src "libresoc.v:176402.13-176402.30" + wire width 3 $1\prev_wr_go[2:0] + attribute \src "libresoc.v:176720.3-176729.6" + wire $1\req_done[0:0] + attribute \src "libresoc.v:176811.3-176819.6" + wire width 3 $1\req_l_r_req$next[2:0]$12343 + attribute \src "libresoc.v:176410.13-176410.31" + wire width 3 $1\req_l_r_req[2:0] + attribute \src "libresoc.v:176802.3-176810.6" + wire width 3 $1\req_l_s_req$next[2:0]$12340 + attribute \src "libresoc.v:176414.13-176414.31" + wire width 3 $1\req_l_s_req[2:0] + attribute \src "libresoc.v:176739.3-176747.6" + wire $1\rok_l_r_rdok$next[0:0]$12319 + attribute \src "libresoc.v:176426.7-176426.26" + wire $1\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:176730.3-176738.6" + wire $1\rok_l_s_rdok$next[0:0]$12316 + attribute \src "libresoc.v:176430.7-176430.26" + wire $1\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:176757.3-176765.6" + wire $1\rst_l_r_rst$next[0:0]$12325 + attribute \src "libresoc.v:176434.7-176434.25" + wire $1\rst_l_r_rst[0:0] + attribute \src "libresoc.v:176748.3-176756.6" + wire $1\rst_l_s_rst$next[0:0]$12322 + attribute \src "libresoc.v:176438.7-176438.25" + wire $1\rst_l_s_rst[0:0] + attribute \src "libresoc.v:176793.3-176801.6" + wire width 5 $1\src_l_r_src$next[4:0]$12337 + attribute \src "libresoc.v:176456.13-176456.32" + wire width 5 $1\src_l_r_src[4:0] + attribute \src "libresoc.v:176784.3-176792.6" + wire width 5 $1\src_l_s_src$next[4:0]$12334 + attribute \src "libresoc.v:176460.13-176460.32" + wire width 5 $1\src_l_s_src[4:0] + attribute \src "libresoc.v:176924.3-176933.6" + wire width 64 $1\src_r0$next[63:0]$12411 + attribute \src "libresoc.v:176466.14-176466.43" + wire width 64 $1\src_r0[63:0] + attribute \src "libresoc.v:176934.3-176943.6" + wire width 64 $1\src_r1$next[63:0]$12414 + attribute \src "libresoc.v:176470.14-176470.43" + wire width 64 $1\src_r1[63:0] + attribute \src "libresoc.v:176944.3-176953.6" + wire width 64 $1\src_r2$next[63:0]$12417 + attribute \src "libresoc.v:176474.14-176474.43" + wire width 64 $1\src_r2[63:0] + attribute \src "libresoc.v:176954.3-176963.6" + wire $1\src_r3$next[0:0]$12420 + attribute \src "libresoc.v:176478.7-176478.20" + wire $1\src_r3[0:0] + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_shift_rot0_sr_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_shift_rot0_sr_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__input_cr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_shift_rot0_sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_shift_rot0_sr_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_shift_rot0_sr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_shift_rot0_sr_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__output_cr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \alu_shift_rot0_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \alu_shift_rot0_xer_ca$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \alu_shift_rot0_xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \alui_l_s_alui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 37 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 33 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 20 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 19 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 input 23 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 output 22 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 5 input 21 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 31 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 30 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 3 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ca$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 32 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 34 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 36 \dest3_o + attribute \src "libresoc.v:175863.7-175863.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 29 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \opc_l_q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 3 \oper_i_alu_shift_rot0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 4 \oper_i_alu_shift_rot0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \oper_i_alu_shift_rot0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 12 \oper_i_alu_shift_rot0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \oper_i_alu_shift_rot0__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \oper_i_alu_shift_rot0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute 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\A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $eq$libresoc.v:176521$12241_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$libresoc.v:176491$12211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_rdmaskn_i + connect \Y $not$libresoc.v:176491$12211_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:176502$12222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $not$libresoc.v:176502$12222_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:176504$12224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $not$libresoc.v:176504$12224_Y + end + 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+ parameter \Y_WIDTH 5 + connect \A \cu_rd__rel_o + connect \Y $not$libresoc.v:176527$12247_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$libresoc.v:176548$12268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_shift_rot0_sr_op__imm_data__ok + connect \Y $not$libresoc.v:176548$12268_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$libresoc.v:176515$12235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$32 + connect \B \$34 + connect \Y $or$libresoc.v:176515$12235_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$libresoc.v:176525$12245 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:176525$12245_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$libresoc.v:176526$12246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:176526$12246_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$libresoc.v:176528$12248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:176528$12248_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$libresoc.v:176529$12249 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:176529$12249_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:176532$12252 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$libresoc.v:176532$12252_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:176538$12258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$5 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:176538$12258_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:176544$12264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \$7 + connect \Y $reduce_and$libresoc.v:176544$12264_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:176509$12229 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \Y $reduce_or$libresoc.v:176509$12229_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:176513$12233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:176513$12233_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:176514$12234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:176514$12234_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:176536$12256 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_shift_rot0_sr_op__imm_data__ok + connect \Y $ternary$libresoc.v:176536$12256_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:176537$12257 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_shift_rot0_sr_op__imm_data__data + connect \S \alu_shift_rot0_sr_op__imm_data__ok + connect \Y $ternary$libresoc.v:176537$12257_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:176539$12259 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $ternary$libresoc.v:176539$12259_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:176540$12260 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $ternary$libresoc.v:176540$12260_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:176541$12261 + parameter \WIDTH 64 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:176541$12261_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:176542$12262 + parameter \WIDTH 1 + connect \A \src_r3 + connect \B \src4_i + connect \S \src_l_q_src [3] + connect \Y $ternary$libresoc.v:176542$12262_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:176543$12263 + parameter \WIDTH 2 + connect \A \src_r4 + connect \B \src5_i + connect \S \src_l_q_src [4] + connect \Y $ternary$libresoc.v:176543$12263_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:176636.15-176642.4" + cell \alu_l$125 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:176643.18-176678.4" + cell \alu_shift_rot0 \alu_shift_rot0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \alu_shift_rot0_cr_a + connect \cr_a_ok \cr_a_ok + connect \n_ready_i \alu_shift_rot0_n_ready_i + connect \n_valid_o \alu_shift_rot0_n_valid_o + connect \o \alu_shift_rot0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_shift_rot0_p_ready_o + connect \p_valid_i \alu_shift_rot0_p_valid_i + connect \ra \alu_shift_rot0_ra + connect \rb \alu_shift_rot0_rb + connect \rc \alu_shift_rot0_rc + connect \sr_op__fn_unit \alu_shift_rot0_sr_op__fn_unit + connect \sr_op__imm_data__data \alu_shift_rot0_sr_op__imm_data__data + connect \sr_op__imm_data__ok \alu_shift_rot0_sr_op__imm_data__ok + connect \sr_op__input_carry \alu_shift_rot0_sr_op__input_carry + connect \sr_op__input_cr \alu_shift_rot0_sr_op__input_cr + connect \sr_op__insn \alu_shift_rot0_sr_op__insn + connect \sr_op__insn_type \alu_shift_rot0_sr_op__insn_type + connect \sr_op__invert_in \alu_shift_rot0_sr_op__invert_in + connect \sr_op__is_32bit \alu_shift_rot0_sr_op__is_32bit + connect \sr_op__is_signed \alu_shift_rot0_sr_op__is_signed + connect \sr_op__oe__oe \alu_shift_rot0_sr_op__oe__oe + connect \sr_op__oe__ok \alu_shift_rot0_sr_op__oe__ok + connect \sr_op__output_carry \alu_shift_rot0_sr_op__output_carry + connect \sr_op__output_cr \alu_shift_rot0_sr_op__output_cr + connect \sr_op__rc__ok \alu_shift_rot0_sr_op__rc__ok + connect \sr_op__rc__rc \alu_shift_rot0_sr_op__rc__rc + connect \sr_op__write_cr0 \alu_shift_rot0_sr_op__write_cr0 + connect \xer_ca \alu_shift_rot0_xer_ca + connect \xer_ca$1 \alu_shift_rot0_xer_ca$1 + connect \xer_ca_ok \xer_ca_ok + connect \xer_so \alu_shift_rot0_xer_so + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:176679.16-176685.4" + cell \alui_l$124 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:176686.15-176692.4" + cell \opc_l$120 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:176693.15-176699.4" + cell \req_l$121 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:176700.15-176706.4" + cell \rok_l$123 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:176707.15-176712.4" + cell \rst_l$122 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:176713.15-176719.4" + cell \src_l$119 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "libresoc.v:175863.7-175863.20" + process $proc$libresoc.v:175863$12436 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:175985.7-175985.24" + process $proc$libresoc.v:175985$12437 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "libresoc.v:175995.7-175995.26" + process $proc$libresoc.v:175995$12438 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "libresoc.v:176003.7-176003.25" + process $proc$libresoc.v:176003$12439 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:176044.14-176044.53" + process $proc$libresoc.v:176044$12440 + assign { } { } + assign $1\alu_shift_rot0_sr_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \alu_shift_rot0_sr_op__fn_unit $1\alu_shift_rot0_sr_op__fn_unit[11:0] + end + attribute \src "libresoc.v:176048.14-176048.73" + process $proc$libresoc.v:176048$12441 + assign { } { } + assign $1\alu_shift_rot0_sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_shift_rot0_sr_op__imm_data__data $1\alu_shift_rot0_sr_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:176052.7-176052.48" + process $proc$libresoc.v:176052$12442 + assign { } { } + assign $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__imm_data__ok $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:176060.13-176060.53" + process $proc$libresoc.v:176060$12443 + assign { } { } + assign $1\alu_shift_rot0_sr_op__input_carry[1:0] 2'00 + sync always + sync init + update \alu_shift_rot0_sr_op__input_carry $1\alu_shift_rot0_sr_op__input_carry[1:0] + end + attribute \src "libresoc.v:176064.7-176064.44" + process $proc$libresoc.v:176064$12444 + assign { } { } + assign $1\alu_shift_rot0_sr_op__input_cr[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__input_cr $1\alu_shift_rot0_sr_op__input_cr[0:0] + end + attribute \src "libresoc.v:176068.14-176068.48" + process $proc$libresoc.v:176068$12445 + assign { } { } + assign $1\alu_shift_rot0_sr_op__insn[31:0] 0 + sync always + sync init + update \alu_shift_rot0_sr_op__insn $1\alu_shift_rot0_sr_op__insn[31:0] + end + attribute \src "libresoc.v:176146.13-176146.52" + process $proc$libresoc.v:176146$12446 + assign { } { } + assign $1\alu_shift_rot0_sr_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_shift_rot0_sr_op__insn_type $1\alu_shift_rot0_sr_op__insn_type[6:0] + end + attribute \src "libresoc.v:176150.7-176150.45" + process $proc$libresoc.v:176150$12447 + assign { } { } + assign $1\alu_shift_rot0_sr_op__invert_in[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__invert_in $1\alu_shift_rot0_sr_op__invert_in[0:0] + end + attribute \src "libresoc.v:176154.7-176154.44" + process $proc$libresoc.v:176154$12448 + assign { } { } + assign $1\alu_shift_rot0_sr_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__is_32bit $1\alu_shift_rot0_sr_op__is_32bit[0:0] + end + attribute \src "libresoc.v:176158.7-176158.45" + process $proc$libresoc.v:176158$12449 + assign { } { } + assign $1\alu_shift_rot0_sr_op__is_signed[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__is_signed $1\alu_shift_rot0_sr_op__is_signed[0:0] + end + attribute \src "libresoc.v:176162.7-176162.42" + process $proc$libresoc.v:176162$12450 + assign { } { } + assign $1\alu_shift_rot0_sr_op__oe__oe[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__oe__oe $1\alu_shift_rot0_sr_op__oe__oe[0:0] + end + attribute \src "libresoc.v:176166.7-176166.42" + process $proc$libresoc.v:176166$12451 + assign { } { } + assign $1\alu_shift_rot0_sr_op__oe__ok[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__oe__ok $1\alu_shift_rot0_sr_op__oe__ok[0:0] + end + attribute \src "libresoc.v:176170.7-176170.48" + process $proc$libresoc.v:176170$12452 + assign { } { } + assign $1\alu_shift_rot0_sr_op__output_carry[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__output_carry $1\alu_shift_rot0_sr_op__output_carry[0:0] + end + attribute \src "libresoc.v:176174.7-176174.45" + process $proc$libresoc.v:176174$12453 + assign { } { } + assign $1\alu_shift_rot0_sr_op__output_cr[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__output_cr $1\alu_shift_rot0_sr_op__output_cr[0:0] + end + attribute \src "libresoc.v:176178.7-176178.42" + process $proc$libresoc.v:176178$12454 + assign { } { } + assign $1\alu_shift_rot0_sr_op__rc__ok[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__rc__ok $1\alu_shift_rot0_sr_op__rc__ok[0:0] + end + attribute \src "libresoc.v:176182.7-176182.42" + process $proc$libresoc.v:176182$12455 + assign { } { } + assign $1\alu_shift_rot0_sr_op__rc__rc[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__rc__rc $1\alu_shift_rot0_sr_op__rc__rc[0:0] + end + attribute \src "libresoc.v:176186.7-176186.45" + process $proc$libresoc.v:176186$12456 + assign { } { } + assign $1\alu_shift_rot0_sr_op__write_cr0[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__write_cr0 $1\alu_shift_rot0_sr_op__write_cr0[0:0] + end + attribute \src "libresoc.v:176198.7-176198.27" + process $proc$libresoc.v:176198$12457 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:176232.14-176232.47" + process $proc$libresoc.v:176232$12458 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "libresoc.v:176236.7-176236.27" + process $proc$libresoc.v:176236$12459 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:176240.13-176240.33" + process $proc$libresoc.v:176240$12460 + assign { } { } + assign $1\data_r1__cr_a[3:0] 4'0000 + sync always + sync init + update \data_r1__cr_a $1\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:176244.7-176244.30" + process $proc$libresoc.v:176244$12461 + assign { } { } + assign $1\data_r1__cr_a_ok[0:0] 1'0 + sync always + sync init + update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:176248.13-176248.35" + process $proc$libresoc.v:176248$12462 + assign { } { } + assign $1\data_r2__xer_ca[1:0] 2'00 + sync always + sync init + update \data_r2__xer_ca $1\data_r2__xer_ca[1:0] + end + attribute \src "libresoc.v:176252.7-176252.32" + process $proc$libresoc.v:176252$12463 + assign { } { } + assign $1\data_r2__xer_ca_ok[0:0] 1'0 + sync always + sync init + update \data_r2__xer_ca_ok $1\data_r2__xer_ca_ok[0:0] + end + attribute \src "libresoc.v:176269.7-176269.25" + process $proc$libresoc.v:176269$12464 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:176273.7-176273.25" + process $proc$libresoc.v:176273$12465 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:176402.13-176402.30" + process $proc$libresoc.v:176402$12466 + assign { } { } + assign $1\prev_wr_go[2:0] 3'000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[2:0] + end + attribute \src "libresoc.v:176410.13-176410.31" + process $proc$libresoc.v:176410$12467 + assign { } { } + assign $1\req_l_r_req[2:0] 3'111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[2:0] + end + attribute \src "libresoc.v:176414.13-176414.31" + process $proc$libresoc.v:176414$12468 + assign { } { } + assign $1\req_l_s_req[2:0] 3'000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[2:0] + end + attribute \src "libresoc.v:176426.7-176426.26" + process $proc$libresoc.v:176426$12469 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:176430.7-176430.26" + process $proc$libresoc.v:176430$12470 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:176434.7-176434.25" + process $proc$libresoc.v:176434$12471 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:176438.7-176438.25" + process $proc$libresoc.v:176438$12472 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:176456.13-176456.32" + process $proc$libresoc.v:176456$12473 + assign { } { } + assign $1\src_l_r_src[4:0] 5'11111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[4:0] + end + attribute \src "libresoc.v:176460.13-176460.32" + process $proc$libresoc.v:176460$12474 + assign { } { } + assign $1\src_l_s_src[4:0] 5'00000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[4:0] + end + attribute \src "libresoc.v:176466.14-176466.43" + process $proc$libresoc.v:176466$12475 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:176470.14-176470.43" + process $proc$libresoc.v:176470$12476 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:176474.14-176474.43" + process $proc$libresoc.v:176474$12477 + assign { } { } + assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r2 $1\src_r2[63:0] + end + attribute \src "libresoc.v:176478.7-176478.20" + process $proc$libresoc.v:176478$12478 + assign { } { } + assign $1\src_r3[0:0] 1'0 + sync always + sync init + update \src_r3 $1\src_r3[0:0] + end + attribute \src "libresoc.v:176482.13-176482.26" + process $proc$libresoc.v:176482$12479 + assign { } { } + assign $1\src_r4[1:0] 2'00 + sync always + sync init + update \src_r4 $1\src_r4[1:0] + end + attribute \src "libresoc.v:176550.3-176551.39" + process $proc$libresoc.v:176550$12270 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:176552.3-176553.43" + process $proc$libresoc.v:176552$12271 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:176554.3-176555.29" + process $proc$libresoc.v:176554$12272 + assign { } { } + assign $0\src_r4[1:0] \src_r4$next + sync posedge \coresync_clk + update \src_r4 $0\src_r4[1:0] + end + attribute \src "libresoc.v:176556.3-176557.29" + process $proc$libresoc.v:176556$12273 + assign { } { } + assign $0\src_r3[0:0] \src_r3$next + sync posedge \coresync_clk + update \src_r3 $0\src_r3[0:0] + end + attribute \src "libresoc.v:176558.3-176559.29" + process $proc$libresoc.v:176558$12274 + assign { } { } + assign $0\src_r2[63:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[63:0] + end + attribute \src "libresoc.v:176560.3-176561.29" + process $proc$libresoc.v:176560$12275 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:176562.3-176563.29" + process $proc$libresoc.v:176562$12276 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:176564.3-176565.47" + process $proc$libresoc.v:176564$12277 + assign { } { } + assign $0\data_r2__xer_ca[1:0] \data_r2__xer_ca$next + sync posedge \coresync_clk + update \data_r2__xer_ca $0\data_r2__xer_ca[1:0] + end + attribute \src "libresoc.v:176566.3-176567.53" + process $proc$libresoc.v:176566$12278 + assign { } { } + assign $0\data_r2__xer_ca_ok[0:0] \data_r2__xer_ca_ok$next + sync posedge \coresync_clk + update \data_r2__xer_ca_ok $0\data_r2__xer_ca_ok[0:0] + end + attribute \src "libresoc.v:176568.3-176569.43" + process $proc$libresoc.v:176568$12279 + assign { } { } + assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next + sync posedge \coresync_clk + update \data_r1__cr_a $0\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:176570.3-176571.49" + process $proc$libresoc.v:176570$12280 + assign { } { } + assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next + sync posedge \coresync_clk + update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:176572.3-176573.37" + process $proc$libresoc.v:176572$12281 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "libresoc.v:176574.3-176575.43" + process $proc$libresoc.v:176574$12282 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:176576.3-176577.79" + process $proc$libresoc.v:176576$12283 + assign { } { } + assign $0\alu_shift_rot0_sr_op__insn_type[6:0] \alu_shift_rot0_sr_op__insn_type$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__insn_type $0\alu_shift_rot0_sr_op__insn_type[6:0] + end + attribute \src "libresoc.v:176578.3-176579.75" + process $proc$libresoc.v:176578$12284 + assign { } { } + assign $0\alu_shift_rot0_sr_op__fn_unit[11:0] \alu_shift_rot0_sr_op__fn_unit$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__fn_unit $0\alu_shift_rot0_sr_op__fn_unit[11:0] + end + attribute \src "libresoc.v:176580.3-176581.89" + process $proc$libresoc.v:176580$12285 + assign { } { } + assign $0\alu_shift_rot0_sr_op__imm_data__data[63:0] \alu_shift_rot0_sr_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__imm_data__data $0\alu_shift_rot0_sr_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:176582.3-176583.85" + process $proc$libresoc.v:176582$12286 + assign { } { } + assign $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] \alu_shift_rot0_sr_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__imm_data__ok $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:176584.3-176585.73" + process $proc$libresoc.v:176584$12287 + assign { } { } + assign $0\alu_shift_rot0_sr_op__rc__rc[0:0] \alu_shift_rot0_sr_op__rc__rc$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__rc__rc $0\alu_shift_rot0_sr_op__rc__rc[0:0] + end + attribute \src "libresoc.v:176586.3-176587.73" + process $proc$libresoc.v:176586$12288 + assign { } { } + assign $0\alu_shift_rot0_sr_op__rc__ok[0:0] \alu_shift_rot0_sr_op__rc__ok$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__rc__ok $0\alu_shift_rot0_sr_op__rc__ok[0:0] + end + attribute \src "libresoc.v:176588.3-176589.73" + process $proc$libresoc.v:176588$12289 + assign { } { } + assign $0\alu_shift_rot0_sr_op__oe__oe[0:0] \alu_shift_rot0_sr_op__oe__oe$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__oe__oe $0\alu_shift_rot0_sr_op__oe__oe[0:0] + end + attribute \src "libresoc.v:176590.3-176591.73" + process $proc$libresoc.v:176590$12290 + assign { } { } + assign $0\alu_shift_rot0_sr_op__oe__ok[0:0] \alu_shift_rot0_sr_op__oe__ok$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__oe__ok $0\alu_shift_rot0_sr_op__oe__ok[0:0] + end + attribute \src "libresoc.v:176592.3-176593.79" + process $proc$libresoc.v:176592$12291 + assign { } { } + assign $0\alu_shift_rot0_sr_op__write_cr0[0:0] \alu_shift_rot0_sr_op__write_cr0$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__write_cr0 $0\alu_shift_rot0_sr_op__write_cr0[0:0] + end + attribute \src "libresoc.v:176594.3-176595.79" + process $proc$libresoc.v:176594$12292 + assign { } { } + assign $0\alu_shift_rot0_sr_op__invert_in[0:0] \alu_shift_rot0_sr_op__invert_in$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__invert_in $0\alu_shift_rot0_sr_op__invert_in[0:0] + end + attribute \src "libresoc.v:176596.3-176597.83" + process $proc$libresoc.v:176596$12293 + assign { } { } + assign $0\alu_shift_rot0_sr_op__input_carry[1:0] \alu_shift_rot0_sr_op__input_carry$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__input_carry $0\alu_shift_rot0_sr_op__input_carry[1:0] + end + attribute \src "libresoc.v:176598.3-176599.85" + process $proc$libresoc.v:176598$12294 + assign { } { } + assign $0\alu_shift_rot0_sr_op__output_carry[0:0] \alu_shift_rot0_sr_op__output_carry$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__output_carry $0\alu_shift_rot0_sr_op__output_carry[0:0] + end + attribute \src "libresoc.v:176600.3-176601.77" + process $proc$libresoc.v:176600$12295 + assign { } { } + assign $0\alu_shift_rot0_sr_op__input_cr[0:0] \alu_shift_rot0_sr_op__input_cr$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__input_cr $0\alu_shift_rot0_sr_op__input_cr[0:0] + end + attribute \src "libresoc.v:176602.3-176603.79" + process $proc$libresoc.v:176602$12296 + assign { } { } + assign $0\alu_shift_rot0_sr_op__output_cr[0:0] \alu_shift_rot0_sr_op__output_cr$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__output_cr $0\alu_shift_rot0_sr_op__output_cr[0:0] + end + attribute \src "libresoc.v:176604.3-176605.77" + process $proc$libresoc.v:176604$12297 + assign { } { } + assign $0\alu_shift_rot0_sr_op__is_32bit[0:0] \alu_shift_rot0_sr_op__is_32bit$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__is_32bit $0\alu_shift_rot0_sr_op__is_32bit[0:0] + end + attribute \src "libresoc.v:176606.3-176607.79" + process $proc$libresoc.v:176606$12298 + assign { } { } + assign $0\alu_shift_rot0_sr_op__is_signed[0:0] \alu_shift_rot0_sr_op__is_signed$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__is_signed $0\alu_shift_rot0_sr_op__is_signed[0:0] + end + attribute \src "libresoc.v:176608.3-176609.69" + process $proc$libresoc.v:176608$12299 + assign { } { } + assign $0\alu_shift_rot0_sr_op__insn[31:0] \alu_shift_rot0_sr_op__insn$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__insn $0\alu_shift_rot0_sr_op__insn[31:0] + end + attribute \src "libresoc.v:176610.3-176611.39" + process $proc$libresoc.v:176610$12300 + assign { } { } + assign $0\req_l_r_req[2:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[2:0] + end + attribute \src "libresoc.v:176612.3-176613.39" + process $proc$libresoc.v:176612$12301 + assign { } { } + assign $0\req_l_s_req[2:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[2:0] + end + attribute \src "libresoc.v:176614.3-176615.39" + process $proc$libresoc.v:176614$12302 + assign { } { } + assign $0\src_l_r_src[4:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[4:0] + end + attribute \src "libresoc.v:176616.3-176617.39" + process $proc$libresoc.v:176616$12303 + assign { } { } + assign $0\src_l_s_src[4:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[4:0] + end + attribute \src "libresoc.v:176618.3-176619.39" + process $proc$libresoc.v:176618$12304 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:176620.3-176621.39" + process $proc$libresoc.v:176620$12305 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:176622.3-176623.39" + process $proc$libresoc.v:176622$12306 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:176624.3-176625.39" + process $proc$libresoc.v:176624$12307 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:176626.3-176627.41" + process $proc$libresoc.v:176626$12308 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:176628.3-176629.41" + process $proc$libresoc.v:176628$12309 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:176630.3-176631.37" + process $proc$libresoc.v:176630$12310 + assign { } { } + assign $0\prev_wr_go[2:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[2:0] + end + attribute \src "libresoc.v:176632.3-176633.46" + process $proc$libresoc.v:176632$12311 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_shift_rot0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "libresoc.v:176634.3-176635.25" + process $proc$libresoc.v:176634$12312 + assign { } { } + assign $0\all_rd_dly[0:0] \$10 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "libresoc.v:176720.3-176729.6" + process $proc$libresoc.v:176720$12313 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:176721.5-176721.29" + switch \initial + attribute \src "libresoc.v:176721.9-176721.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$54 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$46 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "libresoc.v:176730.3-176738.6" + process $proc$libresoc.v:176730$12314 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$12315 $1\rok_l_s_rdok$next[0:0]$12316 + attribute \src "libresoc.v:176731.5-176731.29" + switch \initial + attribute \src "libresoc.v:176731.9-176731.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$12316 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$12316 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12315 + end + attribute \src "libresoc.v:176739.3-176747.6" + process $proc$libresoc.v:176739$12317 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$12318 $1\rok_l_r_rdok$next[0:0]$12319 + attribute \src "libresoc.v:176740.5-176740.29" + switch \initial + attribute \src "libresoc.v:176740.9-176740.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$12319 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$12319 \$64 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12318 + end + attribute \src "libresoc.v:176748.3-176756.6" + process $proc$libresoc.v:176748$12320 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$12321 $1\rst_l_s_rst$next[0:0]$12322 + attribute \src "libresoc.v:176749.5-176749.29" + switch \initial + attribute \src "libresoc.v:176749.9-176749.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$12322 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$12322 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12321 + end + attribute \src "libresoc.v:176757.3-176765.6" + process $proc$libresoc.v:176757$12323 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$12324 $1\rst_l_r_rst$next[0:0]$12325 + attribute \src "libresoc.v:176758.5-176758.29" + switch \initial + attribute \src "libresoc.v:176758.9-176758.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$12325 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$12325 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12324 + end + attribute \src "libresoc.v:176766.3-176774.6" + process $proc$libresoc.v:176766$12326 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$12327 $1\opc_l_s_opc$next[0:0]$12328 + attribute \src "libresoc.v:176767.5-176767.29" + switch \initial + attribute \src "libresoc.v:176767.9-176767.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$12328 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$12328 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12327 + end + attribute \src "libresoc.v:176775.3-176783.6" + process $proc$libresoc.v:176775$12329 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$12330 $1\opc_l_r_opc$next[0:0]$12331 + attribute \src "libresoc.v:176776.5-176776.29" + switch \initial + attribute \src "libresoc.v:176776.9-176776.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$12331 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$12331 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12330 + end + attribute \src "libresoc.v:176784.3-176792.6" + process $proc$libresoc.v:176784$12332 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[4:0]$12333 $1\src_l_s_src$next[4:0]$12334 + attribute \src "libresoc.v:176785.5-176785.29" + switch \initial + attribute \src "libresoc.v:176785.9-176785.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[4:0]$12334 5'00000 + case + assign $1\src_l_s_src$next[4:0]$12334 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[4:0]$12333 + end + attribute \src "libresoc.v:176793.3-176801.6" + process $proc$libresoc.v:176793$12335 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[4:0]$12336 $1\src_l_r_src$next[4:0]$12337 + attribute \src "libresoc.v:176794.5-176794.29" + switch \initial + attribute \src "libresoc.v:176794.9-176794.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[4:0]$12337 5'11111 + case + assign $1\src_l_r_src$next[4:0]$12337 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[4:0]$12336 + end + attribute \src "libresoc.v:176802.3-176810.6" + process $proc$libresoc.v:176802$12338 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[2:0]$12339 $1\req_l_s_req$next[2:0]$12340 + attribute \src "libresoc.v:176803.5-176803.29" + switch \initial + attribute \src "libresoc.v:176803.9-176803.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[2:0]$12340 3'000 + case + assign $1\req_l_s_req$next[2:0]$12340 \$66 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[2:0]$12339 + end + attribute \src "libresoc.v:176811.3-176819.6" + process $proc$libresoc.v:176811$12341 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[2:0]$12342 $1\req_l_r_req$next[2:0]$12343 + attribute \src "libresoc.v:176812.5-176812.29" + switch \initial + attribute \src "libresoc.v:176812.9-176812.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[2:0]$12343 3'111 + case + assign $1\req_l_r_req$next[2:0]$12343 \$68 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[2:0]$12342 + end + attribute \src "libresoc.v:176820.3-176857.6" + process $proc$libresoc.v:176820$12344 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_shift_rot0_sr_op__fn_unit$next[11:0]$12345 $1\alu_shift_rot0_sr_op__fn_unit$next[11:0]$12362 + assign { } { } + assign { } { } + assign $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12348 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12365 + assign $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12349 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12366 + assign $0\alu_shift_rot0_sr_op__insn$next[31:0]$12350 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12367 + assign $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12351 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12368 + assign $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12352 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12369 + assign $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12353 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12370 + assign $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12354 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12371 + assign { } { } + assign { } { } + assign $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12357 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12374 + assign $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12358 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12375 + assign { } { } + assign { } { } + assign $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12361 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12378 + assign $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12346 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12379 + assign $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12347 $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12380 + assign $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12355 $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12381 + assign $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12356 $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12382 + assign $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12359 $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12383 + assign $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12360 $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12384 + attribute \src "libresoc.v:176821.5-176821.29" + switch \initial + attribute \src "libresoc.v:176821.9-176821.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_shift_rot0_sr_op__insn$next[31:0]$12367 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12371 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12370 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12375 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12366 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12374 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12365 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12369 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12378 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12373 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12372 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12376 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12377 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12364 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12363 $1\alu_shift_rot0_sr_op__fn_unit$next[11:0]$12362 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12368 } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__invert_in \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type } + case + assign $1\alu_shift_rot0_sr_op__fn_unit$next[11:0]$12362 \alu_shift_rot0_sr_op__fn_unit + assign $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12363 \alu_shift_rot0_sr_op__imm_data__data + assign $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12364 \alu_shift_rot0_sr_op__imm_data__ok + assign $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12365 \alu_shift_rot0_sr_op__input_carry + assign $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12366 \alu_shift_rot0_sr_op__input_cr + assign $1\alu_shift_rot0_sr_op__insn$next[31:0]$12367 \alu_shift_rot0_sr_op__insn + assign $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12368 \alu_shift_rot0_sr_op__insn_type + assign $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12369 \alu_shift_rot0_sr_op__invert_in + assign $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12370 \alu_shift_rot0_sr_op__is_32bit + assign $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12371 \alu_shift_rot0_sr_op__is_signed + assign $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12372 \alu_shift_rot0_sr_op__oe__oe + assign $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12373 \alu_shift_rot0_sr_op__oe__ok + assign $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12374 \alu_shift_rot0_sr_op__output_carry + assign $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12375 \alu_shift_rot0_sr_op__output_cr + assign $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12376 \alu_shift_rot0_sr_op__rc__ok + assign $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12377 \alu_shift_rot0_sr_op__rc__rc + assign $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12378 \alu_shift_rot0_sr_op__write_cr0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12379 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12380 1'0 + assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12384 1'0 + assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12383 1'0 + assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12381 1'0 + assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12382 1'0 + case + assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12379 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12363 + assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12380 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12364 + assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12381 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12372 + assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12382 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12373 + assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12383 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12376 + assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12384 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12377 + end + sync always + update \alu_shift_rot0_sr_op__fn_unit$next $0\alu_shift_rot0_sr_op__fn_unit$next[11:0]$12345 + update \alu_shift_rot0_sr_op__imm_data__data$next $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12346 + update \alu_shift_rot0_sr_op__imm_data__ok$next $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12347 + update \alu_shift_rot0_sr_op__input_carry$next $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12348 + update \alu_shift_rot0_sr_op__input_cr$next $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12349 + update \alu_shift_rot0_sr_op__insn$next $0\alu_shift_rot0_sr_op__insn$next[31:0]$12350 + update \alu_shift_rot0_sr_op__insn_type$next $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12351 + update \alu_shift_rot0_sr_op__invert_in$next $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12352 + update \alu_shift_rot0_sr_op__is_32bit$next $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12353 + update \alu_shift_rot0_sr_op__is_signed$next $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12354 + update \alu_shift_rot0_sr_op__oe__oe$next $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12355 + update \alu_shift_rot0_sr_op__oe__ok$next $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12356 + update \alu_shift_rot0_sr_op__output_carry$next $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12357 + update \alu_shift_rot0_sr_op__output_cr$next $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12358 + update \alu_shift_rot0_sr_op__rc__ok$next $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12359 + update \alu_shift_rot0_sr_op__rc__rc$next $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12360 + update \alu_shift_rot0_sr_op__write_cr0$next $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12361 + end + attribute \src "libresoc.v:176858.3-176879.6" + process $proc$libresoc.v:176858$12385 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$12386 $2\data_r0__o$next[63:0]$12390 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$12387 $3\data_r0__o_ok$next[0:0]$12392 + attribute \src "libresoc.v:176859.5-176859.29" + switch \initial + attribute \src "libresoc.v:176859.9-176859.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$12389 $1\data_r0__o$next[63:0]$12388 } { \o_ok \alu_shift_rot0_o } + case + assign $1\data_r0__o$next[63:0]$12388 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$12389 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$12391 $2\data_r0__o$next[63:0]$12390 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$12390 $1\data_r0__o$next[63:0]$12388 + assign $2\data_r0__o_ok$next[0:0]$12391 $1\data_r0__o_ok$next[0:0]$12389 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$12392 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$12392 $2\data_r0__o_ok$next[0:0]$12391 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$12386 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12387 + end + attribute \src "libresoc.v:176880.3-176901.6" + process $proc$libresoc.v:176880$12393 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__cr_a$next[3:0]$12394 $2\data_r1__cr_a$next[3:0]$12398 + assign { } { } + assign $0\data_r1__cr_a_ok$next[0:0]$12395 $3\data_r1__cr_a_ok$next[0:0]$12400 + attribute \src "libresoc.v:176881.5-176881.29" + switch \initial + attribute \src "libresoc.v:176881.9-176881.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__cr_a_ok$next[0:0]$12397 $1\data_r1__cr_a$next[3:0]$12396 } { \cr_a_ok \alu_shift_rot0_cr_a } + case + assign $1\data_r1__cr_a$next[3:0]$12396 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$12397 \data_r1__cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__cr_a_ok$next[0:0]$12399 $2\data_r1__cr_a$next[3:0]$12398 } 5'00000 + case + assign $2\data_r1__cr_a$next[3:0]$12398 $1\data_r1__cr_a$next[3:0]$12396 + assign $2\data_r1__cr_a_ok$next[0:0]$12399 $1\data_r1__cr_a_ok$next[0:0]$12397 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__cr_a_ok$next[0:0]$12400 1'0 + case + assign $3\data_r1__cr_a_ok$next[0:0]$12400 $2\data_r1__cr_a_ok$next[0:0]$12399 + end + sync always + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$12394 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$12395 + end + attribute \src "libresoc.v:176902.3-176923.6" + process $proc$libresoc.v:176902$12401 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__xer_ca$next[1:0]$12402 $2\data_r2__xer_ca$next[1:0]$12406 + assign { } { } + assign $0\data_r2__xer_ca_ok$next[0:0]$12403 $3\data_r2__xer_ca_ok$next[0:0]$12408 + attribute \src "libresoc.v:176903.5-176903.29" + switch \initial + attribute \src "libresoc.v:176903.9-176903.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__xer_ca_ok$next[0:0]$12405 $1\data_r2__xer_ca$next[1:0]$12404 } { \xer_ca_ok \alu_shift_rot0_xer_ca } + case + assign $1\data_r2__xer_ca$next[1:0]$12404 \data_r2__xer_ca + assign $1\data_r2__xer_ca_ok$next[0:0]$12405 \data_r2__xer_ca_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__xer_ca_ok$next[0:0]$12407 $2\data_r2__xer_ca$next[1:0]$12406 } 3'000 + case + assign $2\data_r2__xer_ca$next[1:0]$12406 $1\data_r2__xer_ca$next[1:0]$12404 + assign $2\data_r2__xer_ca_ok$next[0:0]$12407 $1\data_r2__xer_ca_ok$next[0:0]$12405 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__xer_ca_ok$next[0:0]$12408 1'0 + case + assign $3\data_r2__xer_ca_ok$next[0:0]$12408 $2\data_r2__xer_ca_ok$next[0:0]$12407 + end + sync always + update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$12402 + update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$12403 + end + attribute \src "libresoc.v:176924.3-176933.6" + process $proc$libresoc.v:176924$12409 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$12410 $1\src_r0$next[63:0]$12411 + attribute \src "libresoc.v:176925.5-176925.29" + switch \initial + attribute \src "libresoc.v:176925.9-176925.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$12411 \src1_i + case + assign $1\src_r0$next[63:0]$12411 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$12410 + end + attribute \src "libresoc.v:176934.3-176943.6" + process $proc$libresoc.v:176934$12412 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$12413 $1\src_r1$next[63:0]$12414 + attribute \src "libresoc.v:176935.5-176935.29" + switch \initial + attribute \src "libresoc.v:176935.9-176935.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_sel + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$12414 \src_or_imm + case + assign $1\src_r1$next[63:0]$12414 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$12413 + end + attribute \src "libresoc.v:176944.3-176953.6" + process $proc$libresoc.v:176944$12415 + assign { } { } + assign { } { } + assign $0\src_r2$next[63:0]$12416 $1\src_r2$next[63:0]$12417 + attribute \src "libresoc.v:176945.5-176945.29" + switch \initial + attribute \src "libresoc.v:176945.9-176945.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[63:0]$12417 \src3_i + case + assign $1\src_r2$next[63:0]$12417 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[63:0]$12416 + end + attribute \src "libresoc.v:176954.3-176963.6" + process $proc$libresoc.v:176954$12418 + assign { } { } + assign { } { } + assign $0\src_r3$next[0:0]$12419 $1\src_r3$next[0:0]$12420 + attribute \src "libresoc.v:176955.5-176955.29" + switch \initial + attribute \src "libresoc.v:176955.9-176955.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r3$next[0:0]$12420 \src4_i + case + assign $1\src_r3$next[0:0]$12420 \src_r3 + end + sync always + update \src_r3$next $0\src_r3$next[0:0]$12419 + end + attribute \src "libresoc.v:176964.3-176973.6" + process $proc$libresoc.v:176964$12421 + assign { } { } + assign { } { } + assign $0\src_r4$next[1:0]$12422 $1\src_r4$next[1:0]$12423 + attribute \src "libresoc.v:176965.5-176965.29" + switch \initial + attribute \src "libresoc.v:176965.9-176965.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r4$next[1:0]$12423 \src5_i + case + assign $1\src_r4$next[1:0]$12423 \src_r4 + end + sync always + update \src_r4$next $0\src_r4$next[1:0]$12422 + end + attribute \src "libresoc.v:176974.3-176982.6" + process $proc$libresoc.v:176974$12424 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$12425 $1\alui_l_r_alui$next[0:0]$12426 + attribute \src "libresoc.v:176975.5-176975.29" + switch \initial + attribute \src "libresoc.v:176975.9-176975.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$12426 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$12426 \$90 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12425 + end + attribute \src "libresoc.v:176983.3-176991.6" + process $proc$libresoc.v:176983$12427 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$12428 $1\alu_l_r_alu$next[0:0]$12429 + attribute \src "libresoc.v:176984.5-176984.29" + switch \initial + attribute \src "libresoc.v:176984.9-176984.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$12429 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$12429 \$92 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12428 + end + attribute \src "libresoc.v:176992.3-177001.6" + process $proc$libresoc.v:176992$12430 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:176993.5-176993.29" + switch \initial + attribute \src "libresoc.v:176993.9-176993.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$114 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__o + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "libresoc.v:177002.3-177011.6" + process $proc$libresoc.v:177002$12431 + assign { } { } + assign { } { } + assign $0\dest2_o[3:0] $1\dest2_o[3:0] + attribute \src "libresoc.v:177003.5-177003.29" + switch \initial + attribute \src "libresoc.v:177003.9-177003.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$116 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[3:0] \data_r1__cr_a + case + assign $1\dest2_o[3:0] 4'0000 + end + sync always + update \dest2_o $0\dest2_o[3:0] + end + attribute \src "libresoc.v:177012.3-177021.6" + process $proc$libresoc.v:177012$12432 + assign { } { } + assign { } { } + assign $0\dest3_o[1:0] $1\dest3_o[1:0] + attribute \src "libresoc.v:177013.5-177013.29" + switch \initial + attribute \src "libresoc.v:177013.9-177013.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$118 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest3_o[1:0] \data_r2__xer_ca + case + assign $1\dest3_o[1:0] 2'00 + end + sync always + update \dest3_o $0\dest3_o[1:0] + end + attribute \src "libresoc.v:177022.3-177030.6" + process $proc$libresoc.v:177022$12433 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[2:0]$12434 $1\prev_wr_go$next[2:0]$12435 + attribute \src "libresoc.v:177023.5-177023.29" + switch \initial + attribute \src "libresoc.v:177023.9-177023.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[2:0]$12435 3'000 + case + assign $1\prev_wr_go$next[2:0]$12435 \$20 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[2:0]$12434 + end + connect \$100 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64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12640 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12640 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 39 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12641 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12641 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 40 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12642 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12642 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 41 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12643 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12643 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 42 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12644 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12644 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 43 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12645 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12645 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 44 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12646 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12646 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 45 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12647 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12647 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 46 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12648 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12648 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 47 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12649 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12649 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 48 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12650 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12650 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 49 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12651 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12651 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 50 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12652 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12652 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 51 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12653 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12653 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 52 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12654 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12654 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 53 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12655 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12655 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 54 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12656 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12656 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 55 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12657 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12657 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 56 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12658 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12658 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 57 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12659 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12659 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 58 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12660 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12660 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 59 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12661 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12661 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 60 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12662 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12662 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 61 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12663 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12663 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 62 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12664 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12664 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 63 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12665 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12665 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 64 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12666 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12666 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 65 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12667 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12667 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 66 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12668 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12668 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 67 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12669 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12669 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 68 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12670 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12670 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 69 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12671 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12671 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 70 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12672 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12672 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 71 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12673 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12673 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 72 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12674 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12674 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 73 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12675 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12675 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 74 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12676 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12676 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 75 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12677 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12677 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 76 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12678 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12678 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 77 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12679 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12679 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 78 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12680 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12680 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 79 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12681 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12681 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 80 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12682 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12682 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 81 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12683 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12683 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 82 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12684 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12684 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 83 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12685 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12685 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 84 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12686 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12686 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 85 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12687 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12687 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 86 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12688 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12688 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 87 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12689 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12689 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 88 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12690 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12690 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 89 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12691 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12691 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 90 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12692 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12692 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 91 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12693 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12693 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 92 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12694 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12694 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 93 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12695 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12695 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 94 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12696 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12696 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 95 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12697 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12697 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 96 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12698 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12698 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 97 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12699 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12699 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 98 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12700 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12700 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 99 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12701 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12701 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 100 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12702 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12702 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 101 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12703 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12703 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 102 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12704 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12704 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 103 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12705 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12705 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 104 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12706 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12706 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 105 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12707 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12707 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 106 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12708 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12708 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 107 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12709 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12709 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 108 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12710 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12710 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 109 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:177220.26-177220.32" + cell $memrd $memrd$\memory$libresoc.v:177220$12596 + parameter \ABITS 7 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_0_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:177220$12596_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:0.0-0.0" + cell $memwr $memwr$\memory$libresoc.v:0$12711 + parameter \ABITS 7 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \PRIORITY 12711 + parameter \WIDTH 64 + connect \ADDR $memwr$\memory$libresoc.v:177218$12590_ADDR + connect \CLK 1'x + connect \DATA $memwr$\memory$libresoc.v:177218$12590_DATA + connect \EN $memwr$\memory$libresoc.v:177218$12590_EN + end + attribute \src "libresoc.v:0.0-0.0" + process $proc$libresoc.v:0$12714 + sync always + sync init + end + attribute \src "libresoc.v:177068.7-177068.20" + process $proc$libresoc.v:177068$12712 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:177084.7-177084.23" + process $proc$libresoc.v:177084$12713 + assign { } { } + assign $1\ren_delay[0:0] 1'0 + sync always + sync init + update \ren_delay $1\ren_delay[0:0] + end + attribute \src "libresoc.v:177100.3-177101.35" + process $proc$libresoc.v:177100$12591 + assign { } { } + assign $0\ren_delay[0:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[0:0] + end + attribute \src "libresoc.v:177216.3-177219.6" + process $proc$libresoc.v:177216$12592 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\memory$libresoc.v:177218$12590_ADDR[6:0]$12593 7'xxxxxxx + assign $0$memwr$\memory$libresoc.v:177218$12590_DATA[63:0]$12594 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:177218$12590_EN[63:0]$12595 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\_0_[6:0] \spr1__addr + attribute \src "libresoc.v:177218.5-177218.59" + switch \spr1__wen + attribute \src "libresoc.v:177218.9-177218.18" + case 1'1 + assign $0$memwr$\memory$libresoc.v:177218$12590_ADDR[6:0]$12593 \spr1__addr$1 + assign $0$memwr$\memory$libresoc.v:177218$12590_DATA[63:0]$12594 \spr1__data_i + assign $0$memwr$\memory$libresoc.v:177218$12590_EN[63:0]$12595 64'1111111111111111111111111111111111111111111111111111111111111111 + case + end + sync posedge \coresync_clk + update \_0_ $0\_0_[6:0] + update $memwr$\memory$libresoc.v:177218$12590_ADDR $0$memwr$\memory$libresoc.v:177218$12590_ADDR[6:0]$12593 + update $memwr$\memory$libresoc.v:177218$12590_DATA $0$memwr$\memory$libresoc.v:177218$12590_DATA[63:0]$12594 + update $memwr$\memory$libresoc.v:177218$12590_EN $0$memwr$\memory$libresoc.v:177218$12590_EN[63:0]$12595 + end + attribute \src "libresoc.v:177221.3-177229.6" + process $proc$libresoc.v:177221$12597 + assign { } { } + assign { } { } + assign $0\ren_delay$next[0:0]$12598 $1\ren_delay$next[0:0]$12599 + attribute \src "libresoc.v:177222.5-177222.29" + switch \initial + attribute \src "libresoc.v:177222.9-177222.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$next[0:0]$12599 1'0 + case + assign $1\ren_delay$next[0:0]$12599 \spr1__ren + end + sync always + update \ren_delay$next $0\ren_delay$next[0:0]$12598 + end + attribute \src "libresoc.v:177230.3-177239.6" + process $proc$libresoc.v:177230$12600 + assign { } { } + assign { } { } + assign $0\spr1__data_o[63:0] $1\spr1__data_o[63:0] + attribute \src "libresoc.v:177231.5-177231.29" + switch \initial + attribute \src "libresoc.v:177231.9-177231.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\spr1__data_o[63:0] \memory_r_data + case + assign $1\spr1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \spr1__data_o $0\spr1__data_o[63:0] + end + connect \memory_r_data $memrd$\memory$libresoc.v:177220$12596_DATA + connect \memory_w_data \spr1__data_i + connect \memory_w_en \spr1__wen + connect \memory_w_addr \spr1__addr$1 + connect \memory_r_addr \spr1__addr +end +attribute \src "libresoc.v:177248.1-178495.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0" +attribute \generator "nMigen" +module \spr0 + attribute \src "libresoc.v:177992.3-177993.25" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:177990.3-177991.40" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:178386.3-178394.6" + wire $0\alu_l_r_alu$next[0:0]$12928 + attribute \src "libresoc.v:177920.3-177921.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:178172.3-178184.6" + wire width 12 $0\alu_spr0_spr_op__fn_unit$next[11:0]$12850 + attribute \src "libresoc.v:177962.3-177963.65" + wire width 12 $0\alu_spr0_spr_op__fn_unit[11:0] + attribute \src "libresoc.v:178172.3-178184.6" + wire width 32 $0\alu_spr0_spr_op__insn$next[31:0]$12851 + attribute \src "libresoc.v:177964.3-177965.59" + wire width 32 $0\alu_spr0_spr_op__insn[31:0] + attribute \src "libresoc.v:178172.3-178184.6" + wire width 7 $0\alu_spr0_spr_op__insn_type$next[6:0]$12852 + attribute \src "libresoc.v:177960.3-177961.69" + wire width 7 $0\alu_spr0_spr_op__insn_type[6:0] + attribute \src "libresoc.v:178172.3-178184.6" + wire $0\alu_spr0_spr_op__is_32bit$next[0:0]$12853 + attribute \src "libresoc.v:177966.3-177967.67" + wire $0\alu_spr0_spr_op__is_32bit[0:0] + attribute \src "libresoc.v:178377.3-178385.6" + wire $0\alui_l_r_alui$next[0:0]$12925 + attribute \src "libresoc.v:177922.3-177923.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:178185.3-178206.6" + wire width 64 $0\data_r0__o$next[63:0]$12859 + attribute \src "libresoc.v:177956.3-177957.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "libresoc.v:178185.3-178206.6" + wire $0\data_r0__o_ok$next[0:0]$12860 + attribute \src "libresoc.v:177958.3-177959.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "libresoc.v:178207.3-178228.6" + wire width 64 $0\data_r1__spr1$next[63:0]$12867 + attribute \src "libresoc.v:177952.3-177953.43" + wire width 64 $0\data_r1__spr1[63:0] + attribute \src "libresoc.v:178207.3-178228.6" + wire $0\data_r1__spr1_ok$next[0:0]$12868 + attribute \src "libresoc.v:177954.3-177955.49" + wire $0\data_r1__spr1_ok[0:0] + attribute \src "libresoc.v:178229.3-178250.6" + wire width 64 $0\data_r2__fast1$next[63:0]$12875 + attribute \src "libresoc.v:177948.3-177949.45" + wire width 64 $0\data_r2__fast1[63:0] + attribute \src "libresoc.v:178229.3-178250.6" + wire $0\data_r2__fast1_ok$next[0:0]$12876 + attribute \src "libresoc.v:177950.3-177951.51" + wire $0\data_r2__fast1_ok[0:0] + attribute \src "libresoc.v:178251.3-178272.6" + wire $0\data_r3__xer_so$next[0:0]$12883 + attribute \src "libresoc.v:177944.3-177945.47" + wire $0\data_r3__xer_so[0:0] + attribute \src "libresoc.v:178251.3-178272.6" + wire $0\data_r3__xer_so_ok$next[0:0]$12884 + attribute \src "libresoc.v:177946.3-177947.53" + wire $0\data_r3__xer_so_ok[0:0] + attribute \src "libresoc.v:178273.3-178294.6" + wire width 2 $0\data_r4__xer_ov$next[1:0]$12891 + attribute \src "libresoc.v:177940.3-177941.47" + wire width 2 $0\data_r4__xer_ov[1:0] + attribute \src "libresoc.v:178273.3-178294.6" + wire $0\data_r4__xer_ov_ok$next[0:0]$12892 + attribute \src "libresoc.v:177942.3-177943.53" + wire $0\data_r4__xer_ov_ok[0:0] + attribute \src "libresoc.v:178295.3-178316.6" + wire width 2 $0\data_r5__xer_ca$next[1:0]$12899 + attribute \src "libresoc.v:177936.3-177937.47" + wire width 2 $0\data_r5__xer_ca[1:0] + attribute \src "libresoc.v:178295.3-178316.6" + wire $0\data_r5__xer_ca_ok$next[0:0]$12900 + attribute \src "libresoc.v:177938.3-177939.53" + wire $0\data_r5__xer_ca_ok[0:0] + attribute \src "libresoc.v:178395.3-178404.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:178405.3-178414.6" + wire width 64 $0\dest2_o[63:0] + attribute \src "libresoc.v:178415.3-178424.6" + wire width 64 $0\dest3_o[63:0] + attribute \src "libresoc.v:178425.3-178434.6" + wire $0\dest4_o[0:0] + attribute \src "libresoc.v:178435.3-178444.6" + wire width 2 $0\dest5_o[1:0] + attribute \src "libresoc.v:178445.3-178454.6" + wire width 2 $0\dest6_o[1:0] + attribute \src "libresoc.v:177249.7-177249.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:178127.3-178135.6" + wire $0\opc_l_r_opc$next[0:0]$12835 + attribute \src "libresoc.v:177976.3-177977.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:178118.3-178126.6" + wire $0\opc_l_s_opc$next[0:0]$12832 + attribute \src "libresoc.v:177978.3-177979.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:178455.3-178463.6" + wire width 6 $0\prev_wr_go$next[5:0]$12937 + attribute \src "libresoc.v:177988.3-177989.37" + wire width 6 $0\prev_wr_go[5:0] + attribute \src "libresoc.v:178072.3-178081.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:178163.3-178171.6" + wire width 6 $0\req_l_r_req$next[5:0]$12847 + attribute \src "libresoc.v:177968.3-177969.39" + wire width 6 $0\req_l_r_req[5:0] + attribute \src "libresoc.v:178154.3-178162.6" + wire width 6 $0\req_l_s_req$next[5:0]$12844 + attribute \src "libresoc.v:177970.3-177971.39" + wire width 6 $0\req_l_s_req[5:0] + attribute \src "libresoc.v:178091.3-178099.6" + wire $0\rok_l_r_rdok$next[0:0]$12823 + attribute \src "libresoc.v:177984.3-177985.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:178082.3-178090.6" + wire $0\rok_l_s_rdok$next[0:0]$12820 + attribute \src "libresoc.v:177986.3-177987.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:178109.3-178117.6" + wire $0\rst_l_r_rst$next[0:0]$12829 + attribute \src "libresoc.v:177980.3-177981.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:178100.3-178108.6" + wire $0\rst_l_s_rst$next[0:0]$12826 + attribute \src "libresoc.v:177982.3-177983.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:178145.3-178153.6" + wire width 6 $0\src_l_r_src$next[5:0]$12841 + attribute \src "libresoc.v:177972.3-177973.39" + wire width 6 $0\src_l_r_src[5:0] + attribute \src "libresoc.v:178136.3-178144.6" + wire width 6 $0\src_l_s_src$next[5:0]$12838 + attribute \src "libresoc.v:177974.3-177975.39" + wire width 6 $0\src_l_s_src[5:0] + attribute \src "libresoc.v:178317.3-178326.6" + wire width 64 $0\src_r0$next[63:0]$12907 + attribute \src "libresoc.v:177934.3-177935.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:178327.3-178336.6" + wire width 64 $0\src_r1$next[63:0]$12910 + attribute \src "libresoc.v:177932.3-177933.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:178337.3-178346.6" + wire width 64 $0\src_r2$next[63:0]$12913 + attribute \src "libresoc.v:177930.3-177931.29" + wire width 64 $0\src_r2[63:0] + attribute \src "libresoc.v:178347.3-178356.6" + wire $0\src_r3$next[0:0]$12916 + attribute \src "libresoc.v:177928.3-177929.29" + wire $0\src_r3[0:0] + attribute \src "libresoc.v:178357.3-178366.6" + wire width 2 $0\src_r4$next[1:0]$12919 + attribute \src "libresoc.v:177926.3-177927.29" + wire width 2 $0\src_r4[1:0] + attribute \src "libresoc.v:178367.3-178376.6" + wire width 2 $0\src_r5$next[1:0]$12922 + attribute \src "libresoc.v:177924.3-177925.29" + wire width 2 $0\src_r5[1:0] + attribute \src "libresoc.v:177385.7-177385.24" + wire $1\all_rd_dly[0:0] + attribute \src "libresoc.v:177395.7-177395.26" + wire $1\alu_done_dly[0:0] + attribute \src "libresoc.v:178386.3-178394.6" + wire $1\alu_l_r_alu$next[0:0]$12929 + attribute \src "libresoc.v:177403.7-177403.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "libresoc.v:178172.3-178184.6" + wire width 12 $1\alu_spr0_spr_op__fn_unit$next[11:0]$12854 + attribute \src "libresoc.v:177446.14-177446.48" + wire width 12 $1\alu_spr0_spr_op__fn_unit[11:0] + attribute \src "libresoc.v:178172.3-178184.6" + wire width 32 $1\alu_spr0_spr_op__insn$next[31:0]$12855 + attribute \src "libresoc.v:177450.14-177450.43" + wire width 32 $1\alu_spr0_spr_op__insn[31:0] + attribute \src "libresoc.v:178172.3-178184.6" + wire width 7 $1\alu_spr0_spr_op__insn_type$next[6:0]$12856 + attribute \src "libresoc.v:177528.13-177528.47" + wire width 7 $1\alu_spr0_spr_op__insn_type[6:0] + attribute \src "libresoc.v:178172.3-178184.6" + wire $1\alu_spr0_spr_op__is_32bit$next[0:0]$12857 + attribute \src "libresoc.v:177532.7-177532.39" + wire $1\alu_spr0_spr_op__is_32bit[0:0] + attribute \src "libresoc.v:178377.3-178385.6" + wire $1\alui_l_r_alui$next[0:0]$12926 + attribute \src "libresoc.v:177550.7-177550.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "libresoc.v:178185.3-178206.6" + wire width 64 $1\data_r0__o$next[63:0]$12861 + attribute \src "libresoc.v:177582.14-177582.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "libresoc.v:178185.3-178206.6" + wire $1\data_r0__o_ok$next[0:0]$12862 + attribute \src "libresoc.v:177586.7-177586.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "libresoc.v:178207.3-178228.6" + wire width 64 $1\data_r1__spr1$next[63:0]$12869 + attribute \src "libresoc.v:177590.14-177590.50" + wire width 64 $1\data_r1__spr1[63:0] + attribute \src "libresoc.v:178207.3-178228.6" + wire $1\data_r1__spr1_ok$next[0:0]$12870 + attribute \src "libresoc.v:177594.7-177594.30" + wire $1\data_r1__spr1_ok[0:0] + attribute \src "libresoc.v:178229.3-178250.6" + wire width 64 $1\data_r2__fast1$next[63:0]$12877 + attribute \src "libresoc.v:177598.14-177598.51" + wire width 64 $1\data_r2__fast1[63:0] + attribute \src "libresoc.v:178229.3-178250.6" + wire $1\data_r2__fast1_ok$next[0:0]$12878 + attribute \src "libresoc.v:177602.7-177602.31" + wire $1\data_r2__fast1_ok[0:0] + attribute \src "libresoc.v:178251.3-178272.6" + wire $1\data_r3__xer_so$next[0:0]$12885 + attribute \src "libresoc.v:177606.7-177606.29" + wire $1\data_r3__xer_so[0:0] + attribute \src "libresoc.v:178251.3-178272.6" + wire $1\data_r3__xer_so_ok$next[0:0]$12886 + attribute \src "libresoc.v:177610.7-177610.32" + wire $1\data_r3__xer_so_ok[0:0] + attribute \src "libresoc.v:178273.3-178294.6" + wire width 2 $1\data_r4__xer_ov$next[1:0]$12893 + attribute \src "libresoc.v:177614.13-177614.35" + wire width 2 $1\data_r4__xer_ov[1:0] + attribute \src "libresoc.v:178273.3-178294.6" + wire $1\data_r4__xer_ov_ok$next[0:0]$12894 + attribute \src "libresoc.v:177618.7-177618.32" + wire $1\data_r4__xer_ov_ok[0:0] + attribute \src "libresoc.v:178295.3-178316.6" + wire width 2 $1\data_r5__xer_ca$next[1:0]$12901 + attribute \src "libresoc.v:177622.13-177622.35" + wire width 2 $1\data_r5__xer_ca[1:0] + attribute \src "libresoc.v:178295.3-178316.6" + wire $1\data_r5__xer_ca_ok$next[0:0]$12902 + attribute \src "libresoc.v:177626.7-177626.32" + wire $1\data_r5__xer_ca_ok[0:0] + attribute \src "libresoc.v:178395.3-178404.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "libresoc.v:178405.3-178414.6" + wire width 64 $1\dest2_o[63:0] + attribute \src "libresoc.v:178415.3-178424.6" + wire width 64 $1\dest3_o[63:0] + attribute \src "libresoc.v:178425.3-178434.6" + wire $1\dest4_o[0:0] + attribute \src "libresoc.v:178435.3-178444.6" + wire width 2 $1\dest5_o[1:0] + attribute \src "libresoc.v:178445.3-178454.6" + wire width 2 $1\dest6_o[1:0] + attribute \src "libresoc.v:178127.3-178135.6" + wire $1\opc_l_r_opc$next[0:0]$12836 + attribute \src "libresoc.v:177654.7-177654.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "libresoc.v:178118.3-178126.6" + wire $1\opc_l_s_opc$next[0:0]$12833 + attribute \src "libresoc.v:177658.7-177658.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "libresoc.v:178455.3-178463.6" + wire width 6 $1\prev_wr_go$next[5:0]$12938 + attribute \src "libresoc.v:177757.13-177757.31" + wire width 6 $1\prev_wr_go[5:0] + attribute \src "libresoc.v:178072.3-178081.6" + wire $1\req_done[0:0] + attribute \src "libresoc.v:178163.3-178171.6" + wire width 6 $1\req_l_r_req$next[5:0]$12848 + attribute \src "libresoc.v:177765.13-177765.32" + wire width 6 $1\req_l_r_req[5:0] + attribute \src "libresoc.v:178154.3-178162.6" + wire width 6 $1\req_l_s_req$next[5:0]$12845 + attribute \src "libresoc.v:177769.13-177769.32" + wire width 6 $1\req_l_s_req[5:0] + attribute \src "libresoc.v:178091.3-178099.6" + wire $1\rok_l_r_rdok$next[0:0]$12824 + attribute \src "libresoc.v:177781.7-177781.26" + wire $1\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:178082.3-178090.6" + wire $1\rok_l_s_rdok$next[0:0]$12821 + attribute \src "libresoc.v:177785.7-177785.26" + wire $1\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:178109.3-178117.6" + wire $1\rst_l_r_rst$next[0:0]$12830 + attribute \src "libresoc.v:177789.7-177789.25" + wire $1\rst_l_r_rst[0:0] + attribute \src "libresoc.v:178100.3-178108.6" + wire $1\rst_l_s_rst$next[0:0]$12827 + attribute \src "libresoc.v:177793.7-177793.25" + wire $1\rst_l_s_rst[0:0] + attribute \src "libresoc.v:178145.3-178153.6" + wire width 6 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"DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_spr0_spr_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_spr0_spr_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_spr0_spr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_spr0_spr_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 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attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + 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\alu_spr0_spr_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_spr0_spr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_spr0_spr_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \alu_spr0_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \alu_spr0_xer_ca$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \alu_spr0_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \alu_spr0_xer_ov$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \alu_spr0_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \alu_spr0_xer_so$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \alui_l_s_alui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 31 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 7 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 6 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 input 10 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 output 9 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 6 input 8 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 input 19 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 output 18 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 6 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r1__spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r1__spr1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__spr1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r2__fast1 + attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src 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\req_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 6 \req_l_q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 6 \req_l_r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 6 \req_l_r_req$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 6 \req_l_s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 6 \req_l_s_req$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + wire \reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" + wire width 6 \reset_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" + wire width 6 \reset_w + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \rok_l_q_rdok + attribute \src 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parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$46 + connect \B 1'0 + connect \Y $eq$libresoc.v:177893$12754_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $eq$libresoc.v:177895$12756 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $eq$libresoc.v:177895$12756_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$libresoc.v:177854$12715 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_rd__rel_o + connect \Y $not$libresoc.v:177854$12715_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$libresoc.v:177858$12719 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_rdmaskn_i + connect \Y $not$libresoc.v:177858$12719_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:177877$12738 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $not$libresoc.v:177877$12738_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:177879$12740 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $not$libresoc.v:177879$12740_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:177882$12743 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_wrmask_o + connect \Y $not$libresoc.v:177882$12743_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:177885$12746 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$27 + connect \Y $not$libresoc.v:177885$12746_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$libresoc.v:177890$12751 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_spr0_n_ready_i + connect \Y $not$libresoc.v:177890$12751_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:177865$12726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$9 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:177865$12726_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$libresoc.v:177889$12750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$36 + connect \B \$38 + connect \Y $or$libresoc.v:177889$12750_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$libresoc.v:177899$12760 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:177899$12760_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$libresoc.v:177900$12761 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:177900$12761_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$libresoc.v:177901$12762 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:177901$12762_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$libresoc.v:177902$12763 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:177902$12763_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:177906$12767 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$libresoc.v:177906$12767_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:177871$12732 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \$11 + connect \Y $reduce_and$libresoc.v:177871$12732_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:177884$12745 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \$30 + connect \Y $reduce_or$libresoc.v:177884$12745_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:177887$12748 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:177887$12748_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:177888$12749 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:177888$12749_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:177913$12774 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $ternary$libresoc.v:177913$12774_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:177914$12775 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src2_i + connect \S \src_l_q_src [1] + connect \Y $ternary$libresoc.v:177914$12775_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:177915$12776 + parameter \WIDTH 64 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:177915$12776_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:177916$12777 + parameter \WIDTH 1 + connect \A \src_r3 + connect \B \src4_i + connect \S \src_l_q_src [3] + connect \Y $ternary$libresoc.v:177916$12777_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:177917$12778 + parameter \WIDTH 2 + connect \A \src_r4 + connect \B \src5_i + connect \S \src_l_q_src [4] + connect \Y $ternary$libresoc.v:177917$12778_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:177918$12779 + parameter \WIDTH 2 + connect \A \src_r5 + connect \B \src6_i + connect \S \src_l_q_src [5] + connect \Y $ternary$libresoc.v:177918$12779_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:177994.14-178000.4" + cell \alu_l$73 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:178001.12-178030.4" + cell \alu_spr0 \alu_spr0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \fast1 \alu_spr0_fast1 + connect \fast1$2 \alu_spr0_fast1$2 + connect \fast1_ok \fast1_ok + connect \n_ready_i \alu_spr0_n_ready_i + connect \n_valid_o \alu_spr0_n_valid_o + connect \o \alu_spr0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_spr0_p_ready_o + connect \p_valid_i \alu_spr0_p_valid_i + connect \ra \alu_spr0_ra + connect \spr1 \alu_spr0_spr1 + connect \spr1$1 \alu_spr0_spr1$1 + connect \spr1_ok \spr1_ok + connect \spr_op__fn_unit \alu_spr0_spr_op__fn_unit + connect \spr_op__insn \alu_spr0_spr_op__insn + connect \spr_op__insn_type \alu_spr0_spr_op__insn_type + connect \spr_op__is_32bit \alu_spr0_spr_op__is_32bit + connect \xer_ca \alu_spr0_xer_ca + connect \xer_ca$5 \alu_spr0_xer_ca$5 + connect \xer_ca_ok \xer_ca_ok + connect \xer_ov \alu_spr0_xer_ov + connect \xer_ov$4 \alu_spr0_xer_ov$4 + connect \xer_ov_ok \xer_ov_ok + connect \xer_so \alu_spr0_xer_so + connect \xer_so$3 \alu_spr0_xer_so$3 + connect \xer_so_ok \xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:178031.15-178037.4" + cell \alui_l$72 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:178038.14-178044.4" + cell \opc_l$68 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:178045.14-178051.4" + cell \req_l$69 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:178052.14-178058.4" + cell \rok_l$71 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:178059.14-178064.4" + cell \rst_l$70 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:178065.14-178071.4" + cell \src_l$67 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "libresoc.v:177249.7-177249.20" + process $proc$libresoc.v:177249$12939 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:177385.7-177385.24" + process $proc$libresoc.v:177385$12940 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "libresoc.v:177395.7-177395.26" + process $proc$libresoc.v:177395$12941 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "libresoc.v:177403.7-177403.25" + process $proc$libresoc.v:177403$12942 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:177446.14-177446.48" + process $proc$libresoc.v:177446$12943 + assign { } { } + assign $1\alu_spr0_spr_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \alu_spr0_spr_op__fn_unit $1\alu_spr0_spr_op__fn_unit[11:0] + end + attribute \src "libresoc.v:177450.14-177450.43" + process $proc$libresoc.v:177450$12944 + assign { } { } + assign $1\alu_spr0_spr_op__insn[31:0] 0 + sync always + sync init + update \alu_spr0_spr_op__insn $1\alu_spr0_spr_op__insn[31:0] + end + attribute \src "libresoc.v:177528.13-177528.47" + process $proc$libresoc.v:177528$12945 + assign { } { } + assign $1\alu_spr0_spr_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_spr0_spr_op__insn_type $1\alu_spr0_spr_op__insn_type[6:0] + end + attribute \src "libresoc.v:177532.7-177532.39" + process $proc$libresoc.v:177532$12946 + assign { } { } + assign $1\alu_spr0_spr_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_spr0_spr_op__is_32bit $1\alu_spr0_spr_op__is_32bit[0:0] + end + attribute \src "libresoc.v:177550.7-177550.27" + process $proc$libresoc.v:177550$12947 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:177582.14-177582.47" + process $proc$libresoc.v:177582$12948 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "libresoc.v:177586.7-177586.27" + process $proc$libresoc.v:177586$12949 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:177590.14-177590.50" + process $proc$libresoc.v:177590$12950 + assign { } { } + assign $1\data_r1__spr1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r1__spr1 $1\data_r1__spr1[63:0] + end + attribute \src "libresoc.v:177594.7-177594.30" + process $proc$libresoc.v:177594$12951 + assign { } { } + assign $1\data_r1__spr1_ok[0:0] 1'0 + sync always + sync init + update \data_r1__spr1_ok $1\data_r1__spr1_ok[0:0] + end + attribute \src "libresoc.v:177598.14-177598.51" + process $proc$libresoc.v:177598$12952 + assign { } { } + assign $1\data_r2__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r2__fast1 $1\data_r2__fast1[63:0] + end + attribute \src "libresoc.v:177602.7-177602.31" + process $proc$libresoc.v:177602$12953 + assign { } { } + assign $1\data_r2__fast1_ok[0:0] 1'0 + sync always + sync init + update \data_r2__fast1_ok $1\data_r2__fast1_ok[0:0] + end + attribute \src "libresoc.v:177606.7-177606.29" + process $proc$libresoc.v:177606$12954 + assign { } { } + assign $1\data_r3__xer_so[0:0] 1'0 + sync always + sync init + update \data_r3__xer_so $1\data_r3__xer_so[0:0] + end + attribute \src "libresoc.v:177610.7-177610.32" + process $proc$libresoc.v:177610$12955 + assign { } { } + assign $1\data_r3__xer_so_ok[0:0] 1'0 + sync always + sync init + update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] + end + attribute \src "libresoc.v:177614.13-177614.35" + process $proc$libresoc.v:177614$12956 + assign { } { } + assign $1\data_r4__xer_ov[1:0] 2'00 + sync always + sync init + update \data_r4__xer_ov $1\data_r4__xer_ov[1:0] + end + attribute \src "libresoc.v:177618.7-177618.32" + process $proc$libresoc.v:177618$12957 + assign { } { } + assign $1\data_r4__xer_ov_ok[0:0] 1'0 + sync always + sync init + update \data_r4__xer_ov_ok $1\data_r4__xer_ov_ok[0:0] + end + attribute \src "libresoc.v:177622.13-177622.35" + process $proc$libresoc.v:177622$12958 + assign { } { } + assign $1\data_r5__xer_ca[1:0] 2'00 + sync always + sync init + update \data_r5__xer_ca $1\data_r5__xer_ca[1:0] + end + attribute \src "libresoc.v:177626.7-177626.32" + process $proc$libresoc.v:177626$12959 + assign { } { } + assign $1\data_r5__xer_ca_ok[0:0] 1'0 + sync always + sync init + update \data_r5__xer_ca_ok $1\data_r5__xer_ca_ok[0:0] + end + attribute \src "libresoc.v:177654.7-177654.25" + process $proc$libresoc.v:177654$12960 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:177658.7-177658.25" + process $proc$libresoc.v:177658$12961 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:177757.13-177757.31" + process $proc$libresoc.v:177757$12962 + assign { } { } + assign $1\prev_wr_go[5:0] 6'000000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[5:0] + end + attribute \src "libresoc.v:177765.13-177765.32" + process $proc$libresoc.v:177765$12963 + assign { } { } + assign $1\req_l_r_req[5:0] 6'111111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[5:0] + end + attribute \src "libresoc.v:177769.13-177769.32" + process $proc$libresoc.v:177769$12964 + assign { } { } + assign $1\req_l_s_req[5:0] 6'000000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[5:0] + end + attribute \src "libresoc.v:177781.7-177781.26" + process $proc$libresoc.v:177781$12965 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:177785.7-177785.26" + process $proc$libresoc.v:177785$12966 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:177789.7-177789.25" + process $proc$libresoc.v:177789$12967 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:177793.7-177793.25" + process $proc$libresoc.v:177793$12968 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:177815.13-177815.32" + process $proc$libresoc.v:177815$12969 + assign { } { } + assign $1\src_l_r_src[5:0] 6'111111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[5:0] + end + attribute \src "libresoc.v:177819.13-177819.32" + process $proc$libresoc.v:177819$12970 + assign { } { } + assign $1\src_l_s_src[5:0] 6'000000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[5:0] + end + attribute \src "libresoc.v:177823.14-177823.43" + process $proc$libresoc.v:177823$12971 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:177827.14-177827.43" + process $proc$libresoc.v:177827$12972 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:177831.14-177831.43" + process $proc$libresoc.v:177831$12973 + assign { } { } + assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r2 $1\src_r2[63:0] + end + attribute \src "libresoc.v:177835.7-177835.20" + process $proc$libresoc.v:177835$12974 + assign { } { } + assign $1\src_r3[0:0] 1'0 + sync always + sync init + update \src_r3 $1\src_r3[0:0] + end + attribute \src "libresoc.v:177839.13-177839.26" + process $proc$libresoc.v:177839$12975 + assign { } { } + assign $1\src_r4[1:0] 2'00 + sync always + sync init + update \src_r4 $1\src_r4[1:0] + end + attribute \src "libresoc.v:177843.13-177843.26" + process $proc$libresoc.v:177843$12976 + assign { } { } + assign $1\src_r5[1:0] 2'00 + sync always + sync init + update \src_r5 $1\src_r5[1:0] + end + attribute \src "libresoc.v:177920.3-177921.39" + process $proc$libresoc.v:177920$12781 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:177922.3-177923.43" + process $proc$libresoc.v:177922$12782 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:177924.3-177925.29" + process $proc$libresoc.v:177924$12783 + assign { } { } + assign $0\src_r5[1:0] \src_r5$next + sync posedge \coresync_clk + update \src_r5 $0\src_r5[1:0] + end + attribute \src "libresoc.v:177926.3-177927.29" + process $proc$libresoc.v:177926$12784 + assign { } { } + assign $0\src_r4[1:0] \src_r4$next + sync posedge \coresync_clk + update \src_r4 $0\src_r4[1:0] + end + attribute \src "libresoc.v:177928.3-177929.29" + process $proc$libresoc.v:177928$12785 + assign { } { } + assign $0\src_r3[0:0] \src_r3$next + sync posedge \coresync_clk + update \src_r3 $0\src_r3[0:0] + end + attribute \src "libresoc.v:177930.3-177931.29" + process $proc$libresoc.v:177930$12786 + assign { } { } + assign $0\src_r2[63:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[63:0] + end + attribute \src "libresoc.v:177932.3-177933.29" + process $proc$libresoc.v:177932$12787 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:177934.3-177935.29" + process $proc$libresoc.v:177934$12788 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:177936.3-177937.47" + process $proc$libresoc.v:177936$12789 + assign { } { } + assign $0\data_r5__xer_ca[1:0] \data_r5__xer_ca$next + sync posedge \coresync_clk + update \data_r5__xer_ca $0\data_r5__xer_ca[1:0] + end + attribute \src "libresoc.v:177938.3-177939.53" + process $proc$libresoc.v:177938$12790 + assign { } { } + assign $0\data_r5__xer_ca_ok[0:0] \data_r5__xer_ca_ok$next + sync posedge \coresync_clk + update \data_r5__xer_ca_ok $0\data_r5__xer_ca_ok[0:0] + end + attribute \src "libresoc.v:177940.3-177941.47" + process $proc$libresoc.v:177940$12791 + assign { } { } + assign $0\data_r4__xer_ov[1:0] \data_r4__xer_ov$next + sync posedge \coresync_clk + update \data_r4__xer_ov $0\data_r4__xer_ov[1:0] + end + attribute \src "libresoc.v:177942.3-177943.53" + process $proc$libresoc.v:177942$12792 + assign { } { } + assign $0\data_r4__xer_ov_ok[0:0] \data_r4__xer_ov_ok$next + sync posedge \coresync_clk + update \data_r4__xer_ov_ok $0\data_r4__xer_ov_ok[0:0] + end + attribute \src "libresoc.v:177944.3-177945.47" + process $proc$libresoc.v:177944$12793 + assign { } { } + assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next + sync posedge \coresync_clk + update \data_r3__xer_so $0\data_r3__xer_so[0:0] + end + attribute \src "libresoc.v:177946.3-177947.53" + process $proc$libresoc.v:177946$12794 + assign { } { } + assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next + sync posedge \coresync_clk + update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] + end + attribute \src "libresoc.v:177948.3-177949.45" + process $proc$libresoc.v:177948$12795 + assign { } { } + assign $0\data_r2__fast1[63:0] \data_r2__fast1$next + sync posedge \coresync_clk + update \data_r2__fast1 $0\data_r2__fast1[63:0] + end + attribute \src "libresoc.v:177950.3-177951.51" + process $proc$libresoc.v:177950$12796 + assign { } { } + assign $0\data_r2__fast1_ok[0:0] \data_r2__fast1_ok$next + sync posedge \coresync_clk + update \data_r2__fast1_ok $0\data_r2__fast1_ok[0:0] + end + attribute \src "libresoc.v:177952.3-177953.43" + process $proc$libresoc.v:177952$12797 + assign { } { } + assign $0\data_r1__spr1[63:0] \data_r1__spr1$next + sync posedge \coresync_clk + update \data_r1__spr1 $0\data_r1__spr1[63:0] + end + attribute \src "libresoc.v:177954.3-177955.49" + process $proc$libresoc.v:177954$12798 + assign { } { } + assign $0\data_r1__spr1_ok[0:0] \data_r1__spr1_ok$next + sync posedge \coresync_clk + update \data_r1__spr1_ok $0\data_r1__spr1_ok[0:0] + end + attribute \src "libresoc.v:177956.3-177957.37" + process $proc$libresoc.v:177956$12799 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "libresoc.v:177958.3-177959.43" + process $proc$libresoc.v:177958$12800 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:177960.3-177961.69" + process $proc$libresoc.v:177960$12801 + assign { } { } + assign $0\alu_spr0_spr_op__insn_type[6:0] \alu_spr0_spr_op__insn_type$next + sync posedge \coresync_clk + update \alu_spr0_spr_op__insn_type $0\alu_spr0_spr_op__insn_type[6:0] + end + attribute \src "libresoc.v:177962.3-177963.65" + process $proc$libresoc.v:177962$12802 + assign { } { } + assign $0\alu_spr0_spr_op__fn_unit[11:0] \alu_spr0_spr_op__fn_unit$next + sync posedge \coresync_clk + update \alu_spr0_spr_op__fn_unit $0\alu_spr0_spr_op__fn_unit[11:0] + end + attribute \src "libresoc.v:177964.3-177965.59" + process $proc$libresoc.v:177964$12803 + assign { } { } + assign $0\alu_spr0_spr_op__insn[31:0] \alu_spr0_spr_op__insn$next + sync posedge \coresync_clk + update \alu_spr0_spr_op__insn $0\alu_spr0_spr_op__insn[31:0] + end + attribute \src "libresoc.v:177966.3-177967.67" + process $proc$libresoc.v:177966$12804 + assign { } { } + assign $0\alu_spr0_spr_op__is_32bit[0:0] \alu_spr0_spr_op__is_32bit$next + sync posedge \coresync_clk + update \alu_spr0_spr_op__is_32bit $0\alu_spr0_spr_op__is_32bit[0:0] + end + attribute \src "libresoc.v:177968.3-177969.39" + process $proc$libresoc.v:177968$12805 + assign { } { } + assign $0\req_l_r_req[5:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[5:0] + end + attribute \src "libresoc.v:177970.3-177971.39" + process $proc$libresoc.v:177970$12806 + assign { } { } + assign $0\req_l_s_req[5:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[5:0] + end + attribute \src "libresoc.v:177972.3-177973.39" + process $proc$libresoc.v:177972$12807 + assign { } { } + assign $0\src_l_r_src[5:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[5:0] + end + attribute \src "libresoc.v:177974.3-177975.39" + process $proc$libresoc.v:177974$12808 + assign { } { } + assign $0\src_l_s_src[5:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[5:0] + end + attribute \src "libresoc.v:177976.3-177977.39" + process $proc$libresoc.v:177976$12809 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:177978.3-177979.39" + process $proc$libresoc.v:177978$12810 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:177980.3-177981.39" + process $proc$libresoc.v:177980$12811 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:177982.3-177983.39" + process $proc$libresoc.v:177982$12812 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:177984.3-177985.41" + process $proc$libresoc.v:177984$12813 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:177986.3-177987.41" + process $proc$libresoc.v:177986$12814 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:177988.3-177989.37" + process $proc$libresoc.v:177988$12815 + assign { } { } + assign $0\prev_wr_go[5:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[5:0] + end + attribute \src "libresoc.v:177990.3-177991.40" + process $proc$libresoc.v:177990$12816 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_spr0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "libresoc.v:177992.3-177993.25" + process $proc$libresoc.v:177992$12817 + assign { } { } + assign $0\all_rd_dly[0:0] \$14 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "libresoc.v:178072.3-178081.6" + process $proc$libresoc.v:178072$12818 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:178073.5-178073.29" + switch \initial + attribute \src "libresoc.v:178073.9-178073.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$58 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$50 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "libresoc.v:178082.3-178090.6" + process $proc$libresoc.v:178082$12819 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$12820 $1\rok_l_s_rdok$next[0:0]$12821 + attribute \src "libresoc.v:178083.5-178083.29" + switch \initial + attribute \src "libresoc.v:178083.9-178083.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$12821 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$12821 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12820 + end + attribute \src "libresoc.v:178091.3-178099.6" + process $proc$libresoc.v:178091$12822 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$12823 $1\rok_l_r_rdok$next[0:0]$12824 + attribute \src "libresoc.v:178092.5-178092.29" + switch \initial + attribute \src "libresoc.v:178092.9-178092.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$12824 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$12824 \$68 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12823 + end + attribute \src "libresoc.v:178100.3-178108.6" + process $proc$libresoc.v:178100$12825 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$12826 $1\rst_l_s_rst$next[0:0]$12827 + attribute \src "libresoc.v:178101.5-178101.29" + switch \initial + attribute \src "libresoc.v:178101.9-178101.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$12827 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$12827 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12826 + end + attribute \src "libresoc.v:178109.3-178117.6" + process $proc$libresoc.v:178109$12828 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$12829 $1\rst_l_r_rst$next[0:0]$12830 + attribute \src "libresoc.v:178110.5-178110.29" + switch \initial + attribute \src "libresoc.v:178110.9-178110.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$12830 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$12830 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12829 + end + attribute \src "libresoc.v:178118.3-178126.6" + process $proc$libresoc.v:178118$12831 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$12832 $1\opc_l_s_opc$next[0:0]$12833 + attribute \src "libresoc.v:178119.5-178119.29" + switch \initial + attribute \src "libresoc.v:178119.9-178119.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$12833 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$12833 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12832 + end + attribute \src "libresoc.v:178127.3-178135.6" + process $proc$libresoc.v:178127$12834 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$12835 $1\opc_l_r_opc$next[0:0]$12836 + attribute \src "libresoc.v:178128.5-178128.29" + switch \initial + attribute \src "libresoc.v:178128.9-178128.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$12836 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$12836 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12835 + end + attribute \src "libresoc.v:178136.3-178144.6" + process $proc$libresoc.v:178136$12837 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[5:0]$12838 $1\src_l_s_src$next[5:0]$12839 + attribute \src "libresoc.v:178137.5-178137.29" + switch \initial + attribute \src "libresoc.v:178137.9-178137.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[5:0]$12839 6'000000 + case + assign $1\src_l_s_src$next[5:0]$12839 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[5:0]$12838 + end + attribute \src "libresoc.v:178145.3-178153.6" + process $proc$libresoc.v:178145$12840 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[5:0]$12841 $1\src_l_r_src$next[5:0]$12842 + attribute \src "libresoc.v:178146.5-178146.29" + switch \initial + attribute \src "libresoc.v:178146.9-178146.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[5:0]$12842 6'111111 + case + assign $1\src_l_r_src$next[5:0]$12842 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[5:0]$12841 + end + attribute \src "libresoc.v:178154.3-178162.6" + process $proc$libresoc.v:178154$12843 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[5:0]$12844 $1\req_l_s_req$next[5:0]$12845 + attribute \src "libresoc.v:178155.5-178155.29" + switch \initial + attribute \src "libresoc.v:178155.9-178155.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[5:0]$12845 6'000000 + case + assign $1\req_l_s_req$next[5:0]$12845 \$70 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[5:0]$12844 + end + attribute \src "libresoc.v:178163.3-178171.6" + process $proc$libresoc.v:178163$12846 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[5:0]$12847 $1\req_l_r_req$next[5:0]$12848 + attribute \src "libresoc.v:178164.5-178164.29" + switch \initial + attribute \src "libresoc.v:178164.9-178164.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[5:0]$12848 6'111111 + case + assign $1\req_l_r_req$next[5:0]$12848 \$72 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[5:0]$12847 + end + attribute \src "libresoc.v:178172.3-178184.6" + process $proc$libresoc.v:178172$12849 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_spr0_spr_op__fn_unit$next[11:0]$12850 $1\alu_spr0_spr_op__fn_unit$next[11:0]$12854 + assign $0\alu_spr0_spr_op__insn$next[31:0]$12851 $1\alu_spr0_spr_op__insn$next[31:0]$12855 + assign $0\alu_spr0_spr_op__insn_type$next[6:0]$12852 $1\alu_spr0_spr_op__insn_type$next[6:0]$12856 + assign $0\alu_spr0_spr_op__is_32bit$next[0:0]$12853 $1\alu_spr0_spr_op__is_32bit$next[0:0]$12857 + attribute \src "libresoc.v:178173.5-178173.29" + switch \initial + attribute \src "libresoc.v:178173.9-178173.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_spr0_spr_op__is_32bit$next[0:0]$12857 $1\alu_spr0_spr_op__insn$next[31:0]$12855 $1\alu_spr0_spr_op__fn_unit$next[11:0]$12854 $1\alu_spr0_spr_op__insn_type$next[6:0]$12856 } { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type } + case + assign $1\alu_spr0_spr_op__fn_unit$next[11:0]$12854 \alu_spr0_spr_op__fn_unit + assign $1\alu_spr0_spr_op__insn$next[31:0]$12855 \alu_spr0_spr_op__insn + assign $1\alu_spr0_spr_op__insn_type$next[6:0]$12856 \alu_spr0_spr_op__insn_type + assign $1\alu_spr0_spr_op__is_32bit$next[0:0]$12857 \alu_spr0_spr_op__is_32bit + end + sync always + update \alu_spr0_spr_op__fn_unit$next $0\alu_spr0_spr_op__fn_unit$next[11:0]$12850 + update \alu_spr0_spr_op__insn$next $0\alu_spr0_spr_op__insn$next[31:0]$12851 + update \alu_spr0_spr_op__insn_type$next $0\alu_spr0_spr_op__insn_type$next[6:0]$12852 + update \alu_spr0_spr_op__is_32bit$next $0\alu_spr0_spr_op__is_32bit$next[0:0]$12853 + end + attribute \src "libresoc.v:178185.3-178206.6" + process $proc$libresoc.v:178185$12858 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$12859 $2\data_r0__o$next[63:0]$12863 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$12860 $3\data_r0__o_ok$next[0:0]$12865 + attribute \src "libresoc.v:178186.5-178186.29" + switch \initial + attribute \src "libresoc.v:178186.9-178186.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$12862 $1\data_r0__o$next[63:0]$12861 } { \o_ok \alu_spr0_o } + case + assign $1\data_r0__o$next[63:0]$12861 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$12862 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$12864 $2\data_r0__o$next[63:0]$12863 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$12863 $1\data_r0__o$next[63:0]$12861 + assign $2\data_r0__o_ok$next[0:0]$12864 $1\data_r0__o_ok$next[0:0]$12862 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$12865 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$12865 $2\data_r0__o_ok$next[0:0]$12864 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$12859 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12860 + end + attribute \src "libresoc.v:178207.3-178228.6" + process $proc$libresoc.v:178207$12866 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__spr1$next[63:0]$12867 $2\data_r1__spr1$next[63:0]$12871 + assign { } { } + assign $0\data_r1__spr1_ok$next[0:0]$12868 $3\data_r1__spr1_ok$next[0:0]$12873 + attribute \src "libresoc.v:178208.5-178208.29" + switch \initial + attribute \src "libresoc.v:178208.9-178208.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__spr1_ok$next[0:0]$12870 $1\data_r1__spr1$next[63:0]$12869 } { \spr1_ok \alu_spr0_spr1 } + case + assign $1\data_r1__spr1$next[63:0]$12869 \data_r1__spr1 + assign $1\data_r1__spr1_ok$next[0:0]$12870 \data_r1__spr1_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__spr1_ok$next[0:0]$12872 $2\data_r1__spr1$next[63:0]$12871 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r1__spr1$next[63:0]$12871 $1\data_r1__spr1$next[63:0]$12869 + assign $2\data_r1__spr1_ok$next[0:0]$12872 $1\data_r1__spr1_ok$next[0:0]$12870 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__spr1_ok$next[0:0]$12873 1'0 + case + assign $3\data_r1__spr1_ok$next[0:0]$12873 $2\data_r1__spr1_ok$next[0:0]$12872 + end + sync always + update \data_r1__spr1$next $0\data_r1__spr1$next[63:0]$12867 + update \data_r1__spr1_ok$next $0\data_r1__spr1_ok$next[0:0]$12868 + end + attribute \src "libresoc.v:178229.3-178250.6" + process $proc$libresoc.v:178229$12874 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__fast1$next[63:0]$12875 $2\data_r2__fast1$next[63:0]$12879 + assign { } { } + assign $0\data_r2__fast1_ok$next[0:0]$12876 $3\data_r2__fast1_ok$next[0:0]$12881 + attribute \src "libresoc.v:178230.5-178230.29" + switch \initial + attribute \src "libresoc.v:178230.9-178230.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__fast1_ok$next[0:0]$12878 $1\data_r2__fast1$next[63:0]$12877 } { \fast1_ok \alu_spr0_fast1 } + case + assign $1\data_r2__fast1$next[63:0]$12877 \data_r2__fast1 + assign $1\data_r2__fast1_ok$next[0:0]$12878 \data_r2__fast1_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__fast1_ok$next[0:0]$12880 $2\data_r2__fast1$next[63:0]$12879 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r2__fast1$next[63:0]$12879 $1\data_r2__fast1$next[63:0]$12877 + assign $2\data_r2__fast1_ok$next[0:0]$12880 $1\data_r2__fast1_ok$next[0:0]$12878 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__fast1_ok$next[0:0]$12881 1'0 + case + assign $3\data_r2__fast1_ok$next[0:0]$12881 $2\data_r2__fast1_ok$next[0:0]$12880 + end + sync always + update \data_r2__fast1$next $0\data_r2__fast1$next[63:0]$12875 + update \data_r2__fast1_ok$next $0\data_r2__fast1_ok$next[0:0]$12876 + end + attribute \src "libresoc.v:178251.3-178272.6" + process $proc$libresoc.v:178251$12882 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r3__xer_so$next[0:0]$12883 $2\data_r3__xer_so$next[0:0]$12887 + assign { } { } + assign $0\data_r3__xer_so_ok$next[0:0]$12884 $3\data_r3__xer_so_ok$next[0:0]$12889 + attribute \src "libresoc.v:178252.5-178252.29" + switch \initial + attribute \src "libresoc.v:178252.9-178252.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r3__xer_so_ok$next[0:0]$12886 $1\data_r3__xer_so$next[0:0]$12885 } { \xer_so_ok \alu_spr0_xer_so } + case + assign $1\data_r3__xer_so$next[0:0]$12885 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$12886 \data_r3__xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r3__xer_so_ok$next[0:0]$12888 $2\data_r3__xer_so$next[0:0]$12887 } 2'00 + case + assign $2\data_r3__xer_so$next[0:0]$12887 $1\data_r3__xer_so$next[0:0]$12885 + assign $2\data_r3__xer_so_ok$next[0:0]$12888 $1\data_r3__xer_so_ok$next[0:0]$12886 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r3__xer_so_ok$next[0:0]$12889 1'0 + case + assign $3\data_r3__xer_so_ok$next[0:0]$12889 $2\data_r3__xer_so_ok$next[0:0]$12888 + end + sync always + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$12883 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$12884 + end + attribute \src "libresoc.v:178273.3-178294.6" + process $proc$libresoc.v:178273$12890 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r4__xer_ov$next[1:0]$12891 $2\data_r4__xer_ov$next[1:0]$12895 + assign { } { } + assign $0\data_r4__xer_ov_ok$next[0:0]$12892 $3\data_r4__xer_ov_ok$next[0:0]$12897 + attribute \src "libresoc.v:178274.5-178274.29" + switch \initial + attribute \src "libresoc.v:178274.9-178274.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r4__xer_ov_ok$next[0:0]$12894 $1\data_r4__xer_ov$next[1:0]$12893 } { \xer_ov_ok \alu_spr0_xer_ov } + case + assign $1\data_r4__xer_ov$next[1:0]$12893 \data_r4__xer_ov + assign $1\data_r4__xer_ov_ok$next[0:0]$12894 \data_r4__xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r4__xer_ov_ok$next[0:0]$12896 $2\data_r4__xer_ov$next[1:0]$12895 } 3'000 + case + assign $2\data_r4__xer_ov$next[1:0]$12895 $1\data_r4__xer_ov$next[1:0]$12893 + assign $2\data_r4__xer_ov_ok$next[0:0]$12896 $1\data_r4__xer_ov_ok$next[0:0]$12894 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r4__xer_ov_ok$next[0:0]$12897 1'0 + case + assign $3\data_r4__xer_ov_ok$next[0:0]$12897 $2\data_r4__xer_ov_ok$next[0:0]$12896 + end + sync always + update \data_r4__xer_ov$next $0\data_r4__xer_ov$next[1:0]$12891 + update \data_r4__xer_ov_ok$next $0\data_r4__xer_ov_ok$next[0:0]$12892 + end + attribute \src "libresoc.v:178295.3-178316.6" + process $proc$libresoc.v:178295$12898 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r5__xer_ca$next[1:0]$12899 $2\data_r5__xer_ca$next[1:0]$12903 + assign { } { } + assign $0\data_r5__xer_ca_ok$next[0:0]$12900 $3\data_r5__xer_ca_ok$next[0:0]$12905 + attribute \src "libresoc.v:178296.5-178296.29" + switch \initial + attribute \src "libresoc.v:178296.9-178296.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r5__xer_ca_ok$next[0:0]$12902 $1\data_r5__xer_ca$next[1:0]$12901 } { \xer_ca_ok \alu_spr0_xer_ca } + case + assign $1\data_r5__xer_ca$next[1:0]$12901 \data_r5__xer_ca + assign $1\data_r5__xer_ca_ok$next[0:0]$12902 \data_r5__xer_ca_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r5__xer_ca_ok$next[0:0]$12904 $2\data_r5__xer_ca$next[1:0]$12903 } 3'000 + case + assign $2\data_r5__xer_ca$next[1:0]$12903 $1\data_r5__xer_ca$next[1:0]$12901 + assign $2\data_r5__xer_ca_ok$next[0:0]$12904 $1\data_r5__xer_ca_ok$next[0:0]$12902 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r5__xer_ca_ok$next[0:0]$12905 1'0 + case + assign $3\data_r5__xer_ca_ok$next[0:0]$12905 $2\data_r5__xer_ca_ok$next[0:0]$12904 + end + sync always + update \data_r5__xer_ca$next $0\data_r5__xer_ca$next[1:0]$12899 + update \data_r5__xer_ca_ok$next $0\data_r5__xer_ca_ok$next[0:0]$12900 + end + attribute \src "libresoc.v:178317.3-178326.6" + process $proc$libresoc.v:178317$12906 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$12907 $1\src_r0$next[63:0]$12908 + attribute \src "libresoc.v:178318.5-178318.29" + switch \initial + attribute \src "libresoc.v:178318.9-178318.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$12908 \src1_i + case + assign $1\src_r0$next[63:0]$12908 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$12907 + end + attribute \src "libresoc.v:178327.3-178336.6" + process $proc$libresoc.v:178327$12909 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$12910 $1\src_r1$next[63:0]$12911 + attribute \src "libresoc.v:178328.5-178328.29" + switch \initial + attribute \src "libresoc.v:178328.9-178328.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$12911 \src2_i + case + assign $1\src_r1$next[63:0]$12911 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$12910 + end + attribute \src "libresoc.v:178337.3-178346.6" + process $proc$libresoc.v:178337$12912 + assign { } { } + assign { } { } + assign $0\src_r2$next[63:0]$12913 $1\src_r2$next[63:0]$12914 + attribute \src "libresoc.v:178338.5-178338.29" + switch \initial + attribute \src "libresoc.v:178338.9-178338.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[63:0]$12914 \src3_i + case + assign $1\src_r2$next[63:0]$12914 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[63:0]$12913 + end + attribute \src "libresoc.v:178347.3-178356.6" + process $proc$libresoc.v:178347$12915 + assign { } { } + assign { } { } + assign $0\src_r3$next[0:0]$12916 $1\src_r3$next[0:0]$12917 + attribute \src "libresoc.v:178348.5-178348.29" + switch \initial + attribute \src "libresoc.v:178348.9-178348.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r3$next[0:0]$12917 \src4_i + case + assign $1\src_r3$next[0:0]$12917 \src_r3 + end + sync always + update \src_r3$next $0\src_r3$next[0:0]$12916 + end + attribute \src "libresoc.v:178357.3-178366.6" + process $proc$libresoc.v:178357$12918 + assign { } { } + assign { } { } + assign $0\src_r4$next[1:0]$12919 $1\src_r4$next[1:0]$12920 + attribute \src "libresoc.v:178358.5-178358.29" + switch \initial + attribute \src "libresoc.v:178358.9-178358.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r4$next[1:0]$12920 \src5_i + case + assign $1\src_r4$next[1:0]$12920 \src_r4 + end + sync always + update \src_r4$next $0\src_r4$next[1:0]$12919 + end + attribute \src "libresoc.v:178367.3-178376.6" + process $proc$libresoc.v:178367$12921 + assign { } { } + assign { } { } + assign $0\src_r5$next[1:0]$12922 $1\src_r5$next[1:0]$12923 + attribute \src "libresoc.v:178368.5-178368.29" + switch \initial + attribute \src "libresoc.v:178368.9-178368.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r5$next[1:0]$12923 \src6_i + case + assign $1\src_r5$next[1:0]$12923 \src_r5 + end + sync always + update \src_r5$next $0\src_r5$next[1:0]$12922 + end + attribute \src "libresoc.v:178377.3-178385.6" + process $proc$libresoc.v:178377$12924 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$12925 $1\alui_l_r_alui$next[0:0]$12926 + attribute \src "libresoc.v:178378.5-178378.29" + switch \initial + attribute \src "libresoc.v:178378.9-178378.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$12926 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$12926 \$98 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12925 + end + attribute \src "libresoc.v:178386.3-178394.6" + process $proc$libresoc.v:178386$12927 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$12928 $1\alu_l_r_alu$next[0:0]$12929 + attribute \src "libresoc.v:178387.5-178387.29" + switch \initial + attribute \src "libresoc.v:178387.9-178387.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$12929 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$12929 \$100 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12928 + end + attribute \src "libresoc.v:178395.3-178404.6" + process $proc$libresoc.v:178395$12930 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:178396.5-178396.29" + switch \initial + attribute \src "libresoc.v:178396.9-178396.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$126 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__o + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "libresoc.v:178405.3-178414.6" + process $proc$libresoc.v:178405$12931 + assign { } { } + assign { } { } + assign $0\dest2_o[63:0] $1\dest2_o[63:0] + attribute \src "libresoc.v:178406.5-178406.29" + switch \initial + attribute \src "libresoc.v:178406.9-178406.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$128 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[63:0] \data_r1__spr1 + case + assign $1\dest2_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest2_o $0\dest2_o[63:0] + end + attribute \src "libresoc.v:178415.3-178424.6" + process $proc$libresoc.v:178415$12932 + assign { } { } + assign { } { } + assign $0\dest3_o[63:0] $1\dest3_o[63:0] + attribute \src "libresoc.v:178416.5-178416.29" + switch \initial + attribute \src "libresoc.v:178416.9-178416.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$130 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest3_o[63:0] \data_r2__fast1 + case + assign $1\dest3_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest3_o $0\dest3_o[63:0] + end + attribute \src "libresoc.v:178425.3-178434.6" + process $proc$libresoc.v:178425$12933 + assign { } { } + assign { } { } + assign $0\dest4_o[0:0] $1\dest4_o[0:0] + attribute \src "libresoc.v:178426.5-178426.29" + switch \initial + attribute \src "libresoc.v:178426.9-178426.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$132 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest4_o[0:0] \data_r3__xer_so + case + assign $1\dest4_o[0:0] 1'0 + end + sync always + update \dest4_o $0\dest4_o[0:0] + end + attribute \src "libresoc.v:178435.3-178444.6" + process $proc$libresoc.v:178435$12934 + assign { } { } + assign { } { } + assign $0\dest5_o[1:0] $1\dest5_o[1:0] + attribute \src "libresoc.v:178436.5-178436.29" + switch \initial + attribute \src "libresoc.v:178436.9-178436.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$134 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest5_o[1:0] \data_r4__xer_ov + case + assign $1\dest5_o[1:0] 2'00 + end + sync always + update \dest5_o $0\dest5_o[1:0] + end + attribute \src "libresoc.v:178445.3-178454.6" + process $proc$libresoc.v:178445$12935 + assign { } { } + assign { } { } + assign $0\dest6_o[1:0] $1\dest6_o[1:0] + attribute \src "libresoc.v:178446.5-178446.29" + switch \initial + attribute \src "libresoc.v:178446.9-178446.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$136 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest6_o[1:0] \data_r5__xer_ca + case + assign $1\dest6_o[1:0] 2'00 + end + sync always + update \dest6_o $0\dest6_o[1:0] + end + attribute \src "libresoc.v:178455.3-178463.6" + process $proc$libresoc.v:178455$12936 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[5:0]$12937 $1\prev_wr_go$next[5:0]$12938 + attribute \src "libresoc.v:178456.5-178456.29" + switch \initial + attribute \src "libresoc.v:178456.9-178456.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[5:0]$12938 6'000000 + case + assign $1\prev_wr_go$next[5:0]$12938 \$24 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[5:0]$12937 + end + connect \$9 $not$libresoc.v:177854$12715_Y + connect \$100 $and$libresoc.v:177855$12716_Y + connect \$102 $and$libresoc.v:177856$12717_Y + connect \$104 $and$libresoc.v:177857$12718_Y + connect \$106 $not$libresoc.v:177858$12719_Y + connect \$108 $and$libresoc.v:177859$12720_Y + connect \$110 $and$libresoc.v:177860$12721_Y + connect \$112 $and$libresoc.v:177861$12722_Y + connect \$114 $and$libresoc.v:177862$12723_Y + connect \$116 $and$libresoc.v:177863$12724_Y + connect \$118 $and$libresoc.v:177864$12725_Y + connect \$11 $or$libresoc.v:177865$12726_Y + connect \$120 $and$libresoc.v:177866$12727_Y + connect \$122 $and$libresoc.v:177867$12728_Y + connect \$124 $and$libresoc.v:177868$12729_Y + connect \$126 $and$libresoc.v:177869$12730_Y + connect \$128 $and$libresoc.v:177870$12731_Y + connect \$8 $reduce_and$libresoc.v:177871$12732_Y + connect \$130 $and$libresoc.v:177872$12733_Y + connect \$132 $and$libresoc.v:177873$12734_Y + connect \$134 $and$libresoc.v:177874$12735_Y + connect \$136 $and$libresoc.v:177875$12736_Y + connect \$14 $and$libresoc.v:177876$12737_Y + connect \$16 $not$libresoc.v:177877$12738_Y + connect \$18 $and$libresoc.v:177878$12739_Y + connect \$20 $not$libresoc.v:177879$12740_Y + connect \$22 $and$libresoc.v:177880$12741_Y + connect \$24 $and$libresoc.v:177881$12742_Y + connect \$28 $not$libresoc.v:177882$12743_Y + connect \$30 $and$libresoc.v:177883$12744_Y + connect \$27 $reduce_or$libresoc.v:177884$12745_Y + connect \$26 $not$libresoc.v:177885$12746_Y + connect \$34 $and$libresoc.v:177886$12747_Y + connect \$36 $reduce_or$libresoc.v:177887$12748_Y + connect \$38 $reduce_or$libresoc.v:177888$12749_Y + connect \$40 $or$libresoc.v:177889$12750_Y + connect \$42 $not$libresoc.v:177890$12751_Y + connect \$44 $and$libresoc.v:177891$12752_Y + connect \$46 $and$libresoc.v:177892$12753_Y + connect \$48 $eq$libresoc.v:177893$12754_Y + connect \$50 $and$libresoc.v:177894$12755_Y + connect \$52 $eq$libresoc.v:177895$12756_Y + connect \$54 $and$libresoc.v:177896$12757_Y + connect \$56 $and$libresoc.v:177897$12758_Y + connect \$58 $and$libresoc.v:177898$12759_Y + connect \$60 $or$libresoc.v:177899$12760_Y + connect \$62 $or$libresoc.v:177900$12761_Y + connect \$64 $or$libresoc.v:177901$12762_Y + connect \$66 $or$libresoc.v:177902$12763_Y + connect \$68 $and$libresoc.v:177903$12764_Y + connect \$6 $and$libresoc.v:177904$12765_Y + connect \$70 $and$libresoc.v:177905$12766_Y + connect \$72 $or$libresoc.v:177906$12767_Y + connect \$74 $and$libresoc.v:177907$12768_Y + connect \$76 $and$libresoc.v:177908$12769_Y + connect \$78 $and$libresoc.v:177909$12770_Y + connect \$80 $and$libresoc.v:177910$12771_Y + connect \$82 $and$libresoc.v:177911$12772_Y + connect \$84 $and$libresoc.v:177912$12773_Y + connect \$86 $ternary$libresoc.v:177913$12774_Y + connect \$88 $ternary$libresoc.v:177914$12775_Y + connect \$90 $ternary$libresoc.v:177915$12776_Y + connect \$92 $ternary$libresoc.v:177916$12777_Y + connect \$94 $ternary$libresoc.v:177917$12778_Y + connect \$96 $ternary$libresoc.v:177918$12779_Y + connect \$98 $and$libresoc.v:177919$12780_Y + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \cu_wr__rel_o \$124 + connect \cu_rd__rel_o \$108 + connect \cu_busy_o \opc_l_q_opc + connect \alu_l_s_alu \all_rd_pulse + connect \alu_spr0_n_ready_i \alu_l_q_alu + connect \alui_l_s_alui \all_rd_pulse + connect \alu_spr0_p_valid_i \alui_l_q_alui + connect \alu_spr0_xer_ca$5 \$96 + connect \alu_spr0_xer_ov$4 \$94 + connect \alu_spr0_xer_so$3 \$92 + connect \alu_spr0_fast1$2 \$90 + connect \alu_spr0_spr1$1 \$88 + connect \alu_spr0_ra \$86 + connect \cu_wrmask_o { \$84 \$82 \$80 \$78 \$76 \$74 } + connect \reset_r \$66 + connect \reset_w \$64 + connect \rst_r \$62 + connect \reset \$60 + connect \wr_any \$40 + connect \cu_done_o \$34 + connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse } + connect \alu_pulse \alu_done_rise + connect \alu_done_rise \$22 + connect \alu_done_dly$next \alu_done + connect \alu_done \alu_spr0_n_valid_o + connect \all_rd_pulse \all_rd_rise + connect \all_rd_rise \$18 + connect \all_rd_dly$next \all_rd + connect \all_rd \$14 +end +attribute \src "libresoc.v:178499.1-179013.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.spr_main" +attribute \generator "nMigen" +module \spr_main + attribute \src "libresoc.v:178766.3-178781.6" + wire width 64 $0\fast1$7[63:0]$12985 + attribute \src "libresoc.v:178843.3-178858.6" + wire $0\fast1_ok[0:0] + attribute \src "libresoc.v:178500.7-178500.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:178801.3-178842.6" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:178801.3-178842.6" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:178991.3-179009.6" + wire width 64 $0\spr1$6[63:0]$13010 + attribute \src "libresoc.v:178782.3-178800.6" + wire $0\spr1_ok[0:0] + attribute \src "libresoc.v:178946.3-178969.6" + wire width 2 $0\xer_ca$10[1:0]$13004 + attribute \src "libresoc.v:178970.3-178990.6" + wire $0\xer_ca_ok[0:0] + attribute \src "libresoc.v:178901.3-178924.6" + wire width 2 $0\xer_ov$9[1:0]$12998 + attribute \src "libresoc.v:178925.3-178945.6" + wire $0\xer_ov_ok[0:0] + attribute \src "libresoc.v:178859.3-178879.6" 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attribute \src "libresoc.v:178946.3-178969.6" + wire width 2 $3\xer_ca$10[1:0]$13007 + attribute \src "libresoc.v:178970.3-178990.6" + wire $3\xer_ca_ok[0:0] + attribute \src "libresoc.v:178901.3-178924.6" + wire width 2 $3\xer_ov$9[1:0]$13001 + attribute \src "libresoc.v:178925.3-178945.6" + wire $3\xer_ov_ok[0:0] + attribute \src "libresoc.v:178859.3-178879.6" + wire $3\xer_so$8[0:0]$12995 + attribute \src "libresoc.v:178880.3-178900.6" + wire $3\xer_so_ok[0:0] + attribute \src "libresoc.v:178759.18-178759.106" + wire $eq$libresoc.v:178759$12977_Y + attribute \src "libresoc.v:178760.18-178760.106" + wire $eq$libresoc.v:178760$12978_Y + attribute \src "libresoc.v:178761.18-178761.106" + wire $eq$libresoc.v:178761$12979_Y + attribute \src "libresoc.v:178762.18-178762.106" + wire $eq$libresoc.v:178762$12980_Y + attribute \src "libresoc.v:178763.18-178763.106" + wire $eq$libresoc.v:178763$12981_Y + attribute \src "libresoc.v:178764.18-178764.106" + wire $eq$libresoc.v:178764$12982_Y + attribute \src "libresoc.v:178765.18-178765.106" + wire $eq$libresoc.v:178765$12983_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 7 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 20 \fast1$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 21 \fast1_ok + attribute \src "libresoc.v:178500.7-178500.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 28 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 11 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 16 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 17 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 5 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:42" + wire width 10 \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 6 \spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 18 \spr1$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 19 \spr1_ok + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \spr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 13 \spr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 3 \spr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 14 \spr_op__insn$4 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \spr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 12 \spr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \spr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \spr_op__is_32bit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 10 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 26 \xer_ca$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 27 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 9 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 24 \xer_ov$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 25 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 8 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 22 \xer_so$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 23 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + cell $eq $eq$libresoc.v:178759$12977 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $eq$libresoc.v:178759$12977_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + cell $eq $eq$libresoc.v:178760$12978 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $eq$libresoc.v:178760$12978_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + cell $eq $eq$libresoc.v:178761$12979 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $eq$libresoc.v:178761$12979_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + cell $eq $eq$libresoc.v:178762$12980 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $eq$libresoc.v:178762$12980_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + cell $eq $eq$libresoc.v:178763$12981 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $eq$libresoc.v:178763$12981_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + cell $eq $eq$libresoc.v:178764$12982 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $eq$libresoc.v:178764$12982_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" + cell $eq $eq$libresoc.v:178765$12983 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $eq$libresoc.v:178765$12983_Y + end + attribute \src "libresoc.v:178500.7-178500.20" + process $proc$libresoc.v:178500$13013 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:178766.3-178781.6" + process $proc$libresoc.v:178766$12984 + assign { } { } + assign { } { } + assign $0\fast1$7[63:0]$12985 $1\fast1$7[63:0]$12986 + attribute \src "libresoc.v:178767.5-178767.29" + switch \initial + attribute \src "libresoc.v:178767.9-178767.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\fast1$7[63:0]$12986 $2\fast1$7[63:0]$12987 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\fast1$7[63:0]$12987 \ra + case + assign $2\fast1$7[63:0]$12987 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\fast1$7[63:0]$12986 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fast1$7 $0\fast1$7[63:0]$12985 + end + attribute \src "libresoc.v:178782.3-178800.6" + process $proc$libresoc.v:178782$12988 + assign { } { } + assign { } { } + assign $0\spr1_ok[0:0] $1\spr1_ok[0:0] + attribute \src "libresoc.v:178783.5-178783.29" + switch \initial + attribute \src "libresoc.v:178783.9-178783.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\spr1_ok[0:0] $2\spr1_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign $2\spr1_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\spr1_ok[0:0] 1'1 + end + case + assign $1\spr1_ok[0:0] 1'0 + end + sync always + update \spr1_ok $0\spr1_ok[0:0] + end + attribute \src "libresoc.v:178801.3-178842.6" + process $proc$libresoc.v:178801$12989 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o_ok[0:0] $1\o_ok[0:0] + assign $0\o[63:0] $1\o[63:0] + attribute \src "libresoc.v:178802.5-178802.29" + switch \initial + attribute \src "libresoc.v:178802.9-178802.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0101110 + assign { } { } + assign { } { } + assign $1\o_ok[0:0] 1'1 + assign $1\o[63:0] $2\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:77" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 , 10'0100001100 + assign { } { } + assign $2\o[63:0] [17:0] \fast1 [17:0] + assign $2\o[63:0] [63:18] $3\o[63:18] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" + switch \$23 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\o[63:18] [45:14] 0 + assign $3\o[63:18] [10:2] 9'000000000 + assign $3\o[63:18] [13] \xer_so + assign $3\o[63:18] [12] \xer_ov [0] + assign $3\o[63:18] [1] \xer_ov [1] + assign $3\o[63:18] [11] \xer_ca [0] + assign $3\o[63:18] [0] \xer_ca [1] + case + assign $3\o[63:18] \fast1 [63:18] + end + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign $2\o[63:0] [63:32] 0 + assign $2\o[63:0] [31:0] \fast1 [63:32] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\o[63:0] \spr1 + end + case + assign $1\o_ok[0:0] 1'0 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \o_ok $0\o_ok[0:0] + update \o $0\o[63:0] + end + attribute \src "libresoc.v:178843.3-178858.6" + process $proc$libresoc.v:178843$12990 + assign { } { } + assign { } { } + assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] + attribute \src "libresoc.v:178844.5-178844.29" + switch \initial + attribute \src "libresoc.v:178844.9-178844.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\fast1_ok[0:0] $2\fast1_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\fast1_ok[0:0] 1'1 + case + assign $2\fast1_ok[0:0] 1'0 + end + case + assign $1\fast1_ok[0:0] 1'0 + end + sync always + update \fast1_ok $0\fast1_ok[0:0] + end + attribute \src "libresoc.v:178859.3-178879.6" + process $proc$libresoc.v:178859$12991 + assign { } { } + assign { } { } + assign $0\xer_so$8[0:0]$12992 $1\xer_so$8[0:0]$12993 + attribute \src "libresoc.v:178860.5-178860.29" + switch \initial + attribute \src "libresoc.v:178860.9-178860.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\xer_so$8[0:0]$12993 $2\xer_so$8[0:0]$12994 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\xer_so$8[0:0]$12994 $3\xer_so$8[0:0]$12995 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + switch \$11 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\xer_so$8[0:0]$12995 \ra [31] + case + assign $3\xer_so$8[0:0]$12995 1'0 + end + case + assign $2\xer_so$8[0:0]$12994 1'0 + end + case + assign $1\xer_so$8[0:0]$12993 1'0 + end + sync always + update \xer_so$8 $0\xer_so$8[0:0]$12992 + end + attribute \src "libresoc.v:178880.3-178900.6" + process $proc$libresoc.v:178880$12996 + assign { } { } + assign { } { } + assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] + attribute \src "libresoc.v:178881.5-178881.29" + switch \initial + attribute \src "libresoc.v:178881.9-178881.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\xer_so_ok[0:0] $2\xer_so_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\xer_so_ok[0:0] $3\xer_so_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\xer_so_ok[0:0] 1'1 + case + assign $3\xer_so_ok[0:0] 1'0 + end + case + assign $2\xer_so_ok[0:0] 1'0 + end + case + assign $1\xer_so_ok[0:0] 1'0 + end + sync always + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:178901.3-178924.6" + process $proc$libresoc.v:178901$12997 + assign { } { } + assign { } { } + assign $0\xer_ov$9[1:0]$12998 $1\xer_ov$9[1:0]$12999 + attribute \src "libresoc.v:178902.5-178902.29" + switch \initial + attribute \src "libresoc.v:178902.9-178902.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\xer_ov$9[1:0]$12999 $2\xer_ov$9[1:0]$13000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\xer_ov$9[1:0]$13000 $3\xer_ov$9[1:0]$13001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\xer_ov$9[1:0]$13001 [0] \ra [30] + assign $3\xer_ov$9[1:0]$13001 [1] \ra [19] + case + assign $3\xer_ov$9[1:0]$13001 2'00 + end + case + assign $2\xer_ov$9[1:0]$13000 2'00 + end + case + assign $1\xer_ov$9[1:0]$12999 2'00 + end + sync always + update \xer_ov$9 $0\xer_ov$9[1:0]$12998 + end + attribute \src "libresoc.v:178925.3-178945.6" + process $proc$libresoc.v:178925$13002 + assign { } { } + assign { } { } + assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:178926.5-178926.29" + switch \initial + attribute \src "libresoc.v:178926.9-178926.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\xer_ov_ok[0:0] $2\xer_ov_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\xer_ov_ok[0:0] $3\xer_ov_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + switch \$17 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\xer_ov_ok[0:0] 1'1 + case + assign $3\xer_ov_ok[0:0] 1'0 + end + case + assign $2\xer_ov_ok[0:0] 1'0 + end + case + assign $1\xer_ov_ok[0:0] 1'0 + end + sync always + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:178946.3-178969.6" + process $proc$libresoc.v:178946$13003 + assign { } { } + assign { } { } + assign $0\xer_ca$10[1:0]$13004 $1\xer_ca$10[1:0]$13005 + attribute \src "libresoc.v:178947.5-178947.29" + switch \initial + attribute \src "libresoc.v:178947.9-178947.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\xer_ca$10[1:0]$13005 $2\xer_ca$10[1:0]$13006 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\xer_ca$10[1:0]$13006 $3\xer_ca$10[1:0]$13007 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\xer_ca$10[1:0]$13007 [0] \ra [29] + assign $3\xer_ca$10[1:0]$13007 [1] \ra [18] + case + assign $3\xer_ca$10[1:0]$13007 2'00 + end + case + assign $2\xer_ca$10[1:0]$13006 2'00 + end + case + assign $1\xer_ca$10[1:0]$13005 2'00 + end + sync always + update \xer_ca$10 $0\xer_ca$10[1:0]$13004 + end + attribute \src "libresoc.v:178970.3-178990.6" + process $proc$libresoc.v:178970$13008 + assign { } { } + assign { } { } + assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0] + attribute \src "libresoc.v:178971.5-178971.29" + switch \initial + attribute \src "libresoc.v:178971.9-178971.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\xer_ca_ok[0:0] $2\xer_ca_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\xer_ca_ok[0:0] $3\xer_ca_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + switch \$21 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\xer_ca_ok[0:0] 1'1 + case + assign $3\xer_ca_ok[0:0] 1'0 + end + case + assign $2\xer_ca_ok[0:0] 1'0 + end + case + assign $1\xer_ca_ok[0:0] 1'0 + end + sync always + update \xer_ca_ok $0\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:178991.3-179009.6" + process $proc$libresoc.v:178991$13009 + assign { } { } + assign { } { } + assign $0\spr1$6[63:0]$13010 $1\spr1$6[63:0]$13011 + attribute \src "libresoc.v:178992.5-178992.29" + switch \initial + attribute \src "libresoc.v:178992.9-178992.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\spr1$6[63:0]$13011 $2\spr1$6[63:0]$13012 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign $2\spr1$6[63:0]$13012 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\spr1$6[63:0]$13012 \ra + end + case + assign $1\spr1$6[63:0]$13011 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \spr1$6 $0\spr1$6[63:0]$13010 + end + connect \$11 $eq$libresoc.v:178759$12977_Y + connect \$13 $eq$libresoc.v:178760$12978_Y + connect \$15 $eq$libresoc.v:178761$12979_Y + connect \$17 $eq$libresoc.v:178762$12980_Y + connect \$19 $eq$libresoc.v:178763$12981_Y + connect \$21 $eq$libresoc.v:178764$12982_Y + connect \$23 $eq$libresoc.v:178765$12983_Y + connect { \spr_op__is_32bit$5 \spr_op__insn$4 \spr_op__fn_unit$3 \spr_op__insn_type$2 } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } + connect \muxid$1 \muxid + connect \spr { \spr_op__insn [15:11] \spr_op__insn [20:16] } +end +attribute \src "libresoc.v:179017.1-179832.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a.sprmap" +attribute \generator "nMigen" +module \sprmap + attribute \src "libresoc.v:179144.3-179174.6" + wire width 3 $0\fast_o[2:0] + attribute \src "libresoc.v:179175.3-179205.6" + wire $0\fast_o_ok[0:0] + attribute \src "libresoc.v:179018.7-179018.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:179206.3-179518.6" + wire width 10 $0\spr_o[9:0] + attribute \src "libresoc.v:179519.3-179831.6" + wire $0\spr_o_ok[0:0] + attribute \src "libresoc.v:179144.3-179174.6" + wire width 3 $1\fast_o[2:0] + attribute \src "libresoc.v:179175.3-179205.6" + wire $1\fast_o_ok[0:0] + attribute \src "libresoc.v:179206.3-179518.6" + wire width 10 $1\spr_o[9:0] + attribute \src "libresoc.v:179519.3-179831.6" + wire $1\spr_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 3 \fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \fast_o_ok + attribute \src "libresoc.v:179018.7-179018.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62" + wire width 10 input 5 \spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 output 1 \spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \spr_o_ok + attribute \src "libresoc.v:179018.7-179018.20" + process $proc$libresoc.v:179018$13018 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:179144.3-179174.6" + process $proc$libresoc.v:179144$13014 + assign { } { } + assign { } { } + assign $0\fast_o[2:0] $1\fast_o[2:0] + attribute \src "libresoc.v:179145.5-179145.29" + switch \initial + attribute \src "libresoc.v:179145.9-179145.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000001 + assign { } { } + assign $1\fast_o[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 + assign { } { } + assign $1\fast_o[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 + assign { } { } + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign { } { } + assign $1\fast_o[2:0] 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 + assign { } { } + assign $1\fast_o[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign { } { } + assign $1\fast_o[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign { } { } + assign $1\fast_o[2:0] 3'111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 + assign { } { } + assign $1\fast_o[2:0] 3'010 + case + assign $1\fast_o[2:0] 3'000 + end + sync always + update \fast_o $0\fast_o[2:0] + end + attribute \src "libresoc.v:179175.3-179205.6" + process $proc$libresoc.v:179175$13015 + assign { } { } + assign { } { } + assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] + attribute \src "libresoc.v:179176.5-179176.29" + switch \initial + attribute \src "libresoc.v:179176.9-179176.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000001 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + case + assign $1\fast_o_ok[0:0] 1'0 + end + sync always + update \fast_o_ok $0\fast_o_ok[0:0] + end + attribute \src "libresoc.v:179206.3-179518.6" + process $proc$libresoc.v:179206$13016 + assign { } { } + assign { } { } + assign $0\spr_o[9:0] $1\spr_o[9:0] + attribute \src "libresoc.v:179207.5-179207.29" + switch \initial + attribute \src "libresoc.v:179207.9-179207.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000000001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 + assign { } { } + assign $1\spr_o[9:0] 10'0000000100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000000111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 + assign { } { } + assign $1\spr_o[9:0] 10'0000001011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000001101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 + assign { } { } + assign $1\spr_o[9:0] 10'0000001110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 + assign { } { } + assign $1\spr_o[9:0] 10'0000001111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\spr_o[9:0] 10'0000010000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 + assign { } { } + assign $1\spr_o[9:0] 10'0000010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000010010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 + assign { } { } + assign $1\spr_o[9:0] 10'0000010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 + assign { } { } + assign $1\spr_o[9:0] 10'0000011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 + assign { } { } + assign $1\spr_o[9:0] 10'0000011001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000011010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 + assign { } { } + assign $1\spr_o[9:0] 10'0000011011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 + assign { } { } + assign $1\spr_o[9:0] 10'0000011100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 + assign { } { } + assign $1\spr_o[9:0] 10'0000011101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 + assign { } { } + assign $1\spr_o[9:0] 10'0000011110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000011111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 + assign { } { } + assign $1\spr_o[9:0] 10'0000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000100001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign { } { } + assign $1\spr_o[9:0] 10'0000100011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000100101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 + assign { } { } + assign $1\spr_o[9:0] 10'0000101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 + assign { } { } + assign $1\spr_o[9:0] 10'0000101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 + assign { } { } + assign $1\spr_o[9:0] 10'0000101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 + assign { } { } + assign $1\spr_o[9:0] 10'0000101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000101101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 + assign { } { } + assign $1\spr_o[9:0] 10'0000101110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 + assign { } { } + assign $1\spr_o[9:0] 10'0000101111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 + assign { } { } + assign $1\spr_o[9:0] 10'0000110000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 + assign { } { } + assign $1\spr_o[9:0] 10'0000110001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 + assign { } { } + assign $1\spr_o[9:0] 10'0000110010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 + assign { } { } + assign $1\spr_o[9:0] 10'0000110011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 + assign { } { } + assign $1\spr_o[9:0] 10'0000110100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 + assign { } { } + assign $1\spr_o[9:0] 10'0000110101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 + assign { } { } + assign $1\spr_o[9:0] 10'0000110110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000110111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 + assign { } { } + assign $1\spr_o[9:0] 10'0000111000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000111001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000111010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000111011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000111100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000111101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000111110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000111111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 + assign { } { } + assign $1\spr_o[9:0] 10'0001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 + assign { } { } + assign $1\spr_o[9:0] 10'0001000001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 + assign { } { } + assign $1\spr_o[9:0] 10'0001000010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 + assign { } { } + assign $1\spr_o[9:0] 10'0001000011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 + assign { } { } + assign $1\spr_o[9:0] 10'0001000100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 + assign { } { } + assign $1\spr_o[9:0] 10'0001000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 + assign { } { } + assign $1\spr_o[9:0] 10'0001000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 + assign { } { } + assign $1\spr_o[9:0] 10'0001000111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 + assign { } { } + assign $1\spr_o[9:0] 10'0001001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 + assign { } { } + assign $1\spr_o[9:0] 10'0001001001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 + assign { } { } + assign $1\spr_o[9:0] 10'0001001010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 + assign { } { } + assign $1\spr_o[9:0] 10'0001001011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 + assign { } { } + assign $1\spr_o[9:0] 10'0001001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 + assign { } { } + assign $1\spr_o[9:0] 10'0001001101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 + assign { } { } + assign $1\spr_o[9:0] 10'0001001110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 + assign { } { } + assign $1\spr_o[9:0] 10'0001001111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 + assign { } { } + assign $1\spr_o[9:0] 10'0001010000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 + assign { } { } + assign $1\spr_o[9:0] 10'0001010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 + assign { } { } + assign $1\spr_o[9:0] 10'0001010010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 + assign { } { } + assign $1\spr_o[9:0] 10'0001010011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 + assign { } { } + assign $1\spr_o[9:0] 10'0001010100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 + assign { } { } + assign $1\spr_o[9:0] 10'0001010101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 + assign { } { } + assign $1\spr_o[9:0] 10'0001010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 + assign { } { } + assign $1\spr_o[9:0] 10'0001010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 + assign { } { } + assign $1\spr_o[9:0] 10'0001011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 + assign { } { } + assign $1\spr_o[9:0] 10'0001011001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 + assign { } { } + assign $1\spr_o[9:0] 10'0001011010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 + assign { } { } + assign $1\spr_o[9:0] 10'0001011011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 + assign { } { } + assign $1\spr_o[9:0] 10'0001011100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 + assign { } { } + assign $1\spr_o[9:0] 10'0001011101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 + assign { } { } + assign $1\spr_o[9:0] 10'0001011110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100101 + assign { } { } + assign $1\spr_o[9:0] 10'0001011111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 + assign { } { } + assign $1\spr_o[9:0] 10'0001100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 + assign { } { } + assign $1\spr_o[9:0] 10'0001100001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 + assign { } { } + assign $1\spr_o[9:0] 10'0001100010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 + assign { } { } + assign $1\spr_o[9:0] 10'0001100011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 + assign { } { } + assign $1\spr_o[9:0] 10'0001100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110000 + assign { } { } + assign $1\spr_o[9:0] 10'0001100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110111 + assign { } { } + assign $1\spr_o[9:0] 10'0001100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010000 + assign { } { } + assign $1\spr_o[9:0] 10'0001101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010001 + assign { } { } + assign $1\spr_o[9:0] 10'0001101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010111 + assign { } { } + assign $1\spr_o[9:0] 10'0001101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000000 + assign { } { } + assign $1\spr_o[9:0] 10'0001101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000010 + assign { } { } + assign $1\spr_o[9:0] 10'0001101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1111111111 + assign { } { } + assign $1\spr_o[9:0] 10'0001101101 + case + assign $1\spr_o[9:0] 10'0000000000 + end + sync always + update \spr_o $0\spr_o[9:0] + end + attribute \src "libresoc.v:179519.3-179831.6" + process $proc$libresoc.v:179519$13017 + assign { } { } + assign { } { } + assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] + attribute \src "libresoc.v:179520.5-179520.29" + switch \initial + attribute \src "libresoc.v:179520.9-179520.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1111111111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + case + assign $1\spr_o_ok[0:0] 1'0 + end + sync always + update \spr_o_ok $0\spr_o_ok[0:0] + end +end +attribute \src "libresoc.v:179836.1-180651.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o.sprmap" +attribute \generator "nMigen" +module \sprmap$212 + attribute \src "libresoc.v:179963.3-179993.6" + wire width 3 $0\fast_o[2:0] + attribute \src "libresoc.v:179994.3-180024.6" + wire $0\fast_o_ok[0:0] + attribute \src "libresoc.v:179837.7-179837.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:180025.3-180337.6" + wire width 10 $0\spr_o[9:0] + attribute \src "libresoc.v:180338.3-180650.6" + wire $0\spr_o_ok[0:0] + attribute \src "libresoc.v:179963.3-179993.6" + wire width 3 $1\fast_o[2:0] + attribute \src "libresoc.v:179994.3-180024.6" + wire $1\fast_o_ok[0:0] + attribute \src "libresoc.v:180025.3-180337.6" + wire width 10 $1\spr_o[9:0] + attribute \src "libresoc.v:180338.3-180650.6" + wire $1\spr_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 3 \fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \fast_o_ok + attribute \src "libresoc.v:179837.7-179837.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62" + wire width 10 input 5 \spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 output 1 \spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \spr_o_ok + attribute \src "libresoc.v:179837.7-179837.20" + process $proc$libresoc.v:179837$13023 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:179963.3-179993.6" + process $proc$libresoc.v:179963$13019 + assign { } { } + assign { } { } + assign $0\fast_o[2:0] $1\fast_o[2:0] + attribute \src "libresoc.v:179964.5-179964.29" + switch \initial + attribute \src "libresoc.v:179964.9-179964.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000001 + assign { } { } + assign $1\fast_o[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 + assign { } { } + assign $1\fast_o[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 + assign { } { } + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign { } { } + assign $1\fast_o[2:0] 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 + assign { } { } + assign $1\fast_o[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign { } { } + assign $1\fast_o[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign { } { } + assign $1\fast_o[2:0] 3'111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 + assign { } { } + assign $1\fast_o[2:0] 3'010 + case + assign $1\fast_o[2:0] 3'000 + end + sync always + update \fast_o $0\fast_o[2:0] + end + attribute \src "libresoc.v:179994.3-180024.6" + process $proc$libresoc.v:179994$13020 + assign { } { } + assign { } { } + assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] + attribute \src "libresoc.v:179995.5-179995.29" + switch \initial + attribute \src "libresoc.v:179995.9-179995.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000001 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + case + assign $1\fast_o_ok[0:0] 1'0 + end + sync always + update \fast_o_ok $0\fast_o_ok[0:0] + end + attribute \src "libresoc.v:180025.3-180337.6" + process $proc$libresoc.v:180025$13021 + assign { } { } + assign { } { } + assign $0\spr_o[9:0] $1\spr_o[9:0] + attribute \src "libresoc.v:180026.5-180026.29" + switch \initial + attribute \src "libresoc.v:180026.9-180026.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000000001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 + assign { } { } + assign $1\spr_o[9:0] 10'0000000100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000000111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 + assign { } { } + assign $1\spr_o[9:0] 10'0000001011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000001101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 + assign { } { } + assign $1\spr_o[9:0] 10'0000001110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 + assign { } { } + assign $1\spr_o[9:0] 10'0000001111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\spr_o[9:0] 10'0000010000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 + assign { } { } + assign $1\spr_o[9:0] 10'0000010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000010010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 + assign { } { } + assign $1\spr_o[9:0] 10'0000010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 + assign { } { } + assign $1\spr_o[9:0] 10'0000011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 + assign { } { } + assign $1\spr_o[9:0] 10'0000011001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000011010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 + assign { } { } + assign $1\spr_o[9:0] 10'0000011011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 + assign { } { } + assign $1\spr_o[9:0] 10'0000011100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 + assign { } { } + assign $1\spr_o[9:0] 10'0000011101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 + assign { } { } + assign $1\spr_o[9:0] 10'0000011110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000011111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 + assign { } { } + assign $1\spr_o[9:0] 10'0000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000100001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign { } { } + assign $1\spr_o[9:0] 10'0000100011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000100101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 + assign { } { } + assign $1\spr_o[9:0] 10'0000101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 + assign { } { } + assign $1\spr_o[9:0] 10'0000101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 + assign { } { } + assign $1\spr_o[9:0] 10'0000101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 + assign { } { } + assign $1\spr_o[9:0] 10'0000101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000101101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 + assign { } { } + assign $1\spr_o[9:0] 10'0000101110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 + assign { } { } + assign $1\spr_o[9:0] 10'0000101111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 + assign { } { } + assign $1\spr_o[9:0] 10'0000110000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 + assign { } { } + assign $1\spr_o[9:0] 10'0000110001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 + assign { } { } + assign $1\spr_o[9:0] 10'0000110010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 + assign { } { } + assign $1\spr_o[9:0] 10'0000110011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 + assign { } { } + assign $1\spr_o[9:0] 10'0000110100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 + assign { } { } + assign $1\spr_o[9:0] 10'0000110101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 + assign { } { } + assign $1\spr_o[9:0] 10'0000110110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000110111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 + assign { } { } + assign $1\spr_o[9:0] 10'0000111000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000111001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000111010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000111011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000111100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000111101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000111110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000111111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 + assign { } { } + assign $1\spr_o[9:0] 10'0001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 + assign { } { } + assign $1\spr_o[9:0] 10'0001000001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 + assign { } { } + assign $1\spr_o[9:0] 10'0001000010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 + assign { } { } + assign $1\spr_o[9:0] 10'0001000011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 + assign { } { } + assign $1\spr_o[9:0] 10'0001000100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 + assign { } { } + assign $1\spr_o[9:0] 10'0001000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 + assign { } { } + assign $1\spr_o[9:0] 10'0001000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 + assign { } { } + assign $1\spr_o[9:0] 10'0001000111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 + assign { } { } + assign $1\spr_o[9:0] 10'0001001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 + assign { } { } + assign $1\spr_o[9:0] 10'0001001001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 + assign { } { } + assign $1\spr_o[9:0] 10'0001001010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 + assign { } { } + assign $1\spr_o[9:0] 10'0001001011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 + assign { } { } + assign $1\spr_o[9:0] 10'0001001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 + assign { } { } + assign $1\spr_o[9:0] 10'0001001101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 + assign { } { } + assign $1\spr_o[9:0] 10'0001001110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 + assign { } { } + assign $1\spr_o[9:0] 10'0001001111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 + assign { } { } + assign $1\spr_o[9:0] 10'0001010000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 + assign { } { } + assign $1\spr_o[9:0] 10'0001010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 + assign { } { } + assign $1\spr_o[9:0] 10'0001010010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 + assign { } { } + assign $1\spr_o[9:0] 10'0001010011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 + assign { } { } + assign $1\spr_o[9:0] 10'0001010100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 + assign { } { } + assign $1\spr_o[9:0] 10'0001010101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 + assign { } { } + assign $1\spr_o[9:0] 10'0001010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 + assign { } { } + assign $1\spr_o[9:0] 10'0001010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 + assign { } { } + assign $1\spr_o[9:0] 10'0001011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 + assign { } { } + assign $1\spr_o[9:0] 10'0001011001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 + assign { } { } + assign $1\spr_o[9:0] 10'0001011010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 + assign { } { } + assign $1\spr_o[9:0] 10'0001011011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 + assign { } { } + assign $1\spr_o[9:0] 10'0001011100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 + assign { } { } + assign $1\spr_o[9:0] 10'0001011101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 + assign { } { } + assign $1\spr_o[9:0] 10'0001011110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100101 + assign { } { } + assign $1\spr_o[9:0] 10'0001011111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 + assign { } { } + assign $1\spr_o[9:0] 10'0001100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 + assign { } { } + assign $1\spr_o[9:0] 10'0001100001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 + assign { } { } + assign $1\spr_o[9:0] 10'0001100010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 + assign { } { } + assign $1\spr_o[9:0] 10'0001100011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 + assign { } { } + assign $1\spr_o[9:0] 10'0001100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110000 + assign { } { } + assign $1\spr_o[9:0] 10'0001100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110111 + assign { } { } + assign $1\spr_o[9:0] 10'0001100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010000 + assign { } { } + assign $1\spr_o[9:0] 10'0001101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010001 + assign { } { } + assign $1\spr_o[9:0] 10'0001101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010111 + assign { } { } + assign $1\spr_o[9:0] 10'0001101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000000 + assign { } { } + assign $1\spr_o[9:0] 10'0001101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000010 + assign { } { } + assign $1\spr_o[9:0] 10'0001101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1111111111 + assign { } { } + assign $1\spr_o[9:0] 10'0001101101 + case + assign $1\spr_o[9:0] 10'0000000000 + end + sync always + update \spr_o $0\spr_o[9:0] + end + attribute \src "libresoc.v:180338.3-180650.6" + process $proc$libresoc.v:180338$13022 + assign { } { } + assign { } { } + assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] + attribute \src "libresoc.v:180339.5-180339.29" + switch \initial + attribute \src "libresoc.v:180339.9-180339.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1111111111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + case + assign $1\spr_o_ok[0:0] 1'0 + end + sync always + update \spr_o_ok $0\spr_o_ok[0:0] + end +end +attribute \src "libresoc.v:180655.1-180713.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.src_l" +attribute \generator "nMigen" +module \src_l + attribute \src "libresoc.v:180656.7-180656.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:180701.3-180709.6" + wire width 4 $0\q_int$next[3:0]$13034 + attribute \src "libresoc.v:180699.3-180700.27" + wire width 4 $0\q_int[3:0] + attribute \src "libresoc.v:180701.3-180709.6" + wire width 4 $1\q_int$next[3:0]$13035 + attribute \src "libresoc.v:180678.13-180678.25" + wire width 4 $1\q_int[3:0] + attribute \src "libresoc.v:180691.17-180691.96" + wire width 4 $and$libresoc.v:180691$13024_Y + attribute \src "libresoc.v:180696.17-180696.96" + wire width 4 $and$libresoc.v:180696$13029_Y + attribute \src "libresoc.v:180693.18-180693.93" + wire width 4 $not$libresoc.v:180693$13026_Y + attribute \src "libresoc.v:180695.17-180695.92" + wire width 4 $not$libresoc.v:180695$13028_Y + attribute \src "libresoc.v:180698.17-180698.92" + wire width 4 $not$libresoc.v:180698$13031_Y + attribute \src "libresoc.v:180692.18-180692.98" + wire width 4 $or$libresoc.v:180692$13025_Y + attribute \src "libresoc.v:180694.18-180694.99" + wire width 4 $or$libresoc.v:180694$13027_Y + attribute \src "libresoc.v:180697.17-180697.97" + wire width 4 $or$libresoc.v:180697$13030_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 4 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 4 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \$3 + attribute \src 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\$1 + connect \Y $and$libresoc.v:180758$13043_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:180755$13040 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_src + connect \Y $not$libresoc.v:180755$13040_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:180757$13042 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \r_src + connect \Y $not$libresoc.v:180757$13042_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:180760$13045 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \r_src + connect \Y $not$libresoc.v:180760$13045_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:180754$13039 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + 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$and $and$libresoc.v:180820$13057 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:180820$13057_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:180817$13054 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \Y $not$libresoc.v:180817$13054_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:180819$13056 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$libresoc.v:180819$13056_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:180822$13059 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$libresoc.v:180822$13059_Y + end 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"libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[2:0]$13063 3'000 + case + assign $1\q_int$next[2:0]$13063 \$5 + end + sync always + update \q_int$next $0\q_int$next[2:0]$13062 + end + connect \$9 $and$libresoc.v:180815$13052_Y + connect \$11 $or$libresoc.v:180816$13053_Y + connect \$13 $not$libresoc.v:180817$13054_Y + connect \$15 $or$libresoc.v:180818$13055_Y + connect \$1 $not$libresoc.v:180819$13056_Y + connect \$3 $and$libresoc.v:180820$13057_Y + connect \$5 $or$libresoc.v:180821$13058_Y + connect \$7 $not$libresoc.v:180822$13059_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "libresoc.v:180841.1-180899.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.src_l" +attribute \generator "nMigen" +module \src_l$119 + attribute \src "libresoc.v:180842.7-180842.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:180887.3-180895.6" + wire width 5 $0\q_int$next[4:0]$13076 + attribute \src "libresoc.v:180885.3-180886.27" + wire width 5 $0\q_int[4:0] + attribute \src "libresoc.v:180887.3-180895.6" + wire width 5 $1\q_int$next[4:0]$13077 + attribute \src "libresoc.v:180864.13-180864.26" + wire width 5 $1\q_int[4:0] + attribute \src "libresoc.v:180877.17-180877.96" + wire width 5 $and$libresoc.v:180877$13066_Y + attribute \src "libresoc.v:180882.17-180882.96" + wire width 5 $and$libresoc.v:180882$13071_Y + attribute \src "libresoc.v:180879.18-180879.93" + wire width 5 $not$libresoc.v:180879$13068_Y + attribute \src "libresoc.v:180881.17-180881.92" + wire width 5 $not$libresoc.v:180881$13070_Y + attribute \src "libresoc.v:180884.17-180884.92" + wire width 5 $not$libresoc.v:180884$13073_Y + attribute \src "libresoc.v:180878.18-180878.98" + wire width 5 $or$libresoc.v:180878$13067_Y + attribute \src "libresoc.v:180880.18-180880.99" + wire width 5 $or$libresoc.v:180880$13069_Y + attribute \src "libresoc.v:180883.17-180883.97" + wire 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\src "libresoc.v:180842.7-180842.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 5 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 5 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 5 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 5 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 5 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 5 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 5 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:180877$13066 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:180877$13066_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:180882$13071 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:180882$13071_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:180879$13068 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_src + connect \Y $not$libresoc.v:180879$13068_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:180881$13070 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \r_src + connect \Y $not$libresoc.v:180881$13070_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:180884$13073 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \r_src + connect \Y $not$libresoc.v:180884$13073_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:180878$13067 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$9 + connect \B \s_src + connect \Y $or$libresoc.v:180878$13067_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:180880$13069 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_src + connect \B \q_int + connect \Y $or$libresoc.v:180880$13069_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:180883$13072 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$3 + connect \B \s_src + connect \Y $or$libresoc.v:180883$13072_Y + end + attribute \src "libresoc.v:180842.7-180842.20" + process $proc$libresoc.v:180842$13078 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:180864.13-180864.26" + process $proc$libresoc.v:180864$13079 + assign { } { } + assign $1\q_int[4:0] 5'00000 + sync always + sync init + update \q_int $1\q_int[4:0] + end + attribute \src "libresoc.v:180885.3-180886.27" + process $proc$libresoc.v:180885$13074 + assign { } { } + assign $0\q_int[4:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[4:0] + end + attribute \src "libresoc.v:180887.3-180895.6" + process $proc$libresoc.v:180887$13075 + assign { } { } + assign { } { } + assign $0\q_int$next[4:0]$13076 $1\q_int$next[4:0]$13077 + attribute \src "libresoc.v:180888.5-180888.29" + switch \initial + attribute \src "libresoc.v:180888.9-180888.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[4:0]$13077 5'00000 + case + assign $1\q_int$next[4:0]$13077 \$5 + end + sync always + update \q_int$next $0\q_int$next[4:0]$13076 + end + connect \$9 $and$libresoc.v:180877$13066_Y + connect \$11 $or$libresoc.v:180878$13067_Y + connect \$13 $not$libresoc.v:180879$13068_Y + connect \$15 $or$libresoc.v:180880$13069_Y + connect \$1 $not$libresoc.v:180881$13070_Y + connect \$3 $and$libresoc.v:180882$13071_Y + connect \$5 $or$libresoc.v:180883$13072_Y + connect \$7 $not$libresoc.v:180884$13073_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "libresoc.v:180903.1-180961.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.src_l" +attribute \generator "nMigen" +module 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"/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:180904.7-180904.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 3 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 3 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:180939$13080 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:180939$13080_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:180944$13085 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:180944$13085_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:180941$13082 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \Y $not$libresoc.v:180941$13082_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:180943$13084 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$libresoc.v:180943$13084_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:180946$13087 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$libresoc.v:180946$13087_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:180940$13081 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$9 + connect \B \s_src + connect \Y $or$libresoc.v:180940$13081_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:180942$13083 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \B \q_int + connect \Y $or$libresoc.v:180942$13083_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:180945$13086 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$3 + connect \B \s_src + connect \Y $or$libresoc.v:180945$13086_Y + end + attribute \src "libresoc.v:180904.7-180904.20" + process $proc$libresoc.v:180904$13092 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:180926.13-180926.25" + process $proc$libresoc.v:180926$13093 + assign { } { } + assign $1\q_int[2:0] 3'000 + sync always + sync init + update \q_int $1\q_int[2:0] + end + attribute \src "libresoc.v:180947.3-180948.27" + process $proc$libresoc.v:180947$13088 + assign { } { } + assign $0\q_int[2:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[2:0] + end + attribute \src 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$or$libresoc.v:181004$13097 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \B \q_int + connect \Y $or$libresoc.v:181004$13097_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:181007$13100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$3 + connect \B \s_src + connect \Y $or$libresoc.v:181007$13100_Y + end + attribute \src "libresoc.v:180966.7-180966.20" + process $proc$libresoc.v:180966$13106 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:180988.13-180988.25" + process $proc$libresoc.v:180988$13107 + assign { } { } + assign $1\q_int[2:0] 3'000 + sync always + sync init + update \q_int $1\q_int[2:0] + end + attribute \src "libresoc.v:181009.3-181010.27" + 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$or$libresoc.v:181064$13109_Y + connect \$13 $not$libresoc.v:181065$13110_Y + connect \$15 $or$libresoc.v:181066$13111_Y + connect \$1 $not$libresoc.v:181067$13112_Y + connect \$3 $and$libresoc.v:181068$13113_Y + connect \$5 $or$libresoc.v:181069$13114_Y + connect \$7 $not$libresoc.v:181070$13115_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "libresoc.v:181089.1-181147.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.src_l" +attribute \generator "nMigen" +module \src_l$55 + attribute \src "libresoc.v:181090.7-181090.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:181135.3-181143.6" + wire width 3 $0\q_int$next[2:0]$13132 + attribute \src "libresoc.v:181133.3-181134.27" + wire width 3 $0\q_int[2:0] + attribute \src "libresoc.v:181135.3-181143.6" + wire width 3 $1\q_int$next[2:0]$13133 + attribute \src "libresoc.v:181112.13-181112.25" + wire width 3 $1\q_int[2:0] + attribute \src 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$or$libresoc.v:181126$13123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$9 + connect \B \s_src + connect \Y $or$libresoc.v:181126$13123_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:181128$13125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \B \q_int + connect \Y $or$libresoc.v:181128$13125_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:181131$13128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$3 + connect \B \s_src + connect \Y $or$libresoc.v:181131$13128_Y + end + attribute \src "libresoc.v:181090.7-181090.20" + process $proc$libresoc.v:181090$13134 + assign { } { } + assign $0\initial[0:0] 1'0 + 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assign $1\q_int$next[2:0]$13133 \$5 + end + sync always + update \q_int$next $0\q_int$next[2:0]$13132 + end + connect \$9 $and$libresoc.v:181125$13122_Y + connect \$11 $or$libresoc.v:181126$13123_Y + connect \$13 $not$libresoc.v:181127$13124_Y + connect \$15 $or$libresoc.v:181128$13125_Y + connect \$1 $not$libresoc.v:181129$13126_Y + connect \$3 $and$libresoc.v:181130$13127_Y + connect \$5 $or$libresoc.v:181131$13128_Y + connect \$7 $not$libresoc.v:181132$13129_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "libresoc.v:181151.1-181209.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.src_l" +attribute \generator "nMigen" +module \src_l$67 + attribute \src "libresoc.v:181152.7-181152.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:181197.3-181205.6" + wire width 6 $0\q_int$next[5:0]$13146 + attribute \src "libresoc.v:181195.3-181196.27" + wire width 6 $0\q_int[5:0] + attribute \src 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6 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 6 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 6 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 6 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 6 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 6 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 6 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 6 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:181152.7-181152.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:181192$13141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:181192$13141_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:181189$13138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_src + connect \Y $not$libresoc.v:181189$13138_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:181191$13140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \r_src + connect \Y $not$libresoc.v:181191$13140_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:181194$13143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + 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$or$libresoc.v:181193$13142_Y + end + attribute \src "libresoc.v:181152.7-181152.20" + process $proc$libresoc.v:181152$13148 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:181174.13-181174.26" + process $proc$libresoc.v:181174$13149 + assign { } { } + assign $1\q_int[5:0] 6'000000 + sync always + sync init + update \q_int $1\q_int[5:0] + end + attribute \src "libresoc.v:181195.3-181196.27" + process $proc$libresoc.v:181195$13144 + assign { } { } + assign $0\q_int[5:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[5:0] + end + attribute \src "libresoc.v:181197.3-181205.6" + process $proc$libresoc.v:181197$13145 + assign { } { } + assign { } { } + assign $0\q_int$next[5:0]$13146 $1\q_int$next[5:0]$13147 + attribute \src "libresoc.v:181198.5-181198.29" + switch \initial + attribute \src "libresoc.v:181198.9-181198.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[5:0]$13147 6'000000 + case + assign $1\q_int$next[5:0]$13147 \$5 + end + sync always + update \q_int$next $0\q_int$next[5:0]$13146 + end + connect \$9 $and$libresoc.v:181187$13136_Y + connect \$11 $or$libresoc.v:181188$13137_Y + connect \$13 $not$libresoc.v:181189$13138_Y + connect \$15 $or$libresoc.v:181190$13139_Y + connect \$1 $not$libresoc.v:181191$13140_Y + connect \$3 $and$libresoc.v:181192$13141_Y + connect \$5 $or$libresoc.v:181193$13142_Y + connect \$7 $not$libresoc.v:181194$13143_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "libresoc.v:181213.1-181271.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.src_l" +attribute \generator "nMigen" +module \src_l$84 + attribute \src "libresoc.v:181214.7-181214.20" + wire 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$or$libresoc.v:181252$13153_Y + attribute \src "libresoc.v:181255.17-181255.97" + wire width 3 $or$libresoc.v:181255$13156_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 3 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src 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\A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:181249$13150_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:181254$13155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:181254$13155_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:181251$13152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \Y $not$libresoc.v:181251$13152_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:181253$13154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$libresoc.v:181253$13154_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:181256$13157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$libresoc.v:181256$13157_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:181250$13151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$9 + connect \B \s_src + connect \Y $or$libresoc.v:181250$13151_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:181252$13153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \B \q_int + connect \Y $or$libresoc.v:181252$13153_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:181255$13156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$3 + connect \B \s_src + connect \Y $or$libresoc.v:181255$13156_Y + end + attribute \src "libresoc.v:181214.7-181214.20" + process $proc$libresoc.v:181214$13162 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:181236.13-181236.25" + process $proc$libresoc.v:181236$13163 + assign { } { } + assign $1\q_int[2:0] 3'000 + sync always + sync init + update \q_int $1\q_int[2:0] + end + attribute \src "libresoc.v:181257.3-181258.27" + process $proc$libresoc.v:181257$13158 + assign { } { } + assign $0\q_int[2:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[2:0] + end + attribute \src "libresoc.v:181259.3-181267.6" + process $proc$libresoc.v:181259$13159 + assign { } { } + assign { } { } + assign $0\q_int$next[2:0]$13160 $1\q_int$next[2:0]$13161 + attribute \src "libresoc.v:181260.5-181260.29" + switch \initial + attribute \src "libresoc.v:181260.9-181260.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[2:0]$13161 3'000 + case + assign $1\q_int$next[2:0]$13161 \$5 + end + sync always + update \q_int$next $0\q_int$next[2:0]$13160 + end + connect \$9 $and$libresoc.v:181249$13150_Y + connect \$11 $or$libresoc.v:181250$13151_Y + connect \$13 $not$libresoc.v:181251$13152_Y + connect \$15 $or$libresoc.v:181252$13153_Y + connect \$1 $not$libresoc.v:181253$13154_Y + connect \$3 $and$libresoc.v:181254$13155_Y + connect \$5 $or$libresoc.v:181255$13156_Y + connect \$7 $not$libresoc.v:181256$13157_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "libresoc.v:181275.1-181333.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.st_active" +attribute \generator "nMigen" +module \st_active + attribute \src "libresoc.v:181276.7-181276.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:181321.3-181329.6" + wire $0\q_int$next[0:0]$13174 + attribute \src "libresoc.v:181319.3-181320.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:181321.3-181329.6" + wire $1\q_int$next[0:0]$13175 + attribute \src "libresoc.v:181298.7-181298.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:181311.17-181311.96" + wire $and$libresoc.v:181311$13164_Y + attribute \src "libresoc.v:181316.17-181316.96" + wire $and$libresoc.v:181316$13169_Y + attribute \src "libresoc.v:181313.18-181313.99" + wire $not$libresoc.v:181313$13166_Y + attribute \src "libresoc.v:181315.17-181315.98" + wire $not$libresoc.v:181315$13168_Y + attribute \src "libresoc.v:181318.17-181318.98" + wire $not$libresoc.v:181318$13171_Y + attribute \src "libresoc.v:181312.18-181312.104" + wire $or$libresoc.v:181312$13165_Y + attribute \src "libresoc.v:181314.18-181314.105" + wire $or$libresoc.v:181314$13167_Y + attribute \src "libresoc.v:181317.17-181317.103" + wire $or$libresoc.v:181317$13170_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:181276.7-181276.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_st_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_st_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_st_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 2 \r_st_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 3 \s_st_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:181311$13164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:181311$13164_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:181316$13169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:181316$13169_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:181313$13166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_st_active + connect \Y $not$libresoc.v:181313$13166_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:181315$13168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_st_active + connect \Y $not$libresoc.v:181315$13168_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:181318$13171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_st_active + connect \Y $not$libresoc.v:181318$13171_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:181312$13165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_st_active + connect \Y $or$libresoc.v:181312$13165_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:181314$13167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_st_active + connect \B \q_int + connect \Y $or$libresoc.v:181314$13167_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:181317$13170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_st_active + connect \Y $or$libresoc.v:181317$13170_Y + end + attribute \src "libresoc.v:181276.7-181276.20" + process $proc$libresoc.v:181276$13176 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:181298.7-181298.19" + process $proc$libresoc.v:181298$13177 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:181319.3-181320.27" + process $proc$libresoc.v:181319$13172 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:181321.3-181329.6" + process $proc$libresoc.v:181321$13173 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$13174 $1\q_int$next[0:0]$13175 + attribute \src "libresoc.v:181322.5-181322.29" + switch \initial + attribute \src "libresoc.v:181322.9-181322.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$13175 1'0 + case + assign $1\q_int$next[0:0]$13175 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$13174 + end + connect \$9 $and$libresoc.v:181311$13164_Y + connect \$11 $or$libresoc.v:181312$13165_Y + connect \$13 $not$libresoc.v:181313$13166_Y + connect \$15 $or$libresoc.v:181314$13167_Y + connect \$1 $not$libresoc.v:181315$13168_Y + connect \$3 $and$libresoc.v:181316$13169_Y + connect \$5 $or$libresoc.v:181317$13170_Y + connect \$7 $not$libresoc.v:181318$13171_Y + connect \qlq_st_active \$15 + connect \qn_st_active \$13 + connect \q_st_active \$11 +end +attribute \src "libresoc.v:181337.1-181395.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.st_done" +attribute \generator "nMigen" +module \st_done + attribute \src "libresoc.v:181338.7-181338.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:181383.3-181391.6" + wire $0\q_int$next[0:0]$13188 + attribute \src "libresoc.v:181381.3-181382.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:181383.3-181391.6" + wire $1\q_int$next[0:0]$13189 + attribute \src "libresoc.v:181360.7-181360.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:181373.17-181373.96" + wire $and$libresoc.v:181373$13178_Y + attribute \src "libresoc.v:181378.17-181378.96" + wire $and$libresoc.v:181378$13183_Y + attribute \src "libresoc.v:181375.18-181375.97" + wire $not$libresoc.v:181375$13180_Y + attribute \src "libresoc.v:181377.17-181377.96" + wire $not$libresoc.v:181377$13182_Y + attribute \src "libresoc.v:181380.17-181380.96" + wire $not$libresoc.v:181380$13185_Y + attribute \src "libresoc.v:181374.18-181374.102" + wire $or$libresoc.v:181374$13179_Y + attribute \src "libresoc.v:181376.18-181376.103" + wire $or$libresoc.v:181376$13181_Y + attribute \src "libresoc.v:181379.17-181379.101" + wire $or$libresoc.v:181379$13184_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:181338.7-181338.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_st_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_st_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_st_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_st_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_st_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:181373$13178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:181373$13178_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:181378$13183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:181378$13183_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:181375$13180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_st_done + connect \Y $not$libresoc.v:181375$13180_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:181377$13182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_st_done + connect \Y $not$libresoc.v:181377$13182_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:181380$13185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_st_done + connect \Y $not$libresoc.v:181380$13185_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:181374$13179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_st_done + connect \Y $or$libresoc.v:181374$13179_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:181376$13181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_st_done + connect \B \q_int + connect \Y $or$libresoc.v:181376$13181_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:181379$13184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_st_done + connect \Y $or$libresoc.v:181379$13184_Y + end + attribute \src "libresoc.v:181338.7-181338.20" + process $proc$libresoc.v:181338$13190 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:181360.7-181360.19" + process $proc$libresoc.v:181360$13191 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:181381.3-181382.27" + process $proc$libresoc.v:181381$13186 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:181383.3-181391.6" + process $proc$libresoc.v:181383$13187 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$13188 $1\q_int$next[0:0]$13189 + attribute \src "libresoc.v:181384.5-181384.29" + switch \initial + attribute \src "libresoc.v:181384.9-181384.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$13189 1'0 + case + assign $1\q_int$next[0:0]$13189 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$13188 + end + connect \$9 $and$libresoc.v:181373$13178_Y + connect \$11 $or$libresoc.v:181374$13179_Y + connect \$13 $not$libresoc.v:181375$13180_Y + connect \$15 $or$libresoc.v:181376$13181_Y + connect \$1 $not$libresoc.v:181377$13182_Y + connect \$3 $and$libresoc.v:181378$13183_Y + connect \$5 $or$libresoc.v:181379$13184_Y + connect \$7 $not$libresoc.v:181380$13185_Y + connect \qlq_st_done \$15 + connect \qn_st_done \$13 + connect \q_st_done \$11 +end +attribute \src "libresoc.v:181399.1-181654.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.state" +attribute \generator "nMigen" +module \state + attribute \src "libresoc.v:181627.3-181636.6" + wire width 64 $0\cia__data_o[63:0] + attribute \src "libresoc.v:181400.7-181400.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:181608.3-181617.6" + wire width 64 $0\msr__data_o[63:0] + attribute \src "libresoc.v:181599.3-181607.6" + wire width 4 $0\ren_delay$12$next[3:0]$13204 + attribute \src "libresoc.v:181539.3-181540.43" + wire width 4 $0\ren_delay$12[3:0]$13201 + attribute \src "libresoc.v:181520.13-181520.34" + wire width 4 $0\ren_delay$12[3:0]$13214 + attribute \src "libresoc.v:181618.3-181626.6" + wire width 4 $0\ren_delay$next[3:0]$13208 + attribute \src "libresoc.v:181541.3-181542.35" + wire width 4 $0\ren_delay[3:0] + attribute \src "libresoc.v:181627.3-181636.6" + wire width 64 $1\cia__data_o[63:0] + attribute \src "libresoc.v:181608.3-181617.6" + wire width 64 $1\msr__data_o[63:0] + attribute \src "libresoc.v:181599.3-181607.6" + wire width 4 $1\ren_delay$12$next[3:0]$13205 + attribute \src "libresoc.v:181618.3-181626.6" + wire width 4 $1\ren_delay$next[3:0]$13209 + attribute \src "libresoc.v:181518.13-181518.29" + wire width 4 $1\ren_delay[3:0] + attribute \src "libresoc.v:181531.18-181531.95" + wire width 64 $or$libresoc.v:181531$13192_Y + attribute \src "libresoc.v:181533.18-181533.124" + wire width 64 $or$libresoc.v:181533$13194_Y + attribute \src "libresoc.v:181534.18-181534.124" + wire width 64 $or$libresoc.v:181534$13195_Y + attribute \src "libresoc.v:181535.18-181535.97" + wire width 64 $or$libresoc.v:181535$13196_Y + attribute \src "libresoc.v:181537.17-181537.123" + wire width 64 $or$libresoc.v:181537$13198_Y + attribute \src "libresoc.v:181538.17-181538.123" + wire width 64 $or$libresoc.v:181538$13199_Y + attribute \src "libresoc.v:181532.18-181532.100" + wire $reduce_or$libresoc.v:181532$13193_Y + attribute \src "libresoc.v:181536.17-181536.95" + wire $reduce_or$libresoc.v:181536$13197_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 64 \$10 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 64 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 64 \$17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 64 \$19 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 64 \$6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 64 \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 3 \cia__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 2 \cia__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 12 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 5 \data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 9 \data_i$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 10 \data_i$2 + attribute \src "libresoc.v:181400.7-181400.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 7 \msr__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 6 \msr__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_0_cia0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_0_cia0__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_0_d_wr10__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_0_d_wr10__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_0_msr0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_0_msr0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_0_msr0__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_0_msr0__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_0_nia0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_0_nia0__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_1_cia1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_1_cia1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_1_d_wr11__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_1_d_wr11__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_1_msr1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_1_msr1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_1_msr1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_1_msr1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_1_nia1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_1_nia1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_2_cia2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_cia2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_2_d_wr12__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_d_wr12__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_2_msr2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_2_msr2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_msr2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_msr2__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_2_nia2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_nia2__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_3_cia3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_3_cia3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_3_d_wr13__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_3_d_wr13__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_3_msr3__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_3_msr3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_3_msr3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_3_msr3__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_3_nia3__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_3_nia3__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 4 \ren_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 4 \ren_delay$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 4 \ren_delay$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 4 \ren_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 8 \state_nia_wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 4 \wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 11 \wen$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:181531$13192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \$6 + connect \B \$8 + connect \Y $or$libresoc.v:181531$13192_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:181533$13194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \reg_0_msr0__data_o + connect \B \reg_1_msr1__data_o + connect \Y $or$libresoc.v:181533$13194_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:181534$13195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \reg_2_msr2__data_o + connect \B \reg_3_msr3__data_o + connect \Y $or$libresoc.v:181534$13195_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:181535$13196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \$15 + connect \B \$17 + connect \Y $or$libresoc.v:181535$13196_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:181537$13198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \reg_0_cia0__data_o + connect \B \reg_1_cia1__data_o + connect \Y $or$libresoc.v:181537$13198_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:181538$13199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \reg_2_cia2__data_o + connect \B \reg_3_cia3__data_o + connect \Y $or$libresoc.v:181538$13199_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:181532$13193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \ren_delay$12 + connect \Y $reduce_or$libresoc.v:181532$13193_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:181536$13197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \ren_delay + connect \Y $reduce_or$libresoc.v:181536$13197_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:181543.15-181556.4" + cell \reg_0$135 \reg_0 + connect \cia0__data_o \reg_0_cia0__data_o + connect \cia0__ren \reg_0_cia0__ren + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \d_wr10__data_i \reg_0_d_wr10__data_i + connect \d_wr10__wen \reg_0_d_wr10__wen + connect \msr0__data_i \reg_0_msr0__data_i + connect \msr0__data_o \reg_0_msr0__data_o + connect \msr0__ren \reg_0_msr0__ren + connect \msr0__wen \reg_0_msr0__wen + connect \nia0__data_i \reg_0_nia0__data_i + connect \nia0__wen \reg_0_nia0__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:181557.15-181570.4" + cell \reg_1$136 \reg_1 + connect \cia1__data_o \reg_1_cia1__data_o + connect \cia1__ren \reg_1_cia1__ren + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \d_wr11__data_i \reg_1_d_wr11__data_i + connect \d_wr11__wen \reg_1_d_wr11__wen + connect \msr1__data_i \reg_1_msr1__data_i + connect \msr1__data_o \reg_1_msr1__data_o + connect \msr1__ren \reg_1_msr1__ren + connect \msr1__wen \reg_1_msr1__wen + connect \nia1__data_i \reg_1_nia1__data_i + connect \nia1__wen \reg_1_nia1__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:181571.15-181584.4" + cell \reg_2$137 \reg_2 + connect \cia2__data_o \reg_2_cia2__data_o + connect \cia2__ren \reg_2_cia2__ren + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \d_wr12__data_i \reg_2_d_wr12__data_i + connect \d_wr12__wen \reg_2_d_wr12__wen + connect \msr2__data_i \reg_2_msr2__data_i + connect \msr2__data_o \reg_2_msr2__data_o + connect \msr2__ren \reg_2_msr2__ren + connect \msr2__wen \reg_2_msr2__wen + connect \nia2__data_i \reg_2_nia2__data_i + connect \nia2__wen \reg_2_nia2__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:181585.15-181598.4" + cell \reg_3$138 \reg_3 + connect \cia3__data_o \reg_3_cia3__data_o + connect \cia3__ren \reg_3_cia3__ren + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \d_wr13__data_i \reg_3_d_wr13__data_i + connect \d_wr13__wen \reg_3_d_wr13__wen + connect \msr3__data_i \reg_3_msr3__data_i + connect \msr3__data_o \reg_3_msr3__data_o + connect \msr3__ren \reg_3_msr3__ren + connect \msr3__wen \reg_3_msr3__wen + connect \nia3__data_i \reg_3_nia3__data_i + connect \nia3__wen \reg_3_nia3__wen + end + attribute \src "libresoc.v:181400.7-181400.20" + process $proc$libresoc.v:181400$13211 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:181518.13-181518.29" + process $proc$libresoc.v:181518$13212 + assign { } { } + assign $1\ren_delay[3:0] 4'0000 + sync always + sync init + update \ren_delay $1\ren_delay[3:0] + end + attribute \src "libresoc.v:181520.13-181520.34" + process $proc$libresoc.v:181520$13213 + assign { } { } + assign $0\ren_delay$12[3:0]$13214 4'0000 + sync always + sync init + update \ren_delay$12 $0\ren_delay$12[3:0]$13214 + end + attribute \src "libresoc.v:181539.3-181540.43" + process $proc$libresoc.v:181539$13200 + assign { } { } + assign $0\ren_delay$12[3:0]$13201 \ren_delay$12$next + sync posedge \coresync_clk + update \ren_delay$12 $0\ren_delay$12[3:0]$13201 + end + attribute \src "libresoc.v:181541.3-181542.35" + process $proc$libresoc.v:181541$13202 + assign { } { } + assign $0\ren_delay[3:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[3:0] + end + attribute \src "libresoc.v:181599.3-181607.6" + process $proc$libresoc.v:181599$13203 + assign { } { } + assign { } { } + assign $0\ren_delay$12$next[3:0]$13204 $1\ren_delay$12$next[3:0]$13205 + attribute \src "libresoc.v:181600.5-181600.29" + switch \initial + attribute \src "libresoc.v:181600.9-181600.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$12$next[3:0]$13205 4'0000 + case + assign $1\ren_delay$12$next[3:0]$13205 \msr__ren + end + sync always + update \ren_delay$12$next $0\ren_delay$12$next[3:0]$13204 + end + attribute \src "libresoc.v:181608.3-181617.6" + process $proc$libresoc.v:181608$13206 + assign { } { } + assign { } { } + assign $0\msr__data_o[63:0] $1\msr__data_o[63:0] + attribute \src "libresoc.v:181609.5-181609.29" + switch \initial + attribute \src "libresoc.v:181609.9-181609.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\msr__data_o[63:0] \$19 + case + assign $1\msr__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \msr__data_o $0\msr__data_o[63:0] + end + attribute \src "libresoc.v:181618.3-181626.6" + process $proc$libresoc.v:181618$13207 + assign { } { } + assign { } { } + assign $0\ren_delay$next[3:0]$13208 $1\ren_delay$next[3:0]$13209 + attribute \src "libresoc.v:181619.5-181619.29" + switch \initial + attribute \src "libresoc.v:181619.9-181619.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$next[3:0]$13209 4'0000 + case + assign $1\ren_delay$next[3:0]$13209 \cia__ren + end + sync always + update \ren_delay$next $0\ren_delay$next[3:0]$13208 + end + attribute \src "libresoc.v:181627.3-181636.6" + process $proc$libresoc.v:181627$13210 + assign { } { } + assign { } { } + assign $0\cia__data_o[63:0] $1\cia__data_o[63:0] + attribute \src "libresoc.v:181628.5-181628.29" + switch \initial + attribute \src "libresoc.v:181628.9-181628.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$4 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cia__data_o[63:0] \$10 + case + assign $1\cia__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \cia__data_o $0\cia__data_o[63:0] + end + connect \$10 $or$libresoc.v:181531$13192_Y + connect \$13 $reduce_or$libresoc.v:181532$13193_Y + connect \$15 $or$libresoc.v:181533$13194_Y + connect \$17 $or$libresoc.v:181534$13195_Y + connect \$19 $or$libresoc.v:181535$13196_Y + connect \$4 $reduce_or$libresoc.v:181536$13197_Y + connect \$6 $or$libresoc.v:181537$13198_Y + connect \$8 $or$libresoc.v:181538$13199_Y + connect \reg_3_d_wr13__data_i \data_i + connect \reg_2_d_wr12__data_i \data_i + connect \reg_1_d_wr11__data_i \data_i + connect \reg_0_d_wr10__data_i \data_i + connect { \reg_3_d_wr13__wen \reg_2_d_wr12__wen \reg_1_d_wr11__wen \reg_0_d_wr10__wen } \wen + connect \reg_3_msr3__data_i \data_i$2 + connect \reg_2_msr2__data_i \data_i$2 + connect \reg_1_msr1__data_i \data_i$2 + connect \reg_0_msr0__data_i \data_i$2 + connect { \reg_3_msr3__wen \reg_2_msr2__wen \reg_1_msr1__wen \reg_0_msr0__wen } \wen$3 + connect \reg_3_nia3__data_i \data_i$1 + connect \reg_2_nia2__data_i \data_i$1 + connect \reg_1_nia1__data_i \data_i$1 + connect \reg_0_nia0__data_i \data_i$1 + connect { \reg_3_nia3__wen \reg_2_nia2__wen \reg_1_nia1__wen \reg_0_nia0__wen } \state_nia_wen + connect { \reg_3_msr3__ren \reg_2_msr2__ren \reg_1_msr1__ren \reg_0_msr0__ren } \msr__ren + connect { \reg_3_cia3__ren \reg_2_cia2__ren \reg_1_cia1__ren \reg_0_cia0__ren } \cia__ren +end +attribute \src "libresoc.v:181658.1-181716.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.sto_l" +attribute \generator "nMigen" +module \sto_l + attribute \src "libresoc.v:181659.7-181659.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:181704.3-181712.6" + wire $0\q_int$next[0:0]$13225 + attribute \src "libresoc.v:181702.3-181703.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:181704.3-181712.6" + wire $1\q_int$next[0:0]$13226 + attribute \src "libresoc.v:181681.7-181681.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:181694.17-181694.96" + wire $and$libresoc.v:181694$13215_Y + attribute \src "libresoc.v:181699.17-181699.96" + wire $and$libresoc.v:181699$13220_Y + attribute \src "libresoc.v:181696.18-181696.93" + wire $not$libresoc.v:181696$13217_Y + attribute \src "libresoc.v:181698.17-181698.92" + wire $not$libresoc.v:181698$13219_Y + attribute \src "libresoc.v:181701.17-181701.92" + wire $not$libresoc.v:181701$13222_Y + attribute \src "libresoc.v:181695.18-181695.98" + wire $or$libresoc.v:181695$13216_Y + attribute \src "libresoc.v:181697.18-181697.99" + wire $or$libresoc.v:181697$13218_Y + attribute \src "libresoc.v:181700.17-181700.97" + wire $or$libresoc.v:181700$13221_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:181659.7-181659.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:181694$13215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:181694$13215_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:181699$13220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:181699$13220_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:181696$13217 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_sto + connect \Y $not$libresoc.v:181696$13217_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:181698$13219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_sto + connect \Y $not$libresoc.v:181698$13219_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:181701$13222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_sto + connect \Y $not$libresoc.v:181701$13222_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:181695$13216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_sto + connect \Y $or$libresoc.v:181695$13216_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:181697$13218 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_sto + connect \B \q_int + connect \Y $or$libresoc.v:181697$13218_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:181700$13221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_sto + connect \Y $or$libresoc.v:181700$13221_Y + end + attribute \src "libresoc.v:181659.7-181659.20" + process $proc$libresoc.v:181659$13227 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:181681.7-181681.19" + process $proc$libresoc.v:181681$13228 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:181702.3-181703.27" + process $proc$libresoc.v:181702$13223 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:181704.3-181712.6" + process $proc$libresoc.v:181704$13224 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$13225 $1\q_int$next[0:0]$13226 + attribute \src "libresoc.v:181705.5-181705.29" + switch \initial + attribute \src "libresoc.v:181705.9-181705.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$13226 1'0 + case + assign $1\q_int$next[0:0]$13226 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$13225 + end + connect \$9 $and$libresoc.v:181694$13215_Y + connect \$11 $or$libresoc.v:181695$13216_Y + connect \$13 $not$libresoc.v:181696$13217_Y + connect \$15 $or$libresoc.v:181697$13218_Y + connect \$1 $not$libresoc.v:181698$13219_Y + connect \$3 $and$libresoc.v:181699$13220_Y + connect \$5 $or$libresoc.v:181700$13221_Y + connect \$7 $not$libresoc.v:181701$13222_Y + connect \qlq_sto \$15 + connect \qn_sto \$13 + connect \q_sto \$11 +end +attribute \src "libresoc.v:181721.1-182854.10" +attribute \cells_not_processed 1 +attribute \top 1 +attribute \nmigen.hierarchy "test_issuer" +attribute \generator "nMigen" +module \test_issuer + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 9 \TAP_bus__tck + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 7 \TAP_bus__tdi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire output 6 \TAP_bus__tdo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 8 \TAP_bus__tms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:105" + wire output 5 \busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 368 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" + wire width 2 input 370 \clk_sel_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:104" + wire input 4 \core_bigendian_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 344 \dbus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 45 output 338 \dbus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 2 input 348 \dbus__bte + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 3 input 347 \dbus__cti + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 342 \dbus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 input 340 \dbus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 output 339 \dbus__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 346 \dbus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 8 output 341 \dbus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 343 \dbus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 345 \dbus__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 19 \eint_0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 20 \eint_0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 21 \eint_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 22 \eint_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 23 \eint_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 24 \eint_2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 37 \gpio_e10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 38 \gpio_e10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 39 \gpio_e10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 40 \gpio_e10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 41 \gpio_e10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 42 \gpio_e10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 43 \gpio_e11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 44 \gpio_e11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 45 \gpio_e11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 46 \gpio_e11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 47 \gpio_e11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 48 \gpio_e11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 49 \gpio_e12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 50 \gpio_e12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 51 \gpio_e12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 52 \gpio_e12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 53 \gpio_e12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 54 \gpio_e12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 55 \gpio_e13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 56 \gpio_e13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 57 \gpio_e13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 58 \gpio_e13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 59 \gpio_e13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 60 \gpio_e13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 61 \gpio_e14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 62 \gpio_e14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 63 \gpio_e14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 64 \gpio_e14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 65 \gpio_e14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 66 \gpio_e14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 67 \gpio_e15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 68 \gpio_e15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 69 \gpio_e15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 70 \gpio_e15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 71 \gpio_e15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 72 \gpio_e15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 25 \gpio_e8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 26 \gpio_e8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 27 \gpio_e8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 28 \gpio_e8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 29 \gpio_e8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 30 \gpio_e8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 31 \gpio_e9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 32 \gpio_e9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 33 \gpio_e9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 34 \gpio_e9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 35 \gpio_e9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 36 \gpio_e9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 73 \gpio_s0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 74 \gpio_s0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 75 \gpio_s0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 76 \gpio_s0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 77 \gpio_s0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 78 \gpio_s0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 79 \gpio_s1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 80 \gpio_s1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 81 \gpio_s1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 82 \gpio_s1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 83 \gpio_s1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 84 \gpio_s1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 85 \gpio_s2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 86 \gpio_s2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 87 \gpio_s2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 88 \gpio_s2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 89 \gpio_s2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 90 \gpio_s2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 91 \gpio_s3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 92 \gpio_s3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 93 \gpio_s3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 94 \gpio_s3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 95 \gpio_s3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 96 \gpio_s3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 97 \gpio_s4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 98 \gpio_s4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 99 \gpio_s4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 100 \gpio_s4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 101 \gpio_s4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 102 \gpio_s4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 103 \gpio_s5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 104 \gpio_s5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 105 \gpio_s5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 106 \gpio_s5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 107 \gpio_s5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 108 \gpio_s5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 109 \gpio_s6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 110 \gpio_s6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 111 \gpio_s6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 112 \gpio_s6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 113 \gpio_s6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 114 \gpio_s6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 115 \gpio_s7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 116 \gpio_s7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 117 \gpio_s7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 118 \gpio_s7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 119 \gpio_s7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 120 \gpio_s7__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 333 \ibus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 45 output 327 \ibus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 2 input 337 \ibus__bte + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 3 input 336 \ibus__cti + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 331 \ibus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 64 input 329 \ibus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 64 input 328 \ibus__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 335 \ibus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 8 output 330 \ibus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 332 \ibus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 334 \ibus__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire output 355 \icp_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 28 input 349 \icp_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 353 \icp_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 output 351 \icp_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 input 350 \icp_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 357 \icp_wb__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 4 input 352 \icp_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 354 \icp_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 356 \icp_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire output 364 \ics_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 28 input 358 \ics_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 362 \ics_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 output 360 \ics_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 input 359 \ics_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 366 \ics_wb__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 4 input 361 \ics_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 363 \ics_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 365 \ics_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" + wire width 16 input 367 \int_level_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire input 17 \jtag_wb__ack + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 29 output 10 \jtag_wb__adr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 14 \jtag_wb__cyc + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 input 12 \jtag_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 output 11 \jtag_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire input 18 \jtag_wb__err + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 13 \jtag_wb__sel + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 15 \jtag_wb__stb + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 16 \jtag_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:106" + wire input 3 \memerr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 121 \mspi0_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 122 \mspi0_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 123 \mspi0_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 124 \mspi0_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 127 \mspi0_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 128 \mspi0_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 125 \mspi0_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 126 \mspi0_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 129 \mspi1_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 130 \mspi1_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 131 \mspi1_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 132 \mspi1_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 135 \mspi1_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 136 \mspi1_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 133 \mspi1_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 134 \mspi1_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 143 \mtwi_scl__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 144 \mtwi_scl__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 137 \mtwi_sda__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 138 \mtwi_sda__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 139 \mtwi_sda__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 140 \mtwi_sda__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 141 \mtwi_sda__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 142 \mtwi_sda__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 373 \pc_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 1 \pc_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:102" + wire width 64 output 2 \pc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:467" + wire output 371 \pll_18_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9" + wire \pll_clk_24_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" + wire \pll_clk_pll_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" + wire output 372 \pll_lck_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" + wire \pll_pll_18_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:482" + wire \pllclk_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:482" + wire \pllclk_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 145 \pwm_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 146 \pwm_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 147 \pwm_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 148 \pwm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 369 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 155 \sd0_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 156 \sd0_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 149 \sd0_cmd__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 150 \sd0_cmd__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 151 \sd0_cmd__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 152 \sd0_cmd__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 153 \sd0_cmd__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 154 \sd0_cmd__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 157 \sd0_data0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 158 \sd0_data0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 159 \sd0_data0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 160 \sd0_data0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 161 \sd0_data0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 162 \sd0_data0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 163 \sd0_data1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 164 \sd0_data1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 165 \sd0_data1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 166 \sd0_data1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 167 \sd0_data1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 168 \sd0_data1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 169 \sd0_data2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 170 \sd0_data2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 171 \sd0_data2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 172 \sd0_data2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 173 \sd0_data2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 174 \sd0_data2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 175 \sd0_data3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 176 \sd0_data3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 177 \sd0_data3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 178 \sd0_data3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 179 \sd0_data3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 180 \sd0_data3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 231 \sdr_a_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 232 \sdr_a_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 267 \sdr_a_10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 268 \sdr_a_10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 269 \sdr_a_11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 270 \sdr_a_11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 271 \sdr_a_12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 272 \sdr_a_12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 233 \sdr_a_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 234 \sdr_a_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 235 \sdr_a_2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 236 \sdr_a_2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 237 \sdr_a_3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 238 \sdr_a_3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 239 \sdr_a_4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 240 \sdr_a_4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 241 \sdr_a_5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 242 \sdr_a_5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 243 \sdr_a_6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 244 \sdr_a_6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 245 \sdr_a_7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 246 \sdr_a_7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 247 \sdr_a_8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 248 \sdr_a_8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 249 \sdr_a_9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 250 \sdr_a_9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 251 \sdr_ba_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 252 \sdr_ba_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 253 \sdr_ba_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 254 \sdr_ba_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 261 \sdr_cas_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 262 \sdr_cas_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 257 \sdr_cke__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 258 \sdr_cke__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 255 \sdr_clock__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 256 \sdr_clock__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 265 \sdr_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 266 \sdr_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 181 \sdr_dm_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 182 \sdr_dm_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 273 \sdr_dm_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 274 \sdr_dm_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 275 \sdr_dm_1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 276 \sdr_dm_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 277 \sdr_dm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 278 \sdr_dm_1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 183 \sdr_dq_0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 184 \sdr_dq_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 185 \sdr_dq_0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 186 \sdr_dq_0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 187 \sdr_dq_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 188 \sdr_dq_0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 291 \sdr_dq_10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 292 \sdr_dq_10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 293 \sdr_dq_10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 294 \sdr_dq_10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 295 \sdr_dq_10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 296 \sdr_dq_10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 297 \sdr_dq_11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 298 \sdr_dq_11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 299 \sdr_dq_11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 300 \sdr_dq_11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 301 \sdr_dq_11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 302 \sdr_dq_11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 303 \sdr_dq_12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 304 \sdr_dq_12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 305 \sdr_dq_12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 306 \sdr_dq_12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 307 \sdr_dq_12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 308 \sdr_dq_12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 309 \sdr_dq_13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 310 \sdr_dq_13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 311 \sdr_dq_13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 312 \sdr_dq_13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 313 \sdr_dq_13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 314 \sdr_dq_13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 315 \sdr_dq_14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 316 \sdr_dq_14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 317 \sdr_dq_14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 318 \sdr_dq_14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 319 \sdr_dq_14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 320 \sdr_dq_14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 321 \sdr_dq_15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 322 \sdr_dq_15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 323 \sdr_dq_15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 324 \sdr_dq_15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 325 \sdr_dq_15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 326 \sdr_dq_15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 189 \sdr_dq_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 190 \sdr_dq_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 191 \sdr_dq_1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 192 \sdr_dq_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 193 \sdr_dq_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 194 \sdr_dq_1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 195 \sdr_dq_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 196 \sdr_dq_2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 197 \sdr_dq_2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 198 \sdr_dq_2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 199 \sdr_dq_2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 200 \sdr_dq_2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 201 \sdr_dq_3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 202 \sdr_dq_3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 203 \sdr_dq_3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 204 \sdr_dq_3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 205 \sdr_dq_3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 206 \sdr_dq_3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 207 \sdr_dq_4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 208 \sdr_dq_4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 209 \sdr_dq_4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 210 \sdr_dq_4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 211 \sdr_dq_4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 212 \sdr_dq_4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 213 \sdr_dq_5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 214 \sdr_dq_5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 215 \sdr_dq_5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 216 \sdr_dq_5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 217 \sdr_dq_5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 218 \sdr_dq_5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 219 \sdr_dq_6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 220 \sdr_dq_6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 221 \sdr_dq_6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 222 \sdr_dq_6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 223 \sdr_dq_6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 224 \sdr_dq_6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 225 \sdr_dq_7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 226 \sdr_dq_7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 227 \sdr_dq_7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 228 \sdr_dq_7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 229 \sdr_dq_7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 230 \sdr_dq_7__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 279 \sdr_dq_8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 280 \sdr_dq_8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 281 \sdr_dq_8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 282 \sdr_dq_8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 283 \sdr_dq_8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 284 \sdr_dq_8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 285 \sdr_dq_9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 286 \sdr_dq_9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 287 \sdr_dq_9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 288 \sdr_dq_9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 289 \sdr_dq_9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 290 \sdr_dq_9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 259 \sdr_ras_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 260 \sdr_ras_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 263 \sdr_we_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 264 \sdr_we_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire \ti_coresync_clk + attribute \module_not_derived 1 + attribute \src "libresoc.v:182480.7-182486.4" + cell \pll \pll + connect \clk_24_i \pll_clk_24_i + connect \clk_pll_o \pll_clk_pll_o + connect \clk_sel_i \clk_sel_i + connect \pll_18_o \pll_pll_18_o + connect \pll_lck_o \pll_lck_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:182487.6-182848.4" + cell \ti \ti + connect \TAP_bus__tck \TAP_bus__tck + connect \TAP_bus__tdi \TAP_bus__tdi + connect \TAP_bus__tdo \TAP_bus__tdo + connect \TAP_bus__tms \TAP_bus__tms + connect \busy_o \busy_o + connect \clk \clk + connect \core_bigendian_i \core_bigendian_i + connect \coresync_clk \ti_coresync_clk + connect \dbus__ack \dbus__ack + connect \dbus__adr \dbus__adr + connect \dbus__cyc \dbus__cyc + connect \dbus__dat_r \dbus__dat_r + connect \dbus__dat_w \dbus__dat_w + connect \dbus__err \dbus__err + connect \dbus__sel \dbus__sel + connect \dbus__stb \dbus__stb + connect \dbus__we \dbus__we + connect \eint_0__core__i \eint_0__core__i + connect \eint_0__pad__i \eint_0__pad__i + connect \eint_1__core__i \eint_1__core__i + connect \eint_1__pad__i \eint_1__pad__i + connect \eint_2__core__i \eint_2__core__i + connect \eint_2__pad__i \eint_2__pad__i + connect \gpio_e10__core__i \gpio_e10__core__i + connect \gpio_e10__core__o \gpio_e10__core__o + connect \gpio_e10__core__oe \gpio_e10__core__oe + connect \gpio_e10__pad__i \gpio_e10__pad__i + connect \gpio_e10__pad__o \gpio_e10__pad__o + connect \gpio_e10__pad__oe \gpio_e10__pad__oe + connect \gpio_e11__core__i \gpio_e11__core__i + connect \gpio_e11__core__o \gpio_e11__core__o + connect \gpio_e11__core__oe \gpio_e11__core__oe + connect \gpio_e11__pad__i \gpio_e11__pad__i + connect \gpio_e11__pad__o \gpio_e11__pad__o + connect \gpio_e11__pad__oe \gpio_e11__pad__oe + connect \gpio_e12__core__i \gpio_e12__core__i + connect \gpio_e12__core__o \gpio_e12__core__o + connect \gpio_e12__core__oe \gpio_e12__core__oe + connect \gpio_e12__pad__i \gpio_e12__pad__i + connect \gpio_e12__pad__o \gpio_e12__pad__o + connect \gpio_e12__pad__oe \gpio_e12__pad__oe + connect \gpio_e13__core__i \gpio_e13__core__i + connect \gpio_e13__core__o \gpio_e13__core__o + connect \gpio_e13__core__oe \gpio_e13__core__oe + connect \gpio_e13__pad__i \gpio_e13__pad__i + connect \gpio_e13__pad__o \gpio_e13__pad__o + connect \gpio_e13__pad__oe \gpio_e13__pad__oe + connect \gpio_e14__core__i \gpio_e14__core__i + connect \gpio_e14__core__o \gpio_e14__core__o + connect \gpio_e14__core__oe \gpio_e14__core__oe + connect \gpio_e14__pad__i \gpio_e14__pad__i + connect \gpio_e14__pad__o \gpio_e14__pad__o + connect \gpio_e14__pad__oe \gpio_e14__pad__oe + connect \gpio_e15__core__i \gpio_e15__core__i + connect \gpio_e15__core__o \gpio_e15__core__o + connect \gpio_e15__core__oe \gpio_e15__core__oe + connect \gpio_e15__pad__i \gpio_e15__pad__i + connect \gpio_e15__pad__o \gpio_e15__pad__o + connect \gpio_e15__pad__oe \gpio_e15__pad__oe + connect \gpio_e8__core__i \gpio_e8__core__i + connect \gpio_e8__core__o \gpio_e8__core__o + connect \gpio_e8__core__oe \gpio_e8__core__oe + connect \gpio_e8__pad__i \gpio_e8__pad__i + connect \gpio_e8__pad__o \gpio_e8__pad__o + connect \gpio_e8__pad__oe \gpio_e8__pad__oe + connect \gpio_e9__core__i \gpio_e9__core__i + connect \gpio_e9__core__o \gpio_e9__core__o + connect \gpio_e9__core__oe \gpio_e9__core__oe + connect \gpio_e9__pad__i \gpio_e9__pad__i + connect \gpio_e9__pad__o \gpio_e9__pad__o + connect \gpio_e9__pad__oe \gpio_e9__pad__oe + connect \gpio_s0__core__i \gpio_s0__core__i + connect \gpio_s0__core__o \gpio_s0__core__o + connect \gpio_s0__core__oe \gpio_s0__core__oe + connect \gpio_s0__pad__i \gpio_s0__pad__i + connect \gpio_s0__pad__o \gpio_s0__pad__o + connect \gpio_s0__pad__oe \gpio_s0__pad__oe + connect \gpio_s1__core__i \gpio_s1__core__i + connect \gpio_s1__core__o \gpio_s1__core__o + connect \gpio_s1__core__oe \gpio_s1__core__oe + connect \gpio_s1__pad__i \gpio_s1__pad__i + connect \gpio_s1__pad__o \gpio_s1__pad__o + connect \gpio_s1__pad__oe \gpio_s1__pad__oe + connect \gpio_s2__core__i \gpio_s2__core__i + connect \gpio_s2__core__o \gpio_s2__core__o + connect \gpio_s2__core__oe \gpio_s2__core__oe + connect \gpio_s2__pad__i \gpio_s2__pad__i + connect \gpio_s2__pad__o \gpio_s2__pad__o + connect \gpio_s2__pad__oe \gpio_s2__pad__oe + connect \gpio_s3__core__i \gpio_s3__core__i + connect \gpio_s3__core__o \gpio_s3__core__o + connect \gpio_s3__core__oe \gpio_s3__core__oe + connect \gpio_s3__pad__i \gpio_s3__pad__i + connect \gpio_s3__pad__o \gpio_s3__pad__o + connect \gpio_s3__pad__oe \gpio_s3__pad__oe + connect \gpio_s4__core__i \gpio_s4__core__i + connect \gpio_s4__core__o \gpio_s4__core__o + connect \gpio_s4__core__oe \gpio_s4__core__oe + connect \gpio_s4__pad__i \gpio_s4__pad__i + connect \gpio_s4__pad__o \gpio_s4__pad__o + connect \gpio_s4__pad__oe \gpio_s4__pad__oe + connect \gpio_s5__core__i \gpio_s5__core__i + connect \gpio_s5__core__o \gpio_s5__core__o + connect \gpio_s5__core__oe \gpio_s5__core__oe + connect \gpio_s5__pad__i \gpio_s5__pad__i + connect \gpio_s5__pad__o \gpio_s5__pad__o + connect \gpio_s5__pad__oe \gpio_s5__pad__oe + connect \gpio_s6__core__i \gpio_s6__core__i + connect \gpio_s6__core__o \gpio_s6__core__o + connect \gpio_s6__core__oe \gpio_s6__core__oe + connect \gpio_s6__pad__i \gpio_s6__pad__i + connect \gpio_s6__pad__o \gpio_s6__pad__o + connect \gpio_s6__pad__oe \gpio_s6__pad__oe + connect \gpio_s7__core__i \gpio_s7__core__i + connect \gpio_s7__core__o \gpio_s7__core__o + connect \gpio_s7__core__oe \gpio_s7__core__oe + connect \gpio_s7__pad__i \gpio_s7__pad__i + connect \gpio_s7__pad__o \gpio_s7__pad__o + connect \gpio_s7__pad__oe \gpio_s7__pad__oe + connect \ibus__ack \ibus__ack + connect \ibus__adr \ibus__adr + connect \ibus__cyc \ibus__cyc + connect \ibus__dat_r \ibus__dat_r + connect \ibus__err \ibus__err + connect \ibus__sel \ibus__sel + connect \ibus__stb \ibus__stb + connect \icp_wb__ack \icp_wb__ack + connect \icp_wb__adr \icp_wb__adr + connect \icp_wb__cyc \icp_wb__cyc + connect \icp_wb__dat_r \icp_wb__dat_r + connect \icp_wb__dat_w \icp_wb__dat_w + connect \icp_wb__sel \icp_wb__sel + connect \icp_wb__stb \icp_wb__stb + connect \icp_wb__we \icp_wb__we + connect \ics_wb__ack \ics_wb__ack + connect \ics_wb__adr \ics_wb__adr + connect \ics_wb__cyc \ics_wb__cyc + connect \ics_wb__dat_r \ics_wb__dat_r + connect \ics_wb__dat_w \ics_wb__dat_w + connect \ics_wb__stb \ics_wb__stb + connect \ics_wb__we \ics_wb__we + connect \int_level_i \int_level_i + connect \jtag_wb__ack \jtag_wb__ack + connect \jtag_wb__adr \jtag_wb__adr + connect \jtag_wb__cyc \jtag_wb__cyc + connect \jtag_wb__dat_r \jtag_wb__dat_r + connect \jtag_wb__dat_w \jtag_wb__dat_w + connect \jtag_wb__sel \jtag_wb__sel + connect \jtag_wb__stb \jtag_wb__stb + connect \jtag_wb__we \jtag_wb__we + connect \mspi0_clk__core__o \mspi0_clk__core__o + connect \mspi0_clk__pad__o \mspi0_clk__pad__o + connect \mspi0_cs_n__core__o \mspi0_cs_n__core__o + connect \mspi0_cs_n__pad__o \mspi0_cs_n__pad__o + connect \mspi0_miso__core__i \mspi0_miso__core__i + connect \mspi0_miso__pad__i \mspi0_miso__pad__i + connect \mspi0_mosi__core__o \mspi0_mosi__core__o + connect \mspi0_mosi__pad__o \mspi0_mosi__pad__o + connect \mspi1_clk__core__o \mspi1_clk__core__o + connect \mspi1_clk__pad__o \mspi1_clk__pad__o + connect \mspi1_cs_n__core__o \mspi1_cs_n__core__o + connect \mspi1_cs_n__pad__o \mspi1_cs_n__pad__o + connect \mspi1_miso__core__i \mspi1_miso__core__i + connect \mspi1_miso__pad__i \mspi1_miso__pad__i + connect \mspi1_mosi__core__o \mspi1_mosi__core__o + connect \mspi1_mosi__pad__o \mspi1_mosi__pad__o + connect \mtwi_scl__core__o \mtwi_scl__core__o + connect \mtwi_scl__pad__o \mtwi_scl__pad__o + connect \mtwi_sda__core__i \mtwi_sda__core__i + connect \mtwi_sda__core__o \mtwi_sda__core__o + connect \mtwi_sda__core__oe \mtwi_sda__core__oe + connect \mtwi_sda__pad__i \mtwi_sda__pad__i + connect \mtwi_sda__pad__o \mtwi_sda__pad__o + connect \mtwi_sda__pad__oe \mtwi_sda__pad__oe + connect \pc_i \pc_i + connect \pc_i_ok \pc_i_ok + connect \pc_o \pc_o + connect \pwm_0__core__o \pwm_0__core__o + connect \pwm_0__pad__o \pwm_0__pad__o + connect \pwm_1__core__o \pwm_1__core__o + connect \pwm_1__pad__o \pwm_1__pad__o + connect \rst \rst + connect \sd0_clk__core__o \sd0_clk__core__o + connect \sd0_clk__pad__o \sd0_clk__pad__o + connect \sd0_cmd__core__i \sd0_cmd__core__i + connect \sd0_cmd__core__o \sd0_cmd__core__o + connect \sd0_cmd__core__oe \sd0_cmd__core__oe + connect \sd0_cmd__pad__i \sd0_cmd__pad__i + connect \sd0_cmd__pad__o \sd0_cmd__pad__o + connect \sd0_cmd__pad__oe \sd0_cmd__pad__oe + connect \sd0_data0__core__i \sd0_data0__core__i + connect \sd0_data0__core__o \sd0_data0__core__o + connect \sd0_data0__core__oe \sd0_data0__core__oe + connect \sd0_data0__pad__i \sd0_data0__pad__i + connect \sd0_data0__pad__o \sd0_data0__pad__o + connect \sd0_data0__pad__oe \sd0_data0__pad__oe + connect \sd0_data1__core__i \sd0_data1__core__i + connect \sd0_data1__core__o \sd0_data1__core__o + connect \sd0_data1__core__oe \sd0_data1__core__oe + connect \sd0_data1__pad__i \sd0_data1__pad__i + connect \sd0_data1__pad__o \sd0_data1__pad__o + connect \sd0_data1__pad__oe \sd0_data1__pad__oe + connect \sd0_data2__core__i \sd0_data2__core__i + connect \sd0_data2__core__o \sd0_data2__core__o + connect \sd0_data2__core__oe \sd0_data2__core__oe + connect \sd0_data2__pad__i \sd0_data2__pad__i + connect \sd0_data2__pad__o \sd0_data2__pad__o + connect \sd0_data2__pad__oe \sd0_data2__pad__oe + connect \sd0_data3__core__i \sd0_data3__core__i + connect \sd0_data3__core__o \sd0_data3__core__o + connect \sd0_data3__core__oe \sd0_data3__core__oe + connect \sd0_data3__pad__i \sd0_data3__pad__i + connect \sd0_data3__pad__o \sd0_data3__pad__o + connect \sd0_data3__pad__oe \sd0_data3__pad__oe + connect \sdr_a_0__core__o \sdr_a_0__core__o + connect \sdr_a_0__pad__o \sdr_a_0__pad__o + connect \sdr_a_10__core__o \sdr_a_10__core__o + connect \sdr_a_10__pad__o \sdr_a_10__pad__o + connect \sdr_a_11__core__o \sdr_a_11__core__o + connect \sdr_a_11__pad__o \sdr_a_11__pad__o + connect \sdr_a_12__core__o \sdr_a_12__core__o + connect \sdr_a_12__pad__o \sdr_a_12__pad__o + connect \sdr_a_1__core__o \sdr_a_1__core__o + connect \sdr_a_1__pad__o \sdr_a_1__pad__o + connect \sdr_a_2__core__o \sdr_a_2__core__o + connect \sdr_a_2__pad__o \sdr_a_2__pad__o + connect \sdr_a_3__core__o \sdr_a_3__core__o + connect \sdr_a_3__pad__o \sdr_a_3__pad__o + connect \sdr_a_4__core__o \sdr_a_4__core__o + connect \sdr_a_4__pad__o \sdr_a_4__pad__o + connect \sdr_a_5__core__o \sdr_a_5__core__o + connect \sdr_a_5__pad__o \sdr_a_5__pad__o + connect \sdr_a_6__core__o \sdr_a_6__core__o + connect \sdr_a_6__pad__o \sdr_a_6__pad__o + connect \sdr_a_7__core__o \sdr_a_7__core__o + connect \sdr_a_7__pad__o \sdr_a_7__pad__o + connect \sdr_a_8__core__o \sdr_a_8__core__o + connect \sdr_a_8__pad__o \sdr_a_8__pad__o + connect \sdr_a_9__core__o \sdr_a_9__core__o + connect \sdr_a_9__pad__o \sdr_a_9__pad__o + connect \sdr_ba_0__core__o \sdr_ba_0__core__o + connect \sdr_ba_0__pad__o \sdr_ba_0__pad__o + connect \sdr_ba_1__core__o \sdr_ba_1__core__o + connect \sdr_ba_1__pad__o \sdr_ba_1__pad__o + connect \sdr_cas_n__core__o \sdr_cas_n__core__o + connect \sdr_cas_n__pad__o \sdr_cas_n__pad__o + connect \sdr_cke__core__o \sdr_cke__core__o + connect \sdr_cke__pad__o \sdr_cke__pad__o + connect \sdr_clock__core__o \sdr_clock__core__o + connect \sdr_clock__pad__o \sdr_clock__pad__o + connect \sdr_cs_n__core__o \sdr_cs_n__core__o + connect \sdr_cs_n__pad__o \sdr_cs_n__pad__o + connect \sdr_dm_0__core__o \sdr_dm_0__core__o + connect \sdr_dm_0__pad__o \sdr_dm_0__pad__o + connect \sdr_dm_1__core__i \sdr_dm_1__core__i + connect \sdr_dm_1__core__o \sdr_dm_1__core__o + connect \sdr_dm_1__core__oe \sdr_dm_1__core__oe + connect \sdr_dm_1__pad__i \sdr_dm_1__pad__i + connect \sdr_dm_1__pad__o \sdr_dm_1__pad__o + connect \sdr_dm_1__pad__oe \sdr_dm_1__pad__oe + connect \sdr_dq_0__core__i \sdr_dq_0__core__i + connect \sdr_dq_0__core__o \sdr_dq_0__core__o + connect \sdr_dq_0__core__oe \sdr_dq_0__core__oe + connect \sdr_dq_0__pad__i \sdr_dq_0__pad__i + connect \sdr_dq_0__pad__o \sdr_dq_0__pad__o + connect \sdr_dq_0__pad__oe \sdr_dq_0__pad__oe + connect \sdr_dq_10__core__i \sdr_dq_10__core__i + connect \sdr_dq_10__core__o \sdr_dq_10__core__o + connect \sdr_dq_10__core__oe \sdr_dq_10__core__oe + connect \sdr_dq_10__pad__i \sdr_dq_10__pad__i + connect \sdr_dq_10__pad__o \sdr_dq_10__pad__o + connect \sdr_dq_10__pad__oe \sdr_dq_10__pad__oe + connect \sdr_dq_11__core__i \sdr_dq_11__core__i + connect \sdr_dq_11__core__o \sdr_dq_11__core__o + connect \sdr_dq_11__core__oe \sdr_dq_11__core__oe + connect \sdr_dq_11__pad__i \sdr_dq_11__pad__i + connect \sdr_dq_11__pad__o \sdr_dq_11__pad__o + connect \sdr_dq_11__pad__oe \sdr_dq_11__pad__oe + connect \sdr_dq_12__core__i \sdr_dq_12__core__i + connect \sdr_dq_12__core__o \sdr_dq_12__core__o + connect \sdr_dq_12__core__oe \sdr_dq_12__core__oe + connect \sdr_dq_12__pad__i \sdr_dq_12__pad__i + connect \sdr_dq_12__pad__o \sdr_dq_12__pad__o + connect \sdr_dq_12__pad__oe \sdr_dq_12__pad__oe + connect \sdr_dq_13__core__i \sdr_dq_13__core__i + connect \sdr_dq_13__core__o \sdr_dq_13__core__o + connect \sdr_dq_13__core__oe \sdr_dq_13__core__oe + connect \sdr_dq_13__pad__i \sdr_dq_13__pad__i + connect \sdr_dq_13__pad__o \sdr_dq_13__pad__o + connect \sdr_dq_13__pad__oe \sdr_dq_13__pad__oe + connect \sdr_dq_14__core__i \sdr_dq_14__core__i + connect \sdr_dq_14__core__o \sdr_dq_14__core__o + connect \sdr_dq_14__core__oe \sdr_dq_14__core__oe + connect \sdr_dq_14__pad__i \sdr_dq_14__pad__i + connect \sdr_dq_14__pad__o \sdr_dq_14__pad__o + connect \sdr_dq_14__pad__oe \sdr_dq_14__pad__oe + connect \sdr_dq_15__core__i \sdr_dq_15__core__i + connect \sdr_dq_15__core__o \sdr_dq_15__core__o + connect \sdr_dq_15__core__oe \sdr_dq_15__core__oe + connect \sdr_dq_15__pad__i \sdr_dq_15__pad__i + connect \sdr_dq_15__pad__o \sdr_dq_15__pad__o + connect \sdr_dq_15__pad__oe \sdr_dq_15__pad__oe + connect \sdr_dq_1__core__i \sdr_dq_1__core__i + connect \sdr_dq_1__core__o \sdr_dq_1__core__o + connect \sdr_dq_1__core__oe \sdr_dq_1__core__oe + connect \sdr_dq_1__pad__i \sdr_dq_1__pad__i + connect \sdr_dq_1__pad__o \sdr_dq_1__pad__o + connect \sdr_dq_1__pad__oe \sdr_dq_1__pad__oe + connect \sdr_dq_2__core__i \sdr_dq_2__core__i + connect \sdr_dq_2__core__o \sdr_dq_2__core__o + connect \sdr_dq_2__core__oe \sdr_dq_2__core__oe + connect \sdr_dq_2__pad__i \sdr_dq_2__pad__i + connect \sdr_dq_2__pad__o \sdr_dq_2__pad__o + connect \sdr_dq_2__pad__oe \sdr_dq_2__pad__oe + connect \sdr_dq_3__core__i \sdr_dq_3__core__i + connect \sdr_dq_3__core__o \sdr_dq_3__core__o + connect \sdr_dq_3__core__oe \sdr_dq_3__core__oe + connect \sdr_dq_3__pad__i \sdr_dq_3__pad__i + connect \sdr_dq_3__pad__o \sdr_dq_3__pad__o + connect \sdr_dq_3__pad__oe \sdr_dq_3__pad__oe + connect \sdr_dq_4__core__i \sdr_dq_4__core__i + connect \sdr_dq_4__core__o \sdr_dq_4__core__o + connect \sdr_dq_4__core__oe \sdr_dq_4__core__oe + connect \sdr_dq_4__pad__i \sdr_dq_4__pad__i + connect \sdr_dq_4__pad__o \sdr_dq_4__pad__o + connect \sdr_dq_4__pad__oe \sdr_dq_4__pad__oe + connect \sdr_dq_5__core__i \sdr_dq_5__core__i + connect \sdr_dq_5__core__o \sdr_dq_5__core__o + connect \sdr_dq_5__core__oe \sdr_dq_5__core__oe + connect \sdr_dq_5__pad__i \sdr_dq_5__pad__i + connect \sdr_dq_5__pad__o \sdr_dq_5__pad__o + connect \sdr_dq_5__pad__oe \sdr_dq_5__pad__oe + connect \sdr_dq_6__core__i \sdr_dq_6__core__i + connect \sdr_dq_6__core__o \sdr_dq_6__core__o + connect \sdr_dq_6__core__oe \sdr_dq_6__core__oe + connect \sdr_dq_6__pad__i \sdr_dq_6__pad__i + connect \sdr_dq_6__pad__o \sdr_dq_6__pad__o + connect \sdr_dq_6__pad__oe \sdr_dq_6__pad__oe + connect \sdr_dq_7__core__i \sdr_dq_7__core__i + connect \sdr_dq_7__core__o \sdr_dq_7__core__o + connect \sdr_dq_7__core__oe \sdr_dq_7__core__oe + connect \sdr_dq_7__pad__i \sdr_dq_7__pad__i + connect \sdr_dq_7__pad__o \sdr_dq_7__pad__o + connect \sdr_dq_7__pad__oe \sdr_dq_7__pad__oe + connect \sdr_dq_8__core__i \sdr_dq_8__core__i + connect \sdr_dq_8__core__o \sdr_dq_8__core__o + connect \sdr_dq_8__core__oe \sdr_dq_8__core__oe + connect \sdr_dq_8__pad__i \sdr_dq_8__pad__i + connect \sdr_dq_8__pad__o \sdr_dq_8__pad__o + connect \sdr_dq_8__pad__oe \sdr_dq_8__pad__oe + connect \sdr_dq_9__core__i \sdr_dq_9__core__i + connect \sdr_dq_9__core__o \sdr_dq_9__core__o + connect \sdr_dq_9__core__oe \sdr_dq_9__core__oe + connect \sdr_dq_9__pad__i \sdr_dq_9__pad__i + connect \sdr_dq_9__pad__o \sdr_dq_9__pad__o + connect \sdr_dq_9__pad__oe \sdr_dq_9__pad__oe + connect \sdr_ras_n__core__o \sdr_ras_n__core__o + connect \sdr_ras_n__pad__o \sdr_ras_n__pad__o + connect \sdr_we_n__core__o \sdr_we_n__core__o + connect \sdr_we_n__pad__o \sdr_we_n__pad__o + end + connect \ti_coresync_clk \pll_clk_pll_o + connect \pllclk_rst \rst + connect \pll_18_o \pll_pll_18_o + connect \pll_clk_24_i \clk + connect \pllclk_clk \pll_clk_pll_o +end +attribute \src "libresoc.v:182858.1-186736.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.pll" +attribute \nmigen.hierarchy "test_issuer.ti" attribute \generator "nMigen" -module \pll - attribute \src "libresoc.v:45742.7-45742.20" +module \ti + attribute \src "libresoc.v:186282.3-186404.6" + wire width 8 $0\core_asmcode$next[7:0]$13478 + attribute \src "libresoc.v:185009.3-185010.41" + wire width 8 $0\core_asmcode[7:0] + attribute \src "libresoc.v:186479.3-186515.6" + wire $0\core_bigendian_i$10$next[0:0]$13760 + attribute \src "libresoc.v:185005.3-185006.57" + wire $0\core_bigendian_i$10[0:0]$13295 + attribute \src "libresoc.v:183001.7-183001.35" + wire $0\core_bigendian_i$10[0:0]$13791 + attribute \src "libresoc.v:186177.3-186189.6" + wire width 4 $0\core_cia__ren[3:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 64 $0\core_core_core_cia$next[63:0]$13479 + attribute \src "libresoc.v:185085.3-185086.53" + wire width 64 $0\core_core_core_cia[63:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 8 $0\core_core_core_cr_rd$next[7:0]$13480 + attribute \src "libresoc.v:185129.3-185130.57" + wire width 8 $0\core_core_core_cr_rd[7:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $0\core_core_core_cr_rd_ok$next[0:0]$13481 + attribute \src "libresoc.v:185131.3-185132.63" + wire $0\core_core_core_cr_rd_ok[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 8 $0\core_core_core_cr_wr$next[7:0]$13482 + attribute \src "libresoc.v:185133.3-185134.57" + wire width 8 $0\core_core_core_cr_wr[7:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $0\core_core_core_exc_$signal$3$next[0:0]$13483 + attribute \src "libresoc.v:185111.3-185112.75" + wire $0\core_core_core_exc_$signal$3[0:0]$13353 + attribute \src "libresoc.v:183027.7-183027.44" + wire $0\core_core_core_exc_$signal$3[0:0]$13799 + attribute \src "libresoc.v:186282.3-186404.6" + wire $0\core_core_core_exc_$signal$4$next[0:0]$13484 + attribute \src "libresoc.v:185113.3-185114.75" + wire $0\core_core_core_exc_$signal$4[0:0]$13355 + attribute \src "libresoc.v:183031.7-183031.44" + wire $0\core_core_core_exc_$signal$4[0:0]$13801 + attribute \src "libresoc.v:186282.3-186404.6" + wire $0\core_core_core_exc_$signal$5$next[0:0]$13485 + attribute \src "libresoc.v:185115.3-185116.75" + wire $0\core_core_core_exc_$signal$5[0:0]$13357 + attribute \src "libresoc.v:183035.7-183035.44" + wire $0\core_core_core_exc_$signal$5[0:0]$13803 + attribute \src "libresoc.v:186282.3-186404.6" + wire $0\core_core_core_exc_$signal$6$next[0:0]$13486 + attribute \src "libresoc.v:185117.3-185118.75" + wire $0\core_core_core_exc_$signal$6[0:0]$13359 + attribute \src "libresoc.v:183039.7-183039.44" + wire $0\core_core_core_exc_$signal$6[0:0]$13805 + attribute \src "libresoc.v:186282.3-186404.6" + wire $0\core_core_core_exc_$signal$7$next[0:0]$13487 + attribute \src "libresoc.v:185119.3-185120.75" + wire $0\core_core_core_exc_$signal$7[0:0]$13361 + attribute \src "libresoc.v:183043.7-183043.44" + wire $0\core_core_core_exc_$signal$7[0:0]$13807 + attribute \src "libresoc.v:186282.3-186404.6" + wire $0\core_core_core_exc_$signal$8$next[0:0]$13488 + attribute \src "libresoc.v:185121.3-185122.75" + wire $0\core_core_core_exc_$signal$8[0:0]$13363 + attribute \src "libresoc.v:183047.7-183047.44" + wire $0\core_core_core_exc_$signal$8[0:0]$13809 + attribute \src "libresoc.v:186282.3-186404.6" + wire $0\core_core_core_exc_$signal$9$next[0:0]$13489 + attribute \src "libresoc.v:185123.3-185124.75" + wire $0\core_core_core_exc_$signal$9[0:0]$13365 + attribute \src "libresoc.v:183051.7-183051.44" + wire $0\core_core_core_exc_$signal$9[0:0]$13811 + attribute \src "libresoc.v:186282.3-186404.6" + wire $0\core_core_core_exc_$signal$next[0:0]$13490 + attribute \src "libresoc.v:185109.3-185110.71" + wire $0\core_core_core_exc_$signal[0:0]$13351 + attribute \src "libresoc.v:183025.7-183025.42" + wire $0\core_core_core_exc_$signal[0:0]$13797 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 12 $0\core_core_core_fn_unit$next[11:0]$13491 + attribute \src "libresoc.v:185091.3-185092.61" + wire width 12 $0\core_core_core_fn_unit[11:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 2 $0\core_core_core_input_carry$next[1:0]$13492 + attribute \src "libresoc.v:185105.3-185106.69" + wire width 2 $0\core_core_core_input_carry[1:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 32 $0\core_core_core_insn$next[31:0]$13493 + attribute \src "libresoc.v:185087.3-185088.55" + wire width 32 $0\core_core_core_insn[31:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 7 $0\core_core_core_insn_type$next[6:0]$13494 + attribute \src "libresoc.v:185089.3-185090.65" + wire width 7 $0\core_core_core_insn_type[6:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $0\core_core_core_is_32bit$next[0:0]$13495 + attribute \src "libresoc.v:185137.3-185138.63" + wire $0\core_core_core_is_32bit[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 64 $0\core_core_core_msr$next[63:0]$13496 + attribute \src "libresoc.v:185083.3-185084.53" + wire width 64 $0\core_core_core_msr[63:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $0\core_core_core_oe$next[0:0]$13497 + attribute \src "libresoc.v:185099.3-185100.51" + wire $0\core_core_core_oe[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $0\core_core_core_oe_ok$next[0:0]$13498 + attribute \src "libresoc.v:185101.3-185102.57" + wire $0\core_core_core_oe_ok[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $0\core_core_core_rc$next[0:0]$13499 + attribute \src "libresoc.v:185095.3-185096.51" + wire $0\core_core_core_rc[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $0\core_core_core_rc_ok$next[0:0]$13500 + attribute \src "libresoc.v:185097.3-185098.57" + wire $0\core_core_core_rc_ok[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 13 $0\core_core_core_trapaddr$next[12:0]$13501 + attribute \src "libresoc.v:185127.3-185128.63" + wire width 13 $0\core_core_core_trapaddr[12:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 8 $0\core_core_core_traptype$next[7:0]$13502 + attribute \src "libresoc.v:185107.3-185108.63" + wire width 8 $0\core_core_core_traptype[7:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 3 $0\core_core_cr_in1$next[2:0]$13503 + attribute \src "libresoc.v:185065.3-185066.49" + wire width 3 $0\core_core_cr_in1[2:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $0\core_core_cr_in1_ok$next[0:0]$13504 + attribute \src "libresoc.v:185067.3-185068.55" + wire $0\core_core_cr_in1_ok[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 3 $0\core_core_cr_in2$1$next[2:0]$13505 + attribute \src "libresoc.v:185073.3-185074.55" + wire width 3 $0\core_core_cr_in2$1[2:0]$13331 + attribute \src "libresoc.v:183206.13-183206.40" + wire width 3 $0\core_core_cr_in2$1[2:0]$13828 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 3 $0\core_core_cr_in2$next[2:0]$13506 + attribute \src "libresoc.v:185069.3-185070.49" + wire width 3 $0\core_core_cr_in2[2:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $0\core_core_cr_in2_ok$2$next[0:0]$13507 + attribute \src "libresoc.v:185075.3-185076.61" + wire $0\core_core_cr_in2_ok$2[0:0]$13333 + attribute \src "libresoc.v:183214.7-183214.37" + wire $0\core_core_cr_in2_ok$2[0:0]$13831 + attribute \src "libresoc.v:186282.3-186404.6" + wire $0\core_core_cr_in2_ok$next[0:0]$13508 + attribute \src "libresoc.v:185071.3-185072.55" + wire $0\core_core_cr_in2_ok[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 3 $0\core_core_cr_out$next[2:0]$13509 + attribute \src "libresoc.v:185077.3-185078.49" + wire width 3 $0\core_core_cr_out[2:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $0\core_core_cr_wr_ok$next[0:0]$13510 + attribute \src "libresoc.v:185135.3-185136.53" + wire $0\core_core_cr_wr_ok[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 5 $0\core_core_ea$next[4:0]$13511 + attribute \src "libresoc.v:185017.3-185018.41" + wire width 5 $0\core_core_ea[4:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 3 $0\core_core_fast1$next[2:0]$13512 + attribute \src "libresoc.v:185047.3-185048.47" + wire width 3 $0\core_core_fast1[2:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $0\core_core_fast1_ok$next[0:0]$13513 + attribute \src "libresoc.v:185049.3-185050.53" + wire $0\core_core_fast1_ok[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 3 $0\core_core_fast2$next[2:0]$13514 + attribute \src "libresoc.v:185051.3-185052.47" + wire width 3 $0\core_core_fast2[2:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $0\core_core_fast2_ok$next[0:0]$13515 + attribute \src "libresoc.v:185053.3-185054.53" + wire $0\core_core_fast2_ok[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 3 $0\core_core_fasto1$next[2:0]$13516 + attribute \src "libresoc.v:185055.3-185056.49" + wire width 3 $0\core_core_fasto1[2:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 3 $0\core_core_fasto2$next[2:0]$13517 + attribute \src "libresoc.v:185061.3-185062.49" + wire width 3 $0\core_core_fasto2[2:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $0\core_core_lk$next[0:0]$13518 + attribute \src "libresoc.v:185093.3-185094.41" + wire $0\core_core_lk[0:0] + attribute \src "libresoc.v:185788.3-185819.6" + wire width 64 $0\core_core_pc$next[63:0]$13399 + attribute \src "libresoc.v:185125.3-185126.41" + wire width 64 $0\core_core_pc[63:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 5 $0\core_core_reg1$next[4:0]$13519 + attribute \src "libresoc.v:185021.3-185022.45" + wire width 5 $0\core_core_reg1[4:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $0\core_core_reg1_ok$next[0:0]$13520 + attribute \src "libresoc.v:185023.3-185024.51" + wire $0\core_core_reg1_ok[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 5 $0\core_core_reg2$next[4:0]$13521 + attribute \src "libresoc.v:185025.3-185026.45" + wire width 5 $0\core_core_reg2[4:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $0\core_core_reg2_ok$next[0:0]$13522 + attribute \src "libresoc.v:185027.3-185028.51" + wire $0\core_core_reg2_ok[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 5 $0\core_core_reg3$next[4:0]$13523 + attribute \src "libresoc.v:185029.3-185030.45" + wire width 5 $0\core_core_reg3[4:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $0\core_core_reg3_ok$next[0:0]$13524 + attribute \src "libresoc.v:185031.3-185032.51" + wire $0\core_core_reg3_ok[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 5 $0\core_core_rego$next[4:0]$13525 + attribute \src "libresoc.v:185011.3-185012.45" + wire width 5 $0\core_core_rego[4:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 10 $0\core_core_spr1$next[9:0]$13526 + attribute \src "libresoc.v:185039.3-185040.45" + wire width 10 $0\core_core_spr1[9:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $0\core_core_spr1_ok$next[0:0]$13527 + attribute \src "libresoc.v:185041.3-185042.51" + wire $0\core_core_spr1_ok[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 10 $0\core_core_spro$next[9:0]$13528 + attribute \src "libresoc.v:185033.3-185034.45" + wire width 10 $0\core_core_spro[9:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 3 $0\core_core_xer_in$next[2:0]$13529 + attribute \src "libresoc.v:185043.3-185044.49" + wire width 3 $0\core_core_xer_in[2:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $0\core_cr_out_ok$next[0:0]$13530 + attribute \src "libresoc.v:185079.3-185080.45" + wire $0\core_cr_out_ok[0:0] + attribute \src "libresoc.v:186211.3-186231.6" + wire width 64 $0\core_data_i[63:0] + attribute \src "libresoc.v:185788.3-185819.6" + wire width 64 $0\core_dec$next[63:0]$13400 + attribute \src "libresoc.v:184995.3-184996.33" + wire width 64 $0\core_dec[63:0] + attribute \src "libresoc.v:185875.3-185884.6" + wire width 5 $0\core_dmi__addr[4:0] + attribute \src "libresoc.v:185885.3-185894.6" + wire $0\core_dmi__ren[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $0\core_ea_ok$next[0:0]$13531 + attribute \src "libresoc.v:185019.3-185020.37" + wire $0\core_ea_ok[0:0] + attribute \src "libresoc.v:185788.3-185819.6" + wire $0\core_eint$next[0:0]$13401 + attribute \src "libresoc.v:185163.3-185164.35" + wire $0\core_eint[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $0\core_fasto1_ok$next[0:0]$13532 + attribute \src "libresoc.v:185057.3-185058.45" + wire $0\core_fasto1_ok[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $0\core_fasto2_ok$next[0:0]$13533 + attribute \src "libresoc.v:185063.3-185064.45" + wire $0\core_fasto2_ok[0:0] + attribute \src "libresoc.v:185924.3-185933.6" + wire width 8 $0\core_full_rd2__ren[7:0] + attribute \src "libresoc.v:185963.3-185972.6" + wire width 3 $0\core_full_rd__ren[2:0] + attribute \src "libresoc.v:186071.3-186085.6" + wire width 3 $0\core_issue__addr$11[2:0]$13449 + attribute \src "libresoc.v:186002.3-186016.6" + wire width 3 $0\core_issue__addr[2:0] + attribute \src "libresoc.v:186101.3-186115.6" + wire width 64 $0\core_issue__data_i[63:0] + attribute \src "libresoc.v:186017.3-186031.6" + wire $0\core_issue__ren[0:0] + attribute \src "libresoc.v:186086.3-186100.6" + wire $0\core_issue__wen[0:0] + attribute \src "libresoc.v:185864.3-185874.6" + wire $0\core_issue_i[0:0] + attribute \src "libresoc.v:185844.3-185863.6" + wire $0\core_ivalid_i[0:0] + attribute \src "libresoc.v:185788.3-185819.6" + wire width 64 $0\core_msr$next[63:0]$13402 + attribute \src "libresoc.v:185147.3-185148.33" + wire width 64 $0\core_msr[63:0] + attribute \src "libresoc.v:186232.3-186247.6" + wire width 4 $0\core_msr__ren[3:0] + attribute \src "libresoc.v:186442.3-186478.6" + wire width 32 $0\core_raw_insn_i$next[31:0]$13754 + attribute \src "libresoc.v:185007.3-185008.47" + wire width 32 $0\core_raw_insn_i[31:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $0\core_rego_ok$next[0:0]$13534 + attribute \src "libresoc.v:185013.3-185014.41" + wire $0\core_rego_ok[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $0\core_spro_ok$next[0:0]$13535 + attribute \src "libresoc.v:185035.3-185036.41" + wire $0\core_spro_ok[0:0] + attribute \src "libresoc.v:186679.3-186697.6" + wire $0\core_stopped_i[0:0] + attribute \src "libresoc.v:186190.3-186210.6" + wire width 4 $0\core_wen[3:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $0\core_xer_out$next[0:0]$13536 + attribute \src "libresoc.v:185045.3-185046.41" + wire $0\core_xer_out[0:0] + attribute \src "libresoc.v:185143.3-185144.43" + wire $0\cu_st__rel_o_dly[0:0] + attribute \src "libresoc.v:185934.3-185942.6" + wire $0\d_cr_delay$next[0:0]$13431 + attribute \src "libresoc.v:185059.3-185060.37" + wire $0\d_cr_delay[0:0] + attribute \src "libresoc.v:185895.3-185903.6" + wire $0\d_reg_delay$next[0:0]$13425 + attribute \src "libresoc.v:185081.3-185082.39" + wire $0\d_reg_delay[0:0] + attribute \src "libresoc.v:185973.3-185981.6" + wire $0\d_xer_delay$next[0:0]$13437 + attribute \src "libresoc.v:185037.3-185038.39" + wire $0\d_xer_delay[0:0] + attribute \src "libresoc.v:186698.3-186716.6" + wire $0\dbg_core_stopped_i[0:0] + attribute \src "libresoc.v:185953.3-185962.6" + wire $0\dbg_d_cr_ack[0:0] + attribute \src "libresoc.v:185943.3-185952.6" + wire width 64 $0\dbg_d_cr_data[63:0] + attribute \src "libresoc.v:185914.3-185923.6" + wire $0\dbg_d_gpr_ack[0:0] + attribute \src "libresoc.v:185904.3-185913.6" + wire width 64 $0\dbg_d_gpr_data[63:0] + attribute \src "libresoc.v:185992.3-186001.6" + wire $0\dbg_d_xer_ack[0:0] + attribute \src "libresoc.v:185982.3-185991.6" + wire width 64 $0\dbg_d_xer_data[63:0] + attribute \src "libresoc.v:185730.3-185738.6" + wire width 4 $0\dbg_dmi_addr_i$next[3:0]$13387 + attribute \src "libresoc.v:185161.3-185162.45" + wire width 4 $0\dbg_dmi_addr_i[3:0] + attribute \src "libresoc.v:186248.3-186256.6" + wire width 64 $0\dbg_dmi_din$next[63:0]$13470 + attribute \src "libresoc.v:185155.3-185156.39" + wire width 64 $0\dbg_dmi_din[63:0] + attribute \src "libresoc.v:185739.3-185747.6" + wire $0\dbg_dmi_req_i$next[0:0]$13390 + attribute \src "libresoc.v:185159.3-185160.43" + wire $0\dbg_dmi_req_i[0:0] + attribute \src "libresoc.v:186143.3-186151.6" + wire $0\dbg_dmi_we_i$next[0:0]$13459 + attribute \src "libresoc.v:185157.3-185158.41" + wire $0\dbg_dmi_we_i[0:0] + attribute \src "libresoc.v:186116.3-186131.6" + wire width 64 $0\dec2_cur_dec$next[63:0]$13454 + attribute \src "libresoc.v:184993.3-184994.41" + wire width 64 $0\dec2_cur_dec[63:0] + attribute \src "libresoc.v:186423.3-186431.6" + wire $0\dec2_cur_eint$next[0:0]$13748 + attribute \src "libresoc.v:185149.3-185150.43" + wire $0\dec2_cur_eint[0:0] + attribute \src "libresoc.v:185748.3-185768.6" + wire width 64 $0\dec2_cur_msr$next[63:0]$13393 + attribute \src "libresoc.v:184997.3-184998.41" + wire width 64 $0\dec2_cur_msr[63:0] + attribute \src "libresoc.v:186582.3-186602.6" + wire width 64 $0\dec2_cur_pc$next[63:0]$13769 + attribute \src "libresoc.v:185003.3-185004.39" + wire width 64 $0\dec2_cur_pc[63:0] + attribute \src "libresoc.v:185769.3-185787.6" + wire width 32 $0\dec2_raw_opcode_in[31:0] + attribute \src "libresoc.v:186432.3-186441.6" + wire width 2 $0\delay$next[1:0]$13751 + attribute \src "libresoc.v:185145.3-185146.27" + wire width 2 $0\delay[1:0] + attribute \src "libresoc.v:186032.3-186059.6" + wire width 2 $0\fsm_state$133$next[1:0]$13444 + attribute \src "libresoc.v:185015.3-185016.45" + wire width 2 $0\fsm_state$133[1:0]$13301 + attribute \src "libresoc.v:184191.13-184191.35" + wire width 2 $0\fsm_state$133[1:0]$13880 + attribute \src "libresoc.v:186633.3-186678.6" + wire width 2 $0\fsm_state$next[1:0]$13780 + attribute \src "libresoc.v:184999.3-185000.35" + wire width 2 $0\fsm_state[1:0] + attribute \src "libresoc.v:185820.3-185843.6" + wire width 32 $0\ilatch$next[31:0]$13416 + attribute \src "libresoc.v:185103.3-185104.29" + wire width 32 $0\ilatch[31:0] + attribute \src "libresoc.v:186516.3-186531.6" + wire width 48 $0\imem_a_pc_i[47:0] + attribute \src "libresoc.v:186532.3-186556.6" + wire $0\imem_a_valid_i[0:0] + attribute \src "libresoc.v:186557.3-186581.6" + wire $0\imem_f_valid_i[0:0] + attribute \src "libresoc.v:182859.7-182859.20" wire $0\initial[0:0] - attribute \src "libresoc.v:45774.3-45783.6" - wire $0\pll_18_o[0:0] - attribute \src "libresoc.v:45764.3-45773.6" - wire $0\pll_lck_o[0:0] - attribute \src "libresoc.v:45774.3-45783.6" - wire $1\pll_18_o[0:0] - attribute \src "libresoc.v:45764.3-45773.6" - wire $1\pll_lck_o[0:0] - attribute \src "libresoc.v:45761.17-45761.105" - wire $eq$libresoc.v:45761$1558_Y - attribute \src "libresoc.v:45762.17-45762.105" - wire $eq$libresoc.v:45762$1559_Y - attribute \src "libresoc.v:45763.17-45763.98" - wire $not$libresoc.v:45763$1560_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9" - wire input 1 \clk_24_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" - wire output 5 \clk_pll_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" - wire width 2 input 3 \clk_sel_i - attribute \src "libresoc.v:45742.7-45742.15" + attribute \src "libresoc.v:186405.3-186413.6" + wire $0\jtag_dmi0__ack_o$next[0:0]$13742 + attribute \src "libresoc.v:185153.3-185154.49" + wire $0\jtag_dmi0__ack_o[0:0] + attribute \src "libresoc.v:186414.3-186422.6" + wire width 64 $0\jtag_dmi0__dout$next[63:0]$13745 + attribute \src "libresoc.v:185151.3-185152.47" + wire width 64 $0\jtag_dmi0__dout[63:0] + attribute \src "libresoc.v:186603.3-186632.6" + wire $0\msr_read$next[0:0]$13774 + attribute \src "libresoc.v:185001.3-185002.33" + wire $0\msr_read[0:0] + attribute \src "libresoc.v:186060.3-186070.6" + wire width 64 $0\new_dec[63:0] + attribute \src "libresoc.v:186132.3-186142.6" + wire width 64 $0\new_tb[63:0] + attribute \src "libresoc.v:186161.3-186176.6" + wire width 64 $0\pc[63:0] + attribute \src "libresoc.v:186257.3-186281.6" + wire $0\pc_changed$next[0:0]$13473 + attribute \src "libresoc.v:185139.3-185140.37" + wire $0\pc_changed[0:0] + attribute \src "libresoc.v:186152.3-186160.6" + wire $0\pc_ok_delay$next[0:0]$13462 + attribute \src "libresoc.v:185141.3-185142.39" + wire $0\pc_ok_delay[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 8 $1\core_asmcode$next[7:0]$13537 + attribute \src "libresoc.v:182995.13-182995.33" + wire width 8 $1\core_asmcode[7:0] + attribute \src "libresoc.v:186479.3-186515.6" + wire $1\core_bigendian_i$10$next[0:0]$13761 + attribute \src "libresoc.v:186177.3-186189.6" + wire width 4 $1\core_cia__ren[3:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 64 $1\core_core_core_cia$next[63:0]$13538 + attribute \src "libresoc.v:183009.14-183009.55" + wire width 64 $1\core_core_core_cia[63:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 8 $1\core_core_core_cr_rd$next[7:0]$13539 + attribute \src "libresoc.v:183013.13-183013.41" + wire width 8 $1\core_core_core_cr_rd[7:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $1\core_core_core_cr_rd_ok$next[0:0]$13540 + attribute \src "libresoc.v:183017.7-183017.37" + wire $1\core_core_core_cr_rd_ok[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 8 $1\core_core_core_cr_wr$next[7:0]$13541 + attribute \src "libresoc.v:183021.13-183021.41" + wire width 8 $1\core_core_core_cr_wr[7:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $1\core_core_core_exc_$signal$3$next[0:0]$13542 + attribute \src "libresoc.v:186282.3-186404.6" + wire $1\core_core_core_exc_$signal$4$next[0:0]$13543 + attribute \src "libresoc.v:186282.3-186404.6" + wire $1\core_core_core_exc_$signal$5$next[0:0]$13544 + attribute \src "libresoc.v:186282.3-186404.6" + wire $1\core_core_core_exc_$signal$6$next[0:0]$13545 + attribute \src "libresoc.v:186282.3-186404.6" + wire $1\core_core_core_exc_$signal$7$next[0:0]$13546 + attribute \src "libresoc.v:186282.3-186404.6" + wire $1\core_core_core_exc_$signal$8$next[0:0]$13547 + attribute \src "libresoc.v:186282.3-186404.6" + wire $1\core_core_core_exc_$signal$9$next[0:0]$13548 + attribute \src "libresoc.v:186282.3-186404.6" + wire $1\core_core_core_exc_$signal$next[0:0]$13549 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 12 $1\core_core_core_fn_unit$next[11:0]$13550 + attribute \src "libresoc.v:183070.14-183070.46" + wire width 12 $1\core_core_core_fn_unit[11:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 2 $1\core_core_core_input_carry$next[1:0]$13551 + attribute \src "libresoc.v:183078.13-183078.46" + wire width 2 $1\core_core_core_input_carry[1:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 32 $1\core_core_core_insn$next[31:0]$13552 + attribute \src "libresoc.v:183082.14-183082.41" + wire width 32 $1\core_core_core_insn[31:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 7 $1\core_core_core_insn_type$next[6:0]$13553 + attribute \src "libresoc.v:183160.13-183160.45" + wire width 7 $1\core_core_core_insn_type[6:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $1\core_core_core_is_32bit$next[0:0]$13554 + attribute \src "libresoc.v:183164.7-183164.37" + wire $1\core_core_core_is_32bit[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 64 $1\core_core_core_msr$next[63:0]$13555 + attribute \src "libresoc.v:183168.14-183168.55" + wire width 64 $1\core_core_core_msr[63:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $1\core_core_core_oe$next[0:0]$13556 + attribute \src "libresoc.v:183172.7-183172.31" + wire $1\core_core_core_oe[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $1\core_core_core_oe_ok$next[0:0]$13557 + attribute \src "libresoc.v:183176.7-183176.34" + wire $1\core_core_core_oe_ok[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $1\core_core_core_rc$next[0:0]$13558 + attribute \src "libresoc.v:183180.7-183180.31" + wire $1\core_core_core_rc[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $1\core_core_core_rc_ok$next[0:0]$13559 + attribute \src "libresoc.v:183184.7-183184.34" + wire $1\core_core_core_rc_ok[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 13 $1\core_core_core_trapaddr$next[12:0]$13560 + attribute \src "libresoc.v:183188.14-183188.48" + wire width 13 $1\core_core_core_trapaddr[12:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 8 $1\core_core_core_traptype$next[7:0]$13561 + attribute \src "libresoc.v:183192.13-183192.44" + wire width 8 $1\core_core_core_traptype[7:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 3 $1\core_core_cr_in1$next[2:0]$13562 + attribute \src "libresoc.v:183196.13-183196.36" + wire width 3 $1\core_core_cr_in1[2:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $1\core_core_cr_in1_ok$next[0:0]$13563 + attribute \src "libresoc.v:183200.7-183200.33" + wire $1\core_core_cr_in1_ok[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 3 $1\core_core_cr_in2$1$next[2:0]$13564 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 3 $1\core_core_cr_in2$next[2:0]$13565 + attribute \src "libresoc.v:183204.13-183204.36" + wire width 3 $1\core_core_cr_in2[2:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $1\core_core_cr_in2_ok$2$next[0:0]$13566 + attribute \src "libresoc.v:186282.3-186404.6" + wire $1\core_core_cr_in2_ok$next[0:0]$13567 + attribute \src "libresoc.v:183212.7-183212.33" + wire $1\core_core_cr_in2_ok[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 3 $1\core_core_cr_out$next[2:0]$13568 + attribute \src "libresoc.v:183220.13-183220.36" + wire width 3 $1\core_core_cr_out[2:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $1\core_core_cr_wr_ok$next[0:0]$13569 + attribute \src "libresoc.v:183224.7-183224.32" + wire $1\core_core_cr_wr_ok[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 5 $1\core_core_ea$next[4:0]$13570 + attribute \src "libresoc.v:183228.13-183228.33" + wire width 5 $1\core_core_ea[4:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 3 $1\core_core_fast1$next[2:0]$13571 + attribute \src "libresoc.v:183232.13-183232.35" + wire width 3 $1\core_core_fast1[2:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $1\core_core_fast1_ok$next[0:0]$13572 + attribute \src "libresoc.v:183236.7-183236.32" + wire $1\core_core_fast1_ok[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 3 $1\core_core_fast2$next[2:0]$13573 + attribute \src "libresoc.v:183240.13-183240.35" + wire width 3 $1\core_core_fast2[2:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $1\core_core_fast2_ok$next[0:0]$13574 + attribute \src "libresoc.v:183244.7-183244.32" + wire $1\core_core_fast2_ok[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 3 $1\core_core_fasto1$next[2:0]$13575 + attribute \src "libresoc.v:183248.13-183248.36" + wire width 3 $1\core_core_fasto1[2:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 3 $1\core_core_fasto2$next[2:0]$13576 + attribute \src "libresoc.v:183252.13-183252.36" + wire width 3 $1\core_core_fasto2[2:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $1\core_core_lk$next[0:0]$13577 + attribute \src "libresoc.v:183256.7-183256.26" + wire $1\core_core_lk[0:0] + attribute \src "libresoc.v:185788.3-185819.6" + wire width 64 $1\core_core_pc$next[63:0]$13403 + attribute \src "libresoc.v:183260.14-183260.49" + wire width 64 $1\core_core_pc[63:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 5 $1\core_core_reg1$next[4:0]$13578 + attribute \src "libresoc.v:183264.13-183264.35" + wire width 5 $1\core_core_reg1[4:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $1\core_core_reg1_ok$next[0:0]$13579 + attribute \src "libresoc.v:183268.7-183268.31" + wire $1\core_core_reg1_ok[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 5 $1\core_core_reg2$next[4:0]$13580 + attribute \src "libresoc.v:183272.13-183272.35" + wire width 5 $1\core_core_reg2[4:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $1\core_core_reg2_ok$next[0:0]$13581 + attribute \src "libresoc.v:183276.7-183276.31" + wire $1\core_core_reg2_ok[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 5 $1\core_core_reg3$next[4:0]$13582 + attribute \src "libresoc.v:183280.13-183280.35" + wire width 5 $1\core_core_reg3[4:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $1\core_core_reg3_ok$next[0:0]$13583 + attribute \src "libresoc.v:183284.7-183284.31" + wire $1\core_core_reg3_ok[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 5 $1\core_core_rego$next[4:0]$13584 + attribute \src "libresoc.v:183288.13-183288.35" + wire width 5 $1\core_core_rego[4:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 10 $1\core_core_spr1$next[9:0]$13585 + attribute \src "libresoc.v:183403.13-183403.37" + wire width 10 $1\core_core_spr1[9:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $1\core_core_spr1_ok$next[0:0]$13586 + attribute \src "libresoc.v:183407.7-183407.31" + wire $1\core_core_spr1_ok[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 10 $1\core_core_spro$next[9:0]$13587 + attribute \src "libresoc.v:183522.13-183522.37" + wire width 10 $1\core_core_spro[9:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 3 $1\core_core_xer_in$next[2:0]$13588 + attribute \src "libresoc.v:183528.13-183528.36" + wire width 3 $1\core_core_xer_in[2:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $1\core_cr_out_ok$next[0:0]$13589 + attribute \src "libresoc.v:183536.7-183536.28" + wire $1\core_cr_out_ok[0:0] + attribute \src "libresoc.v:186211.3-186231.6" + wire width 64 $1\core_data_i[63:0] + attribute \src "libresoc.v:185788.3-185819.6" + wire width 64 $1\core_dec$next[63:0]$13404 + attribute \src "libresoc.v:183550.14-183550.45" + wire width 64 $1\core_dec[63:0] + attribute \src "libresoc.v:185875.3-185884.6" + wire width 5 $1\core_dmi__addr[4:0] + attribute \src "libresoc.v:185885.3-185894.6" + wire $1\core_dmi__ren[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $1\core_ea_ok$next[0:0]$13590 + attribute \src "libresoc.v:183560.7-183560.24" + wire $1\core_ea_ok[0:0] + attribute \src "libresoc.v:185788.3-185819.6" + wire $1\core_eint$next[0:0]$13405 + attribute \src "libresoc.v:183564.7-183564.23" + wire $1\core_eint[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $1\core_fasto1_ok$next[0:0]$13591 + attribute \src "libresoc.v:183568.7-183568.28" + wire $1\core_fasto1_ok[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $1\core_fasto2_ok$next[0:0]$13592 + attribute \src "libresoc.v:183572.7-183572.28" + wire $1\core_fasto2_ok[0:0] + attribute \src "libresoc.v:185924.3-185933.6" + wire width 8 $1\core_full_rd2__ren[7:0] + attribute \src "libresoc.v:185963.3-185972.6" + wire width 3 $1\core_full_rd__ren[2:0] + attribute \src "libresoc.v:186071.3-186085.6" + wire width 3 $1\core_issue__addr$11[2:0]$13450 + attribute \src "libresoc.v:186002.3-186016.6" + wire width 3 $1\core_issue__addr[2:0] + attribute \src "libresoc.v:186101.3-186115.6" + wire width 64 $1\core_issue__data_i[63:0] + attribute \src "libresoc.v:186017.3-186031.6" + wire $1\core_issue__ren[0:0] + attribute \src "libresoc.v:186086.3-186100.6" + wire $1\core_issue__wen[0:0] + attribute \src "libresoc.v:185864.3-185874.6" + wire $1\core_issue_i[0:0] + attribute \src "libresoc.v:185844.3-185863.6" + wire $1\core_ivalid_i[0:0] + attribute \src "libresoc.v:185788.3-185819.6" + wire width 64 $1\core_msr$next[63:0]$13406 + attribute \src "libresoc.v:183600.14-183600.45" + wire width 64 $1\core_msr[63:0] + attribute \src "libresoc.v:186232.3-186247.6" + wire width 4 $1\core_msr__ren[3:0] + attribute \src "libresoc.v:186442.3-186478.6" + wire width 32 $1\core_raw_insn_i$next[31:0]$13755 + attribute \src "libresoc.v:183608.14-183608.37" + wire width 32 $1\core_raw_insn_i[31:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $1\core_rego_ok$next[0:0]$13593 + attribute \src "libresoc.v:183612.7-183612.26" + wire $1\core_rego_ok[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $1\core_spro_ok$next[0:0]$13594 + attribute \src "libresoc.v:183616.7-183616.26" + wire $1\core_spro_ok[0:0] + attribute \src "libresoc.v:186679.3-186697.6" + wire $1\core_stopped_i[0:0] + attribute \src "libresoc.v:186190.3-186210.6" + wire width 4 $1\core_wen[3:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $1\core_xer_out$next[0:0]$13595 + attribute \src "libresoc.v:183628.7-183628.26" + wire $1\core_xer_out[0:0] + attribute \src "libresoc.v:183634.7-183634.30" + wire $1\cu_st__rel_o_dly[0:0] + attribute \src "libresoc.v:185934.3-185942.6" + wire $1\d_cr_delay$next[0:0]$13432 + attribute \src "libresoc.v:183640.7-183640.24" + wire $1\d_cr_delay[0:0] + attribute \src "libresoc.v:185895.3-185903.6" + wire $1\d_reg_delay$next[0:0]$13426 + attribute \src "libresoc.v:183644.7-183644.25" + wire $1\d_reg_delay[0:0] + attribute \src "libresoc.v:185973.3-185981.6" + wire $1\d_xer_delay$next[0:0]$13438 + attribute \src "libresoc.v:183648.7-183648.25" + wire $1\d_xer_delay[0:0] + attribute \src "libresoc.v:186698.3-186716.6" + wire $1\dbg_core_stopped_i[0:0] + attribute \src "libresoc.v:185953.3-185962.6" + wire $1\dbg_d_cr_ack[0:0] + attribute \src "libresoc.v:185943.3-185952.6" + wire width 64 $1\dbg_d_cr_data[63:0] + attribute \src "libresoc.v:185914.3-185923.6" + wire $1\dbg_d_gpr_ack[0:0] + attribute \src "libresoc.v:185904.3-185913.6" + wire width 64 $1\dbg_d_gpr_data[63:0] + attribute \src "libresoc.v:185992.3-186001.6" + wire $1\dbg_d_xer_ack[0:0] + attribute \src "libresoc.v:185982.3-185991.6" + wire width 64 $1\dbg_d_xer_data[63:0] + attribute \src "libresoc.v:185730.3-185738.6" + wire width 4 $1\dbg_dmi_addr_i$next[3:0]$13388 + attribute \src "libresoc.v:183684.13-183684.34" + wire width 4 $1\dbg_dmi_addr_i[3:0] + attribute \src "libresoc.v:186248.3-186256.6" + wire width 64 $1\dbg_dmi_din$next[63:0]$13471 + attribute \src "libresoc.v:183688.14-183688.48" + wire width 64 $1\dbg_dmi_din[63:0] + attribute \src "libresoc.v:185739.3-185747.6" + wire $1\dbg_dmi_req_i$next[0:0]$13391 + attribute \src "libresoc.v:183694.7-183694.27" + wire $1\dbg_dmi_req_i[0:0] + attribute \src "libresoc.v:186143.3-186151.6" + wire $1\dbg_dmi_we_i$next[0:0]$13460 + attribute \src "libresoc.v:183698.7-183698.26" + wire $1\dbg_dmi_we_i[0:0] + attribute \src "libresoc.v:186116.3-186131.6" + wire width 64 $1\dec2_cur_dec$next[63:0]$13455 + attribute \src "libresoc.v:183752.14-183752.49" + wire width 64 $1\dec2_cur_dec[63:0] + attribute \src "libresoc.v:186423.3-186431.6" + wire $1\dec2_cur_eint$next[0:0]$13749 + attribute \src "libresoc.v:183756.7-183756.27" + wire $1\dec2_cur_eint[0:0] + attribute \src "libresoc.v:185748.3-185768.6" + wire width 64 $1\dec2_cur_msr$next[63:0]$13394 + attribute \src "libresoc.v:183760.14-183760.49" + wire width 64 $1\dec2_cur_msr[63:0] + attribute \src "libresoc.v:186582.3-186602.6" + wire width 64 $1\dec2_cur_pc$next[63:0]$13770 + attribute \src "libresoc.v:183764.14-183764.48" + wire width 64 $1\dec2_cur_pc[63:0] + attribute \src "libresoc.v:185769.3-185787.6" + wire width 32 $1\dec2_raw_opcode_in[31:0] + attribute \src "libresoc.v:186432.3-186441.6" + wire width 2 $1\delay$next[1:0]$13752 + attribute \src "libresoc.v:184173.13-184173.25" + wire width 2 $1\delay[1:0] + attribute \src "libresoc.v:186032.3-186059.6" + wire width 2 $1\fsm_state$133$next[1:0]$13445 + attribute \src "libresoc.v:186633.3-186678.6" + wire width 2 $1\fsm_state$next[1:0]$13781 + attribute \src "libresoc.v:184189.13-184189.29" + wire width 2 $1\fsm_state[1:0] + attribute \src "libresoc.v:185820.3-185843.6" + wire width 32 $1\ilatch$next[31:0]$13417 + attribute \src "libresoc.v:184433.14-184433.28" + wire width 32 $1\ilatch[31:0] + attribute \src "libresoc.v:186516.3-186531.6" + wire width 48 $1\imem_a_pc_i[47:0] + attribute \src "libresoc.v:186532.3-186556.6" + wire $1\imem_a_valid_i[0:0] + attribute \src "libresoc.v:186557.3-186581.6" + wire $1\imem_f_valid_i[0:0] + attribute \src "libresoc.v:186405.3-186413.6" + wire $1\jtag_dmi0__ack_o$next[0:0]$13743 + attribute \src "libresoc.v:184451.7-184451.30" + wire $1\jtag_dmi0__ack_o[0:0] + attribute \src "libresoc.v:186414.3-186422.6" + wire width 64 $1\jtag_dmi0__dout$next[63:0]$13746 + attribute \src "libresoc.v:184459.14-184459.52" + wire width 64 $1\jtag_dmi0__dout[63:0] + attribute \src "libresoc.v:186603.3-186632.6" + wire $1\msr_read$next[0:0]$13775 + attribute \src "libresoc.v:184515.7-184515.22" + wire $1\msr_read[0:0] + attribute \src "libresoc.v:186060.3-186070.6" + wire width 64 $1\new_dec[63:0] + attribute \src "libresoc.v:186132.3-186142.6" + wire width 64 $1\new_tb[63:0] + attribute \src "libresoc.v:186161.3-186176.6" + wire width 64 $1\pc[63:0] + attribute \src "libresoc.v:186257.3-186281.6" + wire $1\pc_changed$next[0:0]$13474 + attribute \src "libresoc.v:184543.7-184543.24" + wire $1\pc_changed[0:0] + attribute \src "libresoc.v:186152.3-186160.6" + wire $1\pc_ok_delay$next[0:0]$13463 + attribute \src "libresoc.v:184553.7-184553.25" + wire $1\pc_ok_delay[0:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire width 8 $2\core_asmcode$next[7:0]$13596 + attribute \src "libresoc.v:186479.3-186515.6" + wire $2\core_bigendian_i$10$next[0:0]$13762 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 64 $2\core_core_core_cia$next[63:0]$13597 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 8 $2\core_core_core_cr_rd$next[7:0]$13598 + attribute \src "libresoc.v:186282.3-186404.6" + wire $2\core_core_core_cr_rd_ok$next[0:0]$13599 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 8 $2\core_core_core_cr_wr$next[7:0]$13600 + attribute \src "libresoc.v:186282.3-186404.6" + wire $2\core_core_core_exc_$signal$3$next[0:0]$13601 + attribute \src "libresoc.v:186282.3-186404.6" + wire $2\core_core_core_exc_$signal$4$next[0:0]$13602 + attribute \src "libresoc.v:186282.3-186404.6" + wire $2\core_core_core_exc_$signal$5$next[0:0]$13603 + attribute \src "libresoc.v:186282.3-186404.6" + wire $2\core_core_core_exc_$signal$6$next[0:0]$13604 + attribute \src "libresoc.v:186282.3-186404.6" + wire $2\core_core_core_exc_$signal$7$next[0:0]$13605 + attribute \src "libresoc.v:186282.3-186404.6" + wire $2\core_core_core_exc_$signal$8$next[0:0]$13606 + attribute \src "libresoc.v:186282.3-186404.6" + wire $2\core_core_core_exc_$signal$9$next[0:0]$13607 + attribute \src "libresoc.v:186282.3-186404.6" + wire $2\core_core_core_exc_$signal$next[0:0]$13608 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 12 $2\core_core_core_fn_unit$next[11:0]$13609 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 2 $2\core_core_core_input_carry$next[1:0]$13610 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 32 $2\core_core_core_insn$next[31:0]$13611 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 7 $2\core_core_core_insn_type$next[6:0]$13612 + attribute \src "libresoc.v:186282.3-186404.6" + wire $2\core_core_core_is_32bit$next[0:0]$13613 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 64 $2\core_core_core_msr$next[63:0]$13614 + attribute \src "libresoc.v:186282.3-186404.6" + wire $2\core_core_core_oe$next[0:0]$13615 + attribute \src "libresoc.v:186282.3-186404.6" + wire $2\core_core_core_oe_ok$next[0:0]$13616 + attribute \src "libresoc.v:186282.3-186404.6" + wire $2\core_core_core_rc$next[0:0]$13617 + attribute \src "libresoc.v:186282.3-186404.6" + wire $2\core_core_core_rc_ok$next[0:0]$13618 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 13 $2\core_core_core_trapaddr$next[12:0]$13619 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 8 $2\core_core_core_traptype$next[7:0]$13620 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 3 $2\core_core_cr_in1$next[2:0]$13621 + attribute \src "libresoc.v:186282.3-186404.6" + wire $2\core_core_cr_in1_ok$next[0:0]$13622 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 3 $2\core_core_cr_in2$1$next[2:0]$13623 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 3 $2\core_core_cr_in2$next[2:0]$13624 + attribute \src "libresoc.v:186282.3-186404.6" + wire $2\core_core_cr_in2_ok$2$next[0:0]$13625 + attribute \src "libresoc.v:186282.3-186404.6" + wire $2\core_core_cr_in2_ok$next[0:0]$13626 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 3 $2\core_core_cr_out$next[2:0]$13627 + attribute \src "libresoc.v:186282.3-186404.6" + wire $2\core_core_cr_wr_ok$next[0:0]$13628 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 5 $2\core_core_ea$next[4:0]$13629 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 3 $2\core_core_fast1$next[2:0]$13630 + attribute \src "libresoc.v:186282.3-186404.6" + wire $2\core_core_fast1_ok$next[0:0]$13631 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 3 $2\core_core_fast2$next[2:0]$13632 + attribute \src "libresoc.v:186282.3-186404.6" + wire $2\core_core_fast2_ok$next[0:0]$13633 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 3 $2\core_core_fasto1$next[2:0]$13634 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 3 $2\core_core_fasto2$next[2:0]$13635 + attribute \src "libresoc.v:186282.3-186404.6" + wire $2\core_core_lk$next[0:0]$13636 + attribute \src "libresoc.v:185788.3-185819.6" + wire width 64 $2\core_core_pc$next[63:0]$13407 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 5 $2\core_core_reg1$next[4:0]$13637 + attribute \src "libresoc.v:186282.3-186404.6" + wire $2\core_core_reg1_ok$next[0:0]$13638 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 5 $2\core_core_reg2$next[4:0]$13639 + attribute \src "libresoc.v:186282.3-186404.6" + wire $2\core_core_reg2_ok$next[0:0]$13640 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 5 $2\core_core_reg3$next[4:0]$13641 + attribute \src "libresoc.v:186282.3-186404.6" + wire $2\core_core_reg3_ok$next[0:0]$13642 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 5 $2\core_core_rego$next[4:0]$13643 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 10 $2\core_core_spr1$next[9:0]$13644 + attribute \src "libresoc.v:186282.3-186404.6" + wire $2\core_core_spr1_ok$next[0:0]$13645 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 10 $2\core_core_spro$next[9:0]$13646 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 3 $2\core_core_xer_in$next[2:0]$13647 + attribute \src "libresoc.v:186282.3-186404.6" + wire $2\core_cr_out_ok$next[0:0]$13648 + attribute \src "libresoc.v:186211.3-186231.6" + wire width 64 $2\core_data_i[63:0] + attribute \src "libresoc.v:185788.3-185819.6" + wire width 64 $2\core_dec$next[63:0]$13408 + attribute \src "libresoc.v:186282.3-186404.6" + wire $2\core_ea_ok$next[0:0]$13649 + attribute \src "libresoc.v:185788.3-185819.6" + wire $2\core_eint$next[0:0]$13409 + attribute \src "libresoc.v:186282.3-186404.6" + wire $2\core_fasto1_ok$next[0:0]$13650 + attribute \src "libresoc.v:186282.3-186404.6" + wire $2\core_fasto2_ok$next[0:0]$13651 + attribute \src "libresoc.v:185844.3-185863.6" + wire $2\core_ivalid_i[0:0] + attribute \src "libresoc.v:185788.3-185819.6" + wire width 64 $2\core_msr$next[63:0]$13410 + attribute \src "libresoc.v:186232.3-186247.6" + wire width 4 $2\core_msr__ren[3:0] + attribute \src "libresoc.v:186442.3-186478.6" + wire width 32 $2\core_raw_insn_i$next[31:0]$13756 + attribute \src "libresoc.v:186282.3-186404.6" + wire $2\core_rego_ok$next[0:0]$13652 + attribute \src "libresoc.v:186282.3-186404.6" + wire $2\core_spro_ok$next[0:0]$13653 + attribute \src "libresoc.v:186679.3-186697.6" + wire $2\core_stopped_i[0:0] + attribute \src "libresoc.v:186190.3-186210.6" + wire width 4 $2\core_wen[3:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $2\core_xer_out$next[0:0]$13654 + attribute \src "libresoc.v:186698.3-186716.6" + wire $2\dbg_core_stopped_i[0:0] + attribute \src "libresoc.v:186116.3-186131.6" + wire width 64 $2\dec2_cur_dec$next[63:0]$13456 + attribute \src "libresoc.v:185748.3-185768.6" + wire width 64 $2\dec2_cur_msr$next[63:0]$13395 + attribute \src "libresoc.v:186582.3-186602.6" + wire width 64 $2\dec2_cur_pc$next[63:0]$13771 + attribute \src "libresoc.v:185769.3-185787.6" + wire width 32 $2\dec2_raw_opcode_in[31:0] + attribute \src "libresoc.v:186032.3-186059.6" + wire width 2 $2\fsm_state$133$next[1:0]$13446 + attribute \src "libresoc.v:186633.3-186678.6" + wire width 2 $2\fsm_state$next[1:0]$13782 + attribute \src "libresoc.v:185820.3-185843.6" + wire width 32 $2\ilatch$next[31:0]$13418 + attribute \src "libresoc.v:186516.3-186531.6" + wire width 48 $2\imem_a_pc_i[47:0] + attribute \src "libresoc.v:186532.3-186556.6" + wire $2\imem_a_valid_i[0:0] + attribute \src "libresoc.v:186557.3-186581.6" + wire $2\imem_f_valid_i[0:0] + attribute \src "libresoc.v:186603.3-186632.6" + wire $2\msr_read$next[0:0]$13776 + attribute \src "libresoc.v:186161.3-186176.6" + wire width 64 $2\pc[63:0] + attribute \src "libresoc.v:186257.3-186281.6" + wire $2\pc_changed$next[0:0]$13475 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 8 $3\core_asmcode$next[7:0]$13655 + attribute \src "libresoc.v:186479.3-186515.6" + wire $3\core_bigendian_i$10$next[0:0]$13763 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 64 $3\core_core_core_cia$next[63:0]$13656 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 8 $3\core_core_core_cr_rd$next[7:0]$13657 + attribute \src "libresoc.v:186282.3-186404.6" + wire $3\core_core_core_cr_rd_ok$next[0:0]$13658 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 8 $3\core_core_core_cr_wr$next[7:0]$13659 + attribute \src "libresoc.v:186282.3-186404.6" + wire $3\core_core_core_exc_$signal$3$next[0:0]$13660 + attribute \src "libresoc.v:186282.3-186404.6" + wire $3\core_core_core_exc_$signal$4$next[0:0]$13661 + attribute \src "libresoc.v:186282.3-186404.6" + wire $3\core_core_core_exc_$signal$5$next[0:0]$13662 + attribute \src "libresoc.v:186282.3-186404.6" + wire $3\core_core_core_exc_$signal$6$next[0:0]$13663 + attribute \src "libresoc.v:186282.3-186404.6" + wire $3\core_core_core_exc_$signal$7$next[0:0]$13664 + attribute \src "libresoc.v:186282.3-186404.6" + wire $3\core_core_core_exc_$signal$8$next[0:0]$13665 + attribute \src "libresoc.v:186282.3-186404.6" + wire $3\core_core_core_exc_$signal$9$next[0:0]$13666 + attribute \src "libresoc.v:186282.3-186404.6" + wire $3\core_core_core_exc_$signal$next[0:0]$13667 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 12 $3\core_core_core_fn_unit$next[11:0]$13668 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 2 $3\core_core_core_input_carry$next[1:0]$13669 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 32 $3\core_core_core_insn$next[31:0]$13670 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 7 $3\core_core_core_insn_type$next[6:0]$13671 + attribute \src "libresoc.v:186282.3-186404.6" + wire $3\core_core_core_is_32bit$next[0:0]$13672 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 64 $3\core_core_core_msr$next[63:0]$13673 + attribute \src "libresoc.v:186282.3-186404.6" + wire $3\core_core_core_oe$next[0:0]$13674 + attribute \src "libresoc.v:186282.3-186404.6" + wire $3\core_core_core_oe_ok$next[0:0]$13675 + attribute \src "libresoc.v:186282.3-186404.6" + wire $3\core_core_core_rc$next[0:0]$13676 + attribute \src "libresoc.v:186282.3-186404.6" + wire $3\core_core_core_rc_ok$next[0:0]$13677 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 13 $3\core_core_core_trapaddr$next[12:0]$13678 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 8 $3\core_core_core_traptype$next[7:0]$13679 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 3 $3\core_core_cr_in1$next[2:0]$13680 + attribute \src "libresoc.v:186282.3-186404.6" + wire $3\core_core_cr_in1_ok$next[0:0]$13681 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 3 $3\core_core_cr_in2$1$next[2:0]$13682 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 3 $3\core_core_cr_in2$next[2:0]$13683 + attribute \src "libresoc.v:186282.3-186404.6" + wire $3\core_core_cr_in2_ok$2$next[0:0]$13684 + attribute \src "libresoc.v:186282.3-186404.6" + wire $3\core_core_cr_in2_ok$next[0:0]$13685 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 3 $3\core_core_cr_out$next[2:0]$13686 + attribute \src "libresoc.v:186282.3-186404.6" + wire $3\core_core_cr_wr_ok$next[0:0]$13687 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 5 $3\core_core_ea$next[4:0]$13688 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 3 $3\core_core_fast1$next[2:0]$13689 + attribute \src "libresoc.v:186282.3-186404.6" + wire $3\core_core_fast1_ok$next[0:0]$13690 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 3 $3\core_core_fast2$next[2:0]$13691 + attribute \src "libresoc.v:186282.3-186404.6" + wire $3\core_core_fast2_ok$next[0:0]$13692 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 3 $3\core_core_fasto1$next[2:0]$13693 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 3 $3\core_core_fasto2$next[2:0]$13694 + attribute \src "libresoc.v:186282.3-186404.6" + wire $3\core_core_lk$next[0:0]$13695 + attribute \src "libresoc.v:185788.3-185819.6" + wire width 64 $3\core_core_pc$next[63:0]$13411 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 5 $3\core_core_reg1$next[4:0]$13696 + attribute \src "libresoc.v:186282.3-186404.6" + wire $3\core_core_reg1_ok$next[0:0]$13697 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 5 $3\core_core_reg2$next[4:0]$13698 + attribute \src "libresoc.v:186282.3-186404.6" + wire $3\core_core_reg2_ok$next[0:0]$13699 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 5 $3\core_core_reg3$next[4:0]$13700 + attribute \src "libresoc.v:186282.3-186404.6" + wire $3\core_core_reg3_ok$next[0:0]$13701 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 5 $3\core_core_rego$next[4:0]$13702 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 10 $3\core_core_spr1$next[9:0]$13703 + attribute \src "libresoc.v:186282.3-186404.6" + wire $3\core_core_spr1_ok$next[0:0]$13704 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 10 $3\core_core_spro$next[9:0]$13705 + attribute \src "libresoc.v:186282.3-186404.6" + wire width 3 $3\core_core_xer_in$next[2:0]$13706 + attribute \src "libresoc.v:186282.3-186404.6" + wire $3\core_cr_out_ok$next[0:0]$13707 + attribute \src "libresoc.v:186211.3-186231.6" + wire width 64 $3\core_data_i[63:0] + attribute \src "libresoc.v:185788.3-185819.6" + wire width 64 $3\core_dec$next[63:0]$13412 + attribute \src "libresoc.v:186282.3-186404.6" + wire $3\core_ea_ok$next[0:0]$13708 + attribute \src "libresoc.v:185788.3-185819.6" + wire $3\core_eint$next[0:0]$13413 + attribute \src "libresoc.v:186282.3-186404.6" + wire $3\core_fasto1_ok$next[0:0]$13709 + attribute \src "libresoc.v:186282.3-186404.6" + wire $3\core_fasto2_ok$next[0:0]$13710 + attribute \src "libresoc.v:185788.3-185819.6" + wire width 64 $3\core_msr$next[63:0]$13414 + attribute \src "libresoc.v:186442.3-186478.6" + wire width 32 $3\core_raw_insn_i$next[31:0]$13757 + attribute \src "libresoc.v:186282.3-186404.6" + wire $3\core_rego_ok$next[0:0]$13711 + attribute \src "libresoc.v:186282.3-186404.6" + wire $3\core_spro_ok$next[0:0]$13712 + attribute \src "libresoc.v:186190.3-186210.6" + wire width 4 $3\core_wen[3:0] + attribute \src "libresoc.v:186282.3-186404.6" + wire $3\core_xer_out$next[0:0]$13713 + attribute \src "libresoc.v:185748.3-185768.6" + wire width 64 $3\dec2_cur_msr$next[63:0]$13396 + attribute \src "libresoc.v:186582.3-186602.6" + wire width 64 $3\dec2_cur_pc$next[63:0]$13772 + attribute \src "libresoc.v:186633.3-186678.6" + wire width 2 $3\fsm_state$next[1:0]$13783 + attribute \src "libresoc.v:185820.3-185843.6" + wire width 32 $3\ilatch$next[31:0]$13419 + attribute \src "libresoc.v:186532.3-186556.6" + wire $3\imem_a_valid_i[0:0] + attribute \src "libresoc.v:186557.3-186581.6" + wire $3\imem_f_valid_i[0:0] + attribute \src "libresoc.v:186603.3-186632.6" + wire $3\msr_read$next[0:0]$13777 + attribute \src "libresoc.v:186257.3-186281.6" + wire $3\pc_changed$next[0:0]$13476 + attribute \src "libresoc.v:186479.3-186515.6" + wire $4\core_bigendian_i$10$next[0:0]$13764 + attribute \src "libresoc.v:186282.3-186404.6" + wire $4\core_core_core_cr_rd_ok$next[0:0]$13714 + attribute \src "libresoc.v:186282.3-186404.6" + wire $4\core_core_core_exc_$signal$3$next[0:0]$13715 + attribute \src "libresoc.v:186282.3-186404.6" + wire $4\core_core_core_exc_$signal$4$next[0:0]$13716 + attribute \src "libresoc.v:186282.3-186404.6" + wire $4\core_core_core_exc_$signal$5$next[0:0]$13717 + attribute \src "libresoc.v:186282.3-186404.6" + wire $4\core_core_core_exc_$signal$6$next[0:0]$13718 + attribute \src "libresoc.v:186282.3-186404.6" + wire $4\core_core_core_exc_$signal$7$next[0:0]$13719 + attribute \src "libresoc.v:186282.3-186404.6" + wire $4\core_core_core_exc_$signal$8$next[0:0]$13720 + attribute \src "libresoc.v:186282.3-186404.6" + wire $4\core_core_core_exc_$signal$9$next[0:0]$13721 + attribute \src "libresoc.v:186282.3-186404.6" + wire $4\core_core_core_exc_$signal$next[0:0]$13722 + attribute \src "libresoc.v:186282.3-186404.6" + wire $4\core_core_core_oe_ok$next[0:0]$13723 + attribute \src "libresoc.v:186282.3-186404.6" + wire $4\core_core_core_rc_ok$next[0:0]$13724 + attribute \src "libresoc.v:186282.3-186404.6" + wire $4\core_core_cr_in1_ok$next[0:0]$13725 + attribute \src "libresoc.v:186282.3-186404.6" + wire $4\core_core_cr_in2_ok$2$next[0:0]$13726 + attribute \src "libresoc.v:186282.3-186404.6" + wire $4\core_core_cr_in2_ok$next[0:0]$13727 + attribute \src "libresoc.v:186282.3-186404.6" + wire $4\core_core_cr_wr_ok$next[0:0]$13728 + attribute \src "libresoc.v:186282.3-186404.6" + wire $4\core_core_fast1_ok$next[0:0]$13729 + attribute \src "libresoc.v:186282.3-186404.6" + wire $4\core_core_fast2_ok$next[0:0]$13730 + attribute \src "libresoc.v:186282.3-186404.6" + wire $4\core_core_reg1_ok$next[0:0]$13731 + attribute \src "libresoc.v:186282.3-186404.6" + wire $4\core_core_reg2_ok$next[0:0]$13732 + attribute \src "libresoc.v:186282.3-186404.6" + wire $4\core_core_reg3_ok$next[0:0]$13733 + attribute \src "libresoc.v:186282.3-186404.6" + wire $4\core_core_spr1_ok$next[0:0]$13734 + attribute \src "libresoc.v:186282.3-186404.6" + wire $4\core_cr_out_ok$next[0:0]$13735 + attribute \src "libresoc.v:186282.3-186404.6" + wire $4\core_ea_ok$next[0:0]$13736 + attribute \src "libresoc.v:186282.3-186404.6" + wire $4\core_fasto1_ok$next[0:0]$13737 + attribute \src "libresoc.v:186282.3-186404.6" + wire $4\core_fasto2_ok$next[0:0]$13738 + attribute \src "libresoc.v:186442.3-186478.6" + wire width 32 $4\core_raw_insn_i$next[31:0]$13758 + attribute \src "libresoc.v:186282.3-186404.6" + wire $4\core_rego_ok$next[0:0]$13739 + attribute \src "libresoc.v:186282.3-186404.6" + wire $4\core_spro_ok$next[0:0]$13740 + attribute \src "libresoc.v:186633.3-186678.6" + wire width 2 $4\fsm_state$next[1:0]$13784 + attribute \src "libresoc.v:186603.3-186632.6" + wire $4\msr_read$next[0:0]$13778 + attribute \src "libresoc.v:186633.3-186678.6" + wire width 2 $5\fsm_state$next[1:0]$13785 + attribute \src "libresoc.v:184954.19-184954.115" + wire width 65 $add$libresoc.v:184954$13249_Y + attribute \src "libresoc.v:184962.18-184962.107" + wire width 65 $add$libresoc.v:184962$13257_Y + attribute \src "libresoc.v:184937.19-184937.102" + wire $and$libresoc.v:184937$13230_Y + attribute \src "libresoc.v:184941.19-184941.104" + wire $and$libresoc.v:184941$13234_Y + attribute \src "libresoc.v:184944.19-184944.104" + wire $and$libresoc.v:184944$13237_Y + attribute \src "libresoc.v:184961.18-184961.109" + wire $and$libresoc.v:184961$13256_Y + attribute \src "libresoc.v:184970.18-184970.101" + wire $and$libresoc.v:184970$13265_Y + attribute \src "libresoc.v:184971.18-184971.114" + wire width 4 $and$libresoc.v:184971$13266_Y + attribute \src "libresoc.v:184978.18-184978.101" + wire $and$libresoc.v:184978$13273_Y + attribute \src "libresoc.v:184981.18-184981.101" + wire $and$libresoc.v:184981$13276_Y + attribute \src "libresoc.v:184984.18-184984.101" + wire $and$libresoc.v:184984$13279_Y + attribute \src "libresoc.v:184987.18-184987.101" + wire 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_reg2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 \dec2_reg3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_reg3_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 \dec2_rego + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_rego_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 \dec2_spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_spr1_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 \dec2_spro + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_spro_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" + wire width 13 \dec2_trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 8 \dec2_traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104" + wire width 3 \dec2_xer_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" + wire \dec2_xer_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:173" + wire width 2 \delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:173" + wire width 2 \delay$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 179 \eint_0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 24 \eint_0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 180 \eint_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 25 \eint_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 181 \eint_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 26 \eint_2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + wire width 2 \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" + wire width 2 \fsm_state$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" + wire width 2 \fsm_state$133$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + wire width 2 \fsm_state$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 188 \gpio_e10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 34 \gpio_e10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 35 \gpio_e10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 33 \gpio_e10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 189 \gpio_e10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 190 \gpio_e10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 191 \gpio_e11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 37 \gpio_e11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 38 \gpio_e11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 36 \gpio_e11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 192 \gpio_e11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 193 \gpio_e11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 194 \gpio_e12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 40 \gpio_e12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 41 \gpio_e12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 39 \gpio_e12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 195 \gpio_e12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 196 \gpio_e12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 197 \gpio_e13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 43 \gpio_e13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 44 \gpio_e13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 42 \gpio_e13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 198 \gpio_e13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 199 \gpio_e13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 200 \gpio_e14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 46 \gpio_e14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 47 \gpio_e14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 45 \gpio_e14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 201 \gpio_e14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 202 \gpio_e14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 203 \gpio_e15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 49 \gpio_e15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 50 \gpio_e15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 48 \gpio_e15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 204 \gpio_e15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 205 \gpio_e15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 182 \gpio_e8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 28 \gpio_e8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 29 \gpio_e8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 27 \gpio_e8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 183 \gpio_e8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 184 \gpio_e8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 185 \gpio_e9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 31 \gpio_e9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 32 \gpio_e9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 30 \gpio_e9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 186 \gpio_e9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 187 \gpio_e9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 206 \gpio_s0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 52 \gpio_s0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 53 \gpio_s0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 51 \gpio_s0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 207 \gpio_s0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 208 \gpio_s0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 209 \gpio_s1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 55 \gpio_s1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 56 \gpio_s1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 54 \gpio_s1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 210 \gpio_s1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 211 \gpio_s1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 212 \gpio_s2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 58 \gpio_s2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 59 \gpio_s2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 57 \gpio_s2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 213 \gpio_s2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 214 \gpio_s2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 215 \gpio_s3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 61 \gpio_s3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 62 \gpio_s3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 60 \gpio_s3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 216 \gpio_s3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 217 \gpio_s3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 218 \gpio_s4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 64 \gpio_s4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 65 \gpio_s4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 63 \gpio_s4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 219 \gpio_s4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 220 \gpio_s4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 221 \gpio_s5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 67 \gpio_s5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 68 \gpio_s5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 66 \gpio_s5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 222 \gpio_s5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 223 \gpio_s5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 224 \gpio_s6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 70 \gpio_s6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 71 \gpio_s6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 69 \gpio_s6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 225 \gpio_s6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 226 \gpio_s6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 227 \gpio_s7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 73 \gpio_s7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 74 \gpio_s7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 72 \gpio_s7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 228 \gpio_s7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 229 \gpio_s7__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 18 \ibus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 45 output 23 \ibus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 17 \ibus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 64 input 22 \ibus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 19 \ibus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 8 output 21 \ibus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 20 \ibus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire output 344 \icp_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 28 input 350 \icp_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 345 \icp_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 output 346 \icp_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 input 347 \icp_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 4 input 351 \icp_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 348 \icp_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 349 \icp_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire output 357 \ics_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 28 input 352 \ics_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 354 \ics_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 output 356 \ics_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 input 358 \ics_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 355 \ics_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 359 \ics_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:197" + wire width 32 \ilatch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:197" + wire width 32 \ilatch$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" + wire width 48 \imem_a_pc_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" + wire \imem_a_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" + wire \imem_f_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33" + wire width 64 \imem_f_instr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" + wire \imem_f_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" + wire \imem_wb_icache_en + attribute \src "libresoc.v:182859.7-182859.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" - wire output 2 \pll_18_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" - wire output 4 \pll_lck_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" - cell $eq $eq$libresoc.v:45761$1558 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" + wire width 16 input 353 \int_level_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire \jtag_dmi0__ack_o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire \jtag_dmi0__ack_o$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 4 \jtag_dmi0__addr_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 \jtag_dmi0__din + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 \jtag_dmi0__dout + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 \jtag_dmi0__dout$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire \jtag_dmi0__req_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire \jtag_dmi0__we_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire input 340 \jtag_wb__ack + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 29 output 334 \jtag_wb__adr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 336 \jtag_wb__cyc + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 input 341 \jtag_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 output 339 \jtag_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 335 \jtag_wb__sel + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 337 \jtag_wb__stb + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 338 \jtag_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 75 \mspi0_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 230 \mspi0_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 76 \mspi0_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 231 \mspi0_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 233 \mspi0_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 78 \mspi0_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 77 \mspi0_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 232 \mspi0_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 79 \mspi1_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 234 \mspi1_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 80 \mspi1_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 235 \mspi1_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 237 \mspi1_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 82 \mspi1_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 81 \mspi1_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 236 \mspi1_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:223" + wire \msr_read + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:223" + wire \msr_read$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 86 \mtwi_scl__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 241 \mtwi_scl__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 238 \mtwi_sda__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 84 \mtwi_sda__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 85 \mtwi_sda__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 83 \mtwi_sda__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 239 \mtwi_sda__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 240 \mtwi_sda__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:391" + wire width 64 \new_dec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:408" + wire width 64 \new_tb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" + wire width 64 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:204" + wire width 64 \pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire \pc_changed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire \pc_changed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 7 \pc_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 6 \pc_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:102" + wire width 64 output 5 \pc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:205" + wire \pc_ok_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:205" + wire \pc_ok_delay$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:167" + wire \por_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 87 \pwm_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 242 \pwm_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 88 \pwm_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 243 \pwm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 92 \sd0_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 247 \sd0_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 244 \sd0_cmd__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 90 \sd0_cmd__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 91 \sd0_cmd__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 89 \sd0_cmd__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 245 \sd0_cmd__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 246 \sd0_cmd__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 248 \sd0_data0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 94 \sd0_data0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 95 \sd0_data0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 93 \sd0_data0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 249 \sd0_data0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 250 \sd0_data0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 251 \sd0_data1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 97 \sd0_data1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 98 \sd0_data1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 96 \sd0_data1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 252 \sd0_data1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 253 \sd0_data1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 254 \sd0_data2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 100 \sd0_data2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 101 \sd0_data2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 99 \sd0_data2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 255 \sd0_data2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 256 \sd0_data2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 257 \sd0_data3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 103 \sd0_data3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 104 \sd0_data3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 102 \sd0_data3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 258 \sd0_data3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 259 \sd0_data3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 130 \sdr_a_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 285 \sdr_a_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 148 \sdr_a_10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 303 \sdr_a_10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 149 \sdr_a_11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 304 \sdr_a_11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 150 \sdr_a_12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 305 \sdr_a_12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 131 \sdr_a_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 286 \sdr_a_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 132 \sdr_a_2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 287 \sdr_a_2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 133 \sdr_a_3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 288 \sdr_a_3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 134 \sdr_a_4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 289 \sdr_a_4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 135 \sdr_a_5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 290 \sdr_a_5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 136 \sdr_a_6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 291 \sdr_a_6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 137 \sdr_a_7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 292 \sdr_a_7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 138 \sdr_a_8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 293 \sdr_a_8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 139 \sdr_a_9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 294 \sdr_a_9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 140 \sdr_ba_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 295 \sdr_ba_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 141 \sdr_ba_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 296 \sdr_ba_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 145 \sdr_cas_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 300 \sdr_cas_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 143 \sdr_cke__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 298 \sdr_cke__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 142 \sdr_clock__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 297 \sdr_clock__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 147 \sdr_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 302 \sdr_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 105 \sdr_dm_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 260 \sdr_dm_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 306 \sdr_dm_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 152 \sdr_dm_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 153 \sdr_dm_1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 151 \sdr_dm_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 307 \sdr_dm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 308 \sdr_dm_1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 261 \sdr_dq_0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 107 \sdr_dq_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 108 \sdr_dq_0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 106 \sdr_dq_0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 262 \sdr_dq_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 263 \sdr_dq_0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 315 \sdr_dq_10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 161 \sdr_dq_10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 162 \sdr_dq_10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 160 \sdr_dq_10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 316 \sdr_dq_10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 317 \sdr_dq_10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 318 \sdr_dq_11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 164 \sdr_dq_11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 165 \sdr_dq_11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 163 \sdr_dq_11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 319 \sdr_dq_11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 320 \sdr_dq_11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 321 \sdr_dq_12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 167 \sdr_dq_12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 168 \sdr_dq_12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 166 \sdr_dq_12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 322 \sdr_dq_12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 323 \sdr_dq_12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 324 \sdr_dq_13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 170 \sdr_dq_13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 171 \sdr_dq_13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 169 \sdr_dq_13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 325 \sdr_dq_13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 326 \sdr_dq_13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 327 \sdr_dq_14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 173 \sdr_dq_14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 174 \sdr_dq_14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 172 \sdr_dq_14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 328 \sdr_dq_14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 329 \sdr_dq_14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 330 \sdr_dq_15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 176 \sdr_dq_15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 177 \sdr_dq_15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 175 \sdr_dq_15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 331 \sdr_dq_15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 332 \sdr_dq_15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 264 \sdr_dq_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 110 \sdr_dq_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 111 \sdr_dq_1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 109 \sdr_dq_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 265 \sdr_dq_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 266 \sdr_dq_1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 267 \sdr_dq_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 113 \sdr_dq_2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 114 \sdr_dq_2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 112 \sdr_dq_2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 268 \sdr_dq_2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 269 \sdr_dq_2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 270 \sdr_dq_3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 116 \sdr_dq_3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 117 \sdr_dq_3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 115 \sdr_dq_3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 271 \sdr_dq_3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 272 \sdr_dq_3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 273 \sdr_dq_4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 119 \sdr_dq_4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 120 \sdr_dq_4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 118 \sdr_dq_4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 274 \sdr_dq_4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 275 \sdr_dq_4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 276 \sdr_dq_5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 122 \sdr_dq_5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 123 \sdr_dq_5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 121 \sdr_dq_5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 277 \sdr_dq_5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 278 \sdr_dq_5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 279 \sdr_dq_6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 125 \sdr_dq_6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 126 \sdr_dq_6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 124 \sdr_dq_6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 280 \sdr_dq_6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 281 \sdr_dq_6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 282 \sdr_dq_7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 128 \sdr_dq_7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 129 \sdr_dq_7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 127 \sdr_dq_7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 283 \sdr_dq_7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 284 \sdr_dq_7__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 309 \sdr_dq_8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 155 \sdr_dq_8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 156 \sdr_dq_8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 154 \sdr_dq_8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 310 \sdr_dq_8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 311 \sdr_dq_8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 312 \sdr_dq_9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 158 \sdr_dq_9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 159 \sdr_dq_9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 157 \sdr_dq_9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 313 \sdr_dq_9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 314 \sdr_dq_9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 144 \sdr_ras_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 299 \sdr_ras_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 146 \sdr_we_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 301 \sdr_we_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172" + wire \ti_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" + wire \xics_icp_core_irq_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" + wire width 8 \xics_icp_ics_i_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" + wire width 4 \xics_icp_ics_i_src + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" + wire width 8 \xics_ics_icp_o_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" + wire width 4 \xics_ics_icp_o_src + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:409" + cell $add $add$libresoc.v:184954$13249 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \core_issue__data_o + connect \B 1'1 + connect \Y $add$libresoc.v:184954$13249_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:201" + cell $add $add$libresoc.v:184962$13257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 65 + connect \A \dec2_cur_pc + connect \B 3'100 + connect \Y $add$libresoc.v:184962$13257_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $and $and$libresoc.v:184937$13230 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$97 + connect \B \$99 + connect \Y $and$libresoc.v:184937$13230_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $and $and$libresoc.v:184941$13234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$105 + connect \B \$107 + connect \Y $and$libresoc.v:184941$13234_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $and $and$libresoc.v:184944$13237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$111 + connect \B \$113 + connect \Y $and$libresoc.v:184944$13237_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:184961$13256 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_cu_st__rel_o + connect \B \$32 + connect \Y $and$libresoc.v:184961$13256_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $and $and$libresoc.v:184970$13265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$49 + connect \B \$51 + connect \Y $and$libresoc.v:184970$13265_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:309" + cell $and $and$libresoc.v:184971$13266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \core_state_nia_wen + connect \B 1'1 + connect \Y $and$libresoc.v:184971$13266_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $and $and$libresoc.v:184978$13273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$65 + connect \B \$67 + connect \Y $and$libresoc.v:184978$13273_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $and $and$libresoc.v:184981$13276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$71 + connect \B \$73 + connect \Y $and$libresoc.v:184981$13276_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $and $and$libresoc.v:184984$13279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$77 + connect \B \$79 + connect \Y $and$libresoc.v:184984$13279_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $and $and$libresoc.v:184987$13282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$83 + connect \B \$85 + connect \Y $and$libresoc.v:184987$13282_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $and $and$libresoc.v:184990$13285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$89 + connect \B \$91 + connect \Y $and$libresoc.v:184990$13285_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + cell $pos $extend$libresoc.v:184951$13244 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \core_full_rd2__data_o + connect \Y $extend$libresoc.v:184951$13244_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + cell $pos $extend$libresoc.v:184952$13246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \core_full_rd__data_o + connect \Y $extend$libresoc.v:184952$13246_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" + cell $mul $mul$libresoc.v:184946$13239 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 7 + connect \A \dec2_cur_pc [2] + connect \B 6'100000 + connect \Y $mul$libresoc.v:184946$13239_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" + cell $mul $mul$libresoc.v:184948$13241 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 7 + connect \A \dec2_cur_pc [2] + connect \B 6'100000 + connect \Y $mul$libresoc.v:184948$13241_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:307" + cell $ne $ne$libresoc.v:184950$13243 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \core_core_core_insn_type + connect \B 7'0000001 + connect \Y $ne$libresoc.v:184950$13243_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:174" + cell $ne $ne$libresoc.v:184955$13250 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \clk_sel_i - connect \B 2'00 - connect \Y $eq$libresoc.v:45761$1558_Y + connect \A \delay + connect \B 1'0 + connect \Y $ne$libresoc.v:184955$13250_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" - cell $eq $eq$libresoc.v:45762$1559 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" + cell $ne $ne$libresoc.v:184959$13254 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \clk_sel_i - connect \B 2'00 - connect \Y $eq$libresoc.v:45762$1559_Y + connect \A \delay + connect \B \$28 + connect \Y $ne$libresoc.v:184959$13254_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" - cell $not $not$libresoc.v:45763$1560 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:184936$13229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \clk_24_i - connect \Y $not$libresoc.v:45763$1560_Y + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:184936$13229_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + cell $not $not$libresoc.v:184938$13231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_corebusy_o + connect \Y $not$libresoc.v:184938$13231_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:184939$13232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:184939$13232_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:184940$13233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:184940$13233_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:184942$13235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:184942$13235_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:184943$13236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:184943$13236_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275" + cell $not $not$libresoc.v:184945$13238 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msr_read + connect \Y $not$libresoc.v:184945$13238_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:184960$13255 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_st__rel_o_dly + connect \Y $not$libresoc.v:184960$13255_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:206" + cell $not $not$libresoc.v:184963$13258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pc_i_ok + connect \Y $not$libresoc.v:184963$13258_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + cell $not $not$libresoc.v:184964$13259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_corebusy_o + connect \Y $not$libresoc.v:184964$13259_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + cell $not $not$libresoc.v:184965$13260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pc_changed + connect \Y $not$libresoc.v:184965$13260_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + cell $not $not$libresoc.v:184966$13261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_corebusy_o + connect \Y $not$libresoc.v:184966$13261_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + cell $not $not$libresoc.v:184967$13262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pc_changed + connect \Y $not$libresoc.v:184967$13262_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:184968$13263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:184968$13263_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:184969$13264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:184969$13264_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + cell $not $not$libresoc.v:184973$13268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_corebusy_o + connect \Y $not$libresoc.v:184973$13268_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + cell $not $not$libresoc.v:184974$13269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_corebusy_o + connect \Y $not$libresoc.v:184974$13269_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + cell $not $not$libresoc.v:184975$13270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_corebusy_o + connect \Y $not$libresoc.v:184975$13270_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:184976$13271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:184976$13271_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:184977$13272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:184977$13272_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:184979$13274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:184979$13274_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:184980$13275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:184980$13275_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:184982$13277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:184982$13277_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:184983$13278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:184983$13278_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:184985$13280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:184985$13280_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:184986$13281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:184986$13281_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:184988$13283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:184988$13283_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:184989$13284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:184989$13284_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275" + cell $not $not$libresoc.v:184991$13286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msr_read + connect \Y $not$libresoc.v:184991$13286_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:184992$13287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:184992$13287_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" + cell $or $or$libresoc.v:184957$13252 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B \dbg_core_rst_o + connect \Y $or$libresoc.v:184957$13252_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" + cell $or $or$libresoc.v:184958$13253 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \B \rst + connect \Y $or$libresoc.v:184958$13253_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + cell $pos $pos$libresoc.v:184951$13245 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:184951$13244_Y + connect \Y $pos$libresoc.v:184951$13245_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + cell $pos $pos$libresoc.v:184952$13247 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:184952$13246_Y + connect \Y $pos$libresoc.v:184952$13247_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:184972$13267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \$56 + connect \Y $reduce_or$libresoc.v:184972$13267_Y + end + attribute \src "libresoc.v:184947.19-184947.42" + cell $shr $shr$libresoc.v:184947$13240 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 64 + connect \A \imem_f_instr_o + connect \B \$120 + connect \Y $shr$libresoc.v:184947$13240_Y + end + attribute \src "libresoc.v:184949.19-184949.42" + cell $shr $shr$libresoc.v:184949$13242 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 64 + connect \A \imem_f_instr_o + connect \B \$124 + connect \Y $shr$libresoc.v:184949$13242_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:393" + cell $sub $sub$libresoc.v:184953$13248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \core_issue__data_o + connect \B 1'1 + connect \Y $sub$libresoc.v:184953$13248_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + cell $sub $sub$libresoc.v:184956$13251 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \delay + connect \B 1'1 + connect \Y $sub$libresoc.v:184956$13251_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:185165.8-185258.4" + cell \core \core + connect \bigendian_i \core_bigendian_i$10 + connect \cia__data_o \core_cia__data_o + connect \cia__ren \core_cia__ren + connect \core_core_cia \core_core_core_cia + connect \core_core_cr_rd \core_core_core_cr_rd + connect \core_core_cr_rd_ok \core_core_core_cr_rd_ok + connect \core_core_cr_wr \core_core_core_cr_wr + connect \core_core_exc_$signal \core_core_core_exc_$signal + connect \core_core_exc_$signal$3 \core_core_core_exc_$signal$3 + connect \core_core_exc_$signal$4 \core_core_core_exc_$signal$4 + connect \core_core_exc_$signal$5 \core_core_core_exc_$signal$5 + connect \core_core_exc_$signal$6 \core_core_core_exc_$signal$6 + connect \core_core_exc_$signal$7 \core_core_core_exc_$signal$7 + connect \core_core_exc_$signal$8 \core_core_core_exc_$signal$8 + connect \core_core_exc_$signal$9 \core_core_core_exc_$signal$9 + connect \core_core_fn_unit \core_core_core_fn_unit + connect \core_core_input_carry \core_core_core_input_carry + connect \core_core_insn \core_core_core_insn + connect \core_core_insn_type \core_core_core_insn_type + connect \core_core_is_32bit \core_core_core_is_32bit + connect \core_core_msr \core_core_core_msr + connect \core_core_oe \core_core_core_oe + connect \core_core_oe_ok \core_core_core_oe_ok + connect \core_core_rc \core_core_core_rc + connect \core_core_rc_ok \core_core_core_rc_ok + connect \core_core_trapaddr \core_core_core_trapaddr + connect \core_core_traptype \core_core_core_traptype + connect \core_cr_in1 \core_core_cr_in1 + connect \core_cr_in1_ok \core_core_cr_in1_ok + connect \core_cr_in2 \core_core_cr_in2 + connect \core_cr_in2$1 \core_core_cr_in2$1 + connect \core_cr_in2_ok \core_core_cr_in2_ok + connect \core_cr_in2_ok$2 \core_core_cr_in2_ok$2 + connect \core_cr_out \core_core_cr_out + connect \core_ea \core_core_ea + connect \core_fast1 \core_core_fast1 + connect \core_fast1_ok \core_core_fast1_ok + connect \core_fast2 \core_core_fast2 + connect \core_fast2_ok \core_core_fast2_ok + connect \core_fasto1 \core_core_fasto1 + connect \core_fasto2 \core_core_fasto2 + connect \core_pc \core_core_pc + connect \core_reg1 \core_core_reg1 + connect \core_reg1_ok \core_core_reg1_ok + connect \core_reg2 \core_core_reg2 + connect \core_reg2_ok \core_core_reg2_ok + connect \core_reg3 \core_core_reg3 + connect \core_reg3_ok \core_core_reg3_ok + connect \core_rego \core_core_rego + connect \core_spr1 \core_core_spr1 + connect \core_spr1_ok \core_core_spr1_ok + connect \core_spro \core_core_spro + connect \core_terminate_o \core_core_terminate_o + connect \core_xer_in \core_core_xer_in + connect \corebusy_o \core_corebusy_o + connect \coresync_clk \coresync_clk + connect \coresync_rst \core_coresync_rst + connect \cu_ad__go_i \core_cu_ad__go_i + connect \cu_ad__rel_o \core_cu_ad__rel_o + connect \cu_st__go_i \core_cu_st__go_i + connect \cu_st__rel_o \core_cu_st__rel_o + connect \data_i \core_data_i + connect \dbus__ack \dbus__ack + connect \dbus__adr \dbus__adr + connect \dbus__cyc \dbus__cyc + connect \dbus__dat_r \dbus__dat_r + connect \dbus__dat_w \dbus__dat_w + connect \dbus__err \dbus__err + connect \dbus__sel \dbus__sel + connect \dbus__stb \dbus__stb + connect \dbus__we \dbus__we + connect \dmi__addr \core_dmi__addr + connect \dmi__data_o \core_dmi__data_o + connect \dmi__ren \core_dmi__ren + connect \full_rd2__data_o \core_full_rd2__data_o + connect \full_rd2__ren \core_full_rd2__ren + connect \full_rd__data_o \core_full_rd__data_o + connect \full_rd__ren \core_full_rd__ren + connect \issue__addr \core_issue__addr + connect \issue__addr$10 \core_issue__addr$11 + connect \issue__data_i \core_issue__data_i + connect \issue__data_o \core_issue__data_o + connect \issue__ren \core_issue__ren + connect \issue__wen \core_issue__wen + connect \issue_i \core_issue_i + connect \ivalid_i \core_ivalid_i + connect \msr__data_o \core_msr__data_o + connect \msr__ren \core_msr__ren + connect \raw_insn_i \core_raw_insn_i + connect \state_nia_wen \core_state_nia_wen + connect \wb_dcache_en \core_wb_dcache_en + connect \wen \core_wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:185259.7-185284.4" + cell \dbg \dbg + connect \clk \clk + connect \core_dbg_msr \dbg_core_dbg_msr + connect \core_dbg_pc \dbg_core_dbg_pc + connect \core_rst_o \dbg_core_rst_o + connect \core_stop_o \dbg_core_stop_o + connect \core_stopped_i \dbg_core_stopped_i + connect \d_cr_ack \dbg_d_cr_ack + connect \d_cr_data \dbg_d_cr_data + connect \d_cr_req \dbg_d_cr_req + connect \d_gpr_ack \dbg_d_gpr_ack + connect \d_gpr_addr \dbg_d_gpr_addr + connect \d_gpr_data \dbg_d_gpr_data + connect \d_gpr_req \dbg_d_gpr_req + connect \d_xer_ack \dbg_d_xer_ack + connect \d_xer_data \dbg_d_xer_data + connect \d_xer_req \dbg_d_xer_req + connect \dmi_ack_o \dbg_dmi_ack_o + connect \dmi_addr_i \dbg_dmi_addr_i + connect \dmi_din \dbg_dmi_din + connect \dmi_dout \dbg_dmi_dout + connect \dmi_req_i \dbg_dmi_req_i + connect \dmi_we_i \dbg_dmi_we_i + connect \rst \rst + connect \terminate_i \dbg_terminate_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:185285.8-185351.4" + cell \dec2 \dec2 + connect \asmcode \dec2_asmcode + connect \bigendian \dec2_bigendian + connect \cia \dec2_cia + connect \cr_in1 \dec2_cr_in1 + connect \cr_in1_ok \dec2_cr_in1_ok + connect \cr_in2 \dec2_cr_in2 + connect \cr_in2$1 \dec2_cr_in2$12 + connect \cr_in2_ok \dec2_cr_in2_ok + connect \cr_in2_ok$2 \dec2_cr_in2_ok$13 + connect \cr_out \dec2_cr_out + connect \cr_out_ok \dec2_cr_out_ok + connect \cr_rd \dec2_cr_rd + connect \cr_rd_ok \dec2_cr_rd_ok + connect \cr_wr \dec2_cr_wr + connect \cr_wr_ok \dec2_cr_wr_ok + connect \cur_dec \dec2_cur_dec + connect \cur_eint \dec2_cur_eint + connect \cur_msr \dec2_cur_msr + connect \cur_pc \dec2_cur_pc + connect \ea \dec2_ea + connect \ea_ok \dec2_ea_ok + connect \exc_$signal \dec2_exc_$signal + connect \exc_$signal$3 \dec2_exc_$signal$14 + connect \exc_$signal$4 \dec2_exc_$signal$15 + connect \exc_$signal$5 \dec2_exc_$signal$16 + connect \exc_$signal$6 \dec2_exc_$signal$17 + connect \exc_$signal$7 \dec2_exc_$signal$18 + connect \exc_$signal$8 \dec2_exc_$signal$19 + connect \exc_$signal$9 \dec2_exc_$signal$20 + connect \fast1 \dec2_fast1 + connect \fast1_ok \dec2_fast1_ok + connect \fast2 \dec2_fast2 + connect \fast2_ok \dec2_fast2_ok + connect \fasto1 \dec2_fasto1 + connect \fasto1_ok \dec2_fasto1_ok + connect \fasto2 \dec2_fasto2 + connect \fasto2_ok \dec2_fasto2_ok + connect \fn_unit \dec2_fn_unit + connect \input_carry \dec2_input_carry + connect \insn \dec2_insn + connect \insn_type \dec2_insn_type + connect \is_32bit \dec2_is_32bit + connect \lk \dec2_lk + connect \msr \dec2_msr + connect \oe \dec2_oe + connect \oe_ok \dec2_oe_ok + connect \raw_opcode_in \dec2_raw_opcode_in + connect \rc \dec2_rc + connect \rc_ok \dec2_rc_ok + connect \reg1 \dec2_reg1 + connect \reg1_ok \dec2_reg1_ok + connect \reg2 \dec2_reg2 + connect \reg2_ok \dec2_reg2_ok + connect \reg3 \dec2_reg3 + connect \reg3_ok \dec2_reg3_ok + connect \rego \dec2_rego + connect \rego_ok \dec2_rego_ok + connect \spr1 \dec2_spr1 + connect \spr1_ok \dec2_spr1_ok + connect \spro \dec2_spro + connect \spro_ok \dec2_spro_ok + connect \trapaddr \dec2_trapaddr + connect \traptype \dec2_traptype + connect \xer_in \dec2_xer_in + connect \xer_out \dec2_xer_out + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:185352.8-185368.4" + cell \imem \imem + connect \a_pc_i \imem_a_pc_i + connect \a_valid_i \imem_a_valid_i + connect \clk \clk + connect \f_busy_o \imem_f_busy_o + connect \f_instr_o \imem_f_instr_o + connect \f_valid_i \imem_f_valid_i + connect \ibus__ack \ibus__ack + connect \ibus__adr \ibus__adr + connect \ibus__cyc \ibus__cyc + connect \ibus__dat_r \ibus__dat_r + connect \ibus__err \ibus__err + connect \ibus__sel \ibus__sel + connect \ibus__stb \ibus__stb + connect \rst \rst + connect \wb_icache_en \imem_wb_icache_en + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:185369.8-185700.4" + cell \jtag \jtag + connect \TAP_bus__tck \TAP_bus__tck + connect \TAP_bus__tdi \TAP_bus__tdi + connect \TAP_bus__tdo \TAP_bus__tdo + connect \TAP_bus__tms \TAP_bus__tms + connect \clk \clk + connect \dmi0__ack_o \jtag_dmi0__ack_o + connect \dmi0__addr_i \jtag_dmi0__addr_i + connect \dmi0__din \jtag_dmi0__din + connect \dmi0__dout \jtag_dmi0__dout + connect \dmi0__req_i \jtag_dmi0__req_i + connect \dmi0__we_i \jtag_dmi0__we_i + connect \eint_0__core__i \eint_0__core__i + connect \eint_0__pad__i \eint_0__pad__i + connect \eint_1__core__i \eint_1__core__i + connect \eint_1__pad__i \eint_1__pad__i + connect \eint_2__core__i \eint_2__core__i + connect \eint_2__pad__i \eint_2__pad__i + connect \gpio_e10__core__i \gpio_e10__core__i + connect \gpio_e10__core__o \gpio_e10__core__o + connect \gpio_e10__core__oe \gpio_e10__core__oe + connect \gpio_e10__pad__i \gpio_e10__pad__i + connect \gpio_e10__pad__o \gpio_e10__pad__o + connect \gpio_e10__pad__oe \gpio_e10__pad__oe + connect \gpio_e11__core__i \gpio_e11__core__i + connect \gpio_e11__core__o \gpio_e11__core__o + connect \gpio_e11__core__oe \gpio_e11__core__oe + connect \gpio_e11__pad__i \gpio_e11__pad__i + connect \gpio_e11__pad__o \gpio_e11__pad__o + connect \gpio_e11__pad__oe \gpio_e11__pad__oe + connect \gpio_e12__core__i \gpio_e12__core__i + connect \gpio_e12__core__o \gpio_e12__core__o + connect \gpio_e12__core__oe \gpio_e12__core__oe + connect \gpio_e12__pad__i \gpio_e12__pad__i + connect \gpio_e12__pad__o \gpio_e12__pad__o + connect \gpio_e12__pad__oe \gpio_e12__pad__oe + connect \gpio_e13__core__i \gpio_e13__core__i + connect \gpio_e13__core__o \gpio_e13__core__o + connect \gpio_e13__core__oe \gpio_e13__core__oe + connect \gpio_e13__pad__i \gpio_e13__pad__i + connect \gpio_e13__pad__o \gpio_e13__pad__o + connect \gpio_e13__pad__oe \gpio_e13__pad__oe + connect \gpio_e14__core__i \gpio_e14__core__i + connect \gpio_e14__core__o \gpio_e14__core__o + connect \gpio_e14__core__oe \gpio_e14__core__oe + connect \gpio_e14__pad__i \gpio_e14__pad__i + connect \gpio_e14__pad__o \gpio_e14__pad__o + connect \gpio_e14__pad__oe \gpio_e14__pad__oe + connect \gpio_e15__core__i \gpio_e15__core__i + connect \gpio_e15__core__o \gpio_e15__core__o + connect \gpio_e15__core__oe \gpio_e15__core__oe + connect \gpio_e15__pad__i \gpio_e15__pad__i + connect \gpio_e15__pad__o \gpio_e15__pad__o + connect \gpio_e15__pad__oe \gpio_e15__pad__oe + connect \gpio_e8__core__i \gpio_e8__core__i + connect \gpio_e8__core__o \gpio_e8__core__o + connect \gpio_e8__core__oe \gpio_e8__core__oe + connect \gpio_e8__pad__i \gpio_e8__pad__i + connect \gpio_e8__pad__o \gpio_e8__pad__o + connect \gpio_e8__pad__oe \gpio_e8__pad__oe + connect \gpio_e9__core__i \gpio_e9__core__i + connect \gpio_e9__core__o \gpio_e9__core__o + connect \gpio_e9__core__oe \gpio_e9__core__oe + connect \gpio_e9__pad__i \gpio_e9__pad__i + connect \gpio_e9__pad__o \gpio_e9__pad__o + connect \gpio_e9__pad__oe \gpio_e9__pad__oe + connect \gpio_s0__core__i \gpio_s0__core__i + connect \gpio_s0__core__o \gpio_s0__core__o + connect \gpio_s0__core__oe \gpio_s0__core__oe + connect \gpio_s0__pad__i \gpio_s0__pad__i + connect \gpio_s0__pad__o \gpio_s0__pad__o + connect \gpio_s0__pad__oe \gpio_s0__pad__oe + connect \gpio_s1__core__i \gpio_s1__core__i + connect \gpio_s1__core__o \gpio_s1__core__o + connect \gpio_s1__core__oe \gpio_s1__core__oe + connect \gpio_s1__pad__i \gpio_s1__pad__i + connect \gpio_s1__pad__o \gpio_s1__pad__o + connect \gpio_s1__pad__oe \gpio_s1__pad__oe + connect \gpio_s2__core__i \gpio_s2__core__i + connect \gpio_s2__core__o \gpio_s2__core__o + connect \gpio_s2__core__oe \gpio_s2__core__oe + connect \gpio_s2__pad__i \gpio_s2__pad__i + connect \gpio_s2__pad__o \gpio_s2__pad__o + connect \gpio_s2__pad__oe \gpio_s2__pad__oe + connect \gpio_s3__core__i \gpio_s3__core__i + connect \gpio_s3__core__o \gpio_s3__core__o + connect \gpio_s3__core__oe \gpio_s3__core__oe + connect \gpio_s3__pad__i \gpio_s3__pad__i + connect \gpio_s3__pad__o \gpio_s3__pad__o + connect \gpio_s3__pad__oe \gpio_s3__pad__oe + connect \gpio_s4__core__i \gpio_s4__core__i + connect \gpio_s4__core__o \gpio_s4__core__o + connect \gpio_s4__core__oe \gpio_s4__core__oe + connect \gpio_s4__pad__i \gpio_s4__pad__i + connect \gpio_s4__pad__o \gpio_s4__pad__o + connect \gpio_s4__pad__oe \gpio_s4__pad__oe + connect \gpio_s5__core__i \gpio_s5__core__i + connect \gpio_s5__core__o \gpio_s5__core__o + connect \gpio_s5__core__oe \gpio_s5__core__oe + connect \gpio_s5__pad__i \gpio_s5__pad__i + connect \gpio_s5__pad__o \gpio_s5__pad__o + connect \gpio_s5__pad__oe \gpio_s5__pad__oe + connect \gpio_s6__core__i \gpio_s6__core__i + connect \gpio_s6__core__o \gpio_s6__core__o + connect \gpio_s6__core__oe \gpio_s6__core__oe + connect \gpio_s6__pad__i \gpio_s6__pad__i + connect \gpio_s6__pad__o \gpio_s6__pad__o + connect \gpio_s6__pad__oe \gpio_s6__pad__oe + connect \gpio_s7__core__i \gpio_s7__core__i + connect \gpio_s7__core__o \gpio_s7__core__o + connect \gpio_s7__core__oe \gpio_s7__core__oe + connect \gpio_s7__pad__i \gpio_s7__pad__i + connect \gpio_s7__pad__o \gpio_s7__pad__o + connect \gpio_s7__pad__oe \gpio_s7__pad__oe + connect \jtag_wb__ack \jtag_wb__ack + connect \jtag_wb__adr \jtag_wb__adr + connect \jtag_wb__cyc \jtag_wb__cyc + connect \jtag_wb__dat_r \jtag_wb__dat_r + connect \jtag_wb__dat_w \jtag_wb__dat_w + connect \jtag_wb__sel \jtag_wb__sel + connect \jtag_wb__stb \jtag_wb__stb + connect \jtag_wb__we \jtag_wb__we + connect \mspi0_clk__core__o \mspi0_clk__core__o + connect \mspi0_clk__pad__o \mspi0_clk__pad__o + connect \mspi0_cs_n__core__o \mspi0_cs_n__core__o + connect \mspi0_cs_n__pad__o \mspi0_cs_n__pad__o + connect \mspi0_miso__core__i \mspi0_miso__core__i + connect \mspi0_miso__pad__i \mspi0_miso__pad__i + connect \mspi0_mosi__core__o \mspi0_mosi__core__o + connect \mspi0_mosi__pad__o \mspi0_mosi__pad__o + connect \mspi1_clk__core__o \mspi1_clk__core__o + connect \mspi1_clk__pad__o \mspi1_clk__pad__o + connect \mspi1_cs_n__core__o \mspi1_cs_n__core__o + connect \mspi1_cs_n__pad__o \mspi1_cs_n__pad__o + connect \mspi1_miso__core__i \mspi1_miso__core__i + connect \mspi1_miso__pad__i \mspi1_miso__pad__i + connect \mspi1_mosi__core__o \mspi1_mosi__core__o + connect \mspi1_mosi__pad__o \mspi1_mosi__pad__o + connect \mtwi_scl__core__o \mtwi_scl__core__o + connect \mtwi_scl__pad__o \mtwi_scl__pad__o + connect \mtwi_sda__core__i \mtwi_sda__core__i + connect \mtwi_sda__core__o \mtwi_sda__core__o + connect \mtwi_sda__core__oe \mtwi_sda__core__oe + connect \mtwi_sda__pad__i \mtwi_sda__pad__i + connect \mtwi_sda__pad__o \mtwi_sda__pad__o + connect \mtwi_sda__pad__oe \mtwi_sda__pad__oe + connect \pwm_0__core__o \pwm_0__core__o + connect \pwm_0__pad__o \pwm_0__pad__o + connect \pwm_1__core__o \pwm_1__core__o + connect \pwm_1__pad__o \pwm_1__pad__o + connect \rst \rst + connect \sd0_clk__core__o \sd0_clk__core__o + connect \sd0_clk__pad__o \sd0_clk__pad__o + connect \sd0_cmd__core__i \sd0_cmd__core__i + connect \sd0_cmd__core__o \sd0_cmd__core__o + connect \sd0_cmd__core__oe \sd0_cmd__core__oe + connect \sd0_cmd__pad__i \sd0_cmd__pad__i + connect \sd0_cmd__pad__o \sd0_cmd__pad__o + connect \sd0_cmd__pad__oe \sd0_cmd__pad__oe + connect \sd0_data0__core__i \sd0_data0__core__i + connect \sd0_data0__core__o \sd0_data0__core__o + connect \sd0_data0__core__oe \sd0_data0__core__oe + connect \sd0_data0__pad__i \sd0_data0__pad__i + connect \sd0_data0__pad__o \sd0_data0__pad__o + connect \sd0_data0__pad__oe \sd0_data0__pad__oe + connect \sd0_data1__core__i \sd0_data1__core__i + connect \sd0_data1__core__o \sd0_data1__core__o + connect \sd0_data1__core__oe \sd0_data1__core__oe + connect \sd0_data1__pad__i \sd0_data1__pad__i + connect \sd0_data1__pad__o \sd0_data1__pad__o + connect \sd0_data1__pad__oe \sd0_data1__pad__oe + connect \sd0_data2__core__i \sd0_data2__core__i + connect \sd0_data2__core__o \sd0_data2__core__o + connect \sd0_data2__core__oe \sd0_data2__core__oe + connect \sd0_data2__pad__i \sd0_data2__pad__i + connect \sd0_data2__pad__o \sd0_data2__pad__o + connect \sd0_data2__pad__oe \sd0_data2__pad__oe + connect \sd0_data3__core__i \sd0_data3__core__i + connect \sd0_data3__core__o \sd0_data3__core__o + connect \sd0_data3__core__oe \sd0_data3__core__oe + connect \sd0_data3__pad__i \sd0_data3__pad__i + connect \sd0_data3__pad__o \sd0_data3__pad__o + connect \sd0_data3__pad__oe \sd0_data3__pad__oe + connect \sdr_a_0__core__o \sdr_a_0__core__o + connect \sdr_a_0__pad__o \sdr_a_0__pad__o + connect \sdr_a_10__core__o \sdr_a_10__core__o + connect \sdr_a_10__pad__o \sdr_a_10__pad__o + connect \sdr_a_11__core__o \sdr_a_11__core__o + connect \sdr_a_11__pad__o \sdr_a_11__pad__o + connect \sdr_a_12__core__o \sdr_a_12__core__o + connect \sdr_a_12__pad__o \sdr_a_12__pad__o + connect \sdr_a_1__core__o \sdr_a_1__core__o + connect \sdr_a_1__pad__o \sdr_a_1__pad__o + connect \sdr_a_2__core__o \sdr_a_2__core__o + connect \sdr_a_2__pad__o \sdr_a_2__pad__o + connect \sdr_a_3__core__o \sdr_a_3__core__o + connect \sdr_a_3__pad__o \sdr_a_3__pad__o + connect \sdr_a_4__core__o \sdr_a_4__core__o + connect \sdr_a_4__pad__o \sdr_a_4__pad__o + connect \sdr_a_5__core__o \sdr_a_5__core__o + connect \sdr_a_5__pad__o \sdr_a_5__pad__o + connect \sdr_a_6__core__o \sdr_a_6__core__o + connect \sdr_a_6__pad__o \sdr_a_6__pad__o + connect \sdr_a_7__core__o \sdr_a_7__core__o + connect \sdr_a_7__pad__o \sdr_a_7__pad__o + connect \sdr_a_8__core__o \sdr_a_8__core__o + connect \sdr_a_8__pad__o \sdr_a_8__pad__o + connect \sdr_a_9__core__o \sdr_a_9__core__o + connect \sdr_a_9__pad__o \sdr_a_9__pad__o + connect \sdr_ba_0__core__o \sdr_ba_0__core__o + connect \sdr_ba_0__pad__o \sdr_ba_0__pad__o + connect \sdr_ba_1__core__o \sdr_ba_1__core__o + connect \sdr_ba_1__pad__o \sdr_ba_1__pad__o + connect \sdr_cas_n__core__o \sdr_cas_n__core__o + connect \sdr_cas_n__pad__o \sdr_cas_n__pad__o + connect \sdr_cke__core__o \sdr_cke__core__o + connect \sdr_cke__pad__o \sdr_cke__pad__o + connect \sdr_clock__core__o \sdr_clock__core__o + connect \sdr_clock__pad__o \sdr_clock__pad__o + connect \sdr_cs_n__core__o \sdr_cs_n__core__o + connect \sdr_cs_n__pad__o \sdr_cs_n__pad__o + connect \sdr_dm_0__core__o \sdr_dm_0__core__o + connect \sdr_dm_0__pad__o \sdr_dm_0__pad__o + connect \sdr_dm_1__core__i \sdr_dm_1__core__i + connect \sdr_dm_1__core__o \sdr_dm_1__core__o + connect \sdr_dm_1__core__oe \sdr_dm_1__core__oe + connect \sdr_dm_1__pad__i \sdr_dm_1__pad__i + connect \sdr_dm_1__pad__o \sdr_dm_1__pad__o + connect \sdr_dm_1__pad__oe \sdr_dm_1__pad__oe + connect \sdr_dq_0__core__i \sdr_dq_0__core__i + connect \sdr_dq_0__core__o \sdr_dq_0__core__o + connect \sdr_dq_0__core__oe \sdr_dq_0__core__oe + connect \sdr_dq_0__pad__i \sdr_dq_0__pad__i + connect \sdr_dq_0__pad__o \sdr_dq_0__pad__o + connect \sdr_dq_0__pad__oe \sdr_dq_0__pad__oe + connect \sdr_dq_10__core__i \sdr_dq_10__core__i + connect \sdr_dq_10__core__o \sdr_dq_10__core__o + connect \sdr_dq_10__core__oe \sdr_dq_10__core__oe + connect \sdr_dq_10__pad__i \sdr_dq_10__pad__i + connect \sdr_dq_10__pad__o \sdr_dq_10__pad__o + connect \sdr_dq_10__pad__oe \sdr_dq_10__pad__oe + connect \sdr_dq_11__core__i \sdr_dq_11__core__i + connect \sdr_dq_11__core__o \sdr_dq_11__core__o + connect \sdr_dq_11__core__oe \sdr_dq_11__core__oe + connect \sdr_dq_11__pad__i \sdr_dq_11__pad__i + connect \sdr_dq_11__pad__o \sdr_dq_11__pad__o + connect \sdr_dq_11__pad__oe \sdr_dq_11__pad__oe + connect \sdr_dq_12__core__i \sdr_dq_12__core__i + connect \sdr_dq_12__core__o \sdr_dq_12__core__o + connect \sdr_dq_12__core__oe \sdr_dq_12__core__oe + connect \sdr_dq_12__pad__i \sdr_dq_12__pad__i + connect \sdr_dq_12__pad__o \sdr_dq_12__pad__o + connect \sdr_dq_12__pad__oe \sdr_dq_12__pad__oe + connect \sdr_dq_13__core__i \sdr_dq_13__core__i + connect \sdr_dq_13__core__o \sdr_dq_13__core__o + connect \sdr_dq_13__core__oe \sdr_dq_13__core__oe + connect \sdr_dq_13__pad__i \sdr_dq_13__pad__i + connect \sdr_dq_13__pad__o \sdr_dq_13__pad__o + connect \sdr_dq_13__pad__oe \sdr_dq_13__pad__oe + connect \sdr_dq_14__core__i \sdr_dq_14__core__i + connect \sdr_dq_14__core__o \sdr_dq_14__core__o + connect \sdr_dq_14__core__oe \sdr_dq_14__core__oe + connect \sdr_dq_14__pad__i \sdr_dq_14__pad__i + connect \sdr_dq_14__pad__o \sdr_dq_14__pad__o + connect \sdr_dq_14__pad__oe \sdr_dq_14__pad__oe + connect \sdr_dq_15__core__i \sdr_dq_15__core__i + connect \sdr_dq_15__core__o \sdr_dq_15__core__o + connect \sdr_dq_15__core__oe \sdr_dq_15__core__oe + connect \sdr_dq_15__pad__i \sdr_dq_15__pad__i + connect \sdr_dq_15__pad__o \sdr_dq_15__pad__o + connect \sdr_dq_15__pad__oe \sdr_dq_15__pad__oe + connect \sdr_dq_1__core__i \sdr_dq_1__core__i + connect \sdr_dq_1__core__o \sdr_dq_1__core__o + connect \sdr_dq_1__core__oe \sdr_dq_1__core__oe + connect \sdr_dq_1__pad__i \sdr_dq_1__pad__i + connect \sdr_dq_1__pad__o \sdr_dq_1__pad__o + connect \sdr_dq_1__pad__oe \sdr_dq_1__pad__oe + connect \sdr_dq_2__core__i \sdr_dq_2__core__i + connect \sdr_dq_2__core__o \sdr_dq_2__core__o + connect \sdr_dq_2__core__oe \sdr_dq_2__core__oe + connect \sdr_dq_2__pad__i \sdr_dq_2__pad__i + connect \sdr_dq_2__pad__o \sdr_dq_2__pad__o + connect \sdr_dq_2__pad__oe \sdr_dq_2__pad__oe + connect \sdr_dq_3__core__i \sdr_dq_3__core__i + connect \sdr_dq_3__core__o \sdr_dq_3__core__o + connect \sdr_dq_3__core__oe \sdr_dq_3__core__oe + connect \sdr_dq_3__pad__i \sdr_dq_3__pad__i + connect \sdr_dq_3__pad__o \sdr_dq_3__pad__o + connect \sdr_dq_3__pad__oe \sdr_dq_3__pad__oe + connect \sdr_dq_4__core__i \sdr_dq_4__core__i + connect \sdr_dq_4__core__o \sdr_dq_4__core__o + connect \sdr_dq_4__core__oe \sdr_dq_4__core__oe + connect \sdr_dq_4__pad__i \sdr_dq_4__pad__i + connect \sdr_dq_4__pad__o \sdr_dq_4__pad__o + connect \sdr_dq_4__pad__oe \sdr_dq_4__pad__oe + connect \sdr_dq_5__core__i \sdr_dq_5__core__i + connect \sdr_dq_5__core__o \sdr_dq_5__core__o + connect \sdr_dq_5__core__oe \sdr_dq_5__core__oe + connect \sdr_dq_5__pad__i \sdr_dq_5__pad__i + connect \sdr_dq_5__pad__o \sdr_dq_5__pad__o + connect \sdr_dq_5__pad__oe \sdr_dq_5__pad__oe + connect \sdr_dq_6__core__i \sdr_dq_6__core__i + connect \sdr_dq_6__core__o \sdr_dq_6__core__o + connect \sdr_dq_6__core__oe \sdr_dq_6__core__oe + connect \sdr_dq_6__pad__i \sdr_dq_6__pad__i + connect \sdr_dq_6__pad__o \sdr_dq_6__pad__o + connect \sdr_dq_6__pad__oe \sdr_dq_6__pad__oe + connect \sdr_dq_7__core__i \sdr_dq_7__core__i + connect \sdr_dq_7__core__o \sdr_dq_7__core__o + connect \sdr_dq_7__core__oe \sdr_dq_7__core__oe + connect \sdr_dq_7__pad__i \sdr_dq_7__pad__i + connect \sdr_dq_7__pad__o \sdr_dq_7__pad__o + connect \sdr_dq_7__pad__oe \sdr_dq_7__pad__oe + connect \sdr_dq_8__core__i \sdr_dq_8__core__i + connect \sdr_dq_8__core__o \sdr_dq_8__core__o + connect \sdr_dq_8__core__oe \sdr_dq_8__core__oe + connect \sdr_dq_8__pad__i \sdr_dq_8__pad__i + connect \sdr_dq_8__pad__o \sdr_dq_8__pad__o + connect \sdr_dq_8__pad__oe \sdr_dq_8__pad__oe + connect \sdr_dq_9__core__i \sdr_dq_9__core__i + connect \sdr_dq_9__core__o \sdr_dq_9__core__o + connect \sdr_dq_9__core__oe \sdr_dq_9__core__oe + connect \sdr_dq_9__pad__i \sdr_dq_9__pad__i + connect \sdr_dq_9__pad__o \sdr_dq_9__pad__o + connect \sdr_dq_9__pad__oe \sdr_dq_9__pad__oe + connect \sdr_ras_n__core__o \sdr_ras_n__core__o + connect \sdr_ras_n__pad__o \sdr_ras_n__pad__o + connect \sdr_we_n__core__o \sdr_we_n__core__o + connect \sdr_we_n__pad__o \sdr_we_n__pad__o + connect \wb_dcache_en \core_wb_dcache_en + connect \wb_icache_en \imem_wb_icache_en + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:185701.12-185715.4" + cell \xics_icp \xics_icp + connect \clk \clk + connect \core_irq_o \xics_icp_core_irq_o + connect \icp_wb__ack \icp_wb__ack + connect \icp_wb__adr \icp_wb__adr + connect \icp_wb__cyc \icp_wb__cyc + connect \icp_wb__dat_r \icp_wb__dat_r + connect \icp_wb__dat_w \icp_wb__dat_w + connect \icp_wb__sel \icp_wb__sel + connect \icp_wb__stb \icp_wb__stb + connect \icp_wb__we \icp_wb__we + connect \ics_i_pri \xics_icp_ics_i_pri + connect \ics_i_src \xics_icp_ics_i_src + connect \rst \rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:185716.12-185729.4" + cell \xics_ics \xics_ics + connect \clk \clk + connect \icp_o_pri \xics_ics_icp_o_pri + connect \icp_o_src \xics_ics_icp_o_src + connect \ics_wb__ack \ics_wb__ack + connect \ics_wb__adr \ics_wb__adr + connect \ics_wb__cyc \ics_wb__cyc + connect \ics_wb__dat_r \ics_wb__dat_r + connect \ics_wb__dat_w \ics_wb__dat_w + connect \ics_wb__stb \ics_wb__stb + connect \ics_wb__we \ics_wb__we + connect \int_level_i \int_level_i + connect \rst \rst end - attribute \src "libresoc.v:45742.7-45742.20" - process $proc$libresoc.v:45742$1563 + attribute \src "libresoc.v:182859.7-182859.20" + process $proc$libresoc.v:182859$13788 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:45764.3-45773.6" - process $proc$libresoc.v:45764$1561 + attribute \src "libresoc.v:182995.13-182995.33" + process $proc$libresoc.v:182995$13789 assign { } { } + assign $1\core_asmcode[7:0] 8'00000000 + sync always + sync init + update \core_asmcode $1\core_asmcode[7:0] + end + attribute \src "libresoc.v:183001.7-183001.35" + process $proc$libresoc.v:183001$13790 assign { } { } - assign $0\pll_lck_o[0:0] $1\pll_lck_o[0:0] - attribute \src "libresoc.v:45765.5-45765.29" - switch \initial - attribute \src "libresoc.v:45765.9-45765.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\pll_lck_o[0:0] \clk_24_i - case - assign $1\pll_lck_o[0:0] 1'0 - end + assign $0\core_bigendian_i$10[0:0]$13791 1'0 sync always - update \pll_lck_o $0\pll_lck_o[0:0] + sync init + update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13791 end - attribute \src "libresoc.v:45774.3-45783.6" - process $proc$libresoc.v:45774$1562 + attribute \src "libresoc.v:183009.14-183009.55" + process $proc$libresoc.v:183009$13792 assign { } { } + assign $1\core_core_core_cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_core_core_cia $1\core_core_core_cia[63:0] + end + attribute \src "libresoc.v:183013.13-183013.41" + process $proc$libresoc.v:183013$13793 assign { } { } - assign $0\pll_18_o[0:0] $1\pll_18_o[0:0] - attribute \src "libresoc.v:45775.5-45775.29" - switch \initial - attribute \src "libresoc.v:45775.9-45775.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\pll_18_o[0:0] \$5 - case - assign $1\pll_18_o[0:0] 1'0 - end + assign $1\core_core_core_cr_rd[7:0] 8'00000000 sync always - update \pll_18_o $0\pll_18_o[0:0] + sync init + update \core_core_core_cr_rd $1\core_core_core_cr_rd[7:0] end - connect \$1 $eq$libresoc.v:45761$1558_Y - connect \$3 $eq$libresoc.v:45762$1559_Y - connect \$5 $not$libresoc.v:45763$1560_Y - connect \clk_pll_o \clk_24_i -end -attribute \src "libresoc.v:45789.1-45873.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in.ppick" -attribute \generator "nMigen" -module \ppick - attribute \src "libresoc.v:45846.17-45846.91" - wire $not$libresoc.v:45846$1564_Y - attribute \src "libresoc.v:45848.18-45848.93" - wire $not$libresoc.v:45848$1566_Y - attribute \src "libresoc.v:45850.18-45850.93" - wire $not$libresoc.v:45850$1568_Y - attribute \src "libresoc.v:45851.17-45851.138" - wire width 8 $not$libresoc.v:45851$1569_Y - attribute \src "libresoc.v:45853.18-45853.93" - wire $not$libresoc.v:45853$1571_Y - attribute \src "libresoc.v:45855.18-45855.93" - wire $not$libresoc.v:45855$1573_Y - attribute \src "libresoc.v:45857.18-45857.93" - wire $not$libresoc.v:45857$1575_Y - attribute \src "libresoc.v:45860.17-45860.91" - wire $not$libresoc.v:45860$1578_Y - attribute \src "libresoc.v:45847.18-45847.116" - wire $reduce_or$libresoc.v:45847$1565_Y - attribute \src "libresoc.v:45849.18-45849.122" - wire $reduce_or$libresoc.v:45849$1567_Y - attribute \src "libresoc.v:45852.18-45852.128" - wire $reduce_or$libresoc.v:45852$1570_Y - attribute \src "libresoc.v:45854.18-45854.134" - wire $reduce_or$libresoc.v:45854$1572_Y - attribute \src "libresoc.v:45856.18-45856.140" - wire $reduce_or$libresoc.v:45856$1574_Y - attribute \src "libresoc.v:45858.18-45858.90" - wire $reduce_or$libresoc.v:45858$1576_Y - attribute \src "libresoc.v:45859.17-45859.103" - wire $reduce_or$libresoc.v:45859$1577_Y - attribute \src "libresoc.v:45861.17-45861.109" - wire $reduce_or$libresoc.v:45861$1579_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:45846$1564 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:45846$1564_Y + attribute \src "libresoc.v:183017.7-183017.37" + process $proc$libresoc.v:183017$13794 + assign { } { } + assign $1\core_core_core_cr_rd_ok[0:0] 1'0 + sync always + sync init + update \core_core_core_cr_rd_ok $1\core_core_core_cr_rd_ok[0:0] + end + attribute \src "libresoc.v:183021.13-183021.41" + process $proc$libresoc.v:183021$13795 + assign { } { } + assign $1\core_core_core_cr_wr[7:0] 8'00000000 + sync always + sync init + update \core_core_core_cr_wr $1\core_core_core_cr_wr[7:0] + end + attribute \src "libresoc.v:183025.7-183025.42" + process $proc$libresoc.v:183025$13796 + assign { } { } + assign $0\core_core_core_exc_$signal[0:0]$13797 1'0 + sync always + sync init + update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13797 + end + attribute \src "libresoc.v:183027.7-183027.44" + process $proc$libresoc.v:183027$13798 + assign { } { } + assign $0\core_core_core_exc_$signal$3[0:0]$13799 1'0 + sync always + sync init + update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13799 + end + attribute \src "libresoc.v:183031.7-183031.44" + process $proc$libresoc.v:183031$13800 + assign { } { } + assign $0\core_core_core_exc_$signal$4[0:0]$13801 1'0 + sync always + sync init + update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13801 + end + attribute \src "libresoc.v:183035.7-183035.44" + process $proc$libresoc.v:183035$13802 + assign { } { } + assign $0\core_core_core_exc_$signal$5[0:0]$13803 1'0 + sync always + sync init + update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13803 + end + attribute \src "libresoc.v:183039.7-183039.44" + process $proc$libresoc.v:183039$13804 + assign { } { } + assign $0\core_core_core_exc_$signal$6[0:0]$13805 1'0 + sync always + sync init + update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13805 + end + attribute \src "libresoc.v:183043.7-183043.44" + process $proc$libresoc.v:183043$13806 + assign { } { } + assign $0\core_core_core_exc_$signal$7[0:0]$13807 1'0 + sync always + sync init + update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13807 + end + attribute \src "libresoc.v:183047.7-183047.44" + process $proc$libresoc.v:183047$13808 + assign { } { } + assign $0\core_core_core_exc_$signal$8[0:0]$13809 1'0 + sync always + sync init + update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13809 + end + attribute \src "libresoc.v:183051.7-183051.44" + process $proc$libresoc.v:183051$13810 + assign { } { } + assign $0\core_core_core_exc_$signal$9[0:0]$13811 1'0 + sync always + sync init + update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13811 + end + attribute \src "libresoc.v:183070.14-183070.46" + process $proc$libresoc.v:183070$13812 + assign { } { } + assign $1\core_core_core_fn_unit[11:0] 12'000000000000 + sync always + sync init + update \core_core_core_fn_unit $1\core_core_core_fn_unit[11:0] + end + attribute \src "libresoc.v:183078.13-183078.46" + process $proc$libresoc.v:183078$13813 + assign { } { } + assign $1\core_core_core_input_carry[1:0] 2'00 + sync always + sync init + update \core_core_core_input_carry $1\core_core_core_input_carry[1:0] + end + attribute \src "libresoc.v:183082.14-183082.41" + process $proc$libresoc.v:183082$13814 + assign { } { } + assign $1\core_core_core_insn[31:0] 0 + sync always + sync init + update \core_core_core_insn $1\core_core_core_insn[31:0] + end + attribute \src "libresoc.v:183160.13-183160.45" + process $proc$libresoc.v:183160$13815 + assign { } { } + assign $1\core_core_core_insn_type[6:0] 7'0000000 + sync always + sync init + update \core_core_core_insn_type $1\core_core_core_insn_type[6:0] + end + attribute \src "libresoc.v:183164.7-183164.37" + process $proc$libresoc.v:183164$13816 + assign { } { } + assign $1\core_core_core_is_32bit[0:0] 1'0 + sync always + sync init + update \core_core_core_is_32bit $1\core_core_core_is_32bit[0:0] + end + attribute \src "libresoc.v:183168.14-183168.55" + process $proc$libresoc.v:183168$13817 + assign { } { } + assign $1\core_core_core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_core_core_msr $1\core_core_core_msr[63:0] + end + attribute \src "libresoc.v:183172.7-183172.31" + process $proc$libresoc.v:183172$13818 + assign { } { } + assign $1\core_core_core_oe[0:0] 1'0 + sync always + sync init + update \core_core_core_oe $1\core_core_core_oe[0:0] + end + attribute \src "libresoc.v:183176.7-183176.34" + process $proc$libresoc.v:183176$13819 + assign { } { } + assign $1\core_core_core_oe_ok[0:0] 1'0 + sync always + sync init + update \core_core_core_oe_ok $1\core_core_core_oe_ok[0:0] + end + attribute \src "libresoc.v:183180.7-183180.31" + process $proc$libresoc.v:183180$13820 + assign { } { } + assign $1\core_core_core_rc[0:0] 1'0 + sync always + sync init + update \core_core_core_rc $1\core_core_core_rc[0:0] + end + attribute \src "libresoc.v:183184.7-183184.34" + process $proc$libresoc.v:183184$13821 + assign { } { } + assign $1\core_core_core_rc_ok[0:0] 1'0 + sync always + sync init + update \core_core_core_rc_ok $1\core_core_core_rc_ok[0:0] + end + attribute \src "libresoc.v:183188.14-183188.48" + process $proc$libresoc.v:183188$13822 + assign { } { } + assign $1\core_core_core_trapaddr[12:0] 13'0000000000000 + sync always + sync init + update \core_core_core_trapaddr $1\core_core_core_trapaddr[12:0] + end + attribute \src "libresoc.v:183192.13-183192.44" + process $proc$libresoc.v:183192$13823 + assign { } { } + assign $1\core_core_core_traptype[7:0] 8'00000000 + sync always + sync init + update \core_core_core_traptype $1\core_core_core_traptype[7:0] + end + attribute \src "libresoc.v:183196.13-183196.36" + process $proc$libresoc.v:183196$13824 + assign { } { } + assign $1\core_core_cr_in1[2:0] 3'000 + sync always + sync init + update \core_core_cr_in1 $1\core_core_cr_in1[2:0] + end + attribute \src "libresoc.v:183200.7-183200.33" + process $proc$libresoc.v:183200$13825 + assign { } { } + assign $1\core_core_cr_in1_ok[0:0] 1'0 + sync always + sync init + update \core_core_cr_in1_ok $1\core_core_cr_in1_ok[0:0] + end + attribute \src "libresoc.v:183204.13-183204.36" + process $proc$libresoc.v:183204$13826 + assign { } { } + assign $1\core_core_cr_in2[2:0] 3'000 + sync always + sync init + update \core_core_cr_in2 $1\core_core_cr_in2[2:0] + end + attribute \src "libresoc.v:183206.13-183206.40" + process $proc$libresoc.v:183206$13827 + assign { } { } + assign $0\core_core_cr_in2$1[2:0]$13828 3'000 + sync always + sync init + update \core_core_cr_in2$1 $0\core_core_cr_in2$1[2:0]$13828 + end + attribute \src "libresoc.v:183212.7-183212.33" + process $proc$libresoc.v:183212$13829 + assign { } { } + assign $1\core_core_cr_in2_ok[0:0] 1'0 + sync always + sync init + update \core_core_cr_in2_ok $1\core_core_cr_in2_ok[0:0] + end + attribute \src "libresoc.v:183214.7-183214.37" + process $proc$libresoc.v:183214$13830 + assign { } { } + assign $0\core_core_cr_in2_ok$2[0:0]$13831 1'0 + sync always + sync init + update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13831 + end + attribute \src "libresoc.v:183220.13-183220.36" + process $proc$libresoc.v:183220$13832 + assign { } { } + assign $1\core_core_cr_out[2:0] 3'000 + sync always + sync init + update \core_core_cr_out $1\core_core_cr_out[2:0] + end + attribute \src "libresoc.v:183224.7-183224.32" + process $proc$libresoc.v:183224$13833 + assign { } { } + assign $1\core_core_cr_wr_ok[0:0] 1'0 + sync always + sync init + update \core_core_cr_wr_ok $1\core_core_cr_wr_ok[0:0] + end + attribute \src "libresoc.v:183228.13-183228.33" + process $proc$libresoc.v:183228$13834 + assign { } { } + assign $1\core_core_ea[4:0] 5'00000 + sync always + sync init + update \core_core_ea $1\core_core_ea[4:0] + end + attribute \src "libresoc.v:183232.13-183232.35" + process $proc$libresoc.v:183232$13835 + assign { } { } + assign $1\core_core_fast1[2:0] 3'000 + sync always + sync init + update \core_core_fast1 $1\core_core_fast1[2:0] + end + attribute \src "libresoc.v:183236.7-183236.32" + process $proc$libresoc.v:183236$13836 + assign { } { } + assign $1\core_core_fast1_ok[0:0] 1'0 + sync always + sync init + update \core_core_fast1_ok $1\core_core_fast1_ok[0:0] + end + attribute \src "libresoc.v:183240.13-183240.35" + process $proc$libresoc.v:183240$13837 + assign { } { } + assign $1\core_core_fast2[2:0] 3'000 + sync always + sync init + update \core_core_fast2 $1\core_core_fast2[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:45848$1566 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:45848$1566_Y + attribute \src "libresoc.v:183244.7-183244.32" + process $proc$libresoc.v:183244$13838 + assign { } { } + assign $1\core_core_fast2_ok[0:0] 1'0 + sync always + sync init + update \core_core_fast2_ok $1\core_core_fast2_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:45850$1568 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:45850$1568_Y + attribute \src "libresoc.v:183248.13-183248.36" + process $proc$libresoc.v:183248$13839 + assign { } { } + assign $1\core_core_fasto1[2:0] 3'000 + sync always + sync init + update \core_core_fasto1 $1\core_core_fasto1[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:45851$1569 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:45851$1569_Y + attribute \src "libresoc.v:183252.13-183252.36" + process $proc$libresoc.v:183252$13840 + assign { } { } + assign $1\core_core_fasto2[2:0] 3'000 + sync always + sync init + update \core_core_fasto2 $1\core_core_fasto2[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:45853$1571 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:45853$1571_Y + attribute \src "libresoc.v:183256.7-183256.26" + process $proc$libresoc.v:183256$13841 + assign { } { } + assign $1\core_core_lk[0:0] 1'0 + sync always + sync init + update \core_core_lk $1\core_core_lk[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:45855$1573 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:45855$1573_Y + attribute \src "libresoc.v:183260.14-183260.49" + process $proc$libresoc.v:183260$13842 + assign { } { } + assign $1\core_core_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_core_pc $1\core_core_pc[63:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:45857$1575 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:45857$1575_Y + attribute \src "libresoc.v:183264.13-183264.35" + process $proc$libresoc.v:183264$13843 + assign { } { } + assign $1\core_core_reg1[4:0] 5'00000 + sync always + sync init + update \core_core_reg1 $1\core_core_reg1[4:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:45860$1578 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:45860$1578_Y + attribute \src "libresoc.v:183268.7-183268.31" + process $proc$libresoc.v:183268$13844 + assign { } { } + assign $1\core_core_reg1_ok[0:0] 1'0 + sync always + sync init + update \core_core_reg1_ok $1\core_core_reg1_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:45847$1565 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:45847$1565_Y + attribute \src "libresoc.v:183272.13-183272.35" + process $proc$libresoc.v:183272$13845 + assign { } { } + assign $1\core_core_reg2[4:0] 5'00000 + sync always + sync init + update \core_core_reg2 $1\core_core_reg2[4:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:45849$1567 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:45849$1567_Y + attribute \src "libresoc.v:183276.7-183276.31" + process $proc$libresoc.v:183276$13846 + assign { } { } + assign $1\core_core_reg2_ok[0:0] 1'0 + sync always + sync init + update \core_core_reg2_ok $1\core_core_reg2_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:45852$1570 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:45852$1570_Y + attribute \src "libresoc.v:183280.13-183280.35" + process $proc$libresoc.v:183280$13847 + assign { } { } + assign $1\core_core_reg3[4:0] 5'00000 + sync always + sync init + update \core_core_reg3 $1\core_core_reg3[4:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:45854$1572 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:45854$1572_Y + attribute \src "libresoc.v:183284.7-183284.31" + process $proc$libresoc.v:183284$13848 + assign { } { } + assign $1\core_core_reg3_ok[0:0] 1'0 + sync always + sync init + update \core_core_reg3_ok $1\core_core_reg3_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:45856$1574 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:45856$1574_Y + attribute \src "libresoc.v:183288.13-183288.35" + process $proc$libresoc.v:183288$13849 + assign { } { } + assign $1\core_core_rego[4:0] 5'00000 + sync always + sync init + update \core_core_rego $1\core_core_rego[4:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:45858$1576 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:45858$1576_Y + attribute \src "libresoc.v:183403.13-183403.37" + process $proc$libresoc.v:183403$13850 + assign { } { } + assign $1\core_core_spr1[9:0] 10'0000000000 + sync always + sync init + update \core_core_spr1 $1\core_core_spr1[9:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:45859$1577 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:45859$1577_Y + attribute \src "libresoc.v:183407.7-183407.31" + process $proc$libresoc.v:183407$13851 + assign { } { } + assign $1\core_core_spr1_ok[0:0] 1'0 + sync always + sync init + update \core_core_spr1_ok $1\core_core_spr1_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:45861$1579 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:45861$1579_Y - end - connect \$7 $not$libresoc.v:45846$1564_Y - connect \$12 $reduce_or$libresoc.v:45847$1565_Y - connect \$11 $not$libresoc.v:45848$1566_Y - connect \$16 $reduce_or$libresoc.v:45849$1567_Y - connect \$15 $not$libresoc.v:45850$1568_Y - connect \$1 $not$libresoc.v:45851$1569_Y - connect \$20 $reduce_or$libresoc.v:45852$1570_Y - connect \$19 $not$libresoc.v:45853$1571_Y - connect \$24 $reduce_or$libresoc.v:45854$1572_Y - connect \$23 $not$libresoc.v:45855$1573_Y - connect \$28 $reduce_or$libresoc.v:45856$1574_Y - connect \$27 $not$libresoc.v:45857$1575_Y - connect \$31 $reduce_or$libresoc.v:45858$1576_Y - connect \$4 $reduce_or$libresoc.v:45859$1577_Y - connect \$3 $not$libresoc.v:45860$1578_Y - connect \$8 $reduce_or$libresoc.v:45861$1579_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:45877.1-45961.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out.ppick" -attribute \generator "nMigen" -module \ppick$1 - attribute \src "libresoc.v:45934.17-45934.91" - wire $not$libresoc.v:45934$1580_Y - attribute \src "libresoc.v:45936.18-45936.93" - wire $not$libresoc.v:45936$1582_Y - attribute \src "libresoc.v:45938.18-45938.93" - wire $not$libresoc.v:45938$1584_Y - attribute \src "libresoc.v:45939.17-45939.138" - wire width 8 $not$libresoc.v:45939$1585_Y - attribute \src "libresoc.v:45941.18-45941.93" - wire $not$libresoc.v:45941$1587_Y - attribute \src "libresoc.v:45943.18-45943.93" - wire $not$libresoc.v:45943$1589_Y - attribute \src "libresoc.v:45945.18-45945.93" - wire $not$libresoc.v:45945$1591_Y - attribute \src "libresoc.v:45948.17-45948.91" - wire $not$libresoc.v:45948$1594_Y - attribute \src "libresoc.v:45935.18-45935.116" - wire $reduce_or$libresoc.v:45935$1581_Y - attribute \src "libresoc.v:45937.18-45937.122" - wire $reduce_or$libresoc.v:45937$1583_Y - attribute \src "libresoc.v:45940.18-45940.128" - wire $reduce_or$libresoc.v:45940$1586_Y - attribute \src "libresoc.v:45942.18-45942.134" - wire $reduce_or$libresoc.v:45942$1588_Y - attribute \src "libresoc.v:45944.18-45944.140" - wire $reduce_or$libresoc.v:45944$1590_Y - attribute \src "libresoc.v:45946.18-45946.90" - wire $reduce_or$libresoc.v:45946$1592_Y - attribute \src "libresoc.v:45947.17-45947.103" - wire $reduce_or$libresoc.v:45947$1593_Y - attribute \src "libresoc.v:45949.17-45949.109" - wire $reduce_or$libresoc.v:45949$1595_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:45934$1580 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:45934$1580_Y + attribute \src "libresoc.v:183522.13-183522.37" + process $proc$libresoc.v:183522$13852 + assign { } { } + assign $1\core_core_spro[9:0] 10'0000000000 + sync always + sync init + update \core_core_spro $1\core_core_spro[9:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:45936$1582 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:45936$1582_Y + attribute \src "libresoc.v:183528.13-183528.36" + process $proc$libresoc.v:183528$13853 + assign { } { } + assign $1\core_core_xer_in[2:0] 3'000 + sync always + sync init + update \core_core_xer_in $1\core_core_xer_in[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:45938$1584 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:45938$1584_Y + attribute \src "libresoc.v:183536.7-183536.28" + process $proc$libresoc.v:183536$13854 + assign { } { } + assign $1\core_cr_out_ok[0:0] 1'0 + sync always + sync init + update \core_cr_out_ok $1\core_cr_out_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:45939$1585 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:45939$1585_Y + attribute \src "libresoc.v:183550.14-183550.45" + process $proc$libresoc.v:183550$13855 + assign { } { } + assign $1\core_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_dec $1\core_dec[63:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:45941$1587 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:45941$1587_Y + attribute \src "libresoc.v:183560.7-183560.24" + process $proc$libresoc.v:183560$13856 + assign { } { } + assign $1\core_ea_ok[0:0] 1'0 + sync always + sync init + update \core_ea_ok $1\core_ea_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:45943$1589 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:45943$1589_Y + attribute \src "libresoc.v:183564.7-183564.23" + process $proc$libresoc.v:183564$13857 + assign { } { } + assign $1\core_eint[0:0] 1'0 + sync always + sync init + update \core_eint $1\core_eint[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:45945$1591 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:45945$1591_Y + attribute \src "libresoc.v:183568.7-183568.28" + process $proc$libresoc.v:183568$13858 + assign { } { } + assign $1\core_fasto1_ok[0:0] 1'0 + sync always + sync init + update \core_fasto1_ok $1\core_fasto1_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:45948$1594 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:45948$1594_Y + attribute \src "libresoc.v:183572.7-183572.28" + process $proc$libresoc.v:183572$13859 + assign { } { } + assign $1\core_fasto2_ok[0:0] 1'0 + sync always + sync init + update \core_fasto2_ok $1\core_fasto2_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:45935$1581 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:45935$1581_Y + attribute \src "libresoc.v:183600.14-183600.45" + process $proc$libresoc.v:183600$13860 + assign { } { } + assign $1\core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_msr $1\core_msr[63:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:45937$1583 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:45937$1583_Y + attribute \src "libresoc.v:183608.14-183608.37" + process $proc$libresoc.v:183608$13861 + assign { } { } + assign $1\core_raw_insn_i[31:0] 0 + sync always + sync init + update \core_raw_insn_i $1\core_raw_insn_i[31:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:45940$1586 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:45940$1586_Y + attribute \src "libresoc.v:183612.7-183612.26" + process $proc$libresoc.v:183612$13862 + assign { } { } + assign $1\core_rego_ok[0:0] 1'0 + sync always + sync init + update \core_rego_ok $1\core_rego_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:45942$1588 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:45942$1588_Y + attribute \src "libresoc.v:183616.7-183616.26" + process $proc$libresoc.v:183616$13863 + assign { } { } + assign $1\core_spro_ok[0:0] 1'0 + sync always + sync init + update \core_spro_ok $1\core_spro_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:45944$1590 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:45944$1590_Y + attribute \src "libresoc.v:183628.7-183628.26" + process $proc$libresoc.v:183628$13864 + assign { } { } + assign $1\core_xer_out[0:0] 1'0 + sync always + sync init + update \core_xer_out $1\core_xer_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:45946$1592 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:45946$1592_Y + attribute \src "libresoc.v:183634.7-183634.30" + process $proc$libresoc.v:183634$13865 + assign { } { } + assign $1\cu_st__rel_o_dly[0:0] 1'0 + sync always + sync init + update \cu_st__rel_o_dly $1\cu_st__rel_o_dly[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:45947$1593 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:45947$1593_Y + attribute \src "libresoc.v:183640.7-183640.24" + process $proc$libresoc.v:183640$13866 + assign { } { } + assign $1\d_cr_delay[0:0] 1'0 + sync always + sync init + update \d_cr_delay $1\d_cr_delay[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:45949$1595 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:45949$1595_Y - end - connect \$7 $not$libresoc.v:45934$1580_Y - connect \$12 $reduce_or$libresoc.v:45935$1581_Y - connect \$11 $not$libresoc.v:45936$1582_Y - connect \$16 $reduce_or$libresoc.v:45937$1583_Y - connect \$15 $not$libresoc.v:45938$1584_Y - connect \$1 $not$libresoc.v:45939$1585_Y - connect \$20 $reduce_or$libresoc.v:45940$1586_Y - connect \$19 $not$libresoc.v:45941$1587_Y - connect \$24 $reduce_or$libresoc.v:45942$1588_Y - connect \$23 $not$libresoc.v:45943$1589_Y - connect \$28 $reduce_or$libresoc.v:45944$1590_Y - connect \$27 $not$libresoc.v:45945$1591_Y - connect \$31 $reduce_or$libresoc.v:45946$1592_Y - connect \$4 $reduce_or$libresoc.v:45947$1593_Y - connect \$3 $not$libresoc.v:45948$1594_Y - connect \$8 $reduce_or$libresoc.v:45949$1595_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:45965.1-46780.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a.sprmap" -attribute \generator "nMigen" -module \sprmap - attribute \src "libresoc.v:46092.3-46122.6" - wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:46123.3-46153.6" - wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:45966.7-45966.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:46154.3-46466.6" - wire width 10 $0\spr_o[9:0] - attribute \src "libresoc.v:46467.3-46779.6" - wire $0\spr_o_ok[0:0] - attribute \src "libresoc.v:46092.3-46122.6" - wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:46123.3-46153.6" - wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:46154.3-46466.6" - wire width 10 $1\spr_o[9:0] - attribute \src "libresoc.v:46467.3-46779.6" - wire $1\spr_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 output 3 \fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 4 \fast_o_ok - attribute \src "libresoc.v:45966.7-45966.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62" - wire width 10 input 5 \spr_i - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" - attribute \enum_value_0000010010 "DSISR" - attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" - attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" - attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" - attribute \enum_value_0100010000 "SPRG0_priv" - attribute \enum_value_0100010001 "SPRG1_priv" - attribute \enum_value_0100010010 "SPRG2_priv" - attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 10 output 1 \spr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \spr_o_ok - attribute \src "libresoc.v:45966.7-45966.20" - process $proc$libresoc.v:45966$1600 + attribute \src "libresoc.v:183644.7-183644.25" + process $proc$libresoc.v:183644$13867 assign { } { } - assign $0\initial[0:0] 1'0 + assign $1\d_reg_delay[0:0] 1'0 sync always - update \initial $0\initial[0:0] sync init + update \d_reg_delay $1\d_reg_delay[0:0] end - attribute \src "libresoc.v:46092.3-46122.6" - process $proc$libresoc.v:46092$1596 + attribute \src "libresoc.v:183648.7-183648.25" + process $proc$libresoc.v:183648$13868 assign { } { } + assign $1\d_xer_delay[0:0] 1'0 + sync always + sync init + update \d_xer_delay $1\d_xer_delay[0:0] + end + attribute \src "libresoc.v:183684.13-183684.34" + process $proc$libresoc.v:183684$13869 assign { } { } - assign $0\fast_o[2:0] $1\fast_o[2:0] - attribute \src "libresoc.v:46093.5-46093.29" - switch \initial - attribute \src "libresoc.v:46093.9-46093.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" - switch \spr_i - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000001 - assign { } { } - assign $1\fast_o[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001000 - assign { } { } - assign $1\fast_o[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001001 - assign { } { } - assign $1\fast_o[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010110 - assign { } { } - assign $1\fast_o[2:0] 3'110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011010 - assign { } { } - assign $1\fast_o[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011011 - assign { } { } - assign $1\fast_o[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100001100 - assign { } { } - assign $1\fast_o[2:0] 3'111 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101111 - assign { } { } - assign $1\fast_o[2:0] 3'010 - case - assign $1\fast_o[2:0] 3'000 - end + assign $1\dbg_dmi_addr_i[3:0] 4'0000 sync always - update \fast_o $0\fast_o[2:0] + sync init + update \dbg_dmi_addr_i $1\dbg_dmi_addr_i[3:0] end - attribute \src "libresoc.v:46123.3-46153.6" - process $proc$libresoc.v:46123$1597 + attribute \src "libresoc.v:183688.14-183688.48" + process $proc$libresoc.v:183688$13870 assign { } { } + assign $1\dbg_dmi_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dbg_dmi_din $1\dbg_dmi_din[63:0] + end + attribute \src "libresoc.v:183694.7-183694.27" + process $proc$libresoc.v:183694$13871 assign { } { } - assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] - attribute \src "libresoc.v:46124.5-46124.29" - switch \initial - attribute \src "libresoc.v:46124.9-46124.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" - switch \spr_i - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000001 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001000 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001001 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010110 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011010 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011011 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100001100 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101111 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - case - assign $1\fast_o_ok[0:0] 1'0 - end + assign $1\dbg_dmi_req_i[0:0] 1'0 sync always - update \fast_o_ok $0\fast_o_ok[0:0] + sync init + update \dbg_dmi_req_i $1\dbg_dmi_req_i[0:0] end - attribute \src "libresoc.v:46154.3-46466.6" - process $proc$libresoc.v:46154$1598 + attribute \src "libresoc.v:183698.7-183698.26" + process $proc$libresoc.v:183698$13872 assign { } { } + assign $1\dbg_dmi_we_i[0:0] 1'0 + sync always + sync init + update \dbg_dmi_we_i $1\dbg_dmi_we_i[0:0] + end + attribute \src "libresoc.v:183752.14-183752.49" + process $proc$libresoc.v:183752$13873 assign { } { } - assign $0\spr_o[9:0] $1\spr_o[9:0] - attribute \src "libresoc.v:46155.5-46155.29" - switch \initial - attribute \src "libresoc.v:46155.9-46155.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" - switch \spr_i - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000011 - assign { } { } - assign $1\spr_o[9:0] 10'0000000001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001101 - assign { } { } - assign $1\spr_o[9:0] 10'0000000100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010001 - assign { } { } - assign $1\spr_o[9:0] 10'0000000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\spr_o[9:0] 10'0000000110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010011 - assign { } { } - assign $1\spr_o[9:0] 10'0000000111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011100 - assign { } { } - assign $1\spr_o[9:0] 10'0000001011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011101 - assign { } { } - assign $1\spr_o[9:0] 10'0000001100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000110000 - assign { } { } - assign $1\spr_o[9:0] 10'0000001101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000111101 - assign { } { } - assign $1\spr_o[9:0] 10'0000001110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000000 - assign { } { } - assign $1\spr_o[9:0] 10'0000001111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\spr_o[9:0] 10'0000010000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000010 - assign { } { } - assign $1\spr_o[9:0] 10'0000010001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000011 - assign { } { } - assign $1\spr_o[9:0] 10'0000010010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010001000 - assign { } { } - assign $1\spr_o[9:0] 10'0000010011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010000 - assign { } { } - assign $1\spr_o[9:0] 10'0000010100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011000 - assign { } { } - assign $1\spr_o[9:0] 10'0000010101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011001 - assign { } { } - assign $1\spr_o[9:0] 10'0000010110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011101 - assign { } { } - assign $1\spr_o[9:0] 10'0000010111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011110 - assign { } { } - assign $1\spr_o[9:0] 10'0000011000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011111 - assign { } { } - assign $1\spr_o[9:0] 10'0000011001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010110000 - assign { } { } - assign $1\spr_o[9:0] 10'0000011010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010110100 - assign { } { } - assign $1\spr_o[9:0] 10'0000011011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111010 - assign { } { } - assign $1\spr_o[9:0] 10'0000011100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111011 - assign { } { } - assign $1\spr_o[9:0] 10'0000011101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111100 - assign { } { } - assign $1\spr_o[9:0] 10'0000011110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111110 - assign { } { } - assign $1\spr_o[9:0] 10'0000011111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000000 - assign { } { } - assign $1\spr_o[9:0] 10'0000100000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000011 - assign { } { } - assign $1\spr_o[9:0] 10'0000100001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100001101 - assign { } { } - assign $1\spr_o[9:0] 10'0000100011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010000 - assign { } { } - assign $1\spr_o[9:0] 10'0000100100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010001 - assign { } { } - assign $1\spr_o[9:0] 10'0000100101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\spr_o[9:0] 10'0000100110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010011 - assign { } { } - assign $1\spr_o[9:0] 10'0000100111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011011 - assign { } { } - assign $1\spr_o[9:0] 10'0000101000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011100 - assign { } { } - assign $1\spr_o[9:0] 10'0000101001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011101 - assign { } { } - assign $1\spr_o[9:0] 10'0000101010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011110 - assign { } { } - assign $1\spr_o[9:0] 10'0000101011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011111 - assign { } { } - assign $1\spr_o[9:0] 10'0000101100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110000 - assign { } { } - assign $1\spr_o[9:0] 10'0000101101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110001 - assign { } { } - assign $1\spr_o[9:0] 10'0000101110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110010 - assign { } { } - assign $1\spr_o[9:0] 10'0000101111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110011 - assign { } { } - assign $1\spr_o[9:0] 10'0000110000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110100 - assign { } { } - assign $1\spr_o[9:0] 10'0000110001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110101 - assign { } { } - assign $1\spr_o[9:0] 10'0000110010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110110 - assign { } { } - assign $1\spr_o[9:0] 10'0000110011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111001 - assign { } { } - assign $1\spr_o[9:0] 10'0000110100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111010 - assign { } { } - assign $1\spr_o[9:0] 10'0000110101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111011 - assign { } { } - assign $1\spr_o[9:0] 10'0000110110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111110 - assign { } { } - assign $1\spr_o[9:0] 10'0000110111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111111 - assign { } { } - assign $1\spr_o[9:0] 10'0000111000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010000 - assign { } { } - assign $1\spr_o[9:0] 10'0000111001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010001 - assign { } { } - assign $1\spr_o[9:0] 10'0000111010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010010 - assign { } { } - assign $1\spr_o[9:0] 10'0000111011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010011 - assign { } { } - assign $1\spr_o[9:0] 10'0000111100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101011101 - assign { } { } - assign $1\spr_o[9:0] 10'0000111101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110111110 - assign { } { } - assign $1\spr_o[9:0] 10'0000111110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111010000 - assign { } { } - assign $1\spr_o[9:0] 10'0000111111 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000000 - assign { } { } - assign $1\spr_o[9:0] 10'0001000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000001 - assign { } { } - assign $1\spr_o[9:0] 10'0001000001 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000010 - assign { } { } - assign $1\spr_o[9:0] 10'0001000010 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000011 - assign { } { } - assign $1\spr_o[9:0] 10'0001000011 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000100 - assign { } { } - assign $1\spr_o[9:0] 10'0001000100 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000101 - assign { } { } - assign $1\spr_o[9:0] 10'0001000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000110 - assign { } { } - assign $1\spr_o[9:0] 10'0001000110 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000111 - assign { } { } - assign $1\spr_o[9:0] 10'0001000111 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001000 - assign { } { } - assign $1\spr_o[9:0] 10'0001001000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001011 - assign { } { } - assign $1\spr_o[9:0] 10'0001001001 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001100 - assign { } { } - assign $1\spr_o[9:0] 10'0001001010 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001101 - assign { } { } - assign $1\spr_o[9:0] 10'0001001011 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001110 - assign { } { } - assign $1\spr_o[9:0] 10'0001001100 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010000 - assign { } { } - assign $1\spr_o[9:0] 10'0001001101 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010001 - assign { } { } - assign $1\spr_o[9:0] 10'0001001110 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010010 - assign { } { } - assign $1\spr_o[9:0] 10'0001001111 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010011 - assign { } { } - assign $1\spr_o[9:0] 10'0001010000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010100 - assign { } { } - assign $1\spr_o[9:0] 10'0001010001 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010101 - assign { } { } - assign $1\spr_o[9:0] 10'0001010010 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010110 - assign { } { } - assign $1\spr_o[9:0] 10'0001010011 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010111 - assign { } { } - assign $1\spr_o[9:0] 10'0001010100 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011000 - assign { } { } - assign $1\spr_o[9:0] 10'0001010101 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011011 - assign { } { } - assign $1\spr_o[9:0] 10'0001010110 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011100 - assign { } { } - assign $1\spr_o[9:0] 10'0001010111 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011101 - assign { } { } - assign $1\spr_o[9:0] 10'0001011000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011110 - assign { } { } - assign $1\spr_o[9:0] 10'0001011001 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100000 - assign { } { } - assign $1\spr_o[9:0] 10'0001011010 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100001 - assign { } { } - assign $1\spr_o[9:0] 10'0001011011 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100010 - assign { } { } - assign $1\spr_o[9:0] 10'0001011100 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100011 - assign { } { } - assign $1\spr_o[9:0] 10'0001011101 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100100 - assign { } { } - assign $1\spr_o[9:0] 10'0001011110 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100101 - assign { } { } - assign $1\spr_o[9:0] 10'0001011111 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100110 - assign { } { } - assign $1\spr_o[9:0] 10'0001100000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101000 - assign { } { } - assign $1\spr_o[9:0] 10'0001100001 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101001 - assign { } { } - assign $1\spr_o[9:0] 10'0001100010 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101010 - assign { } { } - assign $1\spr_o[9:0] 10'0001100011 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101011 - assign { } { } - assign $1\spr_o[9:0] 10'0001100100 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100110000 - assign { } { } - assign $1\spr_o[9:0] 10'0001100110 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100110111 - assign { } { } - assign $1\spr_o[9:0] 10'0001100111 - attribute \src "libresoc.v:0.0-0.0" - case 10'1101010000 - assign { } { } - assign $1\spr_o[9:0] 10'0001101000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1101010001 - assign { } { } - assign $1\spr_o[9:0] 10'0001101001 - attribute \src "libresoc.v:0.0-0.0" - case 10'1101010111 - assign { } { } - assign $1\spr_o[9:0] 10'0001101010 - attribute \src "libresoc.v:0.0-0.0" - case 10'1110000000 - assign { } { } - assign $1\spr_o[9:0] 10'0001101011 - attribute \src "libresoc.v:0.0-0.0" - case 10'1110000010 - assign { } { } - assign $1\spr_o[9:0] 10'0001101100 + assign $1\dec2_cur_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dec2_cur_dec $1\dec2_cur_dec[63:0] + end + attribute \src "libresoc.v:183756.7-183756.27" + process $proc$libresoc.v:183756$13874 + assign { } { } + assign $1\dec2_cur_eint[0:0] 1'0 + sync always + sync init + update \dec2_cur_eint $1\dec2_cur_eint[0:0] + end + attribute \src "libresoc.v:183760.14-183760.49" + process $proc$libresoc.v:183760$13875 + assign { } { } + assign $1\dec2_cur_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dec2_cur_msr $1\dec2_cur_msr[63:0] + end + attribute \src "libresoc.v:183764.14-183764.48" + process $proc$libresoc.v:183764$13876 + assign { } { } + assign $1\dec2_cur_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dec2_cur_pc $1\dec2_cur_pc[63:0] + end + attribute \src "libresoc.v:184173.13-184173.25" + process $proc$libresoc.v:184173$13877 + assign { } { } + assign $1\delay[1:0] 2'11 + sync always + sync init + update \delay $1\delay[1:0] + end + attribute \src "libresoc.v:184189.13-184189.29" + process $proc$libresoc.v:184189$13878 + assign { } { } + assign $1\fsm_state[1:0] 2'00 + sync always + sync init + update \fsm_state $1\fsm_state[1:0] + end + attribute \src "libresoc.v:184191.13-184191.35" + process $proc$libresoc.v:184191$13879 + assign { } { } + assign $0\fsm_state$133[1:0]$13880 2'00 + sync always + sync init + update \fsm_state$133 $0\fsm_state$133[1:0]$13880 + end + attribute \src "libresoc.v:184433.14-184433.28" + process $proc$libresoc.v:184433$13881 + assign { } { } + assign $1\ilatch[31:0] 0 + sync always + sync init + update \ilatch $1\ilatch[31:0] + end + attribute \src "libresoc.v:184451.7-184451.30" + process $proc$libresoc.v:184451$13882 + assign { } { } + assign $1\jtag_dmi0__ack_o[0:0] 1'0 + sync always + sync init + update \jtag_dmi0__ack_o $1\jtag_dmi0__ack_o[0:0] + end + attribute \src "libresoc.v:184459.14-184459.52" + process $proc$libresoc.v:184459$13883 + assign { } { } + assign $1\jtag_dmi0__dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \jtag_dmi0__dout $1\jtag_dmi0__dout[63:0] + end + attribute \src "libresoc.v:184515.7-184515.22" + process $proc$libresoc.v:184515$13884 + assign { } { } + assign $1\msr_read[0:0] 1'1 + sync always + sync init + update \msr_read $1\msr_read[0:0] + end + attribute \src "libresoc.v:184543.7-184543.24" + process $proc$libresoc.v:184543$13885 + assign { } { } + assign $1\pc_changed[0:0] 1'0 + sync always + sync init + update \pc_changed $1\pc_changed[0:0] + end + attribute \src "libresoc.v:184553.7-184553.25" + process $proc$libresoc.v:184553$13886 + assign { } { } + assign $1\pc_ok_delay[0:0] 1'0 + sync always + sync init + update \pc_ok_delay $1\pc_ok_delay[0:0] + end + attribute \src "libresoc.v:184993.3-184994.41" + process $proc$libresoc.v:184993$13288 + assign { } { } + assign $0\dec2_cur_dec[63:0] \dec2_cur_dec$next + sync posedge \clk + update \dec2_cur_dec $0\dec2_cur_dec[63:0] + end + attribute \src "libresoc.v:184995.3-184996.33" + process $proc$libresoc.v:184995$13289 + assign { } { } + assign $0\core_dec[63:0] \core_dec$next + sync posedge \clk + update \core_dec $0\core_dec[63:0] + end + attribute \src "libresoc.v:184997.3-184998.41" + process $proc$libresoc.v:184997$13290 + assign { } { } + assign $0\dec2_cur_msr[63:0] \dec2_cur_msr$next + sync posedge \clk + update \dec2_cur_msr $0\dec2_cur_msr[63:0] + end + attribute \src "libresoc.v:184999.3-185000.35" + process $proc$libresoc.v:184999$13291 + assign { } { } + assign $0\fsm_state[1:0] \fsm_state$next + sync posedge \clk + update \fsm_state $0\fsm_state[1:0] + end + attribute \src "libresoc.v:185001.3-185002.33" + process $proc$libresoc.v:185001$13292 + assign { } { } + assign $0\msr_read[0:0] \msr_read$next + sync posedge \clk + update \msr_read $0\msr_read[0:0] + end + attribute \src "libresoc.v:185003.3-185004.39" + process $proc$libresoc.v:185003$13293 + assign { } { } + assign $0\dec2_cur_pc[63:0] \dec2_cur_pc$next + sync posedge \clk + update \dec2_cur_pc $0\dec2_cur_pc[63:0] + end + attribute \src "libresoc.v:185005.3-185006.57" + process $proc$libresoc.v:185005$13294 + assign { } { } + assign $0\core_bigendian_i$10[0:0]$13295 \core_bigendian_i$10$next + sync posedge \clk + update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13295 + end + attribute \src "libresoc.v:185007.3-185008.47" + process $proc$libresoc.v:185007$13296 + assign { } { } + assign $0\core_raw_insn_i[31:0] \core_raw_insn_i$next + sync posedge \clk + update \core_raw_insn_i $0\core_raw_insn_i[31:0] + end + attribute \src "libresoc.v:185009.3-185010.41" + process $proc$libresoc.v:185009$13297 + assign { } { } + assign $0\core_asmcode[7:0] \core_asmcode$next + sync posedge \clk + update \core_asmcode $0\core_asmcode[7:0] + end + attribute \src "libresoc.v:185011.3-185012.45" + process $proc$libresoc.v:185011$13298 + assign { } { } + assign $0\core_core_rego[4:0] \core_core_rego$next + sync posedge \clk + update \core_core_rego $0\core_core_rego[4:0] + end + attribute \src "libresoc.v:185013.3-185014.41" + process $proc$libresoc.v:185013$13299 + assign { } { } + assign $0\core_rego_ok[0:0] \core_rego_ok$next + sync posedge \clk + update \core_rego_ok $0\core_rego_ok[0:0] + end + attribute \src "libresoc.v:185015.3-185016.45" + process $proc$libresoc.v:185015$13300 + assign { } { } + assign $0\fsm_state$133[1:0]$13301 \fsm_state$133$next + sync posedge \clk + update \fsm_state$133 $0\fsm_state$133[1:0]$13301 + end + attribute \src "libresoc.v:185017.3-185018.41" + process $proc$libresoc.v:185017$13302 + assign { } { } + assign $0\core_core_ea[4:0] \core_core_ea$next + sync posedge \clk + update \core_core_ea $0\core_core_ea[4:0] + end + attribute \src "libresoc.v:185019.3-185020.37" + process $proc$libresoc.v:185019$13303 + assign { } { } + assign $0\core_ea_ok[0:0] \core_ea_ok$next + sync posedge \clk + update \core_ea_ok $0\core_ea_ok[0:0] + end + attribute \src "libresoc.v:185021.3-185022.45" + process $proc$libresoc.v:185021$13304 + assign { } { } + assign $0\core_core_reg1[4:0] \core_core_reg1$next + sync posedge \clk + update \core_core_reg1 $0\core_core_reg1[4:0] + end + attribute \src "libresoc.v:185023.3-185024.51" + process $proc$libresoc.v:185023$13305 + assign { } { } + assign $0\core_core_reg1_ok[0:0] \core_core_reg1_ok$next + sync posedge \clk + update \core_core_reg1_ok $0\core_core_reg1_ok[0:0] + end + attribute \src "libresoc.v:185025.3-185026.45" + process $proc$libresoc.v:185025$13306 + assign { } { } + assign $0\core_core_reg2[4:0] \core_core_reg2$next + sync posedge \clk + update \core_core_reg2 $0\core_core_reg2[4:0] + end + attribute \src "libresoc.v:185027.3-185028.51" + process $proc$libresoc.v:185027$13307 + assign { } { } + assign $0\core_core_reg2_ok[0:0] \core_core_reg2_ok$next + sync posedge \clk + update \core_core_reg2_ok $0\core_core_reg2_ok[0:0] + end + attribute \src "libresoc.v:185029.3-185030.45" + process $proc$libresoc.v:185029$13308 + assign { } { } + assign $0\core_core_reg3[4:0] \core_core_reg3$next + sync posedge \clk + update \core_core_reg3 $0\core_core_reg3[4:0] + end + attribute \src "libresoc.v:185031.3-185032.51" + process $proc$libresoc.v:185031$13309 + assign { } { } + assign $0\core_core_reg3_ok[0:0] \core_core_reg3_ok$next + sync posedge \clk + update \core_core_reg3_ok $0\core_core_reg3_ok[0:0] + end + attribute \src "libresoc.v:185033.3-185034.45" + process $proc$libresoc.v:185033$13310 + assign { } { } + assign $0\core_core_spro[9:0] \core_core_spro$next + sync posedge \clk + update \core_core_spro $0\core_core_spro[9:0] + end + attribute \src "libresoc.v:185035.3-185036.41" + process $proc$libresoc.v:185035$13311 + assign { } { } + assign $0\core_spro_ok[0:0] \core_spro_ok$next + sync posedge \clk + update \core_spro_ok $0\core_spro_ok[0:0] + end + attribute \src "libresoc.v:185037.3-185038.39" + process $proc$libresoc.v:185037$13312 + assign { } { } + assign $0\d_xer_delay[0:0] \d_xer_delay$next + sync posedge \clk + update \d_xer_delay $0\d_xer_delay[0:0] + end + attribute \src "libresoc.v:185039.3-185040.45" + process $proc$libresoc.v:185039$13313 + assign { } { } + assign $0\core_core_spr1[9:0] \core_core_spr1$next + sync posedge \clk + update \core_core_spr1 $0\core_core_spr1[9:0] + end + attribute \src "libresoc.v:185041.3-185042.51" + process $proc$libresoc.v:185041$13314 + assign { } { } + assign $0\core_core_spr1_ok[0:0] \core_core_spr1_ok$next + sync posedge \clk + update \core_core_spr1_ok $0\core_core_spr1_ok[0:0] + end + attribute \src "libresoc.v:185043.3-185044.49" + process $proc$libresoc.v:185043$13315 + assign { } { } + assign $0\core_core_xer_in[2:0] \core_core_xer_in$next + sync posedge \clk + update \core_core_xer_in $0\core_core_xer_in[2:0] + end + attribute \src "libresoc.v:185045.3-185046.41" + process $proc$libresoc.v:185045$13316 + assign { } { } + assign $0\core_xer_out[0:0] \core_xer_out$next + sync posedge \clk + update \core_xer_out $0\core_xer_out[0:0] + end + attribute \src "libresoc.v:185047.3-185048.47" + process $proc$libresoc.v:185047$13317 + assign { } { } + assign $0\core_core_fast1[2:0] \core_core_fast1$next + sync posedge \clk + update \core_core_fast1 $0\core_core_fast1[2:0] + end + attribute \src "libresoc.v:185049.3-185050.53" + process $proc$libresoc.v:185049$13318 + assign { } { } + assign $0\core_core_fast1_ok[0:0] \core_core_fast1_ok$next + sync posedge \clk + update \core_core_fast1_ok $0\core_core_fast1_ok[0:0] + end + attribute \src "libresoc.v:185051.3-185052.47" + process $proc$libresoc.v:185051$13319 + assign { } { } + assign $0\core_core_fast2[2:0] \core_core_fast2$next + sync posedge \clk + update \core_core_fast2 $0\core_core_fast2[2:0] + end + attribute \src "libresoc.v:185053.3-185054.53" + process $proc$libresoc.v:185053$13320 + assign { } { } + assign $0\core_core_fast2_ok[0:0] \core_core_fast2_ok$next + sync posedge \clk + update \core_core_fast2_ok $0\core_core_fast2_ok[0:0] + end + attribute \src "libresoc.v:185055.3-185056.49" + process $proc$libresoc.v:185055$13321 + assign { } { } + assign $0\core_core_fasto1[2:0] \core_core_fasto1$next + sync posedge \clk + update \core_core_fasto1 $0\core_core_fasto1[2:0] + end + attribute \src "libresoc.v:185057.3-185058.45" + process $proc$libresoc.v:185057$13322 + assign { } { } + assign $0\core_fasto1_ok[0:0] \core_fasto1_ok$next + sync posedge \clk + update \core_fasto1_ok $0\core_fasto1_ok[0:0] + end + attribute \src "libresoc.v:185059.3-185060.37" + process $proc$libresoc.v:185059$13323 + assign { } { } + assign $0\d_cr_delay[0:0] \d_cr_delay$next + sync posedge \clk + update \d_cr_delay $0\d_cr_delay[0:0] + end + attribute \src "libresoc.v:185061.3-185062.49" + process $proc$libresoc.v:185061$13324 + assign { } { } + assign $0\core_core_fasto2[2:0] \core_core_fasto2$next + sync posedge \clk + update \core_core_fasto2 $0\core_core_fasto2[2:0] + end + attribute \src "libresoc.v:185063.3-185064.45" + process $proc$libresoc.v:185063$13325 + assign { } { } + assign $0\core_fasto2_ok[0:0] \core_fasto2_ok$next + sync posedge \clk + update \core_fasto2_ok $0\core_fasto2_ok[0:0] + end + attribute \src "libresoc.v:185065.3-185066.49" + process $proc$libresoc.v:185065$13326 + assign { } { } + assign $0\core_core_cr_in1[2:0] \core_core_cr_in1$next + sync posedge \clk + update \core_core_cr_in1 $0\core_core_cr_in1[2:0] + end + attribute \src "libresoc.v:185067.3-185068.55" + process $proc$libresoc.v:185067$13327 + assign { } { } + assign $0\core_core_cr_in1_ok[0:0] \core_core_cr_in1_ok$next + sync posedge \clk + update \core_core_cr_in1_ok $0\core_core_cr_in1_ok[0:0] + end + attribute \src "libresoc.v:185069.3-185070.49" + process $proc$libresoc.v:185069$13328 + assign { } { } + assign $0\core_core_cr_in2[2:0] \core_core_cr_in2$next + sync posedge \clk + update \core_core_cr_in2 $0\core_core_cr_in2[2:0] + end + attribute \src "libresoc.v:185071.3-185072.55" + process $proc$libresoc.v:185071$13329 + assign { } { } + assign $0\core_core_cr_in2_ok[0:0] \core_core_cr_in2_ok$next + sync posedge \clk + update \core_core_cr_in2_ok $0\core_core_cr_in2_ok[0:0] + end + attribute \src "libresoc.v:185073.3-185074.55" + process $proc$libresoc.v:185073$13330 + assign { } { } + assign $0\core_core_cr_in2$1[2:0]$13331 \core_core_cr_in2$1$next + sync posedge \clk + update \core_core_cr_in2$1 $0\core_core_cr_in2$1[2:0]$13331 + end + attribute \src "libresoc.v:185075.3-185076.61" + process $proc$libresoc.v:185075$13332 + assign { } { } + assign $0\core_core_cr_in2_ok$2[0:0]$13333 \core_core_cr_in2_ok$2$next + sync posedge \clk + update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13333 + end + attribute \src "libresoc.v:185077.3-185078.49" + process $proc$libresoc.v:185077$13334 + assign { } { } + assign $0\core_core_cr_out[2:0] \core_core_cr_out$next + sync posedge \clk + update \core_core_cr_out $0\core_core_cr_out[2:0] + end + attribute \src "libresoc.v:185079.3-185080.45" + process $proc$libresoc.v:185079$13335 + assign { } { } + assign $0\core_cr_out_ok[0:0] \core_cr_out_ok$next + sync posedge \clk + update \core_cr_out_ok $0\core_cr_out_ok[0:0] + end + attribute \src "libresoc.v:185081.3-185082.39" + process $proc$libresoc.v:185081$13336 + assign { } { } + assign $0\d_reg_delay[0:0] \d_reg_delay$next + sync posedge \clk + update \d_reg_delay $0\d_reg_delay[0:0] + end + attribute \src "libresoc.v:185083.3-185084.53" + process $proc$libresoc.v:185083$13337 + assign { } { } + assign $0\core_core_core_msr[63:0] \core_core_core_msr$next + sync posedge \clk + update \core_core_core_msr $0\core_core_core_msr[63:0] + end + attribute \src "libresoc.v:185085.3-185086.53" + process $proc$libresoc.v:185085$13338 + assign { } { } + assign $0\core_core_core_cia[63:0] \core_core_core_cia$next + sync posedge \clk + update \core_core_core_cia $0\core_core_core_cia[63:0] + end + attribute \src "libresoc.v:185087.3-185088.55" + process $proc$libresoc.v:185087$13339 + assign { } { } + assign $0\core_core_core_insn[31:0] \core_core_core_insn$next + sync posedge \clk + update \core_core_core_insn $0\core_core_core_insn[31:0] + end + attribute \src "libresoc.v:185089.3-185090.65" + process $proc$libresoc.v:185089$13340 + assign { } { } + assign $0\core_core_core_insn_type[6:0] \core_core_core_insn_type$next + sync posedge \clk + update \core_core_core_insn_type $0\core_core_core_insn_type[6:0] + end + attribute \src "libresoc.v:185091.3-185092.61" + process $proc$libresoc.v:185091$13341 + assign { } { } + assign $0\core_core_core_fn_unit[11:0] \core_core_core_fn_unit$next + sync posedge \clk + update \core_core_core_fn_unit $0\core_core_core_fn_unit[11:0] + end + attribute \src "libresoc.v:185093.3-185094.41" + process $proc$libresoc.v:185093$13342 + assign { } { } + assign $0\core_core_lk[0:0] \core_core_lk$next + sync posedge \clk + update \core_core_lk $0\core_core_lk[0:0] + end + attribute \src "libresoc.v:185095.3-185096.51" + process $proc$libresoc.v:185095$13343 + assign { } { } + assign $0\core_core_core_rc[0:0] \core_core_core_rc$next + sync posedge \clk + update \core_core_core_rc $0\core_core_core_rc[0:0] + end + attribute \src "libresoc.v:185097.3-185098.57" + process $proc$libresoc.v:185097$13344 + assign { } { } + assign $0\core_core_core_rc_ok[0:0] \core_core_core_rc_ok$next + sync posedge \clk + update \core_core_core_rc_ok $0\core_core_core_rc_ok[0:0] + end + attribute \src "libresoc.v:185099.3-185100.51" + process $proc$libresoc.v:185099$13345 + assign { } { } + assign $0\core_core_core_oe[0:0] \core_core_core_oe$next + sync posedge \clk + update \core_core_core_oe $0\core_core_core_oe[0:0] + end + attribute \src "libresoc.v:185101.3-185102.57" + process $proc$libresoc.v:185101$13346 + assign { } { } + assign $0\core_core_core_oe_ok[0:0] \core_core_core_oe_ok$next + sync posedge \clk + update \core_core_core_oe_ok $0\core_core_core_oe_ok[0:0] + end + attribute \src "libresoc.v:185103.3-185104.29" + process $proc$libresoc.v:185103$13347 + assign { } { } + assign $0\ilatch[31:0] \ilatch$next + sync posedge \clk + update \ilatch $0\ilatch[31:0] + end + attribute \src "libresoc.v:185105.3-185106.69" + process $proc$libresoc.v:185105$13348 + assign { } { } + assign $0\core_core_core_input_carry[1:0] \core_core_core_input_carry$next + sync posedge \clk + update \core_core_core_input_carry $0\core_core_core_input_carry[1:0] + end + attribute \src "libresoc.v:185107.3-185108.63" + process $proc$libresoc.v:185107$13349 + assign { } { } + assign $0\core_core_core_traptype[7:0] \core_core_core_traptype$next + sync posedge \clk + update \core_core_core_traptype $0\core_core_core_traptype[7:0] + end + attribute \src "libresoc.v:185109.3-185110.71" + process $proc$libresoc.v:185109$13350 + assign { } { } + assign $0\core_core_core_exc_$signal[0:0]$13351 \core_core_core_exc_$signal$next + sync posedge \clk + update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13351 + end + attribute \src "libresoc.v:185111.3-185112.75" + process $proc$libresoc.v:185111$13352 + assign { } { } + assign $0\core_core_core_exc_$signal$3[0:0]$13353 \core_core_core_exc_$signal$3$next + sync posedge \clk + update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13353 + end + attribute \src "libresoc.v:185113.3-185114.75" + process $proc$libresoc.v:185113$13354 + assign { } { } + assign $0\core_core_core_exc_$signal$4[0:0]$13355 \core_core_core_exc_$signal$4$next + sync posedge \clk + update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13355 + end + attribute \src "libresoc.v:185115.3-185116.75" + process $proc$libresoc.v:185115$13356 + assign { } { } + assign $0\core_core_core_exc_$signal$5[0:0]$13357 \core_core_core_exc_$signal$5$next + sync posedge \clk + update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13357 + end + attribute \src "libresoc.v:185117.3-185118.75" + process $proc$libresoc.v:185117$13358 + assign { } { } + assign $0\core_core_core_exc_$signal$6[0:0]$13359 \core_core_core_exc_$signal$6$next + sync posedge \clk + update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13359 + end + attribute \src "libresoc.v:185119.3-185120.75" + process $proc$libresoc.v:185119$13360 + assign { } { } + assign $0\core_core_core_exc_$signal$7[0:0]$13361 \core_core_core_exc_$signal$7$next + sync posedge \clk + update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13361 + end + attribute \src "libresoc.v:185121.3-185122.75" + process $proc$libresoc.v:185121$13362 + assign { } { } + assign $0\core_core_core_exc_$signal$8[0:0]$13363 \core_core_core_exc_$signal$8$next + sync posedge \clk + update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13363 + end + attribute \src "libresoc.v:185123.3-185124.75" + process $proc$libresoc.v:185123$13364 + assign { } { } + assign $0\core_core_core_exc_$signal$9[0:0]$13365 \core_core_core_exc_$signal$9$next + sync posedge \clk + update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13365 + end + attribute \src "libresoc.v:185125.3-185126.41" + process $proc$libresoc.v:185125$13366 + assign { } { } + assign $0\core_core_pc[63:0] \core_core_pc$next + sync posedge \clk + update \core_core_pc $0\core_core_pc[63:0] + end + attribute \src "libresoc.v:185127.3-185128.63" + process $proc$libresoc.v:185127$13367 + assign { } { } + assign $0\core_core_core_trapaddr[12:0] \core_core_core_trapaddr$next + sync posedge \clk + update \core_core_core_trapaddr $0\core_core_core_trapaddr[12:0] + end + attribute \src "libresoc.v:185129.3-185130.57" + process $proc$libresoc.v:185129$13368 + assign { } { } + assign $0\core_core_core_cr_rd[7:0] \core_core_core_cr_rd$next + sync posedge \clk + update \core_core_core_cr_rd $0\core_core_core_cr_rd[7:0] + end + attribute \src "libresoc.v:185131.3-185132.63" + process $proc$libresoc.v:185131$13369 + assign { } { } + assign $0\core_core_core_cr_rd_ok[0:0] \core_core_core_cr_rd_ok$next + sync posedge \clk + update \core_core_core_cr_rd_ok $0\core_core_core_cr_rd_ok[0:0] + end + attribute \src "libresoc.v:185133.3-185134.57" + process $proc$libresoc.v:185133$13370 + assign { } { } + assign $0\core_core_core_cr_wr[7:0] \core_core_core_cr_wr$next + sync posedge \clk + update \core_core_core_cr_wr $0\core_core_core_cr_wr[7:0] + end + attribute \src "libresoc.v:185135.3-185136.53" + process $proc$libresoc.v:185135$13371 + assign { } { } + assign $0\core_core_cr_wr_ok[0:0] \core_core_cr_wr_ok$next + sync posedge \clk + update \core_core_cr_wr_ok $0\core_core_cr_wr_ok[0:0] + end + attribute \src "libresoc.v:185137.3-185138.63" + process $proc$libresoc.v:185137$13372 + assign { } { } + assign $0\core_core_core_is_32bit[0:0] \core_core_core_is_32bit$next + sync posedge \clk + update \core_core_core_is_32bit $0\core_core_core_is_32bit[0:0] + end + attribute \src "libresoc.v:185139.3-185140.37" + process $proc$libresoc.v:185139$13373 + assign { } { } + assign $0\pc_changed[0:0] \pc_changed$next + sync posedge \clk + update \pc_changed $0\pc_changed[0:0] + end + attribute \src "libresoc.v:185141.3-185142.39" + process $proc$libresoc.v:185141$13374 + assign { } { } + assign $0\pc_ok_delay[0:0] \pc_ok_delay$next + sync posedge \clk + update \pc_ok_delay $0\pc_ok_delay[0:0] + end + attribute \src "libresoc.v:185143.3-185144.43" + process $proc$libresoc.v:185143$13375 + assign { } { } + assign $0\cu_st__rel_o_dly[0:0] \core_cu_st__rel_o + sync posedge \clk + update \cu_st__rel_o_dly $0\cu_st__rel_o_dly[0:0] + end + attribute \src "libresoc.v:185145.3-185146.27" + process $proc$libresoc.v:185145$13376 + assign { } { } + assign $0\delay[1:0] \delay$next + sync posedge \por_clk + update \delay $0\delay[1:0] + end + attribute \src "libresoc.v:185147.3-185148.33" + process $proc$libresoc.v:185147$13377 + assign { } { } + assign $0\core_msr[63:0] \core_msr$next + sync posedge \clk + update \core_msr $0\core_msr[63:0] + end + attribute \src "libresoc.v:185149.3-185150.43" + process $proc$libresoc.v:185149$13378 + assign { } { } + assign $0\dec2_cur_eint[0:0] \dec2_cur_eint$next + sync posedge \clk + update \dec2_cur_eint $0\dec2_cur_eint[0:0] + end + attribute \src "libresoc.v:185151.3-185152.47" + process $proc$libresoc.v:185151$13379 + assign { } { } + assign $0\jtag_dmi0__dout[63:0] \jtag_dmi0__dout$next + sync posedge \clk + update \jtag_dmi0__dout $0\jtag_dmi0__dout[63:0] + end + attribute \src "libresoc.v:185153.3-185154.49" + process $proc$libresoc.v:185153$13380 + assign { } { } + assign $0\jtag_dmi0__ack_o[0:0] \jtag_dmi0__ack_o$next + sync posedge \clk + update \jtag_dmi0__ack_o $0\jtag_dmi0__ack_o[0:0] + end + attribute \src "libresoc.v:185155.3-185156.39" + process $proc$libresoc.v:185155$13381 + assign { } { } + assign $0\dbg_dmi_din[63:0] \dbg_dmi_din$next + sync posedge \clk + update \dbg_dmi_din $0\dbg_dmi_din[63:0] + end + attribute \src "libresoc.v:185157.3-185158.41" + process $proc$libresoc.v:185157$13382 + assign { } { } + assign $0\dbg_dmi_we_i[0:0] \dbg_dmi_we_i$next + sync posedge \clk + update \dbg_dmi_we_i $0\dbg_dmi_we_i[0:0] + end + attribute \src "libresoc.v:185159.3-185160.43" + process $proc$libresoc.v:185159$13383 + assign { } { } + assign $0\dbg_dmi_req_i[0:0] \dbg_dmi_req_i$next + sync posedge \clk + update \dbg_dmi_req_i $0\dbg_dmi_req_i[0:0] + end + attribute \src "libresoc.v:185161.3-185162.45" + process $proc$libresoc.v:185161$13384 + assign { } { } + assign $0\dbg_dmi_addr_i[3:0] \dbg_dmi_addr_i$next + sync posedge \clk + update \dbg_dmi_addr_i $0\dbg_dmi_addr_i[3:0] + end + attribute \src "libresoc.v:185163.3-185164.35" + process $proc$libresoc.v:185163$13385 + assign { } { } + assign $0\core_eint[0:0] \core_eint$next + sync posedge \clk + update \core_eint $0\core_eint[0:0] + end + attribute \src "libresoc.v:185730.3-185738.6" + process $proc$libresoc.v:185730$13386 + assign { } { } + assign { } { } + assign $0\dbg_dmi_addr_i$next[3:0]$13387 $1\dbg_dmi_addr_i$next[3:0]$13388 + attribute \src "libresoc.v:185731.5-185731.29" + switch \initial + attribute \src "libresoc.v:185731.9-185731.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" - case 10'1111111111 + case 1'1 assign { } { } - assign $1\spr_o[9:0] 10'0001101101 + assign $1\dbg_dmi_addr_i$next[3:0]$13388 4'0000 case - assign $1\spr_o[9:0] 10'0000000000 + assign $1\dbg_dmi_addr_i$next[3:0]$13388 \jtag_dmi0__addr_i end sync always - update \spr_o $0\spr_o[9:0] + update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$13387 end - attribute \src "libresoc.v:46467.3-46779.6" - process $proc$libresoc.v:46467$1599 + attribute \src "libresoc.v:185739.3-185747.6" + process $proc$libresoc.v:185739$13389 assign { } { } assign { } { } - assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "libresoc.v:46468.5-46468.29" + assign $0\dbg_dmi_req_i$next[0:0]$13390 $1\dbg_dmi_req_i$next[0:0]$13391 + attribute \src "libresoc.v:185740.5-185740.29" switch \initial - attribute \src "libresoc.v:46468.9-46468.17" + attribute \src "libresoc.v:185740.9-185740.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" - switch \spr_i - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000110000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000111101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010001000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010110000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010110100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100001101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101011101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110111110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100110000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100110111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1101010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1101010001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1101010111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1110000000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1110000010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" - case 10'1111111111 + case 1'1 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dbg_dmi_req_i$next[0:0]$13391 1'0 case - assign $1\spr_o_ok[0:0] 1'0 + assign $1\dbg_dmi_req_i$next[0:0]$13391 \jtag_dmi0__req_i end sync always - update \spr_o_ok $0\spr_o_ok[0:0] + update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$13390 end -end -attribute \src "libresoc.v:46784.1-47599.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o.sprmap" -attribute \generator "nMigen" -module \sprmap$2 - attribute \src "libresoc.v:46911.3-46941.6" - wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:46942.3-46972.6" - wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:46785.7-46785.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:46973.3-47285.6" - wire width 10 $0\spr_o[9:0] - attribute \src "libresoc.v:47286.3-47598.6" - wire $0\spr_o_ok[0:0] - attribute \src "libresoc.v:46911.3-46941.6" - wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:46942.3-46972.6" - wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:46973.3-47285.6" - wire width 10 $1\spr_o[9:0] - attribute \src "libresoc.v:47286.3-47598.6" - wire $1\spr_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 output 3 \fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 4 \fast_o_ok - attribute \src "libresoc.v:46785.7-46785.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62" - wire width 10 input 5 \spr_i - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" - attribute \enum_value_0000010010 "DSISR" - attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" - attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" - attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" - attribute \enum_value_0100010000 "SPRG0_priv" - attribute \enum_value_0100010001 "SPRG1_priv" - attribute \enum_value_0100010010 "SPRG2_priv" - attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 10 output 1 \spr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \spr_o_ok - attribute \src "libresoc.v:46785.7-46785.20" - process $proc$libresoc.v:46785$1605 + attribute \src "libresoc.v:185748.3-185768.6" + process $proc$libresoc.v:185748$13392 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:46911.3-46941.6" - process $proc$libresoc.v:46911$1601 assign { } { } assign { } { } - assign $0\fast_o[2:0] $1\fast_o[2:0] - attribute \src "libresoc.v:46912.5-46912.29" + assign $0\dec2_cur_msr$next[63:0]$13393 $3\dec2_cur_msr$next[63:0]$13396 + attribute \src "libresoc.v:185749.5-185749.29" switch \initial - attribute \src "libresoc.v:46912.9-46912.17" + attribute \src "libresoc.v:185749.9-185749.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" - switch \spr_i - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000001 - assign { } { } - assign $1\fast_o[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001000 - assign { } { } - assign $1\fast_o[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001001 - assign { } { } - assign $1\fast_o[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010110 - assign { } { } - assign $1\fast_o[2:0] 3'110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011010 - assign { } { } - assign $1\fast_o[2:0] 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state attribute \src "libresoc.v:0.0-0.0" - case 10'0000011011 + case 2'01 assign { } { } - assign $1\fast_o[2:0] 3'100 + assign $1\dec2_cur_msr$next[63:0]$13394 $2\dec2_cur_msr$next[63:0]$13395 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275" + switch \$117 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dec2_cur_msr$next[63:0]$13395 \core_msr__data_o + case + assign $2\dec2_cur_msr$next[63:0]$13395 \dec2_cur_msr + end + case + assign $1\dec2_cur_msr$next[63:0]$13394 \dec2_cur_msr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" - case 10'0100001100 + case 1'1 assign { } { } - assign $1\fast_o[2:0] 3'111 + assign $3\dec2_cur_msr$next[63:0]$13396 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dec2_cur_msr$next[63:0]$13396 $1\dec2_cur_msr$next[63:0]$13394 + end + sync always + update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$13393 + end + attribute \src "libresoc.v:185769.3-185787.6" + process $proc$libresoc.v:185769$13397 + assign { } { } + assign { } { } + assign $0\dec2_raw_opcode_in[31:0] $1\dec2_raw_opcode_in[31:0] + attribute \src "libresoc.v:185770.5-185770.29" + switch \initial + attribute \src "libresoc.v:185770.9-185770.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state attribute \src "libresoc.v:0.0-0.0" - case 10'1100101111 + case 2'01 assign { } { } - assign $1\fast_o[2:0] 3'010 + assign $1\dec2_raw_opcode_in[31:0] $2\dec2_raw_opcode_in[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\dec2_raw_opcode_in[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dec2_raw_opcode_in[31:0] \$119 + end case - assign $1\fast_o[2:0] 3'000 + assign $1\dec2_raw_opcode_in[31:0] 0 end sync always - update \fast_o $0\fast_o[2:0] + update \dec2_raw_opcode_in $0\dec2_raw_opcode_in[31:0] end - attribute \src "libresoc.v:46942.3-46972.6" - process $proc$libresoc.v:46942$1602 + attribute \src "libresoc.v:185788.3-185819.6" + process $proc$libresoc.v:185788$13398 + assign { } { } + assign { } { } + assign { } { } assign { } { } assign { } { } - assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] - attribute \src "libresoc.v:46943.5-46943.29" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\core_core_pc$next[63:0]$13399 $3\core_core_pc$next[63:0]$13411 + assign $0\core_dec$next[63:0]$13400 $3\core_dec$next[63:0]$13412 + assign $0\core_eint$next[0:0]$13401 $3\core_eint$next[0:0]$13413 + assign $0\core_msr$next[63:0]$13402 $3\core_msr$next[63:0]$13414 + attribute \src "libresoc.v:185789.5-185789.29" switch \initial - attribute \src "libresoc.v:46943.9-46943.17" + attribute \src "libresoc.v:185789.9-185789.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" - switch \spr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state attribute \src "libresoc.v:0.0-0.0" - case 10'0000000001 + case 2'01 assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001000 assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001001 assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010110 assign { } { } - assign $1\fast_o_ok[0:0] 1'1 + assign $1\core_core_pc$next[63:0]$13403 $2\core_core_pc$next[63:0]$13407 + assign $1\core_dec$next[63:0]$13404 $2\core_dec$next[63:0]$13408 + assign $1\core_eint$next[0:0]$13405 $2\core_eint$next[0:0]$13409 + assign $1\core_msr$next[63:0]$13406 $2\core_msr$next[63:0]$13410 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\core_core_pc$next[63:0]$13407 \core_core_pc + assign $2\core_dec$next[63:0]$13408 \core_dec + assign $2\core_eint$next[0:0]$13409 \core_eint + assign $2\core_msr$next[63:0]$13410 \core_msr + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\core_dec$next[63:0]$13408 $2\core_eint$next[0:0]$13409 $2\core_msr$next[63:0]$13410 $2\core_core_pc$next[63:0]$13407 } { \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } + end + case + assign $1\core_core_pc$next[63:0]$13403 \core_core_pc + assign $1\core_dec$next[63:0]$13404 \core_dec + assign $1\core_eint$next[0:0]$13405 \core_eint + assign $1\core_msr$next[63:0]$13406 \core_msr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" - case 10'0000011010 + case 1'1 assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011011 assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100001100 assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101111 assign { } { } - assign $1\fast_o_ok[0:0] 1'1 + assign $3\core_core_pc$next[63:0]$13411 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_msr$next[63:0]$13414 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_eint$next[0:0]$13413 1'0 + assign $3\core_dec$next[63:0]$13412 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $1\fast_o_ok[0:0] 1'0 + assign $3\core_core_pc$next[63:0]$13411 $1\core_core_pc$next[63:0]$13403 + assign $3\core_dec$next[63:0]$13412 $1\core_dec$next[63:0]$13404 + assign $3\core_eint$next[0:0]$13413 $1\core_eint$next[0:0]$13405 + assign $3\core_msr$next[63:0]$13414 $1\core_msr$next[63:0]$13406 end sync always - update \fast_o_ok $0\fast_o_ok[0:0] + update \core_core_pc$next $0\core_core_pc$next[63:0]$13399 + update \core_dec$next $0\core_dec$next[63:0]$13400 + update \core_eint$next $0\core_eint$next[0:0]$13401 + update \core_msr$next $0\core_msr$next[63:0]$13402 end - attribute \src "libresoc.v:46973.3-47285.6" - process $proc$libresoc.v:46973$1603 + attribute \src "libresoc.v:185820.3-185843.6" + process $proc$libresoc.v:185820$13415 assign { } { } assign { } { } - assign $0\spr_o[9:0] $1\spr_o[9:0] - attribute \src "libresoc.v:46974.5-46974.29" + assign { } { } + assign $0\ilatch$next[31:0]$13416 $3\ilatch$next[31:0]$13419 + attribute \src "libresoc.v:185821.5-185821.29" switch \initial - attribute \src "libresoc.v:46974.9-46974.17" + attribute \src "libresoc.v:185821.9-185821.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" - switch \spr_i - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000011 - assign { } { } - assign $1\spr_o[9:0] 10'0000000001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001101 - assign { } { } - assign $1\spr_o[9:0] 10'0000000100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010001 - assign { } { } - assign $1\spr_o[9:0] 10'0000000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\spr_o[9:0] 10'0000000110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010011 - assign { } { } - assign $1\spr_o[9:0] 10'0000000111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011100 - assign { } { } - assign $1\spr_o[9:0] 10'0000001011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011101 - assign { } { } - assign $1\spr_o[9:0] 10'0000001100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000110000 - assign { } { } - assign $1\spr_o[9:0] 10'0000001101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000111101 - assign { } { } - assign $1\spr_o[9:0] 10'0000001110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000000 - assign { } { } - assign $1\spr_o[9:0] 10'0000001111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\spr_o[9:0] 10'0000010000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000010 - assign { } { } - assign $1\spr_o[9:0] 10'0000010001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000011 - assign { } { } - assign $1\spr_o[9:0] 10'0000010010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010001000 - assign { } { } - assign $1\spr_o[9:0] 10'0000010011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010000 - assign { } { } - assign $1\spr_o[9:0] 10'0000010100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011000 - assign { } { } - assign $1\spr_o[9:0] 10'0000010101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011001 - assign { } { } - assign $1\spr_o[9:0] 10'0000010110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011101 - assign { } { } - assign $1\spr_o[9:0] 10'0000010111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011110 - assign { } { } - assign $1\spr_o[9:0] 10'0000011000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011111 - assign { } { } - assign $1\spr_o[9:0] 10'0000011001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010110000 - assign { } { } - assign $1\spr_o[9:0] 10'0000011010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010110100 - assign { } { } - assign $1\spr_o[9:0] 10'0000011011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111010 - assign { } { } - assign $1\spr_o[9:0] 10'0000011100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111011 - assign { } { } - assign $1\spr_o[9:0] 10'0000011101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111100 - assign { } { } - assign $1\spr_o[9:0] 10'0000011110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111110 - assign { } { } - assign $1\spr_o[9:0] 10'0000011111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000000 - assign { } { } - assign $1\spr_o[9:0] 10'0000100000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000011 - assign { } { } - assign $1\spr_o[9:0] 10'0000100001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100001101 - assign { } { } - assign $1\spr_o[9:0] 10'0000100011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010000 - assign { } { } - assign $1\spr_o[9:0] 10'0000100100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010001 - assign { } { } - assign $1\spr_o[9:0] 10'0000100101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\spr_o[9:0] 10'0000100110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010011 - assign { } { } - assign $1\spr_o[9:0] 10'0000100111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011011 - assign { } { } - assign $1\spr_o[9:0] 10'0000101000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011100 - assign { } { } - assign $1\spr_o[9:0] 10'0000101001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011101 - assign { } { } - assign $1\spr_o[9:0] 10'0000101010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011110 - assign { } { } - assign $1\spr_o[9:0] 10'0000101011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011111 - assign { } { } - assign $1\spr_o[9:0] 10'0000101100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110000 - assign { } { } - assign $1\spr_o[9:0] 10'0000101101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110001 - assign { } { } - assign $1\spr_o[9:0] 10'0000101110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110010 - assign { } { } - assign $1\spr_o[9:0] 10'0000101111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110011 - assign { } { } - assign $1\spr_o[9:0] 10'0000110000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110100 - assign { } { } - assign $1\spr_o[9:0] 10'0000110001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110101 - assign { } { } - assign $1\spr_o[9:0] 10'0000110010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110110 - assign { } { } - assign $1\spr_o[9:0] 10'0000110011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111001 - assign { } { } - assign $1\spr_o[9:0] 10'0000110100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111010 - assign { } { } - assign $1\spr_o[9:0] 10'0000110101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111011 - assign { } { } - assign $1\spr_o[9:0] 10'0000110110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111110 - assign { } { } - assign $1\spr_o[9:0] 10'0000110111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111111 - assign { } { } - assign $1\spr_o[9:0] 10'0000111000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010000 - assign { } { } - assign $1\spr_o[9:0] 10'0000111001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010001 - assign { } { } - assign $1\spr_o[9:0] 10'0000111010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010010 - assign { } { } - assign $1\spr_o[9:0] 10'0000111011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010011 - assign { } { } - assign $1\spr_o[9:0] 10'0000111100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101011101 - assign { } { } - assign $1\spr_o[9:0] 10'0000111101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110111110 - assign { } { } - assign $1\spr_o[9:0] 10'0000111110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111010000 - assign { } { } - assign $1\spr_o[9:0] 10'0000111111 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000000 - assign { } { } - assign $1\spr_o[9:0] 10'0001000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000001 - assign { } { } - assign $1\spr_o[9:0] 10'0001000001 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000010 - assign { } { } - assign $1\spr_o[9:0] 10'0001000010 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000011 - assign { } { } - assign $1\spr_o[9:0] 10'0001000011 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000100 - assign { } { } - assign $1\spr_o[9:0] 10'0001000100 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000101 - assign { } { } - assign $1\spr_o[9:0] 10'0001000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000110 - assign { } { } - assign $1\spr_o[9:0] 10'0001000110 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000111 - assign { } { } - assign $1\spr_o[9:0] 10'0001000111 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001000 - assign { } { } - assign $1\spr_o[9:0] 10'0001001000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001011 - assign { } { } - assign $1\spr_o[9:0] 10'0001001001 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001100 - assign { } { } - assign $1\spr_o[9:0] 10'0001001010 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001101 - assign { } { } - assign $1\spr_o[9:0] 10'0001001011 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001110 - assign { } { } - assign $1\spr_o[9:0] 10'0001001100 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010000 - assign { } { } - assign $1\spr_o[9:0] 10'0001001101 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010001 - assign { } { } - assign $1\spr_o[9:0] 10'0001001110 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010010 - assign { } { } - assign $1\spr_o[9:0] 10'0001001111 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010011 - assign { } { } - assign $1\spr_o[9:0] 10'0001010000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010100 - assign { } { } - assign $1\spr_o[9:0] 10'0001010001 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010101 - assign { } { } - assign $1\spr_o[9:0] 10'0001010010 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010110 - assign { } { } - assign $1\spr_o[9:0] 10'0001010011 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010111 - assign { } { } - assign $1\spr_o[9:0] 10'0001010100 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011000 - assign { } { } - assign $1\spr_o[9:0] 10'0001010101 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011011 - assign { } { } - assign $1\spr_o[9:0] 10'0001010110 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011100 - assign { } { } - assign $1\spr_o[9:0] 10'0001010111 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011101 - assign { } { } - assign $1\spr_o[9:0] 10'0001011000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011110 - assign { } { } - assign $1\spr_o[9:0] 10'0001011001 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100000 - assign { } { } - assign $1\spr_o[9:0] 10'0001011010 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100001 - assign { } { } - assign $1\spr_o[9:0] 10'0001011011 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100010 - assign { } { } - assign $1\spr_o[9:0] 10'0001011100 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100011 - assign { } { } - assign $1\spr_o[9:0] 10'0001011101 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100100 - assign { } { } - assign $1\spr_o[9:0] 10'0001011110 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100101 - assign { } { } - assign $1\spr_o[9:0] 10'0001011111 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100110 - assign { } { } - assign $1\spr_o[9:0] 10'0001100000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101000 - assign { } { } - assign $1\spr_o[9:0] 10'0001100001 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101001 - assign { } { } - assign $1\spr_o[9:0] 10'0001100010 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101010 - assign { } { } - assign $1\spr_o[9:0] 10'0001100011 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101011 - assign { } { } - assign $1\spr_o[9:0] 10'0001100100 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100110000 - assign { } { } - assign $1\spr_o[9:0] 10'0001100110 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100110111 - assign { } { } - assign $1\spr_o[9:0] 10'0001100111 - attribute \src "libresoc.v:0.0-0.0" - case 10'1101010000 - assign { } { } - assign $1\spr_o[9:0] 10'0001101000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1101010001 - assign { } { } - assign $1\spr_o[9:0] 10'0001101001 - attribute \src "libresoc.v:0.0-0.0" - case 10'1101010111 - assign { } { } - assign $1\spr_o[9:0] 10'0001101010 - attribute \src "libresoc.v:0.0-0.0" - case 10'1110000000 - assign { } { } - assign $1\spr_o[9:0] 10'0001101011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state attribute \src "libresoc.v:0.0-0.0" - case 10'1110000010 + case 2'01 assign { } { } - assign $1\spr_o[9:0] 10'0001101100 + assign $1\ilatch$next[31:0]$13417 $2\ilatch$next[31:0]$13418 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\ilatch$next[31:0]$13418 \ilatch + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\ilatch$next[31:0]$13418 \$123 + end + case + assign $1\ilatch$next[31:0]$13417 \ilatch + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" - case 10'1111111111 + case 1'1 assign { } { } - assign $1\spr_o[9:0] 10'0001101101 + assign $3\ilatch$next[31:0]$13419 0 case - assign $1\spr_o[9:0] 10'0000000000 + assign $3\ilatch$next[31:0]$13419 $1\ilatch$next[31:0]$13417 end sync always - update \spr_o $0\spr_o[9:0] + update \ilatch$next $0\ilatch$next[31:0]$13416 end - attribute \src "libresoc.v:47286.3-47598.6" - process $proc$libresoc.v:47286$1604 + attribute \src "libresoc.v:185844.3-185863.6" + process $proc$libresoc.v:185844$13420 assign { } { } assign { } { } - assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "libresoc.v:47287.5-47287.29" + assign $0\core_ivalid_i[0:0] $1\core_ivalid_i[0:0] + attribute \src "libresoc.v:185845.5-185845.29" switch \initial - attribute \src "libresoc.v:47287.9-47287.17" + attribute \src "libresoc.v:185845.9-185845.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" - switch \spr_i - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000110000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000111101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010001000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010110000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010110100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100001101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101011101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110111110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state attribute \src "libresoc.v:0.0-0.0" - case 10'1100000010 + case 2'10 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\core_ivalid_i[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000011 + case 2'11 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\core_ivalid_i[0:0] $2\core_ivalid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:307" + switch \$127 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\core_ivalid_i[0:0] 1'1 + case + assign $2\core_ivalid_i[0:0] 1'0 + end + case + assign $1\core_ivalid_i[0:0] 1'0 + end + sync always + update \core_ivalid_i $0\core_ivalid_i[0:0] + end + attribute \src "libresoc.v:185864.3-185874.6" + process $proc$libresoc.v:185864$13421 + assign { } { } + assign { } { } + assign $0\core_issue_i[0:0] $1\core_issue_i[0:0] + attribute \src "libresoc.v:185865.5-185865.29" + switch \initial + attribute \src "libresoc.v:185865.9-185865.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state attribute \src "libresoc.v:0.0-0.0" - case 10'1100000100 + case 2'10 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\core_issue_i[0:0] 1'1 + case + assign $1\core_issue_i[0:0] 1'0 + end + sync always + update \core_issue_i $0\core_issue_i[0:0] + end + attribute \src "libresoc.v:185875.3-185884.6" + process $proc$libresoc.v:185875$13422 + assign { } { } + assign { } { } + assign $0\core_dmi__addr[4:0] $1\core_dmi__addr[4:0] + attribute \src "libresoc.v:185876.5-185876.29" + switch \initial + attribute \src "libresoc.v:185876.9-185876.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325" + switch \dbg_d_gpr_req attribute \src "libresoc.v:0.0-0.0" - case 10'1100000101 + case 1'1 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\core_dmi__addr[4:0] \dbg_d_gpr_addr [4:0] + case + assign $1\core_dmi__addr[4:0] 5'00000 + end + sync always + update \core_dmi__addr $0\core_dmi__addr[4:0] + end + attribute \src "libresoc.v:185885.3-185894.6" + process $proc$libresoc.v:185885$13423 + assign { } { } + assign { } { } + assign $0\core_dmi__ren[0:0] $1\core_dmi__ren[0:0] + attribute \src "libresoc.v:185886.5-185886.29" + switch \initial + attribute \src "libresoc.v:185886.9-185886.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325" + switch \dbg_d_gpr_req attribute \src "libresoc.v:0.0-0.0" - case 10'1100000110 + case 1'1 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\core_dmi__ren[0:0] 1'1 + case + assign $1\core_dmi__ren[0:0] 1'0 + end + sync always + update \core_dmi__ren $0\core_dmi__ren[0:0] + end + attribute \src "libresoc.v:185895.3-185903.6" + process $proc$libresoc.v:185895$13424 + assign { } { } + assign { } { } + assign $0\d_reg_delay$next[0:0]$13425 $1\d_reg_delay$next[0:0]$13426 + attribute \src "libresoc.v:185896.5-185896.29" + switch \initial + attribute \src "libresoc.v:185896.9-185896.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" - case 10'1100000111 + case 1'1 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\d_reg_delay$next[0:0]$13426 1'0 + case + assign $1\d_reg_delay$next[0:0]$13426 \dbg_d_gpr_req + end + sync always + update \d_reg_delay$next $0\d_reg_delay$next[0:0]$13425 + end + attribute \src "libresoc.v:185904.3-185913.6" + process $proc$libresoc.v:185904$13427 + assign { } { } + assign { } { } + assign $0\dbg_d_gpr_data[63:0] $1\dbg_d_gpr_data[63:0] + attribute \src "libresoc.v:185905.5-185905.29" + switch \initial + attribute \src "libresoc.v:185905.9-185905.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:335" + switch \d_reg_delay attribute \src "libresoc.v:0.0-0.0" - case 10'1100001000 + case 1'1 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dbg_d_gpr_data[63:0] \core_dmi__data_o + case + assign $1\dbg_d_gpr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dbg_d_gpr_data $0\dbg_d_gpr_data[63:0] + end + attribute \src "libresoc.v:185914.3-185923.6" + process $proc$libresoc.v:185914$13428 + assign { } { } + assign { } { } + assign $0\dbg_d_gpr_ack[0:0] $1\dbg_d_gpr_ack[0:0] + attribute \src "libresoc.v:185915.5-185915.29" + switch \initial + attribute \src "libresoc.v:185915.9-185915.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:335" + switch \d_reg_delay attribute \src "libresoc.v:0.0-0.0" - case 10'1100001011 + case 1'1 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dbg_d_gpr_ack[0:0] 1'1 + case + assign $1\dbg_d_gpr_ack[0:0] 1'0 + end + sync always + update \dbg_d_gpr_ack $0\dbg_d_gpr_ack[0:0] + end + attribute \src "libresoc.v:185924.3-185933.6" + process $proc$libresoc.v:185924$13429 + assign { } { } + assign { } { } + assign $0\core_full_rd2__ren[7:0] $1\core_full_rd2__ren[7:0] + attribute \src "libresoc.v:185925.5-185925.29" + switch \initial + attribute \src "libresoc.v:185925.9-185925.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:341" + switch \dbg_d_cr_req attribute \src "libresoc.v:0.0-0.0" - case 10'1100001100 + case 1'1 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\core_full_rd2__ren[7:0] 8'11111111 + case + assign $1\core_full_rd2__ren[7:0] 8'00000000 + end + sync always + update \core_full_rd2__ren $0\core_full_rd2__ren[7:0] + end + attribute \src "libresoc.v:185934.3-185942.6" + process $proc$libresoc.v:185934$13430 + assign { } { } + assign { } { } + assign $0\d_cr_delay$next[0:0]$13431 $1\d_cr_delay$next[0:0]$13432 + attribute \src "libresoc.v:185935.5-185935.29" + switch \initial + attribute \src "libresoc.v:185935.9-185935.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" - case 10'1100001101 + case 1'1 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\d_cr_delay$next[0:0]$13432 1'0 + case + assign $1\d_cr_delay$next[0:0]$13432 \dbg_d_cr_req + end + sync always + update \d_cr_delay$next $0\d_cr_delay$next[0:0]$13431 + end + attribute \src "libresoc.v:185943.3-185952.6" + process $proc$libresoc.v:185943$13433 + assign { } { } + assign { } { } + assign $0\dbg_d_cr_data[63:0] $1\dbg_d_cr_data[63:0] + attribute \src "libresoc.v:185944.5-185944.29" + switch \initial + attribute \src "libresoc.v:185944.9-185944.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:345" + switch \d_cr_delay attribute \src "libresoc.v:0.0-0.0" - case 10'1100001110 + case 1'1 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dbg_d_cr_data[63:0] \$129 + case + assign $1\dbg_d_cr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dbg_d_cr_data $0\dbg_d_cr_data[63:0] + end + attribute \src "libresoc.v:185953.3-185962.6" + process $proc$libresoc.v:185953$13434 + assign { } { } + assign { } { } + assign $0\dbg_d_cr_ack[0:0] $1\dbg_d_cr_ack[0:0] + attribute \src "libresoc.v:185954.5-185954.29" + switch \initial + attribute \src "libresoc.v:185954.9-185954.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:345" + switch \d_cr_delay attribute \src "libresoc.v:0.0-0.0" - case 10'1100010000 + case 1'1 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dbg_d_cr_ack[0:0] 1'1 + case + assign $1\dbg_d_cr_ack[0:0] 1'0 + end + sync always + update \dbg_d_cr_ack $0\dbg_d_cr_ack[0:0] + end + attribute \src "libresoc.v:185963.3-185972.6" + process $proc$libresoc.v:185963$13435 + assign { } { } + assign { } { } + assign $0\core_full_rd__ren[2:0] $1\core_full_rd__ren[2:0] + attribute \src "libresoc.v:185964.5-185964.29" + switch \initial + attribute \src "libresoc.v:185964.9-185964.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351" + switch \dbg_d_xer_req attribute \src "libresoc.v:0.0-0.0" - case 10'1100010001 + case 1'1 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\core_full_rd__ren[2:0] 3'111 + case + assign $1\core_full_rd__ren[2:0] 3'000 + end + sync always + update \core_full_rd__ren $0\core_full_rd__ren[2:0] + end + attribute \src "libresoc.v:185973.3-185981.6" + process $proc$libresoc.v:185973$13436 + assign { } { } + assign { } { } + assign $0\d_xer_delay$next[0:0]$13437 $1\d_xer_delay$next[0:0]$13438 + attribute \src "libresoc.v:185974.5-185974.29" + switch \initial + attribute \src "libresoc.v:185974.9-185974.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" - case 10'1100010010 + case 1'1 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\d_xer_delay$next[0:0]$13438 1'0 + case + assign $1\d_xer_delay$next[0:0]$13438 \dbg_d_xer_req + end + sync always + update \d_xer_delay$next $0\d_xer_delay$next[0:0]$13437 + end + attribute \src "libresoc.v:185982.3-185991.6" + process $proc$libresoc.v:185982$13439 + assign { } { } + assign { } { } + assign $0\dbg_d_xer_data[63:0] $1\dbg_d_xer_data[63:0] + attribute \src "libresoc.v:185983.5-185983.29" + switch \initial + attribute \src "libresoc.v:185983.9-185983.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:355" + switch \d_xer_delay attribute \src "libresoc.v:0.0-0.0" - case 10'1100010011 + case 1'1 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dbg_d_xer_data[63:0] \$131 + case + assign $1\dbg_d_xer_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dbg_d_xer_data $0\dbg_d_xer_data[63:0] + end + attribute \src "libresoc.v:185992.3-186001.6" + process $proc$libresoc.v:185992$13440 + assign { } { } + assign { } { } + assign $0\dbg_d_xer_ack[0:0] $1\dbg_d_xer_ack[0:0] + attribute \src "libresoc.v:185993.5-185993.29" + switch \initial + attribute \src "libresoc.v:185993.9-185993.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:355" + switch \d_xer_delay attribute \src "libresoc.v:0.0-0.0" - case 10'1100010100 + case 1'1 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dbg_d_xer_ack[0:0] 1'1 + case + assign $1\dbg_d_xer_ack[0:0] 1'0 + end + sync always + update \dbg_d_xer_ack $0\dbg_d_xer_ack[0:0] + end + attribute \src "libresoc.v:186002.3-186016.6" + process $proc$libresoc.v:186002$13441 + assign { } { } + assign { } { } + assign $0\core_issue__addr[2:0] $1\core_issue__addr[2:0] + attribute \src "libresoc.v:186003.5-186003.29" + switch \initial + attribute \src "libresoc.v:186003.9-186003.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" + switch \fsm_state$133 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010101 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\core_issue__addr[2:0] 3'110 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010110 + case 2'10 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\core_issue__addr[2:0] 3'111 + case + assign $1\core_issue__addr[2:0] 3'000 + end + sync always + update \core_issue__addr $0\core_issue__addr[2:0] + end + attribute \src "libresoc.v:186017.3-186031.6" + process $proc$libresoc.v:186017$13442 + assign { } { } + assign { } { } + assign $0\core_issue__ren[0:0] $1\core_issue__ren[0:0] + attribute \src "libresoc.v:186018.5-186018.29" + switch \initial + attribute \src "libresoc.v:186018.9-186018.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" + switch \fsm_state$133 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010111 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\core_issue__ren[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 10'1100011000 + case 2'10 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\core_issue__ren[0:0] 1'1 + case + assign $1\core_issue__ren[0:0] 1'0 + end + sync always + update \core_issue__ren $0\core_issue__ren[0:0] + end + attribute \src "libresoc.v:186032.3-186059.6" + process $proc$libresoc.v:186032$13443 + assign { } { } + assign { } { } + assign { } { } + assign $0\fsm_state$133$next[1:0]$13444 $2\fsm_state$133$next[1:0]$13446 + attribute \src "libresoc.v:186033.5-186033.29" + switch \initial + attribute \src "libresoc.v:186033.9-186033.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" + switch \fsm_state$133 attribute \src "libresoc.v:0.0-0.0" - case 10'1100011011 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\fsm_state$133$next[1:0]$13445 2'01 attribute \src "libresoc.v:0.0-0.0" - case 10'1100011100 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\fsm_state$133$next[1:0]$13445 2'10 attribute \src "libresoc.v:0.0-0.0" - case 10'1100011101 + case 2'10 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\fsm_state$133$next[1:0]$13445 2'11 attribute \src "libresoc.v:0.0-0.0" - case 10'1100011110 + case 2'11 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\fsm_state$133$next[1:0]$13445 2'00 + case + assign $1\fsm_state$133$next[1:0]$13445 \fsm_state$133 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" - case 10'1100100000 + case 1'1 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $2\fsm_state$133$next[1:0]$13446 2'00 + case + assign $2\fsm_state$133$next[1:0]$13446 $1\fsm_state$133$next[1:0]$13445 + end + sync always + update \fsm_state$133$next $0\fsm_state$133$next[1:0]$13444 + end + attribute \src "libresoc.v:186060.3-186070.6" + process $proc$libresoc.v:186060$13447 + assign { } { } + assign { } { } + assign $0\new_dec[63:0] $1\new_dec[63:0] + attribute \src "libresoc.v:186061.5-186061.29" + switch \initial + attribute \src "libresoc.v:186061.9-186061.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" + switch \fsm_state$133 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100001 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\new_dec[63:0] \$134 [63:0] + case + assign $1\new_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \new_dec $0\new_dec[63:0] + end + attribute \src "libresoc.v:186071.3-186085.6" + process $proc$libresoc.v:186071$13448 + assign { } { } + assign { } { } + assign $0\core_issue__addr$11[2:0]$13449 $1\core_issue__addr$11[2:0]$13450 + attribute \src "libresoc.v:186072.5-186072.29" + switch \initial + attribute \src "libresoc.v:186072.9-186072.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" + switch \fsm_state$133 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100010 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\core_issue__addr$11[2:0]$13450 3'110 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100011 + case 2'11 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\core_issue__addr$11[2:0]$13450 3'111 + case + assign $1\core_issue__addr$11[2:0]$13450 3'000 + end + sync always + update \core_issue__addr$11 $0\core_issue__addr$11[2:0]$13449 + end + attribute \src "libresoc.v:186086.3-186100.6" + process $proc$libresoc.v:186086$13451 + assign { } { } + assign { } { } + assign $0\core_issue__wen[0:0] $1\core_issue__wen[0:0] + attribute \src "libresoc.v:186087.5-186087.29" + switch \initial + attribute \src "libresoc.v:186087.9-186087.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" + switch \fsm_state$133 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100100 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\core_issue__wen[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100101 + case 2'11 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\core_issue__wen[0:0] 1'1 + case + assign $1\core_issue__wen[0:0] 1'0 + end + sync always + update \core_issue__wen $0\core_issue__wen[0:0] + end + attribute \src "libresoc.v:186101.3-186115.6" + process $proc$libresoc.v:186101$13452 + assign { } { } + assign { } { } + assign $0\core_issue__data_i[63:0] $1\core_issue__data_i[63:0] + attribute \src "libresoc.v:186102.5-186102.29" + switch \initial + attribute \src "libresoc.v:186102.9-186102.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" + switch \fsm_state$133 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100110 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\core_issue__data_i[63:0] \new_dec attribute \src "libresoc.v:0.0-0.0" - case 10'1100101000 + case 2'11 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\core_issue__data_i[63:0] \new_tb + case + assign $1\core_issue__data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \core_issue__data_i $0\core_issue__data_i[63:0] + end + attribute \src "libresoc.v:186116.3-186131.6" + process $proc$libresoc.v:186116$13453 + assign { } { } + assign { } { } + assign { } { } + assign $0\dec2_cur_dec$next[63:0]$13454 $2\dec2_cur_dec$next[63:0]$13456 + attribute \src "libresoc.v:186117.5-186117.29" + switch \initial + attribute \src "libresoc.v:186117.9-186117.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" + switch \fsm_state$133 attribute \src "libresoc.v:0.0-0.0" - case 10'1100101001 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec2_cur_dec$next[63:0]$13455 \new_dec + case + assign $1\dec2_cur_dec$next[63:0]$13455 \dec2_cur_dec + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" - case 10'1100101010 + case 1'1 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $2\dec2_cur_dec$next[63:0]$13456 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\dec2_cur_dec$next[63:0]$13456 $1\dec2_cur_dec$next[63:0]$13455 + end + sync always + update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$13454 + end + attribute \src "libresoc.v:186132.3-186142.6" + process $proc$libresoc.v:186132$13457 + assign { } { } + assign { } { } + assign $0\new_tb[63:0] $1\new_tb[63:0] + attribute \src "libresoc.v:186133.5-186133.29" + switch \initial + attribute \src "libresoc.v:186133.9-186133.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" + switch \fsm_state$133 attribute \src "libresoc.v:0.0-0.0" - case 10'1100101011 + case 2'11 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\new_tb[63:0] \$137 [63:0] + case + assign $1\new_tb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \new_tb $0\new_tb[63:0] + end + attribute \src "libresoc.v:186143.3-186151.6" + process $proc$libresoc.v:186143$13458 + assign { } { } + assign { } { } + assign $0\dbg_dmi_we_i$next[0:0]$13459 $1\dbg_dmi_we_i$next[0:0]$13460 + attribute \src "libresoc.v:186144.5-186144.29" + switch \initial + attribute \src "libresoc.v:186144.9-186144.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" - case 10'1100110000 + case 1'1 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dbg_dmi_we_i$next[0:0]$13460 1'0 + case + assign $1\dbg_dmi_we_i$next[0:0]$13460 \jtag_dmi0__we_i + end + sync always + update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$13459 + end + attribute \src "libresoc.v:186152.3-186160.6" + process $proc$libresoc.v:186152$13461 + assign { } { } + assign { } { } + assign $0\pc_ok_delay$next[0:0]$13462 $1\pc_ok_delay$next[0:0]$13463 + attribute \src "libresoc.v:186153.5-186153.29" + switch \initial + attribute \src "libresoc.v:186153.9-186153.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" - case 10'1100110111 + case 1'1 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\pc_ok_delay$next[0:0]$13463 1'0 + case + assign $1\pc_ok_delay$next[0:0]$13463 \$39 + end + sync always + update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$13462 + end + attribute \src "libresoc.v:186161.3-186176.6" + process $proc$libresoc.v:186161$13464 + assign { } { } + assign { } { } + assign { } { } + assign $0\pc[63:0] $2\pc[63:0] + attribute \src "libresoc.v:186162.5-186162.29" + switch \initial + attribute \src "libresoc.v:186162.9-186162.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:207" + switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" - case 10'1101010000 + case 1'1 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\pc[63:0] \pc_i + case + assign $1\pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + switch \pc_ok_delay attribute \src "libresoc.v:0.0-0.0" - case 10'1101010001 + case 1'1 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $2\pc[63:0] \core_cia__data_o + case + assign $2\pc[63:0] $1\pc[63:0] + end + sync always + update \pc $0\pc[63:0] + end + attribute \src "libresoc.v:186177.3-186189.6" + process $proc$libresoc.v:186177$13465 + assign { } { } + assign { } { } + assign $0\core_cia__ren[3:0] $1\core_cia__ren[3:0] + attribute \src "libresoc.v:186178.5-186178.29" + switch \initial + attribute \src "libresoc.v:186178.9-186178.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:207" + switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" - case 10'1101010111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + case 1'1 + assign $1\core_cia__ren[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 10'1110000000 + case assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\core_cia__ren[3:0] 4'0001 + end + sync always + update \core_cia__ren $0\core_cia__ren[3:0] + end + attribute \src "libresoc.v:186190.3-186210.6" + process $proc$libresoc.v:186190$13466 + assign { } { } + assign { } { } + assign $0\core_wen[3:0] $1\core_wen[3:0] + attribute \src "libresoc.v:186191.5-186191.29" + switch \initial + attribute \src "libresoc.v:186191.9-186191.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state attribute \src "libresoc.v:0.0-0.0" - case 10'1110000010 + case 2'11 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\core_wen[3:0] $2\core_wen[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + switch \$41 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\core_wen[3:0] $3\core_wen[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + switch \$43 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_wen[3:0] 4'0001 + case + assign $3\core_wen[3:0] 4'0000 + end + case + assign $2\core_wen[3:0] 4'0000 + end + case + assign $1\core_wen[3:0] 4'0000 + end + sync always + update \core_wen $0\core_wen[3:0] + end + attribute \src "libresoc.v:186211.3-186231.6" + process $proc$libresoc.v:186211$13467 + assign { } { } + assign { } { } + assign $0\core_data_i[63:0] $1\core_data_i[63:0] + attribute \src "libresoc.v:186212.5-186212.29" + switch \initial + attribute \src "libresoc.v:186212.9-186212.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state attribute \src "libresoc.v:0.0-0.0" - case 10'1111111111 + case 2'11 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\core_data_i[63:0] $2\core_data_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + switch \$45 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\core_data_i[63:0] $3\core_data_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + switch \$47 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_data_i[63:0] \nia + case + assign $3\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $2\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end case - assign $1\spr_o_ok[0:0] 1'0 + assign $1\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \spr_o_ok $0\spr_o_ok[0:0] + update \core_data_i $0\core_data_i[63:0] end -end -attribute \src "libresoc.v:47604.1-48728.10" -attribute \cells_not_processed 1 -attribute \top 1 -attribute \nmigen.hierarchy "test_issuer" -attribute \generator "nMigen" -module \test_issuer - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 9 \TAP_bus__tck - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 7 \TAP_bus__tdi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire output 6 \TAP_bus__tdo - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 8 \TAP_bus__tms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:105" - wire output 5 \busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 368 \clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" - wire width 2 input 370 \clk_sel_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:104" - wire input 4 \core_bigendian_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 344 \dbus__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 45 input 338 \dbus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 2 input 348 \dbus__bte - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 3 input 347 \dbus__cti - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 342 \dbus__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 input 340 \dbus__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 input 339 \dbus__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 346 \dbus__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 8 input 341 \dbus__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 343 \dbus__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 345 \dbus__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 19 \eint_0__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 20 \eint_0__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 21 \eint_1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 22 \eint_1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 23 \eint_2__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 24 \eint_2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 37 \gpio_e10__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 38 \gpio_e10__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 39 \gpio_e10__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 40 \gpio_e10__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 41 \gpio_e10__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 42 \gpio_e10__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 43 \gpio_e11__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 44 \gpio_e11__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 45 \gpio_e11__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 46 \gpio_e11__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 47 \gpio_e11__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 48 \gpio_e11__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 49 \gpio_e12__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 50 \gpio_e12__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 51 \gpio_e12__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 52 \gpio_e12__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 53 \gpio_e12__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 54 \gpio_e12__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 55 \gpio_e13__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 56 \gpio_e13__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 57 \gpio_e13__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 58 \gpio_e13__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 59 \gpio_e13__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 60 \gpio_e13__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 61 \gpio_e14__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 62 \gpio_e14__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 63 \gpio_e14__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 64 \gpio_e14__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 65 \gpio_e14__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 66 \gpio_e14__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 67 \gpio_e15__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 68 \gpio_e15__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 69 \gpio_e15__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 70 \gpio_e15__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 71 \gpio_e15__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 72 \gpio_e15__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 25 \gpio_e8__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 26 \gpio_e8__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 27 \gpio_e8__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 28 \gpio_e8__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 29 \gpio_e8__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 30 \gpio_e8__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 31 \gpio_e9__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 32 \gpio_e9__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 33 \gpio_e9__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 34 \gpio_e9__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 35 \gpio_e9__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 36 \gpio_e9__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 73 \gpio_s0__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 74 \gpio_s0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 75 \gpio_s0__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 76 \gpio_s0__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 77 \gpio_s0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 78 \gpio_s0__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 79 \gpio_s1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 80 \gpio_s1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 81 \gpio_s1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 82 \gpio_s1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 83 \gpio_s1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 84 \gpio_s1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 85 \gpio_s2__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 86 \gpio_s2__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 87 \gpio_s2__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 88 \gpio_s2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 89 \gpio_s2__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 90 \gpio_s2__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 91 \gpio_s3__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 92 \gpio_s3__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 93 \gpio_s3__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 94 \gpio_s3__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 95 \gpio_s3__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 96 \gpio_s3__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 97 \gpio_s4__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 98 \gpio_s4__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 99 \gpio_s4__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 100 \gpio_s4__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 101 \gpio_s4__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 102 \gpio_s4__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 103 \gpio_s5__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 104 \gpio_s5__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 105 \gpio_s5__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 106 \gpio_s5__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 107 \gpio_s5__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 108 \gpio_s5__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 109 \gpio_s6__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 110 \gpio_s6__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 111 \gpio_s6__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 112 \gpio_s6__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 113 \gpio_s6__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 114 \gpio_s6__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 115 \gpio_s7__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 116 \gpio_s7__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 117 \gpio_s7__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 118 \gpio_s7__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 119 \gpio_s7__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 120 \gpio_s7__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 333 \ibus__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 45 output 327 \ibus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 2 input 337 \ibus__bte - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 3 input 336 \ibus__cti - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire output 331 \ibus__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 64 input 329 \ibus__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 64 input 328 \ibus__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 335 \ibus__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 8 output 330 \ibus__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire output 332 \ibus__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 334 \ibus__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire output 355 \icp_wb__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 28 input 349 \icp_wb__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 353 \icp_wb__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 output 351 \icp_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 input 350 \icp_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 357 \icp_wb__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 4 input 352 \icp_wb__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 354 \icp_wb__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 356 \icp_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire output 364 \ics_wb__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 28 input 358 \ics_wb__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 362 \ics_wb__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 output 360 \ics_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 input 359 \ics_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 366 \ics_wb__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 4 input 361 \ics_wb__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 363 \ics_wb__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 365 \ics_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" - wire width 16 input 367 \int_level_i - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire input 17 \jtag_wb__ack - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 29 output 10 \jtag_wb__adr - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 14 \jtag_wb__cyc - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 input 12 \jtag_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 output 11 \jtag_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire input 18 \jtag_wb__err - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 13 \jtag_wb__sel - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 15 \jtag_wb__stb - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 16 \jtag_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:106" - wire input 3 \memerr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 121 \mspi0_clk__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 122 \mspi0_clk__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 123 \mspi0_cs_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 124 \mspi0_cs_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 127 \mspi0_miso__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 128 \mspi0_miso__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 125 \mspi0_mosi__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 126 \mspi0_mosi__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 129 \mspi1_clk__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 130 \mspi1_clk__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 131 \mspi1_cs_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 132 \mspi1_cs_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 135 \mspi1_miso__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 136 \mspi1_miso__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 133 \mspi1_mosi__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 134 \mspi1_mosi__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 143 \mtwi_scl__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 144 \mtwi_scl__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 137 \mtwi_sda__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 138 \mtwi_sda__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 139 \mtwi_sda__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 140 \mtwi_sda__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 141 \mtwi_sda__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 142 \mtwi_sda__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 373 \pc_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 1 \pc_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:102" - wire width 64 output 2 \pc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:467" - wire output 371 \pll_18_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9" - wire \pll_clk_24_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" - wire \pll_clk_pll_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" - wire output 372 \pll_lck_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" - wire \pll_pll_18_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:482" - wire \pllclk_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:482" - wire \pllclk_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 145 \pwm_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 146 \pwm_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 147 \pwm_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 148 \pwm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 369 \rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 155 \sd0_clk__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 156 \sd0_clk__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 149 \sd0_cmd__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 150 \sd0_cmd__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 151 \sd0_cmd__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 152 \sd0_cmd__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 153 \sd0_cmd__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 154 \sd0_cmd__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 157 \sd0_data0__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 158 \sd0_data0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 159 \sd0_data0__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 160 \sd0_data0__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 161 \sd0_data0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 162 \sd0_data0__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 163 \sd0_data1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 164 \sd0_data1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 165 \sd0_data1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 166 \sd0_data1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 167 \sd0_data1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 168 \sd0_data1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 169 \sd0_data2__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 170 \sd0_data2__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 171 \sd0_data2__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 172 \sd0_data2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 173 \sd0_data2__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 174 \sd0_data2__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 175 \sd0_data3__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 176 \sd0_data3__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 177 \sd0_data3__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 178 \sd0_data3__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 179 \sd0_data3__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 180 \sd0_data3__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 231 \sdr_a_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 232 \sdr_a_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 267 \sdr_a_10__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 268 \sdr_a_10__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 269 \sdr_a_11__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 270 \sdr_a_11__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 271 \sdr_a_12__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 272 \sdr_a_12__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 233 \sdr_a_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 234 \sdr_a_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 235 \sdr_a_2__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 236 \sdr_a_2__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 237 \sdr_a_3__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 238 \sdr_a_3__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 239 \sdr_a_4__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 240 \sdr_a_4__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 241 \sdr_a_5__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 242 \sdr_a_5__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 243 \sdr_a_6__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 244 \sdr_a_6__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 245 \sdr_a_7__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 246 \sdr_a_7__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 247 \sdr_a_8__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 248 \sdr_a_8__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 249 \sdr_a_9__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 250 \sdr_a_9__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 251 \sdr_ba_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 252 \sdr_ba_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 253 \sdr_ba_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 254 \sdr_ba_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 261 \sdr_cas_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 262 \sdr_cas_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 257 \sdr_cke__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 258 \sdr_cke__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 255 \sdr_clock__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 256 \sdr_clock__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 265 \sdr_cs_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 266 \sdr_cs_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 181 \sdr_dm_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 182 \sdr_dm_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 273 \sdr_dm_1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 274 \sdr_dm_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 275 \sdr_dm_1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 276 \sdr_dm_1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 277 \sdr_dm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 278 \sdr_dm_1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 183 \sdr_dq_0__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 184 \sdr_dq_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 185 \sdr_dq_0__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 186 \sdr_dq_0__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 187 \sdr_dq_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 188 \sdr_dq_0__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 291 \sdr_dq_10__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 292 \sdr_dq_10__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 293 \sdr_dq_10__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 294 \sdr_dq_10__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 295 \sdr_dq_10__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 296 \sdr_dq_10__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 297 \sdr_dq_11__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 298 \sdr_dq_11__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 299 \sdr_dq_11__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 300 \sdr_dq_11__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 301 \sdr_dq_11__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 302 \sdr_dq_11__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 303 \sdr_dq_12__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 304 \sdr_dq_12__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 305 \sdr_dq_12__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 306 \sdr_dq_12__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 307 \sdr_dq_12__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 308 \sdr_dq_12__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 309 \sdr_dq_13__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 310 \sdr_dq_13__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 311 \sdr_dq_13__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 312 \sdr_dq_13__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 313 \sdr_dq_13__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 314 \sdr_dq_13__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 315 \sdr_dq_14__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 316 \sdr_dq_14__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 317 \sdr_dq_14__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 318 \sdr_dq_14__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 319 \sdr_dq_14__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 320 \sdr_dq_14__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 321 \sdr_dq_15__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 322 \sdr_dq_15__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 323 \sdr_dq_15__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 324 \sdr_dq_15__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 325 \sdr_dq_15__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 326 \sdr_dq_15__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 189 \sdr_dq_1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 190 \sdr_dq_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 191 \sdr_dq_1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 192 \sdr_dq_1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 193 \sdr_dq_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 194 \sdr_dq_1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 195 \sdr_dq_2__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 196 \sdr_dq_2__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 197 \sdr_dq_2__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 198 \sdr_dq_2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 199 \sdr_dq_2__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 200 \sdr_dq_2__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 201 \sdr_dq_3__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 202 \sdr_dq_3__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 203 \sdr_dq_3__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 204 \sdr_dq_3__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 205 \sdr_dq_3__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 206 \sdr_dq_3__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 207 \sdr_dq_4__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 208 \sdr_dq_4__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 209 \sdr_dq_4__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 210 \sdr_dq_4__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 211 \sdr_dq_4__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 212 \sdr_dq_4__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 213 \sdr_dq_5__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 214 \sdr_dq_5__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 215 \sdr_dq_5__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 216 \sdr_dq_5__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 217 \sdr_dq_5__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 218 \sdr_dq_5__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 219 \sdr_dq_6__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 220 \sdr_dq_6__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 221 \sdr_dq_6__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 222 \sdr_dq_6__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 223 \sdr_dq_6__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 224 \sdr_dq_6__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 225 \sdr_dq_7__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 226 \sdr_dq_7__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 227 \sdr_dq_7__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 228 \sdr_dq_7__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 229 \sdr_dq_7__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 230 \sdr_dq_7__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 279 \sdr_dq_8__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 280 \sdr_dq_8__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 281 \sdr_dq_8__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 282 \sdr_dq_8__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 283 \sdr_dq_8__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 284 \sdr_dq_8__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 285 \sdr_dq_9__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 286 \sdr_dq_9__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 287 \sdr_dq_9__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 288 \sdr_dq_9__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 289 \sdr_dq_9__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 290 \sdr_dq_9__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 259 \sdr_ras_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 260 \sdr_ras_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 263 \sdr_we_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 264 \sdr_we_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" - wire \ti_coresync_clk - attribute \module_not_derived 1 - attribute \src "libresoc.v:48363.7-48369.4" - cell \pll \pll - connect \clk_24_i \pll_clk_24_i - connect \clk_pll_o \pll_clk_pll_o - connect \clk_sel_i \clk_sel_i - connect \pll_18_o \pll_pll_18_o - connect \pll_lck_o \pll_lck_o + attribute \src "libresoc.v:186232.3-186247.6" + process $proc$libresoc.v:186232$13468 + assign { } { } + assign { } { } + assign $0\core_msr__ren[3:0] $1\core_msr__ren[3:0] + attribute \src "libresoc.v:186233.5-186233.29" + switch \initial + attribute \src "libresoc.v:186233.9-186233.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\core_msr__ren[3:0] $2\core_msr__ren[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + switch \$53 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\core_msr__ren[3:0] 4'0010 + case + assign $2\core_msr__ren[3:0] 4'0000 + end + case + assign $1\core_msr__ren[3:0] 4'0000 + end + sync always + update \core_msr__ren $0\core_msr__ren[3:0] end - attribute \module_not_derived 1 - attribute \src "libresoc.v:48370.6-48722.4" - cell \ti \ti - connect \TAP_bus__tck \TAP_bus__tck - connect \TAP_bus__tdi \TAP_bus__tdi - connect \TAP_bus__tdo \TAP_bus__tdo - connect \TAP_bus__tms \TAP_bus__tms - connect \busy_o \busy_o - connect \clk \clk - connect \core_bigendian_i \core_bigendian_i - connect \coresync_clk \ti_coresync_clk - connect \eint_0__core__i \eint_0__core__i - connect \eint_0__pad__i \eint_0__pad__i - connect \eint_1__core__i \eint_1__core__i - connect \eint_1__pad__i \eint_1__pad__i - connect \eint_2__core__i \eint_2__core__i - connect \eint_2__pad__i \eint_2__pad__i - connect \gpio_e10__core__i \gpio_e10__core__i - connect \gpio_e10__core__o \gpio_e10__core__o - connect \gpio_e10__core__oe \gpio_e10__core__oe - connect \gpio_e10__pad__i \gpio_e10__pad__i - connect \gpio_e10__pad__o \gpio_e10__pad__o - connect \gpio_e10__pad__oe \gpio_e10__pad__oe - connect \gpio_e11__core__i \gpio_e11__core__i - connect \gpio_e11__core__o \gpio_e11__core__o - connect \gpio_e11__core__oe \gpio_e11__core__oe - connect \gpio_e11__pad__i \gpio_e11__pad__i - connect \gpio_e11__pad__o \gpio_e11__pad__o - connect \gpio_e11__pad__oe \gpio_e11__pad__oe - connect \gpio_e12__core__i \gpio_e12__core__i - connect \gpio_e12__core__o \gpio_e12__core__o - connect \gpio_e12__core__oe \gpio_e12__core__oe - connect \gpio_e12__pad__i \gpio_e12__pad__i - connect \gpio_e12__pad__o \gpio_e12__pad__o - connect \gpio_e12__pad__oe \gpio_e12__pad__oe - connect \gpio_e13__core__i \gpio_e13__core__i - connect \gpio_e13__core__o \gpio_e13__core__o - connect \gpio_e13__core__oe \gpio_e13__core__oe - connect \gpio_e13__pad__i \gpio_e13__pad__i - connect \gpio_e13__pad__o \gpio_e13__pad__o - connect \gpio_e13__pad__oe \gpio_e13__pad__oe - connect \gpio_e14__core__i \gpio_e14__core__i - connect \gpio_e14__core__o \gpio_e14__core__o - connect \gpio_e14__core__oe \gpio_e14__core__oe - connect \gpio_e14__pad__i \gpio_e14__pad__i - connect \gpio_e14__pad__o \gpio_e14__pad__o - connect \gpio_e14__pad__oe \gpio_e14__pad__oe - connect \gpio_e15__core__i \gpio_e15__core__i - connect \gpio_e15__core__o \gpio_e15__core__o - connect \gpio_e15__core__oe \gpio_e15__core__oe - connect \gpio_e15__pad__i \gpio_e15__pad__i - connect \gpio_e15__pad__o \gpio_e15__pad__o - connect \gpio_e15__pad__oe \gpio_e15__pad__oe - connect \gpio_e8__core__i \gpio_e8__core__i - connect \gpio_e8__core__o \gpio_e8__core__o - connect \gpio_e8__core__oe \gpio_e8__core__oe - connect \gpio_e8__pad__i \gpio_e8__pad__i - connect \gpio_e8__pad__o \gpio_e8__pad__o - connect \gpio_e8__pad__oe \gpio_e8__pad__oe - connect \gpio_e9__core__i \gpio_e9__core__i - connect \gpio_e9__core__o \gpio_e9__core__o - connect \gpio_e9__core__oe \gpio_e9__core__oe - connect \gpio_e9__pad__i \gpio_e9__pad__i - connect \gpio_e9__pad__o \gpio_e9__pad__o - connect \gpio_e9__pad__oe \gpio_e9__pad__oe - connect \gpio_s0__core__i \gpio_s0__core__i - connect \gpio_s0__core__o \gpio_s0__core__o - connect \gpio_s0__core__oe \gpio_s0__core__oe - connect \gpio_s0__pad__i \gpio_s0__pad__i - connect \gpio_s0__pad__o \gpio_s0__pad__o - connect \gpio_s0__pad__oe \gpio_s0__pad__oe - connect \gpio_s1__core__i \gpio_s1__core__i - connect \gpio_s1__core__o \gpio_s1__core__o - connect \gpio_s1__core__oe \gpio_s1__core__oe - connect \gpio_s1__pad__i \gpio_s1__pad__i - connect \gpio_s1__pad__o \gpio_s1__pad__o - connect \gpio_s1__pad__oe \gpio_s1__pad__oe - connect \gpio_s2__core__i \gpio_s2__core__i - connect \gpio_s2__core__o \gpio_s2__core__o - connect \gpio_s2__core__oe \gpio_s2__core__oe - connect \gpio_s2__pad__i \gpio_s2__pad__i - connect \gpio_s2__pad__o \gpio_s2__pad__o - connect \gpio_s2__pad__oe \gpio_s2__pad__oe - connect \gpio_s3__core__i \gpio_s3__core__i - connect \gpio_s3__core__o \gpio_s3__core__o - connect \gpio_s3__core__oe \gpio_s3__core__oe - connect \gpio_s3__pad__i \gpio_s3__pad__i - connect \gpio_s3__pad__o \gpio_s3__pad__o - connect \gpio_s3__pad__oe \gpio_s3__pad__oe - connect \gpio_s4__core__i \gpio_s4__core__i - connect \gpio_s4__core__o \gpio_s4__core__o - connect \gpio_s4__core__oe \gpio_s4__core__oe - connect \gpio_s4__pad__i \gpio_s4__pad__i - connect \gpio_s4__pad__o \gpio_s4__pad__o - connect \gpio_s4__pad__oe \gpio_s4__pad__oe - connect \gpio_s5__core__i \gpio_s5__core__i - connect \gpio_s5__core__o \gpio_s5__core__o - connect \gpio_s5__core__oe \gpio_s5__core__oe - connect \gpio_s5__pad__i \gpio_s5__pad__i - connect \gpio_s5__pad__o \gpio_s5__pad__o - connect \gpio_s5__pad__oe \gpio_s5__pad__oe - connect \gpio_s6__core__i \gpio_s6__core__i - connect \gpio_s6__core__o \gpio_s6__core__o - connect \gpio_s6__core__oe \gpio_s6__core__oe - connect \gpio_s6__pad__i \gpio_s6__pad__i - connect \gpio_s6__pad__o \gpio_s6__pad__o - connect \gpio_s6__pad__oe \gpio_s6__pad__oe - connect \gpio_s7__core__i \gpio_s7__core__i - connect \gpio_s7__core__o \gpio_s7__core__o - connect \gpio_s7__core__oe \gpio_s7__core__oe - connect \gpio_s7__pad__i \gpio_s7__pad__i - connect \gpio_s7__pad__o \gpio_s7__pad__o - connect \gpio_s7__pad__oe \gpio_s7__pad__oe - connect \ibus__ack \ibus__ack - connect \ibus__adr \ibus__adr - connect \ibus__cyc \ibus__cyc - connect \ibus__dat_r \ibus__dat_r - connect \ibus__err \ibus__err - connect \ibus__sel \ibus__sel - connect \ibus__stb \ibus__stb - connect \icp_wb__ack \icp_wb__ack - connect \icp_wb__adr \icp_wb__adr - connect \icp_wb__cyc \icp_wb__cyc - connect \icp_wb__dat_r \icp_wb__dat_r - connect \icp_wb__dat_w \icp_wb__dat_w - connect \icp_wb__sel \icp_wb__sel - connect \icp_wb__stb \icp_wb__stb - connect \icp_wb__we \icp_wb__we - connect \ics_wb__ack \ics_wb__ack - connect \ics_wb__adr \ics_wb__adr - connect \ics_wb__cyc \ics_wb__cyc - connect \ics_wb__dat_r \ics_wb__dat_r - connect \ics_wb__dat_w \ics_wb__dat_w - connect \ics_wb__stb \ics_wb__stb - connect \ics_wb__we \ics_wb__we - connect \int_level_i \int_level_i - connect \jtag_wb__ack \jtag_wb__ack - connect \jtag_wb__adr \jtag_wb__adr - connect \jtag_wb__cyc \jtag_wb__cyc - connect \jtag_wb__dat_r \jtag_wb__dat_r - connect \jtag_wb__dat_w \jtag_wb__dat_w - connect \jtag_wb__sel \jtag_wb__sel - connect \jtag_wb__stb \jtag_wb__stb - connect \jtag_wb__we \jtag_wb__we - connect \mspi0_clk__core__o \mspi0_clk__core__o - connect \mspi0_clk__pad__o \mspi0_clk__pad__o - connect \mspi0_cs_n__core__o \mspi0_cs_n__core__o - connect \mspi0_cs_n__pad__o \mspi0_cs_n__pad__o - connect \mspi0_miso__core__i \mspi0_miso__core__i - connect \mspi0_miso__pad__i \mspi0_miso__pad__i - connect \mspi0_mosi__core__o \mspi0_mosi__core__o - connect \mspi0_mosi__pad__o \mspi0_mosi__pad__o - connect \mspi1_clk__core__o \mspi1_clk__core__o - connect \mspi1_clk__pad__o \mspi1_clk__pad__o - connect \mspi1_cs_n__core__o \mspi1_cs_n__core__o - connect \mspi1_cs_n__pad__o \mspi1_cs_n__pad__o - connect \mspi1_miso__core__i \mspi1_miso__core__i - connect \mspi1_miso__pad__i \mspi1_miso__pad__i - connect \mspi1_mosi__core__o \mspi1_mosi__core__o - connect \mspi1_mosi__pad__o \mspi1_mosi__pad__o - connect \mtwi_scl__core__o \mtwi_scl__core__o - connect \mtwi_scl__pad__o \mtwi_scl__pad__o - connect \mtwi_sda__core__i \mtwi_sda__core__i - connect \mtwi_sda__core__o \mtwi_sda__core__o - connect \mtwi_sda__core__oe \mtwi_sda__core__oe - connect \mtwi_sda__pad__i \mtwi_sda__pad__i - connect \mtwi_sda__pad__o \mtwi_sda__pad__o - connect \mtwi_sda__pad__oe \mtwi_sda__pad__oe - connect \pc_i \pc_i - connect \pc_i_ok \pc_i_ok - connect \pc_o \pc_o - connect \pwm_0__core__o \pwm_0__core__o - connect \pwm_0__pad__o \pwm_0__pad__o - connect \pwm_1__core__o \pwm_1__core__o - connect \pwm_1__pad__o \pwm_1__pad__o - connect \rst \rst - connect \sd0_clk__core__o \sd0_clk__core__o - connect \sd0_clk__pad__o \sd0_clk__pad__o - connect \sd0_cmd__core__i \sd0_cmd__core__i - connect \sd0_cmd__core__o \sd0_cmd__core__o - connect \sd0_cmd__core__oe \sd0_cmd__core__oe - connect \sd0_cmd__pad__i \sd0_cmd__pad__i - connect \sd0_cmd__pad__o \sd0_cmd__pad__o - connect \sd0_cmd__pad__oe \sd0_cmd__pad__oe - connect \sd0_data0__core__i \sd0_data0__core__i - connect \sd0_data0__core__o \sd0_data0__core__o - connect \sd0_data0__core__oe \sd0_data0__core__oe - connect \sd0_data0__pad__i \sd0_data0__pad__i - connect \sd0_data0__pad__o \sd0_data0__pad__o - connect \sd0_data0__pad__oe \sd0_data0__pad__oe - connect \sd0_data1__core__i \sd0_data1__core__i - connect \sd0_data1__core__o \sd0_data1__core__o - connect \sd0_data1__core__oe \sd0_data1__core__oe - connect \sd0_data1__pad__i \sd0_data1__pad__i - connect \sd0_data1__pad__o \sd0_data1__pad__o - connect \sd0_data1__pad__oe \sd0_data1__pad__oe - connect \sd0_data2__core__i \sd0_data2__core__i - connect \sd0_data2__core__o \sd0_data2__core__o - connect \sd0_data2__core__oe \sd0_data2__core__oe - connect \sd0_data2__pad__i \sd0_data2__pad__i - connect \sd0_data2__pad__o \sd0_data2__pad__o - connect \sd0_data2__pad__oe \sd0_data2__pad__oe - connect \sd0_data3__core__i \sd0_data3__core__i - connect \sd0_data3__core__o \sd0_data3__core__o - connect \sd0_data3__core__oe \sd0_data3__core__oe - connect \sd0_data3__pad__i \sd0_data3__pad__i - connect \sd0_data3__pad__o \sd0_data3__pad__o - connect \sd0_data3__pad__oe \sd0_data3__pad__oe - connect \sdr_a_0__core__o \sdr_a_0__core__o - connect \sdr_a_0__pad__o \sdr_a_0__pad__o - connect \sdr_a_10__core__o \sdr_a_10__core__o - connect \sdr_a_10__pad__o \sdr_a_10__pad__o - connect \sdr_a_11__core__o \sdr_a_11__core__o - connect \sdr_a_11__pad__o \sdr_a_11__pad__o - connect \sdr_a_12__core__o \sdr_a_12__core__o - connect \sdr_a_12__pad__o \sdr_a_12__pad__o - connect \sdr_a_1__core__o \sdr_a_1__core__o - connect \sdr_a_1__pad__o \sdr_a_1__pad__o - connect \sdr_a_2__core__o \sdr_a_2__core__o - connect \sdr_a_2__pad__o \sdr_a_2__pad__o - connect \sdr_a_3__core__o \sdr_a_3__core__o - connect \sdr_a_3__pad__o \sdr_a_3__pad__o - connect \sdr_a_4__core__o \sdr_a_4__core__o - connect \sdr_a_4__pad__o \sdr_a_4__pad__o - connect \sdr_a_5__core__o \sdr_a_5__core__o - connect \sdr_a_5__pad__o \sdr_a_5__pad__o - connect \sdr_a_6__core__o \sdr_a_6__core__o - connect \sdr_a_6__pad__o \sdr_a_6__pad__o - connect \sdr_a_7__core__o \sdr_a_7__core__o - connect \sdr_a_7__pad__o \sdr_a_7__pad__o - connect \sdr_a_8__core__o \sdr_a_8__core__o - connect \sdr_a_8__pad__o \sdr_a_8__pad__o - connect \sdr_a_9__core__o \sdr_a_9__core__o - connect \sdr_a_9__pad__o \sdr_a_9__pad__o - connect \sdr_ba_0__core__o \sdr_ba_0__core__o - connect \sdr_ba_0__pad__o \sdr_ba_0__pad__o - connect \sdr_ba_1__core__o \sdr_ba_1__core__o - connect \sdr_ba_1__pad__o \sdr_ba_1__pad__o - connect \sdr_cas_n__core__o \sdr_cas_n__core__o - connect \sdr_cas_n__pad__o \sdr_cas_n__pad__o - connect \sdr_cke__core__o \sdr_cke__core__o - connect \sdr_cke__pad__o \sdr_cke__pad__o - connect \sdr_clock__core__o \sdr_clock__core__o - connect \sdr_clock__pad__o \sdr_clock__pad__o - connect \sdr_cs_n__core__o \sdr_cs_n__core__o - connect \sdr_cs_n__pad__o \sdr_cs_n__pad__o - connect \sdr_dm_0__core__o \sdr_dm_0__core__o - connect \sdr_dm_0__pad__o \sdr_dm_0__pad__o - connect \sdr_dm_1__core__i \sdr_dm_1__core__i - connect \sdr_dm_1__core__o \sdr_dm_1__core__o - connect \sdr_dm_1__core__oe \sdr_dm_1__core__oe - connect \sdr_dm_1__pad__i \sdr_dm_1__pad__i - connect \sdr_dm_1__pad__o \sdr_dm_1__pad__o - connect \sdr_dm_1__pad__oe \sdr_dm_1__pad__oe - connect \sdr_dq_0__core__i \sdr_dq_0__core__i - connect \sdr_dq_0__core__o \sdr_dq_0__core__o - connect \sdr_dq_0__core__oe \sdr_dq_0__core__oe - connect \sdr_dq_0__pad__i \sdr_dq_0__pad__i - connect \sdr_dq_0__pad__o \sdr_dq_0__pad__o - connect \sdr_dq_0__pad__oe \sdr_dq_0__pad__oe - connect \sdr_dq_10__core__i \sdr_dq_10__core__i - connect \sdr_dq_10__core__o \sdr_dq_10__core__o - connect \sdr_dq_10__core__oe \sdr_dq_10__core__oe - connect \sdr_dq_10__pad__i \sdr_dq_10__pad__i - connect \sdr_dq_10__pad__o \sdr_dq_10__pad__o - connect \sdr_dq_10__pad__oe \sdr_dq_10__pad__oe - connect \sdr_dq_11__core__i \sdr_dq_11__core__i - connect \sdr_dq_11__core__o \sdr_dq_11__core__o - connect \sdr_dq_11__core__oe \sdr_dq_11__core__oe - connect \sdr_dq_11__pad__i \sdr_dq_11__pad__i - connect \sdr_dq_11__pad__o \sdr_dq_11__pad__o - connect \sdr_dq_11__pad__oe \sdr_dq_11__pad__oe - connect \sdr_dq_12__core__i \sdr_dq_12__core__i - connect \sdr_dq_12__core__o \sdr_dq_12__core__o - connect \sdr_dq_12__core__oe \sdr_dq_12__core__oe - connect \sdr_dq_12__pad__i \sdr_dq_12__pad__i - connect \sdr_dq_12__pad__o \sdr_dq_12__pad__o - connect \sdr_dq_12__pad__oe \sdr_dq_12__pad__oe - connect \sdr_dq_13__core__i \sdr_dq_13__core__i - connect \sdr_dq_13__core__o \sdr_dq_13__core__o - connect \sdr_dq_13__core__oe \sdr_dq_13__core__oe - connect \sdr_dq_13__pad__i \sdr_dq_13__pad__i - connect \sdr_dq_13__pad__o \sdr_dq_13__pad__o - connect \sdr_dq_13__pad__oe \sdr_dq_13__pad__oe - connect \sdr_dq_14__core__i \sdr_dq_14__core__i - connect \sdr_dq_14__core__o \sdr_dq_14__core__o - connect \sdr_dq_14__core__oe \sdr_dq_14__core__oe - connect \sdr_dq_14__pad__i \sdr_dq_14__pad__i - connect \sdr_dq_14__pad__o \sdr_dq_14__pad__o - connect \sdr_dq_14__pad__oe \sdr_dq_14__pad__oe - connect \sdr_dq_15__core__i \sdr_dq_15__core__i - connect \sdr_dq_15__core__o \sdr_dq_15__core__o - connect \sdr_dq_15__core__oe \sdr_dq_15__core__oe - connect \sdr_dq_15__pad__i \sdr_dq_15__pad__i - connect \sdr_dq_15__pad__o \sdr_dq_15__pad__o - connect \sdr_dq_15__pad__oe \sdr_dq_15__pad__oe - connect \sdr_dq_1__core__i \sdr_dq_1__core__i - connect \sdr_dq_1__core__o \sdr_dq_1__core__o - connect \sdr_dq_1__core__oe \sdr_dq_1__core__oe - connect \sdr_dq_1__pad__i \sdr_dq_1__pad__i - connect \sdr_dq_1__pad__o \sdr_dq_1__pad__o - connect \sdr_dq_1__pad__oe \sdr_dq_1__pad__oe - connect \sdr_dq_2__core__i \sdr_dq_2__core__i - connect \sdr_dq_2__core__o \sdr_dq_2__core__o - connect \sdr_dq_2__core__oe \sdr_dq_2__core__oe - connect \sdr_dq_2__pad__i \sdr_dq_2__pad__i - connect \sdr_dq_2__pad__o \sdr_dq_2__pad__o - connect \sdr_dq_2__pad__oe \sdr_dq_2__pad__oe - connect \sdr_dq_3__core__i \sdr_dq_3__core__i - connect \sdr_dq_3__core__o \sdr_dq_3__core__o - connect \sdr_dq_3__core__oe \sdr_dq_3__core__oe - connect \sdr_dq_3__pad__i \sdr_dq_3__pad__i - connect \sdr_dq_3__pad__o \sdr_dq_3__pad__o - connect \sdr_dq_3__pad__oe \sdr_dq_3__pad__oe - connect \sdr_dq_4__core__i \sdr_dq_4__core__i - connect \sdr_dq_4__core__o \sdr_dq_4__core__o - connect \sdr_dq_4__core__oe \sdr_dq_4__core__oe - connect \sdr_dq_4__pad__i \sdr_dq_4__pad__i - connect \sdr_dq_4__pad__o \sdr_dq_4__pad__o - connect \sdr_dq_4__pad__oe \sdr_dq_4__pad__oe - connect \sdr_dq_5__core__i \sdr_dq_5__core__i - connect \sdr_dq_5__core__o \sdr_dq_5__core__o - connect \sdr_dq_5__core__oe \sdr_dq_5__core__oe - connect \sdr_dq_5__pad__i \sdr_dq_5__pad__i - connect \sdr_dq_5__pad__o \sdr_dq_5__pad__o - connect \sdr_dq_5__pad__oe \sdr_dq_5__pad__oe - connect \sdr_dq_6__core__i \sdr_dq_6__core__i - connect \sdr_dq_6__core__o \sdr_dq_6__core__o - connect \sdr_dq_6__core__oe \sdr_dq_6__core__oe - connect \sdr_dq_6__pad__i \sdr_dq_6__pad__i - connect \sdr_dq_6__pad__o \sdr_dq_6__pad__o - connect \sdr_dq_6__pad__oe \sdr_dq_6__pad__oe - connect \sdr_dq_7__core__i \sdr_dq_7__core__i - connect \sdr_dq_7__core__o \sdr_dq_7__core__o - connect \sdr_dq_7__core__oe \sdr_dq_7__core__oe - connect \sdr_dq_7__pad__i \sdr_dq_7__pad__i - connect \sdr_dq_7__pad__o \sdr_dq_7__pad__o - connect \sdr_dq_7__pad__oe \sdr_dq_7__pad__oe - connect \sdr_dq_8__core__i \sdr_dq_8__core__i - connect \sdr_dq_8__core__o \sdr_dq_8__core__o - connect \sdr_dq_8__core__oe \sdr_dq_8__core__oe - connect \sdr_dq_8__pad__i \sdr_dq_8__pad__i - connect \sdr_dq_8__pad__o \sdr_dq_8__pad__o - connect \sdr_dq_8__pad__oe \sdr_dq_8__pad__oe - connect \sdr_dq_9__core__i \sdr_dq_9__core__i - connect \sdr_dq_9__core__o \sdr_dq_9__core__o - connect \sdr_dq_9__core__oe \sdr_dq_9__core__oe - connect \sdr_dq_9__pad__i \sdr_dq_9__pad__i - connect \sdr_dq_9__pad__o \sdr_dq_9__pad__o - connect \sdr_dq_9__pad__oe \sdr_dq_9__pad__oe - connect \sdr_ras_n__core__o \sdr_ras_n__core__o - connect \sdr_ras_n__pad__o \sdr_ras_n__pad__o - connect \sdr_we_n__core__o \sdr_we_n__core__o - connect \sdr_we_n__pad__o \sdr_we_n__pad__o + attribute \src "libresoc.v:186248.3-186256.6" + process $proc$libresoc.v:186248$13469 + assign { } { } + assign { } { } + assign $0\dbg_dmi_din$next[63:0]$13470 $1\dbg_dmi_din$next[63:0]$13471 + attribute \src "libresoc.v:186249.5-186249.29" + switch \initial + attribute \src "libresoc.v:186249.9-186249.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_dmi_din$next[63:0]$13471 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $1\dbg_dmi_din$next[63:0]$13471 \jtag_dmi0__din + end + sync always + update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$13470 + end + attribute \src "libresoc.v:186257.3-186281.6" + process $proc$libresoc.v:186257$13472 + assign { } { } + assign { } { } + assign { } { } + assign $0\pc_changed$next[0:0]$13473 $3\pc_changed$next[0:0]$13476 + attribute \src "libresoc.v:186258.5-186258.29" + switch \initial + attribute \src "libresoc.v:186258.9-186258.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\pc_changed$next[0:0]$13474 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\pc_changed$next[0:0]$13474 $2\pc_changed$next[0:0]$13475 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:309" + switch \$55 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\pc_changed$next[0:0]$13475 1'1 + case + assign $2\pc_changed$next[0:0]$13475 \pc_changed + end + case + assign $1\pc_changed$next[0:0]$13474 \pc_changed + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\pc_changed$next[0:0]$13476 1'0 + case + assign $3\pc_changed$next[0:0]$13476 $1\pc_changed$next[0:0]$13474 + end + sync always + update \pc_changed$next $0\pc_changed$next[0:0]$13473 + end + attribute \src "libresoc.v:186282.3-186404.6" + process $proc$libresoc.v:186282$13477 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\core_asmcode$next[7:0]$13478 $1\core_asmcode$next[7:0]$13537 + assign $0\core_core_core_cia$next[63:0]$13479 $1\core_core_core_cia$next[63:0]$13538 + assign $0\core_core_core_cr_rd$next[7:0]$13480 $1\core_core_core_cr_rd$next[7:0]$13539 + assign { } { } + assign $0\core_core_core_cr_wr$next[7:0]$13482 $1\core_core_core_cr_wr$next[7:0]$13541 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\core_core_core_fn_unit$next[11:0]$13491 $1\core_core_core_fn_unit$next[11:0]$13550 + assign $0\core_core_core_input_carry$next[1:0]$13492 $1\core_core_core_input_carry$next[1:0]$13551 + assign $0\core_core_core_insn$next[31:0]$13493 $1\core_core_core_insn$next[31:0]$13552 + assign $0\core_core_core_insn_type$next[6:0]$13494 $1\core_core_core_insn_type$next[6:0]$13553 + assign $0\core_core_core_is_32bit$next[0:0]$13495 $1\core_core_core_is_32bit$next[0:0]$13554 + assign $0\core_core_core_msr$next[63:0]$13496 $1\core_core_core_msr$next[63:0]$13555 + assign $0\core_core_core_oe$next[0:0]$13497 $1\core_core_core_oe$next[0:0]$13556 + assign { } { } + assign $0\core_core_core_rc$next[0:0]$13499 $1\core_core_core_rc$next[0:0]$13558 + assign { } { } + assign $0\core_core_core_trapaddr$next[12:0]$13501 $1\core_core_core_trapaddr$next[12:0]$13560 + assign $0\core_core_core_traptype$next[7:0]$13502 $1\core_core_core_traptype$next[7:0]$13561 + assign $0\core_core_cr_in1$next[2:0]$13503 $1\core_core_cr_in1$next[2:0]$13562 + assign { } { } + assign $0\core_core_cr_in2$1$next[2:0]$13505 $1\core_core_cr_in2$1$next[2:0]$13564 + assign $0\core_core_cr_in2$next[2:0]$13506 $1\core_core_cr_in2$next[2:0]$13565 + assign { } { } + assign { } { } + assign $0\core_core_cr_out$next[2:0]$13509 $1\core_core_cr_out$next[2:0]$13568 + assign { } { } + assign $0\core_core_ea$next[4:0]$13511 $1\core_core_ea$next[4:0]$13570 + assign $0\core_core_fast1$next[2:0]$13512 $1\core_core_fast1$next[2:0]$13571 + assign { } { } + assign $0\core_core_fast2$next[2:0]$13514 $1\core_core_fast2$next[2:0]$13573 + assign { } { } + assign $0\core_core_fasto1$next[2:0]$13516 $1\core_core_fasto1$next[2:0]$13575 + assign $0\core_core_fasto2$next[2:0]$13517 $1\core_core_fasto2$next[2:0]$13576 + assign $0\core_core_lk$next[0:0]$13518 $1\core_core_lk$next[0:0]$13577 + assign $0\core_core_reg1$next[4:0]$13519 $1\core_core_reg1$next[4:0]$13578 + assign { } { } + assign $0\core_core_reg2$next[4:0]$13521 $1\core_core_reg2$next[4:0]$13580 + assign { } { } + assign $0\core_core_reg3$next[4:0]$13523 $1\core_core_reg3$next[4:0]$13582 + assign { } { } + assign $0\core_core_rego$next[4:0]$13525 $1\core_core_rego$next[4:0]$13584 + assign $0\core_core_spr1$next[9:0]$13526 $1\core_core_spr1$next[9:0]$13585 + assign { } { } + assign $0\core_core_spro$next[9:0]$13528 $1\core_core_spro$next[9:0]$13587 + assign $0\core_core_xer_in$next[2:0]$13529 $1\core_core_xer_in$next[2:0]$13588 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\core_xer_out$next[0:0]$13536 $1\core_xer_out$next[0:0]$13595 + assign $0\core_core_core_cr_rd_ok$next[0:0]$13481 $4\core_core_core_cr_rd_ok$next[0:0]$13714 + assign $0\core_core_core_exc_$signal$3$next[0:0]$13483 $4\core_core_core_exc_$signal$3$next[0:0]$13715 + assign $0\core_core_core_exc_$signal$4$next[0:0]$13484 $4\core_core_core_exc_$signal$4$next[0:0]$13716 + assign $0\core_core_core_exc_$signal$5$next[0:0]$13485 $4\core_core_core_exc_$signal$5$next[0:0]$13717 + assign $0\core_core_core_exc_$signal$6$next[0:0]$13486 $4\core_core_core_exc_$signal$6$next[0:0]$13718 + assign $0\core_core_core_exc_$signal$7$next[0:0]$13487 $4\core_core_core_exc_$signal$7$next[0:0]$13719 + assign $0\core_core_core_exc_$signal$8$next[0:0]$13488 $4\core_core_core_exc_$signal$8$next[0:0]$13720 + assign $0\core_core_core_exc_$signal$9$next[0:0]$13489 $4\core_core_core_exc_$signal$9$next[0:0]$13721 + assign $0\core_core_core_exc_$signal$next[0:0]$13490 $4\core_core_core_exc_$signal$next[0:0]$13722 + assign $0\core_core_core_oe_ok$next[0:0]$13498 $4\core_core_core_oe_ok$next[0:0]$13723 + assign $0\core_core_core_rc_ok$next[0:0]$13500 $4\core_core_core_rc_ok$next[0:0]$13724 + assign $0\core_core_cr_in1_ok$next[0:0]$13504 $4\core_core_cr_in1_ok$next[0:0]$13725 + assign $0\core_core_cr_in2_ok$2$next[0:0]$13507 $4\core_core_cr_in2_ok$2$next[0:0]$13726 + assign $0\core_core_cr_in2_ok$next[0:0]$13508 $4\core_core_cr_in2_ok$next[0:0]$13727 + assign $0\core_core_cr_wr_ok$next[0:0]$13510 $4\core_core_cr_wr_ok$next[0:0]$13728 + assign $0\core_core_fast1_ok$next[0:0]$13513 $4\core_core_fast1_ok$next[0:0]$13729 + assign $0\core_core_fast2_ok$next[0:0]$13515 $4\core_core_fast2_ok$next[0:0]$13730 + assign $0\core_core_reg1_ok$next[0:0]$13520 $4\core_core_reg1_ok$next[0:0]$13731 + assign $0\core_core_reg2_ok$next[0:0]$13522 $4\core_core_reg2_ok$next[0:0]$13732 + assign $0\core_core_reg3_ok$next[0:0]$13524 $4\core_core_reg3_ok$next[0:0]$13733 + assign $0\core_core_spr1_ok$next[0:0]$13527 $4\core_core_spr1_ok$next[0:0]$13734 + assign $0\core_cr_out_ok$next[0:0]$13530 $4\core_cr_out_ok$next[0:0]$13735 + assign $0\core_ea_ok$next[0:0]$13531 $4\core_ea_ok$next[0:0]$13736 + assign $0\core_fasto1_ok$next[0:0]$13532 $4\core_fasto1_ok$next[0:0]$13737 + assign $0\core_fasto2_ok$next[0:0]$13533 $4\core_fasto2_ok$next[0:0]$13738 + assign $0\core_rego_ok$next[0:0]$13534 $4\core_rego_ok$next[0:0]$13739 + assign $0\core_spro_ok$next[0:0]$13535 $4\core_spro_ok$next[0:0]$13740 + attribute \src "libresoc.v:186283.5-186283.29" + switch \initial + attribute \src "libresoc.v:186283.9-186283.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\core_core_core_is_32bit$next[0:0]$13554 $1\core_core_cr_wr_ok$next[0:0]$13569 $1\core_core_core_cr_wr$next[7:0]$13541 $1\core_core_core_cr_rd_ok$next[0:0]$13540 $1\core_core_core_cr_rd$next[7:0]$13539 $1\core_core_core_trapaddr$next[12:0]$13560 $1\core_core_core_exc_$signal$9$next[0:0]$13548 $1\core_core_core_exc_$signal$8$next[0:0]$13547 $1\core_core_core_exc_$signal$7$next[0:0]$13546 $1\core_core_core_exc_$signal$6$next[0:0]$13545 $1\core_core_core_exc_$signal$5$next[0:0]$13544 $1\core_core_core_exc_$signal$4$next[0:0]$13543 $1\core_core_core_exc_$signal$3$next[0:0]$13542 $1\core_core_core_exc_$signal$next[0:0]$13549 $1\core_core_core_traptype$next[7:0]$13561 $1\core_core_core_input_carry$next[1:0]$13551 $1\core_core_core_oe_ok$next[0:0]$13557 $1\core_core_core_oe$next[0:0]$13556 $1\core_core_core_rc_ok$next[0:0]$13559 $1\core_core_core_rc$next[0:0]$13558 $1\core_core_lk$next[0:0]$13577 $1\core_core_core_fn_unit$next[11:0]$13550 $1\core_core_core_insn_type$next[6:0]$13553 $1\core_core_core_insn$next[31:0]$13552 $1\core_core_core_cia$next[63:0]$13538 $1\core_core_core_msr$next[63:0]$13555 $1\core_cr_out_ok$next[0:0]$13589 $1\core_core_cr_out$next[2:0]$13568 $1\core_core_cr_in2_ok$2$next[0:0]$13566 $1\core_core_cr_in2$1$next[2:0]$13564 $1\core_core_cr_in2_ok$next[0:0]$13567 $1\core_core_cr_in2$next[2:0]$13565 $1\core_core_cr_in1_ok$next[0:0]$13563 $1\core_core_cr_in1$next[2:0]$13562 $1\core_fasto2_ok$next[0:0]$13592 $1\core_core_fasto2$next[2:0]$13576 $1\core_fasto1_ok$next[0:0]$13591 $1\core_core_fasto1$next[2:0]$13575 $1\core_core_fast2_ok$next[0:0]$13574 $1\core_core_fast2$next[2:0]$13573 $1\core_core_fast1_ok$next[0:0]$13572 $1\core_core_fast1$next[2:0]$13571 $1\core_xer_out$next[0:0]$13595 $1\core_core_xer_in$next[2:0]$13588 $1\core_core_spr1_ok$next[0:0]$13586 $1\core_core_spr1$next[9:0]$13585 $1\core_spro_ok$next[0:0]$13594 $1\core_core_spro$next[9:0]$13587 $1\core_core_reg3_ok$next[0:0]$13583 $1\core_core_reg3$next[4:0]$13582 $1\core_core_reg2_ok$next[0:0]$13581 $1\core_core_reg2$next[4:0]$13580 $1\core_core_reg1_ok$next[0:0]$13579 $1\core_core_reg1$next[4:0]$13578 $1\core_ea_ok$next[0:0]$13590 $1\core_core_ea$next[4:0]$13570 $1\core_rego_ok$next[0:0]$13593 $1\core_core_rego$next[4:0]$13584 $1\core_asmcode$next[7:0]$13537 } 330'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\core_asmcode$next[7:0]$13537 $2\core_asmcode$next[7:0]$13596 + assign $1\core_core_core_cia$next[63:0]$13538 $2\core_core_core_cia$next[63:0]$13597 + assign $1\core_core_core_cr_rd$next[7:0]$13539 $2\core_core_core_cr_rd$next[7:0]$13598 + assign $1\core_core_core_cr_rd_ok$next[0:0]$13540 $2\core_core_core_cr_rd_ok$next[0:0]$13599 + assign $1\core_core_core_cr_wr$next[7:0]$13541 $2\core_core_core_cr_wr$next[7:0]$13600 + assign $1\core_core_core_exc_$signal$3$next[0:0]$13542 $2\core_core_core_exc_$signal$3$next[0:0]$13601 + assign $1\core_core_core_exc_$signal$4$next[0:0]$13543 $2\core_core_core_exc_$signal$4$next[0:0]$13602 + assign $1\core_core_core_exc_$signal$5$next[0:0]$13544 $2\core_core_core_exc_$signal$5$next[0:0]$13603 + assign $1\core_core_core_exc_$signal$6$next[0:0]$13545 $2\core_core_core_exc_$signal$6$next[0:0]$13604 + assign $1\core_core_core_exc_$signal$7$next[0:0]$13546 $2\core_core_core_exc_$signal$7$next[0:0]$13605 + assign $1\core_core_core_exc_$signal$8$next[0:0]$13547 $2\core_core_core_exc_$signal$8$next[0:0]$13606 + assign $1\core_core_core_exc_$signal$9$next[0:0]$13548 $2\core_core_core_exc_$signal$9$next[0:0]$13607 + assign $1\core_core_core_exc_$signal$next[0:0]$13549 $2\core_core_core_exc_$signal$next[0:0]$13608 + assign $1\core_core_core_fn_unit$next[11:0]$13550 $2\core_core_core_fn_unit$next[11:0]$13609 + assign $1\core_core_core_input_carry$next[1:0]$13551 $2\core_core_core_input_carry$next[1:0]$13610 + assign $1\core_core_core_insn$next[31:0]$13552 $2\core_core_core_insn$next[31:0]$13611 + assign $1\core_core_core_insn_type$next[6:0]$13553 $2\core_core_core_insn_type$next[6:0]$13612 + assign $1\core_core_core_is_32bit$next[0:0]$13554 $2\core_core_core_is_32bit$next[0:0]$13613 + assign $1\core_core_core_msr$next[63:0]$13555 $2\core_core_core_msr$next[63:0]$13614 + assign $1\core_core_core_oe$next[0:0]$13556 $2\core_core_core_oe$next[0:0]$13615 + assign $1\core_core_core_oe_ok$next[0:0]$13557 $2\core_core_core_oe_ok$next[0:0]$13616 + assign $1\core_core_core_rc$next[0:0]$13558 $2\core_core_core_rc$next[0:0]$13617 + assign $1\core_core_core_rc_ok$next[0:0]$13559 $2\core_core_core_rc_ok$next[0:0]$13618 + assign $1\core_core_core_trapaddr$next[12:0]$13560 $2\core_core_core_trapaddr$next[12:0]$13619 + assign $1\core_core_core_traptype$next[7:0]$13561 $2\core_core_core_traptype$next[7:0]$13620 + assign $1\core_core_cr_in1$next[2:0]$13562 $2\core_core_cr_in1$next[2:0]$13621 + assign $1\core_core_cr_in1_ok$next[0:0]$13563 $2\core_core_cr_in1_ok$next[0:0]$13622 + assign $1\core_core_cr_in2$1$next[2:0]$13564 $2\core_core_cr_in2$1$next[2:0]$13623 + assign $1\core_core_cr_in2$next[2:0]$13565 $2\core_core_cr_in2$next[2:0]$13624 + assign $1\core_core_cr_in2_ok$2$next[0:0]$13566 $2\core_core_cr_in2_ok$2$next[0:0]$13625 + assign $1\core_core_cr_in2_ok$next[0:0]$13567 $2\core_core_cr_in2_ok$next[0:0]$13626 + assign $1\core_core_cr_out$next[2:0]$13568 $2\core_core_cr_out$next[2:0]$13627 + assign $1\core_core_cr_wr_ok$next[0:0]$13569 $2\core_core_cr_wr_ok$next[0:0]$13628 + assign $1\core_core_ea$next[4:0]$13570 $2\core_core_ea$next[4:0]$13629 + assign $1\core_core_fast1$next[2:0]$13571 $2\core_core_fast1$next[2:0]$13630 + assign $1\core_core_fast1_ok$next[0:0]$13572 $2\core_core_fast1_ok$next[0:0]$13631 + assign $1\core_core_fast2$next[2:0]$13573 $2\core_core_fast2$next[2:0]$13632 + assign $1\core_core_fast2_ok$next[0:0]$13574 $2\core_core_fast2_ok$next[0:0]$13633 + assign $1\core_core_fasto1$next[2:0]$13575 $2\core_core_fasto1$next[2:0]$13634 + assign $1\core_core_fasto2$next[2:0]$13576 $2\core_core_fasto2$next[2:0]$13635 + assign $1\core_core_lk$next[0:0]$13577 $2\core_core_lk$next[0:0]$13636 + assign $1\core_core_reg1$next[4:0]$13578 $2\core_core_reg1$next[4:0]$13637 + assign $1\core_core_reg1_ok$next[0:0]$13579 $2\core_core_reg1_ok$next[0:0]$13638 + assign $1\core_core_reg2$next[4:0]$13580 $2\core_core_reg2$next[4:0]$13639 + assign $1\core_core_reg2_ok$next[0:0]$13581 $2\core_core_reg2_ok$next[0:0]$13640 + assign $1\core_core_reg3$next[4:0]$13582 $2\core_core_reg3$next[4:0]$13641 + assign $1\core_core_reg3_ok$next[0:0]$13583 $2\core_core_reg3_ok$next[0:0]$13642 + assign $1\core_core_rego$next[4:0]$13584 $2\core_core_rego$next[4:0]$13643 + assign $1\core_core_spr1$next[9:0]$13585 $2\core_core_spr1$next[9:0]$13644 + assign $1\core_core_spr1_ok$next[0:0]$13586 $2\core_core_spr1_ok$next[0:0]$13645 + assign $1\core_core_spro$next[9:0]$13587 $2\core_core_spro$next[9:0]$13646 + assign $1\core_core_xer_in$next[2:0]$13588 $2\core_core_xer_in$next[2:0]$13647 + assign $1\core_cr_out_ok$next[0:0]$13589 $2\core_cr_out_ok$next[0:0]$13648 + assign $1\core_ea_ok$next[0:0]$13590 $2\core_ea_ok$next[0:0]$13649 + assign $1\core_fasto1_ok$next[0:0]$13591 $2\core_fasto1_ok$next[0:0]$13650 + assign $1\core_fasto2_ok$next[0:0]$13592 $2\core_fasto2_ok$next[0:0]$13651 + assign $1\core_rego_ok$next[0:0]$13593 $2\core_rego_ok$next[0:0]$13652 + assign $1\core_spro_ok$next[0:0]$13594 $2\core_spro_ok$next[0:0]$13653 + assign $1\core_xer_out$next[0:0]$13595 $2\core_xer_out$next[0:0]$13654 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\core_asmcode$next[7:0]$13596 \core_asmcode + assign $2\core_core_core_cia$next[63:0]$13597 \core_core_core_cia + assign $2\core_core_core_cr_rd$next[7:0]$13598 \core_core_core_cr_rd + assign $2\core_core_core_cr_rd_ok$next[0:0]$13599 \core_core_core_cr_rd_ok + assign $2\core_core_core_cr_wr$next[7:0]$13600 \core_core_core_cr_wr + assign $2\core_core_core_exc_$signal$3$next[0:0]$13601 \core_core_core_exc_$signal$3 + assign $2\core_core_core_exc_$signal$4$next[0:0]$13602 \core_core_core_exc_$signal$4 + assign $2\core_core_core_exc_$signal$5$next[0:0]$13603 \core_core_core_exc_$signal$5 + assign $2\core_core_core_exc_$signal$6$next[0:0]$13604 \core_core_core_exc_$signal$6 + assign $2\core_core_core_exc_$signal$7$next[0:0]$13605 \core_core_core_exc_$signal$7 + assign $2\core_core_core_exc_$signal$8$next[0:0]$13606 \core_core_core_exc_$signal$8 + assign $2\core_core_core_exc_$signal$9$next[0:0]$13607 \core_core_core_exc_$signal$9 + assign $2\core_core_core_exc_$signal$next[0:0]$13608 \core_core_core_exc_$signal + assign $2\core_core_core_fn_unit$next[11:0]$13609 \core_core_core_fn_unit + assign $2\core_core_core_input_carry$next[1:0]$13610 \core_core_core_input_carry + assign $2\core_core_core_insn$next[31:0]$13611 \core_core_core_insn + assign $2\core_core_core_insn_type$next[6:0]$13612 \core_core_core_insn_type + assign $2\core_core_core_is_32bit$next[0:0]$13613 \core_core_core_is_32bit + assign $2\core_core_core_msr$next[63:0]$13614 \core_core_core_msr + assign $2\core_core_core_oe$next[0:0]$13615 \core_core_core_oe + assign $2\core_core_core_oe_ok$next[0:0]$13616 \core_core_core_oe_ok + assign $2\core_core_core_rc$next[0:0]$13617 \core_core_core_rc + assign $2\core_core_core_rc_ok$next[0:0]$13618 \core_core_core_rc_ok + assign $2\core_core_core_trapaddr$next[12:0]$13619 \core_core_core_trapaddr + assign $2\core_core_core_traptype$next[7:0]$13620 \core_core_core_traptype + assign $2\core_core_cr_in1$next[2:0]$13621 \core_core_cr_in1 + assign $2\core_core_cr_in1_ok$next[0:0]$13622 \core_core_cr_in1_ok + assign $2\core_core_cr_in2$1$next[2:0]$13623 \core_core_cr_in2$1 + assign $2\core_core_cr_in2$next[2:0]$13624 \core_core_cr_in2 + assign $2\core_core_cr_in2_ok$2$next[0:0]$13625 \core_core_cr_in2_ok$2 + assign $2\core_core_cr_in2_ok$next[0:0]$13626 \core_core_cr_in2_ok + assign $2\core_core_cr_out$next[2:0]$13627 \core_core_cr_out + assign $2\core_core_cr_wr_ok$next[0:0]$13628 \core_core_cr_wr_ok + assign $2\core_core_ea$next[4:0]$13629 \core_core_ea + assign $2\core_core_fast1$next[2:0]$13630 \core_core_fast1 + assign $2\core_core_fast1_ok$next[0:0]$13631 \core_core_fast1_ok + assign $2\core_core_fast2$next[2:0]$13632 \core_core_fast2 + assign $2\core_core_fast2_ok$next[0:0]$13633 \core_core_fast2_ok + assign $2\core_core_fasto1$next[2:0]$13634 \core_core_fasto1 + assign $2\core_core_fasto2$next[2:0]$13635 \core_core_fasto2 + assign $2\core_core_lk$next[0:0]$13636 \core_core_lk + assign $2\core_core_reg1$next[4:0]$13637 \core_core_reg1 + assign $2\core_core_reg1_ok$next[0:0]$13638 \core_core_reg1_ok + assign $2\core_core_reg2$next[4:0]$13639 \core_core_reg2 + assign $2\core_core_reg2_ok$next[0:0]$13640 \core_core_reg2_ok + assign $2\core_core_reg3$next[4:0]$13641 \core_core_reg3 + assign $2\core_core_reg3_ok$next[0:0]$13642 \core_core_reg3_ok + assign $2\core_core_rego$next[4:0]$13643 \core_core_rego + assign $2\core_core_spr1$next[9:0]$13644 \core_core_spr1 + assign $2\core_core_spr1_ok$next[0:0]$13645 \core_core_spr1_ok + assign $2\core_core_spro$next[9:0]$13646 \core_core_spro + assign $2\core_core_xer_in$next[2:0]$13647 \core_core_xer_in + assign $2\core_cr_out_ok$next[0:0]$13648 \core_cr_out_ok + assign $2\core_ea_ok$next[0:0]$13649 \core_ea_ok + assign $2\core_fasto1_ok$next[0:0]$13650 \core_fasto1_ok + assign $2\core_fasto2_ok$next[0:0]$13651 \core_fasto2_ok + assign $2\core_rego_ok$next[0:0]$13652 \core_rego_ok + assign $2\core_spro_ok$next[0:0]$13653 \core_spro_ok + assign $2\core_xer_out$next[0:0]$13654 \core_xer_out + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\core_core_core_is_32bit$next[0:0]$13613 $2\core_core_cr_wr_ok$next[0:0]$13628 $2\core_core_core_cr_wr$next[7:0]$13600 $2\core_core_core_cr_rd_ok$next[0:0]$13599 $2\core_core_core_cr_rd$next[7:0]$13598 $2\core_core_core_trapaddr$next[12:0]$13619 $2\core_core_core_exc_$signal$9$next[0:0]$13607 $2\core_core_core_exc_$signal$8$next[0:0]$13606 $2\core_core_core_exc_$signal$7$next[0:0]$13605 $2\core_core_core_exc_$signal$6$next[0:0]$13604 $2\core_core_core_exc_$signal$5$next[0:0]$13603 $2\core_core_core_exc_$signal$4$next[0:0]$13602 $2\core_core_core_exc_$signal$3$next[0:0]$13601 $2\core_core_core_exc_$signal$next[0:0]$13608 $2\core_core_core_traptype$next[7:0]$13620 $2\core_core_core_input_carry$next[1:0]$13610 $2\core_core_core_oe_ok$next[0:0]$13616 $2\core_core_core_oe$next[0:0]$13615 $2\core_core_core_rc_ok$next[0:0]$13618 $2\core_core_core_rc$next[0:0]$13617 $2\core_core_lk$next[0:0]$13636 $2\core_core_core_fn_unit$next[11:0]$13609 $2\core_core_core_insn_type$next[6:0]$13612 $2\core_core_core_insn$next[31:0]$13611 $2\core_core_core_cia$next[63:0]$13597 $2\core_core_core_msr$next[63:0]$13614 $2\core_cr_out_ok$next[0:0]$13648 $2\core_core_cr_out$next[2:0]$13627 $2\core_core_cr_in2_ok$2$next[0:0]$13625 $2\core_core_cr_in2$1$next[2:0]$13623 $2\core_core_cr_in2_ok$next[0:0]$13626 $2\core_core_cr_in2$next[2:0]$13624 $2\core_core_cr_in1_ok$next[0:0]$13622 $2\core_core_cr_in1$next[2:0]$13621 $2\core_fasto2_ok$next[0:0]$13651 $2\core_core_fasto2$next[2:0]$13635 $2\core_fasto1_ok$next[0:0]$13650 $2\core_core_fasto1$next[2:0]$13634 $2\core_core_fast2_ok$next[0:0]$13633 $2\core_core_fast2$next[2:0]$13632 $2\core_core_fast1_ok$next[0:0]$13631 $2\core_core_fast1$next[2:0]$13630 $2\core_xer_out$next[0:0]$13654 $2\core_core_xer_in$next[2:0]$13647 $2\core_core_spr1_ok$next[0:0]$13645 $2\core_core_spr1$next[9:0]$13644 $2\core_spro_ok$next[0:0]$13653 $2\core_core_spro$next[9:0]$13646 $2\core_core_reg3_ok$next[0:0]$13642 $2\core_core_reg3$next[4:0]$13641 $2\core_core_reg2_ok$next[0:0]$13640 $2\core_core_reg2$next[4:0]$13639 $2\core_core_reg1_ok$next[0:0]$13638 $2\core_core_reg1$next[4:0]$13637 $2\core_ea_ok$next[0:0]$13649 $2\core_core_ea$next[4:0]$13629 $2\core_rego_ok$next[0:0]$13652 $2\core_core_rego$next[4:0]$13643 $2\core_asmcode$next[7:0]$13596 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal$15 \dec2_exc_$signal$14 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$13 \dec2_cr_in2$12 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } + end + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\core_asmcode$next[7:0]$13537 $3\core_asmcode$next[7:0]$13655 + assign $1\core_core_core_cia$next[63:0]$13538 $3\core_core_core_cia$next[63:0]$13656 + assign $1\core_core_core_cr_rd$next[7:0]$13539 $3\core_core_core_cr_rd$next[7:0]$13657 + assign $1\core_core_core_cr_rd_ok$next[0:0]$13540 $3\core_core_core_cr_rd_ok$next[0:0]$13658 + assign $1\core_core_core_cr_wr$next[7:0]$13541 $3\core_core_core_cr_wr$next[7:0]$13659 + assign $1\core_core_core_exc_$signal$3$next[0:0]$13542 $3\core_core_core_exc_$signal$3$next[0:0]$13660 + assign $1\core_core_core_exc_$signal$4$next[0:0]$13543 $3\core_core_core_exc_$signal$4$next[0:0]$13661 + assign $1\core_core_core_exc_$signal$5$next[0:0]$13544 $3\core_core_core_exc_$signal$5$next[0:0]$13662 + assign $1\core_core_core_exc_$signal$6$next[0:0]$13545 $3\core_core_core_exc_$signal$6$next[0:0]$13663 + assign $1\core_core_core_exc_$signal$7$next[0:0]$13546 $3\core_core_core_exc_$signal$7$next[0:0]$13664 + assign $1\core_core_core_exc_$signal$8$next[0:0]$13547 $3\core_core_core_exc_$signal$8$next[0:0]$13665 + assign $1\core_core_core_exc_$signal$9$next[0:0]$13548 $3\core_core_core_exc_$signal$9$next[0:0]$13666 + assign $1\core_core_core_exc_$signal$next[0:0]$13549 $3\core_core_core_exc_$signal$next[0:0]$13667 + assign $1\core_core_core_fn_unit$next[11:0]$13550 $3\core_core_core_fn_unit$next[11:0]$13668 + assign $1\core_core_core_input_carry$next[1:0]$13551 $3\core_core_core_input_carry$next[1:0]$13669 + assign $1\core_core_core_insn$next[31:0]$13552 $3\core_core_core_insn$next[31:0]$13670 + assign $1\core_core_core_insn_type$next[6:0]$13553 $3\core_core_core_insn_type$next[6:0]$13671 + assign $1\core_core_core_is_32bit$next[0:0]$13554 $3\core_core_core_is_32bit$next[0:0]$13672 + assign $1\core_core_core_msr$next[63:0]$13555 $3\core_core_core_msr$next[63:0]$13673 + assign $1\core_core_core_oe$next[0:0]$13556 $3\core_core_core_oe$next[0:0]$13674 + assign $1\core_core_core_oe_ok$next[0:0]$13557 $3\core_core_core_oe_ok$next[0:0]$13675 + assign $1\core_core_core_rc$next[0:0]$13558 $3\core_core_core_rc$next[0:0]$13676 + assign $1\core_core_core_rc_ok$next[0:0]$13559 $3\core_core_core_rc_ok$next[0:0]$13677 + assign $1\core_core_core_trapaddr$next[12:0]$13560 $3\core_core_core_trapaddr$next[12:0]$13678 + assign $1\core_core_core_traptype$next[7:0]$13561 $3\core_core_core_traptype$next[7:0]$13679 + assign $1\core_core_cr_in1$next[2:0]$13562 $3\core_core_cr_in1$next[2:0]$13680 + assign $1\core_core_cr_in1_ok$next[0:0]$13563 $3\core_core_cr_in1_ok$next[0:0]$13681 + assign $1\core_core_cr_in2$1$next[2:0]$13564 $3\core_core_cr_in2$1$next[2:0]$13682 + assign $1\core_core_cr_in2$next[2:0]$13565 $3\core_core_cr_in2$next[2:0]$13683 + assign $1\core_core_cr_in2_ok$2$next[0:0]$13566 $3\core_core_cr_in2_ok$2$next[0:0]$13684 + assign $1\core_core_cr_in2_ok$next[0:0]$13567 $3\core_core_cr_in2_ok$next[0:0]$13685 + assign $1\core_core_cr_out$next[2:0]$13568 $3\core_core_cr_out$next[2:0]$13686 + assign $1\core_core_cr_wr_ok$next[0:0]$13569 $3\core_core_cr_wr_ok$next[0:0]$13687 + assign $1\core_core_ea$next[4:0]$13570 $3\core_core_ea$next[4:0]$13688 + assign $1\core_core_fast1$next[2:0]$13571 $3\core_core_fast1$next[2:0]$13689 + assign $1\core_core_fast1_ok$next[0:0]$13572 $3\core_core_fast1_ok$next[0:0]$13690 + assign $1\core_core_fast2$next[2:0]$13573 $3\core_core_fast2$next[2:0]$13691 + assign $1\core_core_fast2_ok$next[0:0]$13574 $3\core_core_fast2_ok$next[0:0]$13692 + assign $1\core_core_fasto1$next[2:0]$13575 $3\core_core_fasto1$next[2:0]$13693 + assign $1\core_core_fasto2$next[2:0]$13576 $3\core_core_fasto2$next[2:0]$13694 + assign $1\core_core_lk$next[0:0]$13577 $3\core_core_lk$next[0:0]$13695 + assign $1\core_core_reg1$next[4:0]$13578 $3\core_core_reg1$next[4:0]$13696 + assign $1\core_core_reg1_ok$next[0:0]$13579 $3\core_core_reg1_ok$next[0:0]$13697 + assign $1\core_core_reg2$next[4:0]$13580 $3\core_core_reg2$next[4:0]$13698 + assign $1\core_core_reg2_ok$next[0:0]$13581 $3\core_core_reg2_ok$next[0:0]$13699 + assign $1\core_core_reg3$next[4:0]$13582 $3\core_core_reg3$next[4:0]$13700 + assign $1\core_core_reg3_ok$next[0:0]$13583 $3\core_core_reg3_ok$next[0:0]$13701 + assign $1\core_core_rego$next[4:0]$13584 $3\core_core_rego$next[4:0]$13702 + assign $1\core_core_spr1$next[9:0]$13585 $3\core_core_spr1$next[9:0]$13703 + assign $1\core_core_spr1_ok$next[0:0]$13586 $3\core_core_spr1_ok$next[0:0]$13704 + assign $1\core_core_spro$next[9:0]$13587 $3\core_core_spro$next[9:0]$13705 + assign $1\core_core_xer_in$next[2:0]$13588 $3\core_core_xer_in$next[2:0]$13706 + assign $1\core_cr_out_ok$next[0:0]$13589 $3\core_cr_out_ok$next[0:0]$13707 + assign $1\core_ea_ok$next[0:0]$13590 $3\core_ea_ok$next[0:0]$13708 + assign $1\core_fasto1_ok$next[0:0]$13591 $3\core_fasto1_ok$next[0:0]$13709 + assign $1\core_fasto2_ok$next[0:0]$13592 $3\core_fasto2_ok$next[0:0]$13710 + assign $1\core_rego_ok$next[0:0]$13593 $3\core_rego_ok$next[0:0]$13711 + assign $1\core_spro_ok$next[0:0]$13594 $3\core_spro_ok$next[0:0]$13712 + assign $1\core_xer_out$next[0:0]$13595 $3\core_xer_out$next[0:0]$13713 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + switch \$59 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $3\core_core_core_is_32bit$next[0:0]$13672 $3\core_core_cr_wr_ok$next[0:0]$13687 $3\core_core_core_cr_wr$next[7:0]$13659 $3\core_core_core_cr_rd_ok$next[0:0]$13658 $3\core_core_core_cr_rd$next[7:0]$13657 $3\core_core_core_trapaddr$next[12:0]$13678 $3\core_core_core_exc_$signal$9$next[0:0]$13666 $3\core_core_core_exc_$signal$8$next[0:0]$13665 $3\core_core_core_exc_$signal$7$next[0:0]$13664 $3\core_core_core_exc_$signal$6$next[0:0]$13663 $3\core_core_core_exc_$signal$5$next[0:0]$13662 $3\core_core_core_exc_$signal$4$next[0:0]$13661 $3\core_core_core_exc_$signal$3$next[0:0]$13660 $3\core_core_core_exc_$signal$next[0:0]$13667 $3\core_core_core_traptype$next[7:0]$13679 $3\core_core_core_input_carry$next[1:0]$13669 $3\core_core_core_oe_ok$next[0:0]$13675 $3\core_core_core_oe$next[0:0]$13674 $3\core_core_core_rc_ok$next[0:0]$13677 $3\core_core_core_rc$next[0:0]$13676 $3\core_core_lk$next[0:0]$13695 $3\core_core_core_fn_unit$next[11:0]$13668 $3\core_core_core_insn_type$next[6:0]$13671 $3\core_core_core_insn$next[31:0]$13670 $3\core_core_core_cia$next[63:0]$13656 $3\core_core_core_msr$next[63:0]$13673 $3\core_cr_out_ok$next[0:0]$13707 $3\core_core_cr_out$next[2:0]$13686 $3\core_core_cr_in2_ok$2$next[0:0]$13684 $3\core_core_cr_in2$1$next[2:0]$13682 $3\core_core_cr_in2_ok$next[0:0]$13685 $3\core_core_cr_in2$next[2:0]$13683 $3\core_core_cr_in1_ok$next[0:0]$13681 $3\core_core_cr_in1$next[2:0]$13680 $3\core_fasto2_ok$next[0:0]$13710 $3\core_core_fasto2$next[2:0]$13694 $3\core_fasto1_ok$next[0:0]$13709 $3\core_core_fasto1$next[2:0]$13693 $3\core_core_fast2_ok$next[0:0]$13692 $3\core_core_fast2$next[2:0]$13691 $3\core_core_fast1_ok$next[0:0]$13690 $3\core_core_fast1$next[2:0]$13689 $3\core_xer_out$next[0:0]$13713 $3\core_core_xer_in$next[2:0]$13706 $3\core_core_spr1_ok$next[0:0]$13704 $3\core_core_spr1$next[9:0]$13703 $3\core_spro_ok$next[0:0]$13712 $3\core_core_spro$next[9:0]$13705 $3\core_core_reg3_ok$next[0:0]$13701 $3\core_core_reg3$next[4:0]$13700 $3\core_core_reg2_ok$next[0:0]$13699 $3\core_core_reg2$next[4:0]$13698 $3\core_core_reg1_ok$next[0:0]$13697 $3\core_core_reg1$next[4:0]$13696 $3\core_ea_ok$next[0:0]$13708 $3\core_core_ea$next[4:0]$13688 $3\core_rego_ok$next[0:0]$13711 $3\core_core_rego$next[4:0]$13702 $3\core_asmcode$next[7:0]$13655 } 330'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\core_asmcode$next[7:0]$13655 \core_asmcode + assign $3\core_core_core_cia$next[63:0]$13656 \core_core_core_cia + assign $3\core_core_core_cr_rd$next[7:0]$13657 \core_core_core_cr_rd + assign $3\core_core_core_cr_rd_ok$next[0:0]$13658 \core_core_core_cr_rd_ok + assign $3\core_core_core_cr_wr$next[7:0]$13659 \core_core_core_cr_wr + assign $3\core_core_core_exc_$signal$3$next[0:0]$13660 \core_core_core_exc_$signal$3 + assign $3\core_core_core_exc_$signal$4$next[0:0]$13661 \core_core_core_exc_$signal$4 + assign $3\core_core_core_exc_$signal$5$next[0:0]$13662 \core_core_core_exc_$signal$5 + assign $3\core_core_core_exc_$signal$6$next[0:0]$13663 \core_core_core_exc_$signal$6 + assign $3\core_core_core_exc_$signal$7$next[0:0]$13664 \core_core_core_exc_$signal$7 + assign $3\core_core_core_exc_$signal$8$next[0:0]$13665 \core_core_core_exc_$signal$8 + assign $3\core_core_core_exc_$signal$9$next[0:0]$13666 \core_core_core_exc_$signal$9 + assign $3\core_core_core_exc_$signal$next[0:0]$13667 \core_core_core_exc_$signal + assign $3\core_core_core_fn_unit$next[11:0]$13668 \core_core_core_fn_unit + assign $3\core_core_core_input_carry$next[1:0]$13669 \core_core_core_input_carry + assign $3\core_core_core_insn$next[31:0]$13670 \core_core_core_insn + assign $3\core_core_core_insn_type$next[6:0]$13671 \core_core_core_insn_type + assign $3\core_core_core_is_32bit$next[0:0]$13672 \core_core_core_is_32bit + assign $3\core_core_core_msr$next[63:0]$13673 \core_core_core_msr + assign $3\core_core_core_oe$next[0:0]$13674 \core_core_core_oe + assign $3\core_core_core_oe_ok$next[0:0]$13675 \core_core_core_oe_ok + assign $3\core_core_core_rc$next[0:0]$13676 \core_core_core_rc + assign $3\core_core_core_rc_ok$next[0:0]$13677 \core_core_core_rc_ok + assign $3\core_core_core_trapaddr$next[12:0]$13678 \core_core_core_trapaddr + assign $3\core_core_core_traptype$next[7:0]$13679 \core_core_core_traptype + assign $3\core_core_cr_in1$next[2:0]$13680 \core_core_cr_in1 + assign $3\core_core_cr_in1_ok$next[0:0]$13681 \core_core_cr_in1_ok + assign $3\core_core_cr_in2$1$next[2:0]$13682 \core_core_cr_in2$1 + assign $3\core_core_cr_in2$next[2:0]$13683 \core_core_cr_in2 + assign $3\core_core_cr_in2_ok$2$next[0:0]$13684 \core_core_cr_in2_ok$2 + assign $3\core_core_cr_in2_ok$next[0:0]$13685 \core_core_cr_in2_ok + assign $3\core_core_cr_out$next[2:0]$13686 \core_core_cr_out + assign $3\core_core_cr_wr_ok$next[0:0]$13687 \core_core_cr_wr_ok + assign $3\core_core_ea$next[4:0]$13688 \core_core_ea + assign $3\core_core_fast1$next[2:0]$13689 \core_core_fast1 + assign $3\core_core_fast1_ok$next[0:0]$13690 \core_core_fast1_ok + assign $3\core_core_fast2$next[2:0]$13691 \core_core_fast2 + assign $3\core_core_fast2_ok$next[0:0]$13692 \core_core_fast2_ok + assign $3\core_core_fasto1$next[2:0]$13693 \core_core_fasto1 + assign $3\core_core_fasto2$next[2:0]$13694 \core_core_fasto2 + assign $3\core_core_lk$next[0:0]$13695 \core_core_lk + assign $3\core_core_reg1$next[4:0]$13696 \core_core_reg1 + assign $3\core_core_reg1_ok$next[0:0]$13697 \core_core_reg1_ok + assign $3\core_core_reg2$next[4:0]$13698 \core_core_reg2 + assign $3\core_core_reg2_ok$next[0:0]$13699 \core_core_reg2_ok + assign $3\core_core_reg3$next[4:0]$13700 \core_core_reg3 + assign $3\core_core_reg3_ok$next[0:0]$13701 \core_core_reg3_ok + assign $3\core_core_rego$next[4:0]$13702 \core_core_rego + assign $3\core_core_spr1$next[9:0]$13703 \core_core_spr1 + assign $3\core_core_spr1_ok$next[0:0]$13704 \core_core_spr1_ok + assign $3\core_core_spro$next[9:0]$13705 \core_core_spro + assign $3\core_core_xer_in$next[2:0]$13706 \core_core_xer_in + assign $3\core_cr_out_ok$next[0:0]$13707 \core_cr_out_ok + assign $3\core_ea_ok$next[0:0]$13708 \core_ea_ok + assign $3\core_fasto1_ok$next[0:0]$13709 \core_fasto1_ok + assign $3\core_fasto2_ok$next[0:0]$13710 \core_fasto2_ok + assign $3\core_rego_ok$next[0:0]$13711 \core_rego_ok + assign $3\core_spro_ok$next[0:0]$13712 \core_spro_ok + assign $3\core_xer_out$next[0:0]$13713 \core_xer_out + end + case + assign $1\core_asmcode$next[7:0]$13537 \core_asmcode + assign $1\core_core_core_cia$next[63:0]$13538 \core_core_core_cia + assign $1\core_core_core_cr_rd$next[7:0]$13539 \core_core_core_cr_rd + assign $1\core_core_core_cr_rd_ok$next[0:0]$13540 \core_core_core_cr_rd_ok + assign $1\core_core_core_cr_wr$next[7:0]$13541 \core_core_core_cr_wr + assign $1\core_core_core_exc_$signal$3$next[0:0]$13542 \core_core_core_exc_$signal$3 + assign $1\core_core_core_exc_$signal$4$next[0:0]$13543 \core_core_core_exc_$signal$4 + assign $1\core_core_core_exc_$signal$5$next[0:0]$13544 \core_core_core_exc_$signal$5 + assign $1\core_core_core_exc_$signal$6$next[0:0]$13545 \core_core_core_exc_$signal$6 + assign $1\core_core_core_exc_$signal$7$next[0:0]$13546 \core_core_core_exc_$signal$7 + assign $1\core_core_core_exc_$signal$8$next[0:0]$13547 \core_core_core_exc_$signal$8 + assign $1\core_core_core_exc_$signal$9$next[0:0]$13548 \core_core_core_exc_$signal$9 + assign $1\core_core_core_exc_$signal$next[0:0]$13549 \core_core_core_exc_$signal + assign $1\core_core_core_fn_unit$next[11:0]$13550 \core_core_core_fn_unit + assign $1\core_core_core_input_carry$next[1:0]$13551 \core_core_core_input_carry + assign $1\core_core_core_insn$next[31:0]$13552 \core_core_core_insn + assign $1\core_core_core_insn_type$next[6:0]$13553 \core_core_core_insn_type + assign $1\core_core_core_is_32bit$next[0:0]$13554 \core_core_core_is_32bit + assign $1\core_core_core_msr$next[63:0]$13555 \core_core_core_msr + assign $1\core_core_core_oe$next[0:0]$13556 \core_core_core_oe + assign $1\core_core_core_oe_ok$next[0:0]$13557 \core_core_core_oe_ok + assign $1\core_core_core_rc$next[0:0]$13558 \core_core_core_rc + assign $1\core_core_core_rc_ok$next[0:0]$13559 \core_core_core_rc_ok + assign $1\core_core_core_trapaddr$next[12:0]$13560 \core_core_core_trapaddr + assign $1\core_core_core_traptype$next[7:0]$13561 \core_core_core_traptype + assign $1\core_core_cr_in1$next[2:0]$13562 \core_core_cr_in1 + assign $1\core_core_cr_in1_ok$next[0:0]$13563 \core_core_cr_in1_ok + assign $1\core_core_cr_in2$1$next[2:0]$13564 \core_core_cr_in2$1 + assign $1\core_core_cr_in2$next[2:0]$13565 \core_core_cr_in2 + assign $1\core_core_cr_in2_ok$2$next[0:0]$13566 \core_core_cr_in2_ok$2 + assign $1\core_core_cr_in2_ok$next[0:0]$13567 \core_core_cr_in2_ok + assign $1\core_core_cr_out$next[2:0]$13568 \core_core_cr_out + assign $1\core_core_cr_wr_ok$next[0:0]$13569 \core_core_cr_wr_ok + assign $1\core_core_ea$next[4:0]$13570 \core_core_ea + assign $1\core_core_fast1$next[2:0]$13571 \core_core_fast1 + assign $1\core_core_fast1_ok$next[0:0]$13572 \core_core_fast1_ok + assign $1\core_core_fast2$next[2:0]$13573 \core_core_fast2 + assign $1\core_core_fast2_ok$next[0:0]$13574 \core_core_fast2_ok + assign $1\core_core_fasto1$next[2:0]$13575 \core_core_fasto1 + assign $1\core_core_fasto2$next[2:0]$13576 \core_core_fasto2 + assign $1\core_core_lk$next[0:0]$13577 \core_core_lk + assign $1\core_core_reg1$next[4:0]$13578 \core_core_reg1 + assign $1\core_core_reg1_ok$next[0:0]$13579 \core_core_reg1_ok + assign $1\core_core_reg2$next[4:0]$13580 \core_core_reg2 + assign $1\core_core_reg2_ok$next[0:0]$13581 \core_core_reg2_ok + assign $1\core_core_reg3$next[4:0]$13582 \core_core_reg3 + assign $1\core_core_reg3_ok$next[0:0]$13583 \core_core_reg3_ok + assign $1\core_core_rego$next[4:0]$13584 \core_core_rego + assign $1\core_core_spr1$next[9:0]$13585 \core_core_spr1 + assign $1\core_core_spr1_ok$next[0:0]$13586 \core_core_spr1_ok + assign $1\core_core_spro$next[9:0]$13587 \core_core_spro + assign $1\core_core_xer_in$next[2:0]$13588 \core_core_xer_in + assign $1\core_cr_out_ok$next[0:0]$13589 \core_cr_out_ok + assign $1\core_ea_ok$next[0:0]$13590 \core_ea_ok + assign $1\core_fasto1_ok$next[0:0]$13591 \core_fasto1_ok + assign $1\core_fasto2_ok$next[0:0]$13592 \core_fasto2_ok + assign $1\core_rego_ok$next[0:0]$13593 \core_rego_ok + assign $1\core_spro_ok$next[0:0]$13594 \core_spro_ok + assign $1\core_xer_out$next[0:0]$13595 \core_xer_out + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $4\core_rego_ok$next[0:0]$13739 1'0 + assign $4\core_ea_ok$next[0:0]$13736 1'0 + assign $4\core_core_reg1_ok$next[0:0]$13731 1'0 + assign $4\core_core_reg2_ok$next[0:0]$13732 1'0 + assign $4\core_core_reg3_ok$next[0:0]$13733 1'0 + assign $4\core_spro_ok$next[0:0]$13740 1'0 + assign $4\core_core_spr1_ok$next[0:0]$13734 1'0 + assign $4\core_core_fast1_ok$next[0:0]$13729 1'0 + assign $4\core_core_fast2_ok$next[0:0]$13730 1'0 + assign $4\core_fasto1_ok$next[0:0]$13737 1'0 + assign $4\core_fasto2_ok$next[0:0]$13738 1'0 + assign $4\core_core_cr_in1_ok$next[0:0]$13725 1'0 + assign $4\core_core_cr_in2_ok$next[0:0]$13727 1'0 + assign $4\core_core_cr_in2_ok$2$next[0:0]$13726 1'0 + assign $4\core_cr_out_ok$next[0:0]$13735 1'0 + assign $4\core_core_core_rc_ok$next[0:0]$13724 1'0 + assign $4\core_core_core_oe_ok$next[0:0]$13723 1'0 + assign $4\core_core_core_exc_$signal$next[0:0]$13722 1'0 + assign $4\core_core_core_exc_$signal$3$next[0:0]$13715 1'0 + assign $4\core_core_core_exc_$signal$4$next[0:0]$13716 1'0 + assign $4\core_core_core_exc_$signal$5$next[0:0]$13717 1'0 + assign $4\core_core_core_exc_$signal$6$next[0:0]$13718 1'0 + assign $4\core_core_core_exc_$signal$7$next[0:0]$13719 1'0 + assign $4\core_core_core_exc_$signal$8$next[0:0]$13720 1'0 + assign $4\core_core_core_exc_$signal$9$next[0:0]$13721 1'0 + assign $4\core_core_core_cr_rd_ok$next[0:0]$13714 1'0 + assign $4\core_core_cr_wr_ok$next[0:0]$13728 1'0 + case + assign $4\core_core_core_cr_rd_ok$next[0:0]$13714 $1\core_core_core_cr_rd_ok$next[0:0]$13540 + assign $4\core_core_core_exc_$signal$3$next[0:0]$13715 $1\core_core_core_exc_$signal$3$next[0:0]$13542 + assign $4\core_core_core_exc_$signal$4$next[0:0]$13716 $1\core_core_core_exc_$signal$4$next[0:0]$13543 + assign $4\core_core_core_exc_$signal$5$next[0:0]$13717 $1\core_core_core_exc_$signal$5$next[0:0]$13544 + assign $4\core_core_core_exc_$signal$6$next[0:0]$13718 $1\core_core_core_exc_$signal$6$next[0:0]$13545 + assign $4\core_core_core_exc_$signal$7$next[0:0]$13719 $1\core_core_core_exc_$signal$7$next[0:0]$13546 + assign $4\core_core_core_exc_$signal$8$next[0:0]$13720 $1\core_core_core_exc_$signal$8$next[0:0]$13547 + assign $4\core_core_core_exc_$signal$9$next[0:0]$13721 $1\core_core_core_exc_$signal$9$next[0:0]$13548 + assign $4\core_core_core_exc_$signal$next[0:0]$13722 $1\core_core_core_exc_$signal$next[0:0]$13549 + assign $4\core_core_core_oe_ok$next[0:0]$13723 $1\core_core_core_oe_ok$next[0:0]$13557 + assign $4\core_core_core_rc_ok$next[0:0]$13724 $1\core_core_core_rc_ok$next[0:0]$13559 + assign $4\core_core_cr_in1_ok$next[0:0]$13725 $1\core_core_cr_in1_ok$next[0:0]$13563 + assign $4\core_core_cr_in2_ok$2$next[0:0]$13726 $1\core_core_cr_in2_ok$2$next[0:0]$13566 + assign $4\core_core_cr_in2_ok$next[0:0]$13727 $1\core_core_cr_in2_ok$next[0:0]$13567 + assign $4\core_core_cr_wr_ok$next[0:0]$13728 $1\core_core_cr_wr_ok$next[0:0]$13569 + assign $4\core_core_fast1_ok$next[0:0]$13729 $1\core_core_fast1_ok$next[0:0]$13572 + assign $4\core_core_fast2_ok$next[0:0]$13730 $1\core_core_fast2_ok$next[0:0]$13574 + assign $4\core_core_reg1_ok$next[0:0]$13731 $1\core_core_reg1_ok$next[0:0]$13579 + assign $4\core_core_reg2_ok$next[0:0]$13732 $1\core_core_reg2_ok$next[0:0]$13581 + assign $4\core_core_reg3_ok$next[0:0]$13733 $1\core_core_reg3_ok$next[0:0]$13583 + assign $4\core_core_spr1_ok$next[0:0]$13734 $1\core_core_spr1_ok$next[0:0]$13586 + assign $4\core_cr_out_ok$next[0:0]$13735 $1\core_cr_out_ok$next[0:0]$13589 + assign $4\core_ea_ok$next[0:0]$13736 $1\core_ea_ok$next[0:0]$13590 + assign $4\core_fasto1_ok$next[0:0]$13737 $1\core_fasto1_ok$next[0:0]$13591 + assign $4\core_fasto2_ok$next[0:0]$13738 $1\core_fasto2_ok$next[0:0]$13592 + assign $4\core_rego_ok$next[0:0]$13739 $1\core_rego_ok$next[0:0]$13593 + assign $4\core_spro_ok$next[0:0]$13740 $1\core_spro_ok$next[0:0]$13594 + end + sync always + update \core_asmcode$next $0\core_asmcode$next[7:0]$13478 + update \core_core_core_cia$next $0\core_core_core_cia$next[63:0]$13479 + update \core_core_core_cr_rd$next $0\core_core_core_cr_rd$next[7:0]$13480 + update \core_core_core_cr_rd_ok$next $0\core_core_core_cr_rd_ok$next[0:0]$13481 + update \core_core_core_cr_wr$next $0\core_core_core_cr_wr$next[7:0]$13482 + update \core_core_core_exc_$signal$3$next $0\core_core_core_exc_$signal$3$next[0:0]$13483 + update \core_core_core_exc_$signal$4$next $0\core_core_core_exc_$signal$4$next[0:0]$13484 + update \core_core_core_exc_$signal$5$next $0\core_core_core_exc_$signal$5$next[0:0]$13485 + update \core_core_core_exc_$signal$6$next $0\core_core_core_exc_$signal$6$next[0:0]$13486 + update \core_core_core_exc_$signal$7$next $0\core_core_core_exc_$signal$7$next[0:0]$13487 + update \core_core_core_exc_$signal$8$next $0\core_core_core_exc_$signal$8$next[0:0]$13488 + update \core_core_core_exc_$signal$9$next $0\core_core_core_exc_$signal$9$next[0:0]$13489 + update \core_core_core_exc_$signal$next $0\core_core_core_exc_$signal$next[0:0]$13490 + update \core_core_core_fn_unit$next $0\core_core_core_fn_unit$next[11:0]$13491 + update \core_core_core_input_carry$next $0\core_core_core_input_carry$next[1:0]$13492 + update \core_core_core_insn$next $0\core_core_core_insn$next[31:0]$13493 + update \core_core_core_insn_type$next $0\core_core_core_insn_type$next[6:0]$13494 + update \core_core_core_is_32bit$next $0\core_core_core_is_32bit$next[0:0]$13495 + update \core_core_core_msr$next $0\core_core_core_msr$next[63:0]$13496 + update \core_core_core_oe$next $0\core_core_core_oe$next[0:0]$13497 + update \core_core_core_oe_ok$next $0\core_core_core_oe_ok$next[0:0]$13498 + update \core_core_core_rc$next $0\core_core_core_rc$next[0:0]$13499 + update \core_core_core_rc_ok$next $0\core_core_core_rc_ok$next[0:0]$13500 + update \core_core_core_trapaddr$next $0\core_core_core_trapaddr$next[12:0]$13501 + update \core_core_core_traptype$next $0\core_core_core_traptype$next[7:0]$13502 + update \core_core_cr_in1$next $0\core_core_cr_in1$next[2:0]$13503 + update \core_core_cr_in1_ok$next $0\core_core_cr_in1_ok$next[0:0]$13504 + update \core_core_cr_in2$1$next $0\core_core_cr_in2$1$next[2:0]$13505 + update \core_core_cr_in2$next $0\core_core_cr_in2$next[2:0]$13506 + update \core_core_cr_in2_ok$2$next $0\core_core_cr_in2_ok$2$next[0:0]$13507 + update \core_core_cr_in2_ok$next $0\core_core_cr_in2_ok$next[0:0]$13508 + update \core_core_cr_out$next $0\core_core_cr_out$next[2:0]$13509 + update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$13510 + update \core_core_ea$next $0\core_core_ea$next[4:0]$13511 + update \core_core_fast1$next $0\core_core_fast1$next[2:0]$13512 + update \core_core_fast1_ok$next $0\core_core_fast1_ok$next[0:0]$13513 + update \core_core_fast2$next $0\core_core_fast2$next[2:0]$13514 + update \core_core_fast2_ok$next $0\core_core_fast2_ok$next[0:0]$13515 + update \core_core_fasto1$next $0\core_core_fasto1$next[2:0]$13516 + update \core_core_fasto2$next $0\core_core_fasto2$next[2:0]$13517 + update \core_core_lk$next $0\core_core_lk$next[0:0]$13518 + update \core_core_reg1$next $0\core_core_reg1$next[4:0]$13519 + update \core_core_reg1_ok$next $0\core_core_reg1_ok$next[0:0]$13520 + update \core_core_reg2$next $0\core_core_reg2$next[4:0]$13521 + update \core_core_reg2_ok$next $0\core_core_reg2_ok$next[0:0]$13522 + update \core_core_reg3$next $0\core_core_reg3$next[4:0]$13523 + update \core_core_reg3_ok$next $0\core_core_reg3_ok$next[0:0]$13524 + update \core_core_rego$next $0\core_core_rego$next[4:0]$13525 + update \core_core_spr1$next $0\core_core_spr1$next[9:0]$13526 + update \core_core_spr1_ok$next $0\core_core_spr1_ok$next[0:0]$13527 + update \core_core_spro$next $0\core_core_spro$next[9:0]$13528 + update \core_core_xer_in$next $0\core_core_xer_in$next[2:0]$13529 + update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$13530 + update \core_ea_ok$next $0\core_ea_ok$next[0:0]$13531 + update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$13532 + update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$13533 + update \core_rego_ok$next $0\core_rego_ok$next[0:0]$13534 + update \core_spro_ok$next $0\core_spro_ok$next[0:0]$13535 + update \core_xer_out$next $0\core_xer_out$next[0:0]$13536 + end + attribute \src "libresoc.v:186405.3-186413.6" + process $proc$libresoc.v:186405$13741 + assign { } { } + assign { } { } + assign $0\jtag_dmi0__ack_o$next[0:0]$13742 $1\jtag_dmi0__ack_o$next[0:0]$13743 + attribute \src "libresoc.v:186406.5-186406.29" + switch \initial + attribute \src "libresoc.v:186406.9-186406.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_dmi0__ack_o$next[0:0]$13743 1'0 + case + assign $1\jtag_dmi0__ack_o$next[0:0]$13743 \dbg_dmi_ack_o + end + sync always + update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$13742 + end + attribute \src "libresoc.v:186414.3-186422.6" + process $proc$libresoc.v:186414$13744 + assign { } { } + assign { } { } + assign $0\jtag_dmi0__dout$next[63:0]$13745 $1\jtag_dmi0__dout$next[63:0]$13746 + attribute \src "libresoc.v:186415.5-186415.29" + switch \initial + attribute \src "libresoc.v:186415.9-186415.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_dmi0__dout$next[63:0]$13746 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $1\jtag_dmi0__dout$next[63:0]$13746 \dbg_dmi_dout + end + sync always + update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$13745 + end + attribute \src "libresoc.v:186423.3-186431.6" + process $proc$libresoc.v:186423$13747 + assign { } { } + assign { } { } + assign $0\dec2_cur_eint$next[0:0]$13748 $1\dec2_cur_eint$next[0:0]$13749 + attribute \src "libresoc.v:186424.5-186424.29" + switch \initial + attribute \src "libresoc.v:186424.9-186424.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dec2_cur_eint$next[0:0]$13749 1'0 + case + assign $1\dec2_cur_eint$next[0:0]$13749 \xics_icp_core_irq_o + end + sync always + update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$13748 + end + attribute \src "libresoc.v:186432.3-186441.6" + process $proc$libresoc.v:186432$13750 + assign { } { } + assign { } { } + assign $0\delay$next[1:0]$13751 $1\delay$next[1:0]$13752 + attribute \src "libresoc.v:186433.5-186433.29" + switch \initial + attribute \src "libresoc.v:186433.9-186433.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:174" + switch \$21 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\delay$next[1:0]$13752 \$23 [1:0] + case + assign $1\delay$next[1:0]$13752 \delay + end + sync always + update \delay$next $0\delay$next[1:0]$13751 + end + attribute \src "libresoc.v:186442.3-186478.6" + process $proc$libresoc.v:186442$13753 + assign { } { } + assign { } { } + assign { } { } + assign $0\core_raw_insn_i$next[31:0]$13754 $4\core_raw_insn_i$next[31:0]$13758 + attribute \src "libresoc.v:186443.5-186443.29" + switch \initial + attribute \src "libresoc.v:186443.9-186443.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\core_raw_insn_i$next[31:0]$13755 0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\core_raw_insn_i$next[31:0]$13755 $2\core_raw_insn_i$next[31:0]$13756 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\core_raw_insn_i$next[31:0]$13756 \core_raw_insn_i + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\core_raw_insn_i$next[31:0]$13756 \dec2_raw_opcode_in + end + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\core_raw_insn_i$next[31:0]$13755 $3\core_raw_insn_i$next[31:0]$13757 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + switch \$61 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_raw_insn_i$next[31:0]$13757 0 + case + assign $3\core_raw_insn_i$next[31:0]$13757 \core_raw_insn_i + end + case + assign $1\core_raw_insn_i$next[31:0]$13755 \core_raw_insn_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\core_raw_insn_i$next[31:0]$13758 0 + case + assign $4\core_raw_insn_i$next[31:0]$13758 $1\core_raw_insn_i$next[31:0]$13755 + end + sync always + update \core_raw_insn_i$next $0\core_raw_insn_i$next[31:0]$13754 + end + attribute \src "libresoc.v:186479.3-186515.6" + process $proc$libresoc.v:186479$13759 + assign { } { } + assign { } { } + assign { } { } + assign $0\core_bigendian_i$10$next[0:0]$13760 $4\core_bigendian_i$10$next[0:0]$13764 + attribute \src "libresoc.v:186480.5-186480.29" + switch \initial + attribute \src "libresoc.v:186480.9-186480.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\core_bigendian_i$10$next[0:0]$13761 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\core_bigendian_i$10$next[0:0]$13761 $2\core_bigendian_i$10$next[0:0]$13762 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\core_bigendian_i$10$next[0:0]$13762 \core_bigendian_i$10 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\core_bigendian_i$10$next[0:0]$13762 \core_bigendian_i + end + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\core_bigendian_i$10$next[0:0]$13761 $3\core_bigendian_i$10$next[0:0]$13763 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + switch \$63 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_bigendian_i$10$next[0:0]$13763 1'0 + case + assign $3\core_bigendian_i$10$next[0:0]$13763 \core_bigendian_i$10 + end + case + assign $1\core_bigendian_i$10$next[0:0]$13761 \core_bigendian_i$10 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\core_bigendian_i$10$next[0:0]$13764 1'0 + case + assign $4\core_bigendian_i$10$next[0:0]$13764 $1\core_bigendian_i$10$next[0:0]$13761 + end + sync always + update \core_bigendian_i$10$next $0\core_bigendian_i$10$next[0:0]$13760 end - connect \ti_coresync_clk \pll_clk_pll_o - connect \pllclk_rst \rst - connect \pll_18_o \pll_pll_18_o - connect \pll_clk_24_i \clk - connect \pllclk_clk \pll_clk_pll_o -end -attribute \src "libresoc.v:48732.1-52510.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti" -attribute \generator "nMigen" -module \ti - attribute \src "libresoc.v:52242.3-52278.6" - wire $0\bigendian_i$next[0:0]$2136 - attribute \src "libresoc.v:50859.3-50860.39" - wire $0\bigendian_i[0:0] - attribute \src "libresoc.v:51940.3-51952.6" - wire width 4 $0\cia__ren[3:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 8 $0\core_asmcode$next[7:0]$1854 - attribute \src "libresoc.v:50863.3-50864.41" - wire width 8 $0\core_asmcode[7:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 64 $0\core_core_cia$next[63:0]$1855 - attribute \src "libresoc.v:50939.3-50940.43" - wire width 64 $0\core_core_cia[63:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 8 $0\core_core_cr_rd$next[7:0]$1856 - attribute \src "libresoc.v:50983.3-50984.47" - wire width 8 $0\core_core_cr_rd[7:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $0\core_core_cr_rd_ok$next[0:0]$1857 - attribute \src "libresoc.v:50985.3-50986.53" - wire $0\core_core_cr_rd_ok[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 8 $0\core_core_cr_wr$next[7:0]$1858 - attribute \src "libresoc.v:50987.3-50988.47" - wire width 8 $0\core_core_cr_wr[7:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $0\core_core_cr_wr_ok$next[0:0]$1859 - attribute \src "libresoc.v:50989.3-50990.53" - wire $0\core_core_cr_wr_ok[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $0\core_core_exc_$signal$50$next[0:0]$1860 - attribute \src "libresoc.v:50965.3-50966.67" - wire $0\core_core_exc_$signal$50[0:0]$1729 - attribute \src "libresoc.v:48905.7-48905.40" - wire $0\core_core_exc_$signal$50[0:0]$2175 - attribute \src "libresoc.v:52045.3-52167.6" - wire $0\core_core_exc_$signal$51$next[0:0]$1861 - attribute \src "libresoc.v:50967.3-50968.67" - wire $0\core_core_exc_$signal$51[0:0]$1731 - attribute \src "libresoc.v:48909.7-48909.40" - wire $0\core_core_exc_$signal$51[0:0]$2177 - attribute \src "libresoc.v:52045.3-52167.6" - wire $0\core_core_exc_$signal$52$next[0:0]$1862 - attribute \src "libresoc.v:50969.3-50970.67" - wire $0\core_core_exc_$signal$52[0:0]$1733 - attribute \src "libresoc.v:48913.7-48913.40" - wire $0\core_core_exc_$signal$52[0:0]$2179 - attribute \src "libresoc.v:52045.3-52167.6" - wire $0\core_core_exc_$signal$53$next[0:0]$1863 - attribute \src "libresoc.v:50971.3-50972.67" - wire $0\core_core_exc_$signal$53[0:0]$1735 - attribute \src "libresoc.v:48917.7-48917.40" - wire $0\core_core_exc_$signal$53[0:0]$2181 - attribute \src "libresoc.v:52045.3-52167.6" - wire $0\core_core_exc_$signal$54$next[0:0]$1864 - attribute \src "libresoc.v:50973.3-50974.67" - wire $0\core_core_exc_$signal$54[0:0]$1737 - attribute \src "libresoc.v:48921.7-48921.40" - wire $0\core_core_exc_$signal$54[0:0]$2183 - attribute \src "libresoc.v:52045.3-52167.6" - wire $0\core_core_exc_$signal$55$next[0:0]$1865 - attribute \src "libresoc.v:50975.3-50976.67" - wire $0\core_core_exc_$signal$55[0:0]$1739 - attribute \src "libresoc.v:48925.7-48925.40" - wire $0\core_core_exc_$signal$55[0:0]$2185 - attribute \src "libresoc.v:52045.3-52167.6" - wire $0\core_core_exc_$signal$56$next[0:0]$1866 - attribute \src "libresoc.v:50977.3-50978.67" - wire $0\core_core_exc_$signal$56[0:0]$1741 - attribute \src "libresoc.v:48929.7-48929.40" - wire $0\core_core_exc_$signal$56[0:0]$2187 - attribute \src "libresoc.v:52045.3-52167.6" - wire $0\core_core_exc_$signal$next[0:0]$1867 - attribute \src "libresoc.v:50963.3-50964.61" - wire $0\core_core_exc_$signal[0:0]$1727 - attribute \src "libresoc.v:48903.7-48903.37" - wire $0\core_core_exc_$signal[0:0]$2173 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 12 $0\core_core_fn_unit$next[11:0]$1868 - attribute \src "libresoc.v:50945.3-50946.51" - wire width 12 $0\core_core_fn_unit[11:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 2 $0\core_core_input_carry$next[1:0]$1869 - attribute \src "libresoc.v:50959.3-50960.59" - wire width 2 $0\core_core_input_carry[1:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 32 $0\core_core_insn$next[31:0]$1870 - attribute \src "libresoc.v:50941.3-50942.45" - wire width 32 $0\core_core_insn[31:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 7 $0\core_core_insn_type$next[6:0]$1871 - attribute \src "libresoc.v:50943.3-50944.55" - wire width 7 $0\core_core_insn_type[6:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $0\core_core_is_32bit$next[0:0]$1872 - attribute \src "libresoc.v:50991.3-50992.53" - wire $0\core_core_is_32bit[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $0\core_core_lk$next[0:0]$1873 - attribute \src "libresoc.v:50947.3-50948.41" - wire $0\core_core_lk[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 64 $0\core_core_msr$next[63:0]$1874 - attribute \src "libresoc.v:50937.3-50938.43" - wire width 64 $0\core_core_msr[63:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $0\core_core_oe$next[0:0]$1875 - attribute \src "libresoc.v:50953.3-50954.41" - wire $0\core_core_oe[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $0\core_core_oe_ok$next[0:0]$1876 - attribute \src "libresoc.v:50955.3-50956.47" - wire $0\core_core_oe_ok[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $0\core_core_rc$next[0:0]$1877 - attribute \src "libresoc.v:50949.3-50950.41" - wire $0\core_core_rc[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $0\core_core_rc_ok$next[0:0]$1878 - attribute \src "libresoc.v:50951.3-50952.47" - wire $0\core_core_rc_ok[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 13 $0\core_core_trapaddr$next[12:0]$1879 - attribute \src "libresoc.v:50981.3-50982.53" - wire width 13 $0\core_core_trapaddr[12:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 8 $0\core_core_traptype$next[7:0]$1880 - attribute \src "libresoc.v:50961.3-50962.53" - wire width 8 $0\core_core_traptype[7:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 3 $0\core_cr_in1$next[2:0]$1881 - attribute \src "libresoc.v:50919.3-50920.39" - wire width 3 $0\core_cr_in1[2:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $0\core_cr_in1_ok$next[0:0]$1882 - attribute \src "libresoc.v:50921.3-50922.45" - wire $0\core_cr_in1_ok[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 3 $0\core_cr_in2$48$next[2:0]$1883 - attribute \src "libresoc.v:50927.3-50928.47" - wire width 3 $0\core_cr_in2$48[2:0]$1707 - attribute \src "libresoc.v:49090.13-49090.36" - wire width 3 $0\core_cr_in2$48[2:0]$2205 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 3 $0\core_cr_in2$next[2:0]$1884 - attribute \src "libresoc.v:50923.3-50924.39" - wire width 3 $0\core_cr_in2[2:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $0\core_cr_in2_ok$49$next[0:0]$1885 - attribute \src "libresoc.v:50929.3-50930.53" - wire $0\core_cr_in2_ok$49[0:0]$1709 - attribute \src "libresoc.v:49098.7-49098.33" - wire $0\core_cr_in2_ok$49[0:0]$2208 - attribute \src "libresoc.v:52045.3-52167.6" - wire $0\core_cr_in2_ok$next[0:0]$1886 - attribute \src "libresoc.v:50925.3-50926.45" - wire $0\core_cr_in2_ok[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 3 $0\core_cr_out$next[2:0]$1887 - attribute \src "libresoc.v:50931.3-50932.39" - wire width 3 $0\core_cr_out[2:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $0\core_cr_out_ok$next[0:0]$1888 - attribute \src "libresoc.v:50933.3-50934.45" - wire $0\core_cr_out_ok[0:0] - attribute \src "libresoc.v:51551.3-51582.6" - wire width 64 $0\core_dec$next[63:0]$1775 - attribute \src "libresoc.v:50849.3-50850.33" - wire width 64 $0\core_dec[63:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 5 $0\core_ea$next[4:0]$1889 - attribute \src "libresoc.v:50871.3-50872.31" - wire width 5 $0\core_ea[4:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $0\core_ea_ok$next[0:0]$1890 - attribute \src "libresoc.v:50873.3-50874.37" - wire $0\core_ea_ok[0:0] - attribute \src "libresoc.v:51551.3-51582.6" - wire $0\core_eint$next[0:0]$1776 - attribute \src "libresoc.v:51017.3-51018.35" - wire $0\core_eint[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 3 $0\core_fast1$next[2:0]$1891 - attribute \src "libresoc.v:50901.3-50902.37" - wire width 3 $0\core_fast1[2:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $0\core_fast1_ok$next[0:0]$1892 - attribute \src "libresoc.v:50903.3-50904.43" - wire $0\core_fast1_ok[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 3 $0\core_fast2$next[2:0]$1893 - attribute \src "libresoc.v:50905.3-50906.37" - wire width 3 $0\core_fast2[2:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $0\core_fast2_ok$next[0:0]$1894 - attribute \src "libresoc.v:50907.3-50908.43" - wire $0\core_fast2_ok[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 3 $0\core_fasto1$next[2:0]$1895 - attribute \src "libresoc.v:50909.3-50910.39" - wire width 3 $0\core_fasto1[2:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $0\core_fasto1_ok$next[0:0]$1896 - attribute \src "libresoc.v:50911.3-50912.45" - wire $0\core_fasto1_ok[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 3 $0\core_fasto2$next[2:0]$1897 - attribute \src "libresoc.v:50915.3-50916.39" - wire width 3 $0\core_fasto2[2:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $0\core_fasto2_ok$next[0:0]$1898 - attribute \src "libresoc.v:50917.3-50918.45" - wire $0\core_fasto2_ok[0:0] - attribute \src "libresoc.v:51551.3-51582.6" - wire width 64 $0\core_msr$next[63:0]$1777 - attribute \src "libresoc.v:51001.3-51002.33" - wire width 64 $0\core_msr[63:0] - attribute \src "libresoc.v:51551.3-51582.6" - wire width 64 $0\core_pc$next[63:0]$1778 - attribute \src "libresoc.v:50979.3-50980.31" - wire width 64 $0\core_pc[63:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 5 $0\core_reg1$next[4:0]$1899 - attribute \src "libresoc.v:50875.3-50876.35" - wire width 5 $0\core_reg1[4:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $0\core_reg1_ok$next[0:0]$1900 - attribute \src "libresoc.v:50877.3-50878.41" - wire $0\core_reg1_ok[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 5 $0\core_reg2$next[4:0]$1901 - attribute \src "libresoc.v:50879.3-50880.35" - wire width 5 $0\core_reg2[4:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $0\core_reg2_ok$next[0:0]$1902 - attribute \src "libresoc.v:50881.3-50882.41" - wire $0\core_reg2_ok[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 5 $0\core_reg3$next[4:0]$1903 - attribute \src "libresoc.v:50883.3-50884.35" - wire width 5 $0\core_reg3[4:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $0\core_reg3_ok$next[0:0]$1904 - attribute \src "libresoc.v:50885.3-50886.41" - wire $0\core_reg3_ok[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 5 $0\core_rego$next[4:0]$1905 - attribute \src "libresoc.v:50865.3-50866.35" - wire width 5 $0\core_rego[4:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $0\core_rego_ok$next[0:0]$1906 - attribute \src "libresoc.v:50867.3-50868.41" - wire $0\core_rego_ok[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 10 $0\core_spr1$next[9:0]$1907 - attribute \src "libresoc.v:50893.3-50894.35" - wire width 10 $0\core_spr1[9:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $0\core_spr1_ok$next[0:0]$1908 - attribute \src "libresoc.v:50895.3-50896.41" - wire $0\core_spr1_ok[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 10 $0\core_spro$next[9:0]$1909 - attribute \src "libresoc.v:50887.3-50888.35" - wire width 10 $0\core_spro[9:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $0\core_spro_ok$next[0:0]$1910 - attribute \src "libresoc.v:50889.3-50890.41" - wire $0\core_spro_ok[0:0] - attribute \src "libresoc.v:52442.3-52460.6" - wire $0\core_stopped_i[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 3 $0\core_xer_in$next[2:0]$1911 - attribute \src "libresoc.v:50897.3-50898.39" - wire width 3 $0\core_xer_in[2:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $0\core_xer_out$next[0:0]$1912 - attribute \src "libresoc.v:50899.3-50900.41" - wire $0\core_xer_out[0:0] - attribute \src "libresoc.v:50997.3-50998.30" - wire $0\cu_st__rel_o_dly[0:0] - attribute \src "libresoc.v:51697.3-51705.6" - wire $0\d_cr_delay$next[0:0]$1807 - attribute \src "libresoc.v:50913.3-50914.37" - wire $0\d_cr_delay[0:0] - attribute \src "libresoc.v:51658.3-51666.6" - wire $0\d_reg_delay$next[0:0]$1801 - attribute \src "libresoc.v:50935.3-50936.39" - wire $0\d_reg_delay[0:0] - attribute \src "libresoc.v:51736.3-51744.6" - wire $0\d_xer_delay$next[0:0]$1813 - attribute \src "libresoc.v:50891.3-50892.39" - wire $0\d_xer_delay[0:0] - attribute \src "libresoc.v:51974.3-51994.6" - wire width 64 $0\data_i[63:0] - attribute \src "libresoc.v:52461.3-52479.6" - wire $0\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:51716.3-51725.6" - wire $0\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:51706.3-51715.6" - wire width 64 $0\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:51677.3-51686.6" - wire $0\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:51667.3-51676.6" - wire width 64 $0\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:51755.3-51764.6" - wire $0\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:51745.3-51754.6" - wire width 64 $0\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:51493.3-51501.6" - wire width 4 $0\dbg_dmi_addr_i$next[3:0]$1763 - attribute \src "libresoc.v:51015.3-51016.45" - wire width 4 $0\dbg_dmi_addr_i[3:0] - attribute \src "libresoc.v:52011.3-52019.6" - wire width 64 $0\dbg_dmi_din$next[63:0]$1846 - attribute \src "libresoc.v:51009.3-51010.39" - wire width 64 $0\dbg_dmi_din[63:0] - attribute \src "libresoc.v:51502.3-51510.6" - wire $0\dbg_dmi_req_i$next[0:0]$1766 - attribute \src "libresoc.v:51013.3-51014.43" - wire $0\dbg_dmi_req_i[0:0] - attribute \src "libresoc.v:51906.3-51914.6" - wire $0\dbg_dmi_we_i$next[0:0]$1835 - attribute \src "libresoc.v:51011.3-51012.41" - wire $0\dbg_dmi_we_i[0:0] - attribute \src "libresoc.v:51879.3-51894.6" - wire width 64 $0\dec2_cur_dec$next[63:0]$1830 - attribute \src "libresoc.v:50847.3-50848.41" - wire width 64 $0\dec2_cur_dec[63:0] - attribute \src "libresoc.v:52186.3-52194.6" - wire $0\dec2_cur_eint$next[0:0]$2124 - attribute \src "libresoc.v:51003.3-51004.43" - wire $0\dec2_cur_eint[0:0] - attribute \src "libresoc.v:51511.3-51531.6" - wire width 64 $0\dec2_cur_msr$next[63:0]$1769 - attribute \src "libresoc.v:50851.3-50852.41" - wire width 64 $0\dec2_cur_msr[63:0] - attribute \src "libresoc.v:52345.3-52365.6" - wire width 64 $0\dec2_cur_pc$next[63:0]$2145 - attribute \src "libresoc.v:50857.3-50858.39" - wire width 64 $0\dec2_cur_pc[63:0] - attribute \src "libresoc.v:51532.3-51550.6" - wire width 32 $0\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:52195.3-52204.6" - wire width 2 $0\delay$next[1:0]$2127 - attribute \src "libresoc.v:50999.3-51000.27" - wire width 2 $0\delay[1:0] - attribute \src "libresoc.v:51638.3-51647.6" - wire width 5 $0\dmi__addr[4:0] - attribute \src "libresoc.v:51648.3-51657.6" - wire $0\dmi__ren[0:0] - attribute \src "libresoc.v:51795.3-51822.6" - wire width 2 $0\fsm_state$131$next[1:0]$1820 - attribute \src "libresoc.v:50869.3-50870.45" - wire width 2 $0\fsm_state$131[1:0]$1677 - attribute \src "libresoc.v:50009.13-50009.35" - wire width 2 $0\fsm_state$131[1:0]$2254 - attribute \src "libresoc.v:52396.3-52441.6" - wire width 2 $0\fsm_state$next[1:0]$2156 - attribute \src "libresoc.v:50853.3-50854.35" - wire width 2 $0\fsm_state[1:0] - attribute \src "libresoc.v:51687.3-51696.6" - wire width 8 $0\full_rd2__ren[7:0] - attribute \src "libresoc.v:51726.3-51735.6" - wire width 3 $0\full_rd__ren[2:0] - attribute \src "libresoc.v:51583.3-51606.6" - wire width 32 $0\ilatch$next[31:0]$1792 - attribute \src "libresoc.v:50957.3-50958.29" - wire width 32 $0\ilatch[31:0] - attribute \src "libresoc.v:52279.3-52294.6" - wire width 48 $0\imem_a_pc_i[47:0] - attribute \src "libresoc.v:52295.3-52319.6" - wire $0\imem_a_valid_i[0:0] - attribute \src "libresoc.v:52320.3-52344.6" - wire $0\imem_f_valid_i[0:0] - attribute \src "libresoc.v:48733.7-48733.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:51834.3-51848.6" - wire width 3 $0\issue__addr$135[2:0]$1825 - attribute \src "libresoc.v:51765.3-51779.6" - wire width 3 $0\issue__addr[2:0] - attribute \src "libresoc.v:51864.3-51878.6" - wire width 64 $0\issue__data_i[63:0] - attribute \src "libresoc.v:51780.3-51794.6" - wire $0\issue__ren[0:0] - attribute \src "libresoc.v:51849.3-51863.6" - wire $0\issue__wen[0:0] - attribute \src "libresoc.v:51627.3-51637.6" - wire $0\issue_i[0:0] - attribute \src "libresoc.v:51607.3-51626.6" - wire $0\ivalid_i[0:0] - attribute \src "libresoc.v:52168.3-52176.6" - wire $0\jtag_dmi0__ack_o$next[0:0]$2118 - attribute \src "libresoc.v:51007.3-51008.49" - wire $0\jtag_dmi0__ack_o[0:0] - attribute \src "libresoc.v:52177.3-52185.6" - wire width 64 $0\jtag_dmi0__dout$next[63:0]$2121 - attribute \src "libresoc.v:51005.3-51006.47" - wire width 64 $0\jtag_dmi0__dout[63:0] - attribute \src "libresoc.v:51995.3-52010.6" - wire width 4 $0\msr__ren[3:0] - attribute \src "libresoc.v:52366.3-52395.6" - wire $0\msr_read$next[0:0]$2150 - attribute \src "libresoc.v:50855.3-50856.33" - wire $0\msr_read[0:0] - attribute \src "libresoc.v:51823.3-51833.6" - wire width 64 $0\new_dec[63:0] - attribute \src "libresoc.v:51895.3-51905.6" - wire width 64 $0\new_tb[63:0] - attribute \src "libresoc.v:51924.3-51939.6" - wire width 64 $0\pc[63:0] - attribute \src "libresoc.v:52020.3-52044.6" - wire $0\pc_changed$next[0:0]$1849 - attribute \src "libresoc.v:50993.3-50994.37" - wire $0\pc_changed[0:0] - attribute \src "libresoc.v:51915.3-51923.6" - wire $0\pc_ok_delay$next[0:0]$1838 - attribute \src "libresoc.v:50995.3-50996.39" - wire $0\pc_ok_delay[0:0] - attribute \src "libresoc.v:52205.3-52241.6" - wire width 32 $0\raw_insn_i$next[31:0]$2130 - attribute \src "libresoc.v:50861.3-50862.37" - wire width 32 $0\raw_insn_i[31:0] - attribute \src "libresoc.v:51953.3-51973.6" - wire width 4 $0\wen[3:0] - attribute \src "libresoc.v:52242.3-52278.6" - wire $1\bigendian_i$next[0:0]$2137 - attribute \src "libresoc.v:48865.7-48865.25" - wire $1\bigendian_i[0:0] - attribute \src "libresoc.v:51940.3-51952.6" - wire width 4 $1\cia__ren[3:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 8 $1\core_asmcode$next[7:0]$1913 - attribute \src "libresoc.v:48877.13-48877.33" - wire width 8 $1\core_asmcode[7:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 64 $1\core_core_cia$next[63:0]$1914 - attribute \src "libresoc.v:48883.14-48883.50" - wire width 64 $1\core_core_cia[63:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 8 $1\core_core_cr_rd$next[7:0]$1915 - attribute \src "libresoc.v:48887.13-48887.36" - wire width 8 $1\core_core_cr_rd[7:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $1\core_core_cr_rd_ok$next[0:0]$1916 - attribute \src "libresoc.v:48891.7-48891.32" - wire $1\core_core_cr_rd_ok[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 8 $1\core_core_cr_wr$next[7:0]$1917 - attribute \src "libresoc.v:48895.13-48895.36" - wire width 8 $1\core_core_cr_wr[7:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $1\core_core_cr_wr_ok$next[0:0]$1918 - attribute \src "libresoc.v:48899.7-48899.32" - wire $1\core_core_cr_wr_ok[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $1\core_core_exc_$signal$50$next[0:0]$1919 - attribute \src "libresoc.v:52045.3-52167.6" - wire $1\core_core_exc_$signal$51$next[0:0]$1920 - attribute \src "libresoc.v:52045.3-52167.6" - wire $1\core_core_exc_$signal$52$next[0:0]$1921 - attribute \src "libresoc.v:52045.3-52167.6" - wire $1\core_core_exc_$signal$53$next[0:0]$1922 - attribute \src "libresoc.v:52045.3-52167.6" - wire $1\core_core_exc_$signal$54$next[0:0]$1923 - attribute \src "libresoc.v:52045.3-52167.6" - wire $1\core_core_exc_$signal$55$next[0:0]$1924 - attribute \src "libresoc.v:52045.3-52167.6" - wire $1\core_core_exc_$signal$56$next[0:0]$1925 - attribute \src "libresoc.v:52045.3-52167.6" - wire $1\core_core_exc_$signal$next[0:0]$1926 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 12 $1\core_core_fn_unit$next[11:0]$1927 - attribute \src "libresoc.v:48948.14-48948.41" - wire width 12 $1\core_core_fn_unit[11:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 2 $1\core_core_input_carry$next[1:0]$1928 - attribute \src "libresoc.v:48956.13-48956.41" - wire width 2 $1\core_core_input_carry[1:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 32 $1\core_core_insn$next[31:0]$1929 - attribute \src "libresoc.v:48960.14-48960.36" - wire width 32 $1\core_core_insn[31:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 7 $1\core_core_insn_type$next[6:0]$1930 - attribute \src "libresoc.v:49038.13-49038.40" - wire width 7 $1\core_core_insn_type[6:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $1\core_core_is_32bit$next[0:0]$1931 - attribute \src "libresoc.v:49042.7-49042.32" - wire $1\core_core_is_32bit[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $1\core_core_lk$next[0:0]$1932 - attribute \src "libresoc.v:49046.7-49046.26" - wire $1\core_core_lk[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 64 $1\core_core_msr$next[63:0]$1933 - attribute \src "libresoc.v:49050.14-49050.50" - wire width 64 $1\core_core_msr[63:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $1\core_core_oe$next[0:0]$1934 - attribute \src "libresoc.v:49054.7-49054.26" - wire $1\core_core_oe[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $1\core_core_oe_ok$next[0:0]$1935 - attribute \src "libresoc.v:49058.7-49058.29" - wire $1\core_core_oe_ok[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $1\core_core_rc$next[0:0]$1936 - attribute \src "libresoc.v:49062.7-49062.26" - wire $1\core_core_rc[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $1\core_core_rc_ok$next[0:0]$1937 - attribute \src "libresoc.v:49066.7-49066.29" - wire $1\core_core_rc_ok[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 13 $1\core_core_trapaddr$next[12:0]$1938 - attribute \src "libresoc.v:49070.14-49070.43" - wire width 13 $1\core_core_trapaddr[12:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 8 $1\core_core_traptype$next[7:0]$1939 - attribute \src "libresoc.v:49074.13-49074.39" - wire width 8 $1\core_core_traptype[7:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 3 $1\core_cr_in1$next[2:0]$1940 - attribute \src "libresoc.v:49080.13-49080.31" - wire width 3 $1\core_cr_in1[2:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $1\core_cr_in1_ok$next[0:0]$1941 - attribute \src "libresoc.v:49084.7-49084.28" - wire $1\core_cr_in1_ok[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 3 $1\core_cr_in2$48$next[2:0]$1942 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 3 $1\core_cr_in2$next[2:0]$1943 - attribute \src "libresoc.v:49088.13-49088.31" - wire width 3 $1\core_cr_in2[2:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $1\core_cr_in2_ok$49$next[0:0]$1944 - attribute \src "libresoc.v:52045.3-52167.6" - wire $1\core_cr_in2_ok$next[0:0]$1945 - attribute \src "libresoc.v:49096.7-49096.28" - wire $1\core_cr_in2_ok[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 3 $1\core_cr_out$next[2:0]$1946 - attribute \src "libresoc.v:49104.13-49104.31" - wire width 3 $1\core_cr_out[2:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $1\core_cr_out_ok$next[0:0]$1947 - attribute \src "libresoc.v:49108.7-49108.28" - wire $1\core_cr_out_ok[0:0] - attribute \src "libresoc.v:51551.3-51582.6" - wire width 64 $1\core_dec$next[63:0]$1779 - attribute \src "libresoc.v:49112.14-49112.45" - wire width 64 $1\core_dec[63:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 5 $1\core_ea$next[4:0]$1948 - attribute \src "libresoc.v:49116.13-49116.28" - wire width 5 $1\core_ea[4:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $1\core_ea_ok$next[0:0]$1949 - attribute \src "libresoc.v:49120.7-49120.24" - wire $1\core_ea_ok[0:0] - attribute \src "libresoc.v:51551.3-51582.6" - wire $1\core_eint$next[0:0]$1780 - attribute \src "libresoc.v:49124.7-49124.23" - wire $1\core_eint[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 3 $1\core_fast1$next[2:0]$1950 - attribute \src "libresoc.v:49128.13-49128.30" - wire width 3 $1\core_fast1[2:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $1\core_fast1_ok$next[0:0]$1951 - attribute \src "libresoc.v:49132.7-49132.27" - wire $1\core_fast1_ok[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 3 $1\core_fast2$next[2:0]$1952 - attribute \src "libresoc.v:49136.13-49136.30" - wire width 3 $1\core_fast2[2:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $1\core_fast2_ok$next[0:0]$1953 - attribute \src "libresoc.v:49140.7-49140.27" - wire $1\core_fast2_ok[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 3 $1\core_fasto1$next[2:0]$1954 - attribute \src "libresoc.v:49144.13-49144.31" - wire width 3 $1\core_fasto1[2:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $1\core_fasto1_ok$next[0:0]$1955 - attribute \src "libresoc.v:49148.7-49148.28" - wire $1\core_fasto1_ok[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 3 $1\core_fasto2$next[2:0]$1956 - attribute \src "libresoc.v:49152.13-49152.31" - wire width 3 $1\core_fasto2[2:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $1\core_fasto2_ok$next[0:0]$1957 - attribute \src "libresoc.v:49156.7-49156.28" - wire $1\core_fasto2_ok[0:0] - attribute \src "libresoc.v:51551.3-51582.6" - wire width 64 $1\core_msr$next[63:0]$1781 - attribute \src "libresoc.v:49160.14-49160.45" - wire width 64 $1\core_msr[63:0] - attribute \src "libresoc.v:51551.3-51582.6" - wire width 64 $1\core_pc$next[63:0]$1782 - attribute \src "libresoc.v:49164.14-49164.44" - wire width 64 $1\core_pc[63:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 5 $1\core_reg1$next[4:0]$1958 - attribute \src "libresoc.v:49168.13-49168.30" - wire width 5 $1\core_reg1[4:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $1\core_reg1_ok$next[0:0]$1959 - attribute \src "libresoc.v:49172.7-49172.26" - wire $1\core_reg1_ok[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 5 $1\core_reg2$next[4:0]$1960 - attribute \src "libresoc.v:49176.13-49176.30" - wire width 5 $1\core_reg2[4:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $1\core_reg2_ok$next[0:0]$1961 - attribute \src "libresoc.v:49180.7-49180.26" - wire $1\core_reg2_ok[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 5 $1\core_reg3$next[4:0]$1962 - attribute \src "libresoc.v:49184.13-49184.30" - wire width 5 $1\core_reg3[4:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $1\core_reg3_ok$next[0:0]$1963 - attribute \src "libresoc.v:49188.7-49188.26" - wire $1\core_reg3_ok[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 5 $1\core_rego$next[4:0]$1964 - attribute \src "libresoc.v:49192.13-49192.30" - wire width 5 $1\core_rego[4:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $1\core_rego_ok$next[0:0]$1965 - attribute \src "libresoc.v:49196.7-49196.26" - wire $1\core_rego_ok[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 10 $1\core_spr1$next[9:0]$1966 - attribute \src "libresoc.v:49311.13-49311.32" - wire width 10 $1\core_spr1[9:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $1\core_spr1_ok$next[0:0]$1967 - attribute \src "libresoc.v:49315.7-49315.26" - wire $1\core_spr1_ok[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 10 $1\core_spro$next[9:0]$1968 - attribute \src "libresoc.v:49430.13-49430.32" - wire width 10 $1\core_spro[9:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $1\core_spro_ok$next[0:0]$1969 - attribute \src "libresoc.v:49434.7-49434.26" - wire $1\core_spro_ok[0:0] - attribute \src "libresoc.v:52442.3-52460.6" - wire $1\core_stopped_i[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 3 $1\core_xer_in$next[2:0]$1970 - attribute \src "libresoc.v:49442.13-49442.31" - wire width 3 $1\core_xer_in[2:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire $1\core_xer_out$next[0:0]$1971 - attribute \src "libresoc.v:49446.7-49446.26" - wire $1\core_xer_out[0:0] - attribute \src "libresoc.v:49462.7-49462.30" - wire $1\cu_st__rel_o_dly[0:0] - attribute \src "libresoc.v:51697.3-51705.6" - wire $1\d_cr_delay$next[0:0]$1808 - attribute \src "libresoc.v:49468.7-49468.24" - wire $1\d_cr_delay[0:0] - attribute \src "libresoc.v:51658.3-51666.6" - wire $1\d_reg_delay$next[0:0]$1802 - attribute \src "libresoc.v:49472.7-49472.25" - wire $1\d_reg_delay[0:0] - attribute \src "libresoc.v:51736.3-51744.6" - wire $1\d_xer_delay$next[0:0]$1814 - attribute \src "libresoc.v:49476.7-49476.25" - wire $1\d_xer_delay[0:0] - attribute \src "libresoc.v:51974.3-51994.6" - wire width 64 $1\data_i[63:0] - attribute \src "libresoc.v:52461.3-52479.6" - wire $1\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:51716.3-51725.6" - wire $1\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:51706.3-51715.6" - wire width 64 $1\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:51677.3-51686.6" - wire $1\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:51667.3-51676.6" - wire width 64 $1\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:51755.3-51764.6" - wire $1\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:51745.3-51754.6" - wire width 64 $1\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:51493.3-51501.6" - wire width 4 $1\dbg_dmi_addr_i$next[3:0]$1764 - attribute \src "libresoc.v:49514.13-49514.34" - wire width 4 $1\dbg_dmi_addr_i[3:0] - attribute \src "libresoc.v:52011.3-52019.6" - wire width 64 $1\dbg_dmi_din$next[63:0]$1847 - attribute \src "libresoc.v:49518.14-49518.48" - wire width 64 $1\dbg_dmi_din[63:0] - attribute \src "libresoc.v:51502.3-51510.6" - wire $1\dbg_dmi_req_i$next[0:0]$1767 - attribute \src "libresoc.v:49524.7-49524.27" - wire $1\dbg_dmi_req_i[0:0] - attribute \src "libresoc.v:51906.3-51914.6" - wire $1\dbg_dmi_we_i$next[0:0]$1836 - attribute \src "libresoc.v:49528.7-49528.26" - wire $1\dbg_dmi_we_i[0:0] - attribute \src "libresoc.v:51879.3-51894.6" - wire width 64 $1\dec2_cur_dec$next[63:0]$1831 - attribute \src "libresoc.v:49564.14-49564.49" - wire width 64 $1\dec2_cur_dec[63:0] - attribute \src "libresoc.v:52186.3-52194.6" - wire $1\dec2_cur_eint$next[0:0]$2125 - attribute \src "libresoc.v:49568.7-49568.27" - wire $1\dec2_cur_eint[0:0] - attribute \src "libresoc.v:51511.3-51531.6" - wire width 64 $1\dec2_cur_msr$next[63:0]$1770 - attribute \src "libresoc.v:49572.14-49572.49" - wire width 64 $1\dec2_cur_msr[63:0] - attribute \src "libresoc.v:52345.3-52365.6" - wire width 64 $1\dec2_cur_pc$next[63:0]$2146 - attribute \src "libresoc.v:49576.14-49576.48" - wire width 64 $1\dec2_cur_pc[63:0] - attribute \src "libresoc.v:51532.3-51550.6" - wire width 32 $1\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:52195.3-52204.6" - wire width 2 $1\delay$next[1:0]$2128 - attribute \src "libresoc.v:49985.13-49985.25" - wire width 2 $1\delay[1:0] - attribute \src "libresoc.v:51638.3-51647.6" - wire width 5 $1\dmi__addr[4:0] - attribute \src "libresoc.v:51648.3-51657.6" - wire $1\dmi__ren[0:0] - attribute \src "libresoc.v:51795.3-51822.6" - wire width 2 $1\fsm_state$131$next[1:0]$1821 - attribute \src "libresoc.v:52396.3-52441.6" - wire width 2 $1\fsm_state$next[1:0]$2157 - attribute \src "libresoc.v:50007.13-50007.29" - wire width 2 $1\fsm_state[1:0] - attribute \src "libresoc.v:51687.3-51696.6" - wire width 8 $1\full_rd2__ren[7:0] - attribute \src "libresoc.v:51726.3-51735.6" - wire width 3 $1\full_rd__ren[2:0] - attribute \src "libresoc.v:51583.3-51606.6" - wire width 32 $1\ilatch$next[31:0]$1793 - attribute \src "libresoc.v:50259.14-50259.28" - wire width 32 $1\ilatch[31:0] - attribute \src "libresoc.v:52279.3-52294.6" - wire width 48 $1\imem_a_pc_i[47:0] - attribute \src "libresoc.v:52295.3-52319.6" - wire $1\imem_a_valid_i[0:0] - attribute \src "libresoc.v:52320.3-52344.6" - wire $1\imem_f_valid_i[0:0] - attribute \src "libresoc.v:51834.3-51848.6" - wire width 3 $1\issue__addr$135[2:0]$1826 - attribute \src "libresoc.v:51765.3-51779.6" - wire width 3 $1\issue__addr[2:0] - attribute \src "libresoc.v:51864.3-51878.6" - wire width 64 $1\issue__data_i[63:0] - attribute \src "libresoc.v:51780.3-51794.6" - wire $1\issue__ren[0:0] - attribute \src "libresoc.v:51849.3-51863.6" - wire $1\issue__wen[0:0] - attribute \src "libresoc.v:51627.3-51637.6" - wire $1\issue_i[0:0] - attribute \src "libresoc.v:51607.3-51626.6" - wire $1\ivalid_i[0:0] - attribute \src "libresoc.v:52168.3-52176.6" - wire $1\jtag_dmi0__ack_o$next[0:0]$2119 - attribute \src "libresoc.v:50293.7-50293.30" - wire $1\jtag_dmi0__ack_o[0:0] - attribute \src "libresoc.v:52177.3-52185.6" - wire width 64 $1\jtag_dmi0__dout$next[63:0]$2122 - attribute \src "libresoc.v:50301.14-50301.52" - wire width 64 $1\jtag_dmi0__dout[63:0] - attribute \src "libresoc.v:51995.3-52010.6" - wire width 4 $1\msr__ren[3:0] - attribute \src "libresoc.v:52366.3-52395.6" - wire $1\msr_read$next[0:0]$2151 - attribute \src "libresoc.v:50361.7-50361.22" - wire $1\msr_read[0:0] - attribute \src "libresoc.v:51823.3-51833.6" - wire width 64 $1\new_dec[63:0] - attribute \src "libresoc.v:51895.3-51905.6" - wire width 64 $1\new_tb[63:0] - attribute \src "libresoc.v:51924.3-51939.6" - wire width 64 $1\pc[63:0] - attribute \src "libresoc.v:52020.3-52044.6" - wire $1\pc_changed$next[0:0]$1850 - attribute \src "libresoc.v:50389.7-50389.24" - wire $1\pc_changed[0:0] - attribute \src "libresoc.v:51915.3-51923.6" - wire $1\pc_ok_delay$next[0:0]$1839 - attribute \src "libresoc.v:50399.7-50399.25" - wire $1\pc_ok_delay[0:0] - attribute \src "libresoc.v:52205.3-52241.6" - wire width 32 $1\raw_insn_i$next[31:0]$2131 - attribute \src "libresoc.v:50413.14-50413.32" - wire width 32 $1\raw_insn_i[31:0] - attribute \src "libresoc.v:51953.3-51973.6" - wire width 4 $1\wen[3:0] - attribute \src "libresoc.v:52242.3-52278.6" - wire $2\bigendian_i$next[0:0]$2138 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 8 $2\core_asmcode$next[7:0]$1972 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 64 $2\core_core_cia$next[63:0]$1973 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 8 $2\core_core_cr_rd$next[7:0]$1974 - attribute \src "libresoc.v:52045.3-52167.6" - wire $2\core_core_cr_rd_ok$next[0:0]$1975 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 8 $2\core_core_cr_wr$next[7:0]$1976 - attribute \src "libresoc.v:52045.3-52167.6" - wire $2\core_core_cr_wr_ok$next[0:0]$1977 - attribute \src "libresoc.v:52045.3-52167.6" - wire $2\core_core_exc_$signal$50$next[0:0]$1978 - attribute \src "libresoc.v:52045.3-52167.6" - wire $2\core_core_exc_$signal$51$next[0:0]$1979 - attribute \src "libresoc.v:52045.3-52167.6" - wire $2\core_core_exc_$signal$52$next[0:0]$1980 - attribute \src "libresoc.v:52045.3-52167.6" - wire $2\core_core_exc_$signal$53$next[0:0]$1981 - attribute \src "libresoc.v:52045.3-52167.6" - wire $2\core_core_exc_$signal$54$next[0:0]$1982 - attribute \src "libresoc.v:52045.3-52167.6" - wire $2\core_core_exc_$signal$55$next[0:0]$1983 - attribute \src "libresoc.v:52045.3-52167.6" - wire $2\core_core_exc_$signal$56$next[0:0]$1984 - attribute \src "libresoc.v:52045.3-52167.6" - wire $2\core_core_exc_$signal$next[0:0]$1985 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 12 $2\core_core_fn_unit$next[11:0]$1986 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 2 $2\core_core_input_carry$next[1:0]$1987 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 32 $2\core_core_insn$next[31:0]$1988 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 7 $2\core_core_insn_type$next[6:0]$1989 - attribute \src "libresoc.v:52045.3-52167.6" - wire $2\core_core_is_32bit$next[0:0]$1990 - attribute \src "libresoc.v:52045.3-52167.6" - wire $2\core_core_lk$next[0:0]$1991 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 64 $2\core_core_msr$next[63:0]$1992 - attribute \src "libresoc.v:52045.3-52167.6" - wire $2\core_core_oe$next[0:0]$1993 - attribute \src "libresoc.v:52045.3-52167.6" - wire $2\core_core_oe_ok$next[0:0]$1994 - attribute \src "libresoc.v:52045.3-52167.6" - wire $2\core_core_rc$next[0:0]$1995 - attribute \src "libresoc.v:52045.3-52167.6" - wire $2\core_core_rc_ok$next[0:0]$1996 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 13 $2\core_core_trapaddr$next[12:0]$1997 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 8 $2\core_core_traptype$next[7:0]$1998 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 3 $2\core_cr_in1$next[2:0]$1999 - attribute \src "libresoc.v:52045.3-52167.6" - wire $2\core_cr_in1_ok$next[0:0]$2000 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 3 $2\core_cr_in2$48$next[2:0]$2001 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 3 $2\core_cr_in2$next[2:0]$2002 - attribute \src "libresoc.v:52045.3-52167.6" - wire $2\core_cr_in2_ok$49$next[0:0]$2003 - attribute \src "libresoc.v:52045.3-52167.6" - wire $2\core_cr_in2_ok$next[0:0]$2004 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 3 $2\core_cr_out$next[2:0]$2005 - attribute \src "libresoc.v:52045.3-52167.6" - wire $2\core_cr_out_ok$next[0:0]$2006 - attribute \src "libresoc.v:51551.3-51582.6" - wire width 64 $2\core_dec$next[63:0]$1783 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 5 $2\core_ea$next[4:0]$2007 - attribute \src "libresoc.v:52045.3-52167.6" - wire $2\core_ea_ok$next[0:0]$2008 - attribute \src "libresoc.v:51551.3-51582.6" - wire $2\core_eint$next[0:0]$1784 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 3 $2\core_fast1$next[2:0]$2009 - attribute \src "libresoc.v:52045.3-52167.6" - wire $2\core_fast1_ok$next[0:0]$2010 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 3 $2\core_fast2$next[2:0]$2011 - attribute \src "libresoc.v:52045.3-52167.6" - wire $2\core_fast2_ok$next[0:0]$2012 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 3 $2\core_fasto1$next[2:0]$2013 - attribute \src "libresoc.v:52045.3-52167.6" - wire $2\core_fasto1_ok$next[0:0]$2014 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 3 $2\core_fasto2$next[2:0]$2015 - attribute \src "libresoc.v:52045.3-52167.6" - wire $2\core_fasto2_ok$next[0:0]$2016 - attribute \src "libresoc.v:51551.3-51582.6" - wire width 64 $2\core_msr$next[63:0]$1785 - attribute \src "libresoc.v:51551.3-51582.6" - wire width 64 $2\core_pc$next[63:0]$1786 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 5 $2\core_reg1$next[4:0]$2017 - attribute \src "libresoc.v:52045.3-52167.6" - wire $2\core_reg1_ok$next[0:0]$2018 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 5 $2\core_reg2$next[4:0]$2019 - attribute \src "libresoc.v:52045.3-52167.6" - wire $2\core_reg2_ok$next[0:0]$2020 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 5 $2\core_reg3$next[4:0]$2021 - attribute \src "libresoc.v:52045.3-52167.6" - wire $2\core_reg3_ok$next[0:0]$2022 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 5 $2\core_rego$next[4:0]$2023 - attribute \src "libresoc.v:52045.3-52167.6" - wire $2\core_rego_ok$next[0:0]$2024 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 10 $2\core_spr1$next[9:0]$2025 - attribute \src "libresoc.v:52045.3-52167.6" - wire $2\core_spr1_ok$next[0:0]$2026 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 10 $2\core_spro$next[9:0]$2027 - attribute \src "libresoc.v:52045.3-52167.6" - wire $2\core_spro_ok$next[0:0]$2028 - attribute \src "libresoc.v:52442.3-52460.6" - wire $2\core_stopped_i[0:0] - attribute \src "libresoc.v:52045.3-52167.6" - wire width 3 $2\core_xer_in$next[2:0]$2029 - attribute \src "libresoc.v:52045.3-52167.6" - wire $2\core_xer_out$next[0:0]$2030 - attribute \src "libresoc.v:51974.3-51994.6" - wire width 64 $2\data_i[63:0] - attribute \src "libresoc.v:52461.3-52479.6" - wire $2\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:51879.3-51894.6" - wire width 64 $2\dec2_cur_dec$next[63:0]$1832 - attribute \src "libresoc.v:51511.3-51531.6" - wire width 64 $2\dec2_cur_msr$next[63:0]$1771 - attribute \src "libresoc.v:52345.3-52365.6" - wire width 64 $2\dec2_cur_pc$next[63:0]$2147 - attribute \src "libresoc.v:51532.3-51550.6" - wire width 32 $2\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:51795.3-51822.6" - wire width 2 $2\fsm_state$131$next[1:0]$1822 - attribute \src "libresoc.v:52396.3-52441.6" - wire width 2 $2\fsm_state$next[1:0]$2158 - attribute \src "libresoc.v:51583.3-51606.6" - wire width 32 $2\ilatch$next[31:0]$1794 - attribute \src "libresoc.v:52279.3-52294.6" - wire width 48 $2\imem_a_pc_i[47:0] - attribute \src "libresoc.v:52295.3-52319.6" - wire $2\imem_a_valid_i[0:0] - attribute \src "libresoc.v:52320.3-52344.6" - wire $2\imem_f_valid_i[0:0] - attribute \src "libresoc.v:51607.3-51626.6" - wire $2\ivalid_i[0:0] - attribute \src "libresoc.v:51995.3-52010.6" - wire width 4 $2\msr__ren[3:0] - attribute \src "libresoc.v:52366.3-52395.6" - wire $2\msr_read$next[0:0]$2152 - attribute \src "libresoc.v:51924.3-51939.6" - wire width 64 $2\pc[63:0] - attribute \src "libresoc.v:52020.3-52044.6" - wire $2\pc_changed$next[0:0]$1851 - attribute \src "libresoc.v:52205.3-52241.6" - wire width 32 $2\raw_insn_i$next[31:0]$2132 - attribute \src "libresoc.v:51953.3-51973.6" - wire width 4 $2\wen[3:0] - attribute \src "libresoc.v:52242.3-52278.6" - wire $3\bigendian_i$next[0:0]$2139 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 8 $3\core_asmcode$next[7:0]$2031 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 64 $3\core_core_cia$next[63:0]$2032 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 8 $3\core_core_cr_rd$next[7:0]$2033 - attribute \src "libresoc.v:52045.3-52167.6" - wire $3\core_core_cr_rd_ok$next[0:0]$2034 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 8 $3\core_core_cr_wr$next[7:0]$2035 - attribute \src "libresoc.v:52045.3-52167.6" - wire $3\core_core_cr_wr_ok$next[0:0]$2036 - attribute \src "libresoc.v:52045.3-52167.6" - wire $3\core_core_exc_$signal$50$next[0:0]$2037 - attribute \src "libresoc.v:52045.3-52167.6" - wire $3\core_core_exc_$signal$51$next[0:0]$2038 - attribute \src "libresoc.v:52045.3-52167.6" - wire $3\core_core_exc_$signal$52$next[0:0]$2039 - attribute \src "libresoc.v:52045.3-52167.6" - wire $3\core_core_exc_$signal$53$next[0:0]$2040 - attribute \src "libresoc.v:52045.3-52167.6" - wire $3\core_core_exc_$signal$54$next[0:0]$2041 - attribute \src "libresoc.v:52045.3-52167.6" - wire $3\core_core_exc_$signal$55$next[0:0]$2042 - attribute \src "libresoc.v:52045.3-52167.6" - wire $3\core_core_exc_$signal$56$next[0:0]$2043 - attribute \src "libresoc.v:52045.3-52167.6" - wire $3\core_core_exc_$signal$next[0:0]$2044 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 12 $3\core_core_fn_unit$next[11:0]$2045 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 2 $3\core_core_input_carry$next[1:0]$2046 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 32 $3\core_core_insn$next[31:0]$2047 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 7 $3\core_core_insn_type$next[6:0]$2048 - attribute \src "libresoc.v:52045.3-52167.6" - wire $3\core_core_is_32bit$next[0:0]$2049 - attribute \src "libresoc.v:52045.3-52167.6" - wire $3\core_core_lk$next[0:0]$2050 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 64 $3\core_core_msr$next[63:0]$2051 - attribute \src "libresoc.v:52045.3-52167.6" - wire $3\core_core_oe$next[0:0]$2052 - attribute \src "libresoc.v:52045.3-52167.6" - wire $3\core_core_oe_ok$next[0:0]$2053 - attribute \src "libresoc.v:52045.3-52167.6" - wire $3\core_core_rc$next[0:0]$2054 - attribute \src "libresoc.v:52045.3-52167.6" - wire $3\core_core_rc_ok$next[0:0]$2055 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 13 $3\core_core_trapaddr$next[12:0]$2056 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 8 $3\core_core_traptype$next[7:0]$2057 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 3 $3\core_cr_in1$next[2:0]$2058 - attribute \src "libresoc.v:52045.3-52167.6" - wire $3\core_cr_in1_ok$next[0:0]$2059 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 3 $3\core_cr_in2$48$next[2:0]$2060 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 3 $3\core_cr_in2$next[2:0]$2061 - attribute \src "libresoc.v:52045.3-52167.6" - wire $3\core_cr_in2_ok$49$next[0:0]$2062 - attribute \src "libresoc.v:52045.3-52167.6" - wire $3\core_cr_in2_ok$next[0:0]$2063 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 3 $3\core_cr_out$next[2:0]$2064 - attribute \src "libresoc.v:52045.3-52167.6" - wire $3\core_cr_out_ok$next[0:0]$2065 - attribute \src "libresoc.v:51551.3-51582.6" - wire width 64 $3\core_dec$next[63:0]$1787 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 5 $3\core_ea$next[4:0]$2066 - attribute \src "libresoc.v:52045.3-52167.6" - wire $3\core_ea_ok$next[0:0]$2067 - attribute \src "libresoc.v:51551.3-51582.6" - wire $3\core_eint$next[0:0]$1788 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 3 $3\core_fast1$next[2:0]$2068 - attribute \src "libresoc.v:52045.3-52167.6" - wire $3\core_fast1_ok$next[0:0]$2069 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 3 $3\core_fast2$next[2:0]$2070 - attribute \src "libresoc.v:52045.3-52167.6" - wire $3\core_fast2_ok$next[0:0]$2071 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 3 $3\core_fasto1$next[2:0]$2072 - attribute \src "libresoc.v:52045.3-52167.6" - wire $3\core_fasto1_ok$next[0:0]$2073 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 3 $3\core_fasto2$next[2:0]$2074 - attribute \src "libresoc.v:52045.3-52167.6" - wire $3\core_fasto2_ok$next[0:0]$2075 - attribute \src "libresoc.v:51551.3-51582.6" - wire width 64 $3\core_msr$next[63:0]$1789 - attribute \src "libresoc.v:51551.3-51582.6" - wire width 64 $3\core_pc$next[63:0]$1790 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 5 $3\core_reg1$next[4:0]$2076 - attribute \src "libresoc.v:52045.3-52167.6" - wire $3\core_reg1_ok$next[0:0]$2077 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 5 $3\core_reg2$next[4:0]$2078 - attribute \src "libresoc.v:52045.3-52167.6" - wire $3\core_reg2_ok$next[0:0]$2079 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 5 $3\core_reg3$next[4:0]$2080 - attribute \src "libresoc.v:52045.3-52167.6" - wire $3\core_reg3_ok$next[0:0]$2081 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 5 $3\core_rego$next[4:0]$2082 - attribute \src "libresoc.v:52045.3-52167.6" - wire $3\core_rego_ok$next[0:0]$2083 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 10 $3\core_spr1$next[9:0]$2084 - attribute \src "libresoc.v:52045.3-52167.6" - wire $3\core_spr1_ok$next[0:0]$2085 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 10 $3\core_spro$next[9:0]$2086 - attribute \src "libresoc.v:52045.3-52167.6" - wire $3\core_spro_ok$next[0:0]$2087 - attribute \src "libresoc.v:52045.3-52167.6" - wire width 3 $3\core_xer_in$next[2:0]$2088 - attribute \src "libresoc.v:52045.3-52167.6" - wire $3\core_xer_out$next[0:0]$2089 - attribute \src "libresoc.v:51974.3-51994.6" - wire width 64 $3\data_i[63:0] - attribute \src "libresoc.v:51511.3-51531.6" - wire width 64 $3\dec2_cur_msr$next[63:0]$1772 - attribute \src "libresoc.v:52345.3-52365.6" - wire width 64 $3\dec2_cur_pc$next[63:0]$2148 - attribute \src "libresoc.v:52396.3-52441.6" - wire width 2 $3\fsm_state$next[1:0]$2159 - attribute \src "libresoc.v:51583.3-51606.6" - wire width 32 $3\ilatch$next[31:0]$1795 - attribute \src "libresoc.v:52295.3-52319.6" - wire $3\imem_a_valid_i[0:0] - attribute \src "libresoc.v:52320.3-52344.6" - wire $3\imem_f_valid_i[0:0] - attribute \src "libresoc.v:52366.3-52395.6" - wire $3\msr_read$next[0:0]$2153 - attribute \src "libresoc.v:52020.3-52044.6" - wire $3\pc_changed$next[0:0]$1852 - attribute \src "libresoc.v:52205.3-52241.6" - wire width 32 $3\raw_insn_i$next[31:0]$2133 - attribute \src "libresoc.v:51953.3-51973.6" - wire width 4 $3\wen[3:0] - attribute \src "libresoc.v:52242.3-52278.6" - wire $4\bigendian_i$next[0:0]$2140 - attribute \src "libresoc.v:52045.3-52167.6" - wire $4\core_core_cr_rd_ok$next[0:0]$2090 - attribute \src "libresoc.v:52045.3-52167.6" - wire $4\core_core_cr_wr_ok$next[0:0]$2091 - attribute \src "libresoc.v:52045.3-52167.6" - wire $4\core_core_exc_$signal$50$next[0:0]$2092 - attribute \src "libresoc.v:52045.3-52167.6" - wire $4\core_core_exc_$signal$51$next[0:0]$2093 - attribute \src "libresoc.v:52045.3-52167.6" - wire $4\core_core_exc_$signal$52$next[0:0]$2094 - attribute \src "libresoc.v:52045.3-52167.6" - wire $4\core_core_exc_$signal$53$next[0:0]$2095 - attribute \src "libresoc.v:52045.3-52167.6" - wire $4\core_core_exc_$signal$54$next[0:0]$2096 - attribute \src "libresoc.v:52045.3-52167.6" - wire $4\core_core_exc_$signal$55$next[0:0]$2097 - attribute \src "libresoc.v:52045.3-52167.6" - wire $4\core_core_exc_$signal$56$next[0:0]$2098 - attribute \src "libresoc.v:52045.3-52167.6" - wire $4\core_core_exc_$signal$next[0:0]$2099 - attribute \src "libresoc.v:52045.3-52167.6" - wire $4\core_core_oe_ok$next[0:0]$2100 - attribute \src "libresoc.v:52045.3-52167.6" - wire $4\core_core_rc_ok$next[0:0]$2101 - attribute \src "libresoc.v:52045.3-52167.6" - wire $4\core_cr_in1_ok$next[0:0]$2102 - attribute \src "libresoc.v:52045.3-52167.6" - wire $4\core_cr_in2_ok$49$next[0:0]$2103 - attribute \src "libresoc.v:52045.3-52167.6" - wire $4\core_cr_in2_ok$next[0:0]$2104 - attribute \src "libresoc.v:52045.3-52167.6" - wire $4\core_cr_out_ok$next[0:0]$2105 - attribute \src "libresoc.v:52045.3-52167.6" - wire $4\core_ea_ok$next[0:0]$2106 - attribute \src "libresoc.v:52045.3-52167.6" - wire $4\core_fast1_ok$next[0:0]$2107 - attribute \src "libresoc.v:52045.3-52167.6" - wire $4\core_fast2_ok$next[0:0]$2108 - attribute \src "libresoc.v:52045.3-52167.6" - wire $4\core_fasto1_ok$next[0:0]$2109 - attribute \src "libresoc.v:52045.3-52167.6" - wire $4\core_fasto2_ok$next[0:0]$2110 - attribute \src "libresoc.v:52045.3-52167.6" - wire $4\core_reg1_ok$next[0:0]$2111 - attribute \src "libresoc.v:52045.3-52167.6" - wire $4\core_reg2_ok$next[0:0]$2112 - attribute \src "libresoc.v:52045.3-52167.6" - wire $4\core_reg3_ok$next[0:0]$2113 - attribute \src "libresoc.v:52045.3-52167.6" - wire $4\core_rego_ok$next[0:0]$2114 - attribute \src "libresoc.v:52045.3-52167.6" - wire $4\core_spr1_ok$next[0:0]$2115 - attribute \src "libresoc.v:52045.3-52167.6" - wire $4\core_spro_ok$next[0:0]$2116 - attribute \src "libresoc.v:52396.3-52441.6" - wire width 2 $4\fsm_state$next[1:0]$2160 - attribute \src "libresoc.v:52366.3-52395.6" - wire $4\msr_read$next[0:0]$2154 - attribute \src "libresoc.v:52205.3-52241.6" - wire width 32 $4\raw_insn_i$next[31:0]$2134 - attribute \src "libresoc.v:52396.3-52441.6" - wire width 2 $5\fsm_state$next[1:0]$2161 - attribute \src "libresoc.v:50808.19-50808.110" - wire width 65 $add$libresoc.v:50808$1626_Y - attribute \src "libresoc.v:50815.18-50815.107" - wire width 65 $add$libresoc.v:50815$1633_Y - attribute \src "libresoc.v:50790.18-50790.101" - wire $and$libresoc.v:50790$1606_Y - attribute \src "libresoc.v:50794.19-50794.104" - wire $and$libresoc.v:50794$1610_Y - attribute \src "libresoc.v:50798.19-50798.104" - wire $and$libresoc.v:50798$1614_Y - attribute \src "libresoc.v:50814.18-50814.104" - wire $and$libresoc.v:50814$1632_Y - attribute \src "libresoc.v:50823.18-50823.101" - wire $and$libresoc.v:50823$1641_Y - attribute \src "libresoc.v:50824.18-50824.109" - wire width 4 $and$libresoc.v:50824$1642_Y - attribute \src "libresoc.v:50831.18-50831.101" - wire $and$libresoc.v:50831$1649_Y - attribute \src "libresoc.v:50834.18-50834.101" - wire $and$libresoc.v:50834$1652_Y - attribute \src "libresoc.v:50837.18-50837.101" - wire $and$libresoc.v:50837$1655_Y - attribute \src "libresoc.v:50840.18-50840.101" - wire $and$libresoc.v:50840$1658_Y - attribute \src "libresoc.v:50843.18-50843.101" - wire $and$libresoc.v:50843$1661_Y - attribute \src "libresoc.v:50805.19-50805.109" - wire width 64 $extend$libresoc.v:50805$1621_Y - attribute \src "libresoc.v:50806.19-50806.108" - wire width 64 $extend$libresoc.v:50806$1623_Y - attribute \src "libresoc.v:50800.19-50800.111" - wire width 7 $mul$libresoc.v:50800$1616_Y - attribute \src "libresoc.v:50802.19-50802.111" - wire width 7 $mul$libresoc.v:50802$1618_Y - attribute \src "libresoc.v:50795.18-50795.102" - wire $ne$libresoc.v:50795$1611_Y - attribute \src "libresoc.v:50804.19-50804.118" - wire $ne$libresoc.v:50804$1620_Y - attribute \src "libresoc.v:50812.18-50812.102" - wire $ne$libresoc.v:50812$1630_Y - attribute \src "libresoc.v:50791.19-50791.102" - wire $not$libresoc.v:50791$1607_Y - attribute \src "libresoc.v:50792.19-50792.107" - wire $not$libresoc.v:50792$1608_Y - attribute \src "libresoc.v:50793.19-50793.109" - wire $not$libresoc.v:50793$1609_Y - attribute \src "libresoc.v:50796.19-50796.107" - wire $not$libresoc.v:50796$1612_Y - attribute \src "libresoc.v:50797.19-50797.109" - wire $not$libresoc.v:50797$1613_Y - attribute \src "libresoc.v:50799.19-50799.100" - wire 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process $proc$libresoc.v:186516$13765 + assign { } { } + assign { } { } + assign $0\imem_a_pc_i[47:0] $1\imem_a_pc_i[47:0] + attribute \src "libresoc.v:186517.5-186517.29" + switch \initial + attribute \src "libresoc.v:186517.9-186517.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\imem_a_pc_i[47:0] $2\imem_a_pc_i[47:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + switch \$69 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\imem_a_pc_i[47:0] \pc [47:0] + case + assign $2\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 + end + case + assign $1\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 + end + sync always + update \imem_a_pc_i $0\imem_a_pc_i[47:0] + end + attribute \src "libresoc.v:186532.3-186556.6" + process $proc$libresoc.v:186532$13766 + assign { } { } + assign { } { } + assign $0\imem_a_valid_i[0:0] $1\imem_a_valid_i[0:0] + attribute \src "libresoc.v:186533.5-186533.29" + switch \initial + attribute \src "libresoc.v:186533.9-186533.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\imem_a_valid_i[0:0] $2\imem_a_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + switch \$75 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\imem_a_valid_i[0:0] 1'1 + case + assign $2\imem_a_valid_i[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\imem_a_valid_i[0:0] $3\imem_a_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\imem_a_valid_i[0:0] 1'1 + case + assign $3\imem_a_valid_i[0:0] 1'0 + end + case + assign $1\imem_a_valid_i[0:0] 1'0 + end + sync always + update \imem_a_valid_i $0\imem_a_valid_i[0:0] + end + attribute \src "libresoc.v:186557.3-186581.6" + process $proc$libresoc.v:186557$13767 + assign { } { } + assign { } { } + assign $0\imem_f_valid_i[0:0] $1\imem_f_valid_i[0:0] + attribute \src "libresoc.v:186558.5-186558.29" + switch \initial + attribute \src "libresoc.v:186558.9-186558.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\imem_f_valid_i[0:0] $2\imem_f_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + switch \$81 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\imem_f_valid_i[0:0] 1'1 + case + assign $2\imem_f_valid_i[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\imem_f_valid_i[0:0] $3\imem_f_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\imem_f_valid_i[0:0] 1'1 + case + assign $3\imem_f_valid_i[0:0] 1'0 + end + case + assign $1\imem_f_valid_i[0:0] 1'0 + end + sync always + update \imem_f_valid_i $0\imem_f_valid_i[0:0] + end + attribute \src "libresoc.v:186582.3-186602.6" + process $proc$libresoc.v:186582$13768 + assign { } { } + assign { } { } + assign { } { } + assign $0\dec2_cur_pc$next[63:0]$13769 $3\dec2_cur_pc$next[63:0]$13772 + attribute \src "libresoc.v:186583.5-186583.29" + switch \initial + attribute \src "libresoc.v:186583.9-186583.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec2_cur_pc$next[63:0]$13770 $2\dec2_cur_pc$next[63:0]$13771 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + switch \$87 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dec2_cur_pc$next[63:0]$13771 \pc + case + assign $2\dec2_cur_pc$next[63:0]$13771 \dec2_cur_pc + end + case + assign $1\dec2_cur_pc$next[63:0]$13770 \dec2_cur_pc + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dec2_cur_pc$next[63:0]$13772 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dec2_cur_pc$next[63:0]$13772 $1\dec2_cur_pc$next[63:0]$13770 + end + sync always + update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$13769 + end + attribute \src "libresoc.v:186603.3-186632.6" + process $proc$libresoc.v:186603$13773 + assign { } { } + assign { } { } + assign { } { } + assign $0\msr_read$next[0:0]$13774 $4\msr_read$next[0:0]$13778 + attribute \src "libresoc.v:186604.5-186604.29" + switch \initial + attribute \src "libresoc.v:186604.9-186604.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\msr_read$next[0:0]$13775 $2\msr_read$next[0:0]$13776 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + switch \$93 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr_read$next[0:0]$13776 1'0 + case + assign $2\msr_read$next[0:0]$13776 \msr_read + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\msr_read$next[0:0]$13775 $3\msr_read$next[0:0]$13777 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275" + switch \$95 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\msr_read$next[0:0]$13777 1'1 + case + assign $3\msr_read$next[0:0]$13777 \msr_read + end + case + assign $1\msr_read$next[0:0]$13775 \msr_read + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\msr_read$next[0:0]$13778 1'1 + case + assign $4\msr_read$next[0:0]$13778 $1\msr_read$next[0:0]$13775 + end + sync always + update \msr_read$next $0\msr_read$next[0:0]$13774 + end + attribute \src "libresoc.v:186633.3-186678.6" + process $proc$libresoc.v:186633$13779 + assign { } { } + assign { } { } + assign { } { } + assign $0\fsm_state$next[1:0]$13780 $5\fsm_state$next[1:0]$13785 + attribute \src "libresoc.v:186634.5-186634.29" + switch \initial + attribute \src "libresoc.v:186634.9-186634.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\fsm_state$next[1:0]$13781 $2\fsm_state$next[1:0]$13782 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + switch \$101 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fsm_state$next[1:0]$13782 2'01 + case + assign $2\fsm_state$next[1:0]$13782 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\fsm_state$next[1:0]$13781 $3\fsm_state$next[1:0]$13783 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $3\fsm_state$next[1:0]$13783 \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\fsm_state$next[1:0]$13783 2'10 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\fsm_state$next[1:0]$13781 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\fsm_state$next[1:0]$13781 $4\fsm_state$next[1:0]$13784 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + switch \$103 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$next[1:0]$13784 2'00 + case + assign $4\fsm_state$next[1:0]$13784 \fsm_state + end + case + assign $1\fsm_state$next[1:0]$13781 \fsm_state + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fsm_state$next[1:0]$13785 2'00 + case + assign $5\fsm_state$next[1:0]$13785 $1\fsm_state$next[1:0]$13781 + end + sync always + update \fsm_state$next $0\fsm_state$next[1:0]$13780 + end + attribute \src "libresoc.v:186679.3-186697.6" + process $proc$libresoc.v:186679$13786 + assign { } { } + assign { } { } + assign $0\core_stopped_i[0:0] $1\core_stopped_i[0:0] + attribute \src "libresoc.v:186680.5-186680.29" + switch \initial + attribute \src "libresoc.v:186680.9-186680.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\core_stopped_i[0:0] $2\core_stopped_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + switch \$109 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\core_stopped_i[0:0] 1'1 + end + case + assign $1\core_stopped_i[0:0] 1'0 + end + sync always + update \core_stopped_i $0\core_stopped_i[0:0] + end + attribute \src "libresoc.v:186698.3-186716.6" + process $proc$libresoc.v:186698$13787 + assign { } { } + assign { } { } + assign $0\dbg_core_stopped_i[0:0] $1\dbg_core_stopped_i[0:0] + attribute \src "libresoc.v:186699.5-186699.29" + switch \initial + attribute \src "libresoc.v:186699.9-186699.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dbg_core_stopped_i[0:0] $2\dbg_core_stopped_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + switch \$115 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\dbg_core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dbg_core_stopped_i[0:0] 1'1 + end + case + assign $1\dbg_core_stopped_i[0:0] 1'0 + end + sync always + update \dbg_core_stopped_i $0\dbg_core_stopped_i[0:0] + end + connect \$99 $not$libresoc.v:184936$13229_Y + connect \$101 $and$libresoc.v:184937$13230_Y + connect \$103 $not$libresoc.v:184938$13231_Y + connect \$105 $not$libresoc.v:184939$13232_Y + connect \$107 $not$libresoc.v:184940$13233_Y + connect \$109 $and$libresoc.v:184941$13234_Y + connect \$111 $not$libresoc.v:184942$13235_Y + connect \$113 $not$libresoc.v:184943$13236_Y + connect \$115 $and$libresoc.v:184944$13237_Y + connect \$117 $not$libresoc.v:184945$13238_Y + connect \$120 $mul$libresoc.v:184946$13239_Y + connect \$119 $shr$libresoc.v:184947$13240_Y [31:0] + connect \$124 $mul$libresoc.v:184948$13241_Y + connect \$123 $shr$libresoc.v:184949$13242_Y [31:0] + connect \$127 $ne$libresoc.v:184950$13243_Y + connect \$129 $pos$libresoc.v:184951$13245_Y + connect \$131 $pos$libresoc.v:184952$13247_Y + connect \$135 $sub$libresoc.v:184953$13248_Y + connect \$138 $add$libresoc.v:184954$13249_Y + connect \$21 $ne$libresoc.v:184955$13250_Y + connect \$24 $sub$libresoc.v:184956$13251_Y + connect \$26 $or$libresoc.v:184957$13252_Y + connect \$28 $or$libresoc.v:184958$13253_Y + connect \$30 $ne$libresoc.v:184959$13254_Y + connect \$32 $not$libresoc.v:184960$13255_Y + connect \$34 $and$libresoc.v:184961$13256_Y + connect \$37 $add$libresoc.v:184962$13257_Y + connect \$39 $not$libresoc.v:184963$13258_Y + connect \$41 $not$libresoc.v:184964$13259_Y + connect \$43 $not$libresoc.v:184965$13260_Y + connect \$45 $not$libresoc.v:184966$13261_Y + connect \$47 $not$libresoc.v:184967$13262_Y + connect \$49 $not$libresoc.v:184968$13263_Y + connect \$51 $not$libresoc.v:184969$13264_Y + connect \$53 $and$libresoc.v:184970$13265_Y + connect \$56 $and$libresoc.v:184971$13266_Y + connect \$55 $reduce_or$libresoc.v:184972$13267_Y + connect \$59 $not$libresoc.v:184973$13268_Y + connect \$61 $not$libresoc.v:184974$13269_Y + connect \$63 $not$libresoc.v:184975$13270_Y + connect \$65 $not$libresoc.v:184976$13271_Y + connect \$67 $not$libresoc.v:184977$13272_Y + connect \$69 $and$libresoc.v:184978$13273_Y + connect \$71 $not$libresoc.v:184979$13274_Y + connect \$73 $not$libresoc.v:184980$13275_Y + connect \$75 $and$libresoc.v:184981$13276_Y + connect \$77 $not$libresoc.v:184982$13277_Y + connect \$79 $not$libresoc.v:184983$13278_Y + connect \$81 $and$libresoc.v:184984$13279_Y + connect \$83 $not$libresoc.v:184985$13280_Y + connect \$85 $not$libresoc.v:184986$13281_Y + connect \$87 $and$libresoc.v:184987$13282_Y + connect \$89 $not$libresoc.v:184988$13283_Y + connect \$91 $not$libresoc.v:184989$13284_Y + connect \$93 $and$libresoc.v:184990$13285_Y + connect \$95 $not$libresoc.v:184991$13286_Y + connect \$97 $not$libresoc.v:184992$13287_Y + connect \$23 \$24 + connect \$36 \$37 + connect \$134 \$135 + connect \$137 \$138 + connect \dbg_core_dbg_msr \dec2_cur_msr + connect \dbg_core_dbg_pc \pc + connect \dbg_terminate_i \core_core_terminate_o + connect \nia \$37 [63:0] + connect \pc_o \dec2_cur_pc + connect \core_cu_st__go_i \cu_st__rel_o_rise + connect \core_cu_ad__go_i \core_cu_ad__rel_o + connect \cu_st__rel_o_rise \$34 + connect \cu_st__rel_o_dly$next \core_cu_st__rel_o + connect \dec2_bigendian \core_bigendian_i + connect \busy_o \core_corebusy_o + connect \core_coresync_rst \ti_rst + connect \ti_rst \$30 + connect \por_clk \clk + connect { \xics_icp_ics_i_pri \xics_icp_ics_i_src } { \xics_ics_icp_o_pri \xics_ics_icp_o_src } +end +attribute \src "libresoc.v:186740.1-187925.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0" +attribute \generator "nMigen" +module \trap0 + attribute \src "libresoc.v:187470.3-187471.25" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:187468.3-187469.41" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:187828.3-187836.6" + wire $0\alu_l_r_alu$next[0:0]$14092 + attribute \src "libresoc.v:187396.3-187397.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:187651.3-187668.6" + wire width 64 $0\alu_trap0_trap_op__cia$next[63:0]$14018 + attribute \src "libresoc.v:187436.3-187437.61" + wire width 64 $0\alu_trap0_trap_op__cia[63:0] + attribute \src "libresoc.v:187651.3-187668.6" + wire width 12 $0\alu_trap0_trap_op__fn_unit$next[11:0]$14019 + attribute \src "libresoc.v:187430.3-187431.69" + wire width 12 $0\alu_trap0_trap_op__fn_unit[11:0] + attribute \src "libresoc.v:187651.3-187668.6" + wire width 32 $0\alu_trap0_trap_op__insn$next[31:0]$14020 + attribute \src "libresoc.v:187432.3-187433.63" + wire width 32 $0\alu_trap0_trap_op__insn[31:0] + attribute \src "libresoc.v:187651.3-187668.6" + wire width 7 $0\alu_trap0_trap_op__insn_type$next[6:0]$14021 + attribute \src "libresoc.v:187428.3-187429.73" + wire width 7 $0\alu_trap0_trap_op__insn_type[6:0] + attribute \src "libresoc.v:187651.3-187668.6" + wire $0\alu_trap0_trap_op__is_32bit$next[0:0]$14022 + attribute \src "libresoc.v:187438.3-187439.71" + wire $0\alu_trap0_trap_op__is_32bit[0:0] + attribute \src "libresoc.v:187651.3-187668.6" + wire width 8 $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14023 + attribute \src "libresoc.v:187444.3-187445.71" + wire width 8 $0\alu_trap0_trap_op__ldst_exc[7:0] + attribute \src "libresoc.v:187651.3-187668.6" + wire width 64 $0\alu_trap0_trap_op__msr$next[63:0]$14024 + attribute \src "libresoc.v:187434.3-187435.61" + wire width 64 $0\alu_trap0_trap_op__msr[63:0] + attribute \src "libresoc.v:187651.3-187668.6" + wire width 13 $0\alu_trap0_trap_op__trapaddr$next[12:0]$14025 + attribute \src "libresoc.v:187442.3-187443.71" + wire width 13 $0\alu_trap0_trap_op__trapaddr[12:0] + attribute \src "libresoc.v:187651.3-187668.6" + wire width 8 $0\alu_trap0_trap_op__traptype$next[7:0]$14026 + attribute \src "libresoc.v:187440.3-187441.71" + wire width 8 $0\alu_trap0_trap_op__traptype[7:0] + attribute \src "libresoc.v:187819.3-187827.6" + wire $0\alui_l_r_alui$next[0:0]$14089 + attribute \src "libresoc.v:187398.3-187399.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:187669.3-187690.6" + wire width 64 $0\data_r0__o$next[63:0]$14037 + attribute \src "libresoc.v:187424.3-187425.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "libresoc.v:187669.3-187690.6" + wire $0\data_r0__o_ok$next[0:0]$14038 + attribute \src "libresoc.v:187426.3-187427.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "libresoc.v:187691.3-187712.6" + wire width 64 $0\data_r1__fast1$next[63:0]$14045 + attribute \src "libresoc.v:187420.3-187421.45" + wire width 64 $0\data_r1__fast1[63:0] + attribute \src "libresoc.v:187691.3-187712.6" + wire $0\data_r1__fast1_ok$next[0:0]$14046 + attribute \src "libresoc.v:187422.3-187423.51" + wire $0\data_r1__fast1_ok[0:0] + attribute \src "libresoc.v:187713.3-187734.6" + wire width 64 $0\data_r2__fast2$next[63:0]$14053 + attribute \src "libresoc.v:187416.3-187417.45" + wire width 64 $0\data_r2__fast2[63:0] + attribute \src "libresoc.v:187713.3-187734.6" + wire $0\data_r2__fast2_ok$next[0:0]$14054 + attribute \src "libresoc.v:187418.3-187419.51" + wire $0\data_r2__fast2_ok[0:0] + attribute \src "libresoc.v:187735.3-187756.6" + wire width 64 $0\data_r3__nia$next[63:0]$14061 + attribute \src "libresoc.v:187412.3-187413.41" + wire width 64 $0\data_r3__nia[63:0] + attribute \src "libresoc.v:187735.3-187756.6" + wire $0\data_r3__nia_ok$next[0:0]$14062 + attribute \src "libresoc.v:187414.3-187415.47" + wire $0\data_r3__nia_ok[0:0] + attribute \src "libresoc.v:187757.3-187778.6" + wire width 64 $0\data_r4__msr$next[63:0]$14069 + attribute \src "libresoc.v:187408.3-187409.41" + wire width 64 $0\data_r4__msr[63:0] + attribute \src "libresoc.v:187757.3-187778.6" + wire $0\data_r4__msr_ok$next[0:0]$14070 + attribute \src "libresoc.v:187410.3-187411.47" + wire $0\data_r4__msr_ok[0:0] + attribute \src "libresoc.v:187837.3-187846.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:187847.3-187856.6" + wire width 64 $0\dest2_o[63:0] + attribute \src "libresoc.v:187857.3-187866.6" + wire width 64 $0\dest3_o[63:0] + attribute \src "libresoc.v:187867.3-187876.6" + wire width 64 $0\dest4_o[63:0] + attribute \src "libresoc.v:187877.3-187886.6" + wire width 64 $0\dest5_o[63:0] + attribute \src "libresoc.v:186741.7-186741.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:187606.3-187614.6" + wire $0\opc_l_r_opc$next[0:0]$14003 + attribute \src "libresoc.v:187454.3-187455.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:187597.3-187605.6" + wire $0\opc_l_s_opc$next[0:0]$14000 + attribute \src "libresoc.v:187456.3-187457.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:187887.3-187895.6" + wire width 5 $0\prev_wr_go$next[4:0]$14100 + attribute \src "libresoc.v:187466.3-187467.37" + wire width 5 $0\prev_wr_go[4:0] + attribute \src "libresoc.v:187551.3-187560.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:187642.3-187650.6" + wire width 5 $0\req_l_r_req$next[4:0]$14015 + attribute \src "libresoc.v:187446.3-187447.39" + wire width 5 $0\req_l_r_req[4:0] + attribute \src "libresoc.v:187633.3-187641.6" + wire width 5 $0\req_l_s_req$next[4:0]$14012 + attribute \src "libresoc.v:187448.3-187449.39" + wire width 5 $0\req_l_s_req[4:0] + attribute \src "libresoc.v:187570.3-187578.6" + wire $0\rok_l_r_rdok$next[0:0]$13991 + attribute \src "libresoc.v:187462.3-187463.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:187561.3-187569.6" + wire $0\rok_l_s_rdok$next[0:0]$13988 + attribute \src "libresoc.v:187464.3-187465.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:187588.3-187596.6" + wire $0\rst_l_r_rst$next[0:0]$13997 + attribute \src "libresoc.v:187458.3-187459.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:187579.3-187587.6" + wire $0\rst_l_s_rst$next[0:0]$13994 + attribute \src "libresoc.v:187460.3-187461.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:187624.3-187632.6" + wire width 4 $0\src_l_r_src$next[3:0]$14009 + attribute \src "libresoc.v:187450.3-187451.39" + wire width 4 $0\src_l_r_src[3:0] + attribute \src "libresoc.v:187615.3-187623.6" + wire width 4 $0\src_l_s_src$next[3:0]$14006 + attribute \src "libresoc.v:187452.3-187453.39" + wire width 4 $0\src_l_s_src[3:0] + attribute \src "libresoc.v:187779.3-187788.6" + wire width 64 $0\src_r0$next[63:0]$14077 + attribute \src "libresoc.v:187406.3-187407.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:187789.3-187798.6" + wire width 64 $0\src_r1$next[63:0]$14080 + attribute \src "libresoc.v:187404.3-187405.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:187799.3-187808.6" + wire width 64 $0\src_r2$next[63:0]$14083 + attribute \src "libresoc.v:187402.3-187403.29" + wire width 64 $0\src_r2[63:0] + attribute \src "libresoc.v:187809.3-187818.6" + wire width 64 $0\src_r3$next[63:0]$14086 + attribute \src "libresoc.v:187400.3-187401.29" + wire width 64 $0\src_r3[63:0] + attribute \src "libresoc.v:186867.7-186867.24" + wire $1\all_rd_dly[0:0] + attribute \src "libresoc.v:186877.7-186877.26" + wire $1\alu_done_dly[0:0] + attribute \src "libresoc.v:187828.3-187836.6" + wire $1\alu_l_r_alu$next[0:0]$14093 + attribute \src "libresoc.v:186885.7-186885.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "libresoc.v:187651.3-187668.6" + wire width 64 $1\alu_trap0_trap_op__cia$next[63:0]$14027 + attribute \src "libresoc.v:186921.14-186921.59" + wire width 64 $1\alu_trap0_trap_op__cia[63:0] + attribute \src "libresoc.v:187651.3-187668.6" + wire width 12 $1\alu_trap0_trap_op__fn_unit$next[11:0]$14028 + attribute \src "libresoc.v:186938.14-186938.50" + wire width 12 $1\alu_trap0_trap_op__fn_unit[11:0] + attribute \src "libresoc.v:187651.3-187668.6" + wire width 32 $1\alu_trap0_trap_op__insn$next[31:0]$14029 + attribute \src "libresoc.v:186942.14-186942.45" + wire width 32 $1\alu_trap0_trap_op__insn[31:0] + attribute \src "libresoc.v:187651.3-187668.6" + wire width 7 $1\alu_trap0_trap_op__insn_type$next[6:0]$14030 + attribute \src "libresoc.v:187020.13-187020.49" + wire width 7 $1\alu_trap0_trap_op__insn_type[6:0] + attribute \src "libresoc.v:187651.3-187668.6" + wire $1\alu_trap0_trap_op__is_32bit$next[0:0]$14031 + attribute \src "libresoc.v:187024.7-187024.41" + wire $1\alu_trap0_trap_op__is_32bit[0:0] + attribute \src "libresoc.v:187651.3-187668.6" + wire width 8 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14032 + attribute \src "libresoc.v:187028.13-187028.48" + wire width 8 $1\alu_trap0_trap_op__ldst_exc[7:0] + attribute \src "libresoc.v:187651.3-187668.6" + wire width 64 $1\alu_trap0_trap_op__msr$next[63:0]$14033 + attribute \src "libresoc.v:187032.14-187032.59" + wire width 64 $1\alu_trap0_trap_op__msr[63:0] + attribute \src "libresoc.v:187651.3-187668.6" + wire width 13 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14034 + attribute \src "libresoc.v:187036.14-187036.52" + wire width 13 $1\alu_trap0_trap_op__trapaddr[12:0] + attribute \src "libresoc.v:187651.3-187668.6" + wire width 8 $1\alu_trap0_trap_op__traptype$next[7:0]$14035 + attribute \src "libresoc.v:187040.13-187040.48" + wire width 8 $1\alu_trap0_trap_op__traptype[7:0] + attribute \src "libresoc.v:187819.3-187827.6" + wire $1\alui_l_r_alui$next[0:0]$14090 + attribute \src "libresoc.v:187046.7-187046.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "libresoc.v:187669.3-187690.6" + wire width 64 $1\data_r0__o$next[63:0]$14039 + attribute \src "libresoc.v:187078.14-187078.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "libresoc.v:187669.3-187690.6" + wire $1\data_r0__o_ok$next[0:0]$14040 + attribute \src "libresoc.v:187082.7-187082.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "libresoc.v:187691.3-187712.6" + wire width 64 $1\data_r1__fast1$next[63:0]$14047 + attribute \src "libresoc.v:187086.14-187086.51" + wire width 64 $1\data_r1__fast1[63:0] + attribute \src "libresoc.v:187691.3-187712.6" + wire $1\data_r1__fast1_ok$next[0:0]$14048 + attribute \src "libresoc.v:187090.7-187090.31" + wire $1\data_r1__fast1_ok[0:0] + attribute \src "libresoc.v:187713.3-187734.6" + wire width 64 $1\data_r2__fast2$next[63:0]$14055 + attribute \src "libresoc.v:187094.14-187094.51" + wire width 64 $1\data_r2__fast2[63:0] + attribute \src "libresoc.v:187713.3-187734.6" + wire $1\data_r2__fast2_ok$next[0:0]$14056 + attribute \src "libresoc.v:187098.7-187098.31" + wire $1\data_r2__fast2_ok[0:0] + attribute \src "libresoc.v:187735.3-187756.6" + wire width 64 $1\data_r3__nia$next[63:0]$14063 + attribute \src "libresoc.v:187102.14-187102.49" + wire width 64 $1\data_r3__nia[63:0] + attribute \src "libresoc.v:187735.3-187756.6" + wire $1\data_r3__nia_ok$next[0:0]$14064 + attribute \src "libresoc.v:187106.7-187106.29" + wire $1\data_r3__nia_ok[0:0] + attribute \src "libresoc.v:187757.3-187778.6" + wire width 64 $1\data_r4__msr$next[63:0]$14071 + attribute \src "libresoc.v:187110.14-187110.49" + wire width 64 $1\data_r4__msr[63:0] + attribute \src "libresoc.v:187757.3-187778.6" + wire $1\data_r4__msr_ok$next[0:0]$14072 + attribute \src "libresoc.v:187114.7-187114.29" + wire $1\data_r4__msr_ok[0:0] + attribute \src "libresoc.v:187837.3-187846.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "libresoc.v:187847.3-187856.6" + wire width 64 $1\dest2_o[63:0] + attribute \src "libresoc.v:187857.3-187866.6" + wire width 64 $1\dest3_o[63:0] + attribute \src "libresoc.v:187867.3-187876.6" + wire width 64 $1\dest4_o[63:0] + attribute \src "libresoc.v:187877.3-187886.6" + wire width 64 $1\dest5_o[63:0] + attribute \src "libresoc.v:187606.3-187614.6" + wire $1\opc_l_r_opc$next[0:0]$14004 + attribute \src "libresoc.v:187145.7-187145.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "libresoc.v:187597.3-187605.6" + wire $1\opc_l_s_opc$next[0:0]$14001 + attribute \src "libresoc.v:187149.7-187149.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "libresoc.v:187887.3-187895.6" + wire width 5 $1\prev_wr_go$next[4:0]$14101 + attribute \src "libresoc.v:187258.13-187258.31" + wire width 5 $1\prev_wr_go[4:0] + attribute \src "libresoc.v:187551.3-187560.6" + wire $1\req_done[0:0] + attribute \src "libresoc.v:187642.3-187650.6" + wire width 5 $1\req_l_r_req$next[4:0]$14016 + attribute \src "libresoc.v:187266.13-187266.32" + wire width 5 $1\req_l_r_req[4:0] + attribute \src "libresoc.v:187633.3-187641.6" + wire width 5 $1\req_l_s_req$next[4:0]$14013 + attribute \src "libresoc.v:187270.13-187270.32" + wire width 5 $1\req_l_s_req[4:0] + attribute \src "libresoc.v:187570.3-187578.6" + wire $1\rok_l_r_rdok$next[0:0]$13992 + attribute \src "libresoc.v:187282.7-187282.26" + wire $1\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:187561.3-187569.6" + wire $1\rok_l_s_rdok$next[0:0]$13989 + attribute \src "libresoc.v:187286.7-187286.26" + wire $1\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:187588.3-187596.6" + wire $1\rst_l_r_rst$next[0:0]$13998 + attribute \src "libresoc.v:187290.7-187290.25" + wire $1\rst_l_r_rst[0:0] + attribute \src "libresoc.v:187579.3-187587.6" + wire $1\rst_l_s_rst$next[0:0]$13995 + attribute \src "libresoc.v:187294.7-187294.25" + wire $1\rst_l_s_rst[0:0] + attribute \src "libresoc.v:187624.3-187632.6" + wire width 4 $1\src_l_r_src$next[3:0]$14010 + attribute \src "libresoc.v:187310.13-187310.31" + wire width 4 $1\src_l_r_src[3:0] + attribute \src "libresoc.v:187615.3-187623.6" + wire width 4 $1\src_l_s_src$next[3:0]$14007 + attribute \src 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attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 10 \dec2_spro - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec2_spro_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" - wire width 13 \dec2_trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" - wire width 8 \dec2_traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104" - wire width 3 \dec2_xer_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" - wire \dec2_xer_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:173" - wire width 2 \delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:173" - wire width 2 \delay$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 \dmi__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \dmi__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \dmi__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 170 \eint_0__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 15 \eint_0__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 171 \eint_1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 16 \eint_1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 172 \eint_2__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 17 \eint_2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - wire width 2 \fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" - wire width 2 \fsm_state$131 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" - wire width 2 \fsm_state$131$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - wire width 2 \fsm_state$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 32 \full_rd2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \full_rd2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 6 \full_rd__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \full_rd__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 179 \gpio_e10__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 25 \gpio_e10__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 26 \gpio_e10__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 24 \gpio_e10__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 180 \gpio_e10__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 181 \gpio_e10__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 182 \gpio_e11__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 28 \gpio_e11__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 29 \gpio_e11__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 27 \gpio_e11__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 183 \gpio_e11__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 184 \gpio_e11__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 185 \gpio_e12__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 31 \gpio_e12__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 32 \gpio_e12__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 30 \gpio_e12__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 186 \gpio_e12__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 187 \gpio_e12__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 188 \gpio_e13__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 34 \gpio_e13__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 35 \gpio_e13__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 33 \gpio_e13__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 189 \gpio_e13__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 190 \gpio_e13__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 191 \gpio_e14__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 37 \gpio_e14__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 38 \gpio_e14__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 36 \gpio_e14__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 192 \gpio_e14__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 193 \gpio_e14__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 194 \gpio_e15__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 40 \gpio_e15__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 41 \gpio_e15__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 39 \gpio_e15__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 195 \gpio_e15__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 196 \gpio_e15__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 173 \gpio_e8__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 19 \gpio_e8__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 20 \gpio_e8__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 18 \gpio_e8__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 174 \gpio_e8__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 175 \gpio_e8__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 176 \gpio_e9__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 22 \gpio_e9__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 23 \gpio_e9__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 21 \gpio_e9__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 177 \gpio_e9__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 178 \gpio_e9__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 197 \gpio_s0__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 43 \gpio_s0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 44 \gpio_s0__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 42 \gpio_s0__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 198 \gpio_s0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 199 \gpio_s0__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 200 \gpio_s1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 46 \gpio_s1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 47 \gpio_s1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 45 \gpio_s1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 201 \gpio_s1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 202 \gpio_s1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 203 \gpio_s2__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 49 \gpio_s2__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 50 \gpio_s2__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 48 \gpio_s2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 204 \gpio_s2__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 205 \gpio_s2__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 206 \gpio_s3__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 52 \gpio_s3__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 53 \gpio_s3__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 51 \gpio_s3__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 207 \gpio_s3__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 208 \gpio_s3__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 209 \gpio_s4__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 55 \gpio_s4__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 56 \gpio_s4__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 54 \gpio_s4__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 210 \gpio_s4__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 211 \gpio_s4__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 212 \gpio_s5__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 58 \gpio_s5__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 59 \gpio_s5__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 57 \gpio_s5__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 213 \gpio_s5__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 214 \gpio_s5__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 215 \gpio_s6__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 61 \gpio_s6__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 62 \gpio_s6__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 60 \gpio_s6__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 216 \gpio_s6__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 217 \gpio_s6__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 218 \gpio_s7__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 64 \gpio_s7__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 65 \gpio_s7__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 63 \gpio_s7__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 219 \gpio_s7__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 220 \gpio_s7__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 9 \ibus__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 45 output 14 \ibus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire output 8 \ibus__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 64 input 13 \ibus__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 10 \ibus__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 8 output 12 \ibus__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire output 11 \ibus__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire output 335 \icp_wb__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 28 input 341 \icp_wb__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 336 \icp_wb__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 output 337 \icp_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 input 338 \icp_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 4 input 342 \icp_wb__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 339 \icp_wb__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 340 \icp_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire output 348 \ics_wb__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 28 input 343 \ics_wb__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 345 \ics_wb__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 output 347 \ics_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 input 349 \ics_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 346 \ics_wb__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 350 \ics_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:197" - wire width 32 \ilatch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:197" - wire width 32 \ilatch$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" - wire width 48 \imem_a_pc_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" - wire \imem_a_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" - wire \imem_f_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33" - wire width 64 \imem_f_instr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" - wire \imem_f_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" - wire \imem_wb_icache_en - attribute \src "libresoc.v:48733.7-48733.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" - wire width 16 input 344 \int_level_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \issue__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \issue__addr$135 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \issue__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \issue__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \issue__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \issue__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:98" - wire \issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" - wire \ivalid_i - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire \jtag_dmi0__ack_o - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire \jtag_dmi0__ack_o$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire width 4 \jtag_dmi0__addr_i - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire width 64 \jtag_dmi0__din - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire width 64 \jtag_dmi0__dout - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire width 64 \jtag_dmi0__dout$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire \jtag_dmi0__req_i - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire \jtag_dmi0__we_i - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire input 331 \jtag_wb__ack - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 29 output 325 \jtag_wb__adr - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 327 \jtag_wb__cyc - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 input 332 \jtag_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 output 330 \jtag_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 326 \jtag_wb__sel - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 328 \jtag_wb__stb - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 329 \jtag_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 66 \mspi0_clk__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 221 \mspi0_clk__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 67 \mspi0_cs_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 222 \mspi0_cs_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 224 \mspi0_miso__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 69 \mspi0_miso__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 68 \mspi0_mosi__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 223 \mspi0_mosi__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 70 \mspi1_clk__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 225 \mspi1_clk__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 71 \mspi1_cs_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 226 \mspi1_cs_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 228 \mspi1_miso__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 73 \mspi1_miso__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 72 \mspi1_mosi__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 227 \mspi1_mosi__pad__o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \msr__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \msr__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:223" - wire \msr_read - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:223" - wire \msr_read$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 77 \mtwi_scl__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 232 \mtwi_scl__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 229 \mtwi_sda__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 75 \mtwi_sda__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 76 \mtwi_sda__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 74 \mtwi_sda__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 230 \mtwi_sda__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 231 \mtwi_sda__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:391" - wire width 64 \new_dec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:408" - wire width 64 \new_tb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" - wire width 64 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:204" - wire width 64 \pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire \pc_changed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire \pc_changed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 7 \pc_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 6 \pc_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:102" - wire width 64 output 5 \pc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:205" - wire \pc_ok_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:205" - wire \pc_ok_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:167" - wire \por_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 78 \pwm_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 233 \pwm_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 79 \pwm_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 234 \pwm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" - wire width 32 \raw_insn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" - wire width 32 \raw_insn_i$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 83 \sd0_clk__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 238 \sd0_clk__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 235 \sd0_cmd__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 81 \sd0_cmd__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 82 \sd0_cmd__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 80 \sd0_cmd__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 236 \sd0_cmd__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 237 \sd0_cmd__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 239 \sd0_data0__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 85 \sd0_data0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 86 \sd0_data0__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 84 \sd0_data0__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 240 \sd0_data0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 241 \sd0_data0__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 242 \sd0_data1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 88 \sd0_data1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 89 \sd0_data1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 87 \sd0_data1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 243 \sd0_data1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 244 \sd0_data1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 245 \sd0_data2__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 91 \sd0_data2__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 92 \sd0_data2__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 90 \sd0_data2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 246 \sd0_data2__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 247 \sd0_data2__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 248 \sd0_data3__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 94 \sd0_data3__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 95 \sd0_data3__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 93 \sd0_data3__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 249 \sd0_data3__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 250 \sd0_data3__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 121 \sdr_a_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 276 \sdr_a_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 139 \sdr_a_10__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 294 \sdr_a_10__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 140 \sdr_a_11__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 295 \sdr_a_11__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 141 \sdr_a_12__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 296 \sdr_a_12__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 122 \sdr_a_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 277 \sdr_a_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 123 \sdr_a_2__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 278 \sdr_a_2__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 124 \sdr_a_3__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 279 \sdr_a_3__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 125 \sdr_a_4__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 280 \sdr_a_4__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 126 \sdr_a_5__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 281 \sdr_a_5__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 127 \sdr_a_6__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 282 \sdr_a_6__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 128 \sdr_a_7__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 283 \sdr_a_7__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 129 \sdr_a_8__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 284 \sdr_a_8__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 130 \sdr_a_9__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 285 \sdr_a_9__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 131 \sdr_ba_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 286 \sdr_ba_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 132 \sdr_ba_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 287 \sdr_ba_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 136 \sdr_cas_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 291 \sdr_cas_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 134 \sdr_cke__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 289 \sdr_cke__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 133 \sdr_clock__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 288 \sdr_clock__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 138 \sdr_cs_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 293 \sdr_cs_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 96 \sdr_dm_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 251 \sdr_dm_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 297 \sdr_dm_1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 143 \sdr_dm_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 144 \sdr_dm_1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 142 \sdr_dm_1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 298 \sdr_dm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 299 \sdr_dm_1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 252 \sdr_dq_0__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 98 \sdr_dq_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 99 \sdr_dq_0__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 97 \sdr_dq_0__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 253 \sdr_dq_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 254 \sdr_dq_0__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 306 \sdr_dq_10__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 152 \sdr_dq_10__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 153 \sdr_dq_10__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 151 \sdr_dq_10__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 307 \sdr_dq_10__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 308 \sdr_dq_10__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 309 \sdr_dq_11__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 155 \sdr_dq_11__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 156 \sdr_dq_11__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 154 \sdr_dq_11__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 310 \sdr_dq_11__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 311 \sdr_dq_11__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 312 \sdr_dq_12__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 158 \sdr_dq_12__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 159 \sdr_dq_12__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 157 \sdr_dq_12__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 313 \sdr_dq_12__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 314 \sdr_dq_12__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 315 \sdr_dq_13__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 161 \sdr_dq_13__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 162 \sdr_dq_13__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 160 \sdr_dq_13__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 316 \sdr_dq_13__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 317 \sdr_dq_13__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 318 \sdr_dq_14__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 164 \sdr_dq_14__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 165 \sdr_dq_14__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 163 \sdr_dq_14__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 319 \sdr_dq_14__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 320 \sdr_dq_14__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 321 \sdr_dq_15__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 167 \sdr_dq_15__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 168 \sdr_dq_15__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 166 \sdr_dq_15__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 322 \sdr_dq_15__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 323 \sdr_dq_15__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 255 \sdr_dq_1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 101 \sdr_dq_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 102 \sdr_dq_1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 100 \sdr_dq_1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 256 \sdr_dq_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 257 \sdr_dq_1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 258 \sdr_dq_2__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 104 \sdr_dq_2__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 105 \sdr_dq_2__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 103 \sdr_dq_2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 259 \sdr_dq_2__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 260 \sdr_dq_2__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 261 \sdr_dq_3__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 107 \sdr_dq_3__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 108 \sdr_dq_3__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 106 \sdr_dq_3__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 262 \sdr_dq_3__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 263 \sdr_dq_3__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 264 \sdr_dq_4__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 110 \sdr_dq_4__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 111 \sdr_dq_4__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 109 \sdr_dq_4__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 265 \sdr_dq_4__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 266 \sdr_dq_4__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 267 \sdr_dq_5__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 113 \sdr_dq_5__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 114 \sdr_dq_5__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 112 \sdr_dq_5__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 268 \sdr_dq_5__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 269 \sdr_dq_5__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 270 \sdr_dq_6__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 116 \sdr_dq_6__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 117 \sdr_dq_6__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 115 \sdr_dq_6__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 271 \sdr_dq_6__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 272 \sdr_dq_6__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 273 \sdr_dq_7__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 119 \sdr_dq_7__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 120 \sdr_dq_7__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 118 \sdr_dq_7__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 274 \sdr_dq_7__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 275 \sdr_dq_7__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 300 \sdr_dq_8__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 146 \sdr_dq_8__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 147 \sdr_dq_8__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 145 \sdr_dq_8__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 301 \sdr_dq_8__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 302 \sdr_dq_8__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 303 \sdr_dq_9__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 149 \sdr_dq_9__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 150 \sdr_dq_9__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 148 \sdr_dq_9__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 304 \sdr_dq_9__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 305 \sdr_dq_9__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 135 \sdr_ras_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 290 \sdr_ras_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 137 \sdr_we_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 292 \sdr_we_n__pad__o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \state_nia_wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172" - wire \ti_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" - wire \xics_icp_core_irq_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" - wire width 8 \xics_icp_ics_i_pri - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" - wire width 4 \xics_icp_ics_i_src - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" - wire width 8 \xics_ics_icp_o_pri - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" - wire width 4 \xics_ics_icp_o_src - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:409" - cell $add $add$libresoc.v:50808$1626 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \issue__data_o - connect \B 1'1 - connect \Y $add$libresoc.v:50808$1626_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:201" - cell $add $add$libresoc.v:50815$1633 + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_trap0_trap_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_trap0_trap_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_trap0_trap_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_trap0_trap_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_trap0_trap_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_trap0_trap_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_trap0_trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_trap0_trap_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \alu_trap0_trap_op__ldst_exc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \alu_trap0_trap_op__ldst_exc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_trap0_trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_trap0_trap_op__msr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \alu_trap0_trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \alu_trap0_trap_op__trapaddr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \alu_trap0_trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \alu_trap0_trap_op__traptype$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \alui_l_s_alui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 32 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 12 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 11 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 15 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 14 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 4 input 13 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 input 22 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 output 21 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 5 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r1__fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r1__fast1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__fast1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r2__fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r2__fast2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__fast2_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r3__nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r3__nia$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__nia_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r4__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r4__msr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r4__msr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r4__msr_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 23 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 26 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 27 \dest3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 29 \dest4_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 31 \dest5_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 24 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 25 \fast2_ok + attribute \src "libresoc.v:186741.7-186741.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 30 \msr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 28 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 20 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \opc_l_q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 6 \oper_i_alu_trap0__cia + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 3 \oper_i_alu_trap0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 4 \oper_i_alu_trap0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 2 \oper_i_alu_trap0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \oper_i_alu_trap0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 10 \oper_i_alu_trap0__ldst_exc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 5 \oper_i_alu_trap0__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 9 \oper_i_alu_trap0__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 8 \oper_i_alu_trap0__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 5 \prev_wr_go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 5 \prev_wr_go$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" + wire \req_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 5 \req_l_q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 5 \req_l_r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 5 \req_l_r_req$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 5 \req_l_s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 5 \req_l_s_req$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + wire \reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" + wire width 4 \reset_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" + wire width 5 \reset_w + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \rok_l_q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rok_l_r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rok_l_r_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rok_l_s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rok_l_s_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rst_l_r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rst_l_r_rst$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rst_l_s_rst$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + wire \rst_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 16 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 17 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 18 \src3_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 19 \src4_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 4 \src_l_q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 \src_l_r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 \src_l_r_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 \src_l_s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 \src_l_s_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r2$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + wire \wr_any + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:187336$13888 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 65 - connect \A \dec2_cur_pc - connect \B 3'100 - connect \Y $add$libresoc.v:50815$1633_Y + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$95 + connect \B \$97 + connect \Y $and$libresoc.v:187336$13888_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $and $and$libresoc.v:50790$1606 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:187337$13889 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$95 - connect \B \$97 - connect \Y $and$libresoc.v:50790$1606_Y + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:187337$13889_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $and $and$libresoc.v:50794$1610 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:187338$13890 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$103 - connect \B \$105 - connect \Y $and$libresoc.v:50794$1610_Y + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:187338$13890_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $and $and$libresoc.v:50798$1614 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:187339$13891 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$109 - connect \B \$111 - connect \Y $and$libresoc.v:50798$1614_Y + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:187339$13891_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:50814$1632 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:187340$13892 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_st__rel_o - connect \B \$21 - connect \Y $and$libresoc.v:50814$1632_Y + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:187340$13892_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $and $and$libresoc.v:50823$1641 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:187341$13893 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$38 - connect \B \$40 - connect \Y $and$libresoc.v:50823$1641_Y + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:187341$13893_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:309" - cell $and $and$libresoc.v:50824$1642 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $and$libresoc.v:187342$13894 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \state_nia_wen - connect \B 1'1 - connect \Y $and$libresoc.v:50824$1642_Y + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \req_l_q_req + connect \B { \$101 \$103 \$105 \$107 \$109 } + connect \Y $and$libresoc.v:187342$13894_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $and $and$libresoc.v:50831$1649 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $and$libresoc.v:187343$13895 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$63 - connect \B \$65 - connect \Y $and$libresoc.v:50831$1649_Y + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$111 + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:187343$13895_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $and $and$libresoc.v:50834$1652 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:187344$13896 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$69 - connect \B \$71 - connect \Y $and$libresoc.v:50834$1652_Y + connect \A \cu_wr__go_i [0] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:187344$13896_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $and $and$libresoc.v:50837$1655 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:187345$13897 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$75 - connect \B \$77 - connect \Y $and$libresoc.v:50837$1655_Y + connect \A \cu_wr__go_i [1] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:187345$13897_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $and $and$libresoc.v:50840$1658 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $and $and$libresoc.v:187346$13898 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$81 - connect \B \$83 - connect \Y $and$libresoc.v:50840$1658_Y + connect \A \$3 + connect \B \$5 + connect \Y $and$libresoc.v:187346$13898_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $and $and$libresoc.v:50843$1661 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:187347$13899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$87 - connect \B \$89 - connect \Y $and$libresoc.v:50843$1661_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - cell $pos $extend$libresoc.v:50805$1621 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \full_rd2__data_o - connect \Y $extend$libresoc.v:50805$1621_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - cell $pos $extend$libresoc.v:50806$1623 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \full_rd__data_o - connect \Y $extend$libresoc.v:50806$1623_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - cell $mul $mul$libresoc.v:50800$1616 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 7 - connect \A \dec2_cur_pc [2] - connect \B 6'100000 - connect \Y $mul$libresoc.v:50800$1616_Y + connect \A \cu_wr__go_i [2] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:187347$13899_Y end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - cell $mul $mul$libresoc.v:50802$1618 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:187348$13900 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 7 - connect \A \dec2_cur_pc [2] - connect \B 6'100000 - connect \Y $mul$libresoc.v:50802$1618_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:174" - cell $ne $ne$libresoc.v:50795$1611 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \delay - connect \B 1'0 - connect \Y $ne$libresoc.v:50795$1611_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:307" - cell $ne $ne$libresoc.v:50804$1620 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \core_core_insn_type - connect \B 7'0000001 - connect \Y $ne$libresoc.v:50804$1620_Y + connect \A \cu_wr__go_i [3] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:187348$13900_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" - cell $ne $ne$libresoc.v:50812$1630 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:187349$13901 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \delay - connect \B \$17 - connect \Y $ne$libresoc.v:50812$1630_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" - cell $not $not$libresoc.v:50791$1607 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \corebusy_o - connect \Y $not$libresoc.v:50791$1607_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $not $not$libresoc.v:50792$1608 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:50792$1608_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $not $not$libresoc.v:50793$1609 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_coresync_rst - connect \Y $not$libresoc.v:50793$1609_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $not $not$libresoc.v:50796$1612 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:50796$1612_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $not $not$libresoc.v:50797$1613 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_coresync_rst - connect \Y $not$libresoc.v:50797$1613_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275" - cell $not $not$libresoc.v:50799$1615 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msr_read - connect \Y $not$libresoc.v:50799$1615_Y + connect \A \cu_wr__go_i [4] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:187349$13901_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:50813$1631 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_st__rel_o_dly - connect \Y $not$libresoc.v:50813$1631_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:206" - cell $not $not$libresoc.v:50816$1634 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pc_i_ok - connect \Y $not$libresoc.v:50816$1634_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" - cell $not $not$libresoc.v:50817$1635 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \corebusy_o - connect \Y $not$libresoc.v:50817$1635_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" - cell $not $not$libresoc.v:50818$1636 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pc_changed - connect \Y $not$libresoc.v:50818$1636_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" - cell $not $not$libresoc.v:50819$1637 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \corebusy_o - connect \Y $not$libresoc.v:50819$1637_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" - cell $not $not$libresoc.v:50820$1638 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pc_changed - connect \Y $not$libresoc.v:50820$1638_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $not $not$libresoc.v:50821$1639 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:50821$1639_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $not $not$libresoc.v:50822$1640 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_coresync_rst - connect \Y $not$libresoc.v:50822$1640_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" - cell $not $not$libresoc.v:50826$1644 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \corebusy_o - connect \Y $not$libresoc.v:50826$1644_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" - cell $not $not$libresoc.v:50827$1645 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \corebusy_o - connect \Y $not$libresoc.v:50827$1645_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" - cell $not $not$libresoc.v:50828$1646 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \corebusy_o - connect \Y $not$libresoc.v:50828$1646_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $not $not$libresoc.v:50829$1647 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:50829$1647_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $not $not$libresoc.v:50830$1648 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_coresync_rst - connect \Y $not$libresoc.v:50830$1648_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $not $not$libresoc.v:50832$1650 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:50832$1650_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $not $not$libresoc.v:50833$1651 + cell $and $and$libresoc.v:187351$13903 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \core_coresync_rst - connect \Y $not$libresoc.v:50833$1651_Y + connect \A \all_rd + connect \B \$13 + connect \Y $and$libresoc.v:187351$13903_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $not $not$libresoc.v:50835$1653 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:187353$13905 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:50835$1653_Y + connect \A \alu_done + connect \B \$17 + connect \Y $and$libresoc.v:187353$13905_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $not $not$libresoc.v:50836$1654 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + cell $and $and$libresoc.v:187354$13906 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_coresync_rst - connect \Y $not$libresoc.v:50836$1654_Y + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_wr__go_i + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$libresoc.v:187354$13906_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $not $not$libresoc.v:50838$1656 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $and$libresoc.v:187356$13908 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:50838$1656_Y + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_wr__rel_o + connect \B \$25 + connect \Y $and$libresoc.v:187356$13908_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $not $not$libresoc.v:50839$1657 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $and$libresoc.v:187359$13911 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \core_coresync_rst - connect \Y $not$libresoc.v:50839$1657_Y + connect \A \cu_busy_o + connect \B \$23 + connect \Y $and$libresoc.v:187359$13911_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $not $not$libresoc.v:50841$1659 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + cell $and $and$libresoc.v:187363$13915 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:50841$1659_Y + connect \A \cu_busy_o + connect \B \rok_l_q_rdok + connect \Y $and$libresoc.v:187363$13915_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $not $not$libresoc.v:50842$1660 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $and $and$libresoc.v:187365$13917 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \core_coresync_rst - connect \Y $not$libresoc.v:50842$1660_Y + connect \A \wr_any + connect \B \$39 + connect \Y $and$libresoc.v:187365$13917_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275" - cell $not $not$libresoc.v:50844$1662 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$libresoc.v:187366$13918 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msr_read - connect \Y $not$libresoc.v:50844$1662_Y + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \req_l_q_req + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:187366$13918_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $not $not$libresoc.v:50845$1663 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$libresoc.v:187368$13920 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:50845$1663_Y + connect \A \$41 + connect \B \$45 + connect \Y $and$libresoc.v:187368$13920_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - cell $not $not$libresoc.v:50846$1664 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:187370$13922 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \core_coresync_rst - connect \Y $not$libresoc.v:50846$1664_Y + connect \A \$49 + connect \B \alu_trap0_n_ready_i + connect \Y $and$libresoc.v:187370$13922_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" - cell $or $or$libresoc.v:50810$1628 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:187371$13923 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A 1'0 - connect \B \dbg_core_rst_o - connect \Y $or$libresoc.v:50810$1628_Y + connect \A \$51 + connect \B \alu_trap0_n_valid_o + connect \Y $and$libresoc.v:187371$13923_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" - cell $or $or$libresoc.v:50811$1629 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:187372$13924 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$15 - connect \B \rst - connect \Y $or$libresoc.v:50811$1629_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - cell $pos $pos$libresoc.v:50805$1622 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:50805$1621_Y - connect \Y $pos$libresoc.v:50805$1622_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - cell $pos $pos$libresoc.v:50806$1624 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:50806$1623_Y - connect \Y $pos$libresoc.v:50806$1624_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:50825$1643 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \$45 - connect \Y $reduce_or$libresoc.v:50825$1643_Y - end - attribute \src "libresoc.v:50801.19-50801.42" - cell $shr $shr$libresoc.v:50801$1617 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 64 - connect \A \imem_f_instr_o - connect \B \$118 - connect \Y $shr$libresoc.v:50801$1617_Y - end - attribute \src "libresoc.v:50803.19-50803.42" - cell $shr $shr$libresoc.v:50803$1619 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 64 - connect \A \imem_f_instr_o - connect \B \$122 - connect \Y $shr$libresoc.v:50803$1619_Y + connect \A \$53 + connect \B \cu_busy_o + connect \Y $and$libresoc.v:187372$13924_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:393" - cell $sub $sub$libresoc.v:50807$1625 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + cell $and $and$libresoc.v:187377$13929 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \issue__data_o - connect \B 1'1 - connect \Y $sub$libresoc.v:50807$1625_Y + parameter \Y_WIDTH 1 + connect \A \alu_trap0_n_valid_o + connect \B \cu_busy_o + connect \Y $and$libresoc.v:187377$13929_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" - cell $sub $sub$libresoc.v:50809$1627 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + cell $and $and$libresoc.v:187378$13930 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \delay - connect \B 1'1 - connect \Y $sub$libresoc.v:50809$1627_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:51019.8-51022.4" - cell \core \core - connect \coresync_clk \coresync_clk - connect \coresync_rst \core_coresync_rst - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:51023.7-51048.4" - cell \dbg \dbg - connect \clk \clk - connect \core_dbg_msr \dbg_core_dbg_msr - connect \core_dbg_pc \dbg_core_dbg_pc - connect \core_rst_o \dbg_core_rst_o - connect \core_stop_o \dbg_core_stop_o - connect \core_stopped_i \dbg_core_stopped_i - connect \d_cr_ack \dbg_d_cr_ack - connect \d_cr_data \dbg_d_cr_data - connect \d_cr_req \dbg_d_cr_req - connect \d_gpr_ack \dbg_d_gpr_ack - connect \d_gpr_addr \dbg_d_gpr_addr - connect \d_gpr_data \dbg_d_gpr_data - connect \d_gpr_req \dbg_d_gpr_req - connect \d_xer_ack \dbg_d_xer_ack - connect \d_xer_data \dbg_d_xer_data - connect \d_xer_req \dbg_d_xer_req - connect \dmi_ack_o \dbg_dmi_ack_o - connect \dmi_addr_i \dbg_dmi_addr_i - connect \dmi_din \dbg_dmi_din - connect \dmi_dout \dbg_dmi_dout - connect \dmi_req_i \dbg_dmi_req_i - connect \dmi_we_i \dbg_dmi_we_i - connect \rst \rst - connect \terminate_i \dbg_terminate_i - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:51049.8-51115.4" - cell \dec2 \dec2 - connect \asmcode \dec2_asmcode - connect \bigendian \dec2_bigendian - connect \cia \dec2_cia - connect \cr_in1 \dec2_cr_in1 - connect \cr_in1_ok \dec2_cr_in1_ok - connect \cr_in2 \dec2_cr_in2 - connect \cr_in2$1 \dec2_cr_in2$1 - connect \cr_in2_ok \dec2_cr_in2_ok - connect \cr_in2_ok$2 \dec2_cr_in2_ok$2 - connect \cr_out \dec2_cr_out - connect \cr_out_ok \dec2_cr_out_ok - connect \cr_rd \dec2_cr_rd - connect \cr_rd_ok \dec2_cr_rd_ok - connect \cr_wr \dec2_cr_wr - connect \cr_wr_ok \dec2_cr_wr_ok - connect \cur_dec \dec2_cur_dec - connect \cur_eint \dec2_cur_eint - connect \cur_msr \dec2_cur_msr - connect \cur_pc \dec2_cur_pc - connect \ea \dec2_ea - connect \ea_ok \dec2_ea_ok - connect \exc_$signal \dec2_exc_$signal - connect \exc_$signal$3 \dec2_exc_$signal$3 - connect \exc_$signal$4 \dec2_exc_$signal$4 - connect \exc_$signal$5 \dec2_exc_$signal$5 - connect \exc_$signal$6 \dec2_exc_$signal$6 - connect \exc_$signal$7 \dec2_exc_$signal$7 - connect \exc_$signal$8 \dec2_exc_$signal$8 - connect \exc_$signal$9 \dec2_exc_$signal$9 - connect \fast1 \dec2_fast1 - connect \fast1_ok \dec2_fast1_ok - connect \fast2 \dec2_fast2 - connect \fast2_ok \dec2_fast2_ok - connect \fasto1 \dec2_fasto1 - connect \fasto1_ok \dec2_fasto1_ok - connect \fasto2 \dec2_fasto2 - connect \fasto2_ok \dec2_fasto2_ok - connect \fn_unit \dec2_fn_unit - connect \input_carry \dec2_input_carry - connect \insn \dec2_insn - connect \insn_type \dec2_insn_type - connect \is_32bit \dec2_is_32bit - connect \lk \dec2_lk - connect \msr \dec2_msr - connect \oe \dec2_oe - connect \oe_ok \dec2_oe_ok - connect \raw_opcode_in \dec2_raw_opcode_in - connect \rc \dec2_rc - connect \rc_ok \dec2_rc_ok - connect \reg1 \dec2_reg1 - connect \reg1_ok \dec2_reg1_ok - connect \reg2 \dec2_reg2 - connect \reg2_ok \dec2_reg2_ok - connect \reg3 \dec2_reg3 - connect \reg3_ok \dec2_reg3_ok - connect \rego \dec2_rego - connect \rego_ok \dec2_rego_ok - connect \spr1 \dec2_spr1 - connect \spr1_ok \dec2_spr1_ok - connect \spro \dec2_spro - connect \spro_ok \dec2_spro_ok - connect \trapaddr \dec2_trapaddr - connect \traptype \dec2_traptype - connect \xer_in \dec2_xer_in - connect \xer_out \dec2_xer_out - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:51116.8-51132.4" - cell \imem \imem - connect \a_pc_i \imem_a_pc_i - connect \a_valid_i \imem_a_valid_i - connect \clk \clk - connect \f_busy_o \imem_f_busy_o - connect \f_instr_o \imem_f_instr_o - connect \f_valid_i \imem_f_valid_i - connect \ibus__ack \ibus__ack - connect \ibus__adr \ibus__adr - connect \ibus__cyc \ibus__cyc - connect \ibus__dat_r \ibus__dat_r - connect \ibus__err \ibus__err - connect \ibus__sel \ibus__sel - connect \ibus__stb \ibus__stb - connect \rst \rst - connect \wb_icache_en \imem_wb_icache_en - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:51133.8-51463.4" - cell \jtag \jtag - connect \TAP_bus__tck \TAP_bus__tck - connect \TAP_bus__tdi \TAP_bus__tdi - connect \TAP_bus__tdo \TAP_bus__tdo - connect \TAP_bus__tms \TAP_bus__tms - connect \clk \clk - connect \dmi0__ack_o \jtag_dmi0__ack_o - connect \dmi0__addr_i \jtag_dmi0__addr_i - connect \dmi0__din \jtag_dmi0__din - connect \dmi0__dout \jtag_dmi0__dout - connect \dmi0__req_i \jtag_dmi0__req_i - connect \dmi0__we_i \jtag_dmi0__we_i - connect \eint_0__core__i \eint_0__core__i - connect \eint_0__pad__i \eint_0__pad__i - connect \eint_1__core__i \eint_1__core__i - connect \eint_1__pad__i \eint_1__pad__i - connect \eint_2__core__i \eint_2__core__i - connect \eint_2__pad__i \eint_2__pad__i - connect \gpio_e10__core__i \gpio_e10__core__i - connect \gpio_e10__core__o \gpio_e10__core__o - connect \gpio_e10__core__oe \gpio_e10__core__oe - connect \gpio_e10__pad__i \gpio_e10__pad__i - connect \gpio_e10__pad__o \gpio_e10__pad__o - connect \gpio_e10__pad__oe \gpio_e10__pad__oe - connect \gpio_e11__core__i \gpio_e11__core__i - connect \gpio_e11__core__o \gpio_e11__core__o - connect \gpio_e11__core__oe \gpio_e11__core__oe - connect \gpio_e11__pad__i \gpio_e11__pad__i - connect \gpio_e11__pad__o \gpio_e11__pad__o - connect \gpio_e11__pad__oe \gpio_e11__pad__oe - connect \gpio_e12__core__i \gpio_e12__core__i - connect \gpio_e12__core__o \gpio_e12__core__o - connect \gpio_e12__core__oe \gpio_e12__core__oe - connect \gpio_e12__pad__i \gpio_e12__pad__i - connect \gpio_e12__pad__o \gpio_e12__pad__o - connect \gpio_e12__pad__oe \gpio_e12__pad__oe - connect \gpio_e13__core__i \gpio_e13__core__i - connect \gpio_e13__core__o \gpio_e13__core__o - connect \gpio_e13__core__oe \gpio_e13__core__oe - connect \gpio_e13__pad__i \gpio_e13__pad__i - connect \gpio_e13__pad__o \gpio_e13__pad__o - connect \gpio_e13__pad__oe \gpio_e13__pad__oe - connect \gpio_e14__core__i \gpio_e14__core__i - connect \gpio_e14__core__o \gpio_e14__core__o - connect \gpio_e14__core__oe \gpio_e14__core__oe - connect \gpio_e14__pad__i \gpio_e14__pad__i - connect \gpio_e14__pad__o \gpio_e14__pad__o - connect \gpio_e14__pad__oe \gpio_e14__pad__oe - connect \gpio_e15__core__i \gpio_e15__core__i - connect \gpio_e15__core__o \gpio_e15__core__o - connect \gpio_e15__core__oe \gpio_e15__core__oe - connect \gpio_e15__pad__i \gpio_e15__pad__i - connect \gpio_e15__pad__o \gpio_e15__pad__o - connect \gpio_e15__pad__oe \gpio_e15__pad__oe - connect \gpio_e8__core__i \gpio_e8__core__i - connect \gpio_e8__core__o \gpio_e8__core__o - connect \gpio_e8__core__oe \gpio_e8__core__oe - connect \gpio_e8__pad__i \gpio_e8__pad__i - connect \gpio_e8__pad__o \gpio_e8__pad__o - connect \gpio_e8__pad__oe \gpio_e8__pad__oe - connect \gpio_e9__core__i \gpio_e9__core__i - connect \gpio_e9__core__o \gpio_e9__core__o - connect \gpio_e9__core__oe \gpio_e9__core__oe - connect \gpio_e9__pad__i \gpio_e9__pad__i - connect \gpio_e9__pad__o \gpio_e9__pad__o - connect \gpio_e9__pad__oe \gpio_e9__pad__oe - connect \gpio_s0__core__i \gpio_s0__core__i - connect \gpio_s0__core__o \gpio_s0__core__o - connect \gpio_s0__core__oe \gpio_s0__core__oe - connect \gpio_s0__pad__i \gpio_s0__pad__i - connect \gpio_s0__pad__o \gpio_s0__pad__o - connect \gpio_s0__pad__oe \gpio_s0__pad__oe - connect \gpio_s1__core__i \gpio_s1__core__i - connect \gpio_s1__core__o \gpio_s1__core__o - connect \gpio_s1__core__oe \gpio_s1__core__oe - connect \gpio_s1__pad__i \gpio_s1__pad__i - connect \gpio_s1__pad__o \gpio_s1__pad__o - connect \gpio_s1__pad__oe \gpio_s1__pad__oe - connect \gpio_s2__core__i \gpio_s2__core__i - connect \gpio_s2__core__o \gpio_s2__core__o - connect \gpio_s2__core__oe \gpio_s2__core__oe - connect \gpio_s2__pad__i \gpio_s2__pad__i - connect \gpio_s2__pad__o \gpio_s2__pad__o - connect \gpio_s2__pad__oe \gpio_s2__pad__oe - connect \gpio_s3__core__i \gpio_s3__core__i - connect \gpio_s3__core__o \gpio_s3__core__o - connect \gpio_s3__core__oe \gpio_s3__core__oe - connect \gpio_s3__pad__i \gpio_s3__pad__i - connect \gpio_s3__pad__o \gpio_s3__pad__o - connect \gpio_s3__pad__oe \gpio_s3__pad__oe - connect \gpio_s4__core__i \gpio_s4__core__i - connect \gpio_s4__core__o \gpio_s4__core__o - connect \gpio_s4__core__oe \gpio_s4__core__oe - connect \gpio_s4__pad__i \gpio_s4__pad__i - connect \gpio_s4__pad__o \gpio_s4__pad__o - connect \gpio_s4__pad__oe \gpio_s4__pad__oe - connect \gpio_s5__core__i \gpio_s5__core__i - connect \gpio_s5__core__o \gpio_s5__core__o - connect \gpio_s5__core__oe \gpio_s5__core__oe - connect \gpio_s5__pad__i \gpio_s5__pad__i - connect \gpio_s5__pad__o \gpio_s5__pad__o - connect \gpio_s5__pad__oe \gpio_s5__pad__oe - connect \gpio_s6__core__i \gpio_s6__core__i - connect \gpio_s6__core__o \gpio_s6__core__o - connect \gpio_s6__core__oe \gpio_s6__core__oe - connect \gpio_s6__pad__i \gpio_s6__pad__i - connect \gpio_s6__pad__o \gpio_s6__pad__o - connect \gpio_s6__pad__oe \gpio_s6__pad__oe - connect \gpio_s7__core__i \gpio_s7__core__i - connect \gpio_s7__core__o \gpio_s7__core__o - connect \gpio_s7__core__oe \gpio_s7__core__oe - connect \gpio_s7__pad__i \gpio_s7__pad__i - connect \gpio_s7__pad__o \gpio_s7__pad__o - connect \gpio_s7__pad__oe \gpio_s7__pad__oe - connect \jtag_wb__ack \jtag_wb__ack - connect \jtag_wb__adr \jtag_wb__adr - connect \jtag_wb__cyc \jtag_wb__cyc - connect \jtag_wb__dat_r \jtag_wb__dat_r - connect \jtag_wb__dat_w \jtag_wb__dat_w - connect \jtag_wb__sel \jtag_wb__sel - connect \jtag_wb__stb \jtag_wb__stb - connect \jtag_wb__we \jtag_wb__we - connect \mspi0_clk__core__o \mspi0_clk__core__o - connect \mspi0_clk__pad__o \mspi0_clk__pad__o - connect \mspi0_cs_n__core__o \mspi0_cs_n__core__o - connect \mspi0_cs_n__pad__o \mspi0_cs_n__pad__o - connect \mspi0_miso__core__i \mspi0_miso__core__i - connect \mspi0_miso__pad__i \mspi0_miso__pad__i - connect \mspi0_mosi__core__o \mspi0_mosi__core__o - connect \mspi0_mosi__pad__o \mspi0_mosi__pad__o - connect \mspi1_clk__core__o \mspi1_clk__core__o - connect \mspi1_clk__pad__o \mspi1_clk__pad__o - connect \mspi1_cs_n__core__o \mspi1_cs_n__core__o - connect \mspi1_cs_n__pad__o \mspi1_cs_n__pad__o - connect \mspi1_miso__core__i \mspi1_miso__core__i - connect \mspi1_miso__pad__i \mspi1_miso__pad__i - connect \mspi1_mosi__core__o \mspi1_mosi__core__o - connect \mspi1_mosi__pad__o \mspi1_mosi__pad__o - connect \mtwi_scl__core__o \mtwi_scl__core__o - connect \mtwi_scl__pad__o \mtwi_scl__pad__o - connect \mtwi_sda__core__i \mtwi_sda__core__i - connect \mtwi_sda__core__o \mtwi_sda__core__o - connect \mtwi_sda__core__oe \mtwi_sda__core__oe - connect \mtwi_sda__pad__i \mtwi_sda__pad__i - connect \mtwi_sda__pad__o \mtwi_sda__pad__o - connect \mtwi_sda__pad__oe \mtwi_sda__pad__oe - connect \pwm_0__core__o \pwm_0__core__o - connect \pwm_0__pad__o \pwm_0__pad__o - connect \pwm_1__core__o \pwm_1__core__o - connect \pwm_1__pad__o \pwm_1__pad__o - connect \rst \rst - connect \sd0_clk__core__o \sd0_clk__core__o - connect \sd0_clk__pad__o \sd0_clk__pad__o - connect \sd0_cmd__core__i \sd0_cmd__core__i - connect \sd0_cmd__core__o \sd0_cmd__core__o - connect \sd0_cmd__core__oe \sd0_cmd__core__oe - connect \sd0_cmd__pad__i \sd0_cmd__pad__i - connect \sd0_cmd__pad__o \sd0_cmd__pad__o - connect \sd0_cmd__pad__oe \sd0_cmd__pad__oe - connect \sd0_data0__core__i \sd0_data0__core__i - connect \sd0_data0__core__o \sd0_data0__core__o - connect \sd0_data0__core__oe \sd0_data0__core__oe - connect \sd0_data0__pad__i \sd0_data0__pad__i - connect \sd0_data0__pad__o \sd0_data0__pad__o - connect \sd0_data0__pad__oe \sd0_data0__pad__oe - connect \sd0_data1__core__i \sd0_data1__core__i - connect \sd0_data1__core__o \sd0_data1__core__o - connect \sd0_data1__core__oe \sd0_data1__core__oe - connect \sd0_data1__pad__i \sd0_data1__pad__i - connect \sd0_data1__pad__o \sd0_data1__pad__o - connect \sd0_data1__pad__oe \sd0_data1__pad__oe - connect \sd0_data2__core__i \sd0_data2__core__i - connect \sd0_data2__core__o \sd0_data2__core__o - connect \sd0_data2__core__oe \sd0_data2__core__oe - connect \sd0_data2__pad__i \sd0_data2__pad__i - connect \sd0_data2__pad__o \sd0_data2__pad__o - connect \sd0_data2__pad__oe \sd0_data2__pad__oe - connect \sd0_data3__core__i \sd0_data3__core__i - connect \sd0_data3__core__o \sd0_data3__core__o - connect \sd0_data3__core__oe \sd0_data3__core__oe - connect \sd0_data3__pad__i \sd0_data3__pad__i - connect \sd0_data3__pad__o \sd0_data3__pad__o - connect \sd0_data3__pad__oe \sd0_data3__pad__oe - connect \sdr_a_0__core__o \sdr_a_0__core__o - connect \sdr_a_0__pad__o \sdr_a_0__pad__o - connect \sdr_a_10__core__o \sdr_a_10__core__o - connect \sdr_a_10__pad__o \sdr_a_10__pad__o - connect \sdr_a_11__core__o \sdr_a_11__core__o - connect \sdr_a_11__pad__o \sdr_a_11__pad__o - connect \sdr_a_12__core__o \sdr_a_12__core__o - connect \sdr_a_12__pad__o \sdr_a_12__pad__o - connect \sdr_a_1__core__o \sdr_a_1__core__o - connect \sdr_a_1__pad__o \sdr_a_1__pad__o - connect \sdr_a_2__core__o \sdr_a_2__core__o - connect \sdr_a_2__pad__o \sdr_a_2__pad__o - connect \sdr_a_3__core__o \sdr_a_3__core__o - connect \sdr_a_3__pad__o \sdr_a_3__pad__o - connect \sdr_a_4__core__o \sdr_a_4__core__o - connect \sdr_a_4__pad__o \sdr_a_4__pad__o - connect \sdr_a_5__core__o \sdr_a_5__core__o - connect \sdr_a_5__pad__o \sdr_a_5__pad__o - connect \sdr_a_6__core__o \sdr_a_6__core__o - connect \sdr_a_6__pad__o \sdr_a_6__pad__o - connect \sdr_a_7__core__o \sdr_a_7__core__o - connect \sdr_a_7__pad__o \sdr_a_7__pad__o - connect \sdr_a_8__core__o \sdr_a_8__core__o - connect \sdr_a_8__pad__o \sdr_a_8__pad__o - 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\sdr_dq_15__pad__i - connect \sdr_dq_15__pad__o \sdr_dq_15__pad__o - connect \sdr_dq_15__pad__oe \sdr_dq_15__pad__oe - connect \sdr_dq_1__core__i \sdr_dq_1__core__i - connect \sdr_dq_1__core__o \sdr_dq_1__core__o - connect \sdr_dq_1__core__oe \sdr_dq_1__core__oe - connect \sdr_dq_1__pad__i \sdr_dq_1__pad__i - connect \sdr_dq_1__pad__o \sdr_dq_1__pad__o - connect \sdr_dq_1__pad__oe \sdr_dq_1__pad__oe - connect \sdr_dq_2__core__i \sdr_dq_2__core__i - connect \sdr_dq_2__core__o \sdr_dq_2__core__o - connect \sdr_dq_2__core__oe \sdr_dq_2__core__oe - connect \sdr_dq_2__pad__i \sdr_dq_2__pad__i - connect \sdr_dq_2__pad__o \sdr_dq_2__pad__o - connect \sdr_dq_2__pad__oe \sdr_dq_2__pad__oe - connect \sdr_dq_3__core__i \sdr_dq_3__core__i - connect \sdr_dq_3__core__o \sdr_dq_3__core__o - connect \sdr_dq_3__core__oe \sdr_dq_3__core__oe - connect \sdr_dq_3__pad__i \sdr_dq_3__pad__i - connect \sdr_dq_3__pad__o \sdr_dq_3__pad__o - connect \sdr_dq_3__pad__oe \sdr_dq_3__pad__oe - connect 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connect \sdr_dq_7__pad__i \sdr_dq_7__pad__i - connect \sdr_dq_7__pad__o \sdr_dq_7__pad__o - connect \sdr_dq_7__pad__oe \sdr_dq_7__pad__oe - connect \sdr_dq_8__core__i \sdr_dq_8__core__i - connect \sdr_dq_8__core__o \sdr_dq_8__core__o - connect \sdr_dq_8__core__oe \sdr_dq_8__core__oe - connect \sdr_dq_8__pad__i \sdr_dq_8__pad__i - connect \sdr_dq_8__pad__o \sdr_dq_8__pad__o - connect \sdr_dq_8__pad__oe \sdr_dq_8__pad__oe - connect \sdr_dq_9__core__i \sdr_dq_9__core__i - connect \sdr_dq_9__core__o \sdr_dq_9__core__o - connect \sdr_dq_9__core__oe \sdr_dq_9__core__oe - connect \sdr_dq_9__pad__i \sdr_dq_9__pad__i - connect \sdr_dq_9__pad__o \sdr_dq_9__pad__o - connect \sdr_dq_9__pad__oe \sdr_dq_9__pad__oe - connect \sdr_ras_n__core__o \sdr_ras_n__core__o - connect \sdr_ras_n__pad__o \sdr_ras_n__pad__o - connect \sdr_we_n__core__o \sdr_we_n__core__o - connect \sdr_we_n__pad__o \sdr_we_n__pad__o - connect \wb_icache_en \imem_wb_icache_en - end - attribute \module_not_derived 1 - attribute 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connect \int_level_i \int_level_i - connect \rst \rst - end - attribute \src "libresoc.v:48733.7-48733.20" - process $proc$libresoc.v:48733$2164 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:48865.7-48865.25" - process $proc$libresoc.v:48865$2165 - assign { } { } - assign $1\bigendian_i[0:0] 1'0 - sync always - sync init - update \bigendian_i $1\bigendian_i[0:0] - end - attribute \src "libresoc.v:48877.13-48877.33" - process $proc$libresoc.v:48877$2166 - assign { } { } - assign $1\core_asmcode[7:0] 8'00000000 - sync always - sync init - update \core_asmcode $1\core_asmcode[7:0] - end - attribute \src "libresoc.v:48883.14-48883.50" - process $proc$libresoc.v:48883$2167 - assign { } { } - assign $1\core_core_cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \core_core_cia $1\core_core_cia[63:0] - end - attribute \src "libresoc.v:48887.13-48887.36" - process $proc$libresoc.v:48887$2168 - assign { } { } - assign $1\core_core_cr_rd[7:0] 8'00000000 - sync always - sync init - update \core_core_cr_rd $1\core_core_cr_rd[7:0] - end - attribute \src "libresoc.v:48891.7-48891.32" - process $proc$libresoc.v:48891$2169 - assign { } { } - assign $1\core_core_cr_rd_ok[0:0] 1'0 - sync always - sync init - update \core_core_cr_rd_ok $1\core_core_cr_rd_ok[0:0] - end - attribute \src "libresoc.v:48895.13-48895.36" - process $proc$libresoc.v:48895$2170 - assign { } { } - assign $1\core_core_cr_wr[7:0] 8'00000000 - sync always - sync init - update \core_core_cr_wr $1\core_core_cr_wr[7:0] - end - attribute \src "libresoc.v:48899.7-48899.32" - process $proc$libresoc.v:48899$2171 - assign { } { } - assign $1\core_core_cr_wr_ok[0:0] 1'0 - sync always - sync init - update \core_core_cr_wr_ok $1\core_core_cr_wr_ok[0:0] - end - attribute \src "libresoc.v:48903.7-48903.37" - process $proc$libresoc.v:48903$2172 - assign { } { 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\core_core_exc_$signal$52 $0\core_core_exc_$signal$52[0:0]$2179 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:187381$13933 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:187381$13933_Y end - attribute \src "libresoc.v:48917.7-48917.40" - process $proc$libresoc.v:48917$2180 - assign { } { } - assign $0\core_core_exc_$signal$53[0:0]$2181 1'0 - sync always - sync init - update \core_core_exc_$signal$53 $0\core_core_exc_$signal$53[0:0]$2181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:187382$13934 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fast1_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:187382$13934_Y end - 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parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \nia_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:187384$13936_Y end - attribute \src "libresoc.v:48929.7-48929.40" - process $proc$libresoc.v:48929$2186 - assign { } { } - assign $0\core_core_exc_$signal$56[0:0]$2187 1'0 - sync always - sync init - update \core_core_exc_$signal$56 $0\core_core_exc_$signal$56[0:0]$2187 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:187385$13937 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msr_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:187385$13937_Y end - attribute \src "libresoc.v:48948.14-48948.41" - process $proc$libresoc.v:48948$2188 - assign { } { } - assign $1\core_core_fn_unit[11:0] 12'000000000000 - sync always - sync init - update \core_core_fn_unit $1\core_core_fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + cell $and $and$libresoc.v:187391$13943 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_trap0_p_ready_o + connect \B \alui_l_q_alui + connect \Y $and$libresoc.v:187391$13943_Y end - attribute \src "libresoc.v:48956.13-48956.41" - process $proc$libresoc.v:48956$2189 - assign { } { } - assign $1\core_core_input_carry[1:0] 2'00 - sync always - sync init - update \core_core_input_carry $1\core_core_input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + cell $and $and$libresoc.v:187392$13944 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_trap0_n_valid_o + connect \B \alu_l_q_alu + connect \Y $and$libresoc.v:187392$13944_Y end - attribute \src "libresoc.v:48960.14-48960.36" - process $proc$libresoc.v:48960$2190 - assign { } { } - assign $1\core_core_insn[31:0] 0 - sync always - sync init - update \core_core_insn $1\core_core_insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:187393$13945 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \src_l_q_src + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$libresoc.v:187393$13945_Y end - attribute \src "libresoc.v:49038.13-49038.40" - process $proc$libresoc.v:49038$2191 - assign { } { } - assign $1\core_core_insn_type[6:0] 7'0000000 - sync always - sync init - update \core_core_insn_type $1\core_core_insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:187394$13946 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$93 + connect \B 4'1111 + connect \Y $and$libresoc.v:187394$13946_Y end - attribute \src "libresoc.v:49042.7-49042.32" - process $proc$libresoc.v:49042$2192 - assign { } { } - assign $1\core_core_is_32bit[0:0] 1'0 - sync always - sync init - update \core_core_is_32bit $1\core_core_is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $eq$libresoc.v:187367$13919 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$43 + connect \B 1'0 + connect \Y $eq$libresoc.v:187367$13919_Y end - attribute \src "libresoc.v:49046.7-49046.26" - process $proc$libresoc.v:49046$2193 - assign { } { } - assign $1\core_core_lk[0:0] 1'0 - sync always - sync init - update \core_core_lk $1\core_core_lk[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $eq$libresoc.v:187369$13921 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $eq$libresoc.v:187369$13921_Y end - attribute \src "libresoc.v:49050.14-49050.50" - process $proc$libresoc.v:49050$2194 - assign { } { } - assign $1\core_core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \core_core_msr $1\core_core_msr[63:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:187350$13902 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $not$libresoc.v:187350$13902_Y end - attribute \src "libresoc.v:49054.7-49054.26" - process $proc$libresoc.v:49054$2195 - assign { } { } - assign $1\core_core_oe[0:0] 1'0 - sync always - sync init - update \core_core_oe $1\core_core_oe[0:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:187352$13904 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $not$libresoc.v:187352$13904_Y end - attribute \src "libresoc.v:49058.7-49058.29" - process $proc$libresoc.v:49058$2196 - assign { } { } - assign $1\core_core_oe_ok[0:0] 1'0 - sync always - sync init - update \core_core_oe_ok $1\core_core_oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:187355$13907 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_wrmask_o + connect \Y $not$libresoc.v:187355$13907_Y end - attribute \src "libresoc.v:49062.7-49062.26" - process $proc$libresoc.v:49062$2197 - assign { } { } - assign $1\core_core_rc[0:0] 1'0 - sync always - sync init - update \core_core_rc $1\core_core_rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:187358$13910 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:187358$13910_Y end - attribute \src "libresoc.v:49066.7-49066.29" - process $proc$libresoc.v:49066$2198 - assign { } { } - assign $1\core_core_rc_ok[0:0] 1'0 - sync always - sync init - update \core_core_rc_ok $1\core_core_rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$libresoc.v:187364$13916 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_trap0_n_ready_i + connect \Y $not$libresoc.v:187364$13916_Y end - attribute \src "libresoc.v:49070.14-49070.43" - process $proc$libresoc.v:49070$2199 - assign { } { } - assign $1\core_core_trapaddr[12:0] 13'0000000000000 - sync always - sync init - update \core_core_trapaddr $1\core_core_trapaddr[12:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$libresoc.v:187379$13931 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_rd__rel_o + connect \Y $not$libresoc.v:187379$13931_Y end - attribute \src "libresoc.v:49074.13-49074.39" - process $proc$libresoc.v:49074$2200 - assign { } { } - assign $1\core_core_traptype[7:0] 8'00000000 - sync always - sync init - update \core_core_traptype $1\core_core_traptype[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$libresoc.v:187395$13947 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_rdmaskn_i + connect \Y $not$libresoc.v:187395$13947_Y end - attribute \src "libresoc.v:49080.13-49080.31" - process $proc$libresoc.v:49080$2201 - assign { } { } - assign $1\core_cr_in1[2:0] 3'000 - sync always - sync init - update \core_cr_in1 $1\core_cr_in1[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$libresoc.v:187362$13914 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$33 + connect \B \$35 + connect \Y $or$libresoc.v:187362$13914_Y end - attribute \src "libresoc.v:49084.7-49084.28" - process $proc$libresoc.v:49084$2202 - assign { } { } - assign $1\core_cr_in1_ok[0:0] 1'0 - sync always - sync init - update \core_cr_in1_ok $1\core_cr_in1_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$libresoc.v:187373$13925 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:187373$13925_Y end - attribute \src "libresoc.v:49088.13-49088.31" - process $proc$libresoc.v:49088$2203 - assign { } { } - assign $1\core_cr_in2[2:0] 3'000 - sync always - sync init - update \core_cr_in2 $1\core_cr_in2[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$libresoc.v:187374$13926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:187374$13926_Y end - attribute \src "libresoc.v:49090.13-49090.36" - process $proc$libresoc.v:49090$2204 - assign { } { } - assign $0\core_cr_in2$48[2:0]$2205 3'000 - sync always - sync init - update \core_cr_in2$48 $0\core_cr_in2$48[2:0]$2205 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$libresoc.v:187375$13927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:187375$13927_Y end - attribute \src "libresoc.v:49096.7-49096.28" - process $proc$libresoc.v:49096$2206 - assign { } { } - assign $1\core_cr_in2_ok[0:0] 1'0 - sync always - sync init - update \core_cr_in2_ok $1\core_cr_in2_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$libresoc.v:187376$13928 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:187376$13928_Y end - attribute \src "libresoc.v:49098.7-49098.33" - process $proc$libresoc.v:49098$2207 - assign { } { } - assign $0\core_cr_in2_ok$49[0:0]$2208 1'0 - sync always - sync init - update \core_cr_in2_ok$49 $0\core_cr_in2_ok$49[0:0]$2208 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:187380$13932 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$libresoc.v:187380$13932_Y end - attribute \src "libresoc.v:49104.13-49104.31" - process $proc$libresoc.v:49104$2209 - assign { } { } - assign $1\core_cr_out[2:0] 3'000 - sync always - sync init - update \core_cr_out $1\core_cr_out[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:187390$13942 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$6 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:187390$13942_Y end - attribute \src "libresoc.v:49108.7-49108.28" - process $proc$libresoc.v:49108$2210 - assign { } { } - assign $1\core_cr_out_ok[0:0] 1'0 - sync always - sync init - update \core_cr_out_ok $1\core_cr_out_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:187335$13887 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $reduce_and$libresoc.v:187335$13887_Y end - attribute \src "libresoc.v:49112.14-49112.45" - process $proc$libresoc.v:49112$2211 - assign { } { } - assign $1\core_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \core_dec $1\core_dec[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:187357$13909 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \$27 + connect \Y $reduce_or$libresoc.v:187357$13909_Y end - attribute \src "libresoc.v:49116.13-49116.28" - process $proc$libresoc.v:49116$2212 - assign { } { } - assign $1\core_ea[4:0] 5'00000 - sync always - sync init - update \core_ea $1\core_ea[4:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:187360$13912 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:187360$13912_Y end - attribute \src "libresoc.v:49120.7-49120.24" - process $proc$libresoc.v:49120$2213 - assign { } { } - assign $1\core_ea_ok[0:0] 1'0 - sync always - sync init - update \core_ea_ok $1\core_ea_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:187361$13913 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:187361$13913_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:187386$13938 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $ternary$libresoc.v:187386$13938_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:187387$13939 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src2_i + connect \S \src_l_q_src [1] + connect \Y $ternary$libresoc.v:187387$13939_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:187388$13940 + parameter \WIDTH 64 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:187388$13940_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:187389$13941 + parameter \WIDTH 64 + connect \A \src_r3 + connect \B \src4_i + connect \S \src_l_q_src [3] + connect \Y $ternary$libresoc.v:187389$13941_Y end - attribute \src "libresoc.v:49124.7-49124.23" - process $proc$libresoc.v:49124$2214 - assign { } { } - assign $1\core_eint[0:0] 1'0 - sync always - sync init - update \core_eint $1\core_eint[0:0] + attribute \module_not_derived 1 + attribute \src "libresoc.v:187472.14-187478.4" + cell \alu_l$45 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu end - attribute \src "libresoc.v:49128.13-49128.30" - process $proc$libresoc.v:49128$2215 - assign { } { } - assign $1\core_fast1[2:0] 3'000 - sync always - sync init - update \core_fast1 $1\core_fast1[2:0] + attribute \module_not_derived 1 + attribute \src "libresoc.v:187479.13-187509.4" + cell \alu_trap0 \alu_trap0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \fast1 \alu_trap0_fast1 + connect \fast1$1 \alu_trap0_fast1$1 + connect \fast1_ok \fast1_ok + connect \fast2 \alu_trap0_fast2 + connect \fast2$2 \alu_trap0_fast2$2 + connect \fast2_ok \fast2_ok + connect \msr \alu_trap0_msr + connect \msr_ok \msr_ok + connect \n_ready_i \alu_trap0_n_ready_i + connect \n_valid_o \alu_trap0_n_valid_o + connect \nia \alu_trap0_nia + connect \nia_ok \nia_ok + connect \o \alu_trap0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_trap0_p_ready_o + connect \p_valid_i \alu_trap0_p_valid_i + connect \ra \alu_trap0_ra + connect \rb \alu_trap0_rb + connect \trap_op__cia \alu_trap0_trap_op__cia + connect \trap_op__fn_unit \alu_trap0_trap_op__fn_unit + connect \trap_op__insn \alu_trap0_trap_op__insn + connect \trap_op__insn_type \alu_trap0_trap_op__insn_type + connect \trap_op__is_32bit \alu_trap0_trap_op__is_32bit + connect \trap_op__ldst_exc \alu_trap0_trap_op__ldst_exc + connect \trap_op__msr \alu_trap0_trap_op__msr + connect \trap_op__trapaddr \alu_trap0_trap_op__trapaddr + connect \trap_op__traptype \alu_trap0_trap_op__traptype end - attribute \src "libresoc.v:49132.7-49132.27" - process $proc$libresoc.v:49132$2216 - assign { } { } - assign $1\core_fast1_ok[0:0] 1'0 - sync always - sync init - update \core_fast1_ok $1\core_fast1_ok[0:0] + attribute \module_not_derived 1 + attribute \src "libresoc.v:187510.15-187516.4" + cell \alui_l$44 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui end - attribute \src "libresoc.v:49136.13-49136.30" - process $proc$libresoc.v:49136$2217 - assign { } { } - assign $1\core_fast2[2:0] 3'000 - sync always - sync init - update \core_fast2 $1\core_fast2[2:0] + attribute \module_not_derived 1 + attribute \src "libresoc.v:187517.14-187523.4" + cell \opc_l$40 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc end - attribute \src "libresoc.v:49140.7-49140.27" - process $proc$libresoc.v:49140$2218 - assign { } { } - assign $1\core_fast2_ok[0:0] 1'0 - sync always - sync init - update \core_fast2_ok $1\core_fast2_ok[0:0] + attribute \module_not_derived 1 + attribute \src "libresoc.v:187524.14-187530.4" + cell \req_l$41 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req end - attribute \src "libresoc.v:49144.13-49144.31" - process $proc$libresoc.v:49144$2219 - assign { } { } - assign $1\core_fasto1[2:0] 3'000 - sync always - sync init - update \core_fasto1 $1\core_fasto1[2:0] + attribute \module_not_derived 1 + attribute \src "libresoc.v:187531.14-187537.4" + cell \rok_l$43 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok end - attribute \src "libresoc.v:49148.7-49148.28" - process $proc$libresoc.v:49148$2220 - assign { } { } - assign $1\core_fasto1_ok[0:0] 1'0 - sync always - sync init - update \core_fasto1_ok $1\core_fasto1_ok[0:0] + attribute \module_not_derived 1 + attribute \src "libresoc.v:187538.14-187543.4" + cell \rst_l$42 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst end - attribute \src "libresoc.v:49152.13-49152.31" - process $proc$libresoc.v:49152$2221 - assign { } { } - assign $1\core_fasto2[2:0] 3'000 - sync always - sync init - update \core_fasto2 $1\core_fasto2[2:0] + attribute \module_not_derived 1 + attribute \src "libresoc.v:187544.14-187550.4" + cell \src_l$39 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src end - attribute \src "libresoc.v:49156.7-49156.28" - process $proc$libresoc.v:49156$2222 + attribute \src "libresoc.v:186741.7-186741.20" + process $proc$libresoc.v:186741$14102 assign { } { } - assign $1\core_fasto2_ok[0:0] 1'0 + assign $0\initial[0:0] 1'0 sync always + update \initial $0\initial[0:0] sync init - update \core_fasto2_ok $1\core_fasto2_ok[0:0] end - attribute \src "libresoc.v:49160.14-49160.45" - process $proc$libresoc.v:49160$2223 + attribute \src "libresoc.v:186867.7-186867.24" + process $proc$libresoc.v:186867$14103 assign { } { } - assign $1\core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\all_rd_dly[0:0] 1'0 sync always sync init - update \core_msr $1\core_msr[63:0] + update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:49164.14-49164.44" - process $proc$libresoc.v:49164$2224 + attribute \src "libresoc.v:186877.7-186877.26" + process $proc$libresoc.v:186877$14104 assign { } { } - assign $1\core_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\alu_done_dly[0:0] 1'0 sync always sync init - update \core_pc $1\core_pc[63:0] + update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:49168.13-49168.30" - process $proc$libresoc.v:49168$2225 + attribute \src "libresoc.v:186885.7-186885.25" + process $proc$libresoc.v:186885$14105 assign { } { } - assign $1\core_reg1[4:0] 5'00000 + assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init - update \core_reg1 $1\core_reg1[4:0] + update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:49172.7-49172.26" - process $proc$libresoc.v:49172$2226 + attribute \src "libresoc.v:186921.14-186921.59" + process $proc$libresoc.v:186921$14106 assign { } { } - assign $1\core_reg1_ok[0:0] 1'0 + assign $1\alu_trap0_trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \core_reg1_ok $1\core_reg1_ok[0:0] + update \alu_trap0_trap_op__cia $1\alu_trap0_trap_op__cia[63:0] end - attribute \src "libresoc.v:49176.13-49176.30" - process $proc$libresoc.v:49176$2227 + attribute \src "libresoc.v:186938.14-186938.50" + process $proc$libresoc.v:186938$14107 assign { } { } - assign $1\core_reg2[4:0] 5'00000 + assign $1\alu_trap0_trap_op__fn_unit[11:0] 12'000000000000 sync always sync init - update \core_reg2 $1\core_reg2[4:0] + update \alu_trap0_trap_op__fn_unit $1\alu_trap0_trap_op__fn_unit[11:0] end - attribute \src "libresoc.v:49180.7-49180.26" - process $proc$libresoc.v:49180$2228 + attribute \src "libresoc.v:186942.14-186942.45" + process $proc$libresoc.v:186942$14108 assign { } { } - assign $1\core_reg2_ok[0:0] 1'0 + assign $1\alu_trap0_trap_op__insn[31:0] 0 sync always sync init - update \core_reg2_ok $1\core_reg2_ok[0:0] + update \alu_trap0_trap_op__insn $1\alu_trap0_trap_op__insn[31:0] end - attribute \src "libresoc.v:49184.13-49184.30" - process $proc$libresoc.v:49184$2229 + attribute \src "libresoc.v:187020.13-187020.49" + process $proc$libresoc.v:187020$14109 assign { } { } - assign $1\core_reg3[4:0] 5'00000 + assign $1\alu_trap0_trap_op__insn_type[6:0] 7'0000000 sync always sync init - update \core_reg3 $1\core_reg3[4:0] + update \alu_trap0_trap_op__insn_type $1\alu_trap0_trap_op__insn_type[6:0] end - attribute \src "libresoc.v:49188.7-49188.26" - process $proc$libresoc.v:49188$2230 + attribute \src "libresoc.v:187024.7-187024.41" + process $proc$libresoc.v:187024$14110 assign { } { } - assign $1\core_reg3_ok[0:0] 1'0 + assign $1\alu_trap0_trap_op__is_32bit[0:0] 1'0 sync always sync init - update \core_reg3_ok $1\core_reg3_ok[0:0] + update \alu_trap0_trap_op__is_32bit $1\alu_trap0_trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:49192.13-49192.30" - process $proc$libresoc.v:49192$2231 + attribute \src "libresoc.v:187028.13-187028.48" + process $proc$libresoc.v:187028$14111 assign { } { } - assign $1\core_rego[4:0] 5'00000 + assign $1\alu_trap0_trap_op__ldst_exc[7:0] 8'00000000 sync always sync init - update \core_rego $1\core_rego[4:0] + update \alu_trap0_trap_op__ldst_exc $1\alu_trap0_trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:49196.7-49196.26" - process $proc$libresoc.v:49196$2232 + attribute \src "libresoc.v:187032.14-187032.59" + process $proc$libresoc.v:187032$14112 assign { } { } - assign $1\core_rego_ok[0:0] 1'0 + assign $1\alu_trap0_trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \core_rego_ok $1\core_rego_ok[0:0] + update \alu_trap0_trap_op__msr $1\alu_trap0_trap_op__msr[63:0] end - attribute \src "libresoc.v:49311.13-49311.32" - process $proc$libresoc.v:49311$2233 + attribute \src "libresoc.v:187036.14-187036.52" + process $proc$libresoc.v:187036$14113 assign { } { } - assign $1\core_spr1[9:0] 10'0000000000 + assign $1\alu_trap0_trap_op__trapaddr[12:0] 13'0000000000000 sync always sync init - update \core_spr1 $1\core_spr1[9:0] + update \alu_trap0_trap_op__trapaddr $1\alu_trap0_trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:49315.7-49315.26" - process $proc$libresoc.v:49315$2234 + attribute \src "libresoc.v:187040.13-187040.48" + process $proc$libresoc.v:187040$14114 assign { } { } - assign $1\core_spr1_ok[0:0] 1'0 + assign $1\alu_trap0_trap_op__traptype[7:0] 8'00000000 sync always sync init - update \core_spr1_ok $1\core_spr1_ok[0:0] + update \alu_trap0_trap_op__traptype $1\alu_trap0_trap_op__traptype[7:0] end - attribute \src "libresoc.v:49430.13-49430.32" - process $proc$libresoc.v:49430$2235 + attribute \src "libresoc.v:187046.7-187046.27" + process $proc$libresoc.v:187046$14115 assign { } { } - assign $1\core_spro[9:0] 10'0000000000 + assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init - update \core_spro $1\core_spro[9:0] + update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:49434.7-49434.26" - process $proc$libresoc.v:49434$2236 + attribute \src "libresoc.v:187078.14-187078.47" + process $proc$libresoc.v:187078$14116 assign { } { } - assign $1\core_spro_ok[0:0] 1'0 + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \core_spro_ok $1\core_spro_ok[0:0] + update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:49442.13-49442.31" - process $proc$libresoc.v:49442$2237 + attribute \src "libresoc.v:187082.7-187082.27" + process $proc$libresoc.v:187082$14117 assign { } { } - assign $1\core_xer_in[2:0] 3'000 + assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init - update \core_xer_in $1\core_xer_in[2:0] + update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:49446.7-49446.26" - process $proc$libresoc.v:49446$2238 + attribute \src "libresoc.v:187086.14-187086.51" + process $proc$libresoc.v:187086$14118 assign { } { } - assign $1\core_xer_out[0:0] 1'0 + assign $1\data_r1__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \core_xer_out $1\core_xer_out[0:0] + update \data_r1__fast1 $1\data_r1__fast1[63:0] end - attribute \src "libresoc.v:49462.7-49462.30" - process $proc$libresoc.v:49462$2239 + attribute \src "libresoc.v:187090.7-187090.31" + process $proc$libresoc.v:187090$14119 assign { } { } - assign $1\cu_st__rel_o_dly[0:0] 1'0 + assign $1\data_r1__fast1_ok[0:0] 1'0 sync always sync init - update \cu_st__rel_o_dly $1\cu_st__rel_o_dly[0:0] + update \data_r1__fast1_ok $1\data_r1__fast1_ok[0:0] end - attribute \src "libresoc.v:49468.7-49468.24" - process $proc$libresoc.v:49468$2240 + attribute \src "libresoc.v:187094.14-187094.51" + process $proc$libresoc.v:187094$14120 assign { } { } - assign $1\d_cr_delay[0:0] 1'0 + assign $1\data_r2__fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \d_cr_delay $1\d_cr_delay[0:0] + update \data_r2__fast2 $1\data_r2__fast2[63:0] end - attribute \src "libresoc.v:49472.7-49472.25" - process $proc$libresoc.v:49472$2241 + attribute \src "libresoc.v:187098.7-187098.31" + process $proc$libresoc.v:187098$14121 assign { } { } - assign $1\d_reg_delay[0:0] 1'0 + assign $1\data_r2__fast2_ok[0:0] 1'0 sync always sync init - update \d_reg_delay $1\d_reg_delay[0:0] + update \data_r2__fast2_ok $1\data_r2__fast2_ok[0:0] end - attribute \src "libresoc.v:49476.7-49476.25" - process $proc$libresoc.v:49476$2242 + attribute \src "libresoc.v:187102.14-187102.49" + process $proc$libresoc.v:187102$14122 assign { } { } - assign $1\d_xer_delay[0:0] 1'0 + assign $1\data_r3__nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \d_xer_delay $1\d_xer_delay[0:0] + update \data_r3__nia $1\data_r3__nia[63:0] end - attribute \src "libresoc.v:49514.13-49514.34" - process $proc$libresoc.v:49514$2243 + attribute \src "libresoc.v:187106.7-187106.29" + process $proc$libresoc.v:187106$14123 assign { } { } - assign $1\dbg_dmi_addr_i[3:0] 4'0000 + assign $1\data_r3__nia_ok[0:0] 1'0 sync always sync init - update \dbg_dmi_addr_i $1\dbg_dmi_addr_i[3:0] + update \data_r3__nia_ok $1\data_r3__nia_ok[0:0] end - attribute \src "libresoc.v:49518.14-49518.48" - process $proc$libresoc.v:49518$2244 + attribute \src "libresoc.v:187110.14-187110.49" + process $proc$libresoc.v:187110$14124 assign { } { } - assign $1\dbg_dmi_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\data_r4__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \dbg_dmi_din $1\dbg_dmi_din[63:0] + update \data_r4__msr $1\data_r4__msr[63:0] end - attribute \src "libresoc.v:49524.7-49524.27" - process $proc$libresoc.v:49524$2245 + attribute \src "libresoc.v:187114.7-187114.29" + process $proc$libresoc.v:187114$14125 assign { } { } - assign $1\dbg_dmi_req_i[0:0] 1'0 + assign $1\data_r4__msr_ok[0:0] 1'0 sync always sync init - update \dbg_dmi_req_i $1\dbg_dmi_req_i[0:0] + update \data_r4__msr_ok $1\data_r4__msr_ok[0:0] end - attribute \src "libresoc.v:49528.7-49528.26" - process $proc$libresoc.v:49528$2246 + attribute \src "libresoc.v:187145.7-187145.25" + process $proc$libresoc.v:187145$14126 assign { } { } - assign $1\dbg_dmi_we_i[0:0] 1'0 + assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init - update \dbg_dmi_we_i $1\dbg_dmi_we_i[0:0] + update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:49564.14-49564.49" - process $proc$libresoc.v:49564$2247 + attribute \src "libresoc.v:187149.7-187149.25" + process $proc$libresoc.v:187149$14127 assign { } { } - assign $1\dec2_cur_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init - update \dec2_cur_dec $1\dec2_cur_dec[63:0] + update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:49568.7-49568.27" - process $proc$libresoc.v:49568$2248 + attribute \src "libresoc.v:187258.13-187258.31" + process $proc$libresoc.v:187258$14128 assign { } { } - assign $1\dec2_cur_eint[0:0] 1'0 + assign $1\prev_wr_go[4:0] 5'00000 sync always sync init - update \dec2_cur_eint $1\dec2_cur_eint[0:0] + update \prev_wr_go $1\prev_wr_go[4:0] end - attribute \src "libresoc.v:49572.14-49572.49" - process $proc$libresoc.v:49572$2249 + attribute \src "libresoc.v:187266.13-187266.32" + process $proc$libresoc.v:187266$14129 assign { } { } - assign $1\dec2_cur_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\req_l_r_req[4:0] 5'11111 sync always sync init - update \dec2_cur_msr $1\dec2_cur_msr[63:0] + update \req_l_r_req $1\req_l_r_req[4:0] end - attribute \src "libresoc.v:49576.14-49576.48" - process $proc$libresoc.v:49576$2250 + attribute \src "libresoc.v:187270.13-187270.32" + process $proc$libresoc.v:187270$14130 assign { } { } - assign $1\dec2_cur_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\req_l_s_req[4:0] 5'00000 sync always sync init - update \dec2_cur_pc $1\dec2_cur_pc[63:0] + update \req_l_s_req $1\req_l_s_req[4:0] end - attribute \src "libresoc.v:49985.13-49985.25" - process $proc$libresoc.v:49985$2251 + attribute \src "libresoc.v:187282.7-187282.26" + process $proc$libresoc.v:187282$14131 assign { } { } - assign $1\delay[1:0] 2'11 + assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init - update \delay $1\delay[1:0] + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:50007.13-50007.29" - process $proc$libresoc.v:50007$2252 + attribute \src "libresoc.v:187286.7-187286.26" + process $proc$libresoc.v:187286$14132 assign { } { } - assign $1\fsm_state[1:0] 2'00 + assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init - update \fsm_state $1\fsm_state[1:0] + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:50009.13-50009.35" - process $proc$libresoc.v:50009$2253 + attribute \src "libresoc.v:187290.7-187290.25" + process $proc$libresoc.v:187290$14133 assign { } { } - assign $0\fsm_state$131[1:0]$2254 2'00 + assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init - update \fsm_state$131 $0\fsm_state$131[1:0]$2254 + update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:50259.14-50259.28" - process $proc$libresoc.v:50259$2255 + attribute \src "libresoc.v:187294.7-187294.25" + process $proc$libresoc.v:187294$14134 assign { } { } - assign $1\ilatch[31:0] 0 + assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init - update \ilatch $1\ilatch[31:0] + update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:50293.7-50293.30" - process $proc$libresoc.v:50293$2256 + attribute \src "libresoc.v:187310.13-187310.31" + process $proc$libresoc.v:187310$14135 assign { } { } - assign $1\jtag_dmi0__ack_o[0:0] 1'0 + assign $1\src_l_r_src[3:0] 4'1111 sync always sync init - update \jtag_dmi0__ack_o $1\jtag_dmi0__ack_o[0:0] + update \src_l_r_src $1\src_l_r_src[3:0] end - attribute \src "libresoc.v:50301.14-50301.52" - process $proc$libresoc.v:50301$2257 + attribute \src "libresoc.v:187314.13-187314.31" + process $proc$libresoc.v:187314$14136 assign { } { } - assign $1\jtag_dmi0__dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\src_l_s_src[3:0] 4'0000 sync always sync init - update \jtag_dmi0__dout $1\jtag_dmi0__dout[63:0] + update \src_l_s_src $1\src_l_s_src[3:0] end - attribute \src "libresoc.v:50361.7-50361.22" - process $proc$libresoc.v:50361$2258 + attribute \src "libresoc.v:187318.14-187318.43" + process $proc$libresoc.v:187318$14137 assign { } { } - assign $1\msr_read[0:0] 1'1 + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \msr_read $1\msr_read[0:0] + update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:50389.7-50389.24" - process $proc$libresoc.v:50389$2259 + attribute \src "libresoc.v:187322.14-187322.43" + process $proc$libresoc.v:187322$14138 assign { } { } - assign $1\pc_changed[0:0] 1'0 + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \pc_changed $1\pc_changed[0:0] + update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:50399.7-50399.25" - process $proc$libresoc.v:50399$2260 + attribute \src "libresoc.v:187326.14-187326.43" + process $proc$libresoc.v:187326$14139 assign { } { } - assign $1\pc_ok_delay[0:0] 1'0 + assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \pc_ok_delay $1\pc_ok_delay[0:0] + update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:50413.14-50413.32" - process $proc$libresoc.v:50413$2261 + attribute \src "libresoc.v:187330.14-187330.43" + process $proc$libresoc.v:187330$14140 assign { } { } - assign $1\raw_insn_i[31:0] 0 + assign $1\src_r3[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \raw_insn_i $1\raw_insn_i[31:0] - end - attribute \src "libresoc.v:50847.3-50848.41" - process $proc$libresoc.v:50847$1665 - assign { } { } - assign $0\dec2_cur_dec[63:0] \dec2_cur_dec$next - sync posedge \clk - update \dec2_cur_dec $0\dec2_cur_dec[63:0] - end - attribute \src "libresoc.v:50849.3-50850.33" - process $proc$libresoc.v:50849$1666 - assign { } { } - assign $0\core_dec[63:0] \core_dec$next - sync posedge \clk - update \core_dec $0\core_dec[63:0] - end - attribute \src "libresoc.v:50851.3-50852.41" - process $proc$libresoc.v:50851$1667 - assign { } { } - assign $0\dec2_cur_msr[63:0] \dec2_cur_msr$next - sync posedge \clk - update \dec2_cur_msr $0\dec2_cur_msr[63:0] - end - attribute \src "libresoc.v:50853.3-50854.35" - process $proc$libresoc.v:50853$1668 - assign { } { } - assign $0\fsm_state[1:0] \fsm_state$next - sync posedge \clk - update \fsm_state $0\fsm_state[1:0] - end - attribute \src "libresoc.v:50855.3-50856.33" - process $proc$libresoc.v:50855$1669 - assign { } { } - assign $0\msr_read[0:0] \msr_read$next - sync posedge \clk - update \msr_read $0\msr_read[0:0] - end - attribute \src "libresoc.v:50857.3-50858.39" - process $proc$libresoc.v:50857$1670 - assign { } { } - assign $0\dec2_cur_pc[63:0] \dec2_cur_pc$next - sync posedge \clk - update \dec2_cur_pc $0\dec2_cur_pc[63:0] - end - attribute \src "libresoc.v:50859.3-50860.39" - process $proc$libresoc.v:50859$1671 - assign { } { } - assign $0\bigendian_i[0:0] \bigendian_i$next - sync posedge \clk - update \bigendian_i $0\bigendian_i[0:0] - end - attribute \src "libresoc.v:50861.3-50862.37" - process $proc$libresoc.v:50861$1672 - assign { } { } - assign $0\raw_insn_i[31:0] \raw_insn_i$next - sync posedge \clk - update \raw_insn_i $0\raw_insn_i[31:0] - end - attribute \src "libresoc.v:50863.3-50864.41" - process $proc$libresoc.v:50863$1673 - assign { } { } - assign $0\core_asmcode[7:0] \core_asmcode$next - sync posedge \clk - update \core_asmcode $0\core_asmcode[7:0] - end - attribute \src "libresoc.v:50865.3-50866.35" - process $proc$libresoc.v:50865$1674 - assign { } { } - assign $0\core_rego[4:0] \core_rego$next - sync posedge \clk - update \core_rego $0\core_rego[4:0] - end - attribute \src "libresoc.v:50867.3-50868.41" - process $proc$libresoc.v:50867$1675 - assign { } { } - assign $0\core_rego_ok[0:0] \core_rego_ok$next - sync posedge \clk - update \core_rego_ok $0\core_rego_ok[0:0] - end - attribute \src "libresoc.v:50869.3-50870.45" - process $proc$libresoc.v:50869$1676 - assign { } { } - assign $0\fsm_state$131[1:0]$1677 \fsm_state$131$next - sync posedge \clk - update \fsm_state$131 $0\fsm_state$131[1:0]$1677 - end - attribute \src "libresoc.v:50871.3-50872.31" - process $proc$libresoc.v:50871$1678 - assign { } { } - assign $0\core_ea[4:0] \core_ea$next - sync posedge \clk - update \core_ea $0\core_ea[4:0] - end - attribute \src "libresoc.v:50873.3-50874.37" - process $proc$libresoc.v:50873$1679 - assign { } { } - assign $0\core_ea_ok[0:0] \core_ea_ok$next - sync posedge \clk - update \core_ea_ok $0\core_ea_ok[0:0] - end - attribute \src "libresoc.v:50875.3-50876.35" - process $proc$libresoc.v:50875$1680 - assign { } { } - assign $0\core_reg1[4:0] \core_reg1$next - sync posedge \clk - update \core_reg1 $0\core_reg1[4:0] + update \src_r3 $1\src_r3[63:0] end - attribute \src "libresoc.v:50877.3-50878.41" - process $proc$libresoc.v:50877$1681 + attribute \src "libresoc.v:187396.3-187397.39" + process $proc$libresoc.v:187396$13948 assign { } { } - assign $0\core_reg1_ok[0:0] \core_reg1_ok$next - sync posedge \clk - update \core_reg1_ok $0\core_reg1_ok[0:0] - end - attribute \src "libresoc.v:50879.3-50880.35" - process $proc$libresoc.v:50879$1682 - assign { } { } - assign $0\core_reg2[4:0] \core_reg2$next - sync posedge \clk - update \core_reg2 $0\core_reg2[4:0] - end - attribute \src "libresoc.v:50881.3-50882.41" - process $proc$libresoc.v:50881$1683 - assign { } { } - assign $0\core_reg2_ok[0:0] \core_reg2_ok$next - sync posedge \clk - update \core_reg2_ok $0\core_reg2_ok[0:0] - end - attribute \src "libresoc.v:50883.3-50884.35" - process $proc$libresoc.v:50883$1684 - assign { } { } - assign $0\core_reg3[4:0] \core_reg3$next - sync posedge \clk - update \core_reg3 $0\core_reg3[4:0] - end - attribute \src "libresoc.v:50885.3-50886.41" - process $proc$libresoc.v:50885$1685 - assign { } { } - assign $0\core_reg3_ok[0:0] \core_reg3_ok$next - sync posedge \clk - update \core_reg3_ok $0\core_reg3_ok[0:0] - end - attribute \src "libresoc.v:50887.3-50888.35" - process $proc$libresoc.v:50887$1686 - assign { } { } - assign $0\core_spro[9:0] \core_spro$next - sync posedge \clk - update \core_spro $0\core_spro[9:0] - end - attribute \src "libresoc.v:50889.3-50890.41" - process $proc$libresoc.v:50889$1687 - assign { } { } - assign $0\core_spro_ok[0:0] \core_spro_ok$next - sync posedge \clk - update \core_spro_ok $0\core_spro_ok[0:0] - end - attribute \src "libresoc.v:50891.3-50892.39" - process $proc$libresoc.v:50891$1688 - assign { } { } - assign $0\d_xer_delay[0:0] \d_xer_delay$next - sync posedge \clk - update \d_xer_delay $0\d_xer_delay[0:0] - end - attribute \src "libresoc.v:50893.3-50894.35" - process $proc$libresoc.v:50893$1689 - assign { } { } - assign $0\core_spr1[9:0] \core_spr1$next - sync posedge \clk - update \core_spr1 $0\core_spr1[9:0] - end - attribute \src "libresoc.v:50895.3-50896.41" - process $proc$libresoc.v:50895$1690 - assign { } { } - assign $0\core_spr1_ok[0:0] \core_spr1_ok$next - sync posedge \clk - update \core_spr1_ok $0\core_spr1_ok[0:0] - end - attribute \src "libresoc.v:50897.3-50898.39" - process $proc$libresoc.v:50897$1691 - assign { } { } - assign $0\core_xer_in[2:0] \core_xer_in$next - sync posedge \clk - update \core_xer_in $0\core_xer_in[2:0] - end - attribute \src "libresoc.v:50899.3-50900.41" - process $proc$libresoc.v:50899$1692 - assign { } { } - assign $0\core_xer_out[0:0] \core_xer_out$next - sync posedge \clk - update \core_xer_out $0\core_xer_out[0:0] - end - attribute \src "libresoc.v:50901.3-50902.37" - process $proc$libresoc.v:50901$1693 - assign { } { } - assign $0\core_fast1[2:0] \core_fast1$next - sync posedge \clk - update \core_fast1 $0\core_fast1[2:0] - end - attribute \src "libresoc.v:50903.3-50904.43" - process $proc$libresoc.v:50903$1694 - assign { } { } - assign $0\core_fast1_ok[0:0] \core_fast1_ok$next - sync posedge \clk - update \core_fast1_ok $0\core_fast1_ok[0:0] - end - attribute \src "libresoc.v:50905.3-50906.37" - process $proc$libresoc.v:50905$1695 - assign { } { } - assign $0\core_fast2[2:0] \core_fast2$next - sync posedge \clk - update \core_fast2 $0\core_fast2[2:0] - end - attribute \src "libresoc.v:50907.3-50908.43" - process $proc$libresoc.v:50907$1696 - assign { } { } - assign $0\core_fast2_ok[0:0] \core_fast2_ok$next - sync posedge \clk - update \core_fast2_ok $0\core_fast2_ok[0:0] - end - attribute \src "libresoc.v:50909.3-50910.39" - process $proc$libresoc.v:50909$1697 - assign { } { } - assign $0\core_fasto1[2:0] \core_fasto1$next - sync posedge \clk - update \core_fasto1 $0\core_fasto1[2:0] - end - attribute \src "libresoc.v:50911.3-50912.45" - process $proc$libresoc.v:50911$1698 - assign { } { } - assign $0\core_fasto1_ok[0:0] \core_fasto1_ok$next - sync posedge \clk - update \core_fasto1_ok $0\core_fasto1_ok[0:0] - end - attribute \src "libresoc.v:50913.3-50914.37" - process $proc$libresoc.v:50913$1699 - assign { } { } - assign $0\d_cr_delay[0:0] \d_cr_delay$next - sync posedge \clk - update \d_cr_delay $0\d_cr_delay[0:0] - end - attribute \src "libresoc.v:50915.3-50916.39" - process $proc$libresoc.v:50915$1700 - assign { } { } - assign $0\core_fasto2[2:0] \core_fasto2$next - sync posedge \clk - update \core_fasto2 $0\core_fasto2[2:0] - end - attribute \src "libresoc.v:50917.3-50918.45" - process $proc$libresoc.v:50917$1701 - assign { } { } - assign $0\core_fasto2_ok[0:0] \core_fasto2_ok$next - sync posedge \clk - update \core_fasto2_ok $0\core_fasto2_ok[0:0] - end - attribute \src "libresoc.v:50919.3-50920.39" - process $proc$libresoc.v:50919$1702 - assign { } { } - assign $0\core_cr_in1[2:0] \core_cr_in1$next - sync posedge \clk - update \core_cr_in1 $0\core_cr_in1[2:0] + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:50921.3-50922.45" - process $proc$libresoc.v:50921$1703 + attribute \src "libresoc.v:187398.3-187399.43" + process $proc$libresoc.v:187398$13949 assign { } { } - assign $0\core_cr_in1_ok[0:0] \core_cr_in1_ok$next - sync posedge \clk - update \core_cr_in1_ok $0\core_cr_in1_ok[0:0] + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:50923.3-50924.39" - process $proc$libresoc.v:50923$1704 + attribute \src "libresoc.v:187400.3-187401.29" + process $proc$libresoc.v:187400$13950 assign { } { } - assign $0\core_cr_in2[2:0] \core_cr_in2$next - sync posedge \clk - update \core_cr_in2 $0\core_cr_in2[2:0] + assign $0\src_r3[63:0] \src_r3$next + sync posedge \coresync_clk + update \src_r3 $0\src_r3[63:0] end - attribute \src "libresoc.v:50925.3-50926.45" - process $proc$libresoc.v:50925$1705 + attribute \src "libresoc.v:187402.3-187403.29" + process $proc$libresoc.v:187402$13951 assign { } { } - assign $0\core_cr_in2_ok[0:0] \core_cr_in2_ok$next - sync posedge \clk - update \core_cr_in2_ok $0\core_cr_in2_ok[0:0] + assign $0\src_r2[63:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:50927.3-50928.47" - process $proc$libresoc.v:50927$1706 + attribute \src "libresoc.v:187404.3-187405.29" + process $proc$libresoc.v:187404$13952 assign { } { } - assign $0\core_cr_in2$48[2:0]$1707 \core_cr_in2$48$next - sync posedge \clk - update \core_cr_in2$48 $0\core_cr_in2$48[2:0]$1707 + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:50929.3-50930.53" - process $proc$libresoc.v:50929$1708 + attribute \src "libresoc.v:187406.3-187407.29" + process $proc$libresoc.v:187406$13953 assign { } { } - assign $0\core_cr_in2_ok$49[0:0]$1709 \core_cr_in2_ok$49$next - sync posedge \clk - update \core_cr_in2_ok$49 $0\core_cr_in2_ok$49[0:0]$1709 + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:50931.3-50932.39" - process $proc$libresoc.v:50931$1710 + attribute \src "libresoc.v:187408.3-187409.41" + process $proc$libresoc.v:187408$13954 assign { } { } - assign $0\core_cr_out[2:0] \core_cr_out$next - sync posedge \clk - update \core_cr_out $0\core_cr_out[2:0] + assign $0\data_r4__msr[63:0] \data_r4__msr$next + sync posedge \coresync_clk + update \data_r4__msr $0\data_r4__msr[63:0] end - attribute \src "libresoc.v:50933.3-50934.45" - process $proc$libresoc.v:50933$1711 + attribute \src "libresoc.v:187410.3-187411.47" + process $proc$libresoc.v:187410$13955 assign { } { } - assign $0\core_cr_out_ok[0:0] \core_cr_out_ok$next - sync posedge \clk - update \core_cr_out_ok $0\core_cr_out_ok[0:0] + assign $0\data_r4__msr_ok[0:0] \data_r4__msr_ok$next + sync posedge \coresync_clk + update \data_r4__msr_ok $0\data_r4__msr_ok[0:0] end - attribute \src "libresoc.v:50935.3-50936.39" - process $proc$libresoc.v:50935$1712 + attribute \src "libresoc.v:187412.3-187413.41" + process $proc$libresoc.v:187412$13956 assign { } { } - assign $0\d_reg_delay[0:0] \d_reg_delay$next - sync posedge \clk - update \d_reg_delay $0\d_reg_delay[0:0] + assign $0\data_r3__nia[63:0] \data_r3__nia$next + sync posedge \coresync_clk + update \data_r3__nia $0\data_r3__nia[63:0] end - attribute \src "libresoc.v:50937.3-50938.43" - process $proc$libresoc.v:50937$1713 + attribute \src "libresoc.v:187414.3-187415.47" + process $proc$libresoc.v:187414$13957 assign { } { } - assign $0\core_core_msr[63:0] \core_core_msr$next - sync posedge \clk - update \core_core_msr $0\core_core_msr[63:0] + assign $0\data_r3__nia_ok[0:0] \data_r3__nia_ok$next + sync posedge \coresync_clk + update \data_r3__nia_ok $0\data_r3__nia_ok[0:0] end - attribute \src "libresoc.v:50939.3-50940.43" - process $proc$libresoc.v:50939$1714 + attribute \src "libresoc.v:187416.3-187417.45" + process $proc$libresoc.v:187416$13958 assign { } { } - assign $0\core_core_cia[63:0] \core_core_cia$next - sync posedge \clk - update \core_core_cia $0\core_core_cia[63:0] + assign $0\data_r2__fast2[63:0] \data_r2__fast2$next + sync posedge \coresync_clk + update \data_r2__fast2 $0\data_r2__fast2[63:0] end - attribute \src "libresoc.v:50941.3-50942.45" - process $proc$libresoc.v:50941$1715 + attribute \src "libresoc.v:187418.3-187419.51" + process $proc$libresoc.v:187418$13959 assign { } { } - assign $0\core_core_insn[31:0] \core_core_insn$next - sync posedge \clk - update \core_core_insn $0\core_core_insn[31:0] + assign $0\data_r2__fast2_ok[0:0] \data_r2__fast2_ok$next + sync posedge \coresync_clk + update \data_r2__fast2_ok $0\data_r2__fast2_ok[0:0] end - attribute \src "libresoc.v:50943.3-50944.55" - process $proc$libresoc.v:50943$1716 + attribute \src "libresoc.v:187420.3-187421.45" + process $proc$libresoc.v:187420$13960 assign { } { } - assign $0\core_core_insn_type[6:0] \core_core_insn_type$next - sync posedge \clk - update \core_core_insn_type $0\core_core_insn_type[6:0] + assign $0\data_r1__fast1[63:0] \data_r1__fast1$next + sync posedge \coresync_clk + update \data_r1__fast1 $0\data_r1__fast1[63:0] end - attribute \src "libresoc.v:50945.3-50946.51" - process $proc$libresoc.v:50945$1717 + attribute \src "libresoc.v:187422.3-187423.51" + process $proc$libresoc.v:187422$13961 assign { } { } - assign $0\core_core_fn_unit[11:0] \core_core_fn_unit$next - sync posedge \clk - update \core_core_fn_unit $0\core_core_fn_unit[11:0] + assign $0\data_r1__fast1_ok[0:0] \data_r1__fast1_ok$next + sync posedge \coresync_clk + update \data_r1__fast1_ok $0\data_r1__fast1_ok[0:0] end - attribute \src "libresoc.v:50947.3-50948.41" - process $proc$libresoc.v:50947$1718 + attribute \src "libresoc.v:187424.3-187425.37" + process $proc$libresoc.v:187424$13962 assign { } { } - assign $0\core_core_lk[0:0] \core_core_lk$next - sync posedge \clk - update \core_core_lk $0\core_core_lk[0:0] + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:50949.3-50950.41" - process $proc$libresoc.v:50949$1719 + attribute \src "libresoc.v:187426.3-187427.43" + process $proc$libresoc.v:187426$13963 assign { } { } - assign $0\core_core_rc[0:0] \core_core_rc$next - sync posedge \clk - update \core_core_rc $0\core_core_rc[0:0] + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:50951.3-50952.47" - process $proc$libresoc.v:50951$1720 + attribute \src "libresoc.v:187428.3-187429.73" + process $proc$libresoc.v:187428$13964 assign { } { } - assign $0\core_core_rc_ok[0:0] \core_core_rc_ok$next - sync posedge \clk - update \core_core_rc_ok $0\core_core_rc_ok[0:0] + assign $0\alu_trap0_trap_op__insn_type[6:0] \alu_trap0_trap_op__insn_type$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__insn_type $0\alu_trap0_trap_op__insn_type[6:0] end - attribute \src "libresoc.v:50953.3-50954.41" - process $proc$libresoc.v:50953$1721 + attribute \src "libresoc.v:187430.3-187431.69" + process $proc$libresoc.v:187430$13965 assign { } { } - assign $0\core_core_oe[0:0] \core_core_oe$next - sync posedge \clk - update \core_core_oe $0\core_core_oe[0:0] + assign $0\alu_trap0_trap_op__fn_unit[11:0] \alu_trap0_trap_op__fn_unit$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__fn_unit $0\alu_trap0_trap_op__fn_unit[11:0] end - attribute \src "libresoc.v:50955.3-50956.47" - process $proc$libresoc.v:50955$1722 + attribute \src "libresoc.v:187432.3-187433.63" + process $proc$libresoc.v:187432$13966 assign { } { } - assign $0\core_core_oe_ok[0:0] \core_core_oe_ok$next - sync posedge \clk - update \core_core_oe_ok $0\core_core_oe_ok[0:0] + assign $0\alu_trap0_trap_op__insn[31:0] \alu_trap0_trap_op__insn$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__insn $0\alu_trap0_trap_op__insn[31:0] end - attribute \src "libresoc.v:50957.3-50958.29" - process $proc$libresoc.v:50957$1723 + attribute \src "libresoc.v:187434.3-187435.61" + process $proc$libresoc.v:187434$13967 assign { } { } - assign $0\ilatch[31:0] \ilatch$next - sync posedge \clk - update \ilatch $0\ilatch[31:0] + assign $0\alu_trap0_trap_op__msr[63:0] \alu_trap0_trap_op__msr$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__msr $0\alu_trap0_trap_op__msr[63:0] end - attribute \src "libresoc.v:50959.3-50960.59" - process $proc$libresoc.v:50959$1724 + attribute \src "libresoc.v:187436.3-187437.61" + process $proc$libresoc.v:187436$13968 assign { } { } - assign $0\core_core_input_carry[1:0] \core_core_input_carry$next - sync posedge \clk - update \core_core_input_carry $0\core_core_input_carry[1:0] + assign $0\alu_trap0_trap_op__cia[63:0] \alu_trap0_trap_op__cia$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__cia $0\alu_trap0_trap_op__cia[63:0] end - attribute \src "libresoc.v:50961.3-50962.53" - process $proc$libresoc.v:50961$1725 + attribute \src "libresoc.v:187438.3-187439.71" + process $proc$libresoc.v:187438$13969 assign { } { } - assign $0\core_core_traptype[7:0] \core_core_traptype$next - sync posedge \clk - update \core_core_traptype $0\core_core_traptype[7:0] + assign $0\alu_trap0_trap_op__is_32bit[0:0] \alu_trap0_trap_op__is_32bit$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__is_32bit $0\alu_trap0_trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:50963.3-50964.61" - process $proc$libresoc.v:50963$1726 + attribute \src "libresoc.v:187440.3-187441.71" + process $proc$libresoc.v:187440$13970 assign { } { } - assign $0\core_core_exc_$signal[0:0]$1727 \core_core_exc_$signal$next - sync posedge \clk - update \core_core_exc_$signal $0\core_core_exc_$signal[0:0]$1727 + assign $0\alu_trap0_trap_op__traptype[7:0] \alu_trap0_trap_op__traptype$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__traptype $0\alu_trap0_trap_op__traptype[7:0] end - attribute \src "libresoc.v:50965.3-50966.67" - process $proc$libresoc.v:50965$1728 + attribute \src "libresoc.v:187442.3-187443.71" + process $proc$libresoc.v:187442$13971 assign { } { } - assign $0\core_core_exc_$signal$50[0:0]$1729 \core_core_exc_$signal$50$next - sync posedge \clk - update \core_core_exc_$signal$50 $0\core_core_exc_$signal$50[0:0]$1729 + assign $0\alu_trap0_trap_op__trapaddr[12:0] \alu_trap0_trap_op__trapaddr$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__trapaddr $0\alu_trap0_trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:50967.3-50968.67" - process $proc$libresoc.v:50967$1730 + attribute \src "libresoc.v:187444.3-187445.71" + process $proc$libresoc.v:187444$13972 assign { } { } - assign $0\core_core_exc_$signal$51[0:0]$1731 \core_core_exc_$signal$51$next - sync posedge \clk - update \core_core_exc_$signal$51 $0\core_core_exc_$signal$51[0:0]$1731 + assign $0\alu_trap0_trap_op__ldst_exc[7:0] \alu_trap0_trap_op__ldst_exc$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__ldst_exc $0\alu_trap0_trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:50969.3-50970.67" - process $proc$libresoc.v:50969$1732 + attribute \src "libresoc.v:187446.3-187447.39" + process $proc$libresoc.v:187446$13973 assign { } { } - assign $0\core_core_exc_$signal$52[0:0]$1733 \core_core_exc_$signal$52$next - sync posedge \clk - update \core_core_exc_$signal$52 $0\core_core_exc_$signal$52[0:0]$1733 + assign $0\req_l_r_req[4:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[4:0] end - attribute \src "libresoc.v:50971.3-50972.67" - process $proc$libresoc.v:50971$1734 + attribute \src "libresoc.v:187448.3-187449.39" + process $proc$libresoc.v:187448$13974 assign { } { } - assign $0\core_core_exc_$signal$53[0:0]$1735 \core_core_exc_$signal$53$next - sync posedge \clk - update \core_core_exc_$signal$53 $0\core_core_exc_$signal$53[0:0]$1735 + assign $0\req_l_s_req[4:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[4:0] end - attribute \src "libresoc.v:50973.3-50974.67" - process $proc$libresoc.v:50973$1736 + attribute \src "libresoc.v:187450.3-187451.39" + process $proc$libresoc.v:187450$13975 assign { } { } - assign $0\core_core_exc_$signal$54[0:0]$1737 \core_core_exc_$signal$54$next - sync posedge \clk - update \core_core_exc_$signal$54 $0\core_core_exc_$signal$54[0:0]$1737 + assign $0\src_l_r_src[3:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[3:0] end - attribute \src "libresoc.v:50975.3-50976.67" - process $proc$libresoc.v:50975$1738 + attribute \src "libresoc.v:187452.3-187453.39" + process $proc$libresoc.v:187452$13976 assign { } { } - assign $0\core_core_exc_$signal$55[0:0]$1739 \core_core_exc_$signal$55$next - sync posedge \clk - update \core_core_exc_$signal$55 $0\core_core_exc_$signal$55[0:0]$1739 + assign $0\src_l_s_src[3:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[3:0] end - attribute \src "libresoc.v:50977.3-50978.67" - process $proc$libresoc.v:50977$1740 + attribute \src "libresoc.v:187454.3-187455.39" + process $proc$libresoc.v:187454$13977 assign { } { } - assign $0\core_core_exc_$signal$56[0:0]$1741 \core_core_exc_$signal$56$next - sync posedge \clk - update \core_core_exc_$signal$56 $0\core_core_exc_$signal$56[0:0]$1741 + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:50979.3-50980.31" - process $proc$libresoc.v:50979$1742 + attribute \src "libresoc.v:187456.3-187457.39" + process $proc$libresoc.v:187456$13978 assign { } { } - assign $0\core_pc[63:0] \core_pc$next - sync posedge \clk - update \core_pc $0\core_pc[63:0] + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:50981.3-50982.53" - process $proc$libresoc.v:50981$1743 + attribute \src "libresoc.v:187458.3-187459.39" + process $proc$libresoc.v:187458$13979 assign { } { } - assign $0\core_core_trapaddr[12:0] \core_core_trapaddr$next - sync posedge \clk - update \core_core_trapaddr $0\core_core_trapaddr[12:0] + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:50983.3-50984.47" - process $proc$libresoc.v:50983$1744 + attribute \src "libresoc.v:187460.3-187461.39" + process $proc$libresoc.v:187460$13980 assign { } { } - assign $0\core_core_cr_rd[7:0] \core_core_cr_rd$next - sync posedge \clk - update \core_core_cr_rd $0\core_core_cr_rd[7:0] + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:50985.3-50986.53" - process $proc$libresoc.v:50985$1745 + attribute \src "libresoc.v:187462.3-187463.41" + process $proc$libresoc.v:187462$13981 assign { } { } - assign $0\core_core_cr_rd_ok[0:0] \core_core_cr_rd_ok$next - sync posedge \clk - update \core_core_cr_rd_ok $0\core_core_cr_rd_ok[0:0] + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:50987.3-50988.47" - process $proc$libresoc.v:50987$1746 + attribute \src "libresoc.v:187464.3-187465.41" + process $proc$libresoc.v:187464$13982 assign { } { } - assign $0\core_core_cr_wr[7:0] \core_core_cr_wr$next - sync posedge \clk - update \core_core_cr_wr $0\core_core_cr_wr[7:0] + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:50989.3-50990.53" - process $proc$libresoc.v:50989$1747 + attribute \src "libresoc.v:187466.3-187467.37" + process $proc$libresoc.v:187466$13983 assign { } { } - assign $0\core_core_cr_wr_ok[0:0] \core_core_cr_wr_ok$next - sync posedge \clk - update \core_core_cr_wr_ok $0\core_core_cr_wr_ok[0:0] + assign $0\prev_wr_go[4:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[4:0] end - attribute \src "libresoc.v:50991.3-50992.53" - process $proc$libresoc.v:50991$1748 + attribute \src "libresoc.v:187468.3-187469.41" + process $proc$libresoc.v:187468$13984 assign { } { } - assign $0\core_core_is_32bit[0:0] \core_core_is_32bit$next - sync posedge \clk - update \core_core_is_32bit $0\core_core_is_32bit[0:0] + assign $0\alu_done_dly[0:0] \alu_trap0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:50993.3-50994.37" - process $proc$libresoc.v:50993$1749 + attribute \src "libresoc.v:187470.3-187471.25" + process $proc$libresoc.v:187470$13985 assign { } { } - assign $0\pc_changed[0:0] \pc_changed$next - sync posedge \clk - update \pc_changed $0\pc_changed[0:0] + assign $0\all_rd_dly[0:0] \$11 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:50995.3-50996.39" - process $proc$libresoc.v:50995$1750 + attribute \src "libresoc.v:187551.3-187560.6" + process $proc$libresoc.v:187551$13986 assign { } { } - assign $0\pc_ok_delay[0:0] \pc_ok_delay$next - sync posedge \clk - update \pc_ok_delay $0\pc_ok_delay[0:0] - end - attribute \src "libresoc.v:50997.3-50998.30" - process $proc$libresoc.v:50997$1751 assign { } { } - assign $0\cu_st__rel_o_dly[0:0] 1'0 - sync posedge \clk - update \cu_st__rel_o_dly $0\cu_st__rel_o_dly[0:0] + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:187552.5-187552.29" + switch \initial + attribute \src "libresoc.v:187552.9-187552.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$55 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$47 + end + sync always + update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:50999.3-51000.27" - process $proc$libresoc.v:50999$1752 + attribute \src "libresoc.v:187561.3-187569.6" + process $proc$libresoc.v:187561$13987 assign { } { } - assign $0\delay[1:0] \delay$next - sync posedge \por_clk - update \delay $0\delay[1:0] - end - attribute \src "libresoc.v:51001.3-51002.33" - process $proc$libresoc.v:51001$1753 assign { } { } - assign $0\core_msr[63:0] \core_msr$next - sync posedge \clk - update \core_msr $0\core_msr[63:0] + assign $0\rok_l_s_rdok$next[0:0]$13988 $1\rok_l_s_rdok$next[0:0]$13989 + attribute \src "libresoc.v:187562.5-187562.29" + switch \initial + attribute \src "libresoc.v:187562.9-187562.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$13989 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$13989 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$13988 end - attribute \src "libresoc.v:51003.3-51004.43" - process $proc$libresoc.v:51003$1754 + attribute \src "libresoc.v:187570.3-187578.6" + process $proc$libresoc.v:187570$13990 assign { } { } - assign $0\dec2_cur_eint[0:0] \dec2_cur_eint$next - sync posedge \clk - update \dec2_cur_eint $0\dec2_cur_eint[0:0] - end - attribute \src "libresoc.v:51005.3-51006.47" - process $proc$libresoc.v:51005$1755 assign { } { } - assign $0\jtag_dmi0__dout[63:0] \jtag_dmi0__dout$next - sync posedge \clk - update \jtag_dmi0__dout $0\jtag_dmi0__dout[63:0] + assign $0\rok_l_r_rdok$next[0:0]$13991 $1\rok_l_r_rdok$next[0:0]$13992 + attribute \src "libresoc.v:187571.5-187571.29" + switch \initial + attribute \src "libresoc.v:187571.9-187571.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$13992 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$13992 \$65 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$13991 end - attribute \src "libresoc.v:51007.3-51008.49" - process $proc$libresoc.v:51007$1756 + attribute \src "libresoc.v:187579.3-187587.6" + process $proc$libresoc.v:187579$13993 assign { } { } - assign $0\jtag_dmi0__ack_o[0:0] \jtag_dmi0__ack_o$next - sync posedge \clk - update \jtag_dmi0__ack_o $0\jtag_dmi0__ack_o[0:0] - end - attribute \src "libresoc.v:51009.3-51010.39" - process $proc$libresoc.v:51009$1757 assign { } { } - assign $0\dbg_dmi_din[63:0] \dbg_dmi_din$next - sync posedge \clk - update \dbg_dmi_din $0\dbg_dmi_din[63:0] + assign $0\rst_l_s_rst$next[0:0]$13994 $1\rst_l_s_rst$next[0:0]$13995 + attribute \src "libresoc.v:187580.5-187580.29" + switch \initial + attribute \src "libresoc.v:187580.9-187580.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$13995 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$13995 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$13994 end - attribute \src "libresoc.v:51011.3-51012.41" - process $proc$libresoc.v:51011$1758 + attribute \src "libresoc.v:187588.3-187596.6" + process $proc$libresoc.v:187588$13996 assign { } { } - assign $0\dbg_dmi_we_i[0:0] \dbg_dmi_we_i$next - sync posedge \clk - update \dbg_dmi_we_i $0\dbg_dmi_we_i[0:0] - end - attribute \src "libresoc.v:51013.3-51014.43" - process $proc$libresoc.v:51013$1759 assign { } { } - assign $0\dbg_dmi_req_i[0:0] \dbg_dmi_req_i$next - sync posedge \clk - update \dbg_dmi_req_i $0\dbg_dmi_req_i[0:0] + assign $0\rst_l_r_rst$next[0:0]$13997 $1\rst_l_r_rst$next[0:0]$13998 + attribute \src "libresoc.v:187589.5-187589.29" + switch \initial + attribute \src "libresoc.v:187589.9-187589.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$13998 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$13998 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$13997 end - attribute \src "libresoc.v:51015.3-51016.45" - process $proc$libresoc.v:51015$1760 + attribute \src "libresoc.v:187597.3-187605.6" + process $proc$libresoc.v:187597$13999 assign { } { } - assign $0\dbg_dmi_addr_i[3:0] \dbg_dmi_addr_i$next - sync posedge \clk - update \dbg_dmi_addr_i $0\dbg_dmi_addr_i[3:0] - end - attribute \src "libresoc.v:51017.3-51018.35" - process $proc$libresoc.v:51017$1761 assign { } { } - assign $0\core_eint[0:0] \core_eint$next - sync posedge \clk - update \core_eint $0\core_eint[0:0] + assign $0\opc_l_s_opc$next[0:0]$14000 $1\opc_l_s_opc$next[0:0]$14001 + attribute \src "libresoc.v:187598.5-187598.29" + switch \initial + attribute \src "libresoc.v:187598.9-187598.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$14001 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$14001 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$14000 end - attribute \src "libresoc.v:51493.3-51501.6" - process $proc$libresoc.v:51493$1762 + attribute \src "libresoc.v:187606.3-187614.6" + process $proc$libresoc.v:187606$14002 assign { } { } assign { } { } - assign $0\dbg_dmi_addr_i$next[3:0]$1763 $1\dbg_dmi_addr_i$next[3:0]$1764 - attribute \src "libresoc.v:51494.5-51494.29" + assign $0\opc_l_r_opc$next[0:0]$14003 $1\opc_l_r_opc$next[0:0]$14004 + attribute \src "libresoc.v:187607.5-187607.29" switch \initial - attribute \src "libresoc.v:51494.9-51494.17" + attribute \src "libresoc.v:187607.9-187607.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_addr_i$next[3:0]$1764 4'0000 + assign $1\opc_l_r_opc$next[0:0]$14004 1'1 case - assign $1\dbg_dmi_addr_i$next[3:0]$1764 \jtag_dmi0__addr_i + assign $1\opc_l_r_opc$next[0:0]$14004 \req_done end sync always - update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$1763 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$14003 end - attribute \src "libresoc.v:51502.3-51510.6" - process $proc$libresoc.v:51502$1765 + attribute \src "libresoc.v:187615.3-187623.6" + process $proc$libresoc.v:187615$14005 assign { } { } assign { } { } - assign $0\dbg_dmi_req_i$next[0:0]$1766 $1\dbg_dmi_req_i$next[0:0]$1767 - attribute \src "libresoc.v:51503.5-51503.29" + assign $0\src_l_s_src$next[3:0]$14006 $1\src_l_s_src$next[3:0]$14007 + attribute \src "libresoc.v:187616.5-187616.29" switch \initial - attribute \src "libresoc.v:51503.9-51503.17" + attribute \src "libresoc.v:187616.9-187616.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_req_i$next[0:0]$1767 1'0 + assign $1\src_l_s_src$next[3:0]$14007 4'0000 case - assign $1\dbg_dmi_req_i$next[0:0]$1767 \jtag_dmi0__req_i + assign $1\src_l_s_src$next[3:0]$14007 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$1766 + update \src_l_s_src$next $0\src_l_s_src$next[3:0]$14006 end - attribute \src "libresoc.v:51511.3-51531.6" - process $proc$libresoc.v:51511$1768 + attribute \src "libresoc.v:187624.3-187632.6" + process $proc$libresoc.v:187624$14008 assign { } { } assign { } { } - assign { } { } - assign $0\dec2_cur_msr$next[63:0]$1769 $3\dec2_cur_msr$next[63:0]$1772 - attribute \src "libresoc.v:51512.5-51512.29" + assign $0\src_l_r_src$next[3:0]$14009 $1\src_l_r_src$next[3:0]$14010 + attribute \src "libresoc.v:187625.5-187625.29" switch \initial - attribute \src "libresoc.v:51512.9-51512.17" + attribute \src "libresoc.v:187625.9-187625.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 1'1 assign { } { } - assign $1\dec2_cur_msr$next[63:0]$1770 $2\dec2_cur_msr$next[63:0]$1771 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275" - switch \$115 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dec2_cur_msr$next[63:0]$1771 \msr__data_o - case - assign $2\dec2_cur_msr$next[63:0]$1771 \dec2_cur_msr - end + assign $1\src_l_r_src$next[3:0]$14010 4'1111 + case + assign $1\src_l_r_src$next[3:0]$14010 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[3:0]$14009 + end + attribute \src "libresoc.v:187633.3-187641.6" + process $proc$libresoc.v:187633$14011 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[4:0]$14012 $1\req_l_s_req$next[4:0]$14013 + attribute \src "libresoc.v:187634.5-187634.29" + switch \initial + attribute \src "libresoc.v:187634.9-187634.17" + case 1'1 case - assign $1\dec2_cur_msr$next[63:0]$1770 \dec2_cur_msr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dec2_cur_msr$next[63:0]$1772 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\req_l_s_req$next[4:0]$14013 5'00000 case - assign $3\dec2_cur_msr$next[63:0]$1772 $1\dec2_cur_msr$next[63:0]$1770 + assign $1\req_l_s_req$next[4:0]$14013 \$67 end sync always - update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$1769 + update \req_l_s_req$next $0\req_l_s_req$next[4:0]$14012 end - attribute \src "libresoc.v:51532.3-51550.6" - process $proc$libresoc.v:51532$1773 + attribute \src "libresoc.v:187642.3-187650.6" + process $proc$libresoc.v:187642$14014 assign { } { } assign { } { } - assign $0\dec2_raw_opcode_in[31:0] $1\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:51533.5-51533.29" + assign $0\req_l_r_req$next[4:0]$14015 $1\req_l_r_req$next[4:0]$14016 + attribute \src "libresoc.v:187643.5-187643.29" switch \initial - attribute \src "libresoc.v:51533.9-51533.17" + attribute \src "libresoc.v:187643.9-187643.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 1'1 assign { } { } - assign $1\dec2_raw_opcode_in[31:0] $2\dec2_raw_opcode_in[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\dec2_raw_opcode_in[31:0] 0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\dec2_raw_opcode_in[31:0] \$117 - end + assign $1\req_l_r_req$next[4:0]$14016 5'11111 case - assign $1\dec2_raw_opcode_in[31:0] 0 + assign $1\req_l_r_req$next[4:0]$14016 \$69 end sync always - update \dec2_raw_opcode_in $0\dec2_raw_opcode_in[31:0] + update \req_l_r_req$next $0\req_l_r_req$next[4:0]$14015 end - attribute \src "libresoc.v:51551.3-51582.6" - process $proc$libresoc.v:51551$1774 + attribute \src "libresoc.v:187651.3-187668.6" + process $proc$libresoc.v:187651$14017 + assign { } { } + assign { } { } + assign { } { } assign { } { } assign { } { } assign { } { } @@ -143736,2801 +393816,3292 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $0\core_dec$next[63:0]$1775 $3\core_dec$next[63:0]$1787 - assign $0\core_eint$next[0:0]$1776 $3\core_eint$next[0:0]$1788 - assign $0\core_msr$next[63:0]$1777 $3\core_msr$next[63:0]$1789 - assign $0\core_pc$next[63:0]$1778 $3\core_pc$next[63:0]$1790 - attribute \src "libresoc.v:51552.5-51552.29" + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_trap0_trap_op__cia$next[63:0]$14018 $1\alu_trap0_trap_op__cia$next[63:0]$14027 + assign $0\alu_trap0_trap_op__fn_unit$next[11:0]$14019 $1\alu_trap0_trap_op__fn_unit$next[11:0]$14028 + assign $0\alu_trap0_trap_op__insn$next[31:0]$14020 $1\alu_trap0_trap_op__insn$next[31:0]$14029 + assign $0\alu_trap0_trap_op__insn_type$next[6:0]$14021 $1\alu_trap0_trap_op__insn_type$next[6:0]$14030 + assign $0\alu_trap0_trap_op__is_32bit$next[0:0]$14022 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14031 + assign $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14023 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14032 + assign $0\alu_trap0_trap_op__msr$next[63:0]$14024 $1\alu_trap0_trap_op__msr$next[63:0]$14033 + assign $0\alu_trap0_trap_op__trapaddr$next[12:0]$14025 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14034 + assign $0\alu_trap0_trap_op__traptype$next[7:0]$14026 $1\alu_trap0_trap_op__traptype$next[7:0]$14035 + attribute \src "libresoc.v:187652.5-187652.29" switch \initial - attribute \src "libresoc.v:51552.9-51552.17" + attribute \src "libresoc.v:187652.9-187652.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\core_dec$next[63:0]$1779 $2\core_dec$next[63:0]$1783 - assign $1\core_eint$next[0:0]$1780 $2\core_eint$next[0:0]$1784 - assign $1\core_msr$next[63:0]$1781 $2\core_msr$next[63:0]$1785 - assign $1\core_pc$next[63:0]$1782 $2\core_pc$next[63:0]$1786 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\core_dec$next[63:0]$1783 \core_dec - assign $2\core_eint$next[0:0]$1784 \core_eint - assign $2\core_msr$next[63:0]$1785 \core_msr - assign $2\core_pc$next[63:0]$1786 \core_pc - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $2\core_dec$next[63:0]$1783 $2\core_eint$next[0:0]$1784 $2\core_msr$next[63:0]$1785 $2\core_pc$next[63:0]$1786 } { \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } - end - case - assign $1\core_dec$next[63:0]$1779 \core_dec - assign $1\core_eint$next[0:0]$1780 \core_eint - assign $1\core_msr$next[63:0]$1781 \core_msr - assign $1\core_pc$next[63:0]$1782 \core_pc - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $3\core_pc$next[63:0]$1790 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\core_msr$next[63:0]$1789 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\core_eint$next[0:0]$1788 1'0 - assign $3\core_dec$next[63:0]$1787 64'0000000000000000000000000000000000000000000000000000000000000000 + assign { } { } + assign { $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14032 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14034 $1\alu_trap0_trap_op__traptype$next[7:0]$14035 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14031 $1\alu_trap0_trap_op__cia$next[63:0]$14027 $1\alu_trap0_trap_op__msr$next[63:0]$14033 $1\alu_trap0_trap_op__insn$next[31:0]$14029 $1\alu_trap0_trap_op__fn_unit$next[11:0]$14028 $1\alu_trap0_trap_op__insn_type$next[6:0]$14030 } { \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type } case - assign $3\core_dec$next[63:0]$1787 $1\core_dec$next[63:0]$1779 - assign $3\core_eint$next[0:0]$1788 $1\core_eint$next[0:0]$1780 - assign $3\core_msr$next[63:0]$1789 $1\core_msr$next[63:0]$1781 - assign $3\core_pc$next[63:0]$1790 $1\core_pc$next[63:0]$1782 + assign $1\alu_trap0_trap_op__cia$next[63:0]$14027 \alu_trap0_trap_op__cia + assign $1\alu_trap0_trap_op__fn_unit$next[11:0]$14028 \alu_trap0_trap_op__fn_unit + assign $1\alu_trap0_trap_op__insn$next[31:0]$14029 \alu_trap0_trap_op__insn + assign $1\alu_trap0_trap_op__insn_type$next[6:0]$14030 \alu_trap0_trap_op__insn_type + assign $1\alu_trap0_trap_op__is_32bit$next[0:0]$14031 \alu_trap0_trap_op__is_32bit + assign $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14032 \alu_trap0_trap_op__ldst_exc + assign $1\alu_trap0_trap_op__msr$next[63:0]$14033 \alu_trap0_trap_op__msr + assign $1\alu_trap0_trap_op__trapaddr$next[12:0]$14034 \alu_trap0_trap_op__trapaddr + assign $1\alu_trap0_trap_op__traptype$next[7:0]$14035 \alu_trap0_trap_op__traptype end sync always - update \core_dec$next $0\core_dec$next[63:0]$1775 - update \core_eint$next $0\core_eint$next[0:0]$1776 - update \core_msr$next $0\core_msr$next[63:0]$1777 - update \core_pc$next $0\core_pc$next[63:0]$1778 + update \alu_trap0_trap_op__cia$next $0\alu_trap0_trap_op__cia$next[63:0]$14018 + update \alu_trap0_trap_op__fn_unit$next $0\alu_trap0_trap_op__fn_unit$next[11:0]$14019 + update \alu_trap0_trap_op__insn$next $0\alu_trap0_trap_op__insn$next[31:0]$14020 + update \alu_trap0_trap_op__insn_type$next $0\alu_trap0_trap_op__insn_type$next[6:0]$14021 + update \alu_trap0_trap_op__is_32bit$next $0\alu_trap0_trap_op__is_32bit$next[0:0]$14022 + update \alu_trap0_trap_op__ldst_exc$next $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14023 + update \alu_trap0_trap_op__msr$next $0\alu_trap0_trap_op__msr$next[63:0]$14024 + update \alu_trap0_trap_op__trapaddr$next $0\alu_trap0_trap_op__trapaddr$next[12:0]$14025 + update \alu_trap0_trap_op__traptype$next $0\alu_trap0_trap_op__traptype$next[7:0]$14026 end - attribute \src "libresoc.v:51583.3-51606.6" - process $proc$libresoc.v:51583$1791 + attribute \src "libresoc.v:187669.3-187690.6" + process $proc$libresoc.v:187669$14036 + assign { } { } + assign { } { } + assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\ilatch$next[31:0]$1792 $3\ilatch$next[31:0]$1795 - attribute \src "libresoc.v:51584.5-51584.29" + assign $0\data_r0__o$next[63:0]$14037 $2\data_r0__o$next[63:0]$14041 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$14038 $3\data_r0__o_ok$next[0:0]$14043 + attribute \src "libresoc.v:187670.5-187670.29" switch \initial - attribute \src "libresoc.v:51584.9-51584.17" + attribute \src "libresoc.v:187670.9-187670.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 1'1 assign { } { } - assign $1\ilatch$next[31:0]$1793 $2\ilatch$next[31:0]$1794 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\ilatch$next[31:0]$1794 \ilatch - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\ilatch$next[31:0]$1794 \$121 - end + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$14040 $1\data_r0__o$next[63:0]$14039 } { \o_ok \alu_trap0_o } case - assign $1\ilatch$next[31:0]$1793 \ilatch + assign $1\data_r0__o$next[63:0]$14039 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$14040 \data_r0__o_ok end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ilatch$next[31:0]$1795 0 - case - assign $3\ilatch$next[31:0]$1795 $1\ilatch$next[31:0]$1793 - end - sync always - update \ilatch$next $0\ilatch$next[31:0]$1792 - end - attribute \src "libresoc.v:51607.3-51626.6" - process $proc$libresoc.v:51607$1796 - assign { } { } - assign { } { } - assign $0\ivalid_i[0:0] $1\ivalid_i[0:0] - attribute \src "libresoc.v:51608.5-51608.29" - switch \initial - attribute \src "libresoc.v:51608.9-51608.17" - case 1'1 + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$14042 $2\data_r0__o$next[63:0]$14041 } 65'00000000000000000000000000000000000000000000000000000000000000000 case + assign $2\data_r0__o$next[63:0]$14041 $1\data_r0__o$next[63:0]$14039 + assign $2\data_r0__o_ok$next[0:0]$14042 $1\data_r0__o_ok$next[0:0]$14040 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\ivalid_i[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 1'1 assign { } { } - assign $1\ivalid_i[0:0] $2\ivalid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:307" - switch \$125 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ivalid_i[0:0] 1'1 - case - assign $2\ivalid_i[0:0] 1'0 - end + assign $3\data_r0__o_ok$next[0:0]$14043 1'0 case - assign $1\ivalid_i[0:0] 1'0 + assign $3\data_r0__o_ok$next[0:0]$14043 $2\data_r0__o_ok$next[0:0]$14042 end sync always - update \ivalid_i $0\ivalid_i[0:0] + update \data_r0__o$next $0\data_r0__o$next[63:0]$14037 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$14038 end - attribute \src "libresoc.v:51627.3-51637.6" - process $proc$libresoc.v:51627$1797 + attribute \src "libresoc.v:187691.3-187712.6" + process $proc$libresoc.v:187691$14044 assign { } { } assign { } { } - assign $0\issue_i[0:0] $1\issue_i[0:0] - attribute \src "libresoc.v:51628.5-51628.29" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__fast1$next[63:0]$14045 $2\data_r1__fast1$next[63:0]$14049 + assign { } { } + assign $0\data_r1__fast1_ok$next[0:0]$14046 $3\data_r1__fast1_ok$next[0:0]$14051 + attribute \src "libresoc.v:187692.5-187692.29" switch \initial - attribute \src "libresoc.v:51628.9-51628.17" + attribute \src "libresoc.v:187692.9-187692.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 1'1 + assign { } { } assign { } { } - assign $1\issue_i[0:0] 1'1 + assign { $1\data_r1__fast1_ok$next[0:0]$14048 $1\data_r1__fast1$next[63:0]$14047 } { \fast1_ok \alu_trap0_fast1 } case - assign $1\issue_i[0:0] 1'0 + assign $1\data_r1__fast1$next[63:0]$14047 \data_r1__fast1 + assign $1\data_r1__fast1_ok$next[0:0]$14048 \data_r1__fast1_ok end - sync always - update \issue_i $0\issue_i[0:0] - end - attribute \src "libresoc.v:51638.3-51647.6" - process $proc$libresoc.v:51638$1798 - assign { } { } - assign { } { } - assign $0\dmi__addr[4:0] $1\dmi__addr[4:0] - attribute \src "libresoc.v:51639.5-51639.29" - switch \initial - attribute \src "libresoc.v:51639.9-51639.17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__fast1_ok$next[0:0]$14050 $2\data_r1__fast1$next[63:0]$14049 } 65'00000000000000000000000000000000000000000000000000000000000000000 case + assign $2\data_r1__fast1$next[63:0]$14049 $1\data_r1__fast1$next[63:0]$14047 + assign $2\data_r1__fast1_ok$next[0:0]$14050 $1\data_r1__fast1_ok$next[0:0]$14048 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325" - switch \dbg_d_gpr_req + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi__addr[4:0] \dbg_d_gpr_addr [4:0] + assign $3\data_r1__fast1_ok$next[0:0]$14051 1'0 case - assign $1\dmi__addr[4:0] 5'00000 + assign $3\data_r1__fast1_ok$next[0:0]$14051 $2\data_r1__fast1_ok$next[0:0]$14050 end sync always - update \dmi__addr $0\dmi__addr[4:0] + update \data_r1__fast1$next $0\data_r1__fast1$next[63:0]$14045 + update \data_r1__fast1_ok$next $0\data_r1__fast1_ok$next[0:0]$14046 end - attribute \src "libresoc.v:51648.3-51657.6" - process $proc$libresoc.v:51648$1799 + attribute \src "libresoc.v:187713.3-187734.6" + process $proc$libresoc.v:187713$14052 + assign { } { } + assign { } { } assign { } { } assign { } { } - assign $0\dmi__ren[0:0] $1\dmi__ren[0:0] - attribute \src "libresoc.v:51649.5-51649.29" + assign { } { } + assign { } { } + assign $0\data_r2__fast2$next[63:0]$14053 $2\data_r2__fast2$next[63:0]$14057 + assign { } { } + assign $0\data_r2__fast2_ok$next[0:0]$14054 $3\data_r2__fast2_ok$next[0:0]$14059 + attribute \src "libresoc.v:187714.5-187714.29" switch \initial - attribute \src "libresoc.v:51649.9-51649.17" + attribute \src "libresoc.v:187714.9-187714.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325" - switch \dbg_d_gpr_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi__ren[0:0] 1'1 + assign { } { } + assign { $1\data_r2__fast2_ok$next[0:0]$14056 $1\data_r2__fast2$next[63:0]$14055 } { \fast2_ok \alu_trap0_fast2 } case - assign $1\dmi__ren[0:0] 1'0 + assign $1\data_r2__fast2$next[63:0]$14055 \data_r2__fast2 + assign $1\data_r2__fast2_ok$next[0:0]$14056 \data_r2__fast2_ok end - sync always - update \dmi__ren $0\dmi__ren[0:0] - end - attribute \src "libresoc.v:51658.3-51666.6" - process $proc$libresoc.v:51658$1800 - assign { } { } - assign { } { } - assign $0\d_reg_delay$next[0:0]$1801 $1\d_reg_delay$next[0:0]$1802 - attribute \src "libresoc.v:51659.5-51659.29" - switch \initial - attribute \src "libresoc.v:51659.9-51659.17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__fast2_ok$next[0:0]$14058 $2\data_r2__fast2$next[63:0]$14057 } 65'00000000000000000000000000000000000000000000000000000000000000000 case + assign $2\data_r2__fast2$next[63:0]$14057 $1\data_r2__fast2$next[63:0]$14055 + assign $2\data_r2__fast2_ok$next[0:0]$14058 $1\data_r2__fast2_ok$next[0:0]$14056 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\d_reg_delay$next[0:0]$1802 1'0 + assign $3\data_r2__fast2_ok$next[0:0]$14059 1'0 case - assign $1\d_reg_delay$next[0:0]$1802 \dbg_d_gpr_req + assign $3\data_r2__fast2_ok$next[0:0]$14059 $2\data_r2__fast2_ok$next[0:0]$14058 end sync always - update \d_reg_delay$next $0\d_reg_delay$next[0:0]$1801 + update \data_r2__fast2$next $0\data_r2__fast2$next[63:0]$14053 + update \data_r2__fast2_ok$next $0\data_r2__fast2_ok$next[0:0]$14054 end - attribute \src "libresoc.v:51667.3-51676.6" - process $proc$libresoc.v:51667$1803 + attribute \src "libresoc.v:187735.3-187756.6" + process $proc$libresoc.v:187735$14060 assign { } { } assign { } { } - assign $0\dbg_d_gpr_data[63:0] $1\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:51668.5-51668.29" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r3__nia$next[63:0]$14061 $2\data_r3__nia$next[63:0]$14065 + assign { } { } + assign $0\data_r3__nia_ok$next[0:0]$14062 $3\data_r3__nia_ok$next[0:0]$14067 + attribute \src "libresoc.v:187736.5-187736.29" switch \initial - attribute \src "libresoc.v:51668.9-51668.17" + attribute \src "libresoc.v:187736.9-187736.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:335" - switch \d_reg_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_d_gpr_data[63:0] \dmi__data_o + assign { } { } + assign { $1\data_r3__nia_ok$next[0:0]$14064 $1\data_r3__nia$next[63:0]$14063 } { \nia_ok \alu_trap0_nia } case - assign $1\dbg_d_gpr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\data_r3__nia$next[63:0]$14063 \data_r3__nia + assign $1\data_r3__nia_ok$next[0:0]$14064 \data_r3__nia_ok end - sync always - update \dbg_d_gpr_data $0\dbg_d_gpr_data[63:0] - end - attribute \src "libresoc.v:51677.3-51686.6" - process $proc$libresoc.v:51677$1804 - assign { } { } - assign { } { } - assign $0\dbg_d_gpr_ack[0:0] $1\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:51678.5-51678.29" - switch \initial - attribute \src "libresoc.v:51678.9-51678.17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r3__nia_ok$next[0:0]$14066 $2\data_r3__nia$next[63:0]$14065 } 65'00000000000000000000000000000000000000000000000000000000000000000 case + assign $2\data_r3__nia$next[63:0]$14065 $1\data_r3__nia$next[63:0]$14063 + assign $2\data_r3__nia_ok$next[0:0]$14066 $1\data_r3__nia_ok$next[0:0]$14064 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:335" - switch \d_reg_delay + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_d_gpr_ack[0:0] 1'1 + assign $3\data_r3__nia_ok$next[0:0]$14067 1'0 case - assign $1\dbg_d_gpr_ack[0:0] 1'0 + assign $3\data_r3__nia_ok$next[0:0]$14067 $2\data_r3__nia_ok$next[0:0]$14066 end sync always - update \dbg_d_gpr_ack $0\dbg_d_gpr_ack[0:0] + update \data_r3__nia$next $0\data_r3__nia$next[63:0]$14061 + update \data_r3__nia_ok$next $0\data_r3__nia_ok$next[0:0]$14062 end - attribute \src "libresoc.v:51687.3-51696.6" - process $proc$libresoc.v:51687$1805 + attribute \src "libresoc.v:187757.3-187778.6" + process $proc$libresoc.v:187757$14068 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } assign { } { } + assign $0\data_r4__msr$next[63:0]$14069 $2\data_r4__msr$next[63:0]$14073 assign { } { } - assign $0\full_rd2__ren[7:0] $1\full_rd2__ren[7:0] - attribute \src "libresoc.v:51688.5-51688.29" + assign $0\data_r4__msr_ok$next[0:0]$14070 $3\data_r4__msr_ok$next[0:0]$14075 + attribute \src "libresoc.v:187758.5-187758.29" switch \initial - attribute \src "libresoc.v:51688.9-51688.17" + attribute \src "libresoc.v:187758.9-187758.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:341" - switch \dbg_d_cr_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\full_rd2__ren[7:0] 8'11111111 + assign { } { } + assign { $1\data_r4__msr_ok$next[0:0]$14072 $1\data_r4__msr$next[63:0]$14071 } { \msr_ok \alu_trap0_msr } case - assign $1\full_rd2__ren[7:0] 8'00000000 + assign $1\data_r4__msr$next[63:0]$14071 \data_r4__msr + assign $1\data_r4__msr_ok$next[0:0]$14072 \data_r4__msr_ok end - sync always - update \full_rd2__ren $0\full_rd2__ren[7:0] - end - attribute \src "libresoc.v:51697.3-51705.6" - process $proc$libresoc.v:51697$1806 - assign { } { } - assign { } { } - assign $0\d_cr_delay$next[0:0]$1807 $1\d_cr_delay$next[0:0]$1808 - attribute \src "libresoc.v:51698.5-51698.29" - switch \initial - attribute \src "libresoc.v:51698.9-51698.17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r4__msr_ok$next[0:0]$14074 $2\data_r4__msr$next[63:0]$14073 } 65'00000000000000000000000000000000000000000000000000000000000000000 case + assign $2\data_r4__msr$next[63:0]$14073 $1\data_r4__msr$next[63:0]$14071 + assign $2\data_r4__msr_ok$next[0:0]$14074 $1\data_r4__msr_ok$next[0:0]$14072 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\d_cr_delay$next[0:0]$1808 1'0 + assign $3\data_r4__msr_ok$next[0:0]$14075 1'0 case - assign $1\d_cr_delay$next[0:0]$1808 \dbg_d_cr_req + assign $3\data_r4__msr_ok$next[0:0]$14075 $2\data_r4__msr_ok$next[0:0]$14074 end sync always - update \d_cr_delay$next $0\d_cr_delay$next[0:0]$1807 + update \data_r4__msr$next $0\data_r4__msr$next[63:0]$14069 + update \data_r4__msr_ok$next $0\data_r4__msr_ok$next[0:0]$14070 end - attribute \src "libresoc.v:51706.3-51715.6" - process $proc$libresoc.v:51706$1809 + attribute \src "libresoc.v:187779.3-187788.6" + process $proc$libresoc.v:187779$14076 assign { } { } assign { } { } - assign $0\dbg_d_cr_data[63:0] $1\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:51707.5-51707.29" + assign $0\src_r0$next[63:0]$14077 $1\src_r0$next[63:0]$14078 + attribute \src "libresoc.v:187780.5-187780.29" switch \initial - attribute \src "libresoc.v:51707.9-51707.17" + attribute \src "libresoc.v:187780.9-187780.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:345" - switch \d_cr_delay + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_d_cr_data[63:0] \$127 + assign $1\src_r0$next[63:0]$14078 \src1_i case - assign $1\dbg_d_cr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\src_r0$next[63:0]$14078 \src_r0 end sync always - update \dbg_d_cr_data $0\dbg_d_cr_data[63:0] + update \src_r0$next $0\src_r0$next[63:0]$14077 end - attribute \src "libresoc.v:51716.3-51725.6" - process $proc$libresoc.v:51716$1810 + attribute \src "libresoc.v:187789.3-187798.6" + process $proc$libresoc.v:187789$14079 assign { } { } assign { } { } - assign $0\dbg_d_cr_ack[0:0] $1\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:51717.5-51717.29" + assign $0\src_r1$next[63:0]$14080 $1\src_r1$next[63:0]$14081 + attribute \src "libresoc.v:187790.5-187790.29" switch \initial - attribute \src "libresoc.v:51717.9-51717.17" + attribute \src "libresoc.v:187790.9-187790.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:345" - switch \d_cr_delay + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_d_cr_ack[0:0] 1'1 + assign $1\src_r1$next[63:0]$14081 \src2_i case - assign $1\dbg_d_cr_ack[0:0] 1'0 + assign $1\src_r1$next[63:0]$14081 \src_r1 end sync always - update \dbg_d_cr_ack $0\dbg_d_cr_ack[0:0] + update \src_r1$next $0\src_r1$next[63:0]$14080 end - attribute \src "libresoc.v:51726.3-51735.6" - process $proc$libresoc.v:51726$1811 + attribute \src "libresoc.v:187799.3-187808.6" + process $proc$libresoc.v:187799$14082 assign { } { } assign { } { } - assign $0\full_rd__ren[2:0] $1\full_rd__ren[2:0] - attribute \src "libresoc.v:51727.5-51727.29" + assign $0\src_r2$next[63:0]$14083 $1\src_r2$next[63:0]$14084 + attribute \src "libresoc.v:187800.5-187800.29" switch \initial - attribute \src "libresoc.v:51727.9-51727.17" + attribute \src "libresoc.v:187800.9-187800.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351" - switch \dbg_d_xer_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\full_rd__ren[2:0] 3'111 + assign $1\src_r2$next[63:0]$14084 \src3_i case - assign $1\full_rd__ren[2:0] 3'000 + assign $1\src_r2$next[63:0]$14084 \src_r2 end sync always - update \full_rd__ren $0\full_rd__ren[2:0] + update \src_r2$next $0\src_r2$next[63:0]$14083 end - attribute \src "libresoc.v:51736.3-51744.6" - process $proc$libresoc.v:51736$1812 + attribute \src "libresoc.v:187809.3-187818.6" + process $proc$libresoc.v:187809$14085 assign { } { } assign { } { } - assign $0\d_xer_delay$next[0:0]$1813 $1\d_xer_delay$next[0:0]$1814 - attribute \src "libresoc.v:51737.5-51737.29" + assign $0\src_r3$next[63:0]$14086 $1\src_r3$next[63:0]$14087 + attribute \src "libresoc.v:187810.5-187810.29" switch \initial - attribute \src "libresoc.v:51737.9-51737.17" + attribute \src "libresoc.v:187810.9-187810.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\d_xer_delay$next[0:0]$1814 1'0 + assign $1\src_r3$next[63:0]$14087 \src4_i case - assign $1\d_xer_delay$next[0:0]$1814 \dbg_d_xer_req + assign $1\src_r3$next[63:0]$14087 \src_r3 end sync always - update \d_xer_delay$next $0\d_xer_delay$next[0:0]$1813 + update \src_r3$next $0\src_r3$next[63:0]$14086 end - attribute \src "libresoc.v:51745.3-51754.6" - process $proc$libresoc.v:51745$1815 + attribute \src "libresoc.v:187819.3-187827.6" + process $proc$libresoc.v:187819$14088 assign { } { } assign { } { } - assign $0\dbg_d_xer_data[63:0] $1\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:51746.5-51746.29" + assign $0\alui_l_r_alui$next[0:0]$14089 $1\alui_l_r_alui$next[0:0]$14090 + attribute \src "libresoc.v:187820.5-187820.29" switch \initial - attribute \src "libresoc.v:51746.9-51746.17" + attribute \src "libresoc.v:187820.9-187820.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:355" - switch \d_xer_delay + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_d_xer_data[63:0] \$129 + assign $1\alui_l_r_alui$next[0:0]$14090 1'1 case - assign $1\dbg_d_xer_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\alui_l_r_alui$next[0:0]$14090 \$89 end sync always - update \dbg_d_xer_data $0\dbg_d_xer_data[63:0] + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$14089 end - attribute \src "libresoc.v:51755.3-51764.6" - process $proc$libresoc.v:51755$1816 + attribute \src "libresoc.v:187828.3-187836.6" + process $proc$libresoc.v:187828$14091 assign { } { } assign { } { } - assign $0\dbg_d_xer_ack[0:0] $1\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:51756.5-51756.29" + assign $0\alu_l_r_alu$next[0:0]$14092 $1\alu_l_r_alu$next[0:0]$14093 + attribute \src "libresoc.v:187829.5-187829.29" switch \initial - attribute \src "libresoc.v:51756.9-51756.17" + attribute \src "libresoc.v:187829.9-187829.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:355" - switch \d_xer_delay + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_d_xer_ack[0:0] 1'1 + assign $1\alu_l_r_alu$next[0:0]$14093 1'1 case - assign $1\dbg_d_xer_ack[0:0] 1'0 + assign $1\alu_l_r_alu$next[0:0]$14093 \$91 end sync always - update \dbg_d_xer_ack $0\dbg_d_xer_ack[0:0] + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$14092 end - attribute \src "libresoc.v:51765.3-51779.6" - process $proc$libresoc.v:51765$1817 + attribute \src "libresoc.v:187837.3-187846.6" + process $proc$libresoc.v:187837$14094 assign { } { } assign { } { } - assign $0\issue__addr[2:0] $1\issue__addr[2:0] - attribute \src "libresoc.v:51766.5-51766.29" + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:187838.5-187838.29" switch \initial - attribute \src "libresoc.v:51766.9-51766.17" + attribute \src "libresoc.v:187838.9-187838.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" - switch \fsm_state$131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$115 attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\issue__addr[2:0] 3'110 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 1'1 assign { } { } - assign $1\issue__addr[2:0] 3'111 + assign $1\dest1_o[63:0] \data_r0__o case - assign $1\issue__addr[2:0] 3'000 + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \issue__addr $0\issue__addr[2:0] + update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:51780.3-51794.6" - process $proc$libresoc.v:51780$1818 + attribute \src "libresoc.v:187847.3-187856.6" + process $proc$libresoc.v:187847$14095 assign { } { } assign { } { } - assign $0\issue__ren[0:0] $1\issue__ren[0:0] - attribute \src "libresoc.v:51781.5-51781.29" + assign $0\dest2_o[63:0] $1\dest2_o[63:0] + attribute \src "libresoc.v:187848.5-187848.29" switch \initial - attribute \src "libresoc.v:51781.9-51781.17" + attribute \src "libresoc.v:187848.9-187848.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" - switch \fsm_state$131 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\issue__ren[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$117 attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 1'1 assign { } { } - assign $1\issue__ren[0:0] 1'1 + assign $1\dest2_o[63:0] \data_r1__fast1 case - assign $1\issue__ren[0:0] 1'0 + assign $1\dest2_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \issue__ren $0\issue__ren[0:0] + update \dest2_o $0\dest2_o[63:0] end - attribute \src "libresoc.v:51795.3-51822.6" - process $proc$libresoc.v:51795$1819 + attribute \src "libresoc.v:187857.3-187866.6" + process $proc$libresoc.v:187857$14096 assign { } { } assign { } { } - assign { } { } - assign $0\fsm_state$131$next[1:0]$1820 $2\fsm_state$131$next[1:0]$1822 - attribute \src "libresoc.v:51796.5-51796.29" + assign $0\dest3_o[63:0] $1\dest3_o[63:0] + attribute \src "libresoc.v:187858.5-187858.29" switch \initial - attribute \src "libresoc.v:51796.9-51796.17" + attribute \src "libresoc.v:187858.9-187858.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" - switch \fsm_state$131 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\fsm_state$131$next[1:0]$1821 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\fsm_state$131$next[1:0]$1821 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\fsm_state$131$next[1:0]$1821 2'11 - attribute \src "libresoc.v:0.0-0.0" - case 2'11 - assign { } { } - assign $1\fsm_state$131$next[1:0]$1821 2'00 - case - assign $1\fsm_state$131$next[1:0]$1821 \fsm_state$131 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$119 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fsm_state$131$next[1:0]$1822 2'00 + assign $1\dest3_o[63:0] \data_r2__fast2 case - assign $2\fsm_state$131$next[1:0]$1822 $1\fsm_state$131$next[1:0]$1821 + assign $1\dest3_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fsm_state$131$next $0\fsm_state$131$next[1:0]$1820 + update \dest3_o $0\dest3_o[63:0] end - attribute \src "libresoc.v:51823.3-51833.6" - process $proc$libresoc.v:51823$1823 + attribute \src "libresoc.v:187867.3-187876.6" + process $proc$libresoc.v:187867$14097 assign { } { } assign { } { } - assign $0\new_dec[63:0] $1\new_dec[63:0] - attribute \src "libresoc.v:51824.5-51824.29" + assign $0\dest4_o[63:0] $1\dest4_o[63:0] + attribute \src "libresoc.v:187868.5-187868.29" switch \initial - attribute \src "libresoc.v:51824.9-51824.17" + attribute \src "libresoc.v:187868.9-187868.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" - switch \fsm_state$131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$121 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 1'1 assign { } { } - assign $1\new_dec[63:0] \$132 [63:0] + assign $1\dest4_o[63:0] \data_r3__nia case - assign $1\new_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dest4_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \new_dec $0\new_dec[63:0] + update \dest4_o $0\dest4_o[63:0] end - attribute \src "libresoc.v:51834.3-51848.6" - process $proc$libresoc.v:51834$1824 + attribute \src "libresoc.v:187877.3-187886.6" + process $proc$libresoc.v:187877$14098 assign { } { } assign { } { } - assign $0\issue__addr$135[2:0]$1825 $1\issue__addr$135[2:0]$1826 - attribute \src "libresoc.v:51835.5-51835.29" + assign $0\dest5_o[63:0] $1\dest5_o[63:0] + attribute \src "libresoc.v:187878.5-187878.29" switch \initial - attribute \src "libresoc.v:51835.9-51835.17" + attribute \src "libresoc.v:187878.9-187878.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" - switch \fsm_state$131 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\issue__addr$135[2:0]$1826 3'110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$123 attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 1'1 assign { } { } - assign $1\issue__addr$135[2:0]$1826 3'111 + assign $1\dest5_o[63:0] \data_r4__msr case - assign $1\issue__addr$135[2:0]$1826 3'000 + assign $1\dest5_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \issue__addr$135 $0\issue__addr$135[2:0]$1825 + update \dest5_o $0\dest5_o[63:0] end - attribute \src "libresoc.v:51849.3-51863.6" - process $proc$libresoc.v:51849$1827 + attribute \src "libresoc.v:187887.3-187895.6" + process $proc$libresoc.v:187887$14099 assign { } { } assign { } { } - assign $0\issue__wen[0:0] $1\issue__wen[0:0] - attribute \src "libresoc.v:51850.5-51850.29" + assign $0\prev_wr_go$next[4:0]$14100 $1\prev_wr_go$next[4:0]$14101 + attribute \src "libresoc.v:187888.5-187888.29" switch \initial - attribute \src "libresoc.v:51850.9-51850.17" + attribute \src "libresoc.v:187888.9-187888.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" - switch \fsm_state$131 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\issue__wen[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 1'1 assign { } { } - assign $1\issue__wen[0:0] 1'1 - case - assign $1\issue__wen[0:0] 1'0 - end - sync always - update \issue__wen $0\issue__wen[0:0] + assign $1\prev_wr_go$next[4:0]$14101 5'00000 + case + assign $1\prev_wr_go$next[4:0]$14101 \$21 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[4:0]$14100 + end + connect \$5 $reduce_and$libresoc.v:187335$13887_Y + connect \$99 $and$libresoc.v:187336$13888_Y + connect \$101 $and$libresoc.v:187337$13889_Y + connect \$103 $and$libresoc.v:187338$13890_Y + connect \$105 $and$libresoc.v:187339$13891_Y + connect \$107 $and$libresoc.v:187340$13892_Y + connect \$109 $and$libresoc.v:187341$13893_Y + connect \$111 $and$libresoc.v:187342$13894_Y + connect \$113 $and$libresoc.v:187343$13895_Y + connect \$115 $and$libresoc.v:187344$13896_Y + connect \$117 $and$libresoc.v:187345$13897_Y + connect \$11 $and$libresoc.v:187346$13898_Y + connect \$119 $and$libresoc.v:187347$13899_Y + connect \$121 $and$libresoc.v:187348$13900_Y + connect \$123 $and$libresoc.v:187349$13901_Y + connect \$13 $not$libresoc.v:187350$13902_Y + connect \$15 $and$libresoc.v:187351$13903_Y + connect \$17 $not$libresoc.v:187352$13904_Y + connect \$19 $and$libresoc.v:187353$13905_Y + connect \$21 $and$libresoc.v:187354$13906_Y + connect \$25 $not$libresoc.v:187355$13907_Y + connect \$27 $and$libresoc.v:187356$13908_Y + connect \$24 $reduce_or$libresoc.v:187357$13909_Y + connect \$23 $not$libresoc.v:187358$13910_Y + connect \$31 $and$libresoc.v:187359$13911_Y + connect \$33 $reduce_or$libresoc.v:187360$13912_Y + connect \$35 $reduce_or$libresoc.v:187361$13913_Y + connect \$37 $or$libresoc.v:187362$13914_Y + connect \$3 $and$libresoc.v:187363$13915_Y + connect \$39 $not$libresoc.v:187364$13916_Y + connect \$41 $and$libresoc.v:187365$13917_Y + connect \$43 $and$libresoc.v:187366$13918_Y + connect \$45 $eq$libresoc.v:187367$13919_Y + connect \$47 $and$libresoc.v:187368$13920_Y + connect \$49 $eq$libresoc.v:187369$13921_Y + connect \$51 $and$libresoc.v:187370$13922_Y + connect \$53 $and$libresoc.v:187371$13923_Y + connect \$55 $and$libresoc.v:187372$13924_Y + connect \$57 $or$libresoc.v:187373$13925_Y + connect \$59 $or$libresoc.v:187374$13926_Y + connect \$61 $or$libresoc.v:187375$13927_Y + connect \$63 $or$libresoc.v:187376$13928_Y + connect \$65 $and$libresoc.v:187377$13929_Y + connect \$67 $and$libresoc.v:187378$13930_Y + connect \$6 $not$libresoc.v:187379$13931_Y + connect \$69 $or$libresoc.v:187380$13932_Y + connect \$71 $and$libresoc.v:187381$13933_Y + connect \$73 $and$libresoc.v:187382$13934_Y + connect \$75 $and$libresoc.v:187383$13935_Y + connect \$77 $and$libresoc.v:187384$13936_Y + connect \$79 $and$libresoc.v:187385$13937_Y + connect \$81 $ternary$libresoc.v:187386$13938_Y + connect \$83 $ternary$libresoc.v:187387$13939_Y + connect \$85 $ternary$libresoc.v:187388$13940_Y + connect \$87 $ternary$libresoc.v:187389$13941_Y + connect \$8 $or$libresoc.v:187390$13942_Y + connect \$89 $and$libresoc.v:187391$13943_Y + connect \$91 $and$libresoc.v:187392$13944_Y + connect \$93 $and$libresoc.v:187393$13945_Y + connect \$95 $and$libresoc.v:187394$13946_Y + connect \$97 $not$libresoc.v:187395$13947_Y + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \cu_wr__rel_o \$113 + connect \cu_rd__rel_o \$99 + connect \cu_busy_o \opc_l_q_opc + connect \alu_l_s_alu \all_rd_pulse + connect \alu_trap0_n_ready_i \alu_l_q_alu + connect \alui_l_s_alui \all_rd_pulse + connect \alu_trap0_p_valid_i \alui_l_q_alui + connect \alu_trap0_fast2$2 \$87 + connect \alu_trap0_fast1$1 \$85 + connect \alu_trap0_rb \$83 + connect \alu_trap0_ra \$81 + connect \cu_wrmask_o { \$79 \$77 \$75 \$73 \$71 } + connect \reset_r \$63 + connect \reset_w \$61 + connect \rst_r \$59 + connect \reset \$57 + connect \wr_any \$37 + connect \cu_done_o \$31 + connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse } + connect \alu_pulse \alu_done_rise + connect \alu_done_rise \$19 + connect \alu_done_dly$next \alu_done + connect \alu_done \alu_trap0_n_valid_o + connect \all_rd_pulse \all_rd_rise + connect \all_rd_rise \$15 + connect \all_rd_dly$next \all_rd + connect \all_rd \$11 +end +attribute \src "libresoc.v:187929.1-187987.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.upd_l" +attribute \generator "nMigen" +module \upd_l + attribute \src "libresoc.v:187930.7-187930.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:187975.3-187983.6" + wire $0\q_int$next[0:0]$14151 + attribute \src "libresoc.v:187973.3-187974.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:187975.3-187983.6" + wire $1\q_int$next[0:0]$14152 + attribute \src "libresoc.v:187952.7-187952.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:187965.17-187965.96" + wire $and$libresoc.v:187965$14141_Y + attribute \src "libresoc.v:187970.17-187970.96" + wire $and$libresoc.v:187970$14146_Y + attribute \src "libresoc.v:187967.18-187967.93" + wire $not$libresoc.v:187967$14143_Y + attribute \src "libresoc.v:187969.17-187969.92" + wire $not$libresoc.v:187969$14145_Y + attribute \src "libresoc.v:187972.17-187972.92" + wire $not$libresoc.v:187972$14148_Y + attribute \src "libresoc.v:187966.18-187966.98" + wire $or$libresoc.v:187966$14142_Y + attribute \src "libresoc.v:187968.18-187968.99" + wire $or$libresoc.v:187968$14144_Y + attribute \src "libresoc.v:187971.17-187971.97" + wire $or$libresoc.v:187971$14147_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:187930.7-187930.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:187965$14141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:187965$14141_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:187970$14146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:187970$14146_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:187967$14143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_upd + connect \Y $not$libresoc.v:187967$14143_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:187969$14145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_upd + connect \Y $not$libresoc.v:187969$14145_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:187972$14148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_upd + connect \Y $not$libresoc.v:187972$14148_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:187966$14142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_upd + connect \Y $or$libresoc.v:187966$14142_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:187968$14144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_upd + connect \B \q_int + connect \Y $or$libresoc.v:187968$14144_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:187971$14147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_upd + connect \Y $or$libresoc.v:187971$14147_Y end - attribute \src "libresoc.v:51864.3-51878.6" - process $proc$libresoc.v:51864$1828 + attribute \src "libresoc.v:187930.7-187930.20" + process $proc$libresoc.v:187930$14153 assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:187952.7-187952.19" + process $proc$libresoc.v:187952$14154 assign { } { } - assign $0\issue__data_i[63:0] $1\issue__data_i[63:0] - attribute \src "libresoc.v:51865.5-51865.29" - switch \initial - attribute \src "libresoc.v:51865.9-51865.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" - switch \fsm_state$131 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\issue__data_i[63:0] \new_dec - attribute \src "libresoc.v:0.0-0.0" - case 2'11 - assign { } { } - assign $1\issue__data_i[63:0] \new_tb - case - assign $1\issue__data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end + assign $1\q_int[0:0] 1'0 sync always - update \issue__data_i $0\issue__data_i[63:0] + sync init + update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:51879.3-51894.6" - process $proc$libresoc.v:51879$1829 + attribute \src "libresoc.v:187973.3-187974.27" + process $proc$libresoc.v:187973$14149 assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:187975.3-187983.6" + process $proc$libresoc.v:187975$14150 assign { } { } assign { } { } - assign $0\dec2_cur_dec$next[63:0]$1830 $2\dec2_cur_dec$next[63:0]$1832 - attribute \src "libresoc.v:51880.5-51880.29" + assign $0\q_int$next[0:0]$14151 $1\q_int$next[0:0]$14152 + attribute \src "libresoc.v:187976.5-187976.29" switch \initial - attribute \src "libresoc.v:51880.9-51880.17" + attribute \src "libresoc.v:187976.9-187976.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" - switch \fsm_state$131 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec2_cur_dec$next[63:0]$1831 \new_dec - case - assign $1\dec2_cur_dec$next[63:0]$1831 \dec2_cur_dec - end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dec2_cur_dec$next[63:0]$1832 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\q_int$next[0:0]$14152 1'0 case - assign $2\dec2_cur_dec$next[63:0]$1832 $1\dec2_cur_dec$next[63:0]$1831 + assign $1\q_int$next[0:0]$14152 \$5 end sync always - update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$1830 + update \q_int$next $0\q_int$next[0:0]$14151 + end + connect \$9 $and$libresoc.v:187965$14141_Y + connect \$11 $or$libresoc.v:187966$14142_Y + connect \$13 $not$libresoc.v:187967$14143_Y + connect \$15 $or$libresoc.v:187968$14144_Y + connect \$1 $not$libresoc.v:187969$14145_Y + connect \$3 $and$libresoc.v:187970$14146_Y + connect \$5 $or$libresoc.v:187971$14147_Y + connect \$7 $not$libresoc.v:187972$14148_Y + connect \qlq_upd \$15 + connect \qn_upd \$13 + connect \q_upd \$11 +end +attribute \src "libresoc.v:187991.1-188049.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.valid_l" +attribute \generator "nMigen" +module \valid_l + attribute \src "libresoc.v:187992.7-187992.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:188037.3-188045.6" + wire $0\q_int$next[0:0]$14165 + attribute \src "libresoc.v:188035.3-188036.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:188037.3-188045.6" + wire $1\q_int$next[0:0]$14166 + attribute \src "libresoc.v:188014.7-188014.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:188027.17-188027.96" + wire $and$libresoc.v:188027$14155_Y + attribute \src "libresoc.v:188032.17-188032.96" + wire $and$libresoc.v:188032$14160_Y + attribute \src "libresoc.v:188029.18-188029.95" + wire $not$libresoc.v:188029$14157_Y + attribute \src "libresoc.v:188031.17-188031.94" + wire $not$libresoc.v:188031$14159_Y + attribute \src "libresoc.v:188034.17-188034.94" + wire $not$libresoc.v:188034$14162_Y + attribute \src "libresoc.v:188028.18-188028.100" + wire $or$libresoc.v:188028$14156_Y + attribute \src "libresoc.v:188030.18-188030.101" + wire $or$libresoc.v:188030$14158_Y + attribute \src "libresoc.v:188033.17-188033.99" + wire $or$libresoc.v:188033$14161_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:187992.7-187992.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 3 \q_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 4 \r_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:188027$14155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:188027$14155_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:188032$14160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:188032$14160_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:188029$14157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_valid + connect \Y $not$libresoc.v:188029$14157_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:188031$14159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_valid + connect \Y $not$libresoc.v:188031$14159_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:188034$14162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_valid + connect \Y $not$libresoc.v:188034$14162_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:188028$14156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_valid + connect \Y $or$libresoc.v:188028$14156_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:188030$14158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_valid + connect \B \q_int + connect \Y $or$libresoc.v:188030$14158_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:188033$14161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_valid + connect \Y $or$libresoc.v:188033$14161_Y end - attribute \src "libresoc.v:51895.3-51905.6" - process $proc$libresoc.v:51895$1833 + attribute \src "libresoc.v:187992.7-187992.20" + process $proc$libresoc.v:187992$14167 assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:188014.7-188014.19" + process $proc$libresoc.v:188014$14168 assign { } { } - assign $0\new_tb[63:0] $1\new_tb[63:0] - attribute \src "libresoc.v:51896.5-51896.29" - switch \initial - attribute \src "libresoc.v:51896.9-51896.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" - switch \fsm_state$131 - attribute \src "libresoc.v:0.0-0.0" - case 2'11 - assign { } { } - assign $1\new_tb[63:0] \$136 [63:0] - case - assign $1\new_tb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end + assign $1\q_int[0:0] 1'0 sync always - update \new_tb $0\new_tb[63:0] + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:188035.3-188036.27" + process $proc$libresoc.v:188035$14163 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:51906.3-51914.6" - process $proc$libresoc.v:51906$1834 + attribute \src "libresoc.v:188037.3-188045.6" + process $proc$libresoc.v:188037$14164 assign { } { } assign { } { } - assign $0\dbg_dmi_we_i$next[0:0]$1835 $1\dbg_dmi_we_i$next[0:0]$1836 - attribute \src "libresoc.v:51907.5-51907.29" + assign $0\q_int$next[0:0]$14165 $1\q_int$next[0:0]$14166 + attribute \src "libresoc.v:188038.5-188038.29" switch \initial - attribute \src "libresoc.v:51907.9-51907.17" + attribute \src "libresoc.v:188038.9-188038.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_we_i$next[0:0]$1836 1'0 + assign $1\q_int$next[0:0]$14166 1'0 case - assign $1\dbg_dmi_we_i$next[0:0]$1836 \jtag_dmi0__we_i + assign $1\q_int$next[0:0]$14166 \$5 end sync always - update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$1835 + update \q_int$next $0\q_int$next[0:0]$14165 + end + connect \$9 $and$libresoc.v:188027$14155_Y + connect \$11 $or$libresoc.v:188028$14156_Y + connect \$13 $not$libresoc.v:188029$14157_Y + connect \$15 $or$libresoc.v:188030$14158_Y + connect \$1 $not$libresoc.v:188031$14159_Y + connect \$3 $and$libresoc.v:188032$14160_Y + connect \$5 $or$libresoc.v:188033$14161_Y + connect \$7 $not$libresoc.v:188034$14162_Y + connect \qlq_valid \$15 + connect \qn_valid \$13 + connect \q_valid \$11 +end +attribute \src "libresoc.v:188053.1-188111.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.wri_l" +attribute \generator "nMigen" +module \wri_l + attribute \src "libresoc.v:188054.7-188054.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:188099.3-188107.6" + wire $0\q_int$next[0:0]$14179 + attribute \src "libresoc.v:188097.3-188098.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:188099.3-188107.6" + wire $1\q_int$next[0:0]$14180 + attribute \src "libresoc.v:188076.7-188076.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:188089.17-188089.96" + wire $and$libresoc.v:188089$14169_Y + attribute \src "libresoc.v:188094.17-188094.96" + wire $and$libresoc.v:188094$14174_Y + attribute \src "libresoc.v:188091.18-188091.93" + wire $not$libresoc.v:188091$14171_Y + attribute \src "libresoc.v:188093.17-188093.92" + wire $not$libresoc.v:188093$14173_Y + attribute \src "libresoc.v:188096.17-188096.92" + wire $not$libresoc.v:188096$14176_Y + attribute \src "libresoc.v:188090.18-188090.98" + wire $or$libresoc.v:188090$14170_Y + attribute \src "libresoc.v:188092.18-188092.99" + wire $or$libresoc.v:188092$14172_Y + attribute \src "libresoc.v:188095.17-188095.97" + wire $or$libresoc.v:188095$14175_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:188054.7-188054.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:188089$14169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:188089$14169_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:188094$14174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:188094$14174_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:188091$14171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_wri + connect \Y $not$libresoc.v:188091$14171_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:188093$14173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_wri + connect \Y $not$libresoc.v:188093$14173_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:188096$14176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_wri + connect \Y $not$libresoc.v:188096$14176_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:188090$14170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_wri + connect \Y $or$libresoc.v:188090$14170_Y end - attribute \src "libresoc.v:51915.3-51923.6" - process $proc$libresoc.v:51915$1837 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:188092$14172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_wri + connect \B \q_int + connect \Y $or$libresoc.v:188092$14172_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:188095$14175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_wri + connect \Y $or$libresoc.v:188095$14175_Y + end + attribute \src "libresoc.v:188054.7-188054.20" + process $proc$libresoc.v:188054$14181 assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:188076.7-188076.19" + process $proc$libresoc.v:188076$14182 assign { } { } - assign $0\pc_ok_delay$next[0:0]$1838 $1\pc_ok_delay$next[0:0]$1839 - attribute \src "libresoc.v:51916.5-51916.29" - switch \initial - attribute \src "libresoc.v:51916.9-51916.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\pc_ok_delay$next[0:0]$1839 1'0 - case - assign $1\pc_ok_delay$next[0:0]$1839 \$28 - end + assign $1\q_int[0:0] 1'0 sync always - update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$1838 + sync init + update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:51924.3-51939.6" - process $proc$libresoc.v:51924$1840 + attribute \src "libresoc.v:188097.3-188098.27" + process $proc$libresoc.v:188097$14177 assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:188099.3-188107.6" + process $proc$libresoc.v:188099$14178 assign { } { } assign { } { } - assign $0\pc[63:0] $2\pc[63:0] - attribute \src "libresoc.v:51925.5-51925.29" + assign $0\q_int$next[0:0]$14179 $1\q_int$next[0:0]$14180 + attribute \src "libresoc.v:188100.5-188100.29" switch \initial - attribute \src "libresoc.v:51925.9-51925.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:207" - switch \pc_i_ok - attribute \src "libresoc.v:0.0-0.0" + attribute \src "libresoc.v:188100.9-188100.17" case 1'1 - assign { } { } - assign $1\pc[63:0] \pc_i case - assign $1\pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" - switch \pc_ok_delay + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\pc[63:0] \cia__data_o + assign $1\q_int$next[0:0]$14180 1'0 case - assign $2\pc[63:0] $1\pc[63:0] + assign $1\q_int$next[0:0]$14180 \$5 end sync always - update \pc $0\pc[63:0] + update \q_int$next $0\q_int$next[0:0]$14179 + end + connect \$9 $and$libresoc.v:188089$14169_Y + connect \$11 $or$libresoc.v:188090$14170_Y + connect \$13 $not$libresoc.v:188091$14171_Y + connect \$15 $or$libresoc.v:188092$14172_Y + connect \$1 $not$libresoc.v:188093$14173_Y + connect \$3 $and$libresoc.v:188094$14174_Y + connect \$5 $or$libresoc.v:188095$14175_Y + connect \$7 $not$libresoc.v:188096$14176_Y + connect \qlq_wri \$15 + connect \qn_wri \$13 + connect \q_wri \$11 +end +attribute \src "libresoc.v:188115.1-188181.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_cr_a" +attribute \generator "nMigen" +module \wrpick_CR_cr_a + attribute \src "libresoc.v:188160.17-188160.91" + wire $not$libresoc.v:188160$14183_Y + attribute \src "libresoc.v:188162.18-188162.93" + wire $not$libresoc.v:188162$14185_Y + attribute \src "libresoc.v:188164.18-188164.93" + wire $not$libresoc.v:188164$14187_Y + attribute \src "libresoc.v:188165.17-188165.89" + wire width 6 $not$libresoc.v:188165$14188_Y + attribute \src "libresoc.v:188167.18-188167.93" + wire $not$libresoc.v:188167$14190_Y + attribute \src "libresoc.v:188170.17-188170.91" + wire $not$libresoc.v:188170$14193_Y + attribute \src "libresoc.v:188161.18-188161.106" + wire $reduce_or$libresoc.v:188161$14184_Y + attribute \src "libresoc.v:188163.18-188163.106" + wire $reduce_or$libresoc.v:188163$14186_Y + attribute \src "libresoc.v:188166.18-188166.106" + wire $reduce_or$libresoc.v:188166$14189_Y + attribute \src "libresoc.v:188168.18-188168.90" + wire $reduce_or$libresoc.v:188168$14191_Y + attribute \src "libresoc.v:188169.17-188169.103" + wire $reduce_or$libresoc.v:188169$14192_Y + attribute \src "libresoc.v:188171.17-188171.105" + wire $reduce_or$libresoc.v:188171$14194_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 6 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 6 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 6 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 6 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:188160$14183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:188160$14183_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:188162$14185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:188162$14185_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:188164$14187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:188164$14187_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:188165$14188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \i + connect \Y $not$libresoc.v:188165$14188_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:188167$14190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:188167$14190_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:188170$14193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:188170$14193_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:188161$14184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] \ni [3] } + connect \Y $reduce_or$libresoc.v:188161$14184_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:188163$14186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3:0] \ni [4] } + connect \Y $reduce_or$libresoc.v:188163$14186_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:188166$14189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [4:0] \ni [5] } + connect \Y $reduce_or$libresoc.v:188166$14189_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:188168$14191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:188168$14191_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:188169$14192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:188169$14192_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:188171$14194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:188171$14194_Y + end + connect \$7 $not$libresoc.v:188160$14183_Y + connect \$12 $reduce_or$libresoc.v:188161$14184_Y + connect \$11 $not$libresoc.v:188162$14185_Y + connect \$16 $reduce_or$libresoc.v:188163$14186_Y + connect \$15 $not$libresoc.v:188164$14187_Y + connect \$1 $not$libresoc.v:188165$14188_Y + connect \$20 $reduce_or$libresoc.v:188166$14189_Y + connect \$19 $not$libresoc.v:188167$14190_Y + connect \$23 $reduce_or$libresoc.v:188168$14191_Y + connect \$4 $reduce_or$libresoc.v:188169$14192_Y + connect \$3 $not$libresoc.v:188170$14193_Y + connect \$8 $reduce_or$libresoc.v:188171$14194_Y + connect \en_o \$23 + connect \o { \t5 \t4 \t3 \t2 \t1 \t0 } + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:188185.1-188206.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_full_cr" +attribute \generator "nMigen" +module \wrpick_CR_full_cr + attribute \src "libresoc.v:188200.17-188200.89" + wire $not$libresoc.v:188200$14195_Y + attribute \src "libresoc.v:188201.17-188201.89" + wire $reduce_or$libresoc.v:188201$14196_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:188200$14195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $not$libresoc.v:188200$14195_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:188201$14196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:188201$14196_Y + end + connect \$1 $not$libresoc.v:188200$14195_Y + connect \$3 $reduce_or$libresoc.v:188201$14196_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "libresoc.v:188210.1-188267.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_FAST_fast1" +attribute \generator "nMigen" +module \wrpick_FAST_fast1 + attribute \src "libresoc.v:188249.17-188249.91" + wire $not$libresoc.v:188249$14197_Y + attribute \src "libresoc.v:188251.18-188251.93" + wire $not$libresoc.v:188251$14199_Y + attribute \src "libresoc.v:188253.18-188253.93" + wire $not$libresoc.v:188253$14201_Y + attribute \src "libresoc.v:188254.17-188254.89" + wire width 5 $not$libresoc.v:188254$14202_Y + attribute \src "libresoc.v:188257.17-188257.91" + wire $not$libresoc.v:188257$14205_Y + attribute \src "libresoc.v:188250.18-188250.106" + wire $reduce_or$libresoc.v:188250$14198_Y + attribute \src "libresoc.v:188252.18-188252.106" + wire $reduce_or$libresoc.v:188252$14200_Y + attribute \src "libresoc.v:188255.18-188255.90" + wire $reduce_or$libresoc.v:188255$14203_Y + attribute \src "libresoc.v:188256.17-188256.103" + wire $reduce_or$libresoc.v:188256$14204_Y + attribute \src "libresoc.v:188258.17-188258.105" + wire $reduce_or$libresoc.v:188258$14206_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 5 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 5 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 5 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 5 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:188249$14197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:188249$14197_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:188251$14199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:188251$14199_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:188253$14201 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:188253$14201_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:188254$14202 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \i + connect \Y $not$libresoc.v:188254$14202_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:188257$14205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:188257$14205_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:188250$14198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] \ni [3] } + connect \Y $reduce_or$libresoc.v:188250$14198_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:188252$14200 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3:0] \ni [4] } + connect \Y $reduce_or$libresoc.v:188252$14200_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:188255$14203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:188255$14203_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:188256$14204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:188256$14204_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:188258$14206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:188258$14206_Y + end + connect \$7 $not$libresoc.v:188249$14197_Y + connect \$12 $reduce_or$libresoc.v:188250$14198_Y + connect \$11 $not$libresoc.v:188251$14199_Y + connect \$16 $reduce_or$libresoc.v:188252$14200_Y + connect \$15 $not$libresoc.v:188253$14201_Y + connect \$1 $not$libresoc.v:188254$14202_Y + connect \$19 $reduce_or$libresoc.v:188255$14203_Y + connect \$4 $reduce_or$libresoc.v:188256$14204_Y + connect \$3 $not$libresoc.v:188257$14205_Y + connect \$8 $reduce_or$libresoc.v:188258$14206_Y + connect \en_o \$19 + connect \o { \t4 \t3 \t2 \t1 \t0 } + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:188271.1-188373.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_INT_o" +attribute \generator "nMigen" +module \wrpick_INT_o + attribute \src "libresoc.v:188340.17-188340.91" + wire $not$libresoc.v:188340$14207_Y + attribute \src "libresoc.v:188342.18-188342.93" + wire $not$libresoc.v:188342$14209_Y + attribute \src "libresoc.v:188344.18-188344.93" + wire $not$libresoc.v:188344$14211_Y + attribute \src "libresoc.v:188345.17-188345.89" + wire width 10 $not$libresoc.v:188345$14212_Y + attribute \src "libresoc.v:188347.18-188347.93" + wire $not$libresoc.v:188347$14214_Y + attribute \src "libresoc.v:188349.18-188349.93" + wire $not$libresoc.v:188349$14216_Y + attribute \src "libresoc.v:188351.18-188351.93" + wire $not$libresoc.v:188351$14218_Y + attribute \src "libresoc.v:188353.18-188353.93" + wire $not$libresoc.v:188353$14220_Y + attribute \src "libresoc.v:188355.18-188355.93" + wire $not$libresoc.v:188355$14222_Y + attribute \src "libresoc.v:188358.17-188358.91" + wire $not$libresoc.v:188358$14225_Y + attribute \src "libresoc.v:188341.18-188341.106" + wire $reduce_or$libresoc.v:188341$14208_Y + attribute \src "libresoc.v:188343.18-188343.106" + wire $reduce_or$libresoc.v:188343$14210_Y + attribute \src "libresoc.v:188346.18-188346.106" + wire $reduce_or$libresoc.v:188346$14213_Y + attribute \src "libresoc.v:188348.18-188348.106" + wire $reduce_or$libresoc.v:188348$14215_Y + attribute \src "libresoc.v:188350.18-188350.106" + wire $reduce_or$libresoc.v:188350$14217_Y + attribute \src "libresoc.v:188352.18-188352.106" + wire $reduce_or$libresoc.v:188352$14219_Y + attribute \src "libresoc.v:188354.18-188354.106" + wire $reduce_or$libresoc.v:188354$14221_Y + attribute \src "libresoc.v:188356.18-188356.90" + wire $reduce_or$libresoc.v:188356$14223_Y + attribute \src "libresoc.v:188357.17-188357.103" + wire $reduce_or$libresoc.v:188357$14224_Y + attribute \src "libresoc.v:188359.17-188359.105" + wire $reduce_or$libresoc.v:188359$14226_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 10 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 10 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 10 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 10 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:188340$14207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:188340$14207_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:188342$14209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:188342$14209_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:188344$14211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:188344$14211_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:188345$14212 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \Y_WIDTH 10 + connect \A \i + connect \Y $not$libresoc.v:188345$14212_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:188347$14214 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:188347$14214_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:188349$14216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:188349$14216_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:188351$14218 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:188351$14218_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:188353$14220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$32 + connect \Y $not$libresoc.v:188353$14220_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:188355$14222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$36 + connect \Y $not$libresoc.v:188355$14222_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:188358$14225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:188358$14225_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:188341$14208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] \ni [3] } + connect \Y $reduce_or$libresoc.v:188341$14208_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:188343$14210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3:0] \ni [4] } + connect \Y $reduce_or$libresoc.v:188343$14210_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:188346$14213 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [4:0] \ni [5] } + connect \Y $reduce_or$libresoc.v:188346$14213_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:188348$14215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [5:0] \ni [6] } + connect \Y $reduce_or$libresoc.v:188348$14215_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:188350$14217 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [6:0] \ni [7] } + connect \Y $reduce_or$libresoc.v:188350$14217_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:188352$14219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 9 + parameter \Y_WIDTH 1 + connect \A { \i [7:0] \ni [8] } + connect \Y $reduce_or$libresoc.v:188352$14219_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:188354$14221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A { \i [8:0] \ni [9] } + connect \Y $reduce_or$libresoc.v:188354$14221_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:188356$14223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:188356$14223_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:188357$14224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:188357$14224_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:188359$14226 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:188359$14226_Y + end + connect \$7 $not$libresoc.v:188340$14207_Y + connect \$12 $reduce_or$libresoc.v:188341$14208_Y + connect \$11 $not$libresoc.v:188342$14209_Y + connect \$16 $reduce_or$libresoc.v:188343$14210_Y + connect \$15 $not$libresoc.v:188344$14211_Y + connect \$1 $not$libresoc.v:188345$14212_Y + connect \$20 $reduce_or$libresoc.v:188346$14213_Y + connect \$19 $not$libresoc.v:188347$14214_Y + connect \$24 $reduce_or$libresoc.v:188348$14215_Y + connect \$23 $not$libresoc.v:188349$14216_Y + connect \$28 $reduce_or$libresoc.v:188350$14217_Y + connect \$27 $not$libresoc.v:188351$14218_Y + connect \$32 $reduce_or$libresoc.v:188352$14219_Y + connect \$31 $not$libresoc.v:188353$14220_Y + connect \$36 $reduce_or$libresoc.v:188354$14221_Y + connect \$35 $not$libresoc.v:188355$14222_Y + connect \$39 $reduce_or$libresoc.v:188356$14223_Y + connect \$4 $reduce_or$libresoc.v:188357$14224_Y + connect \$3 $not$libresoc.v:188358$14225_Y + connect \$8 $reduce_or$libresoc.v:188359$14226_Y + connect \en_o \$39 + connect \o { \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } + connect \t9 \$35 + connect \t8 \$31 + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:188377.1-188398.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_SPR_spr1" +attribute \generator "nMigen" +module \wrpick_SPR_spr1 + attribute \src "libresoc.v:188392.17-188392.89" + wire $not$libresoc.v:188392$14227_Y + attribute \src "libresoc.v:188393.17-188393.89" + wire $reduce_or$libresoc.v:188393$14228_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:188392$14227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $not$libresoc.v:188392$14227_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:188393$14228 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:188393$14228_Y + end + connect \$1 $not$libresoc.v:188392$14227_Y + connect \$3 $reduce_or$libresoc.v:188393$14228_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "libresoc.v:188402.1-188423.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_STATE_msr" +attribute \generator "nMigen" +module \wrpick_STATE_msr + attribute \src "libresoc.v:188417.17-188417.89" + wire $not$libresoc.v:188417$14229_Y + attribute \src "libresoc.v:188418.17-188418.89" + wire $reduce_or$libresoc.v:188418$14230_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:188417$14229 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $not$libresoc.v:188417$14229_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:188418$14230 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:188418$14230_Y + end + connect \$1 $not$libresoc.v:188417$14229_Y + connect \$3 $reduce_or$libresoc.v:188418$14230_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "libresoc.v:188427.1-188457.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_STATE_nia" +attribute \generator "nMigen" +module \wrpick_STATE_nia + attribute \src "libresoc.v:188448.17-188448.89" + wire width 2 $not$libresoc.v:188448$14231_Y + attribute \src "libresoc.v:188450.17-188450.91" + wire $not$libresoc.v:188450$14233_Y + attribute \src "libresoc.v:188449.17-188449.103" + wire $reduce_or$libresoc.v:188449$14232_Y + attribute \src "libresoc.v:188451.17-188451.89" + wire $reduce_or$libresoc.v:188451$14234_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 2 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 2 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 2 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 2 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:188448$14231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \i + connect \Y $not$libresoc.v:188448$14231_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:188450$14233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:188450$14233_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:188449$14232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:188449$14232_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:188451$14234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:188451$14234_Y + end + connect \$1 $not$libresoc.v:188448$14231_Y + connect \$4 $reduce_or$libresoc.v:188449$14232_Y + connect \$3 $not$libresoc.v:188450$14233_Y + connect \$7 $reduce_or$libresoc.v:188451$14234_Y + connect \en_o \$7 + connect \o { \t1 \t0 } + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:188461.1-188500.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_ca" +attribute \generator "nMigen" +module \wrpick_XER_xer_ca + attribute \src "libresoc.v:188488.17-188488.91" + wire $not$libresoc.v:188488$14235_Y + attribute \src "libresoc.v:188490.17-188490.89" + wire width 3 $not$libresoc.v:188490$14237_Y + attribute \src "libresoc.v:188492.17-188492.91" + wire $not$libresoc.v:188492$14239_Y + attribute \src "libresoc.v:188489.18-188489.90" + wire $reduce_or$libresoc.v:188489$14236_Y + attribute \src "libresoc.v:188491.17-188491.103" + wire $reduce_or$libresoc.v:188491$14238_Y + attribute \src "libresoc.v:188493.17-188493.105" + wire $reduce_or$libresoc.v:188493$14240_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 3 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 3 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 3 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:188488$14235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:188488$14235_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:188490$14237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \i + connect \Y $not$libresoc.v:188490$14237_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:188492$14239 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:188492$14239_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:188489$14236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:188489$14236_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:188491$14238 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:188491$14238_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:188493$14240 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:188493$14240_Y + end + connect \$7 $not$libresoc.v:188488$14235_Y + connect \$11 $reduce_or$libresoc.v:188489$14236_Y + connect \$1 $not$libresoc.v:188490$14237_Y + connect \$4 $reduce_or$libresoc.v:188491$14238_Y + connect \$3 $not$libresoc.v:188492$14239_Y + connect \$8 $reduce_or$libresoc.v:188493$14240_Y + connect \en_o \$11 + connect \o { \t2 \t1 \t0 } + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:188504.1-188552.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_ov" +attribute \generator "nMigen" +module \wrpick_XER_xer_ov + attribute \src "libresoc.v:188537.17-188537.91" + wire $not$libresoc.v:188537$14241_Y + attribute \src "libresoc.v:188539.18-188539.93" + wire $not$libresoc.v:188539$14243_Y + attribute \src "libresoc.v:188541.17-188541.89" + wire width 4 $not$libresoc.v:188541$14245_Y + attribute \src "libresoc.v:188543.17-188543.91" + wire $not$libresoc.v:188543$14247_Y + attribute \src "libresoc.v:188538.18-188538.106" + wire $reduce_or$libresoc.v:188538$14242_Y + attribute \src "libresoc.v:188540.18-188540.90" + wire $reduce_or$libresoc.v:188540$14244_Y + attribute \src "libresoc.v:188542.17-188542.103" + wire $reduce_or$libresoc.v:188542$14246_Y + attribute \src "libresoc.v:188544.17-188544.105" + wire $reduce_or$libresoc.v:188544$14248_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 4 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 4 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 4 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 4 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:188537$14241 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:188537$14241_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:188539$14243 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:188539$14243_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:188541$14245 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \i + connect \Y $not$libresoc.v:188541$14245_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:188543$14247 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:188543$14247_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:188538$14242 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] \ni [3] } + connect \Y $reduce_or$libresoc.v:188538$14242_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:188540$14244 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:188540$14244_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:188542$14246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:188542$14246_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:188544$14248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:188544$14248_Y + end + connect \$7 $not$libresoc.v:188537$14241_Y + connect \$12 $reduce_or$libresoc.v:188538$14242_Y + connect \$11 $not$libresoc.v:188539$14243_Y + connect \$15 $reduce_or$libresoc.v:188540$14244_Y + connect \$1 $not$libresoc.v:188541$14245_Y + connect \$4 $reduce_or$libresoc.v:188542$14246_Y + connect \$3 $not$libresoc.v:188543$14247_Y + connect \$8 $reduce_or$libresoc.v:188544$14248_Y + connect \en_o \$15 + connect \o { \t3 \t2 \t1 \t0 } + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:188556.1-188604.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_so" +attribute \generator "nMigen" +module \wrpick_XER_xer_so + attribute \src "libresoc.v:188589.17-188589.91" + wire $not$libresoc.v:188589$14249_Y + attribute \src "libresoc.v:188591.18-188591.93" + wire $not$libresoc.v:188591$14251_Y + attribute \src "libresoc.v:188593.17-188593.89" + wire width 4 $not$libresoc.v:188593$14253_Y + attribute \src "libresoc.v:188595.17-188595.91" + wire $not$libresoc.v:188595$14255_Y + attribute \src "libresoc.v:188590.18-188590.106" + wire $reduce_or$libresoc.v:188590$14250_Y + attribute \src "libresoc.v:188592.18-188592.90" + wire $reduce_or$libresoc.v:188592$14252_Y + attribute \src "libresoc.v:188594.17-188594.103" + wire $reduce_or$libresoc.v:188594$14254_Y + attribute \src "libresoc.v:188596.17-188596.105" + wire $reduce_or$libresoc.v:188596$14256_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 4 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 4 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 4 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 4 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:188589$14249 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 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1 + connect \A { \i [2:0] \ni [3] } + connect \Y $reduce_or$libresoc.v:188590$14250_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:188592$14252 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:188592$14252_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:188594$14254 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:188594$14254_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:188596$14256 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:188596$14256_Y + end + connect \$7 $not$libresoc.v:188589$14249_Y + connect \$12 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_2_src32__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_src32__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_2_w2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_w2__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 4 \src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 5 \src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 6 \src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 7 \src2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 8 \src3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 9 \src3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 11 \wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 13 \wen$2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 15 \wen$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:188775$14257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reg_0_src10__data_o + connect \B \$7 + connect \Y $or$libresoc.v:188775$14257_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:188777$14259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reg_1_src21__data_o + connect \B \reg_2_src22__data_o + connect \Y $or$libresoc.v:188777$14259_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:188778$14260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reg_0_src20__data_o + connect \B \$14 + connect \Y $or$libresoc.v:188778$14260_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:188780$14262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reg_1_src31__data_o + connect \B \reg_2_src32__data_o + connect \Y $or$libresoc.v:188780$14262_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:188781$14263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reg_0_src30__data_o + connect \B \$21 + connect \Y $or$libresoc.v:188781$14263_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:188783$14265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reg_1_src11__data_o + connect \B \reg_2_src12__data_o + connect \Y $or$libresoc.v:188783$14265_Y end - attribute \src "libresoc.v:51940.3-51952.6" - process $proc$libresoc.v:51940$1841 - assign { } { } - assign { } { } - assign $0\cia__ren[3:0] $1\cia__ren[3:0] - attribute \src "libresoc.v:51941.5-51941.29" - switch \initial - attribute \src "libresoc.v:51941.9-51941.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:207" - switch \pc_i_ok - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $1\cia__ren[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cia__ren[3:0] 4'0001 - end - sync always - update \cia__ren $0\cia__ren[3:0] + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:188776$14258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \ren_delay$11 + connect \Y $reduce_or$libresoc.v:188776$14258_Y end - attribute \src "libresoc.v:51953.3-51973.6" - process $proc$libresoc.v:51953$1842 - assign { } { } - assign { } { } - assign $0\wen[3:0] $1\wen[3:0] - attribute \src "libresoc.v:51954.5-51954.29" - switch \initial - attribute \src "libresoc.v:51954.9-51954.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'11 - assign { } { } - assign $1\wen[3:0] $2\wen[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" - switch \$30 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wen[3:0] $3\wen[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" - switch \$32 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wen[3:0] 4'0001 - case - assign $3\wen[3:0] 4'0000 - end - case - assign $2\wen[3:0] 4'0000 - end - case - assign $1\wen[3:0] 4'0000 - end - sync always - update \wen $0\wen[3:0] + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:188779$14261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \ren_delay$18 + connect \Y $reduce_or$libresoc.v:188779$14261_Y end - attribute \src "libresoc.v:51974.3-51994.6" - process $proc$libresoc.v:51974$1843 - assign { } { } - assign { } { } - assign $0\data_i[63:0] $1\data_i[63:0] - attribute \src "libresoc.v:51975.5-51975.29" - switch \initial - attribute \src "libresoc.v:51975.9-51975.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'11 - assign { } { } - assign $1\data_i[63:0] $2\data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" - switch \$34 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\data_i[63:0] $3\data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" - switch \$36 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_i[63:0] \nia - case - assign $3\data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - case - assign $2\data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - case - assign $1\data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \data_i $0\data_i[63:0] + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:188782$14264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \ren_delay + connect \Y $reduce_or$libresoc.v:188782$14264_Y end - attribute \src "libresoc.v:51995.3-52010.6" - process $proc$libresoc.v:51995$1844 - assign { } { } - assign { } { } - assign $0\msr__ren[3:0] $1\msr__ren[3:0] - attribute \src "libresoc.v:51996.5-51996.29" - switch \initial - attribute \src "libresoc.v:51996.9-51996.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\msr__ren[3:0] $2\msr__ren[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - switch \$42 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\msr__ren[3:0] 4'0010 - case - assign $2\msr__ren[3:0] 4'0000 - end - case - assign $1\msr__ren[3:0] 4'0000 - end - sync always - update \msr__ren $0\msr__ren[3:0] + attribute \module_not_derived 1 + attribute \src "libresoc.v:188790.15-188809.4" + cell \reg_0$132 \reg_0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest10__data_i \reg_0_dest10__data_i + connect \dest10__wen \reg_0_dest10__wen + connect \dest20__data_i \reg_0_dest20__data_i + connect \dest20__wen \reg_0_dest20__wen + connect \dest30__data_i \reg_0_dest30__data_i + connect \dest30__wen \reg_0_dest30__wen + connect \r0__data_o \reg_0_r0__data_o + connect \r0__ren \reg_0_r0__ren + connect \src10__data_o \reg_0_src10__data_o + connect \src10__ren \reg_0_src10__ren + connect \src20__data_o \reg_0_src20__data_o + connect \src20__ren \reg_0_src20__ren + connect \src30__data_o \reg_0_src30__data_o + connect \src30__ren \reg_0_src30__ren + connect \w0__data_i \reg_0_w0__data_i + connect \w0__wen \reg_0_w0__wen end - attribute \src "libresoc.v:52011.3-52019.6" - process $proc$libresoc.v:52011$1845 - assign { } { } - assign { } { } - assign $0\dbg_dmi_din$next[63:0]$1846 $1\dbg_dmi_din$next[63:0]$1847 - attribute \src "libresoc.v:52012.5-52012.29" - switch \initial - attribute \src "libresoc.v:52012.9-52012.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dbg_dmi_din$next[63:0]$1847 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $1\dbg_dmi_din$next[63:0]$1847 \jtag_dmi0__din - end - sync always - update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$1846 + attribute \module_not_derived 1 + attribute \src "libresoc.v:188810.15-188829.4" + cell \reg_1$133 \reg_1 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest11__data_i \reg_1_dest11__data_i + connect \dest11__wen \reg_1_dest11__wen + connect \dest21__data_i \reg_1_dest21__data_i + connect \dest21__wen \reg_1_dest21__wen + connect \dest31__data_i \reg_1_dest31__data_i + connect \dest31__wen \reg_1_dest31__wen + connect \r1__data_o \reg_1_r1__data_o + connect \r1__ren \reg_1_r1__ren + connect \src11__data_o \reg_1_src11__data_o + connect \src11__ren \reg_1_src11__ren + connect \src21__data_o \reg_1_src21__data_o + connect \src21__ren \reg_1_src21__ren + connect \src31__data_o \reg_1_src31__data_o + connect \src31__ren \reg_1_src31__ren + connect \w1__data_i \reg_1_w1__data_i + connect \w1__wen \reg_1_w1__wen end - attribute \src "libresoc.v:52020.3-52044.6" - process $proc$libresoc.v:52020$1848 - assign { } { } - assign { } { } + attribute \module_not_derived 1 + attribute \src "libresoc.v:188830.15-188849.4" + cell \reg_2$134 \reg_2 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest12__data_i \reg_2_dest12__data_i + connect \dest12__wen \reg_2_dest12__wen + connect \dest22__data_i \reg_2_dest22__data_i + connect \dest22__wen \reg_2_dest22__wen + connect \dest32__data_i \reg_2_dest32__data_i + connect \dest32__wen \reg_2_dest32__wen + connect \r2__data_o \reg_2_r2__data_o + connect \r2__ren \reg_2_r2__ren + connect \src12__data_o \reg_2_src12__data_o + connect \src12__ren \reg_2_src12__ren + connect \src22__data_o \reg_2_src22__data_o + connect \src22__ren \reg_2_src22__ren + connect \src32__data_o \reg_2_src32__data_o + connect \src32__ren \reg_2_src32__ren + connect \w2__data_i \reg_2_w2__data_i + connect \w2__wen \reg_2_w2__wen + end + attribute \src "libresoc.v:188609.7-188609.20" + process $proc$libresoc.v:188609$14283 assign { } { } - assign $0\pc_changed$next[0:0]$1849 $3\pc_changed$next[0:0]$1852 - attribute \src "libresoc.v:52021.5-52021.29" - switch \initial - attribute \src "libresoc.v:52021.9-52021.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\pc_changed$next[0:0]$1850 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'11 - assign { } { } - assign $1\pc_changed$next[0:0]$1850 $2\pc_changed$next[0:0]$1851 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:309" - switch \$44 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\pc_changed$next[0:0]$1851 1'1 - case - assign $2\pc_changed$next[0:0]$1851 \pc_changed - end - case - assign $1\pc_changed$next[0:0]$1850 \pc_changed - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\pc_changed$next[0:0]$1852 1'0 - case - assign $3\pc_changed$next[0:0]$1852 $1\pc_changed$next[0:0]$1850 - end + assign $0\initial[0:0] 1'0 sync always - update \pc_changed$next $0\pc_changed$next[0:0]$1849 + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:52045.3-52167.6" - process $proc$libresoc.v:52045$1853 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:188743.13-188743.29" + process $proc$libresoc.v:188743$14284 assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\core_asmcode$next[7:0]$1854 $1\core_asmcode$next[7:0]$1913 - assign $0\core_core_cia$next[63:0]$1855 $1\core_core_cia$next[63:0]$1914 - assign $0\core_core_cr_rd$next[7:0]$1856 $1\core_core_cr_rd$next[7:0]$1915 - assign { } { } - assign $0\core_core_cr_wr$next[7:0]$1858 $1\core_core_cr_wr$next[7:0]$1917 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\core_core_fn_unit$next[11:0]$1868 $1\core_core_fn_unit$next[11:0]$1927 - assign $0\core_core_input_carry$next[1:0]$1869 $1\core_core_input_carry$next[1:0]$1928 - assign $0\core_core_insn$next[31:0]$1870 $1\core_core_insn$next[31:0]$1929 - assign $0\core_core_insn_type$next[6:0]$1871 $1\core_core_insn_type$next[6:0]$1930 - assign $0\core_core_is_32bit$next[0:0]$1872 $1\core_core_is_32bit$next[0:0]$1931 - assign $0\core_core_lk$next[0:0]$1873 $1\core_core_lk$next[0:0]$1932 - assign $0\core_core_msr$next[63:0]$1874 $1\core_core_msr$next[63:0]$1933 - assign $0\core_core_oe$next[0:0]$1875 $1\core_core_oe$next[0:0]$1934 - assign { } { } - assign $0\core_core_rc$next[0:0]$1877 $1\core_core_rc$next[0:0]$1936 - assign { } { } - assign $0\core_core_trapaddr$next[12:0]$1879 $1\core_core_trapaddr$next[12:0]$1938 - assign $0\core_core_traptype$next[7:0]$1880 $1\core_core_traptype$next[7:0]$1939 - assign $0\core_cr_in1$next[2:0]$1881 $1\core_cr_in1$next[2:0]$1940 - assign { } { } - assign $0\core_cr_in2$48$next[2:0]$1883 $1\core_cr_in2$48$next[2:0]$1942 - assign $0\core_cr_in2$next[2:0]$1884 $1\core_cr_in2$next[2:0]$1943 - assign { } { } - assign { } { } - assign $0\core_cr_out$next[2:0]$1887 $1\core_cr_out$next[2:0]$1946 - assign { } { } - assign $0\core_ea$next[4:0]$1889 $1\core_ea$next[4:0]$1948 - assign { } { } - assign $0\core_fast1$next[2:0]$1891 $1\core_fast1$next[2:0]$1950 - assign { } { } - assign $0\core_fast2$next[2:0]$1893 $1\core_fast2$next[2:0]$1952 - assign { } { } - assign $0\core_fasto1$next[2:0]$1895 $1\core_fasto1$next[2:0]$1954 - assign { } { } - assign $0\core_fasto2$next[2:0]$1897 $1\core_fasto2$next[2:0]$1956 - assign { } { } - assign $0\core_reg1$next[4:0]$1899 $1\core_reg1$next[4:0]$1958 - assign { } { } - assign $0\core_reg2$next[4:0]$1901 $1\core_reg2$next[4:0]$1960 - assign { } { } - assign $0\core_reg3$next[4:0]$1903 $1\core_reg3$next[4:0]$1962 - assign { } { } - assign $0\core_rego$next[4:0]$1905 $1\core_rego$next[4:0]$1964 - assign { } { } - assign $0\core_spr1$next[9:0]$1907 $1\core_spr1$next[9:0]$1966 - assign { } { } - assign $0\core_spro$next[9:0]$1909 $1\core_spro$next[9:0]$1968 - assign { } { } - assign $0\core_xer_in$next[2:0]$1911 $1\core_xer_in$next[2:0]$1970 - assign $0\core_xer_out$next[0:0]$1912 $1\core_xer_out$next[0:0]$1971 - assign $0\core_core_cr_rd_ok$next[0:0]$1857 $4\core_core_cr_rd_ok$next[0:0]$2090 - assign $0\core_core_cr_wr_ok$next[0:0]$1859 $4\core_core_cr_wr_ok$next[0:0]$2091 - assign $0\core_core_exc_$signal$50$next[0:0]$1860 $4\core_core_exc_$signal$50$next[0:0]$2092 - assign $0\core_core_exc_$signal$51$next[0:0]$1861 $4\core_core_exc_$signal$51$next[0:0]$2093 - assign $0\core_core_exc_$signal$52$next[0:0]$1862 $4\core_core_exc_$signal$52$next[0:0]$2094 - assign $0\core_core_exc_$signal$53$next[0:0]$1863 $4\core_core_exc_$signal$53$next[0:0]$2095 - assign $0\core_core_exc_$signal$54$next[0:0]$1864 $4\core_core_exc_$signal$54$next[0:0]$2096 - assign $0\core_core_exc_$signal$55$next[0:0]$1865 $4\core_core_exc_$signal$55$next[0:0]$2097 - assign $0\core_core_exc_$signal$56$next[0:0]$1866 $4\core_core_exc_$signal$56$next[0:0]$2098 - assign $0\core_core_exc_$signal$next[0:0]$1867 $4\core_core_exc_$signal$next[0:0]$2099 - assign $0\core_core_oe_ok$next[0:0]$1876 $4\core_core_oe_ok$next[0:0]$2100 - assign $0\core_core_rc_ok$next[0:0]$1878 $4\core_core_rc_ok$next[0:0]$2101 - assign $0\core_cr_in1_ok$next[0:0]$1882 $4\core_cr_in1_ok$next[0:0]$2102 - assign $0\core_cr_in2_ok$49$next[0:0]$1885 $4\core_cr_in2_ok$49$next[0:0]$2103 - assign $0\core_cr_in2_ok$next[0:0]$1886 $4\core_cr_in2_ok$next[0:0]$2104 - assign $0\core_cr_out_ok$next[0:0]$1888 $4\core_cr_out_ok$next[0:0]$2105 - assign $0\core_ea_ok$next[0:0]$1890 $4\core_ea_ok$next[0:0]$2106 - assign $0\core_fast1_ok$next[0:0]$1892 $4\core_fast1_ok$next[0:0]$2107 - assign $0\core_fast2_ok$next[0:0]$1894 $4\core_fast2_ok$next[0:0]$2108 - assign $0\core_fasto1_ok$next[0:0]$1896 $4\core_fasto1_ok$next[0:0]$2109 - assign $0\core_fasto2_ok$next[0:0]$1898 $4\core_fasto2_ok$next[0:0]$2110 - assign $0\core_reg1_ok$next[0:0]$1900 $4\core_reg1_ok$next[0:0]$2111 - assign $0\core_reg2_ok$next[0:0]$1902 $4\core_reg2_ok$next[0:0]$2112 - assign $0\core_reg3_ok$next[0:0]$1904 $4\core_reg3_ok$next[0:0]$2113 - assign $0\core_rego_ok$next[0:0]$1906 $4\core_rego_ok$next[0:0]$2114 - assign $0\core_spr1_ok$next[0:0]$1908 $4\core_spr1_ok$next[0:0]$2115 - assign $0\core_spro_ok$next[0:0]$1910 $4\core_spro_ok$next[0:0]$2116 - attribute \src "libresoc.v:52046.5-52046.29" - switch \initial - attribute \src "libresoc.v:52046.9-52046.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\core_core_is_32bit$next[0:0]$1931 $1\core_core_cr_wr_ok$next[0:0]$1918 $1\core_core_cr_wr$next[7:0]$1917 $1\core_core_cr_rd_ok$next[0:0]$1916 $1\core_core_cr_rd$next[7:0]$1915 $1\core_core_trapaddr$next[12:0]$1938 $1\core_core_exc_$signal$56$next[0:0]$1925 $1\core_core_exc_$signal$55$next[0:0]$1924 $1\core_core_exc_$signal$54$next[0:0]$1923 $1\core_core_exc_$signal$53$next[0:0]$1922 $1\core_core_exc_$signal$52$next[0:0]$1921 $1\core_core_exc_$signal$51$next[0:0]$1920 $1\core_core_exc_$signal$50$next[0:0]$1919 $1\core_core_exc_$signal$next[0:0]$1926 $1\core_core_traptype$next[7:0]$1939 $1\core_core_input_carry$next[1:0]$1928 $1\core_core_oe_ok$next[0:0]$1935 $1\core_core_oe$next[0:0]$1934 $1\core_core_rc_ok$next[0:0]$1937 $1\core_core_rc$next[0:0]$1936 $1\core_core_lk$next[0:0]$1932 $1\core_core_fn_unit$next[11:0]$1927 $1\core_core_insn_type$next[6:0]$1930 $1\core_core_insn$next[31:0]$1929 $1\core_core_cia$next[63:0]$1914 $1\core_core_msr$next[63:0]$1933 $1\core_cr_out_ok$next[0:0]$1947 $1\core_cr_out$next[2:0]$1946 $1\core_cr_in2_ok$49$next[0:0]$1944 $1\core_cr_in2$48$next[2:0]$1942 $1\core_cr_in2_ok$next[0:0]$1945 $1\core_cr_in2$next[2:0]$1943 $1\core_cr_in1_ok$next[0:0]$1941 $1\core_cr_in1$next[2:0]$1940 $1\core_fasto2_ok$next[0:0]$1957 $1\core_fasto2$next[2:0]$1956 $1\core_fasto1_ok$next[0:0]$1955 $1\core_fasto1$next[2:0]$1954 $1\core_fast2_ok$next[0:0]$1953 $1\core_fast2$next[2:0]$1952 $1\core_fast1_ok$next[0:0]$1951 $1\core_fast1$next[2:0]$1950 $1\core_xer_out$next[0:0]$1971 $1\core_xer_in$next[2:0]$1970 $1\core_spr1_ok$next[0:0]$1967 $1\core_spr1$next[9:0]$1966 $1\core_spro_ok$next[0:0]$1969 $1\core_spro$next[9:0]$1968 $1\core_reg3_ok$next[0:0]$1963 $1\core_reg3$next[4:0]$1962 $1\core_reg2_ok$next[0:0]$1961 $1\core_reg2$next[4:0]$1960 $1\core_reg1_ok$next[0:0]$1959 $1\core_reg1$next[4:0]$1958 $1\core_ea_ok$next[0:0]$1949 $1\core_ea$next[4:0]$1948 $1\core_rego_ok$next[0:0]$1965 $1\core_rego$next[4:0]$1964 $1\core_asmcode$next[7:0]$1913 } 330'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\core_asmcode$next[7:0]$1913 $2\core_asmcode$next[7:0]$1972 - assign $1\core_core_cia$next[63:0]$1914 $2\core_core_cia$next[63:0]$1973 - assign $1\core_core_cr_rd$next[7:0]$1915 $2\core_core_cr_rd$next[7:0]$1974 - assign $1\core_core_cr_rd_ok$next[0:0]$1916 $2\core_core_cr_rd_ok$next[0:0]$1975 - assign $1\core_core_cr_wr$next[7:0]$1917 $2\core_core_cr_wr$next[7:0]$1976 - assign $1\core_core_cr_wr_ok$next[0:0]$1918 $2\core_core_cr_wr_ok$next[0:0]$1977 - assign $1\core_core_exc_$signal$50$next[0:0]$1919 $2\core_core_exc_$signal$50$next[0:0]$1978 - assign $1\core_core_exc_$signal$51$next[0:0]$1920 $2\core_core_exc_$signal$51$next[0:0]$1979 - assign $1\core_core_exc_$signal$52$next[0:0]$1921 $2\core_core_exc_$signal$52$next[0:0]$1980 - assign $1\core_core_exc_$signal$53$next[0:0]$1922 $2\core_core_exc_$signal$53$next[0:0]$1981 - assign $1\core_core_exc_$signal$54$next[0:0]$1923 $2\core_core_exc_$signal$54$next[0:0]$1982 - assign $1\core_core_exc_$signal$55$next[0:0]$1924 $2\core_core_exc_$signal$55$next[0:0]$1983 - assign $1\core_core_exc_$signal$56$next[0:0]$1925 $2\core_core_exc_$signal$56$next[0:0]$1984 - assign $1\core_core_exc_$signal$next[0:0]$1926 $2\core_core_exc_$signal$next[0:0]$1985 - assign $1\core_core_fn_unit$next[11:0]$1927 $2\core_core_fn_unit$next[11:0]$1986 - assign $1\core_core_input_carry$next[1:0]$1928 $2\core_core_input_carry$next[1:0]$1987 - assign $1\core_core_insn$next[31:0]$1929 $2\core_core_insn$next[31:0]$1988 - assign $1\core_core_insn_type$next[6:0]$1930 $2\core_core_insn_type$next[6:0]$1989 - assign $1\core_core_is_32bit$next[0:0]$1931 $2\core_core_is_32bit$next[0:0]$1990 - assign $1\core_core_lk$next[0:0]$1932 $2\core_core_lk$next[0:0]$1991 - assign $1\core_core_msr$next[63:0]$1933 $2\core_core_msr$next[63:0]$1992 - assign $1\core_core_oe$next[0:0]$1934 $2\core_core_oe$next[0:0]$1993 - assign $1\core_core_oe_ok$next[0:0]$1935 $2\core_core_oe_ok$next[0:0]$1994 - assign $1\core_core_rc$next[0:0]$1936 $2\core_core_rc$next[0:0]$1995 - assign $1\core_core_rc_ok$next[0:0]$1937 $2\core_core_rc_ok$next[0:0]$1996 - assign $1\core_core_trapaddr$next[12:0]$1938 $2\core_core_trapaddr$next[12:0]$1997 - assign $1\core_core_traptype$next[7:0]$1939 $2\core_core_traptype$next[7:0]$1998 - assign $1\core_cr_in1$next[2:0]$1940 $2\core_cr_in1$next[2:0]$1999 - assign $1\core_cr_in1_ok$next[0:0]$1941 $2\core_cr_in1_ok$next[0:0]$2000 - assign $1\core_cr_in2$48$next[2:0]$1942 $2\core_cr_in2$48$next[2:0]$2001 - assign $1\core_cr_in2$next[2:0]$1943 $2\core_cr_in2$next[2:0]$2002 - assign $1\core_cr_in2_ok$49$next[0:0]$1944 $2\core_cr_in2_ok$49$next[0:0]$2003 - assign $1\core_cr_in2_ok$next[0:0]$1945 $2\core_cr_in2_ok$next[0:0]$2004 - assign $1\core_cr_out$next[2:0]$1946 $2\core_cr_out$next[2:0]$2005 - assign $1\core_cr_out_ok$next[0:0]$1947 $2\core_cr_out_ok$next[0:0]$2006 - assign $1\core_ea$next[4:0]$1948 $2\core_ea$next[4:0]$2007 - assign $1\core_ea_ok$next[0:0]$1949 $2\core_ea_ok$next[0:0]$2008 - assign $1\core_fast1$next[2:0]$1950 $2\core_fast1$next[2:0]$2009 - assign $1\core_fast1_ok$next[0:0]$1951 $2\core_fast1_ok$next[0:0]$2010 - assign $1\core_fast2$next[2:0]$1952 $2\core_fast2$next[2:0]$2011 - assign $1\core_fast2_ok$next[0:0]$1953 $2\core_fast2_ok$next[0:0]$2012 - assign $1\core_fasto1$next[2:0]$1954 $2\core_fasto1$next[2:0]$2013 - assign $1\core_fasto1_ok$next[0:0]$1955 $2\core_fasto1_ok$next[0:0]$2014 - assign $1\core_fasto2$next[2:0]$1956 $2\core_fasto2$next[2:0]$2015 - assign $1\core_fasto2_ok$next[0:0]$1957 $2\core_fasto2_ok$next[0:0]$2016 - assign $1\core_reg1$next[4:0]$1958 $2\core_reg1$next[4:0]$2017 - assign $1\core_reg1_ok$next[0:0]$1959 $2\core_reg1_ok$next[0:0]$2018 - assign $1\core_reg2$next[4:0]$1960 $2\core_reg2$next[4:0]$2019 - assign $1\core_reg2_ok$next[0:0]$1961 $2\core_reg2_ok$next[0:0]$2020 - assign $1\core_reg3$next[4:0]$1962 $2\core_reg3$next[4:0]$2021 - assign $1\core_reg3_ok$next[0:0]$1963 $2\core_reg3_ok$next[0:0]$2022 - assign $1\core_rego$next[4:0]$1964 $2\core_rego$next[4:0]$2023 - assign $1\core_rego_ok$next[0:0]$1965 $2\core_rego_ok$next[0:0]$2024 - assign $1\core_spr1$next[9:0]$1966 $2\core_spr1$next[9:0]$2025 - assign $1\core_spr1_ok$next[0:0]$1967 $2\core_spr1_ok$next[0:0]$2026 - assign $1\core_spro$next[9:0]$1968 $2\core_spro$next[9:0]$2027 - assign $1\core_spro_ok$next[0:0]$1969 $2\core_spro_ok$next[0:0]$2028 - assign $1\core_xer_in$next[2:0]$1970 $2\core_xer_in$next[2:0]$2029 - assign $1\core_xer_out$next[0:0]$1971 $2\core_xer_out$next[0:0]$2030 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\core_asmcode$next[7:0]$1972 \core_asmcode - assign $2\core_core_cia$next[63:0]$1973 \core_core_cia - assign $2\core_core_cr_rd$next[7:0]$1974 \core_core_cr_rd - assign $2\core_core_cr_rd_ok$next[0:0]$1975 \core_core_cr_rd_ok - assign $2\core_core_cr_wr$next[7:0]$1976 \core_core_cr_wr - assign $2\core_core_cr_wr_ok$next[0:0]$1977 \core_core_cr_wr_ok - assign $2\core_core_exc_$signal$50$next[0:0]$1978 \core_core_exc_$signal$50 - assign $2\core_core_exc_$signal$51$next[0:0]$1979 \core_core_exc_$signal$51 - assign $2\core_core_exc_$signal$52$next[0:0]$1980 \core_core_exc_$signal$52 - assign $2\core_core_exc_$signal$53$next[0:0]$1981 \core_core_exc_$signal$53 - assign $2\core_core_exc_$signal$54$next[0:0]$1982 \core_core_exc_$signal$54 - assign $2\core_core_exc_$signal$55$next[0:0]$1983 \core_core_exc_$signal$55 - assign $2\core_core_exc_$signal$56$next[0:0]$1984 \core_core_exc_$signal$56 - assign $2\core_core_exc_$signal$next[0:0]$1985 \core_core_exc_$signal - assign $2\core_core_fn_unit$next[11:0]$1986 \core_core_fn_unit - assign $2\core_core_input_carry$next[1:0]$1987 \core_core_input_carry - assign $2\core_core_insn$next[31:0]$1988 \core_core_insn - assign $2\core_core_insn_type$next[6:0]$1989 \core_core_insn_type - assign $2\core_core_is_32bit$next[0:0]$1990 \core_core_is_32bit - assign $2\core_core_lk$next[0:0]$1991 \core_core_lk - assign $2\core_core_msr$next[63:0]$1992 \core_core_msr - assign $2\core_core_oe$next[0:0]$1993 \core_core_oe - assign $2\core_core_oe_ok$next[0:0]$1994 \core_core_oe_ok - assign $2\core_core_rc$next[0:0]$1995 \core_core_rc - assign $2\core_core_rc_ok$next[0:0]$1996 \core_core_rc_ok - assign $2\core_core_trapaddr$next[12:0]$1997 \core_core_trapaddr - assign $2\core_core_traptype$next[7:0]$1998 \core_core_traptype - assign $2\core_cr_in1$next[2:0]$1999 \core_cr_in1 - assign $2\core_cr_in1_ok$next[0:0]$2000 \core_cr_in1_ok - assign $2\core_cr_in2$48$next[2:0]$2001 \core_cr_in2$48 - assign $2\core_cr_in2$next[2:0]$2002 \core_cr_in2 - assign $2\core_cr_in2_ok$49$next[0:0]$2003 \core_cr_in2_ok$49 - assign $2\core_cr_in2_ok$next[0:0]$2004 \core_cr_in2_ok - assign $2\core_cr_out$next[2:0]$2005 \core_cr_out - assign $2\core_cr_out_ok$next[0:0]$2006 \core_cr_out_ok - assign $2\core_ea$next[4:0]$2007 \core_ea - assign $2\core_ea_ok$next[0:0]$2008 \core_ea_ok - assign $2\core_fast1$next[2:0]$2009 \core_fast1 - assign $2\core_fast1_ok$next[0:0]$2010 \core_fast1_ok - assign $2\core_fast2$next[2:0]$2011 \core_fast2 - assign $2\core_fast2_ok$next[0:0]$2012 \core_fast2_ok - assign $2\core_fasto1$next[2:0]$2013 \core_fasto1 - assign $2\core_fasto1_ok$next[0:0]$2014 \core_fasto1_ok - assign $2\core_fasto2$next[2:0]$2015 \core_fasto2 - assign $2\core_fasto2_ok$next[0:0]$2016 \core_fasto2_ok - assign $2\core_reg1$next[4:0]$2017 \core_reg1 - assign $2\core_reg1_ok$next[0:0]$2018 \core_reg1_ok - assign $2\core_reg2$next[4:0]$2019 \core_reg2 - assign $2\core_reg2_ok$next[0:0]$2020 \core_reg2_ok - assign $2\core_reg3$next[4:0]$2021 \core_reg3 - assign $2\core_reg3_ok$next[0:0]$2022 \core_reg3_ok - assign $2\core_rego$next[4:0]$2023 \core_rego - assign $2\core_rego_ok$next[0:0]$2024 \core_rego_ok - assign $2\core_spr1$next[9:0]$2025 \core_spr1 - assign $2\core_spr1_ok$next[0:0]$2026 \core_spr1_ok - assign $2\core_spro$next[9:0]$2027 \core_spro - assign $2\core_spro_ok$next[0:0]$2028 \core_spro_ok - assign $2\core_xer_in$next[2:0]$2029 \core_xer_in - assign $2\core_xer_out$next[0:0]$2030 \core_xer_out - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $2\core_core_is_32bit$next[0:0]$1990 $2\core_core_cr_wr_ok$next[0:0]$1977 $2\core_core_cr_wr$next[7:0]$1976 $2\core_core_cr_rd_ok$next[0:0]$1975 $2\core_core_cr_rd$next[7:0]$1974 $2\core_core_trapaddr$next[12:0]$1997 $2\core_core_exc_$signal$56$next[0:0]$1984 $2\core_core_exc_$signal$55$next[0:0]$1983 $2\core_core_exc_$signal$54$next[0:0]$1982 $2\core_core_exc_$signal$53$next[0:0]$1981 $2\core_core_exc_$signal$52$next[0:0]$1980 $2\core_core_exc_$signal$51$next[0:0]$1979 $2\core_core_exc_$signal$50$next[0:0]$1978 $2\core_core_exc_$signal$next[0:0]$1985 $2\core_core_traptype$next[7:0]$1998 $2\core_core_input_carry$next[1:0]$1987 $2\core_core_oe_ok$next[0:0]$1994 $2\core_core_oe$next[0:0]$1993 $2\core_core_rc_ok$next[0:0]$1996 $2\core_core_rc$next[0:0]$1995 $2\core_core_lk$next[0:0]$1991 $2\core_core_fn_unit$next[11:0]$1986 $2\core_core_insn_type$next[6:0]$1989 $2\core_core_insn$next[31:0]$1988 $2\core_core_cia$next[63:0]$1973 $2\core_core_msr$next[63:0]$1992 $2\core_cr_out_ok$next[0:0]$2006 $2\core_cr_out$next[2:0]$2005 $2\core_cr_in2_ok$49$next[0:0]$2003 $2\core_cr_in2$48$next[2:0]$2001 $2\core_cr_in2_ok$next[0:0]$2004 $2\core_cr_in2$next[2:0]$2002 $2\core_cr_in1_ok$next[0:0]$2000 $2\core_cr_in1$next[2:0]$1999 $2\core_fasto2_ok$next[0:0]$2016 $2\core_fasto2$next[2:0]$2015 $2\core_fasto1_ok$next[0:0]$2014 $2\core_fasto1$next[2:0]$2013 $2\core_fast2_ok$next[0:0]$2012 $2\core_fast2$next[2:0]$2011 $2\core_fast1_ok$next[0:0]$2010 $2\core_fast1$next[2:0]$2009 $2\core_xer_out$next[0:0]$2030 $2\core_xer_in$next[2:0]$2029 $2\core_spr1_ok$next[0:0]$2026 $2\core_spr1$next[9:0]$2025 $2\core_spro_ok$next[0:0]$2028 $2\core_spro$next[9:0]$2027 $2\core_reg3_ok$next[0:0]$2022 $2\core_reg3$next[4:0]$2021 $2\core_reg2_ok$next[0:0]$2020 $2\core_reg2$next[4:0]$2019 $2\core_reg1_ok$next[0:0]$2018 $2\core_reg1$next[4:0]$2017 $2\core_ea_ok$next[0:0]$2008 $2\core_ea$next[4:0]$2007 $2\core_rego_ok$next[0:0]$2024 $2\core_rego$next[4:0]$2023 $2\core_asmcode$next[7:0]$1972 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$9 \dec2_exc_$signal$8 \dec2_exc_$signal$7 \dec2_exc_$signal$6 \dec2_exc_$signal$5 \dec2_exc_$signal$4 \dec2_exc_$signal$3 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$2 \dec2_cr_in2$1 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } - end - attribute \src "libresoc.v:0.0-0.0" - case 2'11 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\core_asmcode$next[7:0]$1913 $3\core_asmcode$next[7:0]$2031 - assign $1\core_core_cia$next[63:0]$1914 $3\core_core_cia$next[63:0]$2032 - assign $1\core_core_cr_rd$next[7:0]$1915 $3\core_core_cr_rd$next[7:0]$2033 - assign $1\core_core_cr_rd_ok$next[0:0]$1916 $3\core_core_cr_rd_ok$next[0:0]$2034 - assign $1\core_core_cr_wr$next[7:0]$1917 $3\core_core_cr_wr$next[7:0]$2035 - assign $1\core_core_cr_wr_ok$next[0:0]$1918 $3\core_core_cr_wr_ok$next[0:0]$2036 - assign $1\core_core_exc_$signal$50$next[0:0]$1919 $3\core_core_exc_$signal$50$next[0:0]$2037 - assign $1\core_core_exc_$signal$51$next[0:0]$1920 $3\core_core_exc_$signal$51$next[0:0]$2038 - assign $1\core_core_exc_$signal$52$next[0:0]$1921 $3\core_core_exc_$signal$52$next[0:0]$2039 - assign $1\core_core_exc_$signal$53$next[0:0]$1922 $3\core_core_exc_$signal$53$next[0:0]$2040 - assign $1\core_core_exc_$signal$54$next[0:0]$1923 $3\core_core_exc_$signal$54$next[0:0]$2041 - assign $1\core_core_exc_$signal$55$next[0:0]$1924 $3\core_core_exc_$signal$55$next[0:0]$2042 - assign $1\core_core_exc_$signal$56$next[0:0]$1925 $3\core_core_exc_$signal$56$next[0:0]$2043 - assign $1\core_core_exc_$signal$next[0:0]$1926 $3\core_core_exc_$signal$next[0:0]$2044 - assign $1\core_core_fn_unit$next[11:0]$1927 $3\core_core_fn_unit$next[11:0]$2045 - assign $1\core_core_input_carry$next[1:0]$1928 $3\core_core_input_carry$next[1:0]$2046 - assign $1\core_core_insn$next[31:0]$1929 $3\core_core_insn$next[31:0]$2047 - assign $1\core_core_insn_type$next[6:0]$1930 $3\core_core_insn_type$next[6:0]$2048 - assign $1\core_core_is_32bit$next[0:0]$1931 $3\core_core_is_32bit$next[0:0]$2049 - assign $1\core_core_lk$next[0:0]$1932 $3\core_core_lk$next[0:0]$2050 - assign $1\core_core_msr$next[63:0]$1933 $3\core_core_msr$next[63:0]$2051 - assign $1\core_core_oe$next[0:0]$1934 $3\core_core_oe$next[0:0]$2052 - assign $1\core_core_oe_ok$next[0:0]$1935 $3\core_core_oe_ok$next[0:0]$2053 - assign $1\core_core_rc$next[0:0]$1936 $3\core_core_rc$next[0:0]$2054 - assign $1\core_core_rc_ok$next[0:0]$1937 $3\core_core_rc_ok$next[0:0]$2055 - assign $1\core_core_trapaddr$next[12:0]$1938 $3\core_core_trapaddr$next[12:0]$2056 - assign $1\core_core_traptype$next[7:0]$1939 $3\core_core_traptype$next[7:0]$2057 - assign $1\core_cr_in1$next[2:0]$1940 $3\core_cr_in1$next[2:0]$2058 - assign $1\core_cr_in1_ok$next[0:0]$1941 $3\core_cr_in1_ok$next[0:0]$2059 - assign $1\core_cr_in2$48$next[2:0]$1942 $3\core_cr_in2$48$next[2:0]$2060 - assign $1\core_cr_in2$next[2:0]$1943 $3\core_cr_in2$next[2:0]$2061 - assign $1\core_cr_in2_ok$49$next[0:0]$1944 $3\core_cr_in2_ok$49$next[0:0]$2062 - assign $1\core_cr_in2_ok$next[0:0]$1945 $3\core_cr_in2_ok$next[0:0]$2063 - assign $1\core_cr_out$next[2:0]$1946 $3\core_cr_out$next[2:0]$2064 - assign $1\core_cr_out_ok$next[0:0]$1947 $3\core_cr_out_ok$next[0:0]$2065 - assign $1\core_ea$next[4:0]$1948 $3\core_ea$next[4:0]$2066 - assign $1\core_ea_ok$next[0:0]$1949 $3\core_ea_ok$next[0:0]$2067 - assign $1\core_fast1$next[2:0]$1950 $3\core_fast1$next[2:0]$2068 - assign $1\core_fast1_ok$next[0:0]$1951 $3\core_fast1_ok$next[0:0]$2069 - assign $1\core_fast2$next[2:0]$1952 $3\core_fast2$next[2:0]$2070 - assign $1\core_fast2_ok$next[0:0]$1953 $3\core_fast2_ok$next[0:0]$2071 - assign $1\core_fasto1$next[2:0]$1954 $3\core_fasto1$next[2:0]$2072 - assign $1\core_fasto1_ok$next[0:0]$1955 $3\core_fasto1_ok$next[0:0]$2073 - assign $1\core_fasto2$next[2:0]$1956 $3\core_fasto2$next[2:0]$2074 - assign $1\core_fasto2_ok$next[0:0]$1957 $3\core_fasto2_ok$next[0:0]$2075 - assign $1\core_reg1$next[4:0]$1958 $3\core_reg1$next[4:0]$2076 - assign $1\core_reg1_ok$next[0:0]$1959 $3\core_reg1_ok$next[0:0]$2077 - assign $1\core_reg2$next[4:0]$1960 $3\core_reg2$next[4:0]$2078 - assign $1\core_reg2_ok$next[0:0]$1961 $3\core_reg2_ok$next[0:0]$2079 - assign $1\core_reg3$next[4:0]$1962 $3\core_reg3$next[4:0]$2080 - assign $1\core_reg3_ok$next[0:0]$1963 $3\core_reg3_ok$next[0:0]$2081 - assign $1\core_rego$next[4:0]$1964 $3\core_rego$next[4:0]$2082 - assign $1\core_rego_ok$next[0:0]$1965 $3\core_rego_ok$next[0:0]$2083 - assign $1\core_spr1$next[9:0]$1966 $3\core_spr1$next[9:0]$2084 - assign $1\core_spr1_ok$next[0:0]$1967 $3\core_spr1_ok$next[0:0]$2085 - assign $1\core_spro$next[9:0]$1968 $3\core_spro$next[9:0]$2086 - assign $1\core_spro_ok$next[0:0]$1969 $3\core_spro_ok$next[0:0]$2087 - assign $1\core_xer_in$next[2:0]$1970 $3\core_xer_in$next[2:0]$2088 - assign $1\core_xer_out$next[0:0]$1971 $3\core_xer_out$next[0:0]$2089 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" - switch \$57 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $3\core_core_is_32bit$next[0:0]$2049 $3\core_core_cr_wr_ok$next[0:0]$2036 $3\core_core_cr_wr$next[7:0]$2035 $3\core_core_cr_rd_ok$next[0:0]$2034 $3\core_core_cr_rd$next[7:0]$2033 $3\core_core_trapaddr$next[12:0]$2056 $3\core_core_exc_$signal$56$next[0:0]$2043 $3\core_core_exc_$signal$55$next[0:0]$2042 $3\core_core_exc_$signal$54$next[0:0]$2041 $3\core_core_exc_$signal$53$next[0:0]$2040 $3\core_core_exc_$signal$52$next[0:0]$2039 $3\core_core_exc_$signal$51$next[0:0]$2038 $3\core_core_exc_$signal$50$next[0:0]$2037 $3\core_core_exc_$signal$next[0:0]$2044 $3\core_core_traptype$next[7:0]$2057 $3\core_core_input_carry$next[1:0]$2046 $3\core_core_oe_ok$next[0:0]$2053 $3\core_core_oe$next[0:0]$2052 $3\core_core_rc_ok$next[0:0]$2055 $3\core_core_rc$next[0:0]$2054 $3\core_core_lk$next[0:0]$2050 $3\core_core_fn_unit$next[11:0]$2045 $3\core_core_insn_type$next[6:0]$2048 $3\core_core_insn$next[31:0]$2047 $3\core_core_cia$next[63:0]$2032 $3\core_core_msr$next[63:0]$2051 $3\core_cr_out_ok$next[0:0]$2065 $3\core_cr_out$next[2:0]$2064 $3\core_cr_in2_ok$49$next[0:0]$2062 $3\core_cr_in2$48$next[2:0]$2060 $3\core_cr_in2_ok$next[0:0]$2063 $3\core_cr_in2$next[2:0]$2061 $3\core_cr_in1_ok$next[0:0]$2059 $3\core_cr_in1$next[2:0]$2058 $3\core_fasto2_ok$next[0:0]$2075 $3\core_fasto2$next[2:0]$2074 $3\core_fasto1_ok$next[0:0]$2073 $3\core_fasto1$next[2:0]$2072 $3\core_fast2_ok$next[0:0]$2071 $3\core_fast2$next[2:0]$2070 $3\core_fast1_ok$next[0:0]$2069 $3\core_fast1$next[2:0]$2068 $3\core_xer_out$next[0:0]$2089 $3\core_xer_in$next[2:0]$2088 $3\core_spr1_ok$next[0:0]$2085 $3\core_spr1$next[9:0]$2084 $3\core_spro_ok$next[0:0]$2087 $3\core_spro$next[9:0]$2086 $3\core_reg3_ok$next[0:0]$2081 $3\core_reg3$next[4:0]$2080 $3\core_reg2_ok$next[0:0]$2079 $3\core_reg2$next[4:0]$2078 $3\core_reg1_ok$next[0:0]$2077 $3\core_reg1$next[4:0]$2076 $3\core_ea_ok$next[0:0]$2067 $3\core_ea$next[4:0]$2066 $3\core_rego_ok$next[0:0]$2083 $3\core_rego$next[4:0]$2082 $3\core_asmcode$next[7:0]$2031 } 330'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - case - assign $3\core_asmcode$next[7:0]$2031 \core_asmcode - assign $3\core_core_cia$next[63:0]$2032 \core_core_cia - assign $3\core_core_cr_rd$next[7:0]$2033 \core_core_cr_rd - assign $3\core_core_cr_rd_ok$next[0:0]$2034 \core_core_cr_rd_ok - assign $3\core_core_cr_wr$next[7:0]$2035 \core_core_cr_wr - assign $3\core_core_cr_wr_ok$next[0:0]$2036 \core_core_cr_wr_ok - assign $3\core_core_exc_$signal$50$next[0:0]$2037 \core_core_exc_$signal$50 - assign $3\core_core_exc_$signal$51$next[0:0]$2038 \core_core_exc_$signal$51 - assign $3\core_core_exc_$signal$52$next[0:0]$2039 \core_core_exc_$signal$52 - assign $3\core_core_exc_$signal$53$next[0:0]$2040 \core_core_exc_$signal$53 - assign $3\core_core_exc_$signal$54$next[0:0]$2041 \core_core_exc_$signal$54 - assign $3\core_core_exc_$signal$55$next[0:0]$2042 \core_core_exc_$signal$55 - assign $3\core_core_exc_$signal$56$next[0:0]$2043 \core_core_exc_$signal$56 - assign $3\core_core_exc_$signal$next[0:0]$2044 \core_core_exc_$signal - assign $3\core_core_fn_unit$next[11:0]$2045 \core_core_fn_unit - assign $3\core_core_input_carry$next[1:0]$2046 \core_core_input_carry - assign $3\core_core_insn$next[31:0]$2047 \core_core_insn - assign $3\core_core_insn_type$next[6:0]$2048 \core_core_insn_type - assign $3\core_core_is_32bit$next[0:0]$2049 \core_core_is_32bit - assign $3\core_core_lk$next[0:0]$2050 \core_core_lk - assign $3\core_core_msr$next[63:0]$2051 \core_core_msr - assign $3\core_core_oe$next[0:0]$2052 \core_core_oe - assign $3\core_core_oe_ok$next[0:0]$2053 \core_core_oe_ok - assign $3\core_core_rc$next[0:0]$2054 \core_core_rc - assign $3\core_core_rc_ok$next[0:0]$2055 \core_core_rc_ok - assign $3\core_core_trapaddr$next[12:0]$2056 \core_core_trapaddr - assign $3\core_core_traptype$next[7:0]$2057 \core_core_traptype - assign $3\core_cr_in1$next[2:0]$2058 \core_cr_in1 - assign $3\core_cr_in1_ok$next[0:0]$2059 \core_cr_in1_ok - assign $3\core_cr_in2$48$next[2:0]$2060 \core_cr_in2$48 - assign $3\core_cr_in2$next[2:0]$2061 \core_cr_in2 - assign $3\core_cr_in2_ok$49$next[0:0]$2062 \core_cr_in2_ok$49 - assign $3\core_cr_in2_ok$next[0:0]$2063 \core_cr_in2_ok - assign $3\core_cr_out$next[2:0]$2064 \core_cr_out - assign $3\core_cr_out_ok$next[0:0]$2065 \core_cr_out_ok - assign $3\core_ea$next[4:0]$2066 \core_ea - assign $3\core_ea_ok$next[0:0]$2067 \core_ea_ok - assign $3\core_fast1$next[2:0]$2068 \core_fast1 - assign $3\core_fast1_ok$next[0:0]$2069 \core_fast1_ok - assign $3\core_fast2$next[2:0]$2070 \core_fast2 - assign $3\core_fast2_ok$next[0:0]$2071 \core_fast2_ok - assign $3\core_fasto1$next[2:0]$2072 \core_fasto1 - assign $3\core_fasto1_ok$next[0:0]$2073 \core_fasto1_ok - assign $3\core_fasto2$next[2:0]$2074 \core_fasto2 - assign $3\core_fasto2_ok$next[0:0]$2075 \core_fasto2_ok - assign $3\core_reg1$next[4:0]$2076 \core_reg1 - assign $3\core_reg1_ok$next[0:0]$2077 \core_reg1_ok - assign $3\core_reg2$next[4:0]$2078 \core_reg2 - assign $3\core_reg2_ok$next[0:0]$2079 \core_reg2_ok - assign $3\core_reg3$next[4:0]$2080 \core_reg3 - assign $3\core_reg3_ok$next[0:0]$2081 \core_reg3_ok - assign $3\core_rego$next[4:0]$2082 \core_rego - assign $3\core_rego_ok$next[0:0]$2083 \core_rego_ok - assign $3\core_spr1$next[9:0]$2084 \core_spr1 - assign $3\core_spr1_ok$next[0:0]$2085 \core_spr1_ok - assign $3\core_spro$next[9:0]$2086 \core_spro - assign $3\core_spro_ok$next[0:0]$2087 \core_spro_ok - assign $3\core_xer_in$next[2:0]$2088 \core_xer_in - assign $3\core_xer_out$next[0:0]$2089 \core_xer_out - end - case - assign $1\core_asmcode$next[7:0]$1913 \core_asmcode - assign $1\core_core_cia$next[63:0]$1914 \core_core_cia - assign $1\core_core_cr_rd$next[7:0]$1915 \core_core_cr_rd - assign $1\core_core_cr_rd_ok$next[0:0]$1916 \core_core_cr_rd_ok - assign $1\core_core_cr_wr$next[7:0]$1917 \core_core_cr_wr - assign $1\core_core_cr_wr_ok$next[0:0]$1918 \core_core_cr_wr_ok - assign $1\core_core_exc_$signal$50$next[0:0]$1919 \core_core_exc_$signal$50 - assign $1\core_core_exc_$signal$51$next[0:0]$1920 \core_core_exc_$signal$51 - assign $1\core_core_exc_$signal$52$next[0:0]$1921 \core_core_exc_$signal$52 - assign $1\core_core_exc_$signal$53$next[0:0]$1922 \core_core_exc_$signal$53 - assign $1\core_core_exc_$signal$54$next[0:0]$1923 \core_core_exc_$signal$54 - assign $1\core_core_exc_$signal$55$next[0:0]$1924 \core_core_exc_$signal$55 - assign $1\core_core_exc_$signal$56$next[0:0]$1925 \core_core_exc_$signal$56 - assign $1\core_core_exc_$signal$next[0:0]$1926 \core_core_exc_$signal - assign $1\core_core_fn_unit$next[11:0]$1927 \core_core_fn_unit - assign $1\core_core_input_carry$next[1:0]$1928 \core_core_input_carry - assign $1\core_core_insn$next[31:0]$1929 \core_core_insn - assign $1\core_core_insn_type$next[6:0]$1930 \core_core_insn_type - assign $1\core_core_is_32bit$next[0:0]$1931 \core_core_is_32bit - assign $1\core_core_lk$next[0:0]$1932 \core_core_lk - assign $1\core_core_msr$next[63:0]$1933 \core_core_msr - assign $1\core_core_oe$next[0:0]$1934 \core_core_oe - assign $1\core_core_oe_ok$next[0:0]$1935 \core_core_oe_ok - assign $1\core_core_rc$next[0:0]$1936 \core_core_rc - assign $1\core_core_rc_ok$next[0:0]$1937 \core_core_rc_ok - assign $1\core_core_trapaddr$next[12:0]$1938 \core_core_trapaddr - assign $1\core_core_traptype$next[7:0]$1939 \core_core_traptype - assign $1\core_cr_in1$next[2:0]$1940 \core_cr_in1 - assign $1\core_cr_in1_ok$next[0:0]$1941 \core_cr_in1_ok - assign $1\core_cr_in2$48$next[2:0]$1942 \core_cr_in2$48 - assign $1\core_cr_in2$next[2:0]$1943 \core_cr_in2 - assign $1\core_cr_in2_ok$49$next[0:0]$1944 \core_cr_in2_ok$49 - assign $1\core_cr_in2_ok$next[0:0]$1945 \core_cr_in2_ok - assign $1\core_cr_out$next[2:0]$1946 \core_cr_out - assign $1\core_cr_out_ok$next[0:0]$1947 \core_cr_out_ok - assign $1\core_ea$next[4:0]$1948 \core_ea - assign $1\core_ea_ok$next[0:0]$1949 \core_ea_ok - assign $1\core_fast1$next[2:0]$1950 \core_fast1 - assign $1\core_fast1_ok$next[0:0]$1951 \core_fast1_ok - assign $1\core_fast2$next[2:0]$1952 \core_fast2 - assign $1\core_fast2_ok$next[0:0]$1953 \core_fast2_ok - assign $1\core_fasto1$next[2:0]$1954 \core_fasto1 - assign $1\core_fasto1_ok$next[0:0]$1955 \core_fasto1_ok - assign $1\core_fasto2$next[2:0]$1956 \core_fasto2 - assign $1\core_fasto2_ok$next[0:0]$1957 \core_fasto2_ok - assign $1\core_reg1$next[4:0]$1958 \core_reg1 - assign $1\core_reg1_ok$next[0:0]$1959 \core_reg1_ok - assign $1\core_reg2$next[4:0]$1960 \core_reg2 - assign $1\core_reg2_ok$next[0:0]$1961 \core_reg2_ok - assign $1\core_reg3$next[4:0]$1962 \core_reg3 - assign $1\core_reg3_ok$next[0:0]$1963 \core_reg3_ok - assign $1\core_rego$next[4:0]$1964 \core_rego - assign $1\core_rego_ok$next[0:0]$1965 \core_rego_ok - assign $1\core_spr1$next[9:0]$1966 \core_spr1 - assign $1\core_spr1_ok$next[0:0]$1967 \core_spr1_ok - assign $1\core_spro$next[9:0]$1968 \core_spro - assign $1\core_spro_ok$next[0:0]$1969 \core_spro_ok - assign $1\core_xer_in$next[2:0]$1970 \core_xer_in - assign $1\core_xer_out$next[0:0]$1971 \core_xer_out - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $4\core_rego_ok$next[0:0]$2114 1'0 - assign $4\core_ea_ok$next[0:0]$2106 1'0 - assign $4\core_reg1_ok$next[0:0]$2111 1'0 - assign $4\core_reg2_ok$next[0:0]$2112 1'0 - assign $4\core_reg3_ok$next[0:0]$2113 1'0 - assign $4\core_spro_ok$next[0:0]$2116 1'0 - assign $4\core_spr1_ok$next[0:0]$2115 1'0 - assign $4\core_fast1_ok$next[0:0]$2107 1'0 - assign $4\core_fast2_ok$next[0:0]$2108 1'0 - assign $4\core_fasto1_ok$next[0:0]$2109 1'0 - assign $4\core_fasto2_ok$next[0:0]$2110 1'0 - assign $4\core_cr_in1_ok$next[0:0]$2102 1'0 - assign $4\core_cr_in2_ok$next[0:0]$2104 1'0 - assign $4\core_cr_in2_ok$49$next[0:0]$2103 1'0 - assign $4\core_cr_out_ok$next[0:0]$2105 1'0 - assign $4\core_core_rc_ok$next[0:0]$2101 1'0 - assign $4\core_core_oe_ok$next[0:0]$2100 1'0 - assign $4\core_core_exc_$signal$next[0:0]$2099 1'0 - assign $4\core_core_exc_$signal$50$next[0:0]$2092 1'0 - assign $4\core_core_exc_$signal$51$next[0:0]$2093 1'0 - assign $4\core_core_exc_$signal$52$next[0:0]$2094 1'0 - assign $4\core_core_exc_$signal$53$next[0:0]$2095 1'0 - assign $4\core_core_exc_$signal$54$next[0:0]$2096 1'0 - assign $4\core_core_exc_$signal$55$next[0:0]$2097 1'0 - assign $4\core_core_exc_$signal$56$next[0:0]$2098 1'0 - assign $4\core_core_cr_rd_ok$next[0:0]$2090 1'0 - assign $4\core_core_cr_wr_ok$next[0:0]$2091 1'0 - case - assign $4\core_core_cr_rd_ok$next[0:0]$2090 $1\core_core_cr_rd_ok$next[0:0]$1916 - assign $4\core_core_cr_wr_ok$next[0:0]$2091 $1\core_core_cr_wr_ok$next[0:0]$1918 - assign $4\core_core_exc_$signal$50$next[0:0]$2092 $1\core_core_exc_$signal$50$next[0:0]$1919 - assign $4\core_core_exc_$signal$51$next[0:0]$2093 $1\core_core_exc_$signal$51$next[0:0]$1920 - assign $4\core_core_exc_$signal$52$next[0:0]$2094 $1\core_core_exc_$signal$52$next[0:0]$1921 - assign $4\core_core_exc_$signal$53$next[0:0]$2095 $1\core_core_exc_$signal$53$next[0:0]$1922 - assign $4\core_core_exc_$signal$54$next[0:0]$2096 $1\core_core_exc_$signal$54$next[0:0]$1923 - assign $4\core_core_exc_$signal$55$next[0:0]$2097 $1\core_core_exc_$signal$55$next[0:0]$1924 - assign $4\core_core_exc_$signal$56$next[0:0]$2098 $1\core_core_exc_$signal$56$next[0:0]$1925 - assign $4\core_core_exc_$signal$next[0:0]$2099 $1\core_core_exc_$signal$next[0:0]$1926 - assign $4\core_core_oe_ok$next[0:0]$2100 $1\core_core_oe_ok$next[0:0]$1935 - assign $4\core_core_rc_ok$next[0:0]$2101 $1\core_core_rc_ok$next[0:0]$1937 - assign $4\core_cr_in1_ok$next[0:0]$2102 $1\core_cr_in1_ok$next[0:0]$1941 - assign $4\core_cr_in2_ok$49$next[0:0]$2103 $1\core_cr_in2_ok$49$next[0:0]$1944 - assign $4\core_cr_in2_ok$next[0:0]$2104 $1\core_cr_in2_ok$next[0:0]$1945 - assign $4\core_cr_out_ok$next[0:0]$2105 $1\core_cr_out_ok$next[0:0]$1947 - assign $4\core_ea_ok$next[0:0]$2106 $1\core_ea_ok$next[0:0]$1949 - assign $4\core_fast1_ok$next[0:0]$2107 $1\core_fast1_ok$next[0:0]$1951 - assign $4\core_fast2_ok$next[0:0]$2108 $1\core_fast2_ok$next[0:0]$1953 - assign $4\core_fasto1_ok$next[0:0]$2109 $1\core_fasto1_ok$next[0:0]$1955 - assign $4\core_fasto2_ok$next[0:0]$2110 $1\core_fasto2_ok$next[0:0]$1957 - assign $4\core_reg1_ok$next[0:0]$2111 $1\core_reg1_ok$next[0:0]$1959 - assign $4\core_reg2_ok$next[0:0]$2112 $1\core_reg2_ok$next[0:0]$1961 - assign $4\core_reg3_ok$next[0:0]$2113 $1\core_reg3_ok$next[0:0]$1963 - assign $4\core_rego_ok$next[0:0]$2114 $1\core_rego_ok$next[0:0]$1965 - assign $4\core_spr1_ok$next[0:0]$2115 $1\core_spr1_ok$next[0:0]$1967 - assign $4\core_spro_ok$next[0:0]$2116 $1\core_spro_ok$next[0:0]$1969 - end - sync always - update \core_asmcode$next $0\core_asmcode$next[7:0]$1854 - update \core_core_cia$next $0\core_core_cia$next[63:0]$1855 - update \core_core_cr_rd$next $0\core_core_cr_rd$next[7:0]$1856 - update \core_core_cr_rd_ok$next $0\core_core_cr_rd_ok$next[0:0]$1857 - update \core_core_cr_wr$next $0\core_core_cr_wr$next[7:0]$1858 - update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$1859 - update \core_core_exc_$signal$50$next $0\core_core_exc_$signal$50$next[0:0]$1860 - update \core_core_exc_$signal$51$next $0\core_core_exc_$signal$51$next[0:0]$1861 - update \core_core_exc_$signal$52$next $0\core_core_exc_$signal$52$next[0:0]$1862 - update \core_core_exc_$signal$53$next $0\core_core_exc_$signal$53$next[0:0]$1863 - update \core_core_exc_$signal$54$next $0\core_core_exc_$signal$54$next[0:0]$1864 - update \core_core_exc_$signal$55$next $0\core_core_exc_$signal$55$next[0:0]$1865 - update \core_core_exc_$signal$56$next $0\core_core_exc_$signal$56$next[0:0]$1866 - update \core_core_exc_$signal$next $0\core_core_exc_$signal$next[0:0]$1867 - update \core_core_fn_unit$next $0\core_core_fn_unit$next[11:0]$1868 - update \core_core_input_carry$next $0\core_core_input_carry$next[1:0]$1869 - update \core_core_insn$next $0\core_core_insn$next[31:0]$1870 - update \core_core_insn_type$next $0\core_core_insn_type$next[6:0]$1871 - update \core_core_is_32bit$next $0\core_core_is_32bit$next[0:0]$1872 - update \core_core_lk$next $0\core_core_lk$next[0:0]$1873 - update \core_core_msr$next $0\core_core_msr$next[63:0]$1874 - update \core_core_oe$next $0\core_core_oe$next[0:0]$1875 - update \core_core_oe_ok$next $0\core_core_oe_ok$next[0:0]$1876 - update \core_core_rc$next $0\core_core_rc$next[0:0]$1877 - update \core_core_rc_ok$next $0\core_core_rc_ok$next[0:0]$1878 - update \core_core_trapaddr$next $0\core_core_trapaddr$next[12:0]$1879 - update \core_core_traptype$next $0\core_core_traptype$next[7:0]$1880 - update \core_cr_in1$next $0\core_cr_in1$next[2:0]$1881 - update \core_cr_in1_ok$next $0\core_cr_in1_ok$next[0:0]$1882 - update \core_cr_in2$48$next $0\core_cr_in2$48$next[2:0]$1883 - update \core_cr_in2$next $0\core_cr_in2$next[2:0]$1884 - update \core_cr_in2_ok$49$next $0\core_cr_in2_ok$49$next[0:0]$1885 - update \core_cr_in2_ok$next $0\core_cr_in2_ok$next[0:0]$1886 - update \core_cr_out$next $0\core_cr_out$next[2:0]$1887 - update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$1888 - update \core_ea$next $0\core_ea$next[4:0]$1889 - update \core_ea_ok$next $0\core_ea_ok$next[0:0]$1890 - update \core_fast1$next $0\core_fast1$next[2:0]$1891 - update \core_fast1_ok$next $0\core_fast1_ok$next[0:0]$1892 - update \core_fast2$next $0\core_fast2$next[2:0]$1893 - update \core_fast2_ok$next $0\core_fast2_ok$next[0:0]$1894 - update \core_fasto1$next $0\core_fasto1$next[2:0]$1895 - update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$1896 - update \core_fasto2$next $0\core_fasto2$next[2:0]$1897 - update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$1898 - update \core_reg1$next $0\core_reg1$next[4:0]$1899 - update \core_reg1_ok$next $0\core_reg1_ok$next[0:0]$1900 - update \core_reg2$next $0\core_reg2$next[4:0]$1901 - update \core_reg2_ok$next $0\core_reg2_ok$next[0:0]$1902 - update \core_reg3$next $0\core_reg3$next[4:0]$1903 - update \core_reg3_ok$next $0\core_reg3_ok$next[0:0]$1904 - update \core_rego$next $0\core_rego$next[4:0]$1905 - update \core_rego_ok$next $0\core_rego_ok$next[0:0]$1906 - update \core_spr1$next $0\core_spr1$next[9:0]$1907 - update \core_spr1_ok$next $0\core_spr1_ok$next[0:0]$1908 - update \core_spro$next $0\core_spro$next[9:0]$1909 - update \core_spro_ok$next $0\core_spro_ok$next[0:0]$1910 - update \core_xer_in$next $0\core_xer_in$next[2:0]$1911 - update \core_xer_out$next $0\core_xer_out$next[0:0]$1912 - end - attribute \src "libresoc.v:52168.3-52176.6" - process $proc$libresoc.v:52168$2117 - assign { } { } - assign { } { } - assign $0\jtag_dmi0__ack_o$next[0:0]$2118 $1\jtag_dmi0__ack_o$next[0:0]$2119 - attribute \src "libresoc.v:52169.5-52169.29" - switch \initial - attribute \src "libresoc.v:52169.9-52169.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\jtag_dmi0__ack_o$next[0:0]$2119 1'0 - case - assign $1\jtag_dmi0__ack_o$next[0:0]$2119 \dbg_dmi_ack_o - end + assign $1\ren_delay[2:0] 3'000 sync always - update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$2118 + sync init + update \ren_delay $1\ren_delay[2:0] end - attribute \src "libresoc.v:52177.3-52185.6" - process $proc$libresoc.v:52177$2120 - assign { } { } + attribute \src "libresoc.v:188745.13-188745.34" + process $proc$libresoc.v:188745$14285 assign { } { } - assign $0\jtag_dmi0__dout$next[63:0]$2121 $1\jtag_dmi0__dout$next[63:0]$2122 - attribute \src "libresoc.v:52178.5-52178.29" - switch \initial - attribute \src "libresoc.v:52178.9-52178.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\jtag_dmi0__dout$next[63:0]$2122 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $1\jtag_dmi0__dout$next[63:0]$2122 \dbg_dmi_dout - end + assign $0\ren_delay$11[2:0]$14286 3'000 sync always - update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$2121 + sync init + update \ren_delay$11 $0\ren_delay$11[2:0]$14286 end - attribute \src "libresoc.v:52186.3-52194.6" - process $proc$libresoc.v:52186$2123 + attribute \src "libresoc.v:188749.13-188749.34" + process $proc$libresoc.v:188749$14287 assign { } { } - assign { } { } - assign $0\dec2_cur_eint$next[0:0]$2124 $1\dec2_cur_eint$next[0:0]$2125 - attribute \src "libresoc.v:52187.5-52187.29" - switch \initial - attribute \src "libresoc.v:52187.9-52187.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dec2_cur_eint$next[0:0]$2125 1'0 - case - assign $1\dec2_cur_eint$next[0:0]$2125 \xics_icp_core_irq_o - end + assign $0\ren_delay$18[2:0]$14288 3'000 sync always - update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$2124 + sync init + update \ren_delay$18 $0\ren_delay$18[2:0]$14288 end - attribute \src "libresoc.v:52195.3-52204.6" - process $proc$libresoc.v:52195$2126 - assign { } { } + attribute \src "libresoc.v:188784.3-188785.43" + process $proc$libresoc.v:188784$14266 assign { } { } - assign $0\delay$next[1:0]$2127 $1\delay$next[1:0]$2128 - attribute \src "libresoc.v:52196.5-52196.29" - switch \initial - attribute \src "libresoc.v:52196.9-52196.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:174" - switch \$10 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\delay$next[1:0]$2128 \$12 [1:0] - case - assign $1\delay$next[1:0]$2128 \delay - end - sync always - update \delay$next $0\delay$next[1:0]$2127 + assign $0\ren_delay$18[2:0]$14267 \ren_delay$18$next + sync posedge \coresync_clk + update \ren_delay$18 $0\ren_delay$18[2:0]$14267 end - attribute \src "libresoc.v:52205.3-52241.6" - process $proc$libresoc.v:52205$2129 - assign { } { } - assign { } { } + attribute \src "libresoc.v:188786.3-188787.43" + process $proc$libresoc.v:188786$14268 assign { } { } - assign $0\raw_insn_i$next[31:0]$2130 $4\raw_insn_i$next[31:0]$2134 - attribute \src "libresoc.v:52206.5-52206.29" - switch \initial - attribute \src "libresoc.v:52206.9-52206.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\raw_insn_i$next[31:0]$2131 0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\raw_insn_i$next[31:0]$2131 $2\raw_insn_i$next[31:0]$2132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\raw_insn_i$next[31:0]$2132 \raw_insn_i - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\raw_insn_i$next[31:0]$2132 \dec2_raw_opcode_in - end - attribute \src "libresoc.v:0.0-0.0" - case 2'11 - assign { } { } - assign $1\raw_insn_i$next[31:0]$2131 $3\raw_insn_i$next[31:0]$2133 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" - switch \$59 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\raw_insn_i$next[31:0]$2133 0 - case - assign $3\raw_insn_i$next[31:0]$2133 \raw_insn_i - end - case - assign $1\raw_insn_i$next[31:0]$2131 \raw_insn_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\raw_insn_i$next[31:0]$2134 0 - case - assign $4\raw_insn_i$next[31:0]$2134 $1\raw_insn_i$next[31:0]$2131 - end - sync always - update \raw_insn_i$next $0\raw_insn_i$next[31:0]$2130 + assign $0\ren_delay$11[2:0]$14269 \ren_delay$11$next + sync posedge \coresync_clk + update \ren_delay$11 $0\ren_delay$11[2:0]$14269 end - attribute \src "libresoc.v:52242.3-52278.6" - process $proc$libresoc.v:52242$2135 + attribute \src "libresoc.v:188788.3-188789.35" + process $proc$libresoc.v:188788$14270 assign { } { } + assign $0\ren_delay[2:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[2:0] + end + attribute \src "libresoc.v:188850.3-188858.6" + process $proc$libresoc.v:188850$14271 assign { } { } assign { } { } - assign $0\bigendian_i$next[0:0]$2136 $4\bigendian_i$next[0:0]$2140 - attribute \src "libresoc.v:52243.5-52243.29" + assign $0\ren_delay$18$next[2:0]$14272 $1\ren_delay$18$next[2:0]$14273 + attribute \src "libresoc.v:188851.5-188851.29" switch \initial - attribute \src "libresoc.v:52243.9-52243.17" + attribute \src "libresoc.v:188851.9-188851.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\bigendian_i$next[0:0]$2137 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\bigendian_i$next[0:0]$2137 $2\bigendian_i$next[0:0]$2138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\bigendian_i$next[0:0]$2138 \bigendian_i - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\bigendian_i$next[0:0]$2138 \core_bigendian_i - end - attribute \src "libresoc.v:0.0-0.0" - case 2'11 - assign { } { } - assign $1\bigendian_i$next[0:0]$2137 $3\bigendian_i$next[0:0]$2139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" - switch \$61 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\bigendian_i$next[0:0]$2139 1'0 - case - assign $3\bigendian_i$next[0:0]$2139 \bigendian_i - end - case - assign $1\bigendian_i$next[0:0]$2137 \bigendian_i - end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\bigendian_i$next[0:0]$2140 1'0 - case - assign $4\bigendian_i$next[0:0]$2140 $1\bigendian_i$next[0:0]$2137 - end - sync always - update \bigendian_i$next $0\bigendian_i$next[0:0]$2136 - end - attribute \src "libresoc.v:52279.3-52294.6" - process $proc$libresoc.v:52279$2141 - assign { } { } - assign { } { } - assign $0\imem_a_pc_i[47:0] $1\imem_a_pc_i[47:0] - attribute \src "libresoc.v:52280.5-52280.29" - switch \initial - attribute \src "libresoc.v:52280.9-52280.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\imem_a_pc_i[47:0] $2\imem_a_pc_i[47:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - switch \$67 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\imem_a_pc_i[47:0] \pc [47:0] - case - assign $2\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 - end + assign $1\ren_delay$18$next[2:0]$14273 3'000 case - assign $1\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 + assign $1\ren_delay$18$next[2:0]$14273 \src3__ren end sync always - update \imem_a_pc_i $0\imem_a_pc_i[47:0] + update \ren_delay$18$next $0\ren_delay$18$next[2:0]$14272 end - attribute \src "libresoc.v:52295.3-52319.6" - process $proc$libresoc.v:52295$2142 + attribute \src "libresoc.v:188859.3-188868.6" + process $proc$libresoc.v:188859$14274 assign { } { } assign { } { } - assign $0\imem_a_valid_i[0:0] $1\imem_a_valid_i[0:0] - attribute \src "libresoc.v:52296.5-52296.29" + assign $0\src3__data_o[1:0] $1\src3__data_o[1:0] + attribute \src "libresoc.v:188860.5-188860.29" switch \initial - attribute \src "libresoc.v:52296.9-52296.17" + attribute \src "libresoc.v:188860.9-188860.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\imem_a_valid_i[0:0] $2\imem_a_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - switch \$73 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\imem_a_valid_i[0:0] 1'1 - case - assign $2\imem_a_valid_i[0:0] 1'0 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$19 attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\imem_a_valid_i[0:0] $3\imem_a_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\imem_a_valid_i[0:0] 1'1 - case - assign $3\imem_a_valid_i[0:0] 1'0 - end - case - assign $1\imem_a_valid_i[0:0] 1'0 - end - sync always - update \imem_a_valid_i $0\imem_a_valid_i[0:0] - end - attribute \src "libresoc.v:52320.3-52344.6" - process $proc$libresoc.v:52320$2143 - assign { } { } - assign { } { } - assign $0\imem_f_valid_i[0:0] $1\imem_f_valid_i[0:0] - attribute \src "libresoc.v:52321.5-52321.29" - switch \initial - attribute \src "libresoc.v:52321.9-52321.17" case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 assign { } { } - assign $1\imem_f_valid_i[0:0] $2\imem_f_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - switch \$79 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\imem_f_valid_i[0:0] 1'1 - case - assign $2\imem_f_valid_i[0:0] 1'0 - end - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\imem_f_valid_i[0:0] $3\imem_f_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\imem_f_valid_i[0:0] 1'1 - case - assign $3\imem_f_valid_i[0:0] 1'0 - end + assign $1\src3__data_o[1:0] \$23 case - assign $1\imem_f_valid_i[0:0] 1'0 + assign $1\src3__data_o[1:0] 2'00 end sync always - update \imem_f_valid_i $0\imem_f_valid_i[0:0] + update \src3__data_o $0\src3__data_o[1:0] end - attribute \src "libresoc.v:52345.3-52365.6" - process $proc$libresoc.v:52345$2144 + attribute \src "libresoc.v:188869.3-188877.6" + process $proc$libresoc.v:188869$14275 assign { } { } assign { } { } - assign { } { } - assign $0\dec2_cur_pc$next[63:0]$2145 $3\dec2_cur_pc$next[63:0]$2148 - attribute \src "libresoc.v:52346.5-52346.29" + assign $0\ren_delay$next[2:0]$14276 $1\ren_delay$next[2:0]$14277 + attribute \src "libresoc.v:188870.5-188870.29" switch \initial - attribute \src "libresoc.v:52346.9-52346.17" + attribute \src "libresoc.v:188870.9-188870.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec2_cur_pc$next[63:0]$2146 $2\dec2_cur_pc$next[63:0]$2147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - switch \$85 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dec2_cur_pc$next[63:0]$2147 \pc - case - assign $2\dec2_cur_pc$next[63:0]$2147 \dec2_cur_pc - end - case - assign $1\dec2_cur_pc$next[63:0]$2146 \dec2_cur_pc - end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dec2_cur_pc$next[63:0]$2148 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\ren_delay$next[2:0]$14277 3'000 case - assign $3\dec2_cur_pc$next[63:0]$2148 $1\dec2_cur_pc$next[63:0]$2146 + assign $1\ren_delay$next[2:0]$14277 \src1__ren end sync always - update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$2145 + update \ren_delay$next $0\ren_delay$next[2:0]$14276 end - attribute \src "libresoc.v:52366.3-52395.6" - process $proc$libresoc.v:52366$2149 - assign { } { } + attribute \src "libresoc.v:188878.3-188887.6" + process $proc$libresoc.v:188878$14278 assign { } { } assign { } { } - assign $0\msr_read$next[0:0]$2150 $4\msr_read$next[0:0]$2154 - attribute \src "libresoc.v:52367.5-52367.29" + assign $0\src1__data_o[1:0] $1\src1__data_o[1:0] + attribute \src "libresoc.v:188879.5-188879.29" switch \initial - attribute \src "libresoc.v:52367.9-52367.17" + attribute \src "libresoc.v:188879.9-188879.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\msr_read$next[0:0]$2151 $2\msr_read$next[0:0]$2152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - switch \$91 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\msr_read$next[0:0]$2152 1'0 - case - assign $2\msr_read$next[0:0]$2152 \msr_read - end - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\msr_read$next[0:0]$2151 $3\msr_read$next[0:0]$2153 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275" - switch \$93 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\msr_read$next[0:0]$2153 1'1 - case - assign $3\msr_read$next[0:0]$2153 \msr_read - end - case - assign $1\msr_read$next[0:0]$2151 \msr_read - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\msr_read$next[0:0]$2154 1'1 + assign $1\src1__data_o[1:0] \$9 case - assign $4\msr_read$next[0:0]$2154 $1\msr_read$next[0:0]$2151 + assign $1\src1__data_o[1:0] 2'00 end sync always - update \msr_read$next $0\msr_read$next[0:0]$2150 + update \src1__data_o $0\src1__data_o[1:0] end - attribute \src "libresoc.v:52396.3-52441.6" - process $proc$libresoc.v:52396$2155 + attribute \src "libresoc.v:188888.3-188896.6" + process $proc$libresoc.v:188888$14279 assign { } { } assign { } { } - assign { } { } - assign $0\fsm_state$next[1:0]$2156 $5\fsm_state$next[1:0]$2161 - attribute \src "libresoc.v:52397.5-52397.29" + assign $0\ren_delay$11$next[2:0]$14280 $1\ren_delay$11$next[2:0]$14281 + attribute \src "libresoc.v:188889.5-188889.29" switch \initial - attribute \src "libresoc.v:52397.9-52397.17" + attribute \src "libresoc.v:188889.9-188889.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\fsm_state$next[1:0]$2157 $2\fsm_state$next[1:0]$2158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - switch \$99 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fsm_state$next[1:0]$2158 2'01 - case - assign $2\fsm_state$next[1:0]$2158 \fsm_state - end - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\fsm_state$next[1:0]$2157 $3\fsm_state$next[1:0]$2159 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $3\fsm_state$next[1:0]$2159 \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $3\fsm_state$next[1:0]$2159 2'10 - end - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\fsm_state$next[1:0]$2157 2'11 - attribute \src "libresoc.v:0.0-0.0" - case 2'11 - assign { } { } - assign $1\fsm_state$next[1:0]$2157 $4\fsm_state$next[1:0]$2160 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" - switch \$101 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\fsm_state$next[1:0]$2160 2'00 - case - assign $4\fsm_state$next[1:0]$2160 \fsm_state - end - case - assign $1\fsm_state$next[1:0]$2157 \fsm_state - end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fsm_state$next[1:0]$2161 2'00 - case - assign $5\fsm_state$next[1:0]$2161 $1\fsm_state$next[1:0]$2157 - end - sync always - update \fsm_state$next $0\fsm_state$next[1:0]$2156 - end - attribute \src "libresoc.v:52442.3-52460.6" - process $proc$libresoc.v:52442$2162 - assign { } { } - assign { } { } - assign $0\core_stopped_i[0:0] $1\core_stopped_i[0:0] - attribute \src "libresoc.v:52443.5-52443.29" - switch \initial - attribute \src "libresoc.v:52443.9-52443.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\core_stopped_i[0:0] $2\core_stopped_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - switch \$107 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\core_stopped_i[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\core_stopped_i[0:0] 1'1 - end + assign $1\ren_delay$11$next[2:0]$14281 3'000 case - assign $1\core_stopped_i[0:0] 1'0 + assign $1\ren_delay$11$next[2:0]$14281 \src2__ren end sync always - update \core_stopped_i $0\core_stopped_i[0:0] + update \ren_delay$11$next $0\ren_delay$11$next[2:0]$14280 end - attribute \src "libresoc.v:52461.3-52479.6" - process $proc$libresoc.v:52461$2163 + attribute \src "libresoc.v:188897.3-188906.6" + process $proc$libresoc.v:188897$14282 assign { } { } assign { } { } - assign $0\dbg_core_stopped_i[0:0] $1\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:52462.5-52462.29" + assign $0\src2__data_o[1:0] $1\src2__data_o[1:0] + attribute \src "libresoc.v:188898.5-188898.29" switch \initial - attribute \src "libresoc.v:52462.9-52462.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dbg_core_stopped_i[0:0] $2\dbg_core_stopped_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" - switch \$113 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\dbg_core_stopped_i[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\dbg_core_stopped_i[0:0] 1'1 - end - case - assign $1\dbg_core_stopped_i[0:0] 1'0 - end - sync always - update \dbg_core_stopped_i $0\dbg_core_stopped_i[0:0] - end - connect \$99 $and$libresoc.v:50790$1606_Y - connect \$101 $not$libresoc.v:50791$1607_Y - connect \$103 $not$libresoc.v:50792$1608_Y - connect \$105 $not$libresoc.v:50793$1609_Y - connect \$107 $and$libresoc.v:50794$1610_Y - connect \$10 $ne$libresoc.v:50795$1611_Y - connect \$109 $not$libresoc.v:50796$1612_Y - connect \$111 $not$libresoc.v:50797$1613_Y - connect \$113 $and$libresoc.v:50798$1614_Y - connect \$115 $not$libresoc.v:50799$1615_Y - connect \$118 $mul$libresoc.v:50800$1616_Y - connect \$117 $shr$libresoc.v:50801$1617_Y [31:0] - connect \$122 $mul$libresoc.v:50802$1618_Y - connect \$121 $shr$libresoc.v:50803$1619_Y [31:0] - connect \$125 $ne$libresoc.v:50804$1620_Y - connect \$127 $pos$libresoc.v:50805$1622_Y - connect \$129 $pos$libresoc.v:50806$1624_Y - connect \$133 $sub$libresoc.v:50807$1625_Y - connect \$137 $add$libresoc.v:50808$1626_Y - connect \$13 $sub$libresoc.v:50809$1627_Y - connect \$15 $or$libresoc.v:50810$1628_Y - connect \$17 $or$libresoc.v:50811$1629_Y - connect \$19 $ne$libresoc.v:50812$1630_Y - connect \$21 $not$libresoc.v:50813$1631_Y - connect \$23 $and$libresoc.v:50814$1632_Y - connect \$26 $add$libresoc.v:50815$1633_Y - connect \$28 $not$libresoc.v:50816$1634_Y - connect \$30 $not$libresoc.v:50817$1635_Y - connect \$32 $not$libresoc.v:50818$1636_Y - connect \$34 $not$libresoc.v:50819$1637_Y - connect \$36 $not$libresoc.v:50820$1638_Y - connect \$38 $not$libresoc.v:50821$1639_Y - connect \$40 $not$libresoc.v:50822$1640_Y - connect \$42 $and$libresoc.v:50823$1641_Y - connect \$45 $and$libresoc.v:50824$1642_Y - connect \$44 $reduce_or$libresoc.v:50825$1643_Y - connect \$57 $not$libresoc.v:50826$1644_Y - connect \$59 $not$libresoc.v:50827$1645_Y - connect \$61 $not$libresoc.v:50828$1646_Y - connect \$63 $not$libresoc.v:50829$1647_Y - connect \$65 $not$libresoc.v:50830$1648_Y - connect \$67 $and$libresoc.v:50831$1649_Y - connect \$69 $not$libresoc.v:50832$1650_Y - connect \$71 $not$libresoc.v:50833$1651_Y - connect \$73 $and$libresoc.v:50834$1652_Y - connect \$75 $not$libresoc.v:50835$1653_Y - connect \$77 $not$libresoc.v:50836$1654_Y - connect \$79 $and$libresoc.v:50837$1655_Y - connect \$81 $not$libresoc.v:50838$1656_Y - connect \$83 $not$libresoc.v:50839$1657_Y - connect \$85 $and$libresoc.v:50840$1658_Y - connect \$87 $not$libresoc.v:50841$1659_Y - connect \$89 $not$libresoc.v:50842$1660_Y - connect \$91 $and$libresoc.v:50843$1661_Y - connect \$93 $not$libresoc.v:50844$1662_Y - connect \$95 $not$libresoc.v:50845$1663_Y - connect \$97 $not$libresoc.v:50846$1664_Y - connect \$12 \$13 - connect \$25 \$26 - connect \$132 \$133 - connect \$136 \$137 - connect \corebusy_o 1'0 - connect \cu_st__rel_o 1'0 - connect \cu_ad__rel_o 1'0 - connect \cia__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \core_terminate_o 1'0 - connect \state_nia_wen 4'0000 - connect \msr__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \dmi__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \full_rd2__data_o 0 - connect \full_rd__data_o 6'000000 - connect \issue__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \dbg_core_dbg_msr \dec2_cur_msr - connect \dbg_core_dbg_pc \pc - connect \dbg_terminate_i 1'0 - connect \nia \$26 [63:0] - connect \pc_o \dec2_cur_pc - connect \cu_st__go_i \cu_st__rel_o_rise - connect \cu_ad__go_i 1'0 - connect \cu_st__rel_o_rise \$23 - connect \cu_st__rel_o_dly$next 1'0 - connect \dec2_bigendian \core_bigendian_i - connect \busy_o 1'0 - connect \core_coresync_rst \ti_rst - connect \ti_rst \$19 - connect \por_clk \clk - connect { \xics_icp_ics_i_pri \xics_icp_ics_i_src } { \xics_ics_icp_o_pri \xics_ics_icp_o_src } + attribute \src "libresoc.v:188898.9-188898.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src2__data_o[1:0] \$16 + case + assign $1\src2__data_o[1:0] 2'00 + end + sync always + update \src2__data_o $0\src2__data_o[1:0] + end + connect \$9 $or$libresoc.v:188775$14257_Y + connect \$12 $reduce_or$libresoc.v:188776$14258_Y + connect \$14 $or$libresoc.v:188777$14259_Y + connect \$16 $or$libresoc.v:188778$14260_Y + connect \$19 $reduce_or$libresoc.v:188779$14261_Y + connect \$21 $or$libresoc.v:188780$14262_Y + connect \$23 $or$libresoc.v:188781$14263_Y + connect \$5 $reduce_or$libresoc.v:188782$14264_Y + connect \$7 $or$libresoc.v:188783$14265_Y + connect \full_wr__data_i 6'000000 + connect \full_wr__wen 3'000 + connect { \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } 3'000 + connect { \reg_2_w2__data_i \reg_1_w1__data_i \reg_0_w0__data_i } 6'000000 + connect { \reg_2_r2__ren \reg_1_r1__ren \reg_0_r0__ren } \full_rd__ren + connect \full_rd__data_o { \reg_2_r2__data_o \reg_1_r1__data_o \reg_0_r0__data_o } + connect \reg_2_dest32__data_i \data_i$1 + connect \reg_1_dest31__data_i \data_i$1 + connect \reg_0_dest30__data_i \data_i$1 + connect { \reg_2_dest32__wen \reg_1_dest31__wen \reg_0_dest30__wen } \wen$2 + connect \reg_2_dest22__data_i \data_i + connect \reg_1_dest21__data_i \data_i + connect \reg_0_dest20__data_i \data_i + connect { \reg_2_dest22__wen \reg_1_dest21__wen \reg_0_dest20__wen } \wen + connect \reg_2_dest12__data_i \data_i$3 + connect \reg_1_dest11__data_i \data_i$3 + connect \reg_0_dest10__data_i \data_i$3 + connect { \reg_2_dest12__wen \reg_1_dest11__wen \reg_0_dest10__wen } \wen$4 + connect { \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren + connect { \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren + connect { \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren end -attribute \src "libresoc.v:52514.1-52828.10" +attribute \src "libresoc.v:188932.1-189246.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.xics_icp" attribute \generator "nMigen" module \xics_icp - attribute \src "libresoc.v:52692.3-52720.6" + attribute \src "libresoc.v:189110.3-189138.6" wire width 32 $0\be_out[31:0] - attribute \src "libresoc.v:52743.3-52751.6" - wire $0\core_irq_o$next[0:0]$2297 - attribute \src "libresoc.v:52634.3-52635.37" + attribute \src "libresoc.v:189161.3-189169.6" + wire $0\core_irq_o$next[0:0]$14324 + attribute \src "libresoc.v:189052.3-189053.37" wire $0\core_irq_o[0:0] - attribute \src "libresoc.v:52762.3-52824.6" - wire width 8 $0\cppr$10[7:0]$2301 - attribute \src "libresoc.v:52648.3-52663.6" - wire width 8 $0\cppr$next[7:0]$2280 - attribute \src "libresoc.v:52638.3-52639.25" + attribute \src "libresoc.v:189180.3-189242.6" + wire width 8 $0\cppr$10[7:0]$14328 + attribute \src "libresoc.v:189066.3-189081.6" + wire width 8 $0\cppr$next[7:0]$14307 + attribute \src "libresoc.v:189056.3-189057.25" wire width 8 $0\cppr[7:0] - attribute \src "libresoc.v:52752.3-52761.6" + attribute \src "libresoc.v:189170.3-189179.6" wire width 32 $0\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:52515.7-52515.20" + attribute \src "libresoc.v:188933.7-188933.20" wire $0\initial[0:0] - attribute \src "libresoc.v:52762.3-52824.6" - wire $0\irq$12[0:0]$2302 - attribute \src "libresoc.v:52648.3-52663.6" - wire $0\irq$next[0:0]$2281 - attribute \src "libresoc.v:52642.3-52643.23" + attribute \src "libresoc.v:189180.3-189242.6" + wire $0\irq$12[0:0]$14329 + attribute \src "libresoc.v:189066.3-189081.6" + wire $0\irq$next[0:0]$14308 + attribute \src "libresoc.v:189060.3-189061.23" wire $0\irq[0:0] - attribute \src "libresoc.v:52762.3-52824.6" - wire width 8 $0\mfrr$11[7:0]$2303 - attribute \src "libresoc.v:52648.3-52663.6" - wire width 8 $0\mfrr$next[7:0]$2282 - attribute \src "libresoc.v:52640.3-52641.25" + attribute \src "libresoc.v:189180.3-189242.6" + wire width 8 $0\mfrr$11[7:0]$14330 + attribute \src "libresoc.v:189066.3-189081.6" + wire width 8 $0\mfrr$next[7:0]$14309 + attribute \src "libresoc.v:189058.3-189059.25" wire width 8 $0\mfrr[7:0] - attribute \src "libresoc.v:52731.3-52742.6" + attribute \src "libresoc.v:189149.3-189160.6" wire width 8 $0\min_pri[7:0] - attribute \src "libresoc.v:52721.3-52730.6" + attribute \src "libresoc.v:189139.3-189148.6" wire width 8 $0\pending_priority[7:0] - attribute \src "libresoc.v:52762.3-52824.6" - wire $0\wb_ack$14[0:0]$2304 - attribute \src "libresoc.v:52648.3-52663.6" - wire $0\wb_ack$next[0:0]$2283 - attribute \src "libresoc.v:52646.3-52647.29" + attribute \src "libresoc.v:189180.3-189242.6" + wire $0\wb_ack$14[0:0]$14331 + attribute \src "libresoc.v:189066.3-189081.6" + wire $0\wb_ack$next[0:0]$14310 + attribute \src "libresoc.v:189064.3-189065.29" wire $0\wb_ack[0:0] - attribute \src "libresoc.v:52762.3-52824.6" - wire width 32 $0\wb_rd_data$13[31:0]$2305 - attribute \src "libresoc.v:52648.3-52663.6" - wire width 32 $0\wb_rd_data$next[31:0]$2284 - attribute \src "libresoc.v:52644.3-52645.37" + attribute \src "libresoc.v:189180.3-189242.6" + wire width 32 $0\wb_rd_data$13[31:0]$14332 + attribute \src "libresoc.v:189066.3-189081.6" + wire width 32 $0\wb_rd_data$next[31:0]$14311 + attribute \src "libresoc.v:189062.3-189063.37" wire width 32 $0\wb_rd_data[31:0] - attribute \src "libresoc.v:52664.3-52691.6" + attribute \src "libresoc.v:189082.3-189109.6" wire $0\xirr_accept_rd[0:0] - attribute \src "libresoc.v:52762.3-52824.6" - wire width 24 $0\xisr$9[23:0]$2306 - attribute \src "libresoc.v:52648.3-52663.6" - wire width 24 $0\xisr$next[23:0]$2285 - attribute \src "libresoc.v:52636.3-52637.25" + attribute \src "libresoc.v:189180.3-189242.6" + wire width 24 $0\xisr$9[23:0]$14333 + attribute \src "libresoc.v:189066.3-189081.6" + wire width 24 $0\xisr$next[23:0]$14312 + attribute \src "libresoc.v:189054.3-189055.25" wire width 24 $0\xisr[23:0] - attribute \src "libresoc.v:52692.3-52720.6" + attribute \src "libresoc.v:189110.3-189138.6" wire width 32 $1\be_out[31:0] - attribute \src "libresoc.v:52743.3-52751.6" - wire $1\core_irq_o$next[0:0]$2298 - attribute \src "libresoc.v:52544.7-52544.24" + attribute \src "libresoc.v:189161.3-189169.6" + wire $1\core_irq_o$next[0:0]$14325 + attribute \src "libresoc.v:188962.7-188962.24" wire $1\core_irq_o[0:0] - attribute \src "libresoc.v:52762.3-52824.6" - wire width 8 $1\cppr$10[7:0]$2307 - attribute \src "libresoc.v:52648.3-52663.6" - wire width 8 $1\cppr$next[7:0]$2286 - attribute \src "libresoc.v:52548.13-52548.25" + attribute \src "libresoc.v:189180.3-189242.6" + wire width 8 $1\cppr$10[7:0]$14334 + attribute \src "libresoc.v:189066.3-189081.6" + wire width 8 $1\cppr$next[7:0]$14313 + attribute \src "libresoc.v:188966.13-188966.25" wire width 8 $1\cppr[7:0] - attribute \src "libresoc.v:52752.3-52761.6" + attribute \src "libresoc.v:189170.3-189179.6" wire width 32 $1\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:52762.3-52824.6" - wire $1\irq$12[0:0]$2317 - attribute \src "libresoc.v:52648.3-52663.6" - wire $1\irq$next[0:0]$2287 - attribute \src "libresoc.v:52577.7-52577.17" + attribute \src "libresoc.v:189180.3-189242.6" + wire $1\irq$12[0:0]$14344 + attribute \src "libresoc.v:189066.3-189081.6" + wire $1\irq$next[0:0]$14314 + attribute \src "libresoc.v:188995.7-188995.17" wire $1\irq[0:0] - attribute \src "libresoc.v:52762.3-52824.6" - wire width 8 $1\mfrr$11[7:0]$2308 - attribute \src "libresoc.v:52648.3-52663.6" - wire width 8 $1\mfrr$next[7:0]$2288 - attribute \src "libresoc.v:52585.13-52585.25" + attribute \src "libresoc.v:189180.3-189242.6" + wire width 8 $1\mfrr$11[7:0]$14335 + attribute \src "libresoc.v:189066.3-189081.6" + wire width 8 $1\mfrr$next[7:0]$14315 + attribute \src "libresoc.v:189003.13-189003.25" wire width 8 $1\mfrr[7:0] - attribute \src "libresoc.v:52731.3-52742.6" + attribute \src "libresoc.v:189149.3-189160.6" wire width 8 $1\min_pri[7:0] - attribute \src "libresoc.v:52721.3-52730.6" + attribute \src "libresoc.v:189139.3-189148.6" wire width 8 $1\pending_priority[7:0] - attribute \src "libresoc.v:52762.3-52824.6" - wire $1\wb_ack$14[0:0]$2309 - attribute \src "libresoc.v:52648.3-52663.6" - wire $1\wb_ack$next[0:0]$2289 - attribute \src "libresoc.v:52599.7-52599.20" + attribute \src "libresoc.v:189180.3-189242.6" + wire $1\wb_ack$14[0:0]$14336 + attribute \src "libresoc.v:189066.3-189081.6" + wire $1\wb_ack$next[0:0]$14316 + attribute \src "libresoc.v:189017.7-189017.20" wire $1\wb_ack[0:0] - attribute \src "libresoc.v:52648.3-52663.6" - wire width 32 $1\wb_rd_data$next[31:0]$2290 - attribute \src "libresoc.v:52607.14-52607.32" + attribute \src "libresoc.v:189066.3-189081.6" + wire width 32 $1\wb_rd_data$next[31:0]$14317 + attribute \src "libresoc.v:189025.14-189025.32" wire width 32 $1\wb_rd_data[31:0] - attribute \src "libresoc.v:52664.3-52691.6" + attribute \src "libresoc.v:189082.3-189109.6" wire $1\xirr_accept_rd[0:0] - attribute \src "libresoc.v:52762.3-52824.6" - wire width 24 $1\xisr$9[23:0]$2314 - attribute \src "libresoc.v:52648.3-52663.6" - wire width 24 $1\xisr$next[23:0]$2291 - attribute \src "libresoc.v:52617.14-52617.31" + attribute \src "libresoc.v:189180.3-189242.6" + wire width 24 $1\xisr$9[23:0]$14341 + attribute \src "libresoc.v:189066.3-189081.6" + wire width 24 $1\xisr$next[23:0]$14318 + attribute \src "libresoc.v:189035.14-189035.31" wire width 24 $1\xisr[23:0] - attribute \src "libresoc.v:52692.3-52720.6" + attribute \src "libresoc.v:189110.3-189138.6" wire width 32 $2\be_out[31:0] - attribute \src "libresoc.v:52762.3-52824.6" - wire width 8 $2\cppr$10[7:0]$2310 - attribute \src "libresoc.v:52762.3-52824.6" - wire width 8 $2\mfrr$11[7:0]$2311 - attribute \src "libresoc.v:52664.3-52691.6" + attribute \src "libresoc.v:189180.3-189242.6" + wire width 8 $2\cppr$10[7:0]$14337 + attribute \src "libresoc.v:189180.3-189242.6" + wire width 8 $2\mfrr$11[7:0]$14338 + attribute \src "libresoc.v:189082.3-189109.6" wire $2\xirr_accept_rd[0:0] - attribute \src "libresoc.v:52762.3-52824.6" - wire width 24 $2\xisr$9[23:0]$2315 - attribute \src "libresoc.v:52692.3-52720.6" + attribute \src "libresoc.v:189180.3-189242.6" + wire width 24 $2\xisr$9[23:0]$14342 + attribute \src "libresoc.v:189110.3-189138.6" wire width 32 $3\be_out[31:0] - attribute \src "libresoc.v:52762.3-52824.6" - wire width 8 $3\cppr$10[7:0]$2312 - attribute \src "libresoc.v:52762.3-52824.6" - wire width 8 $3\mfrr$11[7:0]$2313 - attribute \src "libresoc.v:52664.3-52691.6" + attribute \src "libresoc.v:189180.3-189242.6" + wire width 8 $3\cppr$10[7:0]$14339 + attribute \src "libresoc.v:189180.3-189242.6" + wire width 8 $3\mfrr$11[7:0]$14340 + attribute \src "libresoc.v:189082.3-189109.6" wire $3\xirr_accept_rd[0:0] - attribute \src "libresoc.v:52762.3-52824.6" - wire width 8 $4\cppr$10[7:0]$2316 - attribute \src "libresoc.v:52664.3-52691.6" + attribute \src "libresoc.v:189180.3-189242.6" + wire width 8 $4\cppr$10[7:0]$14343 + attribute \src "libresoc.v:189082.3-189109.6" wire $4\xirr_accept_rd[0:0] - attribute \src "libresoc.v:52624.18-52624.116" - wire $and$libresoc.v:52624$2262_Y - attribute \src "libresoc.v:52628.18-52628.116" - wire $and$libresoc.v:52628$2266_Y - attribute \src "libresoc.v:52630.18-52630.116" - wire $and$libresoc.v:52630$2268_Y - attribute \src "libresoc.v:52633.17-52633.109" - wire $and$libresoc.v:52633$2271_Y - attribute \src "libresoc.v:52629.18-52629.110" - wire $eq$libresoc.v:52629$2267_Y - attribute \src "libresoc.v:52626.18-52626.114" - wire $lt$libresoc.v:52626$2264_Y - attribute \src "libresoc.v:52627.18-52627.109" - wire $lt$libresoc.v:52627$2265_Y - attribute \src "libresoc.v:52632.18-52632.114" - wire $lt$libresoc.v:52632$2270_Y - attribute \src "libresoc.v:52625.18-52625.109" - wire $ne$libresoc.v:52625$2263_Y - attribute \src "libresoc.v:52631.18-52631.109" - wire $ne$libresoc.v:52631$2269_Y + attribute \src "libresoc.v:189042.18-189042.116" + wire $and$libresoc.v:189042$14289_Y + attribute \src "libresoc.v:189046.18-189046.116" + wire $and$libresoc.v:189046$14293_Y + attribute \src "libresoc.v:189048.18-189048.116" + wire $and$libresoc.v:189048$14295_Y + attribute \src "libresoc.v:189051.17-189051.109" + wire $and$libresoc.v:189051$14298_Y + attribute \src "libresoc.v:189047.18-189047.110" + wire $eq$libresoc.v:189047$14294_Y + attribute \src "libresoc.v:189044.18-189044.114" + wire $lt$libresoc.v:189044$14291_Y + attribute \src "libresoc.v:189045.18-189045.109" + wire $lt$libresoc.v:189045$14292_Y + attribute \src "libresoc.v:189050.18-189050.114" + wire $lt$libresoc.v:189050$14297_Y + attribute \src "libresoc.v:189043.18-189043.109" + wire $ne$libresoc.v:189043$14290_Y + attribute \src "libresoc.v:189049.18-189049.109" + wire $ne$libresoc.v:189049$14296_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" wire \$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" @@ -146589,7 +397160,7 @@ module \xics_icp wire width 8 input 3 \ics_i_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" wire width 4 input 2 \ics_i_src - attribute \src "libresoc.v:52515.7-52515.15" + attribute \src "libresoc.v:188933.7-188933.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" wire \irq @@ -146640,7 +397211,7 @@ module \xics_icp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" wire width 24 \xisr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:52624$2262 + cell $and $and$libresoc.v:189042$14289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -146648,10 +397219,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$libresoc.v:52624$2262_Y + connect \Y $and$libresoc.v:189042$14289_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:52628$2266 + cell $and $and$libresoc.v:189046$14293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -146659,10 +397230,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$libresoc.v:52628$2266_Y + connect \Y $and$libresoc.v:189046$14293_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:52630$2268 + cell $and $and$libresoc.v:189048$14295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -146670,10 +397241,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$libresoc.v:52630$2268_Y + connect \Y $and$libresoc.v:189048$14295_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96" - cell $and $and$libresoc.v:52633$2271 + cell $and $and$libresoc.v:189051$14298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -146681,10 +397252,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \wb_ack connect \B \icp_wb__cyc - connect \Y $and$libresoc.v:52633$2271_Y + connect \Y $and$libresoc.v:189051$14298_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" - cell $eq $eq$libresoc.v:52629$2267 + cell $eq $eq$libresoc.v:189047$14294 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -146692,10 +397263,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__sel connect \B 4'1111 - connect \Y $eq$libresoc.v:52629$2267_Y + connect \Y $eq$libresoc.v:189047$14294_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" - cell $lt $lt$libresoc.v:52626$2264 + cell $lt $lt$libresoc.v:189044$14291 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -146703,10 +397274,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \mfrr connect \B \pending_priority - connect \Y $lt$libresoc.v:52626$2264_Y + connect \Y $lt$libresoc.v:189044$14291_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" - cell $lt $lt$libresoc.v:52627$2265 + cell $lt $lt$libresoc.v:189045$14292 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -146714,10 +397285,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \min_pri connect \B \cppr$10 - connect \Y $lt$libresoc.v:52627$2265_Y + connect \Y $lt$libresoc.v:189045$14292_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" - cell $lt $lt$libresoc.v:52632$2270 + cell $lt $lt$libresoc.v:189050$14297 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -146725,10 +397296,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \mfrr connect \B \pending_priority - connect \Y $lt$libresoc.v:52632$2270_Y + connect \Y $lt$libresoc.v:189050$14297_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" - cell $ne $ne$libresoc.v:52625$2263 + cell $ne $ne$libresoc.v:189043$14290 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -146736,10 +397307,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \ics_i_pri connect \B 8'11111111 - connect \Y $ne$libresoc.v:52625$2263_Y + connect \Y $ne$libresoc.v:189043$14290_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" - cell $ne $ne$libresoc.v:52631$2269 + cell $ne $ne$libresoc.v:189049$14296 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -146747,123 +397318,123 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \ics_i_pri connect \B 8'11111111 - connect \Y $ne$libresoc.v:52631$2269_Y + connect \Y $ne$libresoc.v:189049$14296_Y end - attribute \src "libresoc.v:52515.7-52515.20" - process $proc$libresoc.v:52515$2318 + attribute \src "libresoc.v:188933.7-188933.20" + process $proc$libresoc.v:188933$14345 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:52544.7-52544.24" - process $proc$libresoc.v:52544$2319 + attribute \src "libresoc.v:188962.7-188962.24" + process $proc$libresoc.v:188962$14346 assign { } { } assign $1\core_irq_o[0:0] 1'0 sync always sync init update \core_irq_o $1\core_irq_o[0:0] end - attribute \src "libresoc.v:52548.13-52548.25" - process $proc$libresoc.v:52548$2320 + attribute \src "libresoc.v:188966.13-188966.25" + process $proc$libresoc.v:188966$14347 assign { } { } assign $1\cppr[7:0] 8'00000000 sync always sync init update \cppr $1\cppr[7:0] end - attribute \src "libresoc.v:52577.7-52577.17" - process $proc$libresoc.v:52577$2321 + attribute \src "libresoc.v:188995.7-188995.17" + process $proc$libresoc.v:188995$14348 assign { } { } assign $1\irq[0:0] 1'0 sync always sync init update \irq $1\irq[0:0] end - attribute \src "libresoc.v:52585.13-52585.25" - process $proc$libresoc.v:52585$2322 + attribute \src "libresoc.v:189003.13-189003.25" + process $proc$libresoc.v:189003$14349 assign { } { } assign $1\mfrr[7:0] 8'11111111 sync always sync init update \mfrr $1\mfrr[7:0] end - attribute \src "libresoc.v:52599.7-52599.20" - process $proc$libresoc.v:52599$2323 + attribute \src "libresoc.v:189017.7-189017.20" + process $proc$libresoc.v:189017$14350 assign { } { } assign $1\wb_ack[0:0] 1'0 sync always sync init update \wb_ack $1\wb_ack[0:0] end - attribute \src "libresoc.v:52607.14-52607.32" - process $proc$libresoc.v:52607$2324 + attribute \src "libresoc.v:189025.14-189025.32" + process $proc$libresoc.v:189025$14351 assign { } { } assign $1\wb_rd_data[31:0] 0 sync always sync init update \wb_rd_data $1\wb_rd_data[31:0] end - attribute \src "libresoc.v:52617.14-52617.31" - process $proc$libresoc.v:52617$2325 + attribute \src "libresoc.v:189035.14-189035.31" + process $proc$libresoc.v:189035$14352 assign { } { } assign $1\xisr[23:0] 24'000000000000000000000000 sync always sync init update \xisr $1\xisr[23:0] end - attribute \src "libresoc.v:52634.3-52635.37" - process $proc$libresoc.v:52634$2272 + attribute \src "libresoc.v:189052.3-189053.37" + process $proc$libresoc.v:189052$14299 assign { } { } assign $0\core_irq_o[0:0] \core_irq_o$next sync posedge \clk update \core_irq_o $0\core_irq_o[0:0] end - attribute \src "libresoc.v:52636.3-52637.25" - process $proc$libresoc.v:52636$2273 + attribute \src "libresoc.v:189054.3-189055.25" + process $proc$libresoc.v:189054$14300 assign { } { } assign $0\xisr[23:0] \xisr$next sync posedge \clk update \xisr $0\xisr[23:0] end - attribute \src "libresoc.v:52638.3-52639.25" - process $proc$libresoc.v:52638$2274 + attribute \src "libresoc.v:189056.3-189057.25" + process $proc$libresoc.v:189056$14301 assign { } { } assign $0\cppr[7:0] \cppr$next sync posedge \clk update \cppr $0\cppr[7:0] end - attribute \src "libresoc.v:52640.3-52641.25" - process $proc$libresoc.v:52640$2275 + attribute \src "libresoc.v:189058.3-189059.25" + process $proc$libresoc.v:189058$14302 assign { } { } assign $0\mfrr[7:0] \mfrr$next sync posedge \clk update \mfrr $0\mfrr[7:0] end - attribute \src "libresoc.v:52642.3-52643.23" - process $proc$libresoc.v:52642$2276 + attribute \src "libresoc.v:189060.3-189061.23" + process $proc$libresoc.v:189060$14303 assign { } { } assign $0\irq[0:0] \irq$next sync posedge \clk update \irq $0\irq[0:0] end - attribute \src "libresoc.v:52644.3-52645.37" - process $proc$libresoc.v:52644$2277 + attribute \src "libresoc.v:189062.3-189063.37" + process $proc$libresoc.v:189062$14304 assign { } { } assign $0\wb_rd_data[31:0] \wb_rd_data$next sync posedge \clk update \wb_rd_data $0\wb_rd_data[31:0] end - attribute \src "libresoc.v:52646.3-52647.29" - process $proc$libresoc.v:52646$2278 + attribute \src "libresoc.v:189064.3-189065.29" + process $proc$libresoc.v:189064$14305 assign { } { } assign $0\wb_ack[0:0] \wb_ack$next sync posedge \clk update \wb_ack $0\wb_ack[0:0] end - attribute \src "libresoc.v:52648.3-52663.6" - process $proc$libresoc.v:52648$2279 + attribute \src "libresoc.v:189066.3-189081.6" + process $proc$libresoc.v:189066$14306 assign { } { } assign { } { } assign { } { } @@ -146871,15 +397442,15 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $0\cppr$next[7:0]$2280 $1\cppr$next[7:0]$2286 - assign $0\irq$next[0:0]$2281 $1\irq$next[0:0]$2287 - assign $0\mfrr$next[7:0]$2282 $1\mfrr$next[7:0]$2288 - assign $0\wb_ack$next[0:0]$2283 $1\wb_ack$next[0:0]$2289 - assign $0\wb_rd_data$next[31:0]$2284 $1\wb_rd_data$next[31:0]$2290 - assign $0\xisr$next[23:0]$2285 $1\xisr$next[23:0]$2291 - attribute \src "libresoc.v:52649.5-52649.29" + assign $0\cppr$next[7:0]$14307 $1\cppr$next[7:0]$14313 + assign $0\irq$next[0:0]$14308 $1\irq$next[0:0]$14314 + assign $0\mfrr$next[7:0]$14309 $1\mfrr$next[7:0]$14315 + assign $0\wb_ack$next[0:0]$14310 $1\wb_ack$next[0:0]$14316 + assign $0\wb_rd_data$next[31:0]$14311 $1\wb_rd_data$next[31:0]$14317 + assign $0\xisr$next[23:0]$14312 $1\xisr$next[23:0]$14318 + attribute \src "libresoc.v:189067.5-189067.29" switch \initial - attribute \src "libresoc.v:52649.9-52649.17" + attribute \src "libresoc.v:189067.9-189067.17" case 1'1 case end @@ -146893,36 +397464,36 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $1\xisr$next[23:0]$2291 24'000000000000000000000000 - assign $1\cppr$next[7:0]$2286 8'00000000 - assign $1\mfrr$next[7:0]$2288 8'11111111 - assign $1\irq$next[0:0]$2287 1'0 - assign $1\wb_rd_data$next[31:0]$2290 0 - assign $1\wb_ack$next[0:0]$2289 1'0 + assign $1\xisr$next[23:0]$14318 24'000000000000000000000000 + assign $1\cppr$next[7:0]$14313 8'00000000 + assign $1\mfrr$next[7:0]$14315 8'11111111 + assign $1\irq$next[0:0]$14314 1'0 + assign $1\wb_rd_data$next[31:0]$14317 0 + assign $1\wb_ack$next[0:0]$14316 1'0 case - assign $1\cppr$next[7:0]$2286 \cppr$2 - assign $1\irq$next[0:0]$2287 \irq$4 - assign $1\mfrr$next[7:0]$2288 \mfrr$3 - assign $1\wb_ack$next[0:0]$2289 \wb_ack$6 - assign $1\wb_rd_data$next[31:0]$2290 \wb_rd_data$5 - assign $1\xisr$next[23:0]$2291 \xisr$1 + assign $1\cppr$next[7:0]$14313 \cppr$2 + assign $1\irq$next[0:0]$14314 \irq$4 + assign $1\mfrr$next[7:0]$14315 \mfrr$3 + assign $1\wb_ack$next[0:0]$14316 \wb_ack$6 + assign $1\wb_rd_data$next[31:0]$14317 \wb_rd_data$5 + assign $1\xisr$next[23:0]$14318 \xisr$1 end sync always - update \cppr$next $0\cppr$next[7:0]$2280 - update \irq$next $0\irq$next[0:0]$2281 - update \mfrr$next $0\mfrr$next[7:0]$2282 - update \wb_ack$next $0\wb_ack$next[0:0]$2283 - update \wb_rd_data$next $0\wb_rd_data$next[31:0]$2284 - update \xisr$next $0\xisr$next[23:0]$2285 + update \cppr$next $0\cppr$next[7:0]$14307 + update \irq$next $0\irq$next[0:0]$14308 + update \mfrr$next $0\mfrr$next[7:0]$14309 + update \wb_ack$next $0\wb_ack$next[0:0]$14310 + update \wb_rd_data$next $0\wb_rd_data$next[31:0]$14311 + update \xisr$next $0\xisr$next[23:0]$14312 end - attribute \src "libresoc.v:52664.3-52691.6" - process $proc$libresoc.v:52664$2292 + attribute \src "libresoc.v:189082.3-189109.6" + process $proc$libresoc.v:189082$14319 assign { } { } assign { } { } assign $0\xirr_accept_rd[0:0] $1\xirr_accept_rd[0:0] - attribute \src "libresoc.v:52665.5-52665.29" + attribute \src "libresoc.v:189083.5-189083.29" switch \initial - attribute \src "libresoc.v:52665.9-52665.17" + attribute \src "libresoc.v:189083.9-189083.17" case 1'1 case end @@ -146966,14 +397537,14 @@ module \xics_icp sync always update \xirr_accept_rd $0\xirr_accept_rd[0:0] end - attribute \src "libresoc.v:52692.3-52720.6" - process $proc$libresoc.v:52692$2293 + attribute \src "libresoc.v:189110.3-189138.6" + process $proc$libresoc.v:189110$14320 assign { } { } assign { } { } assign $0\be_out[31:0] $1\be_out[31:0] - attribute \src "libresoc.v:52693.5-52693.29" + attribute \src "libresoc.v:189111.5-189111.29" switch \initial - attribute \src "libresoc.v:52693.9-52693.17" + attribute \src "libresoc.v:189111.9-189111.17" case 1'1 case end @@ -147016,14 +397587,14 @@ module \xics_icp sync always update \be_out $0\be_out[31:0] end - attribute \src "libresoc.v:52721.3-52730.6" - process $proc$libresoc.v:52721$2294 + attribute \src "libresoc.v:189139.3-189148.6" + process $proc$libresoc.v:189139$14321 assign { } { } assign { } { } assign $0\pending_priority[7:0] $1\pending_priority[7:0] - attribute \src "libresoc.v:52722.5-52722.29" + attribute \src "libresoc.v:189140.5-189140.29" switch \initial - attribute \src "libresoc.v:52722.9-52722.17" + attribute \src "libresoc.v:189140.9-189140.17" case 1'1 case end @@ -147039,13 +397610,13 @@ module \xics_icp sync always update \pending_priority $0\pending_priority[7:0] end - attribute \src "libresoc.v:52731.3-52742.6" - process $proc$libresoc.v:52731$2295 + attribute \src "libresoc.v:189149.3-189160.6" + process $proc$libresoc.v:189149$14322 assign { } { } assign $0\min_pri[7:0] $1\min_pri[7:0] - attribute \src "libresoc.v:52732.5-52732.29" + attribute \src "libresoc.v:189150.5-189150.29" switch \initial - attribute \src "libresoc.v:52732.9-52732.17" + attribute \src "libresoc.v:189150.9-189150.17" case 1'1 case end @@ -147063,14 +397634,14 @@ module \xics_icp sync always update \min_pri $0\min_pri[7:0] end - attribute \src "libresoc.v:52743.3-52751.6" - process $proc$libresoc.v:52743$2296 + attribute \src "libresoc.v:189161.3-189169.6" + process $proc$libresoc.v:189161$14323 assign { } { } assign { } { } - assign $0\core_irq_o$next[0:0]$2297 $1\core_irq_o$next[0:0]$2298 - attribute \src "libresoc.v:52744.5-52744.29" + assign $0\core_irq_o$next[0:0]$14324 $1\core_irq_o$next[0:0]$14325 + attribute \src "libresoc.v:189162.5-189162.29" switch \initial - attribute \src "libresoc.v:52744.9-52744.17" + attribute \src "libresoc.v:189162.9-189162.17" case 1'1 case end @@ -147079,21 +397650,21 @@ module \xics_icp attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\core_irq_o$next[0:0]$2298 1'0 + assign $1\core_irq_o$next[0:0]$14325 1'0 case - assign $1\core_irq_o$next[0:0]$2298 \irq + assign $1\core_irq_o$next[0:0]$14325 \irq end sync always - update \core_irq_o$next $0\core_irq_o$next[0:0]$2297 + update \core_irq_o$next $0\core_irq_o$next[0:0]$14324 end - attribute \src "libresoc.v:52752.3-52761.6" - process $proc$libresoc.v:52752$2299 + attribute \src "libresoc.v:189170.3-189179.6" + process $proc$libresoc.v:189170$14326 assign { } { } assign { } { } assign $0\icp_wb__dat_r[31:0] $1\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:52753.5-52753.29" + attribute \src "libresoc.v:189171.5-189171.29" switch \initial - attribute \src "libresoc.v:52753.9-52753.17" + attribute \src "libresoc.v:189171.9-189171.17" case 1'1 case end @@ -147109,8 +397680,8 @@ module \xics_icp sync always update \icp_wb__dat_r $0\icp_wb__dat_r[31:0] end - attribute \src "libresoc.v:52762.3-52824.6" - process $proc$libresoc.v:52762$2300 + attribute \src "libresoc.v:189180.3-189242.6" + process $proc$libresoc.v:189180$14327 assign { } { } assign { } { } assign { } { } @@ -147120,18 +397691,18 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $0\mfrr$11[7:0]$2303 $1\mfrr$11[7:0]$2308 - assign $0\wb_ack$14[0:0]$2304 $1\wb_ack$14[0:0]$2309 + assign $0\mfrr$11[7:0]$14330 $1\mfrr$11[7:0]$14335 + assign $0\wb_ack$14[0:0]$14331 $1\wb_ack$14[0:0]$14336 assign { } { } assign { } { } assign { } { } - assign $0\xisr$9[23:0]$2306 $2\xisr$9[23:0]$2315 - assign $0\cppr$10[7:0]$2301 $4\cppr$10[7:0]$2316 - assign $0\wb_rd_data$13[31:0]$2305 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } - assign $0\irq$12[0:0]$2302 $1\irq$12[0:0]$2317 - attribute \src "libresoc.v:52763.5-52763.29" + assign $0\xisr$9[23:0]$14333 $2\xisr$9[23:0]$14342 + assign $0\cppr$10[7:0]$14328 $4\cppr$10[7:0]$14343 + assign $0\wb_rd_data$13[31:0]$14332 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + assign $0\irq$12[0:0]$14329 $1\irq$12[0:0]$14344 + attribute \src "libresoc.v:189181.5-189181.29" switch \initial - attribute \src "libresoc.v:52763.9-52763.17" + attribute \src "libresoc.v:189181.9-189181.17" case 1'1 case end @@ -147142,712 +397713,712 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $1\wb_ack$14[0:0]$2309 1'1 - assign $1\cppr$10[7:0]$2307 $2\cppr$10[7:0]$2310 - assign $1\mfrr$11[7:0]$2308 $2\mfrr$11[7:0]$2311 + assign $1\wb_ack$14[0:0]$14336 1'1 + assign $1\cppr$10[7:0]$14334 $2\cppr$10[7:0]$14337 + assign $1\mfrr$11[7:0]$14335 $2\mfrr$11[7:0]$14338 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" switch \icp_wb__we attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } - assign $2\cppr$10[7:0]$2310 $3\cppr$10[7:0]$2312 - assign $2\mfrr$11[7:0]$2311 $3\mfrr$11[7:0]$2313 + assign $2\cppr$10[7:0]$14337 $3\cppr$10[7:0]$14339 + assign $2\mfrr$11[7:0]$14338 $3\mfrr$11[7:0]$14340 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:121" switch \icp_wb__adr [5:0] attribute \src "libresoc.v:0.0-0.0" case 6'000000 assign { } { } - assign $3\mfrr$11[7:0]$2313 \mfrr - assign $3\cppr$10[7:0]$2312 \be_in [31:24] + assign $3\mfrr$11[7:0]$14340 \mfrr + assign $3\cppr$10[7:0]$14339 \be_in [31:24] attribute \src "libresoc.v:0.0-0.0" case 6'000001 assign { } { } - assign $3\mfrr$11[7:0]$2313 \mfrr - assign $3\cppr$10[7:0]$2312 \be_in [31:24] + assign $3\mfrr$11[7:0]$14340 \mfrr + assign $3\cppr$10[7:0]$14339 \be_in [31:24] attribute \src "libresoc.v:0.0-0.0" case 6'000011 - assign $3\cppr$10[7:0]$2312 \cppr + assign $3\cppr$10[7:0]$14339 \cppr assign { } { } - assign $3\mfrr$11[7:0]$2313 \be_in [31:24] + assign $3\mfrr$11[7:0]$14340 \be_in [31:24] case - assign $3\cppr$10[7:0]$2312 \cppr - assign $3\mfrr$11[7:0]$2313 \mfrr + assign $3\cppr$10[7:0]$14339 \cppr + assign $3\mfrr$11[7:0]$14340 \mfrr end case - assign $2\cppr$10[7:0]$2310 \cppr - assign $2\mfrr$11[7:0]$2311 \mfrr + assign $2\cppr$10[7:0]$14337 \cppr + assign $2\mfrr$11[7:0]$14338 \mfrr end case - assign $1\cppr$10[7:0]$2307 \cppr - assign $1\mfrr$11[7:0]$2308 \mfrr - assign $1\wb_ack$14[0:0]$2309 1'0 + assign $1\cppr$10[7:0]$14334 \cppr + assign $1\mfrr$11[7:0]$14335 \mfrr + assign $1\wb_ack$14[0:0]$14336 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" switch \$17 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xisr$9[23:0]$2314 { 20'00000000000000000001 \ics_i_src } + assign $1\xisr$9[23:0]$14341 { 20'00000000000000000001 \ics_i_src } case - assign $1\xisr$9[23:0]$2314 24'000000000000000000000000 + assign $1\xisr$9[23:0]$14341 24'000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xisr$9[23:0]$2315 24'000000000000000000000010 + assign $2\xisr$9[23:0]$14342 24'000000000000000000000010 case - assign $2\xisr$9[23:0]$2315 $1\xisr$9[23:0]$2314 + assign $2\xisr$9[23:0]$14342 $1\xisr$9[23:0]$14341 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:185" switch \xirr_accept_rd attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cppr$10[7:0]$2316 \min_pri + assign $4\cppr$10[7:0]$14343 \min_pri case - assign $4\cppr$10[7:0]$2316 $1\cppr$10[7:0]$2307 + assign $4\cppr$10[7:0]$14343 $1\cppr$10[7:0]$14334 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" switch { \irq \$21 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\irq$12[0:0]$2317 1'1 + assign $1\irq$12[0:0]$14344 1'1 case - assign $1\irq$12[0:0]$2317 1'0 + assign $1\irq$12[0:0]$14344 1'0 end sync always - update \cppr$10 $0\cppr$10[7:0]$2301 - update \irq$12 $0\irq$12[0:0]$2302 - update \mfrr$11 $0\mfrr$11[7:0]$2303 - update \wb_ack$14 $0\wb_ack$14[0:0]$2304 - update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$2305 - update \xisr$9 $0\xisr$9[23:0]$2306 + update \cppr$10 $0\cppr$10[7:0]$14328 + update \irq$12 $0\irq$12[0:0]$14329 + update \mfrr$11 $0\mfrr$11[7:0]$14330 + update \wb_ack$14 $0\wb_ack$14[0:0]$14331 + update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$14332 + update \xisr$9 $0\xisr$9[23:0]$14333 end - connect \$15 $and$libresoc.v:52624$2262_Y - connect \$17 $ne$libresoc.v:52625$2263_Y - connect \$19 $lt$libresoc.v:52626$2264_Y - connect \$21 $lt$libresoc.v:52627$2265_Y - connect \$23 $and$libresoc.v:52628$2266_Y - connect \$25 $eq$libresoc.v:52629$2267_Y - connect \$27 $and$libresoc.v:52630$2268_Y - connect \$29 $ne$libresoc.v:52631$2269_Y - connect \$31 $lt$libresoc.v:52632$2270_Y - connect \$7 $and$libresoc.v:52633$2271_Y + connect \$15 $and$libresoc.v:189042$14289_Y + connect \$17 $ne$libresoc.v:189043$14290_Y + connect \$19 $lt$libresoc.v:189044$14291_Y + connect \$21 $lt$libresoc.v:189045$14292_Y + connect \$23 $and$libresoc.v:189046$14293_Y + connect \$25 $eq$libresoc.v:189047$14294_Y + connect \$27 $and$libresoc.v:189048$14295_Y + connect \$29 $ne$libresoc.v:189049$14296_Y + connect \$31 $lt$libresoc.v:189050$14297_Y + connect \$7 $and$libresoc.v:189051$14298_Y connect { \wb_ack$6 \wb_rd_data$5 \irq$4 \mfrr$3 \cppr$2 \xisr$1 } { \wb_ack$14 \wb_rd_data$13 \irq$12 \mfrr$11 \cppr$10 \xisr$9 } connect \be_in { \icp_wb__dat_w [7:0] \icp_wb__dat_w [15:8] \icp_wb__dat_w [23:16] \icp_wb__dat_w [31:24] } connect \icp_wb__ack \$7 end -attribute \src "libresoc.v:52832.1-53881.10" +attribute \src "libresoc.v:189250.1-190299.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.xics_ics" attribute \generator "nMigen" module \xics_ics - attribute \src "libresoc.v:53762.3-53811.6" + attribute \src "libresoc.v:190180.3-190229.6" wire width 32 $0\be_out[31:0] - attribute \src "libresoc.v:53473.3-53482.6" + attribute \src "libresoc.v:189891.3-189900.6" wire width 4 $0\cur_idx0[3:0] - attribute \src "libresoc.v:53682.3-53691.6" + attribute \src "libresoc.v:190100.3-190109.6" wire width 4 $0\cur_idx10[3:0] - attribute \src "libresoc.v:53702.3-53711.6" + attribute \src "libresoc.v:190120.3-190129.6" wire width 4 $0\cur_idx11[3:0] - attribute \src "libresoc.v:53722.3-53731.6" + attribute \src "libresoc.v:190140.3-190149.6" wire width 4 $0\cur_idx12[3:0] - attribute \src "libresoc.v:53742.3-53751.6" + attribute \src "libresoc.v:190160.3-190169.6" wire width 4 $0\cur_idx13[3:0] - attribute \src "libresoc.v:53812.3-53821.6" + attribute \src "libresoc.v:190230.3-190239.6" wire width 4 $0\cur_idx14[3:0] - attribute \src "libresoc.v:53832.3-53841.6" + attribute \src "libresoc.v:190250.3-190259.6" wire width 4 $0\cur_idx15[3:0] - attribute \src "libresoc.v:53493.3-53502.6" + attribute \src "libresoc.v:189911.3-189920.6" wire width 4 $0\cur_idx1[3:0] - attribute \src "libresoc.v:53513.3-53522.6" + attribute \src "libresoc.v:189931.3-189940.6" wire width 4 $0\cur_idx2[3:0] - attribute \src "libresoc.v:53533.3-53542.6" + attribute \src "libresoc.v:189951.3-189960.6" wire width 4 $0\cur_idx3[3:0] - attribute \src "libresoc.v:53562.3-53571.6" + attribute \src "libresoc.v:189980.3-189989.6" wire width 4 $0\cur_idx4[3:0] - attribute \src "libresoc.v:53582.3-53591.6" + attribute \src "libresoc.v:190000.3-190009.6" wire width 4 $0\cur_idx5[3:0] - attribute \src "libresoc.v:53602.3-53611.6" + attribute \src "libresoc.v:190020.3-190029.6" wire width 4 $0\cur_idx6[3:0] - attribute \src "libresoc.v:53622.3-53631.6" + attribute \src "libresoc.v:190040.3-190049.6" wire width 4 $0\cur_idx7[3:0] - attribute \src "libresoc.v:53642.3-53651.6" + attribute \src "libresoc.v:190060.3-190069.6" wire width 4 $0\cur_idx8[3:0] - attribute \src "libresoc.v:53662.3-53671.6" + attribute \src "libresoc.v:190080.3-190089.6" wire width 4 $0\cur_idx9[3:0] - attribute \src "libresoc.v:53463.3-53472.6" + attribute \src "libresoc.v:189881.3-189890.6" wire width 8 $0\cur_pri0[7:0] - attribute \src "libresoc.v:53672.3-53681.6" + attribute \src "libresoc.v:190090.3-190099.6" wire width 8 $0\cur_pri10[7:0] - attribute \src "libresoc.v:53692.3-53701.6" + attribute \src "libresoc.v:190110.3-190119.6" wire width 8 $0\cur_pri11[7:0] - attribute \src "libresoc.v:53712.3-53721.6" + attribute \src "libresoc.v:190130.3-190139.6" wire width 8 $0\cur_pri12[7:0] - attribute \src "libresoc.v:53732.3-53741.6" + attribute \src "libresoc.v:190150.3-190159.6" wire width 8 $0\cur_pri13[7:0] - attribute \src "libresoc.v:53752.3-53761.6" + attribute \src "libresoc.v:190170.3-190179.6" wire width 8 $0\cur_pri14[7:0] - attribute \src "libresoc.v:53822.3-53831.6" + attribute \src "libresoc.v:190240.3-190249.6" wire width 8 $0\cur_pri15[7:0] - attribute \src "libresoc.v:53483.3-53492.6" + attribute \src "libresoc.v:189901.3-189910.6" wire width 8 $0\cur_pri1[7:0] - attribute \src "libresoc.v:53503.3-53512.6" + attribute \src "libresoc.v:189921.3-189930.6" wire width 8 $0\cur_pri2[7:0] - attribute \src "libresoc.v:53523.3-53532.6" + attribute \src "libresoc.v:189941.3-189950.6" wire width 8 $0\cur_pri3[7:0] - attribute \src "libresoc.v:53543.3-53552.6" + attribute \src "libresoc.v:189961.3-189970.6" wire width 8 $0\cur_pri4[7:0] - attribute \src "libresoc.v:53572.3-53581.6" + attribute \src "libresoc.v:189990.3-189999.6" wire width 8 $0\cur_pri5[7:0] - attribute \src "libresoc.v:53592.3-53601.6" + attribute \src "libresoc.v:190010.3-190019.6" wire width 8 $0\cur_pri6[7:0] - attribute \src "libresoc.v:53612.3-53621.6" + attribute \src "libresoc.v:190030.3-190039.6" wire width 8 $0\cur_pri7[7:0] - attribute \src "libresoc.v:53632.3-53641.6" + attribute \src "libresoc.v:190050.3-190059.6" wire width 8 $0\cur_pri8[7:0] - attribute \src "libresoc.v:53652.3-53661.6" + attribute \src "libresoc.v:190070.3-190079.6" wire width 8 $0\cur_pri9[7:0] - attribute \src "libresoc.v:53842.3-53851.6" + attribute \src "libresoc.v:190260.3-190269.6" wire $0\ibit[0:0] - attribute \src "libresoc.v:53353.3-53354.25" + attribute \src "libresoc.v:189771.3-189772.25" wire width 8 $0\icp_o_pri[7:0] - attribute \src "libresoc.v:53351.3-53352.28" + attribute \src "libresoc.v:189769.3-189770.28" wire width 4 $0\icp_o_src[3:0] - attribute \src "libresoc.v:53861.3-53869.6" - wire $0\ics_wb__ack$next[0:0]$2572 - attribute \src "libresoc.v:53345.3-53346.39" + attribute \src "libresoc.v:190279.3-190287.6" + wire $0\ics_wb__ack$next[0:0]$14599 + attribute \src "libresoc.v:189763.3-189764.39" wire $0\ics_wb__ack[0:0] - attribute \src "libresoc.v:53852.3-53860.6" - wire width 32 $0\ics_wb__dat_r$next[31:0]$2569 - attribute \src "libresoc.v:53347.3-53348.43" + attribute \src "libresoc.v:190270.3-190278.6" + wire width 32 $0\ics_wb__dat_r$next[31:0]$14596 + attribute \src "libresoc.v:189765.3-189766.43" wire width 32 $0\ics_wb__dat_r[31:0] - attribute \src "libresoc.v:52833.7-52833.20" + attribute \src "libresoc.v:189251.7-189251.20" wire $0\initial[0:0] - attribute \src "libresoc.v:53553.3-53561.6" - wire width 16 $0\int_level_l$next[15:0]$2541 - attribute \src "libresoc.v:53349.3-53350.39" + attribute \src "libresoc.v:189971.3-189979.6" + wire width 16 $0\int_level_l$next[15:0]$14568 + attribute \src "libresoc.v:189767.3-189768.39" wire width 16 $0\int_level_l[15:0] - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $0\xive0_pri$next[7:0]$2451 - attribute \src "libresoc.v:53355.3-53356.35" + attribute \src "libresoc.v:189795.3-189880.6" + wire width 8 $0\xive0_pri$next[7:0]$14478 + attribute \src "libresoc.v:189773.3-189774.35" wire width 8 $0\xive0_pri[7:0] - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $0\xive10_pri$next[7:0]$2452 - attribute \src "libresoc.v:53375.3-53376.37" + attribute \src "libresoc.v:189795.3-189880.6" + wire width 8 $0\xive10_pri$next[7:0]$14479 + attribute \src "libresoc.v:189793.3-189794.37" wire width 8 $0\xive10_pri[7:0] - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $0\xive11_pri$next[7:0]$2453 - attribute \src "libresoc.v:53335.3-53336.37" + attribute \src "libresoc.v:189795.3-189880.6" + wire width 8 $0\xive11_pri$next[7:0]$14480 + attribute \src "libresoc.v:189753.3-189754.37" wire width 8 $0\xive11_pri[7:0] - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $0\xive12_pri$next[7:0]$2454 - attribute \src "libresoc.v:53337.3-53338.37" + attribute \src "libresoc.v:189795.3-189880.6" + wire width 8 $0\xive12_pri$next[7:0]$14481 + attribute \src "libresoc.v:189755.3-189756.37" wire width 8 $0\xive12_pri[7:0] - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $0\xive13_pri$next[7:0]$2455 - attribute \src "libresoc.v:53339.3-53340.37" + attribute \src "libresoc.v:189795.3-189880.6" + wire width 8 $0\xive13_pri$next[7:0]$14482 + attribute \src "libresoc.v:189757.3-189758.37" wire width 8 $0\xive13_pri[7:0] - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $0\xive14_pri$next[7:0]$2456 - attribute \src "libresoc.v:53341.3-53342.37" + attribute \src "libresoc.v:189795.3-189880.6" + wire width 8 $0\xive14_pri$next[7:0]$14483 + attribute \src "libresoc.v:189759.3-189760.37" wire width 8 $0\xive14_pri[7:0] - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $0\xive15_pri$next[7:0]$2457 - attribute \src "libresoc.v:53343.3-53344.37" + attribute \src "libresoc.v:189795.3-189880.6" + wire width 8 $0\xive15_pri$next[7:0]$14484 + attribute \src "libresoc.v:189761.3-189762.37" wire width 8 $0\xive15_pri[7:0] - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $0\xive1_pri$next[7:0]$2458 - attribute \src "libresoc.v:53357.3-53358.35" + attribute \src "libresoc.v:189795.3-189880.6" + wire width 8 $0\xive1_pri$next[7:0]$14485 + attribute \src "libresoc.v:189775.3-189776.35" wire width 8 $0\xive1_pri[7:0] - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $0\xive2_pri$next[7:0]$2459 - attribute \src "libresoc.v:53359.3-53360.35" + attribute \src "libresoc.v:189795.3-189880.6" + wire width 8 $0\xive2_pri$next[7:0]$14486 + attribute \src "libresoc.v:189777.3-189778.35" wire width 8 $0\xive2_pri[7:0] - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $0\xive3_pri$next[7:0]$2460 - attribute \src "libresoc.v:53361.3-53362.35" + attribute \src "libresoc.v:189795.3-189880.6" + wire width 8 $0\xive3_pri$next[7:0]$14487 + attribute \src "libresoc.v:189779.3-189780.35" wire width 8 $0\xive3_pri[7:0] - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $0\xive4_pri$next[7:0]$2461 - attribute \src "libresoc.v:53363.3-53364.35" + attribute \src "libresoc.v:189795.3-189880.6" + wire width 8 $0\xive4_pri$next[7:0]$14488 + attribute \src "libresoc.v:189781.3-189782.35" wire width 8 $0\xive4_pri[7:0] - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $0\xive5_pri$next[7:0]$2462 - attribute \src "libresoc.v:53365.3-53366.35" + attribute \src "libresoc.v:189795.3-189880.6" + wire width 8 $0\xive5_pri$next[7:0]$14489 + attribute \src "libresoc.v:189783.3-189784.35" wire width 8 $0\xive5_pri[7:0] - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $0\xive6_pri$next[7:0]$2463 - attribute \src "libresoc.v:53367.3-53368.35" + attribute \src "libresoc.v:189795.3-189880.6" + wire width 8 $0\xive6_pri$next[7:0]$14490 + attribute \src "libresoc.v:189785.3-189786.35" wire width 8 $0\xive6_pri[7:0] - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $0\xive7_pri$next[7:0]$2464 - attribute \src "libresoc.v:53369.3-53370.35" + attribute \src "libresoc.v:189795.3-189880.6" + wire width 8 $0\xive7_pri$next[7:0]$14491 + attribute \src "libresoc.v:189787.3-189788.35" wire width 8 $0\xive7_pri[7:0] - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $0\xive8_pri$next[7:0]$2465 - attribute \src "libresoc.v:53371.3-53372.35" + attribute \src "libresoc.v:189795.3-189880.6" + wire width 8 $0\xive8_pri$next[7:0]$14492 + attribute \src "libresoc.v:189789.3-189790.35" wire width 8 $0\xive8_pri[7:0] - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $0\xive9_pri$next[7:0]$2466 - attribute \src "libresoc.v:53373.3-53374.35" + attribute \src "libresoc.v:189795.3-189880.6" + wire width 8 $0\xive9_pri$next[7:0]$14493 + attribute \src "libresoc.v:189791.3-189792.35" wire width 8 $0\xive9_pri[7:0] - attribute \src "libresoc.v:53762.3-53811.6" + attribute \src "libresoc.v:190180.3-190229.6" wire width 32 $1\be_out[31:0] - attribute \src "libresoc.v:53473.3-53482.6" + attribute \src "libresoc.v:189891.3-189900.6" wire width 4 $1\cur_idx0[3:0] - attribute \src "libresoc.v:53682.3-53691.6" + attribute \src "libresoc.v:190100.3-190109.6" wire width 4 $1\cur_idx10[3:0] - attribute \src "libresoc.v:53702.3-53711.6" + attribute \src "libresoc.v:190120.3-190129.6" wire width 4 $1\cur_idx11[3:0] - attribute \src "libresoc.v:53722.3-53731.6" + attribute \src "libresoc.v:190140.3-190149.6" wire width 4 $1\cur_idx12[3:0] - attribute \src "libresoc.v:53742.3-53751.6" + attribute \src "libresoc.v:190160.3-190169.6" wire width 4 $1\cur_idx13[3:0] - attribute \src "libresoc.v:53812.3-53821.6" + attribute \src "libresoc.v:190230.3-190239.6" wire width 4 $1\cur_idx14[3:0] - attribute \src "libresoc.v:53832.3-53841.6" + attribute \src "libresoc.v:190250.3-190259.6" wire width 4 $1\cur_idx15[3:0] - attribute \src "libresoc.v:53493.3-53502.6" + attribute \src "libresoc.v:189911.3-189920.6" wire width 4 $1\cur_idx1[3:0] - attribute \src "libresoc.v:53513.3-53522.6" + attribute \src "libresoc.v:189931.3-189940.6" wire width 4 $1\cur_idx2[3:0] - attribute \src "libresoc.v:53533.3-53542.6" + attribute \src "libresoc.v:189951.3-189960.6" wire width 4 $1\cur_idx3[3:0] - attribute \src "libresoc.v:53562.3-53571.6" + attribute \src "libresoc.v:189980.3-189989.6" wire width 4 $1\cur_idx4[3:0] - attribute \src "libresoc.v:53582.3-53591.6" + attribute \src "libresoc.v:190000.3-190009.6" wire width 4 $1\cur_idx5[3:0] - attribute \src "libresoc.v:53602.3-53611.6" + attribute \src "libresoc.v:190020.3-190029.6" wire width 4 $1\cur_idx6[3:0] - attribute \src "libresoc.v:53622.3-53631.6" + attribute \src "libresoc.v:190040.3-190049.6" wire width 4 $1\cur_idx7[3:0] - attribute \src "libresoc.v:53642.3-53651.6" + attribute \src "libresoc.v:190060.3-190069.6" wire width 4 $1\cur_idx8[3:0] - attribute \src "libresoc.v:53662.3-53671.6" + attribute \src "libresoc.v:190080.3-190089.6" wire width 4 $1\cur_idx9[3:0] - attribute \src "libresoc.v:53463.3-53472.6" + attribute \src "libresoc.v:189881.3-189890.6" wire width 8 $1\cur_pri0[7:0] - attribute \src "libresoc.v:53672.3-53681.6" + attribute \src "libresoc.v:190090.3-190099.6" wire width 8 $1\cur_pri10[7:0] - attribute \src "libresoc.v:53692.3-53701.6" + attribute \src "libresoc.v:190110.3-190119.6" wire width 8 $1\cur_pri11[7:0] - attribute \src "libresoc.v:53712.3-53721.6" + attribute \src "libresoc.v:190130.3-190139.6" wire width 8 $1\cur_pri12[7:0] - attribute \src "libresoc.v:53732.3-53741.6" + attribute \src "libresoc.v:190150.3-190159.6" wire width 8 $1\cur_pri13[7:0] - attribute \src "libresoc.v:53752.3-53761.6" + attribute \src "libresoc.v:190170.3-190179.6" wire width 8 $1\cur_pri14[7:0] - attribute \src "libresoc.v:53822.3-53831.6" + attribute \src "libresoc.v:190240.3-190249.6" wire width 8 $1\cur_pri15[7:0] - attribute \src "libresoc.v:53483.3-53492.6" + attribute \src "libresoc.v:189901.3-189910.6" wire width 8 $1\cur_pri1[7:0] - attribute \src "libresoc.v:53503.3-53512.6" + attribute \src "libresoc.v:189921.3-189930.6" wire width 8 $1\cur_pri2[7:0] - attribute \src "libresoc.v:53523.3-53532.6" + attribute \src "libresoc.v:189941.3-189950.6" wire width 8 $1\cur_pri3[7:0] - attribute \src "libresoc.v:53543.3-53552.6" + attribute \src "libresoc.v:189961.3-189970.6" wire width 8 $1\cur_pri4[7:0] - attribute \src "libresoc.v:53572.3-53581.6" + attribute \src "libresoc.v:189990.3-189999.6" wire width 8 $1\cur_pri5[7:0] - attribute \src "libresoc.v:53592.3-53601.6" + attribute \src "libresoc.v:190010.3-190019.6" wire width 8 $1\cur_pri6[7:0] - attribute \src "libresoc.v:53612.3-53621.6" + attribute \src "libresoc.v:190030.3-190039.6" wire width 8 $1\cur_pri7[7:0] - attribute \src "libresoc.v:53632.3-53641.6" + attribute \src "libresoc.v:190050.3-190059.6" wire width 8 $1\cur_pri8[7:0] - attribute \src "libresoc.v:53652.3-53661.6" + attribute \src "libresoc.v:190070.3-190079.6" wire width 8 $1\cur_pri9[7:0] - attribute \src "libresoc.v:53842.3-53851.6" + attribute \src "libresoc.v:190260.3-190269.6" wire $1\ibit[0:0] - attribute \src "libresoc.v:53114.13-53114.30" + attribute \src "libresoc.v:189532.13-189532.30" wire width 8 $1\icp_o_pri[7:0] - attribute \src "libresoc.v:53119.13-53119.29" + attribute \src "libresoc.v:189537.13-189537.29" wire width 4 $1\icp_o_src[3:0] - attribute \src "libresoc.v:53861.3-53869.6" - wire $1\ics_wb__ack$next[0:0]$2573 - attribute \src "libresoc.v:53128.7-53128.25" + attribute \src "libresoc.v:190279.3-190287.6" + wire $1\ics_wb__ack$next[0:0]$14600 + attribute \src "libresoc.v:189546.7-189546.25" wire $1\ics_wb__ack[0:0] - attribute \src "libresoc.v:53852.3-53860.6" - wire width 32 $1\ics_wb__dat_r$next[31:0]$2570 - attribute \src "libresoc.v:53137.14-53137.35" + attribute \src "libresoc.v:190270.3-190278.6" + wire width 32 $1\ics_wb__dat_r$next[31:0]$14597 + attribute \src "libresoc.v:189555.14-189555.35" wire width 32 $1\ics_wb__dat_r[31:0] - attribute \src "libresoc.v:53553.3-53561.6" - wire width 16 $1\int_level_l$next[15:0]$2542 - attribute \src "libresoc.v:53149.14-53149.36" + attribute \src "libresoc.v:189971.3-189979.6" + wire width 16 $1\int_level_l$next[15:0]$14569 + attribute \src "libresoc.v:189567.14-189567.36" wire width 16 $1\int_level_l[15:0] - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $1\xive0_pri$next[7:0]$2467 - attribute \src "libresoc.v:53169.13-53169.30" + attribute \src "libresoc.v:189795.3-189880.6" + wire width 8 $1\xive0_pri$next[7:0]$14494 + attribute \src "libresoc.v:189587.13-189587.30" wire width 8 $1\xive0_pri[7:0] - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $1\xive10_pri$next[7:0]$2468 - attribute \src "libresoc.v:53173.13-53173.31" + attribute \src "libresoc.v:189795.3-189880.6" + wire width 8 $1\xive10_pri$next[7:0]$14495 + attribute \src "libresoc.v:189591.13-189591.31" wire width 8 $1\xive10_pri[7:0] - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $1\xive11_pri$next[7:0]$2469 - attribute \src "libresoc.v:53177.13-53177.31" + attribute \src "libresoc.v:189795.3-189880.6" + wire width 8 $1\xive11_pri$next[7:0]$14496 + attribute \src "libresoc.v:189595.13-189595.31" wire width 8 $1\xive11_pri[7:0] - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $1\xive12_pri$next[7:0]$2470 - attribute \src "libresoc.v:53181.13-53181.31" + attribute \src "libresoc.v:189795.3-189880.6" + wire width 8 $1\xive12_pri$next[7:0]$14497 + attribute \src "libresoc.v:189599.13-189599.31" wire width 8 $1\xive12_pri[7:0] - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $1\xive13_pri$next[7:0]$2471 - attribute \src "libresoc.v:53185.13-53185.31" + attribute \src "libresoc.v:189795.3-189880.6" + wire width 8 $1\xive13_pri$next[7:0]$14498 + attribute \src "libresoc.v:189603.13-189603.31" wire width 8 $1\xive13_pri[7:0] - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $1\xive14_pri$next[7:0]$2472 - attribute \src "libresoc.v:53189.13-53189.31" + attribute \src "libresoc.v:189795.3-189880.6" + wire width 8 $1\xive14_pri$next[7:0]$14499 + attribute \src "libresoc.v:189607.13-189607.31" wire width 8 $1\xive14_pri[7:0] - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $1\xive15_pri$next[7:0]$2473 - attribute \src "libresoc.v:53193.13-53193.31" + attribute \src "libresoc.v:189795.3-189880.6" + wire width 8 $1\xive15_pri$next[7:0]$14500 + attribute \src "libresoc.v:189611.13-189611.31" wire width 8 $1\xive15_pri[7:0] - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $1\xive1_pri$next[7:0]$2474 - attribute \src "libresoc.v:53197.13-53197.30" + attribute \src "libresoc.v:189795.3-189880.6" + wire width 8 $1\xive1_pri$next[7:0]$14501 + attribute \src "libresoc.v:189615.13-189615.30" wire width 8 $1\xive1_pri[7:0] - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $1\xive2_pri$next[7:0]$2475 - attribute \src "libresoc.v:53201.13-53201.30" + attribute \src "libresoc.v:189795.3-189880.6" + wire width 8 $1\xive2_pri$next[7:0]$14502 + attribute \src "libresoc.v:189619.13-189619.30" wire width 8 $1\xive2_pri[7:0] - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $1\xive3_pri$next[7:0]$2476 - attribute \src "libresoc.v:53205.13-53205.30" + attribute \src "libresoc.v:189795.3-189880.6" + wire width 8 $1\xive3_pri$next[7:0]$14503 + attribute \src "libresoc.v:189623.13-189623.30" wire width 8 $1\xive3_pri[7:0] - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $1\xive4_pri$next[7:0]$2477 - attribute \src "libresoc.v:53209.13-53209.30" + attribute \src "libresoc.v:189795.3-189880.6" + wire width 8 $1\xive4_pri$next[7:0]$14504 + attribute \src "libresoc.v:189627.13-189627.30" wire width 8 $1\xive4_pri[7:0] - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $1\xive5_pri$next[7:0]$2478 - attribute \src "libresoc.v:53213.13-53213.30" + attribute \src "libresoc.v:189795.3-189880.6" + wire width 8 $1\xive5_pri$next[7:0]$14505 + attribute \src "libresoc.v:189631.13-189631.30" wire width 8 $1\xive5_pri[7:0] - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $1\xive6_pri$next[7:0]$2479 - attribute \src "libresoc.v:53217.13-53217.30" + attribute \src "libresoc.v:189795.3-189880.6" + wire width 8 $1\xive6_pri$next[7:0]$14506 + attribute \src "libresoc.v:189635.13-189635.30" wire width 8 $1\xive6_pri[7:0] - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $1\xive7_pri$next[7:0]$2480 - attribute \src "libresoc.v:53221.13-53221.30" + attribute \src "libresoc.v:189795.3-189880.6" + wire width 8 $1\xive7_pri$next[7:0]$14507 + attribute \src "libresoc.v:189639.13-189639.30" wire width 8 $1\xive7_pri[7:0] - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $1\xive8_pri$next[7:0]$2481 - attribute \src "libresoc.v:53225.13-53225.30" + attribute \src "libresoc.v:189795.3-189880.6" + wire width 8 $1\xive8_pri$next[7:0]$14508 + attribute \src "libresoc.v:189643.13-189643.30" wire width 8 $1\xive8_pri[7:0] - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $1\xive9_pri$next[7:0]$2482 - attribute \src "libresoc.v:53229.13-53229.30" + attribute \src "libresoc.v:189795.3-189880.6" + wire width 8 $1\xive9_pri$next[7:0]$14509 + attribute \src "libresoc.v:189647.13-189647.30" wire width 8 $1\xive9_pri[7:0] - attribute \src "libresoc.v:53762.3-53811.6" + attribute \src "libresoc.v:190180.3-190229.6" wire width 32 $2\be_out[31:0] - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $2\xive0_pri$next[7:0]$2483 - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $2\xive10_pri$next[7:0]$2484 - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $2\xive11_pri$next[7:0]$2485 - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $2\xive12_pri$next[7:0]$2486 - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $2\xive13_pri$next[7:0]$2487 - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $2\xive14_pri$next[7:0]$2488 - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $2\xive15_pri$next[7:0]$2489 - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $2\xive1_pri$next[7:0]$2490 - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $2\xive2_pri$next[7:0]$2491 - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $2\xive3_pri$next[7:0]$2492 - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $2\xive4_pri$next[7:0]$2493 - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $2\xive5_pri$next[7:0]$2494 - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $2\xive6_pri$next[7:0]$2495 - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 $2\xive7_pri$next[7:0]$2496 - attribute \src "libresoc.v:53377.3-53462.6" - wire width 8 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+ wire width 8 $ternary$libresoc.v:189715$14418_Y + attribute \src "libresoc.v:189717.18-189717.116" + wire width 8 $ternary$libresoc.v:189717$14420_Y + attribute \src "libresoc.v:189719.18-189719.116" + wire width 8 $ternary$libresoc.v:189719$14422_Y + attribute \src "libresoc.v:189722.18-189722.116" + wire width 8 $ternary$libresoc.v:189722$14425_Y + attribute \src "libresoc.v:189724.18-189724.116" + wire width 8 $ternary$libresoc.v:189724$14427_Y + attribute \src "libresoc.v:189726.18-189726.117" + wire width 8 $ternary$libresoc.v:189726$14429_Y + attribute \src "libresoc.v:189728.18-189728.117" + wire width 8 $ternary$libresoc.v:189728$14431_Y + attribute \src "libresoc.v:189730.18-189730.117" + wire width 8 $ternary$libresoc.v:189730$14433_Y + attribute \src "libresoc.v:189733.18-189733.117" + wire width 8 $ternary$libresoc.v:189733$14436_Y + attribute \src "libresoc.v:189735.18-189735.117" + wire width 8 $ternary$libresoc.v:189735$14438_Y + attribute \src "libresoc.v:189737.18-189737.117" + wire width 8 $ternary$libresoc.v:189737$14440_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" @@ -148156,7 +398727,7 @@ module \xics_ics wire input 7 \ics_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire input 11 \ics_wb__we - attribute \src "libresoc.v:52833.7-52833.15" + attribute \src "libresoc.v:189251.7-189251.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" wire width 16 input 5 \int_level_i @@ -148245,7 +398816,7 @@ module \xics_ics attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive9_pri$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:53234$2328 + cell $and $and$libresoc.v:189652$14355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -148253,10 +398824,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [3] connect \B \$99 - connect \Y $and$libresoc.v:53234$2328_Y + connect \Y $and$libresoc.v:189652$14355_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:53236$2330 + cell $and $and$libresoc.v:189654$14357 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -148264,10 +398835,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [3] connect \B \$103 - connect \Y $and$libresoc.v:53236$2330_Y + connect \Y $and$libresoc.v:189654$14357_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:53238$2332 + cell $and $and$libresoc.v:189656$14359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -148275,10 +398846,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [4] connect \B \$107 - connect \Y $and$libresoc.v:53238$2332_Y + connect \Y $and$libresoc.v:189656$14359_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:53240$2334 + cell $and $and$libresoc.v:189658$14361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -148286,10 +398857,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [4] connect \B \$111 - connect \Y $and$libresoc.v:53240$2334_Y + connect \Y $and$libresoc.v:189658$14361_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:53242$2336 + cell $and $and$libresoc.v:189660$14363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -148297,10 +398868,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [5] connect \B \$115 - connect \Y $and$libresoc.v:53242$2336_Y + connect \Y $and$libresoc.v:189660$14363_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:53244$2338 + cell $and $and$libresoc.v:189662$14365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -148308,10 +398879,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [5] connect \B \$119 - connect \Y $and$libresoc.v:53244$2338_Y + connect \Y $and$libresoc.v:189662$14365_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:53246$2340 + cell $and $and$libresoc.v:189664$14367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -148319,10 +398890,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [6] connect \B \$123 - connect \Y $and$libresoc.v:53246$2340_Y + connect \Y $and$libresoc.v:189664$14367_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:53249$2343 + cell $and $and$libresoc.v:189667$14370 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -148330,10 +398901,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [6] connect \B \$127 - connect \Y $and$libresoc.v:53249$2343_Y + connect \Y $and$libresoc.v:189667$14370_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:53251$2345 + cell $and $and$libresoc.v:189669$14372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -148341,10 +398912,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [7] connect \B \$131 - connect \Y $and$libresoc.v:53251$2345_Y + connect \Y $and$libresoc.v:189669$14372_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:53253$2347 + cell $and $and$libresoc.v:189671$14374 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -148352,10 +398923,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [7] connect \B \$135 - connect \Y $and$libresoc.v:53253$2347_Y + connect \Y $and$libresoc.v:189671$14374_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:53256$2350 + cell $and $and$libresoc.v:189674$14377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -148363,10 +398934,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [8] connect \B \$139 - connect \Y $and$libresoc.v:53256$2350_Y + connect \Y $and$libresoc.v:189674$14377_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:53258$2352 + cell $and $and$libresoc.v:189676$14379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -148374,10 +398945,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [8] connect \B \$143 - connect \Y $and$libresoc.v:53258$2352_Y + connect \Y $and$libresoc.v:189676$14379_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:53260$2354 + cell $and $and$libresoc.v:189678$14381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -148385,10 +398956,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [9] connect \B \$147 - connect \Y $and$libresoc.v:53260$2354_Y + connect \Y $and$libresoc.v:189678$14381_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:53262$2356 + cell $and $and$libresoc.v:189680$14383 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -148396,10 +398967,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [9] connect \B \$151 - connect \Y $and$libresoc.v:53262$2356_Y + connect \Y $and$libresoc.v:189680$14383_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:53264$2358 + cell $and $and$libresoc.v:189682$14385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -148407,10 +398978,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [10] connect \B \$155 - connect \Y $and$libresoc.v:53264$2358_Y + connect \Y $and$libresoc.v:189682$14385_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:53266$2360 + cell $and $and$libresoc.v:189684$14387 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -148418,10 +398989,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [10] connect \B \$159 - connect \Y $and$libresoc.v:53266$2360_Y + connect \Y $and$libresoc.v:189684$14387_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:53268$2362 + cell $and $and$libresoc.v:189686$14389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -148429,10 +399000,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [11] connect \B \$163 - connect \Y $and$libresoc.v:53268$2362_Y + connect \Y $and$libresoc.v:189686$14389_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:53271$2365 + cell $and $and$libresoc.v:189689$14392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -148440,10 +399011,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [11] connect \B \$167 - connect \Y $and$libresoc.v:53271$2365_Y + connect \Y $and$libresoc.v:189689$14392_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:53273$2367 + cell $and $and$libresoc.v:189691$14394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -148451,10 +399022,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [12] connect \B \$171 - connect \Y $and$libresoc.v:53273$2367_Y + connect \Y $and$libresoc.v:189691$14394_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:53275$2369 + cell $and $and$libresoc.v:189693$14396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -148462,10 +399033,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [12] connect \B \$175 - connect \Y $and$libresoc.v:53275$2369_Y + connect \Y $and$libresoc.v:189693$14396_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:53278$2372 + cell $and $and$libresoc.v:189696$14399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -148473,10 +399044,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [13] connect \B \$179 - connect \Y $and$libresoc.v:53278$2372_Y + connect \Y $and$libresoc.v:189696$14399_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:53280$2374 + cell $and $and$libresoc.v:189698$14401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -148484,10 +399055,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [13] connect \B \$183 - connect \Y $and$libresoc.v:53280$2374_Y + connect \Y $and$libresoc.v:189698$14401_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:53282$2376 + cell $and $and$libresoc.v:189700$14403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -148495,10 +399066,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [14] connect \B \$187 - connect \Y $and$libresoc.v:53282$2376_Y + connect \Y $and$libresoc.v:189700$14403_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:53284$2378 + cell $and $and$libresoc.v:189702$14405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -148506,10 +399077,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [14] connect \B \$191 - connect \Y $and$libresoc.v:53284$2378_Y + connect \Y $and$libresoc.v:189702$14405_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:53286$2380 + cell $and $and$libresoc.v:189704$14407 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -148517,10 +399088,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [15] connect \B \$195 - connect \Y $and$libresoc.v:53286$2380_Y + connect \Y $and$libresoc.v:189704$14407_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:53289$2383 + cell $and $and$libresoc.v:189707$14410 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -148528,10 +399099,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [15] connect \B \$199 - connect \Y $and$libresoc.v:53289$2383_Y + connect \Y $and$libresoc.v:189707$14410_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:304" - cell $and $and$libresoc.v:53313$2407 + cell $and $and$libresoc.v:189731$14434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -148539,10 +399110,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__cyc connect \B \ics_wb__stb - connect \Y $and$libresoc.v:53313$2407_Y + connect \Y $and$libresoc.v:189731$14434_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341" - cell $and $and$libresoc.v:53321$2415 + cell $and $and$libresoc.v:189739$14442 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -148550,10 +399121,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \wb_valid connect \B \ics_wb__we - connect \Y $and$libresoc.v:53321$2415_Y + connect \Y $and$libresoc.v:189739$14442_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:53323$2417 + cell $and $and$libresoc.v:189741$14444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -148561,10 +399132,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [0] connect \B \$75 - connect \Y $and$libresoc.v:53323$2417_Y + connect \Y $and$libresoc.v:189741$14444_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:53325$2419 + cell $and $and$libresoc.v:189743$14446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -148572,10 +399143,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [0] connect \B \$79 - connect \Y $and$libresoc.v:53325$2419_Y + connect \Y $and$libresoc.v:189743$14446_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:53327$2421 + cell $and $and$libresoc.v:189745$14448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -148583,10 +399154,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [1] connect \B \$83 - connect \Y $and$libresoc.v:53327$2421_Y + connect \Y $and$libresoc.v:189745$14448_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:53330$2424 + cell $and $and$libresoc.v:189748$14451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -148594,10 +399165,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [1] connect \B \$87 - connect \Y $and$libresoc.v:53330$2424_Y + connect \Y $and$libresoc.v:189748$14451_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:53332$2426 + cell $and $and$libresoc.v:189750$14453 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -148605,10 +399176,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [2] connect \B \$91 - connect \Y $and$libresoc.v:53332$2426_Y + connect \Y $and$libresoc.v:189750$14453_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:53334$2428 + cell $and $and$libresoc.v:189752$14455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -148616,10 +399187,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [2] connect \B \$95 - connect \Y $and$libresoc.v:53334$2428_Y + connect \Y $and$libresoc.v:189752$14455_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:53248$2342 + cell $eq $eq$libresoc.v:189666$14369 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -148627,10 +399198,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:53248$2342_Y + connect \Y $eq$libresoc.v:189666$14369_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:53270$2364 + cell $eq $eq$libresoc.v:189688$14391 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -148638,10 +399209,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:53270$2364_Y + connect \Y $eq$libresoc.v:189688$14391_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" - cell $eq $eq$libresoc.v:53287$2381 + cell $eq $eq$libresoc.v:189705$14408 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -148649,10 +399220,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__adr [9:0] connect \B 1'0 - connect \Y $eq$libresoc.v:53287$2381_Y + connect \Y $eq$libresoc.v:189705$14408_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:53290$2384 + cell $eq $eq$libresoc.v:189708$14411 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -148660,10 +399231,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \cur_pri15 connect \B 8'11111111 - connect \Y $eq$libresoc.v:53290$2384_Y + connect \Y $eq$libresoc.v:189708$14411_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:53292$2386 + cell $eq $eq$libresoc.v:189710$14413 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -148671,10 +399242,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:53292$2386_Y + connect \Y $eq$libresoc.v:189710$14413_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:53294$2388 + cell $eq $eq$libresoc.v:189712$14415 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -148682,10 +399253,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:53294$2388_Y + connect \Y $eq$libresoc.v:189712$14415_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:53296$2390 + cell $eq $eq$libresoc.v:189714$14417 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -148693,10 +399264,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:53296$2390_Y + connect \Y $eq$libresoc.v:189714$14417_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:53298$2392 + cell $eq $eq$libresoc.v:189716$14419 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -148704,10 +399275,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:53298$2392_Y + connect \Y $eq$libresoc.v:189716$14419_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:53300$2394 + cell $eq $eq$libresoc.v:189718$14421 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -148715,10 +399286,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:53300$2394_Y + connect \Y $eq$libresoc.v:189718$14421_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:294" - cell $eq $eq$libresoc.v:53302$2396 + cell $eq $eq$libresoc.v:189720$14423 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -148726,10 +399297,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__adr [9:0] connect \B 3'100 - connect \Y $eq$libresoc.v:53302$2396_Y + connect \Y $eq$libresoc.v:189720$14423_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:53303$2397 + cell $eq $eq$libresoc.v:189721$14424 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -148737,10 +399308,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:53303$2397_Y + connect \Y $eq$libresoc.v:189721$14424_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:53305$2399 + cell $eq $eq$libresoc.v:189723$14426 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -148748,10 +399319,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:53305$2399_Y + connect \Y $eq$libresoc.v:189723$14426_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:53307$2401 + cell $eq $eq$libresoc.v:189725$14428 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -148759,10 +399330,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:53307$2401_Y + connect \Y $eq$libresoc.v:189725$14428_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:53309$2403 + cell $eq $eq$libresoc.v:189727$14430 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -148770,10 +399341,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:53309$2403_Y + connect \Y $eq$libresoc.v:189727$14430_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:53311$2405 + cell $eq $eq$libresoc.v:189729$14432 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -148781,10 +399352,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:53311$2405_Y + connect \Y $eq$libresoc.v:189729$14432_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:53314$2408 + cell $eq $eq$libresoc.v:189732$14435 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -148792,10 +399363,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:53314$2408_Y + connect \Y $eq$libresoc.v:189732$14435_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:53316$2410 + cell $eq $eq$libresoc.v:189734$14437 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -148803,10 +399374,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:53316$2410_Y + connect \Y $eq$libresoc.v:189734$14437_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:53318$2412 + cell $eq $eq$libresoc.v:189736$14439 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -148814,10 +399385,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:53318$2412_Y + connect \Y $eq$libresoc.v:189736$14439_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:53329$2423 + cell $eq $eq$libresoc.v:189747$14450 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -148825,10 +399396,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:53329$2423_Y + connect \Y $eq$libresoc.v:189747$14450_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:53233$2327 + cell $lt $lt$libresoc.v:189651$14354 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -148836,10 +399407,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B \cur_pri2 - connect \Y $lt$libresoc.v:53233$2327_Y + connect \Y $lt$libresoc.v:189651$14354_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:53235$2329 + cell $lt $lt$libresoc.v:189653$14356 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -148847,10 +399418,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B \cur_pri2 - connect \Y $lt$libresoc.v:53235$2329_Y + connect \Y $lt$libresoc.v:189653$14356_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:53237$2331 + cell $lt $lt$libresoc.v:189655$14358 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -148858,10 +399429,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B \cur_pri3 - connect \Y $lt$libresoc.v:53237$2331_Y + connect \Y $lt$libresoc.v:189655$14358_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:53239$2333 + cell $lt $lt$libresoc.v:189657$14360 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -148869,10 +399440,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B \cur_pri3 - connect \Y $lt$libresoc.v:53239$2333_Y + connect \Y $lt$libresoc.v:189657$14360_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:53241$2335 + cell $lt $lt$libresoc.v:189659$14362 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -148880,10 +399451,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B \cur_pri4 - connect \Y $lt$libresoc.v:53241$2335_Y + connect \Y $lt$libresoc.v:189659$14362_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:53243$2337 + cell $lt $lt$libresoc.v:189661$14364 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -148891,10 +399462,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B \cur_pri4 - connect \Y $lt$libresoc.v:53243$2337_Y + connect \Y $lt$libresoc.v:189661$14364_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:53245$2339 + cell $lt $lt$libresoc.v:189663$14366 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -148902,10 +399473,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B \cur_pri5 - connect \Y $lt$libresoc.v:53245$2339_Y + connect \Y $lt$libresoc.v:189663$14366_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:53247$2341 + cell $lt $lt$libresoc.v:189665$14368 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -148913,10 +399484,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B \cur_pri5 - connect \Y $lt$libresoc.v:53247$2341_Y + connect \Y $lt$libresoc.v:189665$14368_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:53250$2344 + cell $lt $lt$libresoc.v:189668$14371 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -148924,10 +399495,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B \cur_pri6 - connect \Y $lt$libresoc.v:53250$2344_Y + connect \Y $lt$libresoc.v:189668$14371_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:53252$2346 + cell $lt $lt$libresoc.v:189670$14373 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -148935,10 +399506,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B \cur_pri6 - connect \Y $lt$libresoc.v:53252$2346_Y + connect \Y $lt$libresoc.v:189670$14373_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:53255$2349 + cell $lt $lt$libresoc.v:189673$14376 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -148946,10 +399517,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B \cur_pri7 - connect \Y $lt$libresoc.v:53255$2349_Y + connect \Y $lt$libresoc.v:189673$14376_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:53257$2351 + cell $lt $lt$libresoc.v:189675$14378 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -148957,10 +399528,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B \cur_pri7 - connect \Y $lt$libresoc.v:53257$2351_Y + connect \Y $lt$libresoc.v:189675$14378_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:53259$2353 + cell $lt $lt$libresoc.v:189677$14380 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -148968,10 +399539,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B \cur_pri8 - connect \Y $lt$libresoc.v:53259$2353_Y + connect \Y $lt$libresoc.v:189677$14380_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:53261$2355 + cell $lt $lt$libresoc.v:189679$14382 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -148979,10 +399550,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B \cur_pri8 - connect \Y $lt$libresoc.v:53261$2355_Y + connect \Y $lt$libresoc.v:189679$14382_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:53263$2357 + cell $lt $lt$libresoc.v:189681$14384 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -148990,10 +399561,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B \cur_pri9 - connect \Y $lt$libresoc.v:53263$2357_Y + connect \Y $lt$libresoc.v:189681$14384_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:53265$2359 + cell $lt $lt$libresoc.v:189683$14386 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -149001,10 +399572,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B \cur_pri9 - connect \Y $lt$libresoc.v:53265$2359_Y + connect \Y $lt$libresoc.v:189683$14386_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:53267$2361 + cell $lt $lt$libresoc.v:189685$14388 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -149012,10 +399583,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B \cur_pri10 - connect \Y $lt$libresoc.v:53267$2361_Y + connect \Y $lt$libresoc.v:189685$14388_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:53269$2363 + cell $lt $lt$libresoc.v:189687$14390 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -149023,10 +399594,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B \cur_pri10 - connect \Y $lt$libresoc.v:53269$2363_Y + connect \Y $lt$libresoc.v:189687$14390_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:53272$2366 + cell $lt $lt$libresoc.v:189690$14393 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -149034,10 +399605,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B \cur_pri11 - connect \Y $lt$libresoc.v:53272$2366_Y + connect \Y $lt$libresoc.v:189690$14393_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:53274$2368 + cell $lt $lt$libresoc.v:189692$14395 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -149045,10 +399616,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B \cur_pri11 - connect \Y $lt$libresoc.v:53274$2368_Y + connect \Y $lt$libresoc.v:189692$14395_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:53277$2371 + cell $lt $lt$libresoc.v:189695$14398 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -149056,10 +399627,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B \cur_pri12 - connect \Y $lt$libresoc.v:53277$2371_Y + connect \Y $lt$libresoc.v:189695$14398_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:53279$2373 + cell $lt $lt$libresoc.v:189697$14400 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -149067,10 +399638,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B \cur_pri12 - connect \Y $lt$libresoc.v:53279$2373_Y + connect \Y $lt$libresoc.v:189697$14400_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:53281$2375 + cell $lt $lt$libresoc.v:189699$14402 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -149078,10 +399649,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B \cur_pri13 - connect \Y $lt$libresoc.v:53281$2375_Y + connect \Y $lt$libresoc.v:189699$14402_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:53283$2377 + cell $lt $lt$libresoc.v:189701$14404 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -149089,10 +399660,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B \cur_pri13 - connect \Y $lt$libresoc.v:53283$2377_Y + connect \Y $lt$libresoc.v:189701$14404_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:53285$2379 + cell $lt $lt$libresoc.v:189703$14406 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -149100,10 +399671,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B \cur_pri14 - connect \Y $lt$libresoc.v:53285$2379_Y + connect \Y $lt$libresoc.v:189703$14406_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:53288$2382 + cell $lt $lt$libresoc.v:189706$14409 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -149111,10 +399682,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B \cur_pri14 - connect \Y $lt$libresoc.v:53288$2382_Y + connect \Y $lt$libresoc.v:189706$14409_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:53322$2416 + cell $lt $lt$libresoc.v:189740$14443 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -149122,10 +399693,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B \max_pri - connect \Y $lt$libresoc.v:53322$2416_Y + connect \Y $lt$libresoc.v:189740$14443_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:53324$2418 + cell $lt $lt$libresoc.v:189742$14445 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -149133,10 +399704,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B \max_pri - connect \Y $lt$libresoc.v:53324$2418_Y + connect \Y $lt$libresoc.v:189742$14445_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:53326$2420 + cell $lt $lt$libresoc.v:189744$14447 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -149144,10 +399715,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B \cur_pri0 - connect \Y $lt$libresoc.v:53326$2420_Y + connect \Y $lt$libresoc.v:189744$14447_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:53328$2422 + cell $lt $lt$libresoc.v:189746$14449 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -149155,10 +399726,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B \cur_pri0 - connect \Y $lt$libresoc.v:53328$2422_Y + connect \Y $lt$libresoc.v:189746$14449_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:53331$2425 + cell $lt $lt$libresoc.v:189749$14452 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -149166,10 +399737,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B \cur_pri1 - connect \Y $lt$libresoc.v:53331$2425_Y + connect \Y $lt$libresoc.v:189749$14452_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:53333$2427 + cell $lt $lt$libresoc.v:189751$14454 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -149177,10 +399748,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B \cur_pri1 - connect \Y $lt$libresoc.v:53333$2427_Y + connect \Y $lt$libresoc.v:189751$14454_Y end - attribute \src "libresoc.v:53320.18-53320.40" - cell $shr $shr$libresoc.v:53320$2414 + attribute \src "libresoc.v:189738.18-189738.40" + cell $shr $shr$libresoc.v:189738$14441 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -149188,469 +399759,469 @@ module \xics_ics parameter \Y_WIDTH 16 connect \A \int_level_l connect \B \reg_idx - connect \Y $shr$libresoc.v:53320$2414_Y + connect \Y $shr$libresoc.v:189738$14441_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:53232$2326 + cell $mux $ternary$libresoc.v:189650$14353 parameter \WIDTH 8 connect \A \xive0_pri connect \B 8'11111111 connect \S \$8 - connect \Y $ternary$libresoc.v:53232$2326_Y + connect \Y $ternary$libresoc.v:189650$14353_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:53254$2348 + cell $mux $ternary$libresoc.v:189672$14375 parameter \WIDTH 8 connect \A \xive1_pri connect \B 8'11111111 connect \S \$12 - connect \Y $ternary$libresoc.v:53254$2348_Y + connect \Y $ternary$libresoc.v:189672$14375_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:53276$2370 + cell $mux $ternary$libresoc.v:189694$14397 parameter \WIDTH 8 connect \A \xive2_pri connect \B 8'11111111 connect \S \$16 - connect \Y $ternary$libresoc.v:53276$2370_Y + connect \Y $ternary$libresoc.v:189694$14397_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:53291$2385 + cell $mux $ternary$libresoc.v:189709$14412 parameter \WIDTH 8 connect \A \cur_pri15 connect \B 8'11111111 connect \S \$204 - connect \Y $ternary$libresoc.v:53291$2385_Y + connect \Y $ternary$libresoc.v:189709$14412_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:53293$2387 + cell $mux $ternary$libresoc.v:189711$14414 parameter \WIDTH 8 connect \A \xive3_pri connect \B 8'11111111 connect \S \$20 - connect \Y $ternary$libresoc.v:53293$2387_Y + connect \Y $ternary$libresoc.v:189711$14414_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:53295$2389 + cell $mux $ternary$libresoc.v:189713$14416 parameter \WIDTH 8 connect \A \xive4_pri connect \B 8'11111111 connect \S \$24 - connect \Y $ternary$libresoc.v:53295$2389_Y + connect \Y $ternary$libresoc.v:189713$14416_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:53297$2391 + cell $mux $ternary$libresoc.v:189715$14418 parameter \WIDTH 8 connect \A \xive5_pri connect \B 8'11111111 connect \S \$28 - connect \Y $ternary$libresoc.v:53297$2391_Y + connect \Y $ternary$libresoc.v:189715$14418_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:53299$2393 + cell $mux $ternary$libresoc.v:189717$14420 parameter \WIDTH 8 connect \A \xive6_pri connect \B 8'11111111 connect \S \$32 - connect \Y $ternary$libresoc.v:53299$2393_Y + connect \Y $ternary$libresoc.v:189717$14420_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:53301$2395 + cell $mux $ternary$libresoc.v:189719$14422 parameter \WIDTH 8 connect \A \xive7_pri connect \B 8'11111111 connect \S \$36 - connect \Y $ternary$libresoc.v:53301$2395_Y + connect \Y $ternary$libresoc.v:189719$14422_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:53304$2398 + cell $mux $ternary$libresoc.v:189722$14425 parameter \WIDTH 8 connect \A \xive8_pri connect \B 8'11111111 connect \S \$40 - connect \Y $ternary$libresoc.v:53304$2398_Y + connect \Y $ternary$libresoc.v:189722$14425_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:53306$2400 + cell $mux $ternary$libresoc.v:189724$14427 parameter \WIDTH 8 connect \A \xive9_pri connect \B 8'11111111 connect \S \$44 - connect \Y $ternary$libresoc.v:53306$2400_Y + connect \Y $ternary$libresoc.v:189724$14427_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:53308$2402 + cell $mux $ternary$libresoc.v:189726$14429 parameter \WIDTH 8 connect \A \xive10_pri connect \B 8'11111111 connect \S \$48 - connect \Y $ternary$libresoc.v:53308$2402_Y + connect \Y $ternary$libresoc.v:189726$14429_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:53310$2404 + cell $mux $ternary$libresoc.v:189728$14431 parameter \WIDTH 8 connect \A \xive11_pri connect \B 8'11111111 connect \S \$52 - connect \Y $ternary$libresoc.v:53310$2404_Y + connect \Y $ternary$libresoc.v:189728$14431_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:53312$2406 + cell $mux $ternary$libresoc.v:189730$14433 parameter \WIDTH 8 connect \A \xive12_pri connect \B 8'11111111 connect \S \$56 - connect \Y $ternary$libresoc.v:53312$2406_Y + connect \Y $ternary$libresoc.v:189730$14433_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:53315$2409 + cell $mux $ternary$libresoc.v:189733$14436 parameter \WIDTH 8 connect \A \xive13_pri connect \B 8'11111111 connect \S \$60 - connect \Y $ternary$libresoc.v:53315$2409_Y + connect \Y $ternary$libresoc.v:189733$14436_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:53317$2411 + cell $mux $ternary$libresoc.v:189735$14438 parameter \WIDTH 8 connect \A \xive14_pri connect \B 8'11111111 connect \S \$64 - connect \Y $ternary$libresoc.v:53317$2411_Y + connect \Y $ternary$libresoc.v:189735$14438_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:53319$2413 + cell $mux $ternary$libresoc.v:189737$14440 parameter \WIDTH 8 connect \A \xive15_pri connect \B 8'11111111 connect \S \$68 - connect \Y $ternary$libresoc.v:53319$2413_Y + connect \Y $ternary$libresoc.v:189737$14440_Y end - attribute \src "libresoc.v:52833.7-52833.20" - process $proc$libresoc.v:52833$2574 + attribute \src "libresoc.v:189251.7-189251.20" + process $proc$libresoc.v:189251$14601 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:53114.13-53114.30" - process $proc$libresoc.v:53114$2575 + attribute \src "libresoc.v:189532.13-189532.30" + process $proc$libresoc.v:189532$14602 assign { } { } assign $1\icp_o_pri[7:0] 8'00000000 sync always sync init update \icp_o_pri $1\icp_o_pri[7:0] end - attribute \src "libresoc.v:53119.13-53119.29" - process $proc$libresoc.v:53119$2576 + attribute \src "libresoc.v:189537.13-189537.29" + process $proc$libresoc.v:189537$14603 assign { } { } assign $1\icp_o_src[3:0] 4'0000 sync always sync init update \icp_o_src $1\icp_o_src[3:0] end - attribute \src "libresoc.v:53128.7-53128.25" - process $proc$libresoc.v:53128$2577 + attribute \src "libresoc.v:189546.7-189546.25" + process $proc$libresoc.v:189546$14604 assign { } { } assign $1\ics_wb__ack[0:0] 1'0 sync always sync init update \ics_wb__ack $1\ics_wb__ack[0:0] end - attribute \src "libresoc.v:53137.14-53137.35" - process $proc$libresoc.v:53137$2578 + attribute \src "libresoc.v:189555.14-189555.35" + process $proc$libresoc.v:189555$14605 assign { } { } assign $1\ics_wb__dat_r[31:0] 0 sync always sync init update \ics_wb__dat_r $1\ics_wb__dat_r[31:0] end - attribute \src "libresoc.v:53149.14-53149.36" - process $proc$libresoc.v:53149$2579 + attribute \src "libresoc.v:189567.14-189567.36" + process $proc$libresoc.v:189567$14606 assign { } { } assign $1\int_level_l[15:0] 16'0000000000000000 sync always sync init update \int_level_l $1\int_level_l[15:0] end - attribute \src "libresoc.v:53169.13-53169.30" - process $proc$libresoc.v:53169$2580 + attribute \src "libresoc.v:189587.13-189587.30" + process $proc$libresoc.v:189587$14607 assign { } { } assign $1\xive0_pri[7:0] 8'11111111 sync always sync init update \xive0_pri $1\xive0_pri[7:0] end - attribute \src "libresoc.v:53173.13-53173.31" - process $proc$libresoc.v:53173$2581 + attribute \src "libresoc.v:189591.13-189591.31" + process $proc$libresoc.v:189591$14608 assign { } { } assign $1\xive10_pri[7:0] 8'11111111 sync always sync init update \xive10_pri $1\xive10_pri[7:0] end - attribute \src "libresoc.v:53177.13-53177.31" - process $proc$libresoc.v:53177$2582 + attribute \src "libresoc.v:189595.13-189595.31" + process $proc$libresoc.v:189595$14609 assign { } { } assign $1\xive11_pri[7:0] 8'11111111 sync always sync init update \xive11_pri $1\xive11_pri[7:0] end - attribute \src "libresoc.v:53181.13-53181.31" - process $proc$libresoc.v:53181$2583 + attribute \src "libresoc.v:189599.13-189599.31" + process $proc$libresoc.v:189599$14610 assign { } { } assign $1\xive12_pri[7:0] 8'11111111 sync always sync init update \xive12_pri $1\xive12_pri[7:0] end - attribute \src "libresoc.v:53185.13-53185.31" - process $proc$libresoc.v:53185$2584 + attribute \src "libresoc.v:189603.13-189603.31" + process $proc$libresoc.v:189603$14611 assign { } { } assign $1\xive13_pri[7:0] 8'11111111 sync always sync init update \xive13_pri $1\xive13_pri[7:0] end - attribute \src "libresoc.v:53189.13-53189.31" - process $proc$libresoc.v:53189$2585 + attribute \src "libresoc.v:189607.13-189607.31" + process $proc$libresoc.v:189607$14612 assign { } { } assign $1\xive14_pri[7:0] 8'11111111 sync always sync init update \xive14_pri $1\xive14_pri[7:0] end - attribute \src "libresoc.v:53193.13-53193.31" - process $proc$libresoc.v:53193$2586 + attribute \src "libresoc.v:189611.13-189611.31" + process $proc$libresoc.v:189611$14613 assign { } { } assign $1\xive15_pri[7:0] 8'11111111 sync always sync init update \xive15_pri $1\xive15_pri[7:0] end - attribute \src "libresoc.v:53197.13-53197.30" - process $proc$libresoc.v:53197$2587 + attribute \src "libresoc.v:189615.13-189615.30" + process $proc$libresoc.v:189615$14614 assign { } { } assign $1\xive1_pri[7:0] 8'11111111 sync always sync init update \xive1_pri $1\xive1_pri[7:0] end - attribute \src "libresoc.v:53201.13-53201.30" - process $proc$libresoc.v:53201$2588 + attribute \src "libresoc.v:189619.13-189619.30" + process $proc$libresoc.v:189619$14615 assign { } { } assign $1\xive2_pri[7:0] 8'11111111 sync always sync init update \xive2_pri $1\xive2_pri[7:0] end - attribute \src "libresoc.v:53205.13-53205.30" - process $proc$libresoc.v:53205$2589 + attribute \src "libresoc.v:189623.13-189623.30" + process $proc$libresoc.v:189623$14616 assign { } { } assign $1\xive3_pri[7:0] 8'11111111 sync always sync init update \xive3_pri $1\xive3_pri[7:0] end - attribute \src "libresoc.v:53209.13-53209.30" - process $proc$libresoc.v:53209$2590 + attribute \src "libresoc.v:189627.13-189627.30" + process $proc$libresoc.v:189627$14617 assign { } { } assign $1\xive4_pri[7:0] 8'11111111 sync always sync init update \xive4_pri $1\xive4_pri[7:0] end - attribute \src "libresoc.v:53213.13-53213.30" - process $proc$libresoc.v:53213$2591 + attribute \src "libresoc.v:189631.13-189631.30" + process $proc$libresoc.v:189631$14618 assign { } { } assign $1\xive5_pri[7:0] 8'11111111 sync always sync init update \xive5_pri $1\xive5_pri[7:0] end - attribute \src "libresoc.v:53217.13-53217.30" - process $proc$libresoc.v:53217$2592 + attribute \src "libresoc.v:189635.13-189635.30" + process $proc$libresoc.v:189635$14619 assign { } { } assign $1\xive6_pri[7:0] 8'11111111 sync always sync init update \xive6_pri $1\xive6_pri[7:0] end - attribute \src "libresoc.v:53221.13-53221.30" - process $proc$libresoc.v:53221$2593 + attribute \src "libresoc.v:189639.13-189639.30" + process $proc$libresoc.v:189639$14620 assign { } { } assign $1\xive7_pri[7:0] 8'11111111 sync always sync init update \xive7_pri $1\xive7_pri[7:0] end - attribute \src "libresoc.v:53225.13-53225.30" - process $proc$libresoc.v:53225$2594 + attribute \src "libresoc.v:189643.13-189643.30" + process $proc$libresoc.v:189643$14621 assign { } { } assign $1\xive8_pri[7:0] 8'11111111 sync always sync init update \xive8_pri $1\xive8_pri[7:0] end - attribute \src "libresoc.v:53229.13-53229.30" - process $proc$libresoc.v:53229$2595 + attribute \src "libresoc.v:189647.13-189647.30" + process $proc$libresoc.v:189647$14622 assign { } { } assign $1\xive9_pri[7:0] 8'11111111 sync always sync init update \xive9_pri $1\xive9_pri[7:0] end - attribute \src "libresoc.v:53335.3-53336.37" - process $proc$libresoc.v:53335$2429 + attribute \src "libresoc.v:189753.3-189754.37" + process $proc$libresoc.v:189753$14456 assign { } { } assign $0\xive11_pri[7:0] \xive11_pri$next sync posedge \clk update \xive11_pri $0\xive11_pri[7:0] end - attribute \src "libresoc.v:53337.3-53338.37" - process $proc$libresoc.v:53337$2430 + attribute \src "libresoc.v:189755.3-189756.37" + process $proc$libresoc.v:189755$14457 assign { } { } assign $0\xive12_pri[7:0] \xive12_pri$next sync posedge \clk update \xive12_pri $0\xive12_pri[7:0] end - attribute \src "libresoc.v:53339.3-53340.37" - process $proc$libresoc.v:53339$2431 + attribute \src "libresoc.v:189757.3-189758.37" + process $proc$libresoc.v:189757$14458 assign { } { } assign $0\xive13_pri[7:0] \xive13_pri$next sync posedge \clk update \xive13_pri $0\xive13_pri[7:0] end - attribute \src "libresoc.v:53341.3-53342.37" - process $proc$libresoc.v:53341$2432 + attribute \src "libresoc.v:189759.3-189760.37" + process $proc$libresoc.v:189759$14459 assign { } { } assign $0\xive14_pri[7:0] \xive14_pri$next sync posedge \clk update \xive14_pri $0\xive14_pri[7:0] end - attribute \src "libresoc.v:53343.3-53344.37" - process $proc$libresoc.v:53343$2433 + attribute \src "libresoc.v:189761.3-189762.37" + process $proc$libresoc.v:189761$14460 assign { } { } assign $0\xive15_pri[7:0] \xive15_pri$next sync posedge \clk update \xive15_pri $0\xive15_pri[7:0] end - attribute \src "libresoc.v:53345.3-53346.39" - process $proc$libresoc.v:53345$2434 + attribute \src "libresoc.v:189763.3-189764.39" + process $proc$libresoc.v:189763$14461 assign { } { } assign $0\ics_wb__ack[0:0] \ics_wb__ack$next sync posedge \clk update \ics_wb__ack $0\ics_wb__ack[0:0] end - attribute \src "libresoc.v:53347.3-53348.43" - process $proc$libresoc.v:53347$2435 + attribute \src "libresoc.v:189765.3-189766.43" + process $proc$libresoc.v:189765$14462 assign { } { } assign $0\ics_wb__dat_r[31:0] \ics_wb__dat_r$next sync posedge \clk update \ics_wb__dat_r $0\ics_wb__dat_r[31:0] end - attribute \src "libresoc.v:53349.3-53350.39" - process $proc$libresoc.v:53349$2436 + attribute \src "libresoc.v:189767.3-189768.39" + process $proc$libresoc.v:189767$14463 assign { } { } assign $0\int_level_l[15:0] \int_level_l$next sync posedge \clk update \int_level_l $0\int_level_l[15:0] end - attribute \src "libresoc.v:53351.3-53352.28" - process $proc$libresoc.v:53351$2437 + attribute \src "libresoc.v:189769.3-189770.28" + process $proc$libresoc.v:189769$14464 assign { } { } assign $0\icp_o_src[3:0] \cur_idx15 sync posedge \clk update \icp_o_src $0\icp_o_src[3:0] end - attribute \src "libresoc.v:53353.3-53354.25" - process $proc$libresoc.v:53353$2438 + attribute \src "libresoc.v:189771.3-189772.25" + process $proc$libresoc.v:189771$14465 assign { } { } assign $0\icp_o_pri[7:0] \$203 sync posedge \clk update \icp_o_pri $0\icp_o_pri[7:0] end - attribute \src "libresoc.v:53355.3-53356.35" - process $proc$libresoc.v:53355$2439 + attribute \src "libresoc.v:189773.3-189774.35" + process $proc$libresoc.v:189773$14466 assign { } { } assign $0\xive0_pri[7:0] \xive0_pri$next sync posedge \clk update \xive0_pri $0\xive0_pri[7:0] end - attribute \src "libresoc.v:53357.3-53358.35" - process $proc$libresoc.v:53357$2440 + attribute \src "libresoc.v:189775.3-189776.35" + process $proc$libresoc.v:189775$14467 assign { } { } assign $0\xive1_pri[7:0] \xive1_pri$next sync posedge \clk update \xive1_pri $0\xive1_pri[7:0] end - attribute \src "libresoc.v:53359.3-53360.35" - process $proc$libresoc.v:53359$2441 + attribute \src "libresoc.v:189777.3-189778.35" + process $proc$libresoc.v:189777$14468 assign { } { } assign $0\xive2_pri[7:0] \xive2_pri$next sync posedge \clk update \xive2_pri $0\xive2_pri[7:0] end - attribute \src "libresoc.v:53361.3-53362.35" - process $proc$libresoc.v:53361$2442 + attribute \src "libresoc.v:189779.3-189780.35" + process $proc$libresoc.v:189779$14469 assign { } { } assign $0\xive3_pri[7:0] \xive3_pri$next sync posedge \clk update \xive3_pri $0\xive3_pri[7:0] end - attribute \src "libresoc.v:53363.3-53364.35" - process $proc$libresoc.v:53363$2443 + attribute \src "libresoc.v:189781.3-189782.35" + process $proc$libresoc.v:189781$14470 assign { } { } assign $0\xive4_pri[7:0] \xive4_pri$next sync posedge \clk update \xive4_pri $0\xive4_pri[7:0] end - attribute \src "libresoc.v:53365.3-53366.35" - process $proc$libresoc.v:53365$2444 + attribute \src "libresoc.v:189783.3-189784.35" + process $proc$libresoc.v:189783$14471 assign { } { } assign $0\xive5_pri[7:0] \xive5_pri$next sync posedge \clk update \xive5_pri $0\xive5_pri[7:0] end - attribute \src "libresoc.v:53367.3-53368.35" - process $proc$libresoc.v:53367$2445 + attribute \src "libresoc.v:189785.3-189786.35" + process $proc$libresoc.v:189785$14472 assign { } { } assign $0\xive6_pri[7:0] \xive6_pri$next sync posedge \clk update \xive6_pri $0\xive6_pri[7:0] end - attribute \src "libresoc.v:53369.3-53370.35" - process $proc$libresoc.v:53369$2446 + attribute \src "libresoc.v:189787.3-189788.35" + process $proc$libresoc.v:189787$14473 assign { } { } assign $0\xive7_pri[7:0] \xive7_pri$next sync posedge \clk update \xive7_pri $0\xive7_pri[7:0] end - attribute \src "libresoc.v:53371.3-53372.35" - process $proc$libresoc.v:53371$2447 + attribute \src "libresoc.v:189789.3-189790.35" + process $proc$libresoc.v:189789$14474 assign { } { } assign $0\xive8_pri[7:0] \xive8_pri$next sync posedge \clk update \xive8_pri $0\xive8_pri[7:0] end - attribute \src "libresoc.v:53373.3-53374.35" - process $proc$libresoc.v:53373$2448 + attribute \src "libresoc.v:189791.3-189792.35" + process $proc$libresoc.v:189791$14475 assign { } { } assign $0\xive9_pri[7:0] \xive9_pri$next sync posedge \clk update \xive9_pri $0\xive9_pri[7:0] end - attribute \src "libresoc.v:53375.3-53376.37" - process $proc$libresoc.v:53375$2449 + attribute \src "libresoc.v:189793.3-189794.37" + process $proc$libresoc.v:189793$14476 assign { } { } assign $0\xive10_pri[7:0] \xive10_pri$next sync posedge \clk update \xive10_pri $0\xive10_pri[7:0] end - attribute \src "libresoc.v:53377.3-53462.6" - process $proc$libresoc.v:53377$2450 + attribute \src "libresoc.v:189795.3-189880.6" + process $proc$libresoc.v:189795$14477 assign { } { } assign { } { } assign { } { } @@ -149699,25 +400270,25 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $0\xive0_pri$next[7:0]$2451 $4\xive0_pri$next[7:0]$2515 - assign $0\xive10_pri$next[7:0]$2452 $4\xive10_pri$next[7:0]$2516 - assign $0\xive11_pri$next[7:0]$2453 $4\xive11_pri$next[7:0]$2517 - assign $0\xive12_pri$next[7:0]$2454 $4\xive12_pri$next[7:0]$2518 - assign $0\xive13_pri$next[7:0]$2455 $4\xive13_pri$next[7:0]$2519 - assign $0\xive14_pri$next[7:0]$2456 $4\xive14_pri$next[7:0]$2520 - assign $0\xive15_pri$next[7:0]$2457 $4\xive15_pri$next[7:0]$2521 - assign $0\xive1_pri$next[7:0]$2458 $4\xive1_pri$next[7:0]$2522 - assign $0\xive2_pri$next[7:0]$2459 $4\xive2_pri$next[7:0]$2523 - assign $0\xive3_pri$next[7:0]$2460 $4\xive3_pri$next[7:0]$2524 - assign $0\xive4_pri$next[7:0]$2461 $4\xive4_pri$next[7:0]$2525 - assign $0\xive5_pri$next[7:0]$2462 $4\xive5_pri$next[7:0]$2526 - assign $0\xive6_pri$next[7:0]$2463 $4\xive6_pri$next[7:0]$2527 - assign $0\xive7_pri$next[7:0]$2464 $4\xive7_pri$next[7:0]$2528 - assign $0\xive8_pri$next[7:0]$2465 $4\xive8_pri$next[7:0]$2529 - assign $0\xive9_pri$next[7:0]$2466 $4\xive9_pri$next[7:0]$2530 - attribute \src "libresoc.v:53378.5-53378.29" + assign $0\xive0_pri$next[7:0]$14478 $4\xive0_pri$next[7:0]$14542 + assign $0\xive10_pri$next[7:0]$14479 $4\xive10_pri$next[7:0]$14543 + assign $0\xive11_pri$next[7:0]$14480 $4\xive11_pri$next[7:0]$14544 + assign $0\xive12_pri$next[7:0]$14481 $4\xive12_pri$next[7:0]$14545 + assign $0\xive13_pri$next[7:0]$14482 $4\xive13_pri$next[7:0]$14546 + assign $0\xive14_pri$next[7:0]$14483 $4\xive14_pri$next[7:0]$14547 + assign $0\xive15_pri$next[7:0]$14484 $4\xive15_pri$next[7:0]$14548 + assign $0\xive1_pri$next[7:0]$14485 $4\xive1_pri$next[7:0]$14549 + assign $0\xive2_pri$next[7:0]$14486 $4\xive2_pri$next[7:0]$14550 + assign $0\xive3_pri$next[7:0]$14487 $4\xive3_pri$next[7:0]$14551 + assign $0\xive4_pri$next[7:0]$14488 $4\xive4_pri$next[7:0]$14552 + assign $0\xive5_pri$next[7:0]$14489 $4\xive5_pri$next[7:0]$14553 + assign $0\xive6_pri$next[7:0]$14490 $4\xive6_pri$next[7:0]$14554 + assign $0\xive7_pri$next[7:0]$14491 $4\xive7_pri$next[7:0]$14555 + assign $0\xive8_pri$next[7:0]$14492 $4\xive8_pri$next[7:0]$14556 + assign $0\xive9_pri$next[7:0]$14493 $4\xive9_pri$next[7:0]$14557 + attribute \src "libresoc.v:189796.5-189796.29" switch \initial - attribute \src "libresoc.v:53378.9-53378.17" + attribute \src "libresoc.v:189796.9-189796.17" case 1'1 case end @@ -149741,22 +400312,22 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $1\xive0_pri$next[7:0]$2467 $2\xive0_pri$next[7:0]$2483 - assign $1\xive10_pri$next[7:0]$2468 $2\xive10_pri$next[7:0]$2484 - assign $1\xive11_pri$next[7:0]$2469 $2\xive11_pri$next[7:0]$2485 - assign $1\xive12_pri$next[7:0]$2470 $2\xive12_pri$next[7:0]$2486 - assign $1\xive13_pri$next[7:0]$2471 $2\xive13_pri$next[7:0]$2487 - assign $1\xive14_pri$next[7:0]$2472 $2\xive14_pri$next[7:0]$2488 - assign $1\xive15_pri$next[7:0]$2473 $2\xive15_pri$next[7:0]$2489 - assign $1\xive1_pri$next[7:0]$2474 $2\xive1_pri$next[7:0]$2490 - assign $1\xive2_pri$next[7:0]$2475 $2\xive2_pri$next[7:0]$2491 - assign $1\xive3_pri$next[7:0]$2476 $2\xive3_pri$next[7:0]$2492 - assign $1\xive4_pri$next[7:0]$2477 $2\xive4_pri$next[7:0]$2493 - assign $1\xive5_pri$next[7:0]$2478 $2\xive5_pri$next[7:0]$2494 - assign $1\xive6_pri$next[7:0]$2479 $2\xive6_pri$next[7:0]$2495 - assign $1\xive7_pri$next[7:0]$2480 $2\xive7_pri$next[7:0]$2496 - assign $1\xive8_pri$next[7:0]$2481 $2\xive8_pri$next[7:0]$2497 - assign $1\xive9_pri$next[7:0]$2482 $2\xive9_pri$next[7:0]$2498 + assign $1\xive0_pri$next[7:0]$14494 $2\xive0_pri$next[7:0]$14510 + assign $1\xive10_pri$next[7:0]$14495 $2\xive10_pri$next[7:0]$14511 + assign $1\xive11_pri$next[7:0]$14496 $2\xive11_pri$next[7:0]$14512 + assign $1\xive12_pri$next[7:0]$14497 $2\xive12_pri$next[7:0]$14513 + assign $1\xive13_pri$next[7:0]$14498 $2\xive13_pri$next[7:0]$14514 + assign $1\xive14_pri$next[7:0]$14499 $2\xive14_pri$next[7:0]$14515 + assign $1\xive15_pri$next[7:0]$14500 $2\xive15_pri$next[7:0]$14516 + assign $1\xive1_pri$next[7:0]$14501 $2\xive1_pri$next[7:0]$14517 + assign $1\xive2_pri$next[7:0]$14502 $2\xive2_pri$next[7:0]$14518 + assign $1\xive3_pri$next[7:0]$14503 $2\xive3_pri$next[7:0]$14519 + assign $1\xive4_pri$next[7:0]$14504 $2\xive4_pri$next[7:0]$14520 + assign $1\xive5_pri$next[7:0]$14505 $2\xive5_pri$next[7:0]$14521 + assign $1\xive6_pri$next[7:0]$14506 $2\xive6_pri$next[7:0]$14522 + assign $1\xive7_pri$next[7:0]$14507 $2\xive7_pri$next[7:0]$14523 + assign $1\xive8_pri$next[7:0]$14508 $2\xive8_pri$next[7:0]$14524 + assign $1\xive9_pri$next[7:0]$14509 $2\xive9_pri$next[7:0]$14525 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:342" switch \reg_is_xive attribute \src "libresoc.v:0.0-0.0" @@ -149777,381 +400348,381 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $2\xive0_pri$next[7:0]$2483 $3\xive0_pri$next[7:0]$2499 - assign $2\xive10_pri$next[7:0]$2484 $3\xive10_pri$next[7:0]$2500 - assign $2\xive11_pri$next[7:0]$2485 $3\xive11_pri$next[7:0]$2501 - assign $2\xive12_pri$next[7:0]$2486 $3\xive12_pri$next[7:0]$2502 - assign $2\xive13_pri$next[7:0]$2487 $3\xive13_pri$next[7:0]$2503 - assign $2\xive14_pri$next[7:0]$2488 $3\xive14_pri$next[7:0]$2504 - assign $2\xive15_pri$next[7:0]$2489 $3\xive15_pri$next[7:0]$2505 - assign $2\xive1_pri$next[7:0]$2490 $3\xive1_pri$next[7:0]$2506 - assign $2\xive2_pri$next[7:0]$2491 $3\xive2_pri$next[7:0]$2507 - assign $2\xive3_pri$next[7:0]$2492 $3\xive3_pri$next[7:0]$2508 - assign $2\xive4_pri$next[7:0]$2493 $3\xive4_pri$next[7:0]$2509 - assign $2\xive5_pri$next[7:0]$2494 $3\xive5_pri$next[7:0]$2510 - assign $2\xive6_pri$next[7:0]$2495 $3\xive6_pri$next[7:0]$2511 - assign $2\xive7_pri$next[7:0]$2496 $3\xive7_pri$next[7:0]$2512 - assign $2\xive8_pri$next[7:0]$2497 $3\xive8_pri$next[7:0]$2513 - assign $2\xive9_pri$next[7:0]$2498 $3\xive9_pri$next[7:0]$2514 + assign $2\xive0_pri$next[7:0]$14510 $3\xive0_pri$next[7:0]$14526 + assign $2\xive10_pri$next[7:0]$14511 $3\xive10_pri$next[7:0]$14527 + assign $2\xive11_pri$next[7:0]$14512 $3\xive11_pri$next[7:0]$14528 + assign $2\xive12_pri$next[7:0]$14513 $3\xive12_pri$next[7:0]$14529 + assign $2\xive13_pri$next[7:0]$14514 $3\xive13_pri$next[7:0]$14530 + assign $2\xive14_pri$next[7:0]$14515 $3\xive14_pri$next[7:0]$14531 + assign $2\xive15_pri$next[7:0]$14516 $3\xive15_pri$next[7:0]$14532 + assign $2\xive1_pri$next[7:0]$14517 $3\xive1_pri$next[7:0]$14533 + assign $2\xive2_pri$next[7:0]$14518 $3\xive2_pri$next[7:0]$14534 + assign $2\xive3_pri$next[7:0]$14519 $3\xive3_pri$next[7:0]$14535 + assign $2\xive4_pri$next[7:0]$14520 $3\xive4_pri$next[7:0]$14536 + assign $2\xive5_pri$next[7:0]$14521 $3\xive5_pri$next[7:0]$14537 + assign $2\xive6_pri$next[7:0]$14522 $3\xive6_pri$next[7:0]$14538 + assign $2\xive7_pri$next[7:0]$14523 $3\xive7_pri$next[7:0]$14539 + assign $2\xive8_pri$next[7:0]$14524 $3\xive8_pri$next[7:0]$14540 + assign $2\xive9_pri$next[7:0]$14525 $3\xive9_pri$next[7:0]$14541 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:345" switch \reg_idx attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $3\xive10_pri$next[7:0]$2500 \xive10_pri - assign $3\xive11_pri$next[7:0]$2501 \xive11_pri - assign $3\xive12_pri$next[7:0]$2502 \xive12_pri - assign $3\xive13_pri$next[7:0]$2503 \xive13_pri - assign $3\xive14_pri$next[7:0]$2504 \xive14_pri - assign $3\xive15_pri$next[7:0]$2505 \xive15_pri - assign $3\xive1_pri$next[7:0]$2506 \xive1_pri - assign $3\xive2_pri$next[7:0]$2507 \xive2_pri - assign $3\xive3_pri$next[7:0]$2508 \xive3_pri - assign $3\xive4_pri$next[7:0]$2509 \xive4_pri - assign $3\xive5_pri$next[7:0]$2510 \xive5_pri - assign $3\xive6_pri$next[7:0]$2511 \xive6_pri - assign $3\xive7_pri$next[7:0]$2512 \xive7_pri - assign $3\xive8_pri$next[7:0]$2513 \xive8_pri - assign $3\xive9_pri$next[7:0]$2514 \xive9_pri - assign $3\xive0_pri$next[7:0]$2499 \be_in [7:0] + assign $3\xive10_pri$next[7:0]$14527 \xive10_pri + assign $3\xive11_pri$next[7:0]$14528 \xive11_pri + assign $3\xive12_pri$next[7:0]$14529 \xive12_pri + assign $3\xive13_pri$next[7:0]$14530 \xive13_pri + assign $3\xive14_pri$next[7:0]$14531 \xive14_pri + assign $3\xive15_pri$next[7:0]$14532 \xive15_pri + assign $3\xive1_pri$next[7:0]$14533 \xive1_pri + assign $3\xive2_pri$next[7:0]$14534 \xive2_pri + assign $3\xive3_pri$next[7:0]$14535 \xive3_pri + assign $3\xive4_pri$next[7:0]$14536 \xive4_pri + assign $3\xive5_pri$next[7:0]$14537 \xive5_pri + assign $3\xive6_pri$next[7:0]$14538 \xive6_pri + assign $3\xive7_pri$next[7:0]$14539 \xive7_pri + assign $3\xive8_pri$next[7:0]$14540 \xive8_pri + assign $3\xive9_pri$next[7:0]$14541 \xive9_pri + assign $3\xive0_pri$next[7:0]$14526 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0001 - assign $3\xive0_pri$next[7:0]$2499 \xive0_pri - assign $3\xive10_pri$next[7:0]$2500 \xive10_pri - assign $3\xive11_pri$next[7:0]$2501 \xive11_pri - assign $3\xive12_pri$next[7:0]$2502 \xive12_pri - assign $3\xive13_pri$next[7:0]$2503 \xive13_pri - assign $3\xive14_pri$next[7:0]$2504 \xive14_pri - assign $3\xive15_pri$next[7:0]$2505 \xive15_pri + assign $3\xive0_pri$next[7:0]$14526 \xive0_pri + assign $3\xive10_pri$next[7:0]$14527 \xive10_pri + assign $3\xive11_pri$next[7:0]$14528 \xive11_pri + assign $3\xive12_pri$next[7:0]$14529 \xive12_pri + assign $3\xive13_pri$next[7:0]$14530 \xive13_pri + assign $3\xive14_pri$next[7:0]$14531 \xive14_pri + assign $3\xive15_pri$next[7:0]$14532 \xive15_pri assign { } { } - assign $3\xive2_pri$next[7:0]$2507 \xive2_pri - assign $3\xive3_pri$next[7:0]$2508 \xive3_pri - assign $3\xive4_pri$next[7:0]$2509 \xive4_pri - assign $3\xive5_pri$next[7:0]$2510 \xive5_pri - assign $3\xive6_pri$next[7:0]$2511 \xive6_pri - assign $3\xive7_pri$next[7:0]$2512 \xive7_pri - assign $3\xive8_pri$next[7:0]$2513 \xive8_pri - assign $3\xive9_pri$next[7:0]$2514 \xive9_pri - assign $3\xive1_pri$next[7:0]$2506 \be_in [7:0] + assign $3\xive2_pri$next[7:0]$14534 \xive2_pri + assign $3\xive3_pri$next[7:0]$14535 \xive3_pri + assign $3\xive4_pri$next[7:0]$14536 \xive4_pri + assign $3\xive5_pri$next[7:0]$14537 \xive5_pri + assign $3\xive6_pri$next[7:0]$14538 \xive6_pri + assign $3\xive7_pri$next[7:0]$14539 \xive7_pri + assign $3\xive8_pri$next[7:0]$14540 \xive8_pri + assign $3\xive9_pri$next[7:0]$14541 \xive9_pri + assign $3\xive1_pri$next[7:0]$14533 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0010 - assign $3\xive0_pri$next[7:0]$2499 \xive0_pri - assign $3\xive10_pri$next[7:0]$2500 \xive10_pri - assign $3\xive11_pri$next[7:0]$2501 \xive11_pri - assign $3\xive12_pri$next[7:0]$2502 \xive12_pri - assign $3\xive13_pri$next[7:0]$2503 \xive13_pri - assign $3\xive14_pri$next[7:0]$2504 \xive14_pri - assign $3\xive15_pri$next[7:0]$2505 \xive15_pri - assign $3\xive1_pri$next[7:0]$2506 \xive1_pri + assign $3\xive0_pri$next[7:0]$14526 \xive0_pri + assign $3\xive10_pri$next[7:0]$14527 \xive10_pri + assign $3\xive11_pri$next[7:0]$14528 \xive11_pri + assign $3\xive12_pri$next[7:0]$14529 \xive12_pri + assign $3\xive13_pri$next[7:0]$14530 \xive13_pri + assign $3\xive14_pri$next[7:0]$14531 \xive14_pri + assign $3\xive15_pri$next[7:0]$14532 \xive15_pri + assign $3\xive1_pri$next[7:0]$14533 \xive1_pri assign { } { } - assign $3\xive3_pri$next[7:0]$2508 \xive3_pri - assign $3\xive4_pri$next[7:0]$2509 \xive4_pri - assign $3\xive5_pri$next[7:0]$2510 \xive5_pri - assign $3\xive6_pri$next[7:0]$2511 \xive6_pri - assign $3\xive7_pri$next[7:0]$2512 \xive7_pri - assign $3\xive8_pri$next[7:0]$2513 \xive8_pri - assign $3\xive9_pri$next[7:0]$2514 \xive9_pri - assign $3\xive2_pri$next[7:0]$2507 \be_in [7:0] + assign $3\xive3_pri$next[7:0]$14535 \xive3_pri + assign $3\xive4_pri$next[7:0]$14536 \xive4_pri + assign $3\xive5_pri$next[7:0]$14537 \xive5_pri + assign $3\xive6_pri$next[7:0]$14538 \xive6_pri + assign $3\xive7_pri$next[7:0]$14539 \xive7_pri + assign $3\xive8_pri$next[7:0]$14540 \xive8_pri + assign $3\xive9_pri$next[7:0]$14541 \xive9_pri + assign $3\xive2_pri$next[7:0]$14534 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0011 - assign $3\xive0_pri$next[7:0]$2499 \xive0_pri - assign $3\xive10_pri$next[7:0]$2500 \xive10_pri - assign $3\xive11_pri$next[7:0]$2501 \xive11_pri - assign $3\xive12_pri$next[7:0]$2502 \xive12_pri - assign $3\xive13_pri$next[7:0]$2503 \xive13_pri - assign $3\xive14_pri$next[7:0]$2504 \xive14_pri - assign $3\xive15_pri$next[7:0]$2505 \xive15_pri - assign $3\xive1_pri$next[7:0]$2506 \xive1_pri - assign $3\xive2_pri$next[7:0]$2507 \xive2_pri + assign $3\xive0_pri$next[7:0]$14526 \xive0_pri + assign $3\xive10_pri$next[7:0]$14527 \xive10_pri + assign $3\xive11_pri$next[7:0]$14528 \xive11_pri + assign $3\xive12_pri$next[7:0]$14529 \xive12_pri + assign $3\xive13_pri$next[7:0]$14530 \xive13_pri + assign $3\xive14_pri$next[7:0]$14531 \xive14_pri + assign $3\xive15_pri$next[7:0]$14532 \xive15_pri + assign $3\xive1_pri$next[7:0]$14533 \xive1_pri + assign $3\xive2_pri$next[7:0]$14534 \xive2_pri assign { } { } - assign $3\xive4_pri$next[7:0]$2509 \xive4_pri - assign $3\xive5_pri$next[7:0]$2510 \xive5_pri - assign $3\xive6_pri$next[7:0]$2511 \xive6_pri - assign $3\xive7_pri$next[7:0]$2512 \xive7_pri - assign $3\xive8_pri$next[7:0]$2513 \xive8_pri - assign $3\xive9_pri$next[7:0]$2514 \xive9_pri - assign $3\xive3_pri$next[7:0]$2508 \be_in [7:0] + assign $3\xive4_pri$next[7:0]$14536 \xive4_pri + assign $3\xive5_pri$next[7:0]$14537 \xive5_pri + assign $3\xive6_pri$next[7:0]$14538 \xive6_pri + assign $3\xive7_pri$next[7:0]$14539 \xive7_pri + assign $3\xive8_pri$next[7:0]$14540 \xive8_pri + assign $3\xive9_pri$next[7:0]$14541 \xive9_pri + assign $3\xive3_pri$next[7:0]$14535 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0100 - assign $3\xive0_pri$next[7:0]$2499 \xive0_pri - assign $3\xive10_pri$next[7:0]$2500 \xive10_pri - assign $3\xive11_pri$next[7:0]$2501 \xive11_pri - assign $3\xive12_pri$next[7:0]$2502 \xive12_pri - assign $3\xive13_pri$next[7:0]$2503 \xive13_pri - assign $3\xive14_pri$next[7:0]$2504 \xive14_pri - assign $3\xive15_pri$next[7:0]$2505 \xive15_pri - assign $3\xive1_pri$next[7:0]$2506 \xive1_pri - assign $3\xive2_pri$next[7:0]$2507 \xive2_pri - assign $3\xive3_pri$next[7:0]$2508 \xive3_pri + assign $3\xive0_pri$next[7:0]$14526 \xive0_pri + assign $3\xive10_pri$next[7:0]$14527 \xive10_pri + assign $3\xive11_pri$next[7:0]$14528 \xive11_pri + assign $3\xive12_pri$next[7:0]$14529 \xive12_pri + assign $3\xive13_pri$next[7:0]$14530 \xive13_pri + assign $3\xive14_pri$next[7:0]$14531 \xive14_pri + assign $3\xive15_pri$next[7:0]$14532 \xive15_pri + assign $3\xive1_pri$next[7:0]$14533 \xive1_pri + assign $3\xive2_pri$next[7:0]$14534 \xive2_pri + assign $3\xive3_pri$next[7:0]$14535 \xive3_pri assign { } { } - assign $3\xive5_pri$next[7:0]$2510 \xive5_pri - assign $3\xive6_pri$next[7:0]$2511 \xive6_pri - assign $3\xive7_pri$next[7:0]$2512 \xive7_pri - assign $3\xive8_pri$next[7:0]$2513 \xive8_pri - assign $3\xive9_pri$next[7:0]$2514 \xive9_pri - assign $3\xive4_pri$next[7:0]$2509 \be_in [7:0] + assign $3\xive5_pri$next[7:0]$14537 \xive5_pri + assign $3\xive6_pri$next[7:0]$14538 \xive6_pri + assign $3\xive7_pri$next[7:0]$14539 \xive7_pri + assign $3\xive8_pri$next[7:0]$14540 \xive8_pri + assign $3\xive9_pri$next[7:0]$14541 \xive9_pri + assign $3\xive4_pri$next[7:0]$14536 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0101 - assign $3\xive0_pri$next[7:0]$2499 \xive0_pri - assign $3\xive10_pri$next[7:0]$2500 \xive10_pri - assign $3\xive11_pri$next[7:0]$2501 \xive11_pri - assign $3\xive12_pri$next[7:0]$2502 \xive12_pri - assign $3\xive13_pri$next[7:0]$2503 \xive13_pri - assign $3\xive14_pri$next[7:0]$2504 \xive14_pri - assign $3\xive15_pri$next[7:0]$2505 \xive15_pri - assign $3\xive1_pri$next[7:0]$2506 \xive1_pri - assign $3\xive2_pri$next[7:0]$2507 \xive2_pri - assign $3\xive3_pri$next[7:0]$2508 \xive3_pri - assign $3\xive4_pri$next[7:0]$2509 \xive4_pri + assign $3\xive0_pri$next[7:0]$14526 \xive0_pri + assign $3\xive10_pri$next[7:0]$14527 \xive10_pri + assign $3\xive11_pri$next[7:0]$14528 \xive11_pri + assign $3\xive12_pri$next[7:0]$14529 \xive12_pri + assign $3\xive13_pri$next[7:0]$14530 \xive13_pri + assign $3\xive14_pri$next[7:0]$14531 \xive14_pri + assign $3\xive15_pri$next[7:0]$14532 \xive15_pri + assign $3\xive1_pri$next[7:0]$14533 \xive1_pri + assign $3\xive2_pri$next[7:0]$14534 \xive2_pri + assign $3\xive3_pri$next[7:0]$14535 \xive3_pri + assign $3\xive4_pri$next[7:0]$14536 \xive4_pri assign { } { } - assign $3\xive6_pri$next[7:0]$2511 \xive6_pri - assign $3\xive7_pri$next[7:0]$2512 \xive7_pri - assign $3\xive8_pri$next[7:0]$2513 \xive8_pri - assign $3\xive9_pri$next[7:0]$2514 \xive9_pri - assign $3\xive5_pri$next[7:0]$2510 \be_in [7:0] + assign $3\xive6_pri$next[7:0]$14538 \xive6_pri + assign $3\xive7_pri$next[7:0]$14539 \xive7_pri + assign $3\xive8_pri$next[7:0]$14540 \xive8_pri + assign $3\xive9_pri$next[7:0]$14541 \xive9_pri + assign $3\xive5_pri$next[7:0]$14537 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0110 - assign $3\xive0_pri$next[7:0]$2499 \xive0_pri - assign $3\xive10_pri$next[7:0]$2500 \xive10_pri - assign $3\xive11_pri$next[7:0]$2501 \xive11_pri - assign $3\xive12_pri$next[7:0]$2502 \xive12_pri - assign $3\xive13_pri$next[7:0]$2503 \xive13_pri - assign $3\xive14_pri$next[7:0]$2504 \xive14_pri - assign $3\xive15_pri$next[7:0]$2505 \xive15_pri - assign $3\xive1_pri$next[7:0]$2506 \xive1_pri - assign $3\xive2_pri$next[7:0]$2507 \xive2_pri - assign $3\xive3_pri$next[7:0]$2508 \xive3_pri - assign $3\xive4_pri$next[7:0]$2509 \xive4_pri - assign $3\xive5_pri$next[7:0]$2510 \xive5_pri + assign $3\xive0_pri$next[7:0]$14526 \xive0_pri + assign $3\xive10_pri$next[7:0]$14527 \xive10_pri + assign $3\xive11_pri$next[7:0]$14528 \xive11_pri + assign $3\xive12_pri$next[7:0]$14529 \xive12_pri + assign $3\xive13_pri$next[7:0]$14530 \xive13_pri + assign $3\xive14_pri$next[7:0]$14531 \xive14_pri + assign $3\xive15_pri$next[7:0]$14532 \xive15_pri + assign $3\xive1_pri$next[7:0]$14533 \xive1_pri + assign $3\xive2_pri$next[7:0]$14534 \xive2_pri + assign $3\xive3_pri$next[7:0]$14535 \xive3_pri + assign $3\xive4_pri$next[7:0]$14536 \xive4_pri + assign $3\xive5_pri$next[7:0]$14537 \xive5_pri assign { } { } - assign $3\xive7_pri$next[7:0]$2512 \xive7_pri - assign $3\xive8_pri$next[7:0]$2513 \xive8_pri - assign $3\xive9_pri$next[7:0]$2514 \xive9_pri - assign $3\xive6_pri$next[7:0]$2511 \be_in [7:0] + assign $3\xive7_pri$next[7:0]$14539 \xive7_pri + assign $3\xive8_pri$next[7:0]$14540 \xive8_pri + assign $3\xive9_pri$next[7:0]$14541 \xive9_pri + assign $3\xive6_pri$next[7:0]$14538 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0111 - assign $3\xive0_pri$next[7:0]$2499 \xive0_pri - assign $3\xive10_pri$next[7:0]$2500 \xive10_pri - assign $3\xive11_pri$next[7:0]$2501 \xive11_pri - assign $3\xive12_pri$next[7:0]$2502 \xive12_pri - assign $3\xive13_pri$next[7:0]$2503 \xive13_pri - assign $3\xive14_pri$next[7:0]$2504 \xive14_pri - assign $3\xive15_pri$next[7:0]$2505 \xive15_pri - assign $3\xive1_pri$next[7:0]$2506 \xive1_pri - assign $3\xive2_pri$next[7:0]$2507 \xive2_pri - assign $3\xive3_pri$next[7:0]$2508 \xive3_pri - assign $3\xive4_pri$next[7:0]$2509 \xive4_pri - assign $3\xive5_pri$next[7:0]$2510 \xive5_pri - assign $3\xive6_pri$next[7:0]$2511 \xive6_pri + assign $3\xive0_pri$next[7:0]$14526 \xive0_pri + assign $3\xive10_pri$next[7:0]$14527 \xive10_pri + assign $3\xive11_pri$next[7:0]$14528 \xive11_pri + assign $3\xive12_pri$next[7:0]$14529 \xive12_pri + assign $3\xive13_pri$next[7:0]$14530 \xive13_pri + assign $3\xive14_pri$next[7:0]$14531 \xive14_pri + assign $3\xive15_pri$next[7:0]$14532 \xive15_pri + assign $3\xive1_pri$next[7:0]$14533 \xive1_pri + assign $3\xive2_pri$next[7:0]$14534 \xive2_pri + assign $3\xive3_pri$next[7:0]$14535 \xive3_pri + assign $3\xive4_pri$next[7:0]$14536 \xive4_pri + assign $3\xive5_pri$next[7:0]$14537 \xive5_pri + assign $3\xive6_pri$next[7:0]$14538 \xive6_pri assign { } { } - assign $3\xive8_pri$next[7:0]$2513 \xive8_pri - assign $3\xive9_pri$next[7:0]$2514 \xive9_pri - assign $3\xive7_pri$next[7:0]$2512 \be_in [7:0] + assign $3\xive8_pri$next[7:0]$14540 \xive8_pri + assign $3\xive9_pri$next[7:0]$14541 \xive9_pri + assign $3\xive7_pri$next[7:0]$14539 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1000 - assign $3\xive0_pri$next[7:0]$2499 \xive0_pri - assign $3\xive10_pri$next[7:0]$2500 \xive10_pri - assign $3\xive11_pri$next[7:0]$2501 \xive11_pri - assign $3\xive12_pri$next[7:0]$2502 \xive12_pri - assign $3\xive13_pri$next[7:0]$2503 \xive13_pri - assign $3\xive14_pri$next[7:0]$2504 \xive14_pri - assign $3\xive15_pri$next[7:0]$2505 \xive15_pri - assign $3\xive1_pri$next[7:0]$2506 \xive1_pri - assign $3\xive2_pri$next[7:0]$2507 \xive2_pri - assign $3\xive3_pri$next[7:0]$2508 \xive3_pri - assign $3\xive4_pri$next[7:0]$2509 \xive4_pri - assign $3\xive5_pri$next[7:0]$2510 \xive5_pri - assign $3\xive6_pri$next[7:0]$2511 \xive6_pri - assign $3\xive7_pri$next[7:0]$2512 \xive7_pri + assign $3\xive0_pri$next[7:0]$14526 \xive0_pri + assign $3\xive10_pri$next[7:0]$14527 \xive10_pri + assign $3\xive11_pri$next[7:0]$14528 \xive11_pri + assign $3\xive12_pri$next[7:0]$14529 \xive12_pri + assign $3\xive13_pri$next[7:0]$14530 \xive13_pri + assign $3\xive14_pri$next[7:0]$14531 \xive14_pri + assign $3\xive15_pri$next[7:0]$14532 \xive15_pri + assign $3\xive1_pri$next[7:0]$14533 \xive1_pri + assign $3\xive2_pri$next[7:0]$14534 \xive2_pri + assign $3\xive3_pri$next[7:0]$14535 \xive3_pri + assign $3\xive4_pri$next[7:0]$14536 \xive4_pri + assign $3\xive5_pri$next[7:0]$14537 \xive5_pri + assign $3\xive6_pri$next[7:0]$14538 \xive6_pri + assign $3\xive7_pri$next[7:0]$14539 \xive7_pri assign { } { } - assign $3\xive9_pri$next[7:0]$2514 \xive9_pri - assign $3\xive8_pri$next[7:0]$2513 \be_in [7:0] + assign $3\xive9_pri$next[7:0]$14541 \xive9_pri + assign $3\xive8_pri$next[7:0]$14540 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1001 - assign $3\xive0_pri$next[7:0]$2499 \xive0_pri - assign $3\xive10_pri$next[7:0]$2500 \xive10_pri - assign $3\xive11_pri$next[7:0]$2501 \xive11_pri - assign $3\xive12_pri$next[7:0]$2502 \xive12_pri - assign $3\xive13_pri$next[7:0]$2503 \xive13_pri - assign $3\xive14_pri$next[7:0]$2504 \xive14_pri - assign $3\xive15_pri$next[7:0]$2505 \xive15_pri - assign $3\xive1_pri$next[7:0]$2506 \xive1_pri - assign $3\xive2_pri$next[7:0]$2507 \xive2_pri - assign $3\xive3_pri$next[7:0]$2508 \xive3_pri - assign $3\xive4_pri$next[7:0]$2509 \xive4_pri - assign $3\xive5_pri$next[7:0]$2510 \xive5_pri - assign $3\xive6_pri$next[7:0]$2511 \xive6_pri - assign $3\xive7_pri$next[7:0]$2512 \xive7_pri - assign $3\xive8_pri$next[7:0]$2513 \xive8_pri + assign $3\xive0_pri$next[7:0]$14526 \xive0_pri + assign $3\xive10_pri$next[7:0]$14527 \xive10_pri + assign $3\xive11_pri$next[7:0]$14528 \xive11_pri + assign $3\xive12_pri$next[7:0]$14529 \xive12_pri + assign $3\xive13_pri$next[7:0]$14530 \xive13_pri + assign $3\xive14_pri$next[7:0]$14531 \xive14_pri + assign $3\xive15_pri$next[7:0]$14532 \xive15_pri + assign $3\xive1_pri$next[7:0]$14533 \xive1_pri + assign $3\xive2_pri$next[7:0]$14534 \xive2_pri + assign $3\xive3_pri$next[7:0]$14535 \xive3_pri + assign $3\xive4_pri$next[7:0]$14536 \xive4_pri + assign $3\xive5_pri$next[7:0]$14537 \xive5_pri + assign $3\xive6_pri$next[7:0]$14538 \xive6_pri + assign $3\xive7_pri$next[7:0]$14539 \xive7_pri + assign $3\xive8_pri$next[7:0]$14540 \xive8_pri assign { } { } - assign $3\xive9_pri$next[7:0]$2514 \be_in [7:0] + assign $3\xive9_pri$next[7:0]$14541 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1010 - assign $3\xive0_pri$next[7:0]$2499 \xive0_pri + assign $3\xive0_pri$next[7:0]$14526 \xive0_pri assign { } { } - assign $3\xive11_pri$next[7:0]$2501 \xive11_pri - assign $3\xive12_pri$next[7:0]$2502 \xive12_pri - assign $3\xive13_pri$next[7:0]$2503 \xive13_pri - assign $3\xive14_pri$next[7:0]$2504 \xive14_pri - assign $3\xive15_pri$next[7:0]$2505 \xive15_pri - assign $3\xive1_pri$next[7:0]$2506 \xive1_pri - assign $3\xive2_pri$next[7:0]$2507 \xive2_pri - assign $3\xive3_pri$next[7:0]$2508 \xive3_pri - assign $3\xive4_pri$next[7:0]$2509 \xive4_pri - assign $3\xive5_pri$next[7:0]$2510 \xive5_pri - assign $3\xive6_pri$next[7:0]$2511 \xive6_pri - assign $3\xive7_pri$next[7:0]$2512 \xive7_pri - assign $3\xive8_pri$next[7:0]$2513 \xive8_pri - assign $3\xive9_pri$next[7:0]$2514 \xive9_pri - assign $3\xive10_pri$next[7:0]$2500 \be_in [7:0] + assign $3\xive11_pri$next[7:0]$14528 \xive11_pri + assign $3\xive12_pri$next[7:0]$14529 \xive12_pri + assign $3\xive13_pri$next[7:0]$14530 \xive13_pri + assign $3\xive14_pri$next[7:0]$14531 \xive14_pri + assign $3\xive15_pri$next[7:0]$14532 \xive15_pri + assign $3\xive1_pri$next[7:0]$14533 \xive1_pri + assign $3\xive2_pri$next[7:0]$14534 \xive2_pri + assign $3\xive3_pri$next[7:0]$14535 \xive3_pri + assign $3\xive4_pri$next[7:0]$14536 \xive4_pri + assign $3\xive5_pri$next[7:0]$14537 \xive5_pri + assign $3\xive6_pri$next[7:0]$14538 \xive6_pri + assign $3\xive7_pri$next[7:0]$14539 \xive7_pri + assign $3\xive8_pri$next[7:0]$14540 \xive8_pri + assign $3\xive9_pri$next[7:0]$14541 \xive9_pri + assign $3\xive10_pri$next[7:0]$14527 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1011 - assign $3\xive0_pri$next[7:0]$2499 \xive0_pri - assign $3\xive10_pri$next[7:0]$2500 \xive10_pri + assign $3\xive0_pri$next[7:0]$14526 \xive0_pri + assign $3\xive10_pri$next[7:0]$14527 \xive10_pri assign { } { } - assign $3\xive12_pri$next[7:0]$2502 \xive12_pri - assign $3\xive13_pri$next[7:0]$2503 \xive13_pri - assign $3\xive14_pri$next[7:0]$2504 \xive14_pri - assign $3\xive15_pri$next[7:0]$2505 \xive15_pri - assign $3\xive1_pri$next[7:0]$2506 \xive1_pri - assign $3\xive2_pri$next[7:0]$2507 \xive2_pri - assign $3\xive3_pri$next[7:0]$2508 \xive3_pri - assign $3\xive4_pri$next[7:0]$2509 \xive4_pri - assign $3\xive5_pri$next[7:0]$2510 \xive5_pri - assign $3\xive6_pri$next[7:0]$2511 \xive6_pri - assign $3\xive7_pri$next[7:0]$2512 \xive7_pri - assign $3\xive8_pri$next[7:0]$2513 \xive8_pri - assign $3\xive9_pri$next[7:0]$2514 \xive9_pri - assign $3\xive11_pri$next[7:0]$2501 \be_in [7:0] + assign $3\xive12_pri$next[7:0]$14529 \xive12_pri + assign $3\xive13_pri$next[7:0]$14530 \xive13_pri + assign $3\xive14_pri$next[7:0]$14531 \xive14_pri + assign $3\xive15_pri$next[7:0]$14532 \xive15_pri + assign $3\xive1_pri$next[7:0]$14533 \xive1_pri + assign $3\xive2_pri$next[7:0]$14534 \xive2_pri + assign $3\xive3_pri$next[7:0]$14535 \xive3_pri + assign $3\xive4_pri$next[7:0]$14536 \xive4_pri + assign $3\xive5_pri$next[7:0]$14537 \xive5_pri + assign $3\xive6_pri$next[7:0]$14538 \xive6_pri + assign $3\xive7_pri$next[7:0]$14539 \xive7_pri + assign $3\xive8_pri$next[7:0]$14540 \xive8_pri + assign $3\xive9_pri$next[7:0]$14541 \xive9_pri + assign $3\xive11_pri$next[7:0]$14528 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1100 - assign $3\xive0_pri$next[7:0]$2499 \xive0_pri - assign $3\xive10_pri$next[7:0]$2500 \xive10_pri - assign $3\xive11_pri$next[7:0]$2501 \xive11_pri + assign $3\xive0_pri$next[7:0]$14526 \xive0_pri + assign $3\xive10_pri$next[7:0]$14527 \xive10_pri + assign $3\xive11_pri$next[7:0]$14528 \xive11_pri assign { } { } - assign $3\xive13_pri$next[7:0]$2503 \xive13_pri - assign $3\xive14_pri$next[7:0]$2504 \xive14_pri - assign $3\xive15_pri$next[7:0]$2505 \xive15_pri - assign $3\xive1_pri$next[7:0]$2506 \xive1_pri - assign $3\xive2_pri$next[7:0]$2507 \xive2_pri - assign $3\xive3_pri$next[7:0]$2508 \xive3_pri - assign $3\xive4_pri$next[7:0]$2509 \xive4_pri - assign $3\xive5_pri$next[7:0]$2510 \xive5_pri - assign $3\xive6_pri$next[7:0]$2511 \xive6_pri - assign $3\xive7_pri$next[7:0]$2512 \xive7_pri - assign $3\xive8_pri$next[7:0]$2513 \xive8_pri - assign $3\xive9_pri$next[7:0]$2514 \xive9_pri - assign $3\xive12_pri$next[7:0]$2502 \be_in [7:0] + assign $3\xive13_pri$next[7:0]$14530 \xive13_pri + assign $3\xive14_pri$next[7:0]$14531 \xive14_pri + assign $3\xive15_pri$next[7:0]$14532 \xive15_pri + assign $3\xive1_pri$next[7:0]$14533 \xive1_pri + assign $3\xive2_pri$next[7:0]$14534 \xive2_pri + assign $3\xive3_pri$next[7:0]$14535 \xive3_pri + assign $3\xive4_pri$next[7:0]$14536 \xive4_pri + assign $3\xive5_pri$next[7:0]$14537 \xive5_pri + assign $3\xive6_pri$next[7:0]$14538 \xive6_pri + assign $3\xive7_pri$next[7:0]$14539 \xive7_pri + assign $3\xive8_pri$next[7:0]$14540 \xive8_pri + assign $3\xive9_pri$next[7:0]$14541 \xive9_pri + assign $3\xive12_pri$next[7:0]$14529 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1101 - assign $3\xive0_pri$next[7:0]$2499 \xive0_pri - assign $3\xive10_pri$next[7:0]$2500 \xive10_pri - assign $3\xive11_pri$next[7:0]$2501 \xive11_pri - assign $3\xive12_pri$next[7:0]$2502 \xive12_pri + assign $3\xive0_pri$next[7:0]$14526 \xive0_pri + assign $3\xive10_pri$next[7:0]$14527 \xive10_pri + assign $3\xive11_pri$next[7:0]$14528 \xive11_pri + assign $3\xive12_pri$next[7:0]$14529 \xive12_pri assign { } { } - assign $3\xive14_pri$next[7:0]$2504 \xive14_pri - assign $3\xive15_pri$next[7:0]$2505 \xive15_pri - assign $3\xive1_pri$next[7:0]$2506 \xive1_pri - assign $3\xive2_pri$next[7:0]$2507 \xive2_pri - assign $3\xive3_pri$next[7:0]$2508 \xive3_pri - assign $3\xive4_pri$next[7:0]$2509 \xive4_pri - assign $3\xive5_pri$next[7:0]$2510 \xive5_pri - assign $3\xive6_pri$next[7:0]$2511 \xive6_pri - assign $3\xive7_pri$next[7:0]$2512 \xive7_pri - assign $3\xive8_pri$next[7:0]$2513 \xive8_pri - assign $3\xive9_pri$next[7:0]$2514 \xive9_pri - assign $3\xive13_pri$next[7:0]$2503 \be_in [7:0] + assign $3\xive14_pri$next[7:0]$14531 \xive14_pri + assign $3\xive15_pri$next[7:0]$14532 \xive15_pri + assign $3\xive1_pri$next[7:0]$14533 \xive1_pri + assign $3\xive2_pri$next[7:0]$14534 \xive2_pri + assign $3\xive3_pri$next[7:0]$14535 \xive3_pri + assign $3\xive4_pri$next[7:0]$14536 \xive4_pri + assign $3\xive5_pri$next[7:0]$14537 \xive5_pri + assign $3\xive6_pri$next[7:0]$14538 \xive6_pri + assign $3\xive7_pri$next[7:0]$14539 \xive7_pri + assign $3\xive8_pri$next[7:0]$14540 \xive8_pri + assign $3\xive9_pri$next[7:0]$14541 \xive9_pri + assign $3\xive13_pri$next[7:0]$14530 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1110 - assign $3\xive0_pri$next[7:0]$2499 \xive0_pri - assign $3\xive10_pri$next[7:0]$2500 \xive10_pri - assign $3\xive11_pri$next[7:0]$2501 \xive11_pri - assign $3\xive12_pri$next[7:0]$2502 \xive12_pri - assign $3\xive13_pri$next[7:0]$2503 \xive13_pri + assign $3\xive0_pri$next[7:0]$14526 \xive0_pri + assign $3\xive10_pri$next[7:0]$14527 \xive10_pri + assign $3\xive11_pri$next[7:0]$14528 \xive11_pri + assign $3\xive12_pri$next[7:0]$14529 \xive12_pri + assign $3\xive13_pri$next[7:0]$14530 \xive13_pri assign { } { } - assign $3\xive15_pri$next[7:0]$2505 \xive15_pri - assign $3\xive1_pri$next[7:0]$2506 \xive1_pri - assign $3\xive2_pri$next[7:0]$2507 \xive2_pri - assign $3\xive3_pri$next[7:0]$2508 \xive3_pri - assign $3\xive4_pri$next[7:0]$2509 \xive4_pri - assign $3\xive5_pri$next[7:0]$2510 \xive5_pri - assign $3\xive6_pri$next[7:0]$2511 \xive6_pri - assign $3\xive7_pri$next[7:0]$2512 \xive7_pri - assign $3\xive8_pri$next[7:0]$2513 \xive8_pri - assign $3\xive9_pri$next[7:0]$2514 \xive9_pri - assign $3\xive14_pri$next[7:0]$2504 \be_in [7:0] + assign $3\xive15_pri$next[7:0]$14532 \xive15_pri + assign $3\xive1_pri$next[7:0]$14533 \xive1_pri + assign $3\xive2_pri$next[7:0]$14534 \xive2_pri + assign $3\xive3_pri$next[7:0]$14535 \xive3_pri + assign $3\xive4_pri$next[7:0]$14536 \xive4_pri + assign $3\xive5_pri$next[7:0]$14537 \xive5_pri + assign $3\xive6_pri$next[7:0]$14538 \xive6_pri + assign $3\xive7_pri$next[7:0]$14539 \xive7_pri + assign $3\xive8_pri$next[7:0]$14540 \xive8_pri + assign $3\xive9_pri$next[7:0]$14541 \xive9_pri + assign $3\xive14_pri$next[7:0]$14531 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'---- - assign $3\xive0_pri$next[7:0]$2499 \xive0_pri - assign $3\xive10_pri$next[7:0]$2500 \xive10_pri - assign $3\xive11_pri$next[7:0]$2501 \xive11_pri - assign $3\xive12_pri$next[7:0]$2502 \xive12_pri - assign $3\xive13_pri$next[7:0]$2503 \xive13_pri - assign $3\xive14_pri$next[7:0]$2504 \xive14_pri + assign $3\xive0_pri$next[7:0]$14526 \xive0_pri + assign $3\xive10_pri$next[7:0]$14527 \xive10_pri + assign $3\xive11_pri$next[7:0]$14528 \xive11_pri + assign $3\xive12_pri$next[7:0]$14529 \xive12_pri + assign $3\xive13_pri$next[7:0]$14530 \xive13_pri + assign $3\xive14_pri$next[7:0]$14531 \xive14_pri assign { } { } - assign $3\xive1_pri$next[7:0]$2506 \xive1_pri - assign $3\xive2_pri$next[7:0]$2507 \xive2_pri - assign $3\xive3_pri$next[7:0]$2508 \xive3_pri - assign $3\xive4_pri$next[7:0]$2509 \xive4_pri - assign $3\xive5_pri$next[7:0]$2510 \xive5_pri - assign $3\xive6_pri$next[7:0]$2511 \xive6_pri - assign $3\xive7_pri$next[7:0]$2512 \xive7_pri - assign $3\xive8_pri$next[7:0]$2513 \xive8_pri - assign $3\xive9_pri$next[7:0]$2514 \xive9_pri - assign $3\xive15_pri$next[7:0]$2505 \be_in [7:0] + assign $3\xive1_pri$next[7:0]$14533 \xive1_pri + assign $3\xive2_pri$next[7:0]$14534 \xive2_pri + assign $3\xive3_pri$next[7:0]$14535 \xive3_pri + assign $3\xive4_pri$next[7:0]$14536 \xive4_pri + assign $3\xive5_pri$next[7:0]$14537 \xive5_pri + assign $3\xive6_pri$next[7:0]$14538 \xive6_pri + assign $3\xive7_pri$next[7:0]$14539 \xive7_pri + assign $3\xive8_pri$next[7:0]$14540 \xive8_pri + assign $3\xive9_pri$next[7:0]$14541 \xive9_pri + assign $3\xive15_pri$next[7:0]$14532 \be_in [7:0] case - assign $3\xive0_pri$next[7:0]$2499 \xive0_pri - assign $3\xive10_pri$next[7:0]$2500 \xive10_pri - assign $3\xive11_pri$next[7:0]$2501 \xive11_pri - assign $3\xive12_pri$next[7:0]$2502 \xive12_pri - assign $3\xive13_pri$next[7:0]$2503 \xive13_pri - assign $3\xive14_pri$next[7:0]$2504 \xive14_pri - assign $3\xive15_pri$next[7:0]$2505 \xive15_pri - assign $3\xive1_pri$next[7:0]$2506 \xive1_pri - assign $3\xive2_pri$next[7:0]$2507 \xive2_pri - assign $3\xive3_pri$next[7:0]$2508 \xive3_pri - assign $3\xive4_pri$next[7:0]$2509 \xive4_pri - assign $3\xive5_pri$next[7:0]$2510 \xive5_pri - assign $3\xive6_pri$next[7:0]$2511 \xive6_pri - assign $3\xive7_pri$next[7:0]$2512 \xive7_pri - assign $3\xive8_pri$next[7:0]$2513 \xive8_pri - assign $3\xive9_pri$next[7:0]$2514 \xive9_pri + assign $3\xive0_pri$next[7:0]$14526 \xive0_pri + assign $3\xive10_pri$next[7:0]$14527 \xive10_pri + assign $3\xive11_pri$next[7:0]$14528 \xive11_pri + assign $3\xive12_pri$next[7:0]$14529 \xive12_pri + assign $3\xive13_pri$next[7:0]$14530 \xive13_pri + assign $3\xive14_pri$next[7:0]$14531 \xive14_pri + assign $3\xive15_pri$next[7:0]$14532 \xive15_pri + assign $3\xive1_pri$next[7:0]$14533 \xive1_pri + assign $3\xive2_pri$next[7:0]$14534 \xive2_pri + assign $3\xive3_pri$next[7:0]$14535 \xive3_pri + assign $3\xive4_pri$next[7:0]$14536 \xive4_pri + assign $3\xive5_pri$next[7:0]$14537 \xive5_pri + assign $3\xive6_pri$next[7:0]$14538 \xive6_pri + assign $3\xive7_pri$next[7:0]$14539 \xive7_pri + assign $3\xive8_pri$next[7:0]$14540 \xive8_pri + assign $3\xive9_pri$next[7:0]$14541 \xive9_pri end case - assign $2\xive0_pri$next[7:0]$2483 \xive0_pri - assign $2\xive10_pri$next[7:0]$2484 \xive10_pri - assign $2\xive11_pri$next[7:0]$2485 \xive11_pri - assign $2\xive12_pri$next[7:0]$2486 \xive12_pri - assign $2\xive13_pri$next[7:0]$2487 \xive13_pri - assign $2\xive14_pri$next[7:0]$2488 \xive14_pri - assign $2\xive15_pri$next[7:0]$2489 \xive15_pri - assign $2\xive1_pri$next[7:0]$2490 \xive1_pri - assign $2\xive2_pri$next[7:0]$2491 \xive2_pri - assign $2\xive3_pri$next[7:0]$2492 \xive3_pri - assign $2\xive4_pri$next[7:0]$2493 \xive4_pri - assign $2\xive5_pri$next[7:0]$2494 \xive5_pri - assign $2\xive6_pri$next[7:0]$2495 \xive6_pri - assign $2\xive7_pri$next[7:0]$2496 \xive7_pri - assign $2\xive8_pri$next[7:0]$2497 \xive8_pri - assign $2\xive9_pri$next[7:0]$2498 \xive9_pri - end - case - assign $1\xive0_pri$next[7:0]$2467 \xive0_pri - assign $1\xive10_pri$next[7:0]$2468 \xive10_pri - assign $1\xive11_pri$next[7:0]$2469 \xive11_pri - assign $1\xive12_pri$next[7:0]$2470 \xive12_pri - assign $1\xive13_pri$next[7:0]$2471 \xive13_pri - assign $1\xive14_pri$next[7:0]$2472 \xive14_pri - assign $1\xive15_pri$next[7:0]$2473 \xive15_pri - assign $1\xive1_pri$next[7:0]$2474 \xive1_pri - assign $1\xive2_pri$next[7:0]$2475 \xive2_pri - assign $1\xive3_pri$next[7:0]$2476 \xive3_pri - assign $1\xive4_pri$next[7:0]$2477 \xive4_pri - assign $1\xive5_pri$next[7:0]$2478 \xive5_pri - assign $1\xive6_pri$next[7:0]$2479 \xive6_pri - assign $1\xive7_pri$next[7:0]$2480 \xive7_pri - assign $1\xive8_pri$next[7:0]$2481 \xive8_pri - assign $1\xive9_pri$next[7:0]$2482 \xive9_pri + assign $2\xive0_pri$next[7:0]$14510 \xive0_pri + assign $2\xive10_pri$next[7:0]$14511 \xive10_pri + assign $2\xive11_pri$next[7:0]$14512 \xive11_pri + assign $2\xive12_pri$next[7:0]$14513 \xive12_pri + assign $2\xive13_pri$next[7:0]$14514 \xive13_pri + assign $2\xive14_pri$next[7:0]$14515 \xive14_pri + assign $2\xive15_pri$next[7:0]$14516 \xive15_pri + assign $2\xive1_pri$next[7:0]$14517 \xive1_pri + assign $2\xive2_pri$next[7:0]$14518 \xive2_pri + assign $2\xive3_pri$next[7:0]$14519 \xive3_pri + assign $2\xive4_pri$next[7:0]$14520 \xive4_pri + assign $2\xive5_pri$next[7:0]$14521 \xive5_pri + assign $2\xive6_pri$next[7:0]$14522 \xive6_pri + assign $2\xive7_pri$next[7:0]$14523 \xive7_pri + assign $2\xive8_pri$next[7:0]$14524 \xive8_pri + assign $2\xive9_pri$next[7:0]$14525 \xive9_pri + end + case + assign $1\xive0_pri$next[7:0]$14494 \xive0_pri + assign $1\xive10_pri$next[7:0]$14495 \xive10_pri + assign $1\xive11_pri$next[7:0]$14496 \xive11_pri + assign $1\xive12_pri$next[7:0]$14497 \xive12_pri + assign $1\xive13_pri$next[7:0]$14498 \xive13_pri + assign $1\xive14_pri$next[7:0]$14499 \xive14_pri + assign $1\xive15_pri$next[7:0]$14500 \xive15_pri + assign $1\xive1_pri$next[7:0]$14501 \xive1_pri + assign $1\xive2_pri$next[7:0]$14502 \xive2_pri + assign $1\xive3_pri$next[7:0]$14503 \xive3_pri + assign $1\xive4_pri$next[7:0]$14504 \xive4_pri + assign $1\xive5_pri$next[7:0]$14505 \xive5_pri + assign $1\xive6_pri$next[7:0]$14506 \xive6_pri + assign $1\xive7_pri$next[7:0]$14507 \xive7_pri + assign $1\xive8_pri$next[7:0]$14508 \xive8_pri + assign $1\xive9_pri$next[7:0]$14509 \xive9_pri end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -150173,66 +400744,66 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $4\xive0_pri$next[7:0]$2515 8'11111111 - assign $4\xive1_pri$next[7:0]$2522 8'11111111 - assign $4\xive2_pri$next[7:0]$2523 8'11111111 - assign $4\xive3_pri$next[7:0]$2524 8'11111111 - assign $4\xive4_pri$next[7:0]$2525 8'11111111 - assign $4\xive5_pri$next[7:0]$2526 8'11111111 - assign $4\xive6_pri$next[7:0]$2527 8'11111111 - assign $4\xive7_pri$next[7:0]$2528 8'11111111 - assign $4\xive8_pri$next[7:0]$2529 8'11111111 - assign $4\xive9_pri$next[7:0]$2530 8'11111111 - assign $4\xive10_pri$next[7:0]$2516 8'11111111 - assign $4\xive11_pri$next[7:0]$2517 8'11111111 - assign $4\xive12_pri$next[7:0]$2518 8'11111111 - assign $4\xive13_pri$next[7:0]$2519 8'11111111 - assign $4\xive14_pri$next[7:0]$2520 8'11111111 - assign $4\xive15_pri$next[7:0]$2521 8'11111111 + assign $4\xive0_pri$next[7:0]$14542 8'11111111 + assign $4\xive1_pri$next[7:0]$14549 8'11111111 + assign $4\xive2_pri$next[7:0]$14550 8'11111111 + assign $4\xive3_pri$next[7:0]$14551 8'11111111 + assign $4\xive4_pri$next[7:0]$14552 8'11111111 + assign $4\xive5_pri$next[7:0]$14553 8'11111111 + assign $4\xive6_pri$next[7:0]$14554 8'11111111 + assign $4\xive7_pri$next[7:0]$14555 8'11111111 + assign $4\xive8_pri$next[7:0]$14556 8'11111111 + assign $4\xive9_pri$next[7:0]$14557 8'11111111 + assign $4\xive10_pri$next[7:0]$14543 8'11111111 + assign $4\xive11_pri$next[7:0]$14544 8'11111111 + assign $4\xive12_pri$next[7:0]$14545 8'11111111 + assign $4\xive13_pri$next[7:0]$14546 8'11111111 + assign $4\xive14_pri$next[7:0]$14547 8'11111111 + assign $4\xive15_pri$next[7:0]$14548 8'11111111 case - assign $4\xive0_pri$next[7:0]$2515 $1\xive0_pri$next[7:0]$2467 - assign $4\xive10_pri$next[7:0]$2516 $1\xive10_pri$next[7:0]$2468 - assign $4\xive11_pri$next[7:0]$2517 $1\xive11_pri$next[7:0]$2469 - assign $4\xive12_pri$next[7:0]$2518 $1\xive12_pri$next[7:0]$2470 - assign $4\xive13_pri$next[7:0]$2519 $1\xive13_pri$next[7:0]$2471 - assign $4\xive14_pri$next[7:0]$2520 $1\xive14_pri$next[7:0]$2472 - assign $4\xive15_pri$next[7:0]$2521 $1\xive15_pri$next[7:0]$2473 - assign $4\xive1_pri$next[7:0]$2522 $1\xive1_pri$next[7:0]$2474 - assign $4\xive2_pri$next[7:0]$2523 $1\xive2_pri$next[7:0]$2475 - assign $4\xive3_pri$next[7:0]$2524 $1\xive3_pri$next[7:0]$2476 - assign $4\xive4_pri$next[7:0]$2525 $1\xive4_pri$next[7:0]$2477 - assign $4\xive5_pri$next[7:0]$2526 $1\xive5_pri$next[7:0]$2478 - assign $4\xive6_pri$next[7:0]$2527 $1\xive6_pri$next[7:0]$2479 - assign $4\xive7_pri$next[7:0]$2528 $1\xive7_pri$next[7:0]$2480 - assign $4\xive8_pri$next[7:0]$2529 $1\xive8_pri$next[7:0]$2481 - assign $4\xive9_pri$next[7:0]$2530 $1\xive9_pri$next[7:0]$2482 + assign $4\xive0_pri$next[7:0]$14542 $1\xive0_pri$next[7:0]$14494 + assign $4\xive10_pri$next[7:0]$14543 $1\xive10_pri$next[7:0]$14495 + assign $4\xive11_pri$next[7:0]$14544 $1\xive11_pri$next[7:0]$14496 + assign $4\xive12_pri$next[7:0]$14545 $1\xive12_pri$next[7:0]$14497 + assign $4\xive13_pri$next[7:0]$14546 $1\xive13_pri$next[7:0]$14498 + assign $4\xive14_pri$next[7:0]$14547 $1\xive14_pri$next[7:0]$14499 + assign $4\xive15_pri$next[7:0]$14548 $1\xive15_pri$next[7:0]$14500 + assign $4\xive1_pri$next[7:0]$14549 $1\xive1_pri$next[7:0]$14501 + assign $4\xive2_pri$next[7:0]$14550 $1\xive2_pri$next[7:0]$14502 + assign $4\xive3_pri$next[7:0]$14551 $1\xive3_pri$next[7:0]$14503 + assign $4\xive4_pri$next[7:0]$14552 $1\xive4_pri$next[7:0]$14504 + assign $4\xive5_pri$next[7:0]$14553 $1\xive5_pri$next[7:0]$14505 + assign $4\xive6_pri$next[7:0]$14554 $1\xive6_pri$next[7:0]$14506 + assign $4\xive7_pri$next[7:0]$14555 $1\xive7_pri$next[7:0]$14507 + assign $4\xive8_pri$next[7:0]$14556 $1\xive8_pri$next[7:0]$14508 + assign $4\xive9_pri$next[7:0]$14557 $1\xive9_pri$next[7:0]$14509 end sync always - update \xive0_pri$next $0\xive0_pri$next[7:0]$2451 - update \xive10_pri$next $0\xive10_pri$next[7:0]$2452 - update \xive11_pri$next $0\xive11_pri$next[7:0]$2453 - update \xive12_pri$next $0\xive12_pri$next[7:0]$2454 - update \xive13_pri$next $0\xive13_pri$next[7:0]$2455 - update \xive14_pri$next $0\xive14_pri$next[7:0]$2456 - update \xive15_pri$next $0\xive15_pri$next[7:0]$2457 - update \xive1_pri$next $0\xive1_pri$next[7:0]$2458 - update \xive2_pri$next $0\xive2_pri$next[7:0]$2459 - update \xive3_pri$next $0\xive3_pri$next[7:0]$2460 - update \xive4_pri$next $0\xive4_pri$next[7:0]$2461 - update \xive5_pri$next $0\xive5_pri$next[7:0]$2462 - update \xive6_pri$next $0\xive6_pri$next[7:0]$2463 - update \xive7_pri$next $0\xive7_pri$next[7:0]$2464 - update \xive8_pri$next $0\xive8_pri$next[7:0]$2465 - update \xive9_pri$next $0\xive9_pri$next[7:0]$2466 + update \xive0_pri$next $0\xive0_pri$next[7:0]$14478 + update \xive10_pri$next $0\xive10_pri$next[7:0]$14479 + update \xive11_pri$next $0\xive11_pri$next[7:0]$14480 + update \xive12_pri$next $0\xive12_pri$next[7:0]$14481 + update \xive13_pri$next $0\xive13_pri$next[7:0]$14482 + update \xive14_pri$next $0\xive14_pri$next[7:0]$14483 + update \xive15_pri$next $0\xive15_pri$next[7:0]$14484 + update \xive1_pri$next $0\xive1_pri$next[7:0]$14485 + update \xive2_pri$next $0\xive2_pri$next[7:0]$14486 + update \xive3_pri$next $0\xive3_pri$next[7:0]$14487 + update \xive4_pri$next $0\xive4_pri$next[7:0]$14488 + update \xive5_pri$next $0\xive5_pri$next[7:0]$14489 + update \xive6_pri$next $0\xive6_pri$next[7:0]$14490 + update \xive7_pri$next $0\xive7_pri$next[7:0]$14491 + update \xive8_pri$next $0\xive8_pri$next[7:0]$14492 + update \xive9_pri$next $0\xive9_pri$next[7:0]$14493 end - attribute \src "libresoc.v:53463.3-53472.6" - process $proc$libresoc.v:53463$2531 + attribute \src "libresoc.v:189881.3-189890.6" + process $proc$libresoc.v:189881$14558 assign { } { } assign { } { } assign $0\cur_pri0[7:0] $1\cur_pri0[7:0] - attribute \src "libresoc.v:53464.5-53464.29" + attribute \src "libresoc.v:189882.5-189882.29" switch \initial - attribute \src "libresoc.v:53464.9-53464.17" + attribute \src "libresoc.v:189882.9-189882.17" case 1'1 case end @@ -150248,14 +400819,14 @@ module \xics_ics sync always update \cur_pri0 $0\cur_pri0[7:0] end - attribute \src "libresoc.v:53473.3-53482.6" - process $proc$libresoc.v:53473$2532 + attribute \src "libresoc.v:189891.3-189900.6" + process $proc$libresoc.v:189891$14559 assign { } { } assign { } { } assign $0\cur_idx0[3:0] $1\cur_idx0[3:0] - attribute \src "libresoc.v:53474.5-53474.29" + attribute \src "libresoc.v:189892.5-189892.29" switch \initial - attribute \src "libresoc.v:53474.9-53474.17" + attribute \src "libresoc.v:189892.9-189892.17" case 1'1 case end @@ -150271,14 +400842,14 @@ module \xics_ics sync always update \cur_idx0 $0\cur_idx0[3:0] end - attribute \src "libresoc.v:53483.3-53492.6" - process $proc$libresoc.v:53483$2533 + attribute \src "libresoc.v:189901.3-189910.6" + process $proc$libresoc.v:189901$14560 assign { } { } assign { } { } assign $0\cur_pri1[7:0] $1\cur_pri1[7:0] - attribute \src "libresoc.v:53484.5-53484.29" + attribute \src "libresoc.v:189902.5-189902.29" switch \initial - attribute \src "libresoc.v:53484.9-53484.17" + attribute \src "libresoc.v:189902.9-189902.17" case 1'1 case end @@ -150294,14 +400865,14 @@ module \xics_ics sync always update \cur_pri1 $0\cur_pri1[7:0] end - attribute \src "libresoc.v:53493.3-53502.6" - process $proc$libresoc.v:53493$2534 + attribute \src "libresoc.v:189911.3-189920.6" + process $proc$libresoc.v:189911$14561 assign { } { } assign { } { } assign $0\cur_idx1[3:0] $1\cur_idx1[3:0] - attribute \src "libresoc.v:53494.5-53494.29" + attribute \src "libresoc.v:189912.5-189912.29" switch \initial - attribute \src "libresoc.v:53494.9-53494.17" + attribute \src "libresoc.v:189912.9-189912.17" case 1'1 case end @@ -150317,14 +400888,14 @@ module \xics_ics sync always update \cur_idx1 $0\cur_idx1[3:0] end - attribute \src "libresoc.v:53503.3-53512.6" - process $proc$libresoc.v:53503$2535 + attribute \src "libresoc.v:189921.3-189930.6" + process $proc$libresoc.v:189921$14562 assign { } { } assign { } { } assign $0\cur_pri2[7:0] $1\cur_pri2[7:0] - attribute \src "libresoc.v:53504.5-53504.29" + attribute \src "libresoc.v:189922.5-189922.29" switch \initial - attribute \src "libresoc.v:53504.9-53504.17" + attribute \src "libresoc.v:189922.9-189922.17" case 1'1 case end @@ -150340,14 +400911,14 @@ module \xics_ics sync always update \cur_pri2 $0\cur_pri2[7:0] end - attribute \src "libresoc.v:53513.3-53522.6" - process $proc$libresoc.v:53513$2536 + attribute \src "libresoc.v:189931.3-189940.6" + process $proc$libresoc.v:189931$14563 assign { } { } assign { } { } assign $0\cur_idx2[3:0] $1\cur_idx2[3:0] - attribute \src "libresoc.v:53514.5-53514.29" + attribute \src "libresoc.v:189932.5-189932.29" switch \initial - attribute \src "libresoc.v:53514.9-53514.17" + attribute \src "libresoc.v:189932.9-189932.17" case 1'1 case end @@ -150363,14 +400934,14 @@ module \xics_ics sync always update \cur_idx2 $0\cur_idx2[3:0] end - attribute \src "libresoc.v:53523.3-53532.6" - process $proc$libresoc.v:53523$2537 + attribute \src "libresoc.v:189941.3-189950.6" + process $proc$libresoc.v:189941$14564 assign { } { } assign { } { } assign $0\cur_pri3[7:0] $1\cur_pri3[7:0] - attribute \src "libresoc.v:53524.5-53524.29" + attribute \src "libresoc.v:189942.5-189942.29" switch \initial - attribute \src "libresoc.v:53524.9-53524.17" + attribute \src "libresoc.v:189942.9-189942.17" case 1'1 case end @@ -150386,14 +400957,14 @@ module \xics_ics sync always update \cur_pri3 $0\cur_pri3[7:0] end - attribute \src "libresoc.v:53533.3-53542.6" - process $proc$libresoc.v:53533$2538 + attribute \src "libresoc.v:189951.3-189960.6" + process $proc$libresoc.v:189951$14565 assign { } { } assign { } { } assign $0\cur_idx3[3:0] $1\cur_idx3[3:0] - attribute \src "libresoc.v:53534.5-53534.29" + attribute \src "libresoc.v:189952.5-189952.29" switch \initial - attribute \src "libresoc.v:53534.9-53534.17" + attribute \src "libresoc.v:189952.9-189952.17" case 1'1 case end @@ -150409,14 +400980,14 @@ module \xics_ics sync always update \cur_idx3 $0\cur_idx3[3:0] end - attribute \src "libresoc.v:53543.3-53552.6" - process $proc$libresoc.v:53543$2539 + attribute \src "libresoc.v:189961.3-189970.6" + process $proc$libresoc.v:189961$14566 assign { } { } assign { } { } assign $0\cur_pri4[7:0] $1\cur_pri4[7:0] - attribute \src "libresoc.v:53544.5-53544.29" + attribute \src "libresoc.v:189962.5-189962.29" switch \initial - attribute \src "libresoc.v:53544.9-53544.17" + attribute \src "libresoc.v:189962.9-189962.17" case 1'1 case end @@ -150432,14 +401003,14 @@ module \xics_ics sync always update \cur_pri4 $0\cur_pri4[7:0] end - attribute \src "libresoc.v:53553.3-53561.6" - process $proc$libresoc.v:53553$2540 + attribute \src "libresoc.v:189971.3-189979.6" + process $proc$libresoc.v:189971$14567 assign { } { } assign { } { } - assign $0\int_level_l$next[15:0]$2541 $1\int_level_l$next[15:0]$2542 - attribute \src "libresoc.v:53554.5-53554.29" + assign $0\int_level_l$next[15:0]$14568 $1\int_level_l$next[15:0]$14569 + attribute \src "libresoc.v:189972.5-189972.29" switch \initial - attribute \src "libresoc.v:53554.9-53554.17" + attribute \src "libresoc.v:189972.9-189972.17" case 1'1 case end @@ -150448,21 +401019,21 @@ module \xics_ics attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\int_level_l$next[15:0]$2542 16'0000000000000000 + assign $1\int_level_l$next[15:0]$14569 16'0000000000000000 case - assign $1\int_level_l$next[15:0]$2542 \int_level_i + assign $1\int_level_l$next[15:0]$14569 \int_level_i end sync always - update \int_level_l$next $0\int_level_l$next[15:0]$2541 + update \int_level_l$next $0\int_level_l$next[15:0]$14568 end - attribute \src "libresoc.v:53562.3-53571.6" - process $proc$libresoc.v:53562$2543 + attribute \src "libresoc.v:189980.3-189989.6" + process $proc$libresoc.v:189980$14570 assign { } { } assign { } { } assign $0\cur_idx4[3:0] $1\cur_idx4[3:0] - attribute \src "libresoc.v:53563.5-53563.29" + attribute \src "libresoc.v:189981.5-189981.29" switch \initial - attribute \src "libresoc.v:53563.9-53563.17" + attribute \src "libresoc.v:189981.9-189981.17" case 1'1 case end @@ -150478,14 +401049,14 @@ module \xics_ics sync always update \cur_idx4 $0\cur_idx4[3:0] end - attribute \src "libresoc.v:53572.3-53581.6" - process $proc$libresoc.v:53572$2544 + attribute \src "libresoc.v:189990.3-189999.6" + process $proc$libresoc.v:189990$14571 assign { } { } assign { } { } assign $0\cur_pri5[7:0] $1\cur_pri5[7:0] - attribute \src "libresoc.v:53573.5-53573.29" + attribute \src "libresoc.v:189991.5-189991.29" switch \initial - attribute \src "libresoc.v:53573.9-53573.17" + attribute \src "libresoc.v:189991.9-189991.17" case 1'1 case end @@ -150501,14 +401072,14 @@ module \xics_ics sync always update \cur_pri5 $0\cur_pri5[7:0] end - attribute \src "libresoc.v:53582.3-53591.6" - process $proc$libresoc.v:53582$2545 + attribute \src "libresoc.v:190000.3-190009.6" + process $proc$libresoc.v:190000$14572 assign { } { } assign { } { } assign $0\cur_idx5[3:0] $1\cur_idx5[3:0] - attribute \src "libresoc.v:53583.5-53583.29" + attribute \src "libresoc.v:190001.5-190001.29" switch \initial - attribute \src "libresoc.v:53583.9-53583.17" + attribute \src "libresoc.v:190001.9-190001.17" case 1'1 case end @@ -150524,14 +401095,14 @@ module \xics_ics sync always update \cur_idx5 $0\cur_idx5[3:0] end - attribute \src "libresoc.v:53592.3-53601.6" - process $proc$libresoc.v:53592$2546 + attribute \src "libresoc.v:190010.3-190019.6" + process $proc$libresoc.v:190010$14573 assign { } { } assign { } { } assign $0\cur_pri6[7:0] $1\cur_pri6[7:0] - attribute \src "libresoc.v:53593.5-53593.29" + attribute \src "libresoc.v:190011.5-190011.29" switch \initial - attribute \src "libresoc.v:53593.9-53593.17" + attribute \src "libresoc.v:190011.9-190011.17" case 1'1 case end @@ -150547,14 +401118,14 @@ module \xics_ics sync always update \cur_pri6 $0\cur_pri6[7:0] end - attribute \src "libresoc.v:53602.3-53611.6" - process $proc$libresoc.v:53602$2547 + attribute \src "libresoc.v:190020.3-190029.6" + process $proc$libresoc.v:190020$14574 assign { } { } assign { } { } assign $0\cur_idx6[3:0] $1\cur_idx6[3:0] - attribute \src "libresoc.v:53603.5-53603.29" + attribute \src "libresoc.v:190021.5-190021.29" switch \initial - attribute \src "libresoc.v:53603.9-53603.17" + attribute \src "libresoc.v:190021.9-190021.17" case 1'1 case end @@ -150570,14 +401141,14 @@ module \xics_ics sync always update \cur_idx6 $0\cur_idx6[3:0] end - attribute \src "libresoc.v:53612.3-53621.6" - process $proc$libresoc.v:53612$2548 + attribute \src "libresoc.v:190030.3-190039.6" + process $proc$libresoc.v:190030$14575 assign { } { } assign { } { } assign $0\cur_pri7[7:0] $1\cur_pri7[7:0] - attribute \src "libresoc.v:53613.5-53613.29" + attribute \src "libresoc.v:190031.5-190031.29" switch \initial - attribute \src "libresoc.v:53613.9-53613.17" + attribute \src "libresoc.v:190031.9-190031.17" case 1'1 case end @@ -150593,14 +401164,14 @@ module \xics_ics sync always update \cur_pri7 $0\cur_pri7[7:0] end - attribute \src "libresoc.v:53622.3-53631.6" - process $proc$libresoc.v:53622$2549 + attribute \src "libresoc.v:190040.3-190049.6" + process $proc$libresoc.v:190040$14576 assign { } { } assign { } { } assign $0\cur_idx7[3:0] $1\cur_idx7[3:0] - attribute \src "libresoc.v:53623.5-53623.29" + attribute \src "libresoc.v:190041.5-190041.29" switch \initial - attribute \src "libresoc.v:53623.9-53623.17" + attribute \src "libresoc.v:190041.9-190041.17" case 1'1 case end @@ -150616,14 +401187,14 @@ module \xics_ics sync always update \cur_idx7 $0\cur_idx7[3:0] end - attribute \src "libresoc.v:53632.3-53641.6" - process $proc$libresoc.v:53632$2550 + attribute \src "libresoc.v:190050.3-190059.6" + process $proc$libresoc.v:190050$14577 assign { } { } assign { } { } assign $0\cur_pri8[7:0] $1\cur_pri8[7:0] - attribute \src "libresoc.v:53633.5-53633.29" + attribute \src "libresoc.v:190051.5-190051.29" switch \initial - attribute \src "libresoc.v:53633.9-53633.17" + attribute \src "libresoc.v:190051.9-190051.17" case 1'1 case end @@ -150639,14 +401210,14 @@ module \xics_ics sync always update \cur_pri8 $0\cur_pri8[7:0] end - attribute \src "libresoc.v:53642.3-53651.6" - process $proc$libresoc.v:53642$2551 + attribute \src "libresoc.v:190060.3-190069.6" + process $proc$libresoc.v:190060$14578 assign { } { } assign { } { } assign $0\cur_idx8[3:0] $1\cur_idx8[3:0] - attribute \src "libresoc.v:53643.5-53643.29" + attribute \src "libresoc.v:190061.5-190061.29" switch \initial - attribute \src "libresoc.v:53643.9-53643.17" + attribute \src "libresoc.v:190061.9-190061.17" case 1'1 case end @@ -150662,14 +401233,14 @@ module \xics_ics sync always update \cur_idx8 $0\cur_idx8[3:0] end - attribute \src "libresoc.v:53652.3-53661.6" - process $proc$libresoc.v:53652$2552 + attribute \src "libresoc.v:190070.3-190079.6" + process $proc$libresoc.v:190070$14579 assign { } { } assign { } { } assign $0\cur_pri9[7:0] $1\cur_pri9[7:0] - attribute \src "libresoc.v:53653.5-53653.29" + attribute \src "libresoc.v:190071.5-190071.29" switch \initial - attribute \src "libresoc.v:53653.9-53653.17" + attribute \src "libresoc.v:190071.9-190071.17" case 1'1 case end @@ -150685,14 +401256,14 @@ module \xics_ics sync always update \cur_pri9 $0\cur_pri9[7:0] end - attribute \src "libresoc.v:53662.3-53671.6" - process $proc$libresoc.v:53662$2553 + attribute \src "libresoc.v:190080.3-190089.6" + process $proc$libresoc.v:190080$14580 assign { } { } assign { } { } assign $0\cur_idx9[3:0] $1\cur_idx9[3:0] - attribute \src "libresoc.v:53663.5-53663.29" + attribute \src "libresoc.v:190081.5-190081.29" switch \initial - attribute \src "libresoc.v:53663.9-53663.17" + attribute \src "libresoc.v:190081.9-190081.17" case 1'1 case end @@ -150708,14 +401279,14 @@ module \xics_ics sync always update \cur_idx9 $0\cur_idx9[3:0] end - attribute \src "libresoc.v:53672.3-53681.6" - process $proc$libresoc.v:53672$2554 + attribute \src "libresoc.v:190090.3-190099.6" + process $proc$libresoc.v:190090$14581 assign { } { } assign { } { } assign $0\cur_pri10[7:0] $1\cur_pri10[7:0] - attribute \src "libresoc.v:53673.5-53673.29" + attribute \src "libresoc.v:190091.5-190091.29" switch \initial - attribute \src "libresoc.v:53673.9-53673.17" + attribute \src "libresoc.v:190091.9-190091.17" case 1'1 case end @@ -150731,14 +401302,14 @@ module \xics_ics sync always update \cur_pri10 $0\cur_pri10[7:0] end - attribute \src "libresoc.v:53682.3-53691.6" - process $proc$libresoc.v:53682$2555 + attribute \src "libresoc.v:190100.3-190109.6" + process $proc$libresoc.v:190100$14582 assign { } { } assign { } { } assign $0\cur_idx10[3:0] $1\cur_idx10[3:0] - attribute \src "libresoc.v:53683.5-53683.29" + attribute \src "libresoc.v:190101.5-190101.29" switch \initial - attribute \src "libresoc.v:53683.9-53683.17" + attribute \src "libresoc.v:190101.9-190101.17" case 1'1 case end @@ -150754,14 +401325,14 @@ module \xics_ics sync always update \cur_idx10 $0\cur_idx10[3:0] end - attribute \src "libresoc.v:53692.3-53701.6" - process $proc$libresoc.v:53692$2556 + attribute \src "libresoc.v:190110.3-190119.6" + process $proc$libresoc.v:190110$14583 assign { } { } assign { } { } assign $0\cur_pri11[7:0] $1\cur_pri11[7:0] - attribute \src "libresoc.v:53693.5-53693.29" + attribute \src "libresoc.v:190111.5-190111.29" switch \initial - attribute \src "libresoc.v:53693.9-53693.17" + attribute \src "libresoc.v:190111.9-190111.17" case 1'1 case end @@ -150777,14 +401348,14 @@ module \xics_ics sync always update \cur_pri11 $0\cur_pri11[7:0] end - attribute \src "libresoc.v:53702.3-53711.6" - process $proc$libresoc.v:53702$2557 + attribute \src "libresoc.v:190120.3-190129.6" + process $proc$libresoc.v:190120$14584 assign { } { } assign { } { } assign $0\cur_idx11[3:0] $1\cur_idx11[3:0] - attribute \src "libresoc.v:53703.5-53703.29" + attribute \src "libresoc.v:190121.5-190121.29" switch \initial - attribute \src "libresoc.v:53703.9-53703.17" + attribute \src "libresoc.v:190121.9-190121.17" case 1'1 case end @@ -150800,14 +401371,14 @@ module \xics_ics sync always update \cur_idx11 $0\cur_idx11[3:0] end - attribute \src "libresoc.v:53712.3-53721.6" - process $proc$libresoc.v:53712$2558 + attribute \src "libresoc.v:190130.3-190139.6" + process $proc$libresoc.v:190130$14585 assign { } { } assign { } { } assign $0\cur_pri12[7:0] $1\cur_pri12[7:0] - attribute \src "libresoc.v:53713.5-53713.29" + attribute \src "libresoc.v:190131.5-190131.29" switch \initial - attribute \src "libresoc.v:53713.9-53713.17" + attribute \src "libresoc.v:190131.9-190131.17" case 1'1 case end @@ -150823,14 +401394,14 @@ module \xics_ics sync always update \cur_pri12 $0\cur_pri12[7:0] end - attribute \src "libresoc.v:53722.3-53731.6" - process $proc$libresoc.v:53722$2559 + attribute \src "libresoc.v:190140.3-190149.6" + process $proc$libresoc.v:190140$14586 assign { } { } assign { } { } assign $0\cur_idx12[3:0] $1\cur_idx12[3:0] - attribute \src "libresoc.v:53723.5-53723.29" + attribute \src "libresoc.v:190141.5-190141.29" switch \initial - attribute \src "libresoc.v:53723.9-53723.17" + attribute \src "libresoc.v:190141.9-190141.17" case 1'1 case end @@ -150846,14 +401417,14 @@ module \xics_ics sync always update \cur_idx12 $0\cur_idx12[3:0] end - attribute \src "libresoc.v:53732.3-53741.6" - process $proc$libresoc.v:53732$2560 + attribute \src "libresoc.v:190150.3-190159.6" + process $proc$libresoc.v:190150$14587 assign { } { } assign { } { } assign $0\cur_pri13[7:0] $1\cur_pri13[7:0] - attribute \src "libresoc.v:53733.5-53733.29" + attribute \src "libresoc.v:190151.5-190151.29" switch \initial - attribute \src "libresoc.v:53733.9-53733.17" + attribute \src "libresoc.v:190151.9-190151.17" case 1'1 case end @@ -150869,14 +401440,14 @@ module \xics_ics sync always update \cur_pri13 $0\cur_pri13[7:0] end - attribute \src "libresoc.v:53742.3-53751.6" - process $proc$libresoc.v:53742$2561 + attribute \src "libresoc.v:190160.3-190169.6" + process $proc$libresoc.v:190160$14588 assign { } { } assign { } { } assign $0\cur_idx13[3:0] $1\cur_idx13[3:0] - attribute \src "libresoc.v:53743.5-53743.29" + attribute \src "libresoc.v:190161.5-190161.29" switch \initial - attribute \src "libresoc.v:53743.9-53743.17" + attribute \src "libresoc.v:190161.9-190161.17" case 1'1 case end @@ -150892,14 +401463,14 @@ module \xics_ics sync always update \cur_idx13 $0\cur_idx13[3:0] end - attribute \src "libresoc.v:53752.3-53761.6" - process $proc$libresoc.v:53752$2562 + attribute \src "libresoc.v:190170.3-190179.6" + process $proc$libresoc.v:190170$14589 assign { } { } assign { } { } assign $0\cur_pri14[7:0] $1\cur_pri14[7:0] - attribute \src "libresoc.v:53753.5-53753.29" + attribute \src "libresoc.v:190171.5-190171.29" switch \initial - attribute \src "libresoc.v:53753.9-53753.17" + attribute \src "libresoc.v:190171.9-190171.17" case 1'1 case end @@ -150915,14 +401486,14 @@ module \xics_ics sync always update \cur_pri14 $0\cur_pri14[7:0] end - attribute \src "libresoc.v:53762.3-53811.6" - process $proc$libresoc.v:53762$2563 + attribute \src "libresoc.v:190180.3-190229.6" + process $proc$libresoc.v:190180$14590 assign { } { } assign { } { } assign $0\be_out[31:0] $1\be_out[31:0] - attribute \src "libresoc.v:53763.5-53763.29" + attribute \src "libresoc.v:190181.5-190181.29" switch \initial - attribute \src "libresoc.v:53763.9-53763.17" + attribute \src "libresoc.v:190181.9-190181.17" case 1'1 case end @@ -151015,14 +401586,14 @@ module \xics_ics sync always update \be_out $0\be_out[31:0] end - attribute \src "libresoc.v:53812.3-53821.6" - process $proc$libresoc.v:53812$2564 + attribute \src "libresoc.v:190230.3-190239.6" + process $proc$libresoc.v:190230$14591 assign { } { } assign { } { } assign $0\cur_idx14[3:0] $1\cur_idx14[3:0] - attribute \src "libresoc.v:53813.5-53813.29" + attribute \src "libresoc.v:190231.5-190231.29" switch \initial - attribute \src "libresoc.v:53813.9-53813.17" + attribute \src "libresoc.v:190231.9-190231.17" case 1'1 case end @@ -151038,14 +401609,14 @@ module \xics_ics sync always update \cur_idx14 $0\cur_idx14[3:0] end - attribute \src "libresoc.v:53822.3-53831.6" - process $proc$libresoc.v:53822$2565 + attribute \src "libresoc.v:190240.3-190249.6" + process $proc$libresoc.v:190240$14592 assign { } { } assign { } { } assign $0\cur_pri15[7:0] $1\cur_pri15[7:0] - attribute \src "libresoc.v:53823.5-53823.29" + attribute \src "libresoc.v:190241.5-190241.29" switch \initial - attribute \src "libresoc.v:53823.9-53823.17" + attribute \src "libresoc.v:190241.9-190241.17" case 1'1 case end @@ -151061,14 +401632,14 @@ module \xics_ics sync always update \cur_pri15 $0\cur_pri15[7:0] end - attribute \src "libresoc.v:53832.3-53841.6" - process $proc$libresoc.v:53832$2566 + attribute \src "libresoc.v:190250.3-190259.6" + process $proc$libresoc.v:190250$14593 assign { } { } assign { } { } assign $0\cur_idx15[3:0] $1\cur_idx15[3:0] - attribute \src "libresoc.v:53833.5-53833.29" + attribute \src "libresoc.v:190251.5-190251.29" switch \initial - attribute \src "libresoc.v:53833.9-53833.17" + attribute \src "libresoc.v:190251.9-190251.17" case 1'1 case end @@ -151084,14 +401655,14 @@ module \xics_ics sync always update \cur_idx15 $0\cur_idx15[3:0] end - attribute \src "libresoc.v:53842.3-53851.6" - process $proc$libresoc.v:53842$2567 + attribute \src "libresoc.v:190260.3-190269.6" + process $proc$libresoc.v:190260$14594 assign { } { } assign { } { } assign $0\ibit[0:0] $1\ibit[0:0] - attribute \src "libresoc.v:53843.5-53843.29" + attribute \src "libresoc.v:190261.5-190261.29" switch \initial - attribute \src "libresoc.v:53843.9-53843.17" + attribute \src "libresoc.v:190261.9-190261.17" case 1'1 case end @@ -151107,14 +401678,14 @@ module \xics_ics sync always update \ibit $0\ibit[0:0] end - attribute \src "libresoc.v:53852.3-53860.6" - process $proc$libresoc.v:53852$2568 + attribute \src "libresoc.v:190270.3-190278.6" + process $proc$libresoc.v:190270$14595 assign { } { } assign { } { } - assign $0\ics_wb__dat_r$next[31:0]$2569 $1\ics_wb__dat_r$next[31:0]$2570 - attribute \src "libresoc.v:53853.5-53853.29" + assign $0\ics_wb__dat_r$next[31:0]$14596 $1\ics_wb__dat_r$next[31:0]$14597 + attribute \src "libresoc.v:190271.5-190271.29" switch \initial - attribute \src "libresoc.v:53853.9-53853.17" + attribute \src "libresoc.v:190271.9-190271.17" case 1'1 case end @@ -151123,21 +401694,21 @@ module \xics_ics attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ics_wb__dat_r$next[31:0]$2570 0 + assign $1\ics_wb__dat_r$next[31:0]$14597 0 case - assign $1\ics_wb__dat_r$next[31:0]$2570 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + assign $1\ics_wb__dat_r$next[31:0]$14597 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } end sync always - update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$2569 + update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$14596 end - attribute \src "libresoc.v:53861.3-53869.6" - process $proc$libresoc.v:53861$2571 + attribute \src "libresoc.v:190279.3-190287.6" + process $proc$libresoc.v:190279$14598 assign { } { } assign { } { } - assign $0\ics_wb__ack$next[0:0]$2572 $1\ics_wb__ack$next[0:0]$2573 - attribute \src "libresoc.v:53862.5-53862.29" + assign $0\ics_wb__ack$next[0:0]$14599 $1\ics_wb__ack$next[0:0]$14600 + attribute \src "libresoc.v:190280.5-190280.29" switch \initial - attribute \src "libresoc.v:53862.9-53862.17" + attribute \src "libresoc.v:190280.9-190280.17" case 1'1 case end @@ -151146,116 +401717,116 @@ module \xics_ics attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ics_wb__ack$next[0:0]$2573 1'0 - case - assign $1\ics_wb__ack$next[0:0]$2573 \wb_valid - end - sync always - update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$2572 - end - connect \$7 $ternary$libresoc.v:53232$2326_Y - connect \$99 $lt$libresoc.v:53233$2327_Y - connect \$101 $and$libresoc.v:53234$2328_Y - connect \$103 $lt$libresoc.v:53235$2329_Y - connect \$105 $and$libresoc.v:53236$2330_Y - connect \$107 $lt$libresoc.v:53237$2331_Y - connect \$109 $and$libresoc.v:53238$2332_Y - connect \$111 $lt$libresoc.v:53239$2333_Y - connect \$113 $and$libresoc.v:53240$2334_Y - connect \$115 $lt$libresoc.v:53241$2335_Y - connect \$117 $and$libresoc.v:53242$2336_Y - connect \$119 $lt$libresoc.v:53243$2337_Y - connect \$121 $and$libresoc.v:53244$2338_Y - connect \$123 $lt$libresoc.v:53245$2339_Y - connect \$125 $and$libresoc.v:53246$2340_Y - connect \$127 $lt$libresoc.v:53247$2341_Y - connect \$12 $eq$libresoc.v:53248$2342_Y - connect \$129 $and$libresoc.v:53249$2343_Y - connect \$131 $lt$libresoc.v:53250$2344_Y - connect \$133 $and$libresoc.v:53251$2345_Y - connect \$135 $lt$libresoc.v:53252$2346_Y - connect \$137 $and$libresoc.v:53253$2347_Y - connect \$11 $ternary$libresoc.v:53254$2348_Y - connect \$139 $lt$libresoc.v:53255$2349_Y - connect \$141 $and$libresoc.v:53256$2350_Y - connect \$143 $lt$libresoc.v:53257$2351_Y - connect \$145 $and$libresoc.v:53258$2352_Y - connect \$147 $lt$libresoc.v:53259$2353_Y - connect \$149 $and$libresoc.v:53260$2354_Y - connect \$151 $lt$libresoc.v:53261$2355_Y - connect \$153 $and$libresoc.v:53262$2356_Y - connect \$155 $lt$libresoc.v:53263$2357_Y - connect \$157 $and$libresoc.v:53264$2358_Y - connect \$159 $lt$libresoc.v:53265$2359_Y - connect \$161 $and$libresoc.v:53266$2360_Y - connect \$163 $lt$libresoc.v:53267$2361_Y - connect \$165 $and$libresoc.v:53268$2362_Y - connect \$167 $lt$libresoc.v:53269$2363_Y - connect \$16 $eq$libresoc.v:53270$2364_Y - connect \$169 $and$libresoc.v:53271$2365_Y - connect \$171 $lt$libresoc.v:53272$2366_Y - connect \$173 $and$libresoc.v:53273$2367_Y - connect \$175 $lt$libresoc.v:53274$2368_Y - connect \$177 $and$libresoc.v:53275$2369_Y - connect \$15 $ternary$libresoc.v:53276$2370_Y - connect \$179 $lt$libresoc.v:53277$2371_Y - connect \$181 $and$libresoc.v:53278$2372_Y - connect \$183 $lt$libresoc.v:53279$2373_Y - connect \$185 $and$libresoc.v:53280$2374_Y - connect \$187 $lt$libresoc.v:53281$2375_Y - connect \$189 $and$libresoc.v:53282$2376_Y - connect \$191 $lt$libresoc.v:53283$2377_Y - connect \$193 $and$libresoc.v:53284$2378_Y - connect \$195 $lt$libresoc.v:53285$2379_Y - connect \$197 $and$libresoc.v:53286$2380_Y - connect \$1 $eq$libresoc.v:53287$2381_Y - connect \$199 $lt$libresoc.v:53288$2382_Y - connect \$201 $and$libresoc.v:53289$2383_Y - connect \$204 $eq$libresoc.v:53290$2384_Y - connect \$203 $ternary$libresoc.v:53291$2385_Y - connect \$20 $eq$libresoc.v:53292$2386_Y - connect \$19 $ternary$libresoc.v:53293$2387_Y - connect \$24 $eq$libresoc.v:53294$2388_Y - connect \$23 $ternary$libresoc.v:53295$2389_Y - connect \$28 $eq$libresoc.v:53296$2390_Y - connect \$27 $ternary$libresoc.v:53297$2391_Y - connect \$32 $eq$libresoc.v:53298$2392_Y - connect \$31 $ternary$libresoc.v:53299$2393_Y - connect \$36 $eq$libresoc.v:53300$2394_Y - connect \$35 $ternary$libresoc.v:53301$2395_Y - connect \$3 $eq$libresoc.v:53302$2396_Y - connect \$40 $eq$libresoc.v:53303$2397_Y - connect \$39 $ternary$libresoc.v:53304$2398_Y - connect \$44 $eq$libresoc.v:53305$2399_Y - connect \$43 $ternary$libresoc.v:53306$2400_Y - connect \$48 $eq$libresoc.v:53307$2401_Y - connect \$47 $ternary$libresoc.v:53308$2402_Y - connect \$52 $eq$libresoc.v:53309$2403_Y - connect \$51 $ternary$libresoc.v:53310$2404_Y - connect \$56 $eq$libresoc.v:53311$2405_Y - connect \$55 $ternary$libresoc.v:53312$2406_Y - connect \$5 $and$libresoc.v:53313$2407_Y - connect \$60 $eq$libresoc.v:53314$2408_Y - connect \$59 $ternary$libresoc.v:53315$2409_Y - connect \$64 $eq$libresoc.v:53316$2410_Y - connect \$63 $ternary$libresoc.v:53317$2411_Y - connect \$68 $eq$libresoc.v:53318$2412_Y - connect \$67 $ternary$libresoc.v:53319$2413_Y - connect \$71 $shr$libresoc.v:53320$2414_Y [0] - connect \$73 $and$libresoc.v:53321$2415_Y - connect \$75 $lt$libresoc.v:53322$2416_Y - connect \$77 $and$libresoc.v:53323$2417_Y - connect \$79 $lt$libresoc.v:53324$2418_Y - connect \$81 $and$libresoc.v:53325$2419_Y - connect \$83 $lt$libresoc.v:53326$2420_Y - connect \$85 $and$libresoc.v:53327$2421_Y - connect \$87 $lt$libresoc.v:53328$2422_Y - connect \$8 $eq$libresoc.v:53329$2423_Y - connect \$89 $and$libresoc.v:53330$2424_Y - connect \$91 $lt$libresoc.v:53331$2425_Y - connect \$93 $and$libresoc.v:53332$2426_Y - connect \$95 $lt$libresoc.v:53333$2427_Y - connect \$97 $and$libresoc.v:53334$2428_Y + assign $1\ics_wb__ack$next[0:0]$14600 1'0 + case + assign $1\ics_wb__ack$next[0:0]$14600 \wb_valid + end + sync always + update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$14599 + end + connect \$7 $ternary$libresoc.v:189650$14353_Y + connect \$99 $lt$libresoc.v:189651$14354_Y + connect \$101 $and$libresoc.v:189652$14355_Y + connect \$103 $lt$libresoc.v:189653$14356_Y + connect \$105 $and$libresoc.v:189654$14357_Y + connect \$107 $lt$libresoc.v:189655$14358_Y + connect \$109 $and$libresoc.v:189656$14359_Y + connect \$111 $lt$libresoc.v:189657$14360_Y + connect \$113 $and$libresoc.v:189658$14361_Y + connect \$115 $lt$libresoc.v:189659$14362_Y + connect \$117 $and$libresoc.v:189660$14363_Y + connect \$119 $lt$libresoc.v:189661$14364_Y + connect \$121 $and$libresoc.v:189662$14365_Y + connect \$123 $lt$libresoc.v:189663$14366_Y + connect \$125 $and$libresoc.v:189664$14367_Y + connect \$127 $lt$libresoc.v:189665$14368_Y + connect \$12 $eq$libresoc.v:189666$14369_Y + connect \$129 $and$libresoc.v:189667$14370_Y + connect \$131 $lt$libresoc.v:189668$14371_Y + connect \$133 $and$libresoc.v:189669$14372_Y + connect \$135 $lt$libresoc.v:189670$14373_Y + connect \$137 $and$libresoc.v:189671$14374_Y + connect \$11 $ternary$libresoc.v:189672$14375_Y + connect \$139 $lt$libresoc.v:189673$14376_Y + connect \$141 $and$libresoc.v:189674$14377_Y + connect \$143 $lt$libresoc.v:189675$14378_Y + connect \$145 $and$libresoc.v:189676$14379_Y + connect \$147 $lt$libresoc.v:189677$14380_Y + connect \$149 $and$libresoc.v:189678$14381_Y + connect \$151 $lt$libresoc.v:189679$14382_Y + connect \$153 $and$libresoc.v:189680$14383_Y + connect \$155 $lt$libresoc.v:189681$14384_Y + connect \$157 $and$libresoc.v:189682$14385_Y + connect \$159 $lt$libresoc.v:189683$14386_Y + connect \$161 $and$libresoc.v:189684$14387_Y + connect \$163 $lt$libresoc.v:189685$14388_Y + connect \$165 $and$libresoc.v:189686$14389_Y + connect \$167 $lt$libresoc.v:189687$14390_Y + connect \$16 $eq$libresoc.v:189688$14391_Y + connect \$169 $and$libresoc.v:189689$14392_Y + connect \$171 $lt$libresoc.v:189690$14393_Y + connect \$173 $and$libresoc.v:189691$14394_Y + connect \$175 $lt$libresoc.v:189692$14395_Y + connect \$177 $and$libresoc.v:189693$14396_Y + connect \$15 $ternary$libresoc.v:189694$14397_Y + connect \$179 $lt$libresoc.v:189695$14398_Y + connect \$181 $and$libresoc.v:189696$14399_Y + connect \$183 $lt$libresoc.v:189697$14400_Y + connect \$185 $and$libresoc.v:189698$14401_Y + connect \$187 $lt$libresoc.v:189699$14402_Y + connect \$189 $and$libresoc.v:189700$14403_Y + connect \$191 $lt$libresoc.v:189701$14404_Y + connect \$193 $and$libresoc.v:189702$14405_Y + connect \$195 $lt$libresoc.v:189703$14406_Y + connect \$197 $and$libresoc.v:189704$14407_Y + connect \$1 $eq$libresoc.v:189705$14408_Y + connect \$199 $lt$libresoc.v:189706$14409_Y + connect \$201 $and$libresoc.v:189707$14410_Y + connect \$204 $eq$libresoc.v:189708$14411_Y + connect \$203 $ternary$libresoc.v:189709$14412_Y + connect \$20 $eq$libresoc.v:189710$14413_Y + connect \$19 $ternary$libresoc.v:189711$14414_Y + connect \$24 $eq$libresoc.v:189712$14415_Y + connect \$23 $ternary$libresoc.v:189713$14416_Y + connect \$28 $eq$libresoc.v:189714$14417_Y + connect \$27 $ternary$libresoc.v:189715$14418_Y + connect \$32 $eq$libresoc.v:189716$14419_Y + connect \$31 $ternary$libresoc.v:189717$14420_Y + connect \$36 $eq$libresoc.v:189718$14421_Y + connect \$35 $ternary$libresoc.v:189719$14422_Y + connect \$3 $eq$libresoc.v:189720$14423_Y + connect \$40 $eq$libresoc.v:189721$14424_Y + connect \$39 $ternary$libresoc.v:189722$14425_Y + connect \$44 $eq$libresoc.v:189723$14426_Y + connect \$43 $ternary$libresoc.v:189724$14427_Y + connect \$48 $eq$libresoc.v:189725$14428_Y + connect \$47 $ternary$libresoc.v:189726$14429_Y + connect \$52 $eq$libresoc.v:189727$14430_Y + connect \$51 $ternary$libresoc.v:189728$14431_Y + connect \$56 $eq$libresoc.v:189729$14432_Y + connect \$55 $ternary$libresoc.v:189730$14433_Y + connect \$5 $and$libresoc.v:189731$14434_Y + connect \$60 $eq$libresoc.v:189732$14435_Y + connect \$59 $ternary$libresoc.v:189733$14436_Y + connect \$64 $eq$libresoc.v:189734$14437_Y + connect \$63 $ternary$libresoc.v:189735$14438_Y + connect \$68 $eq$libresoc.v:189736$14439_Y + connect \$67 $ternary$libresoc.v:189737$14440_Y + connect \$71 $shr$libresoc.v:189738$14441_Y [0] + connect \$73 $and$libresoc.v:189739$14442_Y + connect \$75 $lt$libresoc.v:189740$14443_Y + connect \$77 $and$libresoc.v:189741$14444_Y + connect \$79 $lt$libresoc.v:189742$14445_Y + connect \$81 $and$libresoc.v:189743$14446_Y + connect \$83 $lt$libresoc.v:189744$14447_Y + connect \$85 $and$libresoc.v:189745$14448_Y + connect \$87 $lt$libresoc.v:189746$14449_Y + connect \$8 $eq$libresoc.v:189747$14450_Y + connect \$89 $and$libresoc.v:189748$14451_Y + connect \$91 $lt$libresoc.v:189749$14452_Y + connect \$93 $and$libresoc.v:189750$14453_Y + connect \$95 $lt$libresoc.v:189751$14454_Y + connect \$97 $and$libresoc.v:189752$14455_Y connect \icp_r_pri \$203 connect \icp_r_src \cur_idx15 connect \max_idx 4'0000